diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/hdl/scalp_zynqps_wrapper.vhd b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/hdl/scalp_zynqps_wrapper.vhd
deleted file mode 100644
index f77bbbfc318a1335d945495657dc9dc51b32450f..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/hdl/scalp_zynqps_wrapper.vhd
+++ /dev/null
@@ -1,109 +0,0 @@
---Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
---Date : Mon Sep 7 11:52:31 2020
---Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
---Command : generate_target scalp_zynqps_wrapper.bd
---Design : scalp_zynqps_wrapper
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity scalp_zynqps_wrapper is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC;
- FclkClk0xCO : out STD_LOGIC;
- FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
- Spi1MOSIxSO : out STD_LOGIC;
- Spi1SSxSO : out STD_LOGIC;
- Spi1SclkxCO : out STD_LOGIC;
- Usb0VBusPwrFaultxSI : in STD_LOGIC
- );
-end scalp_zynqps_wrapper;
-
-architecture STRUCTURE of scalp_zynqps_wrapper is
- component scalp_zynqps is
- port (
- FclkClk0xCO : out STD_LOGIC;
- FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
- Spi1MOSIxSO : out STD_LOGIC;
- Spi1SSxSO : out STD_LOGIC;
- Spi1SclkxCO : out STD_LOGIC;
- Usb0VBusPwrFaultxSI : in STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC;
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- DDR_cas_n : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 )
- );
- end component scalp_zynqps;
-begin
-scalp_zynqps_i: component scalp_zynqps
- port map (
- DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
- DDR_cas_n => DDR_cas_n,
- DDR_ck_n => DDR_ck_n,
- DDR_ck_p => DDR_ck_p,
- DDR_cke => DDR_cke,
- DDR_cs_n => DDR_cs_n,
- DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
- DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
- DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_odt => DDR_odt,
- DDR_ras_n => DDR_ras_n,
- DDR_reset_n => DDR_reset_n,
- DDR_we_n => DDR_we_n,
- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
- FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
- FclkClk0xCO => FclkClk0xCO,
- FclkReset0xRO(0) => FclkReset0xRO(0),
- Spi1MOSIxSO => Spi1MOSIxSO,
- Spi1SSxSO => Spi1SSxSO,
- Spi1SclkxCO => Spi1SclkxCO,
- Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI
- );
-end STRUCTURE;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/hw_handoff/scalp_zynqps_bd.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/hw_handoff/scalp_zynqps_bd.tcl
deleted file mode 100644
index 4858b24787977c9944746cae1d77aa35505163ff..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/hw_handoff/scalp_zynqps_bd.tcl
+++ /dev/null
@@ -1,646 +0,0 @@
-
-################################################################
-# This is a generated script based on design: scalp_zynqps
-#
-# Though there are limitations about the generated script,
-# the main purpose of this utility is to make learning
-# IP Integrator Tcl commands easier.
-################################################################
-
-namespace eval _tcl {
-proc get_script_folder {} {
- set script_path [file normalize [info script]]
- set script_folder [file dirname $script_path]
- return $script_folder
-}
-}
-variable script_folder
-set script_folder [_tcl::get_script_folder]
-
-################################################################
-# Check if script is running in correct Vivado version.
-################################################################
-set scripts_vivado_version 2019.2
-set current_vivado_version [version -short]
-
-if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
- puts ""
- catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
-
- return 1
-}
-
-################################################################
-# START
-################################################################
-
-# To test this script, run the following commands from Vivado Tcl console:
-# source scalp_zynqps_script.tcl
-
-# If there is no project opened, this script will create a
-# project, but make sure you do not have an existing project
-# <./myproj/project_1.xpr> in the current working folder.
-
-set list_projs [get_projects -quiet]
-if { $list_projs eq "" } {
- create_project project_1 myproj -part xc7z015clg485-2
-}
-
-
-# CHANGE DESIGN NAME HERE
-variable design_name
-set design_name scalp_zynqps
-
-# This script was generated for a remote BD. To create a non-remote design,
-# change the variable <run_remote_bd_flow> to <0>.
-
-set run_remote_bd_flow 1
-if { $run_remote_bd_flow == 1 } {
- # Set the reference directory for source file relative paths (by default
- # the value is script directory path)
- set origin_dir .
-
- # Use origin directory path location variable, if specified in the tcl shell
- if { [info exists ::origin_dir_loc] } {
- set origin_dir $::origin_dir_loc
- }
-
- set str_bd_folder [file normalize ${origin_dir}]
- set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
-
- # Check if remote design exists on disk
- if { [file exists $str_bd_filepath ] == 1 } {
- catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
- common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
- common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project."
-
- return 1
- }
-
- # Check if design exists in memory
- set list_existing_designs [get_bd_designs -quiet $design_name]
- if { $list_existing_designs ne "" } {
- catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
-
- common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
-
- return 1
- }
-
- # Check if design exists on disk within project
- set list_existing_designs [get_files -quiet */${design_name}.bd]
- if { $list_existing_designs ne "" } {
- catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location:
- $list_existing_designs"}
- catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
-
- common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
-
- return 1
- }
-
- # Now can create the remote BD
- # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
- create_bd_design -dir $str_bd_folder $design_name
-} else {
-
- # Create regular design
- if { [catch {create_bd_design $design_name} errmsg] } {
- common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable <design_name>."
-
- return 1
- }
-}
-
-current_bd_design $design_name
-
-##################################################################
-# DESIGN PROCs
-##################################################################
-
-
-
-# Procedure to create entire design; Provide argument to make
-# procedure reusable. If parentCell is "", will use root.
-proc create_root_design { parentCell } {
-
- variable script_folder
- variable design_name
-
- if { $parentCell eq "" } {
- set parentCell [get_bd_cells /]
- }
-
- # Get object for parentCell
- set parentObj [get_bd_cells $parentCell]
- if { $parentObj == "" } {
- catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
- return
- }
-
- # Make sure parentObj is hier blk
- set parentType [get_property TYPE $parentObj]
- if { $parentType ne "hier" } {
- catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
- return
- }
-
- # Save current instance; Restore later
- set oldCurInst [current_bd_instance .]
-
- # Set parent object as current
- current_bd_instance $parentObj
-
-
- # Create interface ports
- set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
-
- set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
-
-
- # Create ports
- set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
- set_property -dict [ list \
- CONFIG.FREQ_HZ {125000000} \
- ] $FclkClk0xCO
- set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
- set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
- set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
- set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
- set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
-
- # Create instance: gnd_constant, and set properties
- set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
- set_property -dict [ list \
- CONFIG.CONST_VAL {0} \
- ] $gnd_constant
-
- # Create instance: processing_system7_0, and set properties
- set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
- set_property -dict [ list \
- CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {750.000000} \
- CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {97.222221} \
- CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.204082} \
- CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {194.444443} \
- CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {134.615387} \
- CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {97.222221} \
- CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
- CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {159.090912} \
- CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
- CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {97.222221} \
- CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {750} \
- CONFIG.PCW_ARMPLL_CTRL_FBDIV {30} \
- CONFIG.PCW_CAN1_CAN1_IO {MIO 52 .. 53} \
- CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
- CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {18} \
- CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_CAN_PERIPHERAL_VALID {1} \
- CONFIG.PCW_CLK0_FREQ {125000000} \
- CONFIG.PCW_CLK1_FREQ {10000000} \
- CONFIG.PCW_CLK2_FREQ {10000000} \
- CONFIG.PCW_CLK3_FREQ {10000000} \
- CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1500.000} \
- CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {49} \
- CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \
- CONFIG.PCW_DDRPLL_CTRL_FBDIV {20} \
- CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1000.000} \
- CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
- CONFIG.PCW_DDR_RAM_HIGHADDR {0x0FFFFFFF} \
- CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
- CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
- CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {14} \
- CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
- CONFIG.PCW_ENET0_RESET_ENABLE {0} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_ENET1_RESET_ENABLE {0} \
- CONFIG.PCW_ENET_RESET_ENABLE {1} \
- CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_EN_CAN1 {1} \
- CONFIG.PCW_EN_EMIO_CAN1 {0} \
- CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
- CONFIG.PCW_EN_EMIO_ENET0 {0} \
- CONFIG.PCW_EN_EMIO_I2C0 {0} \
- CONFIG.PCW_EN_EMIO_SDIO1 {0} \
- CONFIG.PCW_EN_EMIO_SPI0 {0} \
- CONFIG.PCW_EN_EMIO_SPI1 {1} \
- CONFIG.PCW_EN_EMIO_UART0 {0} \
- CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
- CONFIG.PCW_EN_ENET0 {1} \
- CONFIG.PCW_EN_GPIO {1} \
- CONFIG.PCW_EN_I2C0 {1} \
- CONFIG.PCW_EN_QSPI {1} \
- CONFIG.PCW_EN_SDIO1 {1} \
- CONFIG.PCW_EN_SPI0 {1} \
- CONFIG.PCW_EN_SPI1 {1} \
- CONFIG.PCW_EN_UART0 {1} \
- CONFIG.PCW_EN_UART1 {1} \
- CONFIG.PCW_EN_USB0 {1} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {7} \
- CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
- CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {125} \
- CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
- CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
- CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
- CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
- CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
- CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
- CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
- CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_I2C0_RESET_ENABLE {0} \
- CONFIG.PCW_I2C1_RESET_ENABLE {0} \
- CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {125.000000} \
- CONFIG.PCW_I2C_RESET_ENABLE {1} \
- CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
- CONFIG.PCW_IOPLL_CTRL_FBDIV {35} \
- CONFIG.PCW_IO_IO_PLL_FREQMHZ {1750.000} \
- CONFIG.PCW_MIO_0_DIRECTION {inout} \
- CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_0_PULLUP {enabled} \
- CONFIG.PCW_MIO_0_SLEW {slow} \
- CONFIG.PCW_MIO_10_DIRECTION {inout} \
- CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_10_PULLUP {enabled} \
- CONFIG.PCW_MIO_10_SLEW {slow} \
- CONFIG.PCW_MIO_11_DIRECTION {inout} \
- CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_11_PULLUP {enabled} \
- CONFIG.PCW_MIO_11_SLEW {slow} \
- CONFIG.PCW_MIO_12_DIRECTION {inout} \
- CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_12_PULLUP {enabled} \
- CONFIG.PCW_MIO_12_SLEW {slow} \
- CONFIG.PCW_MIO_13_DIRECTION {inout} \
- CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_13_PULLUP {enabled} \
- CONFIG.PCW_MIO_13_SLEW {slow} \
- CONFIG.PCW_MIO_14_DIRECTION {inout} \
- CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_14_PULLUP {enabled} \
- CONFIG.PCW_MIO_14_SLEW {slow} \
- CONFIG.PCW_MIO_15_DIRECTION {inout} \
- CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_15_PULLUP {enabled} \
- CONFIG.PCW_MIO_15_SLEW {slow} \
- CONFIG.PCW_MIO_16_DIRECTION {out} \
- CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_16_PULLUP {enabled} \
- CONFIG.PCW_MIO_16_SLEW {slow} \
- CONFIG.PCW_MIO_17_DIRECTION {out} \
- CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_17_PULLUP {enabled} \
- CONFIG.PCW_MIO_17_SLEW {slow} \
- CONFIG.PCW_MIO_18_DIRECTION {out} \
- CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_18_PULLUP {enabled} \
- CONFIG.PCW_MIO_18_SLEW {slow} \
- CONFIG.PCW_MIO_19_DIRECTION {out} \
- CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_19_PULLUP {enabled} \
- CONFIG.PCW_MIO_19_SLEW {slow} \
- CONFIG.PCW_MIO_1_DIRECTION {out} \
- CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_1_PULLUP {enabled} \
- CONFIG.PCW_MIO_1_SLEW {slow} \
- CONFIG.PCW_MIO_20_DIRECTION {out} \
- CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_20_PULLUP {enabled} \
- CONFIG.PCW_MIO_20_SLEW {slow} \
- CONFIG.PCW_MIO_21_DIRECTION {out} \
- CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_21_PULLUP {enabled} \
- CONFIG.PCW_MIO_21_SLEW {slow} \
- CONFIG.PCW_MIO_22_DIRECTION {in} \
- CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_22_PULLUP {enabled} \
- CONFIG.PCW_MIO_22_SLEW {slow} \
- CONFIG.PCW_MIO_23_DIRECTION {in} \
- CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_23_PULLUP {enabled} \
- CONFIG.PCW_MIO_23_SLEW {slow} \
- CONFIG.PCW_MIO_24_DIRECTION {in} \
- CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_24_PULLUP {enabled} \
- CONFIG.PCW_MIO_24_SLEW {slow} \
- CONFIG.PCW_MIO_25_DIRECTION {in} \
- CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_25_PULLUP {enabled} \
- CONFIG.PCW_MIO_25_SLEW {slow} \
- CONFIG.PCW_MIO_26_DIRECTION {in} \
- CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_26_PULLUP {enabled} \
- CONFIG.PCW_MIO_26_SLEW {slow} \
- CONFIG.PCW_MIO_27_DIRECTION {in} \
- CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_27_PULLUP {enabled} \
- CONFIG.PCW_MIO_27_SLEW {slow} \
- CONFIG.PCW_MIO_28_DIRECTION {inout} \
- CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_28_PULLUP {enabled} \
- CONFIG.PCW_MIO_28_SLEW {slow} \
- CONFIG.PCW_MIO_29_DIRECTION {in} \
- CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_29_PULLUP {enabled} \
- CONFIG.PCW_MIO_29_SLEW {slow} \
- CONFIG.PCW_MIO_2_DIRECTION {inout} \
- CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_2_PULLUP {disabled} \
- CONFIG.PCW_MIO_2_SLEW {slow} \
- CONFIG.PCW_MIO_30_DIRECTION {out} \
- CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_30_PULLUP {enabled} \
- CONFIG.PCW_MIO_30_SLEW {slow} \
- CONFIG.PCW_MIO_31_DIRECTION {in} \
- CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_31_PULLUP {enabled} \
- CONFIG.PCW_MIO_31_SLEW {slow} \
- CONFIG.PCW_MIO_32_DIRECTION {inout} \
- CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_32_PULLUP {enabled} \
- CONFIG.PCW_MIO_32_SLEW {slow} \
- CONFIG.PCW_MIO_33_DIRECTION {inout} \
- CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_33_PULLUP {enabled} \
- CONFIG.PCW_MIO_33_SLEW {slow} \
- CONFIG.PCW_MIO_34_DIRECTION {inout} \
- CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_34_PULLUP {enabled} \
- CONFIG.PCW_MIO_34_SLEW {slow} \
- CONFIG.PCW_MIO_35_DIRECTION {inout} \
- CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_35_PULLUP {enabled} \
- CONFIG.PCW_MIO_35_SLEW {slow} \
- CONFIG.PCW_MIO_36_DIRECTION {in} \
- CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_36_PULLUP {enabled} \
- CONFIG.PCW_MIO_36_SLEW {slow} \
- CONFIG.PCW_MIO_37_DIRECTION {inout} \
- CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_37_PULLUP {enabled} \
- CONFIG.PCW_MIO_37_SLEW {slow} \
- CONFIG.PCW_MIO_38_DIRECTION {inout} \
- CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_38_PULLUP {enabled} \
- CONFIG.PCW_MIO_38_SLEW {slow} \
- CONFIG.PCW_MIO_39_DIRECTION {inout} \
- CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_39_PULLUP {enabled} \
- CONFIG.PCW_MIO_39_SLEW {slow} \
- CONFIG.PCW_MIO_3_DIRECTION {inout} \
- CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_3_PULLUP {disabled} \
- CONFIG.PCW_MIO_3_SLEW {slow} \
- CONFIG.PCW_MIO_40_DIRECTION {inout} \
- CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_40_PULLUP {enabled} \
- CONFIG.PCW_MIO_40_SLEW {slow} \
- CONFIG.PCW_MIO_41_DIRECTION {inout} \
- CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_41_PULLUP {enabled} \
- CONFIG.PCW_MIO_41_SLEW {slow} \
- CONFIG.PCW_MIO_42_DIRECTION {inout} \
- CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_42_PULLUP {enabled} \
- CONFIG.PCW_MIO_42_SLEW {slow} \
- CONFIG.PCW_MIO_43_DIRECTION {inout} \
- CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_43_PULLUP {enabled} \
- CONFIG.PCW_MIO_43_SLEW {slow} \
- CONFIG.PCW_MIO_44_DIRECTION {inout} \
- CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_44_PULLUP {enabled} \
- CONFIG.PCW_MIO_44_SLEW {slow} \
- CONFIG.PCW_MIO_45_DIRECTION {inout} \
- CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_45_PULLUP {enabled} \
- CONFIG.PCW_MIO_45_SLEW {slow} \
- CONFIG.PCW_MIO_46_DIRECTION {in} \
- CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_46_PULLUP {enabled} \
- CONFIG.PCW_MIO_46_SLEW {slow} \
- CONFIG.PCW_MIO_47_DIRECTION {out} \
- CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_47_PULLUP {enabled} \
- CONFIG.PCW_MIO_47_SLEW {slow} \
- CONFIG.PCW_MIO_48_DIRECTION {out} \
- CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_48_PULLUP {enabled} \
- CONFIG.PCW_MIO_48_SLEW {slow} \
- CONFIG.PCW_MIO_49_DIRECTION {in} \
- CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_49_PULLUP {enabled} \
- CONFIG.PCW_MIO_49_SLEW {slow} \
- CONFIG.PCW_MIO_4_DIRECTION {inout} \
- CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_4_PULLUP {disabled} \
- CONFIG.PCW_MIO_4_SLEW {slow} \
- CONFIG.PCW_MIO_50_DIRECTION {inout} \
- CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_50_PULLUP {enabled} \
- CONFIG.PCW_MIO_50_SLEW {slow} \
- CONFIG.PCW_MIO_51_DIRECTION {inout} \
- CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_51_PULLUP {enabled} \
- CONFIG.PCW_MIO_51_SLEW {slow} \
- CONFIG.PCW_MIO_52_DIRECTION {out} \
- CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_52_PULLUP {enabled} \
- CONFIG.PCW_MIO_52_SLEW {slow} \
- CONFIG.PCW_MIO_53_DIRECTION {in} \
- CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 2.5V} \
- CONFIG.PCW_MIO_53_PULLUP {enabled} \
- CONFIG.PCW_MIO_53_SLEW {slow} \
- CONFIG.PCW_MIO_5_DIRECTION {inout} \
- CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_5_PULLUP {disabled} \
- CONFIG.PCW_MIO_5_SLEW {slow} \
- CONFIG.PCW_MIO_6_DIRECTION {out} \
- CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_6_PULLUP {disabled} \
- CONFIG.PCW_MIO_6_SLEW {slow} \
- CONFIG.PCW_MIO_7_DIRECTION {out} \
- CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_7_PULLUP {disabled} \
- CONFIG.PCW_MIO_7_SLEW {slow} \
- CONFIG.PCW_MIO_8_DIRECTION {out} \
- CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_8_PULLUP {disabled} \
- CONFIG.PCW_MIO_8_SLEW {slow} \
- CONFIG.PCW_MIO_9_DIRECTION {in} \
- CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
- CONFIG.PCW_MIO_9_PULLUP {enabled} \
- CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#SPI 0#UART 0#UART 0#UART 1#UART 1#I2C 0#I2C 0#CAN 1#CAN 1} \
- CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx} \
- CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
- CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
- CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
- CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
- CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {9} \
- CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 2.5V} \
- CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
- CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
- CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
- CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
- CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {13} \
- CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {133} \
- CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
- CONFIG.PCW_SD1_GRP_CD_ENABLE {1} \
- CONFIG.PCW_SD1_GRP_CD_IO {MIO 9} \
- CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
- CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
- CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \
- CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {18} \
- CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
- CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
- CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \
- CONFIG.PCW_SPI0_GRP_SS0_IO {MIO 42} \
- CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
- CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
- CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_SPI0_SPI0_IO {MIO 40 .. 45} \
- CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \
- CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \
- CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \
- CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \
- CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \
- CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \
- CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_SPI1_SPI1_IO {EMIO} \
- CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {11} \
- CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
- CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
- CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
- CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_UART0_UART0_IO {MIO 46 .. 47} \
- CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
- CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
- CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {18} \
- CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
- CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
- CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {500.000000} \
- CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
- CONFIG.PCW_UIPARAM_DDR_BL {8} \
- CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
- CONFIG.PCW_UIPARAM_DDR_CL {7} \
- CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
- CONFIG.PCW_UIPARAM_DDR_CWL {6} \
- CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
- CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
- CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
- CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
- CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
- CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \
- CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
- CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
- CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
- CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
- CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
- CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
- CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
- CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
- CONFIG.PCW_USB0_RESET_ENABLE {0} \
- CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
- CONFIG.PCW_USB1_RESET_ENABLE {0} \
- CONFIG.PCW_USB_RESET_ENABLE {1} \
- CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
- ] $processing_system7_0
-
- # Create instance: util_vector_logic_0, and set properties
- set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
- set_property -dict [ list \
- CONFIG.C_OPERATION {or} \
- CONFIG.C_SIZE {1} \
- CONFIG.LOGO_FILE {data/sym_orgate.png} \
- ] $util_vector_logic_0
-
- # Create instance: util_vector_logic_1, and set properties
- set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
- set_property -dict [ list \
- CONFIG.C_OPERATION {not} \
- CONFIG.C_SIZE {1} \
- CONFIG.LOGO_FILE {data/sym_notgate.png} \
- ] $util_vector_logic_1
-
- # Create instance: vio_0, and set properties
- set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ]
- set_property -dict [ list \
- CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
- CONFIG.C_NUM_PROBE_IN {0} \
- ] $vio_0
-
- # Create interface connections
- connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
- connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
-
- # Create port connections
- connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
- connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins vio_0/clk]
- connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins util_vector_logic_1/Op1]
- connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
- connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
- connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
- connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
- connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
- connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
-
- # Create address segments
-
-
- # Restore current instance
- current_bd_instance $oldCurInst
-
- validate_bd_design
- save_bd_design
-}
-# End of create_root_design()
-
-
-##################################################################
-# MAIN FLOW
-##################################################################
-
-create_root_design ""
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xci
deleted file mode 100644
index adce14d017431b414e5a7a03eb810f279881ef78..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xci
+++ /dev/null
@@ -1,48 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>xci</spirit:library>
- <spirit:name>unknown</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>scalp_zynqps_gnd_constant_0</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">0</spirit:configurableElementValue>
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xml
deleted file mode 100644
index 14c8dcc88bd1f03fb9499888fed19324a5ff0fb1..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xml
+++ /dev/null
@@ -1,265 +0,0 @@
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.h
deleted file mode 100644
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v
deleted file mode 100644
index efcfe970834e2414e5c26606f7f23769378194aa..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v
+++ /dev/null
@@ -1,68 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 6
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_gnd_constant_0 (
- dout
-);
-
-output wire [0 : 0] dout;
-
- xlconstant_v1_1_6_xlconstant #(
- .CONST_WIDTH(1),
- .CONST_VAL('H0)
- ) inst (
- .dout(dout)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/xlconstant_v1_1_6.h
deleted file mode 100644
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v
deleted file mode 100644
index ddbbd68efd0e65adaab6be47a7dca6bafb26dcb0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 6
-
-(* X_CORE_INFO = "xlconstant_v1_1_6_xlconstant,Vivado 2019.2" *)
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_gnd_constant_0,xlconstant_v1_1_6_xlconstant,{}" *)
-(* CORE_GENERATION_INFO = "scalp_zynqps_gnd_constant_0,xlconstant_v1_1_6_xlconstant,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x0}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_gnd_constant_0 (
- dout
-);
-
-output wire [0 : 0] dout;
-
- xlconstant_v1_1_6_xlconstant #(
- .CONST_WIDTH(1),
- .CONST_VAL('H0)
- ) inst (
- .dout(dout)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
deleted file mode 100644
index 062c75278e7f0b5f51b9146f37e0fbe3699ec879..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v
+++ /dev/null
@@ -1,3935 +0,0 @@
-
-//-----------------------------------------------------------------------------
-// processing_system7
-// processor sub system wrapper
-//-----------------------------------------------------------------------------
-//
-// ************************************************************************
-// ** DISCLAIMER OF LIABILITY **
-// ** **
-// ** This file contains proprietary and confidential information of **
-// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-// ** from Xilinx, and may be used, copied and/or diSCLosed only **
-// ** pursuant to the terms of a valid license agreement with Xilinx. **
-// ** **
-// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-// ** does not warrant that functions included in the Materials will **
-// ** meet the requirements of Licensee, or that the operation of the **
-// ** Materials will be uninterrupted or error-free, or that defects **
-// ** in the Materials will be corrected. Furthermore, Xilinx does **
-// ** not warrant or make any representations regarding use, or the **
-// ** results of the use, of the Materials in terms of correctness, **
-// ** accuracy, reliability or otherwise. **
-// ** **
-// ** Xilinx products are not designed or intended to be fail-safe, **
-// ** or for use in any application requiring fail-safe performance, **
-// ** such as life-support or safety devices or systems, Class III **
-// ** medical devices, nuclear facilities, applications related to **
-// ** the deployment of airbags, or any other applications that could **
-// ** lead to death, personal injury or severe property or **
-// ** environmental damage (individually and collectively, "critical **
-// ** applications"). Customer assumes the sole risk and liability **
-// ** of any use of Xilinx products in critical applications, **
-// ** subject only to applicable laws and regulations governing **
-// ** limitations on product liability. **
-// ** **
-// ** Copyright 2010 Xilinx, Inc. **
-// ** All rights reserved. **
-// ** **
-// ** This disclaimer and copyright notice must be retained as part **
-// ** of this file at all times. **
-// ************************************************************************
-//
-//-----------------------------------------------------------------------------
-// Filename: processing_system7_v5_5_processing_system7.v
-// Version: v1.00.a
-// Description: This is the wrapper file for PSS.
-//-----------------------------------------------------------------------------
-// Structure: This section shows the hierarchical structure of
-// pss_wrapper.
-//
-// --processing_system7_v5_5_processing_system7.v
-// --PS7.v - Unisim component
-//-----------------------------------------------------------------------------
-// Author: SD
-//
-// History:
-//
-// SD 09/20/11 -- First version
-// ~~~~~~
-// Created the first version v2.00.a
-// ^^^^^^
-//------------------------------------------------------------------------------
-// ^^^^^^
-// SR 11/25/11 -- v3.00.a version
-// ~~~~~~~
-// Key changes are
-// 1. Changed all clock, reset and clktrig ports to be individual
-// signals instead of vectors. This is required for modeling of tools.
-// 2. Interrupts are now defined as individual signals as well.
-// 3. Added Clk buffer logic for FCLK_CLK
-// 4. Includes the ACP related changes done
-//
-// TODO:
-// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
-// number of interrupt ports connected for IRQ_F2P.
-//
-//------------------------------------------------------------------------------
-// ^^^^^^
-// KP 12/07/11 -- v3.00.a version
-// ~~~~~~~
-// Key changes are
-// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
-//------------------------------------------------------------------------------
-// ^^^^^^
-// NR 12/09/11 -- v3.00.a version
-// ~~~~~~~
-// Key changes are
-// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
-// to STRING and fix for CR 640523
-//------------------------------------------------------------------------------
-// ^^^^^^
-// NR 12/13/11 -- v3.00.a version
-// ~~~~~~~
-// Key changes are
-// Updated IRQ_F2P logic to address CR 641523.
-//------------------------------------------------------------------------------
-// ^^^^^^
-// NR 02/01/12 -- v3.01.a version
-// ~~~~~~~
-// Key changes are
-// Updated SDIO logic to address CR 636210.
-// |
-// Added C_PS7_SI_REV parameter to track SI Rev
-// Removed compress/decompress logic to address CR 642527.
-//------------------------------------------------------------------------------
-// ^^^^^^
-// NR 02/27/12 -- v3.01.a version
-// ~~~~~~~
-// Key changes are
-// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
-// ports as fix for CR 646379
-//------------------------------------------------------------------------------
-// ^^^^^^
-// NR 03/05/12 -- v3.01.a version
-// ~~~~~~~
-// Key changes are
-// Added/updated compress/decompress logic to address 648393
-//------------------------------------------------------------------------------
-// ^^^^^^
-// NR 03/14/12 -- v4.00.a version
-// ~~~~~~~
-// Unused parameters deleted CR 651120
-// Addressed CR 651751
-//------------------------------------------------------------------------------
-// ^^^^^^
-// NR 04/17/12 -- v4.01.a version
-// ~~~~~~~
-// Added FTM trace buffer functionality
-// Added support for ACP AxUSER ports local update
-//------------------------------------------------------------------------------
-// ^^^^^^
-// VR 05/18/12 -- v4.01.a version
-// ~~~~~~~
-// Fixed CR#659157
-//------------------------------------------------------------------------------
-// ^^^^^^
-// VR 07/25/12 -- v4.01.a version
-// ~~~~~~~
-// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
-// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
-//------------------------------------------------------------------------------
-// ^^^^^^
-// VR 11/06/12 -- v5.00 version
-// ~~~~~~~
-// CR #682573
-// Added BIBUF to fixed IO ports and IBUF to fixed input ports
-//------------------------------------------------------------------------------
-(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={750} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SPI} ioStandard={} bidis={2} ioBank={} clockFreq={159.090912} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS25} bidis={5} ioBank={Vcco_p1} clockFreq={159.090912} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={97.222221} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={133} usageRate={0.5} /><PLL domain={Processor} vco={1500.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1750.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>" *)
-(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=500, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=76.687, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=77.8025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=72.8405, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=111.904, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=73.119, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.8935, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=77.045, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=111.903, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=76.428, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=76.428, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=76.428, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=76.428, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\
-, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50, PCW_APU_PERIPHERAL_FREQMHZ=750, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=133, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=125, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=30, PCW_IOPLL_CTRL_FBDIV=35, PCW_DDRPLL_CTRL_FBDIV=20, PCW_CPU_CPU_PLL_FREQMHZ=1500.000, PCW_IO_IO_PLL_FREQMHZ=1750.000, PCW_DDR_DDR_PLL_FREQMHZ=1000.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=125\
-, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 2.5V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=16 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\
-, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=1, PCW_SD1_GRP_CD_IO=MIO 9, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=MIO 46 .. 47, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=MIO 40 .. 45, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=MIO 42, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=1, PCW_SPI1_SPI1_IO=EMIO, PCW_SPI1_GRP_SS0_ENABLE=1\
-, PCW_SPI1_GRP_SS0_IO=EMIO, PCW_SPI1_GRP_SS1_ENABLE=1, PCW_SPI1_GRP_SS1_IO=EMIO, PCW_SPI1_GRP_SS2_ENABLE=1, PCW_SPI1_GRP_SS2_IO=EMIO, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=1, PCW_CAN1_CAN1_IO=MIO 52 .. 53, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=MIO 50 .. 51, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL\
-, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0\
-, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
-(* HW_HANDOFF = "scalp_zynqps_processing_system7_0_0.hwdef" *)
-
-module processing_system7_v5_5_processing_system7
-
-#(
- parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
- parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
- parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
- parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
- parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
- parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
- parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
- parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
- parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
- parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
- parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
- parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
- parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
- parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
- parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
- parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
- parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
- parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
- parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
- parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
- parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
- parameter integer C_NUM_F2P_INTR_INPUTS = 1,
- parameter C_FCLK_CLK0_BUF = "TRUE",
- parameter C_FCLK_CLK1_BUF = "TRUE",
- parameter C_FCLK_CLK2_BUF = "TRUE",
- parameter C_FCLK_CLK3_BUF = "TRUE",
- parameter integer C_EMIO_GPIO_WIDTH = 64,
- parameter integer C_INCLUDE_TRACE_BUFFER = 0,
- parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
- parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
- parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
- parameter integer C_TRACE_PIPELINE_WIDTH = 8,
- parameter C_PS7_SI_REV = "PRODUCTION",
- parameter integer C_EN_EMIO_ENET0 = 0,
- parameter integer C_EN_EMIO_ENET1 = 0,
- parameter integer C_EN_EMIO_TRACE = 0,
- parameter integer C_DQ_WIDTH = 32,
- parameter integer C_DQS_WIDTH = 4,
- parameter integer C_DM_WIDTH = 4,
- parameter integer C_MIO_PRIMITIVE = 54,
- parameter C_PACKAGE_NAME = "clg484",
- parameter C_IRQ_F2P_MODE = "DIRECT",
- parameter C_TRACE_INTERNAL_WIDTH = 32,
- parameter integer C_EN_EMIO_PJTAG = 0,
-
- // Enable and disable AFI Secure transaction
- parameter C_USE_AXI_NONSECURE = 0,
-
- //parameters for HP enable ports
- parameter C_USE_S_AXI_HP0 = 0,
- parameter C_USE_S_AXI_HP1 = 0,
- parameter C_USE_S_AXI_HP2 = 0,
- parameter C_USE_S_AXI_HP3 = 0,
-
- //parameters for GP and ACP enable ports */
- parameter C_USE_M_AXI_GP0 = 0,
- parameter C_USE_M_AXI_GP1 = 0,
- parameter C_USE_S_AXI_GP0 = 0,
- parameter C_USE_S_AXI_GP1 = 0,
- parameter C_USE_S_AXI_ACP = 0,
- parameter C_GP0_EN_MODIFIABLE_TXN=0,
- parameter C_GP1_EN_MODIFIABLE_TXN=0
-
-)
-(
- //FMIO =========================================
-
- //FMIO CAN0
- output CAN0_PHY_TX,
- input CAN0_PHY_RX,
-
- //FMIO CAN1
- output CAN1_PHY_TX,
- input CAN1_PHY_RX,
-
- //FMIO ENET0
- output reg ENET0_GMII_TX_EN = 'b0,
- output reg ENET0_GMII_TX_ER = 'b0,
- output ENET0_MDIO_MDC,
- output ENET0_MDIO_O,
- output ENET0_MDIO_T,
- output ENET0_PTP_DELAY_REQ_RX,
- output ENET0_PTP_DELAY_REQ_TX,
- output ENET0_PTP_PDELAY_REQ_RX,
- output ENET0_PTP_PDELAY_REQ_TX,
- output ENET0_PTP_PDELAY_RESP_RX,
- output ENET0_PTP_PDELAY_RESP_TX,
- output ENET0_PTP_SYNC_FRAME_RX,
- output ENET0_PTP_SYNC_FRAME_TX,
- output ENET0_SOF_RX,
- output ENET0_SOF_TX,
-
-
- output reg [7:0] ENET0_GMII_TXD,
-
-
- input ENET0_GMII_COL,
- input ENET0_GMII_CRS,
- input ENET0_GMII_RX_CLK,
- input ENET0_GMII_RX_DV,
- input ENET0_GMII_RX_ER,
- input ENET0_GMII_TX_CLK,
- input ENET0_MDIO_I,
- input ENET0_EXT_INTIN,
- input [7:0] ENET0_GMII_RXD,
-
- //FMIO ENET1
- output reg ENET1_GMII_TX_EN = 'b0,
- output reg ENET1_GMII_TX_ER = 'b0,
- output ENET1_MDIO_MDC,
- output ENET1_MDIO_O,
- output ENET1_MDIO_T,
- output ENET1_PTP_DELAY_REQ_RX,
- output ENET1_PTP_DELAY_REQ_TX,
- output ENET1_PTP_PDELAY_REQ_RX,
- output ENET1_PTP_PDELAY_REQ_TX,
- output ENET1_PTP_PDELAY_RESP_RX,
- output ENET1_PTP_PDELAY_RESP_TX,
- output ENET1_PTP_SYNC_FRAME_RX,
- output ENET1_PTP_SYNC_FRAME_TX,
- output ENET1_SOF_RX,
- output ENET1_SOF_TX,
- output reg [7:0] ENET1_GMII_TXD,
-
- input ENET1_GMII_COL,
- input ENET1_GMII_CRS,
- input ENET1_GMII_RX_CLK,
- input ENET1_GMII_RX_DV,
- input ENET1_GMII_RX_ER,
- input ENET1_GMII_TX_CLK,
- input ENET1_MDIO_I,
- input ENET1_EXT_INTIN,
- input [7:0] ENET1_GMII_RXD,
-
- //FMIO GPIO
- input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
- output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
- output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
-
- //FMIO I2C0
- input I2C0_SDA_I,
- output I2C0_SDA_O,
- output I2C0_SDA_T,
- input I2C0_SCL_I,
- output I2C0_SCL_O,
- output I2C0_SCL_T,
-
- //FMIO I2C1
- input I2C1_SDA_I,
- output I2C1_SDA_O,
- output I2C1_SDA_T,
- input I2C1_SCL_I,
- output I2C1_SCL_O,
- output I2C1_SCL_T,
-
- //FMIO PJTAG
- input PJTAG_TCK,
- input PJTAG_TMS,
- input PJTAG_TDI,
- output PJTAG_TDO,
-
-
- //FMIO SDIO0
- output SDIO0_CLK,
- input SDIO0_CLK_FB,
- output SDIO0_CMD_O,
- input SDIO0_CMD_I,
- output SDIO0_CMD_T,
- input [3:0] SDIO0_DATA_I,
- output [3:0] SDIO0_DATA_O,
- output [3:0] SDIO0_DATA_T,
- output SDIO0_LED,
- input SDIO0_CDN,
- input SDIO0_WP,
- output SDIO0_BUSPOW,
- output [2:0] SDIO0_BUSVOLT,
-
- //FMIO SDIO1
- output SDIO1_CLK,
- input SDIO1_CLK_FB,
- output SDIO1_CMD_O,
- input SDIO1_CMD_I,
- output SDIO1_CMD_T,
- input [3:0] SDIO1_DATA_I,
- output [3:0] SDIO1_DATA_O,
- output [3:0] SDIO1_DATA_T,
- output SDIO1_LED,
- input SDIO1_CDN,
- input SDIO1_WP,
- output SDIO1_BUSPOW,
- output [2:0] SDIO1_BUSVOLT,
-
- //FMIO SPI0
- input SPI0_SCLK_I,
- output SPI0_SCLK_O,
- output SPI0_SCLK_T,
- input SPI0_MOSI_I,
- output SPI0_MOSI_O,
- output SPI0_MOSI_T,
- input SPI0_MISO_I,
- output SPI0_MISO_O,
- output SPI0_MISO_T,
- input SPI0_SS_I,
- output SPI0_SS_O,
- output SPI0_SS1_O,
- output SPI0_SS2_O,
- output SPI0_SS_T,
-
- //FMIO SPI1
- input SPI1_SCLK_I,
- output SPI1_SCLK_O,
- output SPI1_SCLK_T,
- input SPI1_MOSI_I,
- output SPI1_MOSI_O,
- output SPI1_MOSI_T,
- input SPI1_MISO_I,
- output SPI1_MISO_O,
- output SPI1_MISO_T,
- input SPI1_SS_I,
- output SPI1_SS_O,
- output SPI1_SS1_O,
- output SPI1_SS2_O,
- output SPI1_SS_T,
-
- //FMIO UART0
- output UART0_DTRN,
- output UART0_RTSN,
- output UART0_TX,
- input UART0_CTSN,
- input UART0_DCDN,
- input UART0_DSRN,
- input UART0_RIN,
- input UART0_RX,
-
- //FMIO UART1
- output UART1_DTRN,
- output UART1_RTSN,
- output UART1_TX,
- input UART1_CTSN,
- input UART1_DCDN,
- input UART1_DSRN,
- input UART1_RIN,
- input UART1_RX,
-
- //FMIO TTC0
- output TTC0_WAVE0_OUT,
- output TTC0_WAVE1_OUT,
- output TTC0_WAVE2_OUT,
- input TTC0_CLK0_IN,
- input TTC0_CLK1_IN,
- input TTC0_CLK2_IN,
-
- //FMIO TTC1
- output TTC1_WAVE0_OUT,
- output TTC1_WAVE1_OUT,
- output TTC1_WAVE2_OUT,
- input TTC1_CLK0_IN,
- input TTC1_CLK1_IN,
- input TTC1_CLK2_IN,
-
- //WDT
- input WDT_CLK_IN,
- output WDT_RST_OUT,
-
- //FTPORT
- input TRACE_CLK,
- output TRACE_CTL,
- output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
- output reg TRACE_CLK_OUT,
-
- // USB
- output [1:0] USB0_PORT_INDCTL,
- output USB0_VBUS_PWRSELECT,
- input USB0_VBUS_PWRFAULT,
-
- output [1:0] USB1_PORT_INDCTL,
- output USB1_VBUS_PWRSELECT,
- input USB1_VBUS_PWRFAULT,
-
- input SRAM_INTIN,
-
- //AIO ===================================================
-
- //M_AXI_GP0
-
- // -- Output
-
- output M_AXI_GP0_ARESETN,
- output M_AXI_GP0_ARVALID,
- output M_AXI_GP0_AWVALID,
- output M_AXI_GP0_BREADY,
- output M_AXI_GP0_RREADY,
- output M_AXI_GP0_WLAST,
- output M_AXI_GP0_WVALID,
- output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
- output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
- output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
- output [1:0] M_AXI_GP0_ARBURST,
- output [1:0] M_AXI_GP0_ARLOCK,
- output [2:0] M_AXI_GP0_ARSIZE,
- output [1:0] M_AXI_GP0_AWBURST,
- output [1:0] M_AXI_GP0_AWLOCK,
- output [2:0] M_AXI_GP0_AWSIZE,
- output [2:0] M_AXI_GP0_ARPROT,
- output [2:0] M_AXI_GP0_AWPROT,
- output [31:0] M_AXI_GP0_ARADDR,
- output [31:0] M_AXI_GP0_AWADDR,
- output [31:0] M_AXI_GP0_WDATA,
- output [3:0] M_AXI_GP0_ARCACHE,
- output [3:0] M_AXI_GP0_ARLEN,
- output [3:0] M_AXI_GP0_ARQOS,
- output [3:0] M_AXI_GP0_AWCACHE,
- output [3:0] M_AXI_GP0_AWLEN,
- output [3:0] M_AXI_GP0_AWQOS,
- output [3:0] M_AXI_GP0_WSTRB,
-
- // -- Input
-
- input M_AXI_GP0_ACLK,
- input M_AXI_GP0_ARREADY,
- input M_AXI_GP0_AWREADY,
- input M_AXI_GP0_BVALID,
- input M_AXI_GP0_RLAST,
- input M_AXI_GP0_RVALID,
- input M_AXI_GP0_WREADY,
- input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
- input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
- input [1:0] M_AXI_GP0_BRESP,
- input [1:0] M_AXI_GP0_RRESP,
- input [31:0] M_AXI_GP0_RDATA,
-
-
- //M_AXI_GP1
-
- // -- Output
-
- output M_AXI_GP1_ARESETN,
- output M_AXI_GP1_ARVALID,
- output M_AXI_GP1_AWVALID,
- output M_AXI_GP1_BREADY,
- output M_AXI_GP1_RREADY,
- output M_AXI_GP1_WLAST,
- output M_AXI_GP1_WVALID,
- output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
- output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
- output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
- output [1:0] M_AXI_GP1_ARBURST,
- output [1:0] M_AXI_GP1_ARLOCK,
- output [2:0] M_AXI_GP1_ARSIZE,
- output [1:0] M_AXI_GP1_AWBURST,
- output [1:0] M_AXI_GP1_AWLOCK,
- output [2:0] M_AXI_GP1_AWSIZE,
- output [2:0] M_AXI_GP1_ARPROT,
- output [2:0] M_AXI_GP1_AWPROT,
- output [31:0] M_AXI_GP1_ARADDR,
- output [31:0] M_AXI_GP1_AWADDR,
- output [31:0] M_AXI_GP1_WDATA,
- output [3:0] M_AXI_GP1_ARCACHE,
- output [3:0] M_AXI_GP1_ARLEN,
- output [3:0] M_AXI_GP1_ARQOS,
- output [3:0] M_AXI_GP1_AWCACHE,
- output [3:0] M_AXI_GP1_AWLEN,
- output [3:0] M_AXI_GP1_AWQOS,
- output [3:0] M_AXI_GP1_WSTRB,
-
- // -- Input
-
- input M_AXI_GP1_ACLK,
- input M_AXI_GP1_ARREADY,
- input M_AXI_GP1_AWREADY,
- input M_AXI_GP1_BVALID,
- input M_AXI_GP1_RLAST,
- input M_AXI_GP1_RVALID,
- input M_AXI_GP1_WREADY,
- input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
- input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
- input [1:0] M_AXI_GP1_BRESP,
- input [1:0] M_AXI_GP1_RRESP,
- input [31:0] M_AXI_GP1_RDATA,
-
-
- // S_AXI_GP0
-
- // -- Output
-
- output S_AXI_GP0_ARESETN,
- output S_AXI_GP0_ARREADY,
- output S_AXI_GP0_AWREADY,
- output S_AXI_GP0_BVALID,
- output S_AXI_GP0_RLAST,
- output S_AXI_GP0_RVALID,
- output S_AXI_GP0_WREADY,
- output [1:0] S_AXI_GP0_BRESP,
- output [1:0] S_AXI_GP0_RRESP,
- output [31:0] S_AXI_GP0_RDATA,
- output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
- output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
-
- // -- Input
- input S_AXI_GP0_ACLK,
- input S_AXI_GP0_ARVALID,
- input S_AXI_GP0_AWVALID,
- input S_AXI_GP0_BREADY,
- input S_AXI_GP0_RREADY,
- input S_AXI_GP0_WLAST,
- input S_AXI_GP0_WVALID,
- input [1:0] S_AXI_GP0_ARBURST,
- input [1:0] S_AXI_GP0_ARLOCK,
- input [2:0] S_AXI_GP0_ARSIZE,
- input [1:0] S_AXI_GP0_AWBURST,
- input [1:0] S_AXI_GP0_AWLOCK,
- input [2:0] S_AXI_GP0_AWSIZE,
- input [2:0] S_AXI_GP0_ARPROT,
- input [2:0] S_AXI_GP0_AWPROT,
- input [31:0] S_AXI_GP0_ARADDR,
- input [31:0] S_AXI_GP0_AWADDR,
- input [31:0] S_AXI_GP0_WDATA,
- input [3:0] S_AXI_GP0_ARCACHE,
- input [3:0] S_AXI_GP0_ARLEN,
- input [3:0] S_AXI_GP0_ARQOS,
- input [3:0] S_AXI_GP0_AWCACHE,
- input [3:0] S_AXI_GP0_AWLEN,
- input [3:0] S_AXI_GP0_AWQOS,
- input [3:0] S_AXI_GP0_WSTRB,
- input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
- input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
- input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
-
- // S_AXI_GP1
-
- // -- Output
- output S_AXI_GP1_ARESETN,
- output S_AXI_GP1_ARREADY,
- output S_AXI_GP1_AWREADY,
- output S_AXI_GP1_BVALID,
- output S_AXI_GP1_RLAST,
- output S_AXI_GP1_RVALID,
- output S_AXI_GP1_WREADY,
- output [1:0] S_AXI_GP1_BRESP,
- output [1:0] S_AXI_GP1_RRESP,
- output [31:0] S_AXI_GP1_RDATA,
- output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
- output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
-
- // -- Input
- input S_AXI_GP1_ACLK,
- input S_AXI_GP1_ARVALID,
- input S_AXI_GP1_AWVALID,
- input S_AXI_GP1_BREADY,
- input S_AXI_GP1_RREADY,
- input S_AXI_GP1_WLAST,
- input S_AXI_GP1_WVALID,
- input [1:0] S_AXI_GP1_ARBURST,
- input [1:0] S_AXI_GP1_ARLOCK,
- input [2:0] S_AXI_GP1_ARSIZE,
- input [1:0] S_AXI_GP1_AWBURST,
- input [1:0] S_AXI_GP1_AWLOCK,
- input [2:0] S_AXI_GP1_AWSIZE,
- input [2:0] S_AXI_GP1_ARPROT,
- input [2:0] S_AXI_GP1_AWPROT,
- input [31:0] S_AXI_GP1_ARADDR,
- input [31:0] S_AXI_GP1_AWADDR,
- input [31:0] S_AXI_GP1_WDATA,
- input [3:0] S_AXI_GP1_ARCACHE,
- input [3:0] S_AXI_GP1_ARLEN,
- input [3:0] S_AXI_GP1_ARQOS,
- input [3:0] S_AXI_GP1_AWCACHE,
- input [3:0] S_AXI_GP1_AWLEN,
- input [3:0] S_AXI_GP1_AWQOS,
- input [3:0] S_AXI_GP1_WSTRB,
- input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
- input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
- input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
-
- //S_AXI_ACP
-
- // -- Output
-
- output S_AXI_ACP_ARESETN,
- output S_AXI_ACP_ARREADY,
- output S_AXI_ACP_AWREADY,
- output S_AXI_ACP_BVALID,
- output S_AXI_ACP_RLAST,
- output S_AXI_ACP_RVALID,
- output S_AXI_ACP_WREADY,
- output [1:0] S_AXI_ACP_BRESP,
- output [1:0] S_AXI_ACP_RRESP,
- output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
- output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
- output [63:0] S_AXI_ACP_RDATA,
-
- // -- Input
-
- input S_AXI_ACP_ACLK,
- input S_AXI_ACP_ARVALID,
- input S_AXI_ACP_AWVALID,
- input S_AXI_ACP_BREADY,
- input S_AXI_ACP_RREADY,
- input S_AXI_ACP_WLAST,
- input S_AXI_ACP_WVALID,
- input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
- input [2:0] S_AXI_ACP_ARPROT,
- input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
- input [2:0] S_AXI_ACP_AWPROT,
- input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
- input [31:0] S_AXI_ACP_ARADDR,
- input [31:0] S_AXI_ACP_AWADDR,
- input [3:0] S_AXI_ACP_ARCACHE,
- input [3:0] S_AXI_ACP_ARLEN,
- input [3:0] S_AXI_ACP_ARQOS,
- input [3:0] S_AXI_ACP_AWCACHE,
- input [3:0] S_AXI_ACP_AWLEN,
- input [3:0] S_AXI_ACP_AWQOS,
- input [1:0] S_AXI_ACP_ARBURST,
- input [1:0] S_AXI_ACP_ARLOCK,
- input [2:0] S_AXI_ACP_ARSIZE,
- input [1:0] S_AXI_ACP_AWBURST,
- input [1:0] S_AXI_ACP_AWLOCK,
- input [2:0] S_AXI_ACP_AWSIZE,
- input [4:0] S_AXI_ACP_ARUSER,
- input [4:0] S_AXI_ACP_AWUSER,
- input [63:0] S_AXI_ACP_WDATA,
- input [7:0] S_AXI_ACP_WSTRB,
-
- // S_AXI_HP_0
-
- // -- Output
- output S_AXI_HP0_ARESETN,
- output S_AXI_HP0_ARREADY,
- output S_AXI_HP0_AWREADY,
- output S_AXI_HP0_BVALID,
- output S_AXI_HP0_RLAST,
- output S_AXI_HP0_RVALID,
- output S_AXI_HP0_WREADY,
- output [1:0] S_AXI_HP0_BRESP,
- output [1:0] S_AXI_HP0_RRESP,
- output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
- output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
- output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
- output [7:0] S_AXI_HP0_RCOUNT,
- output [7:0] S_AXI_HP0_WCOUNT,
- output [2:0] S_AXI_HP0_RACOUNT,
- output [5:0] S_AXI_HP0_WACOUNT,
-
- // -- Input
- input S_AXI_HP0_ACLK,
- input S_AXI_HP0_ARVALID,
- input S_AXI_HP0_AWVALID,
- input S_AXI_HP0_BREADY,
- input S_AXI_HP0_RDISSUECAP1_EN,
- input S_AXI_HP0_RREADY,
- input S_AXI_HP0_WLAST,
- input S_AXI_HP0_WRISSUECAP1_EN,
- input S_AXI_HP0_WVALID,
- input [1:0] S_AXI_HP0_ARBURST,
- input [1:0] S_AXI_HP0_ARLOCK,
- input [2:0] S_AXI_HP0_ARSIZE,
- input [1:0] S_AXI_HP0_AWBURST,
- input [1:0] S_AXI_HP0_AWLOCK,
- input [2:0] S_AXI_HP0_AWSIZE,
- input [2:0] S_AXI_HP0_ARPROT,
- input [2:0] S_AXI_HP0_AWPROT,
- input [31:0] S_AXI_HP0_ARADDR,
- input [31:0] S_AXI_HP0_AWADDR,
- input [3:0] S_AXI_HP0_ARCACHE,
- input [3:0] S_AXI_HP0_ARLEN,
- input [3:0] S_AXI_HP0_ARQOS,
- input [3:0] S_AXI_HP0_AWCACHE,
- input [3:0] S_AXI_HP0_AWLEN,
- input [3:0] S_AXI_HP0_AWQOS,
- input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
- input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
- input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
- input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
- input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
-
- // S_AXI_HP1
- // -- Output
- output S_AXI_HP1_ARESETN,
- output S_AXI_HP1_ARREADY,
- output S_AXI_HP1_AWREADY,
- output S_AXI_HP1_BVALID,
- output S_AXI_HP1_RLAST,
- output S_AXI_HP1_RVALID,
- output S_AXI_HP1_WREADY,
- output [1:0] S_AXI_HP1_BRESP,
- output [1:0] S_AXI_HP1_RRESP,
- output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
- output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
- output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
- output [7:0] S_AXI_HP1_RCOUNT,
- output [7:0] S_AXI_HP1_WCOUNT,
- output [2:0] S_AXI_HP1_RACOUNT,
- output [5:0] S_AXI_HP1_WACOUNT,
-
-
- // -- Input
- input S_AXI_HP1_ACLK,
- input S_AXI_HP1_ARVALID,
- input S_AXI_HP1_AWVALID,
- input S_AXI_HP1_BREADY,
- input S_AXI_HP1_RDISSUECAP1_EN,
- input S_AXI_HP1_RREADY,
- input S_AXI_HP1_WLAST,
- input S_AXI_HP1_WRISSUECAP1_EN,
- input S_AXI_HP1_WVALID,
- input [1:0] S_AXI_HP1_ARBURST,
- input [1:0] S_AXI_HP1_ARLOCK,
- input [2:0] S_AXI_HP1_ARSIZE,
- input [1:0] S_AXI_HP1_AWBURST,
- input [1:0] S_AXI_HP1_AWLOCK,
- input [2:0] S_AXI_HP1_AWSIZE,
- input [2:0] S_AXI_HP1_ARPROT,
- input [2:0] S_AXI_HP1_AWPROT,
- input [31:0] S_AXI_HP1_ARADDR,
- input [31:0] S_AXI_HP1_AWADDR,
- input [3:0] S_AXI_HP1_ARCACHE,
- input [3:0] S_AXI_HP1_ARLEN,
- input [3:0] S_AXI_HP1_ARQOS,
- input [3:0] S_AXI_HP1_AWCACHE,
- input [3:0] S_AXI_HP1_AWLEN,
- input [3:0] S_AXI_HP1_AWQOS,
- input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
- input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
- input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
- input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
- input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
-
- // S_AXI_HP2
- // -- Output
- output S_AXI_HP2_ARESETN,
- output S_AXI_HP2_ARREADY,
- output S_AXI_HP2_AWREADY,
- output S_AXI_HP2_BVALID,
- output S_AXI_HP2_RLAST,
- output S_AXI_HP2_RVALID,
- output S_AXI_HP2_WREADY,
- output [1:0] S_AXI_HP2_BRESP,
- output [1:0] S_AXI_HP2_RRESP,
- output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
- output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
- output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
- output [7:0] S_AXI_HP2_RCOUNT,
- output [7:0] S_AXI_HP2_WCOUNT,
- output [2:0] S_AXI_HP2_RACOUNT,
- output [5:0] S_AXI_HP2_WACOUNT,
-
-
- // -- Input
- input S_AXI_HP2_ACLK,
- input S_AXI_HP2_ARVALID,
- input S_AXI_HP2_AWVALID,
- input S_AXI_HP2_BREADY,
- input S_AXI_HP2_RDISSUECAP1_EN,
- input S_AXI_HP2_RREADY,
- input S_AXI_HP2_WLAST,
- input S_AXI_HP2_WRISSUECAP1_EN,
- input S_AXI_HP2_WVALID,
- input [1:0] S_AXI_HP2_ARBURST,
- input [1:0] S_AXI_HP2_ARLOCK,
- input [2:0] S_AXI_HP2_ARSIZE,
- input [1:0] S_AXI_HP2_AWBURST,
- input [1:0] S_AXI_HP2_AWLOCK,
- input [2:0] S_AXI_HP2_AWSIZE,
- input [2:0] S_AXI_HP2_ARPROT,
- input [2:0] S_AXI_HP2_AWPROT,
- input [31:0] S_AXI_HP2_ARADDR,
- input [31:0] S_AXI_HP2_AWADDR,
- input [3:0] S_AXI_HP2_ARCACHE,
- input [3:0] S_AXI_HP2_ARLEN,
- input [3:0] S_AXI_HP2_ARQOS,
- input [3:0] S_AXI_HP2_AWCACHE,
- input [3:0] S_AXI_HP2_AWLEN,
- input [3:0] S_AXI_HP2_AWQOS,
- input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
- input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
- input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
- input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
- input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
-
- // S_AXI_HP_3
-
- // -- Output
- output S_AXI_HP3_ARESETN,
- output S_AXI_HP3_ARREADY,
- output S_AXI_HP3_AWREADY,
- output S_AXI_HP3_BVALID,
- output S_AXI_HP3_RLAST,
- output S_AXI_HP3_RVALID,
- output S_AXI_HP3_WREADY,
- output [1:0] S_AXI_HP3_BRESP,
- output [1:0] S_AXI_HP3_RRESP,
- output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
- output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
- output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
- output [7:0] S_AXI_HP3_RCOUNT,
- output [7:0] S_AXI_HP3_WCOUNT,
- output [2:0] S_AXI_HP3_RACOUNT,
- output [5:0] S_AXI_HP3_WACOUNT,
-
-
- // -- Input
- input S_AXI_HP3_ACLK,
- input S_AXI_HP3_ARVALID,
- input S_AXI_HP3_AWVALID,
- input S_AXI_HP3_BREADY,
- input S_AXI_HP3_RDISSUECAP1_EN,
- input S_AXI_HP3_RREADY,
- input S_AXI_HP3_WLAST,
- input S_AXI_HP3_WRISSUECAP1_EN,
- input S_AXI_HP3_WVALID,
- input [1:0] S_AXI_HP3_ARBURST,
- input [1:0] S_AXI_HP3_ARLOCK,
- input [2:0] S_AXI_HP3_ARSIZE,
- input [1:0] S_AXI_HP3_AWBURST,
- input [1:0] S_AXI_HP3_AWLOCK,
- input [2:0] S_AXI_HP3_AWSIZE,
- input [2:0] S_AXI_HP3_ARPROT,
- input [2:0] S_AXI_HP3_AWPROT,
- input [31:0] S_AXI_HP3_ARADDR,
- input [31:0] S_AXI_HP3_AWADDR,
- input [3:0] S_AXI_HP3_ARCACHE,
- input [3:0] S_AXI_HP3_ARLEN,
- input [3:0] S_AXI_HP3_ARQOS,
- input [3:0] S_AXI_HP3_AWCACHE,
- input [3:0] S_AXI_HP3_AWLEN,
- input [3:0] S_AXI_HP3_AWQOS,
- input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
- input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
- input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
- input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
- input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
-
- //FIO ========================================
-
- //IRQ
- //output [28:0] IRQ_P2F,
- output IRQ_P2F_DMAC_ABORT ,
- output IRQ_P2F_DMAC0,
- output IRQ_P2F_DMAC1,
- output IRQ_P2F_DMAC2,
- output IRQ_P2F_DMAC3,
- output IRQ_P2F_DMAC4,
- output IRQ_P2F_DMAC5,
- output IRQ_P2F_DMAC6,
- output IRQ_P2F_DMAC7,
- output IRQ_P2F_SMC,
- output IRQ_P2F_QSPI,
- output IRQ_P2F_CTI,
- output IRQ_P2F_GPIO,
- output IRQ_P2F_USB0,
- output IRQ_P2F_ENET0,
- output IRQ_P2F_ENET_WAKE0,
- output IRQ_P2F_SDIO0,
- output IRQ_P2F_I2C0,
- output IRQ_P2F_SPI0,
- output IRQ_P2F_UART0,
- output IRQ_P2F_CAN0,
- output IRQ_P2F_USB1,
- output IRQ_P2F_ENET1,
- output IRQ_P2F_ENET_WAKE1,
- output IRQ_P2F_SDIO1,
- output IRQ_P2F_I2C1,
- output IRQ_P2F_SPI1,
- output IRQ_P2F_UART1,
- output IRQ_P2F_CAN1,
- input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
- input Core0_nFIQ,
- input Core0_nIRQ,
- input Core1_nFIQ,
- input Core1_nIRQ,
-
- //DMA
-
- output [1:0] DMA0_DATYPE,
- output DMA0_DAVALID,
- output DMA0_DRREADY,
- output DMA0_RSTN,
- output [1:0] DMA1_DATYPE,
- output DMA1_DAVALID,
- output DMA1_DRREADY,
- output DMA1_RSTN,
- output [1:0] DMA2_DATYPE,
- output DMA2_DAVALID,
- output DMA2_DRREADY,
- output DMA2_RSTN,
- output [1:0] DMA3_DATYPE,
- output DMA3_DAVALID,
- output DMA3_DRREADY,
- output DMA3_RSTN,
- input DMA0_ACLK,
- input DMA0_DAREADY,
- input DMA0_DRLAST,
- input DMA0_DRVALID,
- input DMA1_ACLK,
- input DMA1_DAREADY,
- input DMA1_DRLAST,
- input DMA1_DRVALID,
- input DMA2_ACLK,
- input DMA2_DAREADY,
- input DMA2_DRLAST,
- input DMA2_DRVALID,
- input DMA3_ACLK,
- input DMA3_DAREADY,
- input DMA3_DRLAST,
- input DMA3_DRVALID,
- input [1:0] DMA0_DRTYPE,
- input [1:0] DMA1_DRTYPE,
- input [1:0] DMA2_DRTYPE,
- input [1:0] DMA3_DRTYPE,
-
- //FCLK
- output FCLK_CLK3,
- output FCLK_CLK2,
- output FCLK_CLK1,
- output FCLK_CLK0,
-
- input FCLK_CLKTRIG3_N,
- input FCLK_CLKTRIG2_N,
- input FCLK_CLKTRIG1_N,
- input FCLK_CLKTRIG0_N,
-
- output FCLK_RESET3_N,
- output FCLK_RESET2_N,
- output FCLK_RESET1_N,
- output FCLK_RESET0_N,
-
- //FTMD
- input [31:0] FTMD_TRACEIN_DATA,
- input FTMD_TRACEIN_VALID,
- input FTMD_TRACEIN_CLK,
- input [3:0] FTMD_TRACEIN_ATID,
-
- //FTMT
- input FTMT_F2P_TRIG_0,
- output FTMT_F2P_TRIGACK_0,
- input FTMT_F2P_TRIG_1,
- output FTMT_F2P_TRIGACK_1,
- input FTMT_F2P_TRIG_2,
- output FTMT_F2P_TRIGACK_2,
- input FTMT_F2P_TRIG_3,
- output FTMT_F2P_TRIGACK_3,
- input [31:0] FTMT_F2P_DEBUG,
- input FTMT_P2F_TRIGACK_0,
- output FTMT_P2F_TRIG_0,
- input FTMT_P2F_TRIGACK_1,
- output FTMT_P2F_TRIG_1,
- input FTMT_P2F_TRIGACK_2,
- output FTMT_P2F_TRIG_2,
- input FTMT_P2F_TRIGACK_3,
- output FTMT_P2F_TRIG_3,
- output [31:0] FTMT_P2F_DEBUG,
-
- //FIDLE
- input FPGA_IDLE_N,
-
- //EVENT
-
- output EVENT_EVENTO,
- output [1:0] EVENT_STANDBYWFE,
- output [1:0] EVENT_STANDBYWFI,
- input EVENT_EVENTI,
-
-
- //DARB
- input [3:0] DDR_ARB,
- inout [C_MIO_PRIMITIVE - 1:0] MIO,
-
- //DDR
- inout DDR_CAS_n, // CASB
- inout DDR_CKE, // CKE
- inout DDR_Clk_n, // CKN
- inout DDR_Clk, // CKP
- inout DDR_CS_n, // CSB
- inout DDR_DRSTB, // DDR_DRSTB
- inout DDR_ODT, // ODT
- inout DDR_RAS_n, // RASB
- inout DDR_WEB,
- inout [2:0] DDR_BankAddr, // BA
- inout [14:0] DDR_Addr, // A
-
- inout DDR_VRN,
- inout DDR_VRP,
- inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
- inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
- inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
- inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
-
- inout PS_SRSTB, // SRSTB
- inout PS_CLK, // CLK
- inout PS_PORB // PORB
-
-
-);
-
-wire [11:0] M_AXI_GP0_AWID_FULL;
-wire [11:0] M_AXI_GP0_WID_FULL;
-wire [11:0] M_AXI_GP0_ARID_FULL;
-
-wire [11:0] M_AXI_GP0_BID_FULL;
-wire [11:0] M_AXI_GP0_RID_FULL;
-
-wire [11:0] M_AXI_GP1_AWID_FULL;
-wire [11:0] M_AXI_GP1_WID_FULL;
-wire [11:0] M_AXI_GP1_ARID_FULL;
-
-wire [11:0] M_AXI_GP1_BID_FULL;
-wire [11:0] M_AXI_GP1_RID_FULL;
-
-wire [3:0] M_AXI_GP0_ARCACHE_t;
-wire [3:0] M_AXI_GP1_ARCACHE_t;
-wire [3:0] M_AXI_GP0_AWCACHE_t;
-wire [3:0] M_AXI_GP1_AWCACHE_t;
-
-
-// Wires for connecting to the PS7
-wire ENET0_GMII_TX_EN_i;
-wire ENET0_GMII_TX_ER_i;
-reg ENET0_GMII_COL_i;
-reg ENET0_GMII_CRS_i;
-reg ENET0_GMII_RX_DV_i;
-reg ENET0_GMII_RX_ER_i;
-reg [7:0] ENET0_GMII_RXD_i;
-wire [7:0] ENET0_GMII_TXD_i;
-
-wire ENET1_GMII_TX_EN_i;
-wire ENET1_GMII_TX_ER_i;
-reg ENET1_GMII_COL_i;
-reg ENET1_GMII_CRS_i;
-reg ENET1_GMII_RX_DV_i;
-reg ENET1_GMII_RX_ER_i;
-reg [7:0] ENET1_GMII_RXD_i;
-wire [7:0] ENET1_GMII_TXD_i;
-
-reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
-reg FTMD_TRACEIN_VALID_notracebuf;
-reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
-
-wire [31:0] FTMD_TRACEIN_DATA_i;
-wire FTMD_TRACEIN_VALID_i;
-wire [3:0] FTMD_TRACEIN_ATID_i;
-
-wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
-wire FTMD_TRACEIN_VALID_tracebuf;
-wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
-
-wire [5:0] S_AXI_GP0_BID_out;
-wire [5:0] S_AXI_GP0_RID_out;
-wire [5:0] S_AXI_GP0_ARID_in;
-wire [5:0] S_AXI_GP0_AWID_in;
-wire [5:0] S_AXI_GP0_WID_in;
-
-wire [5:0] S_AXI_GP1_BID_out;
-wire [5:0] S_AXI_GP1_RID_out;
-wire [5:0] S_AXI_GP1_ARID_in;
-wire [5:0] S_AXI_GP1_AWID_in;
-wire [5:0] S_AXI_GP1_WID_in;
-
-wire [5:0] S_AXI_HP0_BID_out;
-wire [5:0] S_AXI_HP0_RID_out;
-wire [5:0] S_AXI_HP0_ARID_in;
-wire [5:0] S_AXI_HP0_AWID_in;
-wire [5:0] S_AXI_HP0_WID_in;
-
-wire [5:0] S_AXI_HP1_BID_out;
-wire [5:0] S_AXI_HP1_RID_out;
-wire [5:0] S_AXI_HP1_ARID_in;
-wire [5:0] S_AXI_HP1_AWID_in;
-wire [5:0] S_AXI_HP1_WID_in;
-
-wire [5:0] S_AXI_HP2_BID_out;
-wire [5:0] S_AXI_HP2_RID_out;
-wire [5:0] S_AXI_HP2_ARID_in;
-wire [5:0] S_AXI_HP2_AWID_in;
-wire [5:0] S_AXI_HP2_WID_in;
-
-wire [5:0] S_AXI_HP3_BID_out;
-wire [5:0] S_AXI_HP3_RID_out;
-wire [5:0] S_AXI_HP3_ARID_in;
-wire [5:0] S_AXI_HP3_AWID_in;
-wire [5:0] S_AXI_HP3_WID_in;
-
-wire [2:0] S_AXI_ACP_BID_out;
-wire [2:0] S_AXI_ACP_RID_out;
-wire [2:0] S_AXI_ACP_ARID_in;
-wire [2:0] S_AXI_ACP_AWID_in;
-wire [2:0] S_AXI_ACP_WID_in;
-
-wire [63:0] S_AXI_HP0_WDATA_in;
-wire [7:0] S_AXI_HP0_WSTRB_in;
-wire [63:0] S_AXI_HP0_RDATA_out;
-
-wire [63:0] S_AXI_HP1_WDATA_in;
-wire [7:0] S_AXI_HP1_WSTRB_in;
-wire [63:0] S_AXI_HP1_RDATA_out;
-
-wire [63:0] S_AXI_HP2_WDATA_in;
-wire [7:0] S_AXI_HP2_WSTRB_in;
-wire [63:0] S_AXI_HP2_RDATA_out;
-
-wire [63:0] S_AXI_HP3_WDATA_in;
-wire [7:0] S_AXI_HP3_WSTRB_in;
-wire [63:0] S_AXI_HP3_RDATA_out;
-
-wire [1:0] M_AXI_GP0_ARSIZE_i;
-wire [1:0] M_AXI_GP0_AWSIZE_i;
-
-wire [1:0] M_AXI_GP1_ARSIZE_i;
-wire [1:0] M_AXI_GP1_AWSIZE_i;
-
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
-
-
-wire SAXIACPARREADY_W;
-wire SAXIACPAWREADY_W;
-wire SAXIACPBVALID_W;
-wire SAXIACPRLAST_W;
-wire SAXIACPRVALID_W;
-wire SAXIACPWREADY_W;
-wire [1:0] SAXIACPBRESP_W;
-wire [1:0] SAXIACPRRESP_W;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
-wire [63:0] SAXIACPRDATA_W;
-
-wire S_AXI_ATC_ARVALID;
-wire S_AXI_ATC_AWVALID;
-wire S_AXI_ATC_BREADY;
-wire S_AXI_ATC_RREADY;
-wire S_AXI_ATC_WLAST;
-wire S_AXI_ATC_WVALID;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
-wire [2:0] S_AXI_ATC_ARPROT;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
-wire [2:0] S_AXI_ATC_AWPROT;
-wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
-wire [31:0] S_AXI_ATC_ARADDR;
-wire [31:0] S_AXI_ATC_AWADDR;
-wire [3:0] S_AXI_ATC_ARCACHE;
-wire [3:0] S_AXI_ATC_ARLEN;
-wire [3:0] S_AXI_ATC_ARQOS;
-wire [3:0] S_AXI_ATC_AWCACHE;
-wire [3:0] S_AXI_ATC_AWLEN;
-wire [3:0] S_AXI_ATC_AWQOS;
-wire [1:0] S_AXI_ATC_ARBURST;
-wire [1:0] S_AXI_ATC_ARLOCK;
-wire [2:0] S_AXI_ATC_ARSIZE;
-wire [1:0] S_AXI_ATC_AWBURST;
-wire [1:0] S_AXI_ATC_AWLOCK;
-wire [2:0] S_AXI_ATC_AWSIZE;
-wire [4:0] S_AXI_ATC_ARUSER;
-wire [4:0] S_AXI_ATC_AWUSER;
-wire [63:0] S_AXI_ATC_WDATA;
-wire [7:0] S_AXI_ATC_WSTRB;
-
-
-wire SAXIACPARVALID_W;
-wire SAXIACPAWVALID_W;
-wire SAXIACPBREADY_W;
-wire SAXIACPRREADY_W;
-wire SAXIACPWLAST_W;
-wire SAXIACPWVALID_W;
-wire [2:0] SAXIACPARPROT_W;
-wire [2:0] SAXIACPAWPROT_W;
-wire [31:0] SAXIACPARADDR_W;
-wire [31:0] SAXIACPAWADDR_W;
-wire [3:0] SAXIACPARCACHE_W;
-wire [3:0] SAXIACPARLEN_W;
-wire [3:0] SAXIACPARQOS_W;
-wire [3:0] SAXIACPAWCACHE_W;
-wire [3:0] SAXIACPAWLEN_W;
-wire [3:0] SAXIACPAWQOS_W;
-wire [1:0] SAXIACPARBURST_W;
-wire [1:0] SAXIACPARLOCK_W;
-wire [2:0] SAXIACPARSIZE_W;
-wire [1:0] SAXIACPAWBURST_W;
-wire [1:0] SAXIACPAWLOCK_W;
-wire [2:0] SAXIACPAWSIZE_W;
-wire [4:0] SAXIACPARUSER_W;
-wire [4:0] SAXIACPAWUSER_W;
-wire [63:0] SAXIACPWDATA_W;
-wire [7:0] SAXIACPWSTRB_W;
-
-// AxUSER signal update
-wire [4:0] param_aruser;
-wire [4:0] param_awuser;
-
-// Added to address CR 651751
-wire [3:0] fclk_clktrig_gnd = 4'h0;
-
-
-wire [19:0] irq_f2p_i;
-wire [15:0] irq_f2p_null = 16'h0000;
-
-// EMIO I2C0
-wire I2C0_SDA_T_n;
-wire I2C0_SCL_T_n;
-// EMIO I2C1
-wire I2C1_SDA_T_n;
-wire I2C1_SCL_T_n;
-// EMIO SPI0
-wire SPI0_SCLK_T_n;
-wire SPI0_MOSI_T_n;
-wire SPI0_MISO_T_n;
-wire SPI0_SS_T_n;
-// EMIO SPI1
-wire SPI1_SCLK_T_n;
-wire SPI1_MOSI_T_n;
-wire SPI1_MISO_T_n;
-wire SPI1_SS_T_n;
-
-// EMIO GEM0
-wire ENET0_MDIO_T_n;
-
-// EMIO GEM1
-wire ENET1_MDIO_T_n;
-
-// EMIO GPIO
-wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
-
-wire [63:0] gpio_out_t_n;
-wire [63:0] gpio_out;
-wire [63:0] gpio_in63_0;
-
-//For Clock buffering
-wire [3:0] FCLK_CLK_unbuffered;
-wire [3:0] FCLK_CLK_buffered;
-wire FCLK_CLK0_temp;
-
-// EMIO PJTAG
-wire PJTAG_TDO_O;
-wire PJTAG_TDO_T;
-wire PJTAG_TDO_T_n;
-
-// EMIO SDIO0
-wire SDIO0_CMD_T_n;
-wire [3:0] SDIO0_DATA_T_n;
-
-// EMIO SDIO1
-wire SDIO1_CMD_T_n;
-wire [3:0] SDIO1_DATA_T_n;
-
-// buffered IO
-wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
-wire buffered_DDR_WEB;
-wire buffered_DDR_CAS_n;
-wire buffered_DDR_CKE;
-wire buffered_DDR_Clk_n;
-wire buffered_DDR_Clk;
-wire buffered_DDR_CS_n;
-wire buffered_DDR_DRSTB;
-wire buffered_DDR_ODT;
-wire buffered_DDR_RAS_n;
-wire [2:0] buffered_DDR_BankAddr;
-wire [14:0] buffered_DDR_Addr;
-
-wire buffered_DDR_VRN;
-wire buffered_DDR_VRP;
-wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
-wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
-wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
-wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
-
-wire buffered_PS_SRSTB;
-wire buffered_PS_CLK;
-wire buffered_PS_PORB;
-
-wire S_AXI_HP0_ACLK_temp;
-wire S_AXI_HP1_ACLK_temp;
-wire S_AXI_HP2_ACLK_temp;
-wire S_AXI_HP3_ACLK_temp;
-wire M_AXI_GP0_ACLK_temp;
-wire M_AXI_GP1_ACLK_temp;
-wire S_AXI_GP0_ACLK_temp;
-wire S_AXI_GP1_ACLK_temp;
-wire S_AXI_ACP_ACLK_temp;
-
-wire [31:0] TRACE_DATA_i;
-wire TRACE_CTL_i;
-(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
-(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
-
-// fixed CR #665394
-integer j;
-generate
- if (C_EN_EMIO_TRACE == 1) begin
- always @(posedge TRACE_CLK)
- begin
- TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
- TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
- for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
- TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
- TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
- end
- TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
- end
- end
-else
-begin
-always @*
-begin
-TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
- TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
- for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
- TRACE_CTL_PIPE[j-1] <= 1'b0;
- TRACE_DATA_PIPE[j-1] <= 1'b0;
- end
- TRACE_CLK_OUT <= 1'b0;
- end
-end
-endgenerate
-
-assign TRACE_CTL = TRACE_CTL_PIPE[0];
-
-assign TRACE_DATA = TRACE_DATA_PIPE[0];
-
-//irq_p2f
-
-// Updated IRQ_F2P logic to address CR 641523
-generate
- if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
- assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
- end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
- assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
- end else begin : irq_f2p_select
- if (C_IRQ_F2P_MODE == "DIRECT") begin
- assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
- irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
- IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
- end else begin
- assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
- IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
- irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
- end
- end
-endgenerate
-
-assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
-assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
-assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
-assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
-
-
-
-// Compress Function
-
-
-// Modified as per CR 631955
-//function [11:0] uncompress_id;
-// input [5:0] id;
-// begin
-// case (id[5:0])
-// // dmac0
-// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
-// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
-// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
-// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
-// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
-// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
-// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
-// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
-// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
-// // ioum
-// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
-// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
-// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
-// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
-// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
-// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
-// // devci
-// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
-// // dap
-// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
-// // l2m1 (CPU000)
-// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
-// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
-// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
-// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
-// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
-// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
-// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
-// // l2m1 (CPU001)
-// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
-// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
-// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
-// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
-// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
-// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
-// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
-// // l2m1 (L2CC)
-// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
-// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
-// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
-// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
-// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
-// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
-// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
-// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
-// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
-// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
-// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
-// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
-// // l2m1 (ACP)
-// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
-// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
-// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
-// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
-// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
-// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
-// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
-// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
-// default : uncompress_id = ~0;
-// endcase
-// end
-//endfunction
-//
-//function [5:0] compress_id;
-// input [11:0] id;
-// begin
-// case (id[11:0])
-// // dmac0
-// 12'b010000_1000_00 : compress_id = 'd1 ;
-// 12'b010000_0000_00 : compress_id = 'd2 ;
-// 12'b010000_0001_00 : compress_id = 'd3 ;
-// 12'b010000_0010_00 : compress_id = 'd4 ;
-// 12'b010000_0011_00 : compress_id = 'd5 ;
-// 12'b010000_0100_00 : compress_id = 'd6 ;
-// 12'b010000_0101_00 : compress_id = 'd7 ;
-// 12'b010000_0110_00 : compress_id = 'd8 ;
-// 12'b010000_0111_00 : compress_id = 'd9 ;
-// // ioum
-// 12'b0100000_000_01 : compress_id = 'd10 ;
-// 12'b0100000_001_01 : compress_id = 'd11 ;
-// 12'b0100000_010_01 : compress_id = 'd12 ;
-// 12'b0100000_011_01 : compress_id = 'd13 ;
-// 12'b0100000_100_01 : compress_id = 'd14 ;
-// 12'b0100000_101_01 : compress_id = 'd15 ;
-// // devci
-// 12'b1000_0000_0000 : compress_id = 'd16 ;
-// // dap
-// 12'b1000_0000_0001 : compress_id = 'd17 ;
-// // l2m1 (CPU000)
-// 12'b11_000_000_00_00 : compress_id = 'd18 ;
-// 12'b11_010_000_00_00 : compress_id = 'd19 ;
-// 12'b11_011_000_00_00 : compress_id = 'd20 ;
-// 12'b11_100_000_00_00 : compress_id = 'd21 ;
-// 12'b11_101_000_00_00 : compress_id = 'd22 ;
-// 12'b11_110_000_00_00 : compress_id = 'd23 ;
-// 12'b11_111_000_00_00 : compress_id = 'd24 ;
-// // l2m1 (CPU001)
-// 12'b11_000_001_00_00 : compress_id = 'd25 ;
-// 12'b11_010_001_00_00 : compress_id = 'd26 ;
-// 12'b11_011_001_00_00 : compress_id = 'd27 ;
-// 12'b11_100_001_00_00 : compress_id = 'd28 ;
-// 12'b11_101_001_00_00 : compress_id = 'd29 ;
-// 12'b11_110_001_00_00 : compress_id = 'd30 ;
-// 12'b11_111_001_00_00 : compress_id = 'd31 ;
-// // l2m1 (L2CC)
-// 12'b11_000_00101_00 : compress_id = 'd32 ;
-// 12'b11_000_01001_00 : compress_id = 'd33 ;
-// 12'b11_000_01101_00 : compress_id = 'd34 ;
-// 12'b11_000_10011_00 : compress_id = 'd35 ;
-// 12'b11_000_10111_00 : compress_id = 'd36 ;
-// 12'b11_000_11011_00 : compress_id = 'd37 ;
-// 12'b11_000_11111_00 : compress_id = 'd38 ;
-// 12'b11_000_00011_00 : compress_id = 'd39 ;
-// 12'b11_000_00111_00 : compress_id = 'd40 ;
-// 12'b11_000_01011_00 : compress_id = 'd41 ;
-// 12'b11_000_01111_00 : compress_id = 'd42 ;
-// 12'b11_000_00001_00 : compress_id = 'd43 ;
-// // l2m1 (ACP)
-// 12'b11_000_10000_00 : compress_id = 'd44 ;
-// 12'b11_001_10000_00 : compress_id = 'd45 ;
-// 12'b11_010_10000_00 : compress_id = 'd46 ;
-// 12'b11_011_10000_00 : compress_id = 'd47 ;
-// 12'b11_100_10000_00 : compress_id = 'd48 ;
-// 12'b11_101_10000_00 : compress_id = 'd49 ;
-// 12'b11_110_10000_00 : compress_id = 'd50 ;
-// 12'b11_111_10000_00 : compress_id = 'd51 ;
-// default: compress_id = ~0;
-// endcase
-// end
-//endfunction
-
-// Modified as per CR 648393
-
- function [5:0] compress_id;
- input [11:0] id;
- begin
- compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
- compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
- compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
- compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
- compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
- compress_id[5] = id[11] & id[10] & ~id[3];
- end
- endfunction
-
- function [11:0] uncompress_id;
- input [5:0] id;
- begin
- case (id[5:0])
- // dmac0
- 6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
- 6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
- 6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
- 6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
- 6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
- 6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
- 6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
- 6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
- 6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
- // ioum
- 6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
- 6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
- 6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
- 6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
- 6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
- 6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
- // devci
- 6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
- // dap
- 6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
- // l2m1 (CPU000)
- 6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
- 6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
- 6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
- 6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
- 6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
- 6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
- 6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
- // l2m1 (CPU001)
- 6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
- 6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
- 6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
- 6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
- 6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
- 6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
- 6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
- // l2m1 (L2CC)
- 6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
- 6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
- 6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
- 6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
- 6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
- 6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
- 6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
- 6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
- 6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
- 6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
- 6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
- 6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
- // l2m1 (ACP)
- 6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
- 6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
- 6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
- 6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
- 6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
- 6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
- 6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
- 6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
- default : uncompress_id = 12'hx ;
- endcase
- end
- endfunction
-
-
-// Static Remap logic Enablement and Disablement for C_M_AXI0 port
-
- assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
- assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
- assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
- assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
- assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
-
- // Static Remap logic Enablement and Disablement for C_M_AXI1 port
-
- assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
- assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
- assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
- assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
- assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
-
-
-//// Compress_id and uncompress_id has been removed to address CR 642527
-//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
-// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
-// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
-// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
-// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
-// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
-//
-// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
-// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
-// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
-// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
-// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
-
-
-// Pipeline Stage for ENET0
-
-generate
- if (C_EN_EMIO_ENET0 == 1) begin
- always @(posedge ENET0_GMII_TX_CLK)
- begin
- ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
- ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
- ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
- ENET0_GMII_COL_i <= ENET0_GMII_COL;
- ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
- end
- end
- else
- always@*
- begin
- ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
- ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
- ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
- ENET0_GMII_COL_i <= 'b0;
- ENET0_GMII_CRS_i <= 'b0;
- end
-endgenerate
-
-generate
- if (C_EN_EMIO_ENET0 == 1) begin
- always @(posedge ENET0_GMII_RX_CLK)
- begin
- ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
- ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
- ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
- end
- end
- else
- begin
- always @*
- begin
- ENET0_GMII_RXD_i <= 0;
- ENET0_GMII_RX_DV_i <= 0;
- ENET0_GMII_RX_ER_i <= 0;
- end
- end
-endgenerate
-
-// Pipeline Stage for ENET1
-
-generate
- if (C_EN_EMIO_ENET1 == 1) begin
- always @(posedge ENET1_GMII_TX_CLK)
- begin
- ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
- ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
- ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
- ENET1_GMII_COL_i <= ENET1_GMII_COL;
- ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
- end
- end
- else
- begin
- always@*
- begin
- ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
- ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
- ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
- ENET1_GMII_COL_i <= 0;
- ENET1_GMII_CRS_i <= 0;
- end
- end
-endgenerate
-
-generate
- if (C_EN_EMIO_ENET1 == 1) begin
- always @(posedge ENET1_GMII_RX_CLK)
- begin
- ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
- ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
- ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
- end
- end
-else
- begin
- always @*
- begin
- ENET1_GMII_RXD_i <= 'b0;
- ENET1_GMII_RX_DV_i <= 'b0;
- ENET1_GMII_RX_ER_i <= 'b0;
- end
- end
-endgenerate
-
-// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
-
-generate
- if (C_EN_EMIO_TRACE == 1) begin
- if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
-
- // Pipeline Stage for Traceport ATID
- always @(posedge FTMD_TRACEIN_CLK)
- begin
- FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
- FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
- FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
- end
-
- assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
- assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
- assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
-
- end else begin : gen_trace_buffer
-
- processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
- .USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
- .C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
- )
- trace_buffer_i (
- .TRACE_CLK(FTMD_TRACEIN_CLK),
- .RST(~FCLK_RESET0_N),
- .TRACE_VALID_IN(FTMD_TRACEIN_VALID),
- .TRACE_DATA_IN(FTMD_TRACEIN_DATA),
- .TRACE_ATID_IN(FTMD_TRACEIN_ATID),
- .TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
- .TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
- .TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
- );
-
- assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
- assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
- assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
-
- end
- end
- else
- begin
- assign FTMD_TRACEIN_DATA_i = 1'b0;
- assign FTMD_TRACEIN_VALID_i = 1'b0;
- assign FTMD_TRACEIN_ATID_i = 1'b0;
- end
-endgenerate
-
-
- // ID Width Control on AXI Slave ports
- // S_AXI_GP0
-
- function [5:0] id_in_gp0;
- input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
- begin
- case (C_S_AXI_GP0_ID_WIDTH)
- 1: id_in_gp0 = {5'b0, axi_id_gp0_in};
- 2: id_in_gp0 = {4'b0, axi_id_gp0_in};
- 3: id_in_gp0 = {3'b0, axi_id_gp0_in};
- 4: id_in_gp0 = {2'b0, axi_id_gp0_in};
- 5: id_in_gp0 = {1'b0, axi_id_gp0_in};
- 6: id_in_gp0 = axi_id_gp0_in;
- default : id_in_gp0 = axi_id_gp0_in;
- endcase
- end
- endfunction
-
- assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
- assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
- assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
-
- function [5:0] id_out_gp0;
- input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
- begin
- case (C_S_AXI_GP0_ID_WIDTH)
- 1: id_out_gp0 = axi_id_gp0_out[0];
- 2: id_out_gp0 = axi_id_gp0_out[1:0];
- 3: id_out_gp0 = axi_id_gp0_out[2:0];
- 4: id_out_gp0 = axi_id_gp0_out[3:0];
- 5: id_out_gp0 = axi_id_gp0_out[4:0];
- 6: id_out_gp0 = axi_id_gp0_out;
- default : id_out_gp0 = axi_id_gp0_out;
- endcase
- end
- endfunction
-
- assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
- assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
-
- // S_AXI_GP1
-
- function [5:0] id_in_gp1;
- input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
- begin
- case (C_S_AXI_GP1_ID_WIDTH)
- 1: id_in_gp1 = {5'b0, axi_id_gp1_in};
- 2: id_in_gp1 = {4'b0, axi_id_gp1_in};
- 3: id_in_gp1 = {3'b0, axi_id_gp1_in};
- 4: id_in_gp1 = {2'b0, axi_id_gp1_in};
- 5: id_in_gp1 = {1'b0, axi_id_gp1_in};
- 6: id_in_gp1 = axi_id_gp1_in;
- default : id_in_gp1 = axi_id_gp1_in;
- endcase
- end
- endfunction
-
- assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
- assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
- assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
-
- function [5:0] id_out_gp1;
- input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
- begin
- case (C_S_AXI_GP1_ID_WIDTH)
- 1: id_out_gp1 = axi_id_gp1_out[0];
- 2: id_out_gp1 = axi_id_gp1_out[1:0];
- 3: id_out_gp1 = axi_id_gp1_out[2:0];
- 4: id_out_gp1 = axi_id_gp1_out[3:0];
- 5: id_out_gp1 = axi_id_gp1_out[4:0];
- 6: id_out_gp1 = axi_id_gp1_out;
- default : id_out_gp1 = axi_id_gp1_out;
- endcase
- end
- endfunction
-
- assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
- assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
-
-// S_AXI_HP0
-
- function [5:0] id_in_hp0;
- input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
- begin
- case (C_S_AXI_HP0_ID_WIDTH)
- 1: id_in_hp0 = {5'b0, axi_id_hp0_in};
- 2: id_in_hp0 = {4'b0, axi_id_hp0_in};
- 3: id_in_hp0 = {3'b0, axi_id_hp0_in};
- 4: id_in_hp0 = {2'b0, axi_id_hp0_in};
- 5: id_in_hp0 = {1'b0, axi_id_hp0_in};
- 6: id_in_hp0 = axi_id_hp0_in;
- default : id_in_hp0 = axi_id_hp0_in;
- endcase
- end
- endfunction
-
- assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
- assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
- assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
-
- function [5:0] id_out_hp0;
- input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
- begin
- case (C_S_AXI_HP0_ID_WIDTH)
- 1: id_out_hp0 = axi_id_hp0_out[0];
- 2: id_out_hp0 = axi_id_hp0_out[1:0];
- 3: id_out_hp0 = axi_id_hp0_out[2:0];
- 4: id_out_hp0 = axi_id_hp0_out[3:0];
- 5: id_out_hp0 = axi_id_hp0_out[4:0];
- 6: id_out_hp0 = axi_id_hp0_out;
- default : id_out_hp0 = axi_id_hp0_out;
- endcase
- end
- endfunction
-
- assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
- assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
-
- assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
- assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
- assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
-
-// S_AXI_HP1
-
- function [5:0] id_in_hp1;
- input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
- begin
- case (C_S_AXI_HP1_ID_WIDTH)
- 1: id_in_hp1 = {5'b0, axi_id_hp1_in};
- 2: id_in_hp1 = {4'b0, axi_id_hp1_in};
- 3: id_in_hp1 = {3'b0, axi_id_hp1_in};
- 4: id_in_hp1 = {2'b0, axi_id_hp1_in};
- 5: id_in_hp1 = {1'b0, axi_id_hp1_in};
- 6: id_in_hp1 = axi_id_hp1_in;
- default : id_in_hp1 = axi_id_hp1_in;
- endcase
- end
- endfunction
-
-
-
- assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
- assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
- assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
-
- function [5:0] id_out_hp1;
- input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
- begin
- case (C_S_AXI_HP1_ID_WIDTH)
- 1: id_out_hp1 = axi_id_hp1_out[0];
- 2: id_out_hp1 = axi_id_hp1_out[1:0];
- 3: id_out_hp1 = axi_id_hp1_out[2:0];
- 4: id_out_hp1 = axi_id_hp1_out[3:0];
- 5: id_out_hp1 = axi_id_hp1_out[4:0];
- 6: id_out_hp1 = axi_id_hp1_out;
- default : id_out_hp1 = axi_id_hp1_out;
- endcase
- end
- endfunction
-
- assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
- assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
-
- assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
- assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
- assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
-
-
-// S_AXI_HP2
-
- function [5:0] id_in_hp2;
- input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
- begin
- case (C_S_AXI_HP2_ID_WIDTH)
- 1: id_in_hp2 = {5'b0, axi_id_hp2_in};
- 2: id_in_hp2 = {4'b0, axi_id_hp2_in};
- 3: id_in_hp2 = {3'b0, axi_id_hp2_in};
- 4: id_in_hp2 = {2'b0, axi_id_hp2_in};
- 5: id_in_hp2 = {1'b0, axi_id_hp2_in};
- 6: id_in_hp2 = axi_id_hp2_in;
- default : id_in_hp2 = axi_id_hp2_in;
- endcase
- end
- endfunction
-
- assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
- assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
- assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
-
-
- function [5:0] id_out_hp2;
- input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
- begin
- case (C_S_AXI_HP2_ID_WIDTH)
- 1: id_out_hp2 = axi_id_hp2_out[0];
- 2: id_out_hp2 = axi_id_hp2_out[1:0];
- 3: id_out_hp2 = axi_id_hp2_out[2:0];
- 4: id_out_hp2 = axi_id_hp2_out[3:0];
- 5: id_out_hp2 = axi_id_hp2_out[4:0];
- 6: id_out_hp2 = axi_id_hp2_out;
- default : id_out_hp2 = axi_id_hp2_out;
- endcase
- end
- endfunction
-
- assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
- assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
-
- assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
- assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
- assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
-
-
-// S_AXI_HP3
-
- function [5:0] id_in_hp3;
- input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
- begin
- case (C_S_AXI_HP3_ID_WIDTH)
- 1: id_in_hp3 = {5'b0, axi_id_hp3_in};
- 2: id_in_hp3 = {4'b0, axi_id_hp3_in};
- 3: id_in_hp3 = {3'b0, axi_id_hp3_in};
- 4: id_in_hp3 = {2'b0, axi_id_hp3_in};
- 5: id_in_hp3 = {1'b0, axi_id_hp3_in};
- 6: id_in_hp3 = axi_id_hp3_in;
- default : id_in_hp3 = axi_id_hp3_in;
- endcase
- end
- endfunction
-
- assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
- assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
- assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
-
-
-
- function [5:0] id_out_hp3;
- input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
- begin
- case (C_S_AXI_HP3_ID_WIDTH)
- 1: id_out_hp3 = axi_id_hp3_out[0];
- 2: id_out_hp3 = axi_id_hp3_out[1:0];
- 3: id_out_hp3 = axi_id_hp3_out[2:0];
- 4: id_out_hp3 = axi_id_hp3_out[3:0];
- 5: id_out_hp3 = axi_id_hp3_out[4:0];
- 6: id_out_hp3 = axi_id_hp3_out;
- default : id_out_hp3 = axi_id_hp3_out;
- endcase
- end
- endfunction
-
- assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
- assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
-
- assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
- assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
- assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
-
-
-// S_AXI_ACP
-
- function [2:0] id_in_acp;
- input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
- begin
- case (C_S_AXI_ACP_ID_WIDTH)
- 1: id_in_acp = {2'b0, axi_id_acp_in};
- 2: id_in_acp = {1'b0, axi_id_acp_in};
- 3: id_in_acp = axi_id_acp_in;
- default : id_in_acp = axi_id_acp_in;
- endcase
- end
- endfunction
-
- assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
- assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
- assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
-
- function [2:0] id_out_acp;
- input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
- begin
- case (C_S_AXI_ACP_ID_WIDTH)
- 1: id_out_acp = axi_id_acp_out[0];
- 2: id_out_acp = axi_id_acp_out[1:0];
- 3: id_out_acp = axi_id_acp_out;
- default : id_out_acp = axi_id_acp_out;
- endcase
- end
- endfunction
-
- assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
- assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
-
-// FMIO Tristate Inversion logic
-
-//FMIO I2C0
-assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
-assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
-//FMIO I2C1
-assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
-assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
-//FMIO SPI0
-assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
-assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
-assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
-assign SPI0_SS_T = ~ SPI0_SS_T_n;
-//FMIO SPI1
-assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
-assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
-assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
-assign SPI1_SS_T = ~ SPI1_SS_T_n;
-
-
-
-// EMIO GEM0 MDIO
-assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
-
-// EMIO GEM1 MDIO
-assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
-
-// EMIO GPIO
-assign GPIO_T = ~ GPIO_T_n;
-
-// EMIO GPIO Width Control
-
- function [63:0] gpio_width_adjust_in;
- input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
- begin
- case (C_EMIO_GPIO_WIDTH)
- 1: gpio_width_adjust_in = {63'b0, gpio_in};
- 2: gpio_width_adjust_in = {62'b0, gpio_in};
- 3: gpio_width_adjust_in = {61'b0, gpio_in};
- 4: gpio_width_adjust_in = {60'b0, gpio_in};
- 5: gpio_width_adjust_in = {59'b0, gpio_in};
- 6: gpio_width_adjust_in = {58'b0, gpio_in};
- 7: gpio_width_adjust_in = {57'b0, gpio_in};
- 8: gpio_width_adjust_in = {56'b0, gpio_in};
- 9: gpio_width_adjust_in = {55'b0, gpio_in};
- 10: gpio_width_adjust_in = {54'b0, gpio_in};
- 11: gpio_width_adjust_in = {53'b0, gpio_in};
- 12: gpio_width_adjust_in = {52'b0, gpio_in};
- 13: gpio_width_adjust_in = {51'b0, gpio_in};
- 14: gpio_width_adjust_in = {50'b0, gpio_in};
- 15: gpio_width_adjust_in = {49'b0, gpio_in};
- 16: gpio_width_adjust_in = {48'b0, gpio_in};
- 17: gpio_width_adjust_in = {47'b0, gpio_in};
- 18: gpio_width_adjust_in = {46'b0, gpio_in};
- 19: gpio_width_adjust_in = {45'b0, gpio_in};
- 20: gpio_width_adjust_in = {44'b0, gpio_in};
- 21: gpio_width_adjust_in = {43'b0, gpio_in};
- 22: gpio_width_adjust_in = {42'b0, gpio_in};
- 23: gpio_width_adjust_in = {41'b0, gpio_in};
- 24: gpio_width_adjust_in = {40'b0, gpio_in};
- 25: gpio_width_adjust_in = {39'b0, gpio_in};
- 26: gpio_width_adjust_in = {38'b0, gpio_in};
- 27: gpio_width_adjust_in = {37'b0, gpio_in};
- 28: gpio_width_adjust_in = {36'b0, gpio_in};
- 29: gpio_width_adjust_in = {35'b0, gpio_in};
- 30: gpio_width_adjust_in = {34'b0, gpio_in};
- 31: gpio_width_adjust_in = {33'b0, gpio_in};
- 32: gpio_width_adjust_in = {32'b0, gpio_in};
- 33: gpio_width_adjust_in = {31'b0, gpio_in};
- 34: gpio_width_adjust_in = {30'b0, gpio_in};
- 35: gpio_width_adjust_in = {29'b0, gpio_in};
- 36: gpio_width_adjust_in = {28'b0, gpio_in};
- 37: gpio_width_adjust_in = {27'b0, gpio_in};
- 38: gpio_width_adjust_in = {26'b0, gpio_in};
- 39: gpio_width_adjust_in = {25'b0, gpio_in};
- 40: gpio_width_adjust_in = {24'b0, gpio_in};
- 41: gpio_width_adjust_in = {23'b0, gpio_in};
- 42: gpio_width_adjust_in = {22'b0, gpio_in};
- 43: gpio_width_adjust_in = {21'b0, gpio_in};
- 44: gpio_width_adjust_in = {20'b0, gpio_in};
- 45: gpio_width_adjust_in = {19'b0, gpio_in};
- 46: gpio_width_adjust_in = {18'b0, gpio_in};
- 47: gpio_width_adjust_in = {17'b0, gpio_in};
- 48: gpio_width_adjust_in = {16'b0, gpio_in};
- 49: gpio_width_adjust_in = {15'b0, gpio_in};
- 50: gpio_width_adjust_in = {14'b0, gpio_in};
- 51: gpio_width_adjust_in = {13'b0, gpio_in};
- 52: gpio_width_adjust_in = {12'b0, gpio_in};
- 53: gpio_width_adjust_in = {11'b0, gpio_in};
- 54: gpio_width_adjust_in = {10'b0, gpio_in};
- 55: gpio_width_adjust_in = {9'b0, gpio_in};
- 56: gpio_width_adjust_in = {8'b0, gpio_in};
- 57: gpio_width_adjust_in = {7'b0, gpio_in};
- 58: gpio_width_adjust_in = {6'b0, gpio_in};
- 59: gpio_width_adjust_in = {5'b0, gpio_in};
- 60: gpio_width_adjust_in = {4'b0, gpio_in};
- 61: gpio_width_adjust_in = {3'b0, gpio_in};
- 62: gpio_width_adjust_in = {2'b0, gpio_in};
- 63: gpio_width_adjust_in = {1'b0, gpio_in};
- 64: gpio_width_adjust_in = gpio_in;
- default : gpio_width_adjust_in = gpio_in;
- endcase
- end
- endfunction
-
- assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
-
-
- function [63:0] gpio_width_adjust_out;
- input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
- begin
- case (C_EMIO_GPIO_WIDTH)
- 1: gpio_width_adjust_out = gpio_o[0];
- 2: gpio_width_adjust_out = gpio_o[1:0];
- 3: gpio_width_adjust_out = gpio_o[2:0];
- 4: gpio_width_adjust_out = gpio_o[3:0];
- 5: gpio_width_adjust_out = gpio_o[4:0];
- 6: gpio_width_adjust_out = gpio_o[5:0];
- 7: gpio_width_adjust_out = gpio_o[6:0];
- 8: gpio_width_adjust_out = gpio_o[7:0];
- 9: gpio_width_adjust_out = gpio_o[8:0];
- 10: gpio_width_adjust_out = gpio_o[9:0];
- 11: gpio_width_adjust_out = gpio_o[10:0];
- 12: gpio_width_adjust_out = gpio_o[11:0];
- 13: gpio_width_adjust_out = gpio_o[12:0];
- 14: gpio_width_adjust_out = gpio_o[13:0];
- 15: gpio_width_adjust_out = gpio_o[14:0];
- 16: gpio_width_adjust_out = gpio_o[15:0];
- 17: gpio_width_adjust_out = gpio_o[16:0];
- 18: gpio_width_adjust_out = gpio_o[17:0];
- 19: gpio_width_adjust_out = gpio_o[18:0];
- 20: gpio_width_adjust_out = gpio_o[19:0];
- 21: gpio_width_adjust_out = gpio_o[20:0];
- 22: gpio_width_adjust_out = gpio_o[21:0];
- 23: gpio_width_adjust_out = gpio_o[22:0];
- 24: gpio_width_adjust_out = gpio_o[23:0];
- 25: gpio_width_adjust_out = gpio_o[24:0];
- 26: gpio_width_adjust_out = gpio_o[25:0];
- 27: gpio_width_adjust_out = gpio_o[26:0];
- 28: gpio_width_adjust_out = gpio_o[27:0];
- 29: gpio_width_adjust_out = gpio_o[28:0];
- 30: gpio_width_adjust_out = gpio_o[29:0];
- 31: gpio_width_adjust_out = gpio_o[30:0];
- 32: gpio_width_adjust_out = gpio_o[31:0];
- 33: gpio_width_adjust_out = gpio_o[32:0];
- 34: gpio_width_adjust_out = gpio_o[33:0];
- 35: gpio_width_adjust_out = gpio_o[34:0];
- 36: gpio_width_adjust_out = gpio_o[35:0];
- 37: gpio_width_adjust_out = gpio_o[36:0];
- 38: gpio_width_adjust_out = gpio_o[37:0];
- 39: gpio_width_adjust_out = gpio_o[38:0];
- 40: gpio_width_adjust_out = gpio_o[39:0];
- 41: gpio_width_adjust_out = gpio_o[40:0];
- 42: gpio_width_adjust_out = gpio_o[41:0];
- 43: gpio_width_adjust_out = gpio_o[42:0];
- 44: gpio_width_adjust_out = gpio_o[43:0];
- 45: gpio_width_adjust_out = gpio_o[44:0];
- 46: gpio_width_adjust_out = gpio_o[45:0];
- 47: gpio_width_adjust_out = gpio_o[46:0];
- 48: gpio_width_adjust_out = gpio_o[47:0];
- 49: gpio_width_adjust_out = gpio_o[48:0];
- 50: gpio_width_adjust_out = gpio_o[49:0];
- 51: gpio_width_adjust_out = gpio_o[50:0];
- 52: gpio_width_adjust_out = gpio_o[51:0];
- 53: gpio_width_adjust_out = gpio_o[52:0];
- 54: gpio_width_adjust_out = gpio_o[53:0];
- 55: gpio_width_adjust_out = gpio_o[54:0];
- 56: gpio_width_adjust_out = gpio_o[55:0];
- 57: gpio_width_adjust_out = gpio_o[56:0];
- 58: gpio_width_adjust_out = gpio_o[57:0];
- 59: gpio_width_adjust_out = gpio_o[58:0];
- 60: gpio_width_adjust_out = gpio_o[59:0];
- 61: gpio_width_adjust_out = gpio_o[60:0];
- 62: gpio_width_adjust_out = gpio_o[61:0];
- 63: gpio_width_adjust_out = gpio_o[62:0];
- 64: gpio_width_adjust_out = gpio_o;
- default : gpio_width_adjust_out = gpio_o;
- endcase
- end
- endfunction
-
- assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
- assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
-
-// Adding OBUFT to JTAG out port
-generate
- if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
- OBUFT jtag_obuft_inst (
- .O(PJTAG_TDO),
- .I(PJTAG_TDO_O),
- .T(PJTAG_TDO_T)
- );
- end
- else
- begin
- assign PJTAG_TDO = 1'b0;
- end
-endgenerate
-// -------
-// EMIO PJTAG
-assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
-
-// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
-// FOR Other SI REV, inversion is required
-
-assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
-assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
-
-// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
-// FOR Other SI REV, inversion is required
-assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
-assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
-
-// FCLK_CLK optional clock buffers
-
-generate
- if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
- BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
- end
- if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
- BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
- end
- if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
- BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
- end
- if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
- BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
- end
-endgenerate
-
-assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
-assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
-assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
-assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
-
-assign FCLK_CLK0 = FCLK_CLK0_temp;
-
-// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
-
-BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
-BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
-BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
-BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
-BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
-BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
-BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
-BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
-BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
-BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
-BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
-BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
-BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
-BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
-
-genvar i;
-generate
- for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
- BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
- end
-endgenerate
-
-generate
- for (i=0; i < 3; i=i+1) begin
- BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
- end
-endgenerate
-
-generate
- for (i=0; i < 15; i=i+1) begin
- BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
- end
-endgenerate
-
-generate
- for (i=0; i < C_DM_WIDTH; i=i+1) begin
- BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
- end
-endgenerate
-
-generate
- for (i=0; i < C_DQ_WIDTH; i=i+1) begin
- BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
- end
-endgenerate
-
-generate
- for (i=0; i < C_DQS_WIDTH; i=i+1) begin
- BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
- end
-endgenerate
-
-generate
- for (i=0; i < C_DQS_WIDTH; i=i+1) begin
- BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
- end
-endgenerate
-
-// Connect FCLK in case of disable the AXI port for non Secure Transaction
-//Start
-
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
- assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
- end
-endgenerate
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
- assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
- end
-endgenerate
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
- assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
- end
-endgenerate
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
- assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
- end
-endgenerate
-
-//Start
-
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
- assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
- end
-endgenerate
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
- assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
- end
-endgenerate
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
- assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
- end
-endgenerate
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
- assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
- end
-endgenerate
-
-generate
- if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
- assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
- end
- else begin
- assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
- end
-endgenerate
-
-assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ;
-assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ;
-assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ;
-assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ;
-
-
-//END
-//====================
-//PSS TOP
-//====================
-generate
-if (C_PACKAGE_NAME == "clg225" ) begin
- wire [21:0] dummy;
- PS7 PS7_i (
- .DMA0DATYPE (DMA0_DATYPE ),
- .DMA0DAVALID (DMA0_DAVALID),
- .DMA0DRREADY (DMA0_DRREADY),
- .DMA0RSTN (DMA0_RSTN ),
- .DMA1DATYPE (DMA1_DATYPE ),
- .DMA1DAVALID (DMA1_DAVALID),
- .DMA1DRREADY (DMA1_DRREADY),
- .DMA1RSTN (DMA1_RSTN ),
- .DMA2DATYPE (DMA2_DATYPE ),
- .DMA2DAVALID (DMA2_DAVALID),
- .DMA2DRREADY (DMA2_DRREADY),
- .DMA2RSTN (DMA2_RSTN ),
- .DMA3DATYPE (DMA3_DATYPE ),
- .DMA3DAVALID (DMA3_DAVALID),
- .DMA3DRREADY (DMA3_DRREADY),
- .DMA3RSTN (DMA3_RSTN ),
- .EMIOCAN0PHYTX (CAN0_PHY_TX ),
- .EMIOCAN1PHYTX (CAN1_PHY_TX ),
- .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
- .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
- .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
- .EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
- .EMIOENET0MDIOO (ENET0_MDIO_O ),
- .EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
- .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
- .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
- .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
- .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
- .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
- .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
- .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
- .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
- .EMIOENET0SOFRX (ENET0_SOF_RX),
- .EMIOENET0SOFTX (ENET0_SOF_TX),
- .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
- .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
- .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
- .EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
- .EMIOENET1MDIOO (ENET1_MDIO_O),
- .EMIOENET1MDIOTN (ENET1_MDIO_T_n),
- .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
- .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
- .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
- .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
- .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
- .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
- .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
- .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
- .EMIOENET1SOFRX (ENET1_SOF_RX),
- .EMIOENET1SOFTX (ENET1_SOF_TX),
- .EMIOGPIOO (gpio_out),
- .EMIOGPIOTN (gpio_out_t_n),
- .EMIOI2C0SCLO (I2C0_SCL_O),
- .EMIOI2C0SCLTN (I2C0_SCL_T_n),
- .EMIOI2C0SDAO (I2C0_SDA_O),
- .EMIOI2C0SDATN (I2C0_SDA_T_n),
- .EMIOI2C1SCLO (I2C1_SCL_O),
- .EMIOI2C1SCLTN (I2C1_SCL_T_n),
- .EMIOI2C1SDAO (I2C1_SDA_O),
- .EMIOI2C1SDATN (I2C1_SDA_T_n),
- .EMIOPJTAGTDO (PJTAG_TDO_O),
- .EMIOPJTAGTDTN (PJTAG_TDO_T_n),
- .EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
- .EMIOSDIO0CLK (SDIO0_CLK ),
- .EMIOSDIO0CMDO (SDIO0_CMD_O ),
- .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
- .EMIOSDIO0DATAO (SDIO0_DATA_O),
- .EMIOSDIO0DATATN (SDIO0_DATA_T_n),
- .EMIOSDIO0LED (SDIO0_LED),
- .EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
- .EMIOSDIO1CLK (SDIO1_CLK ),
- .EMIOSDIO1CMDO (SDIO1_CMD_O ),
- .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
- .EMIOSDIO1DATAO (SDIO1_DATA_O),
- .EMIOSDIO1DATATN (SDIO1_DATA_T_n),
- .EMIOSDIO1LED (SDIO1_LED),
- .EMIOSPI0MO (SPI0_MOSI_O),
- .EMIOSPI0MOTN (SPI0_MOSI_T_n),
- .EMIOSPI0SCLKO (SPI0_SCLK_O),
- .EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
- .EMIOSPI0SO (SPI0_MISO_O),
- .EMIOSPI0STN (SPI0_MISO_T_n),
- .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
- .EMIOSPI0SSNTN (SPI0_SS_T_n),
- .EMIOSPI1MO (SPI1_MOSI_O),
- .EMIOSPI1MOTN (SPI1_MOSI_T_n),
- .EMIOSPI1SCLKO (SPI1_SCLK_O),
- .EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
- .EMIOSPI1SO (SPI1_MISO_O),
- .EMIOSPI1STN (SPI1_MISO_T_n),
- .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
- .EMIOSPI1SSNTN (SPI1_SS_T_n),
- .EMIOTRACECTL (TRACE_CTL_i),
- .EMIOTRACEDATA (TRACE_DATA_i),
- .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
- .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
- .EMIOUART0DTRN (UART0_DTRN),
- .EMIOUART0RTSN (UART0_RTSN),
- .EMIOUART0TX (UART0_TX ),
- .EMIOUART1DTRN (UART1_DTRN),
- .EMIOUART1RTSN (UART1_RTSN),
- .EMIOUART1TX (UART1_TX ),
- .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
- .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
- .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
- .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
- .EMIOWDTRSTO (WDT_RST_OUT),
- .EVENTEVENTO (EVENT_EVENTO),
- .EVENTSTANDBYWFE (EVENT_STANDBYWFE),
- .EVENTSTANDBYWFI (EVENT_STANDBYWFI),
- .FCLKCLK (FCLK_CLK_unbuffered),
- .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
- .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
- .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
- .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
- .FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
- .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
- .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
- .MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
- .MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
- .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
- .MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
- .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
- .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
- .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
- .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
- .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
- .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
- .MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
- .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
- .MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
- .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
- .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
- .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
- .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
- .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
- .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
- .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
- .MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
- .MAXIGP0BREADY (M_AXI_GP0_BREADY ),
- .MAXIGP0RREADY (M_AXI_GP0_RREADY ),
- .MAXIGP0WDATA (M_AXI_GP0_WDATA ),
- .MAXIGP0WID (M_AXI_GP0_WID_FULL ),
- .MAXIGP0WLAST (M_AXI_GP0_WLAST ),
- .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
- .MAXIGP0WVALID (M_AXI_GP0_WVALID ),
- .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
- .MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
- .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
- .MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
- .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
- .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
- .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
- .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
- .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
- .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
- .MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
- .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
- .MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
- .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
- .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
- .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
- .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
- .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
- .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
- .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
- .MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
- .MAXIGP1BREADY (M_AXI_GP1_BREADY ),
- .MAXIGP1RREADY (M_AXI_GP1_RREADY ),
- .MAXIGP1WDATA (M_AXI_GP1_WDATA ),
- .MAXIGP1WID (M_AXI_GP1_WID_FULL ),
- .MAXIGP1WLAST (M_AXI_GP1_WLAST ),
- .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
- .MAXIGP1WVALID (M_AXI_GP1_WVALID ),
- .SAXIACPARESETN (S_AXI_ACP_ARESETN),
- .SAXIACPARREADY (SAXIACPARREADY_W),
- .SAXIACPAWREADY (SAXIACPAWREADY_W),
- .SAXIACPBID (S_AXI_ACP_BID_out ),
- .SAXIACPBRESP (SAXIACPBRESP_W ),
- .SAXIACPBVALID (SAXIACPBVALID_W ),
- .SAXIACPRDATA (SAXIACPRDATA_W ),
- .SAXIACPRID (S_AXI_ACP_RID_out),
- .SAXIACPRLAST (SAXIACPRLAST_W ),
- .SAXIACPRRESP (SAXIACPRRESP_W ),
- .SAXIACPRVALID (SAXIACPRVALID_W ),
- .SAXIACPWREADY (SAXIACPWREADY_W ),
- .SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
- .SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
- .SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
- .SAXIGP0BID (S_AXI_GP0_BID_out),
- .SAXIGP0BRESP (S_AXI_GP0_BRESP ),
- .SAXIGP0BVALID (S_AXI_GP0_BVALID ),
- .SAXIGP0RDATA (S_AXI_GP0_RDATA ),
- .SAXIGP0RID (S_AXI_GP0_RID_out ),
- .SAXIGP0RLAST (S_AXI_GP0_RLAST ),
- .SAXIGP0RRESP (S_AXI_GP0_RRESP ),
- .SAXIGP0RVALID (S_AXI_GP0_RVALID ),
- .SAXIGP0WREADY (S_AXI_GP0_WREADY ),
- .SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
- .SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
- .SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
- .SAXIGP1BID (S_AXI_GP1_BID_out ),
- .SAXIGP1BRESP (S_AXI_GP1_BRESP ),
- .SAXIGP1BVALID (S_AXI_GP1_BVALID ),
- .SAXIGP1RDATA (S_AXI_GP1_RDATA ),
- .SAXIGP1RID (S_AXI_GP1_RID_out ),
- .SAXIGP1RLAST (S_AXI_GP1_RLAST ),
- .SAXIGP1RRESP (S_AXI_GP1_RRESP ),
- .SAXIGP1RVALID (S_AXI_GP1_RVALID ),
- .SAXIGP1WREADY (S_AXI_GP1_WREADY ),
- .SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
- .SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
- .SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
- .SAXIHP0BID (S_AXI_HP0_BID_out ),
- .SAXIHP0BRESP (S_AXI_HP0_BRESP ),
- .SAXIHP0BVALID (S_AXI_HP0_BVALID ),
- .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
- .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
- .SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
- .SAXIHP0RID (S_AXI_HP0_RID_out ),
- .SAXIHP0RLAST (S_AXI_HP0_RLAST),
- .SAXIHP0RRESP (S_AXI_HP0_RRESP),
- .SAXIHP0RVALID (S_AXI_HP0_RVALID),
- .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
- .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
- .SAXIHP0WREADY (S_AXI_HP0_WREADY),
- .SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
- .SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
- .SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
- .SAXIHP1BID (S_AXI_HP1_BID_out ),
- .SAXIHP1BRESP (S_AXI_HP1_BRESP ),
- .SAXIHP1BVALID (S_AXI_HP1_BVALID ),
- .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
- .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
- .SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
- .SAXIHP1RID (S_AXI_HP1_RID_out ),
- .SAXIHP1RLAST (S_AXI_HP1_RLAST ),
- .SAXIHP1RRESP (S_AXI_HP1_RRESP ),
- .SAXIHP1RVALID (S_AXI_HP1_RVALID),
- .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
- .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
- .SAXIHP1WREADY (S_AXI_HP1_WREADY),
- .SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
- .SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
- .SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
- .SAXIHP2BID (S_AXI_HP2_BID_out ),
- .SAXIHP2BRESP (S_AXI_HP2_BRESP),
- .SAXIHP2BVALID (S_AXI_HP2_BVALID),
- .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
- .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
- .SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
- .SAXIHP2RID (S_AXI_HP2_RID_out ),
- .SAXIHP2RLAST (S_AXI_HP2_RLAST),
- .SAXIHP2RRESP (S_AXI_HP2_RRESP),
- .SAXIHP2RVALID (S_AXI_HP2_RVALID),
- .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
- .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
- .SAXIHP2WREADY (S_AXI_HP2_WREADY),
- .SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
- .SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
- .SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
- .SAXIHP3BID (S_AXI_HP3_BID_out),
- .SAXIHP3BRESP (S_AXI_HP3_BRESP),
- .SAXIHP3BVALID (S_AXI_HP3_BVALID),
- .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
- .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
- .SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
- .SAXIHP3RID (S_AXI_HP3_RID_out),
- .SAXIHP3RLAST (S_AXI_HP3_RLAST),
- .SAXIHP3RRESP (S_AXI_HP3_RRESP),
- .SAXIHP3RVALID (S_AXI_HP3_RVALID),
- .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
- .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
- .SAXIHP3WREADY (S_AXI_HP3_WREADY),
- .DDRARB (DDR_ARB),
- .DMA0ACLK (DMA0_ACLK ),
- .DMA0DAREADY (DMA0_DAREADY),
- .DMA0DRLAST (DMA0_DRLAST ),
- .DMA0DRTYPE (DMA0_DRTYPE),
- .DMA0DRVALID (DMA0_DRVALID),
- .DMA1ACLK (DMA1_ACLK ),
- .DMA1DAREADY (DMA1_DAREADY),
- .DMA1DRLAST (DMA1_DRLAST ),
- .DMA1DRTYPE (DMA1_DRTYPE),
- .DMA1DRVALID (DMA1_DRVALID),
- .DMA2ACLK (DMA2_ACLK ),
- .DMA2DAREADY (DMA2_DAREADY),
- .DMA2DRLAST (DMA2_DRLAST ),
- .DMA2DRTYPE (DMA2_DRTYPE),
- .DMA2DRVALID (DMA2_DRVALID),
- .DMA3ACLK (DMA3_ACLK ),
- .DMA3DAREADY (DMA3_DAREADY),
- .DMA3DRLAST (DMA3_DRLAST ),
- .DMA3DRTYPE (DMA3_DRTYPE),
- .DMA3DRVALID (DMA3_DRVALID),
- .EMIOCAN0PHYRX (CAN0_PHY_RX),
- .EMIOCAN1PHYRX (CAN1_PHY_RX),
- .EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
- .EMIOENET0GMIICOL (ENET0_GMII_COL_i),
- .EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
- .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
- .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
- .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
- .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
- .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
- .EMIOENET0MDIOI (ENET0_MDIO_I),
- .EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
- .EMIOENET1GMIICOL (ENET1_GMII_COL_i),
- .EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
- .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
- .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
- .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
- .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
- .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
- .EMIOENET1MDIOI (ENET1_MDIO_I),
- .EMIOGPIOI (gpio_in63_0 ),
- .EMIOI2C0SCLI (I2C0_SCL_I),
- .EMIOI2C0SDAI (I2C0_SDA_I),
- .EMIOI2C1SCLI (I2C1_SCL_I),
- .EMIOI2C1SDAI (I2C1_SDA_I),
- .EMIOPJTAGTCK (PJTAG_TCK),
- .EMIOPJTAGTDI (PJTAG_TDI),
- .EMIOPJTAGTMS (PJTAG_TMS),
- .EMIOSDIO0CDN (SDIO0_CDN),
- .EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
- .EMIOSDIO0CMDI (SDIO0_CMD_I ),
- .EMIOSDIO0DATAI (SDIO0_DATA_I ),
- .EMIOSDIO0WP (SDIO0_WP),
- .EMIOSDIO1CDN (SDIO1_CDN),
- .EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
- .EMIOSDIO1CMDI (SDIO1_CMD_I ),
- .EMIOSDIO1DATAI (SDIO1_DATA_I ),
- .EMIOSDIO1WP (SDIO1_WP),
- .EMIOSPI0MI (SPI0_MISO_I),
- .EMIOSPI0SCLKI (SPI0_SCLK_I),
- .EMIOSPI0SI (SPI0_MOSI_I),
- .EMIOSPI0SSIN (SPI0_SS_I),
- .EMIOSPI1MI (SPI1_MISO_I),
- .EMIOSPI1SCLKI (SPI1_SCLK_I),
- .EMIOSPI1SI (SPI1_MOSI_I),
- .EMIOSPI1SSIN (SPI1_SS_I),
- .EMIOSRAMINTIN (SRAM_INTIN),
- .EMIOTRACECLK (TRACE_CLK),
- .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
- .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
- .EMIOUART0CTSN (UART0_CTSN),
- .EMIOUART0DCDN (UART0_DCDN),
- .EMIOUART0DSRN (UART0_DSRN),
- .EMIOUART0RIN (UART0_RIN ),
- .EMIOUART0RX (UART0_RX ),
- .EMIOUART1CTSN (UART1_CTSN),
- .EMIOUART1DCDN (UART1_DCDN),
- .EMIOUART1DSRN (UART1_DSRN),
- .EMIOUART1RIN (UART1_RIN ),
- .EMIOUART1RX (UART1_RX ),
- .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
- .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
- .EMIOWDTCLKI (WDT_CLK_IN),
- .EVENTEVENTI (EVENT_EVENTI),
- .FCLKCLKTRIGN (fclk_clktrig_gnd),
- .FPGAIDLEN (FPGA_IDLE_N),
- .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
- .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
- .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
- .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
- .FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
- .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
- .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
- .IRQF2P (irq_f2p_i),
- .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
- .MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
- .MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
- .MAXIGP0BID (M_AXI_GP0_BID_FULL ),
- .MAXIGP0BRESP (M_AXI_GP0_BRESP ),
- .MAXIGP0BVALID (M_AXI_GP0_BVALID ),
- .MAXIGP0RDATA (M_AXI_GP0_RDATA ),
- .MAXIGP0RID (M_AXI_GP0_RID_FULL ),
- .MAXIGP0RLAST (M_AXI_GP0_RLAST ),
- .MAXIGP0RRESP (M_AXI_GP0_RRESP ),
- .MAXIGP0RVALID (M_AXI_GP0_RVALID ),
- .MAXIGP0WREADY (M_AXI_GP0_WREADY ),
- .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
- .MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
- .MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
- .MAXIGP1BID (M_AXI_GP1_BID_FULL ),
- .MAXIGP1BRESP (M_AXI_GP1_BRESP ),
- .MAXIGP1BVALID (M_AXI_GP1_BVALID ),
- .MAXIGP1RDATA (M_AXI_GP1_RDATA ),
- .MAXIGP1RID (M_AXI_GP1_RID_FULL ),
- .MAXIGP1RLAST (M_AXI_GP1_RLAST ),
- .MAXIGP1RRESP (M_AXI_GP1_RRESP ),
- .MAXIGP1RVALID (M_AXI_GP1_RVALID ),
- .MAXIGP1WREADY (M_AXI_GP1_WREADY ),
- .SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
- .SAXIACPARADDR (SAXIACPARADDR_W ),
- .SAXIACPARBURST (SAXIACPARBURST_W),
- .SAXIACPARCACHE (SAXIACPARCACHE_W),
- .SAXIACPARID (S_AXI_ACP_ARID_in ),
- .SAXIACPARLEN (SAXIACPARLEN_W ),
- .SAXIACPARLOCK (SAXIACPARLOCK_W ),
- .SAXIACPARPROT (SAXIACPARPROT_W ),
- .SAXIACPARQOS (S_AXI_ACP_ARQOS ),
- .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
- .SAXIACPARUSER (SAXIACPARUSER_W ),
- .SAXIACPARVALID (SAXIACPARVALID_W),
- .SAXIACPAWADDR (SAXIACPAWADDR_W ),
- .SAXIACPAWBURST (SAXIACPAWBURST_W),
- .SAXIACPAWCACHE (SAXIACPAWCACHE_W),
- .SAXIACPAWID (S_AXI_ACP_AWID_in ),
- .SAXIACPAWLEN (SAXIACPAWLEN_W ),
- .SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
- .SAXIACPAWPROT (SAXIACPAWPROT_W ),
- .SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
- .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
- .SAXIACPAWUSER (SAXIACPAWUSER_W ),
- .SAXIACPAWVALID (SAXIACPAWVALID_W),
- .SAXIACPBREADY (SAXIACPBREADY_W ),
- .SAXIACPRREADY (SAXIACPRREADY_W ),
- .SAXIACPWDATA (SAXIACPWDATA_W ),
- .SAXIACPWID (S_AXI_ACP_WID_in ),
- .SAXIACPWLAST (SAXIACPWLAST_W ),
- .SAXIACPWSTRB (SAXIACPWSTRB_W ),
- .SAXIACPWVALID (SAXIACPWVALID_W ),
- .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
- .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
- .SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
- .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
- .SAXIGP0ARID (S_AXI_GP0_ARID_in ),
- .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
- .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
- .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
- .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
- .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
- .SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
- .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
- .SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
- .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
- .SAXIGP0AWID (S_AXI_GP0_AWID_in ),
- .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
- .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
- .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
- .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
- .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
- .SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
- .SAXIGP0BREADY (S_AXI_GP0_BREADY ),
- .SAXIGP0RREADY (S_AXI_GP0_RREADY ),
- .SAXIGP0WDATA (S_AXI_GP0_WDATA ),
- .SAXIGP0WID (S_AXI_GP0_WID_in ),
- .SAXIGP0WLAST (S_AXI_GP0_WLAST ),
- .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
- .SAXIGP0WVALID (S_AXI_GP0_WVALID ),
- .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
- .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
- .SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
- .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
- .SAXIGP1ARID (S_AXI_GP1_ARID_in ),
- .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
- .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
- .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
- .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
- .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
- .SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
- .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
- .SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
- .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
- .SAXIGP1AWID (S_AXI_GP1_AWID_in ),
- .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
- .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
- .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
- .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
- .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
- .SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
- .SAXIGP1BREADY (S_AXI_GP1_BREADY ),
- .SAXIGP1RREADY (S_AXI_GP1_RREADY ),
- .SAXIGP1WDATA (S_AXI_GP1_WDATA ),
- .SAXIGP1WID (S_AXI_GP1_WID_in ),
- .SAXIGP1WLAST (S_AXI_GP1_WLAST ),
- .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
- .SAXIGP1WVALID (S_AXI_GP1_WVALID ),
- .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
- .SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
- .SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
- .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
- .SAXIHP0ARID (S_AXI_HP0_ARID_in),
- .SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
- .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
- .SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
- .SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
- .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
- .SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
- .SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
- .SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
- .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
- .SAXIHP0AWID (S_AXI_HP0_AWID_in),
- .SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
- .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
- .SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
- .SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
- .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
- .SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
- .SAXIHP0BREADY (S_AXI_HP0_BREADY),
- .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
- .SAXIHP0RREADY (S_AXI_HP0_RREADY),
- .SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
- .SAXIHP0WID (S_AXI_HP0_WID_in),
- .SAXIHP0WLAST (S_AXI_HP0_WLAST),
- .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
- .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
- .SAXIHP0WVALID (S_AXI_HP0_WVALID),
- .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
- .SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
- .SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
- .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
- .SAXIHP1ARID (S_AXI_HP1_ARID_in),
- .SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
- .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
- .SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
- .SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
- .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
- .SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
- .SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
- .SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
- .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
- .SAXIHP1AWID (S_AXI_HP1_AWID_in),
- .SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
- .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
- .SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
- .SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
- .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
- .SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
- .SAXIHP1BREADY (S_AXI_HP1_BREADY),
- .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
- .SAXIHP1RREADY (S_AXI_HP1_RREADY),
- .SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
- .SAXIHP1WID (S_AXI_HP1_WID_in),
- .SAXIHP1WLAST (S_AXI_HP1_WLAST),
- .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
- .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
- .SAXIHP1WVALID (S_AXI_HP1_WVALID),
- .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
- .SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
- .SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
- .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
- .SAXIHP2ARID (S_AXI_HP2_ARID_in),
- .SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
- .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
- .SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
- .SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
- .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
- .SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
- .SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
- .SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
- .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
- .SAXIHP2AWID (S_AXI_HP2_AWID_in),
- .SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
- .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
- .SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
- .SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
- .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
- .SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
- .SAXIHP2BREADY (S_AXI_HP2_BREADY),
- .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
- .SAXIHP2RREADY (S_AXI_HP2_RREADY),
- .SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
- .SAXIHP2WID (S_AXI_HP2_WID_in),
- .SAXIHP2WLAST (S_AXI_HP2_WLAST),
- .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
- .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
- .SAXIHP2WVALID (S_AXI_HP2_WVALID),
- .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
- .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
- .SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
- .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
- .SAXIHP3ARID (S_AXI_HP3_ARID_in ),
- .SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
- .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
- .SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
- .SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
- .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
- .SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
- .SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
- .SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
- .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
- .SAXIHP3AWID (S_AXI_HP3_AWID_in),
- .SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
- .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
- .SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
- .SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
- .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
- .SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
- .SAXIHP3BREADY (S_AXI_HP3_BREADY),
- .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
- .SAXIHP3RREADY (S_AXI_HP3_RREADY),
- .SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
- .SAXIHP3WID (S_AXI_HP3_WID_in),
- .SAXIHP3WLAST (S_AXI_HP3_WLAST),
- .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
- .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
- .SAXIHP3WVALID (S_AXI_HP3_WVALID),
- .DDRA (buffered_DDR_Addr),
- .DDRBA (buffered_DDR_BankAddr),
- .DDRCASB (buffered_DDR_CAS_n),
- .DDRCKE (buffered_DDR_CKE),
- .DDRCKN (buffered_DDR_Clk_n),
- .DDRCKP (buffered_DDR_Clk),
- .DDRCSB (buffered_DDR_CS_n),
- .DDRDM (buffered_DDR_DM),
- .DDRDQ (buffered_DDR_DQ),
- .DDRDQSN (buffered_DDR_DQS_n),
- .DDRDQSP (buffered_DDR_DQS),
- .DDRDRSTB (buffered_DDR_DRSTB),
- .DDRODT (buffered_DDR_ODT),
- .DDRRASB (buffered_DDR_RAS_n),
- .DDRVRN (buffered_DDR_VRN),
- .DDRVRP (buffered_DDR_VRP),
- .DDRWEB (buffered_DDR_WEB),
- .MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
- .PSCLK (buffered_PS_CLK),
- .PSPORB (buffered_PS_PORB),
- .PSSRSTB (buffered_PS_SRSTB)
-
-
-);
- end
- else begin
- PS7 PS7_i (
- .DMA0DATYPE (DMA0_DATYPE ),
- .DMA0DAVALID (DMA0_DAVALID),
- .DMA0DRREADY (DMA0_DRREADY),
- .DMA0RSTN (DMA0_RSTN ),
- .DMA1DATYPE (DMA1_DATYPE ),
- .DMA1DAVALID (DMA1_DAVALID),
- .DMA1DRREADY (DMA1_DRREADY),
- .DMA1RSTN (DMA1_RSTN ),
- .DMA2DATYPE (DMA2_DATYPE ),
- .DMA2DAVALID (DMA2_DAVALID),
- .DMA2DRREADY (DMA2_DRREADY),
- .DMA2RSTN (DMA2_RSTN ),
- .DMA3DATYPE (DMA3_DATYPE ),
- .DMA3DAVALID (DMA3_DAVALID),
- .DMA3DRREADY (DMA3_DRREADY),
- .DMA3RSTN (DMA3_RSTN ),
- .EMIOCAN0PHYTX (CAN0_PHY_TX ),
- .EMIOCAN1PHYTX (CAN1_PHY_TX ),
- .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
- .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
- .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
- .EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
- .EMIOENET0MDIOO (ENET0_MDIO_O ),
- .EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
- .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
- .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
- .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
- .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
- .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
- .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
- .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
- .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
- .EMIOENET0SOFRX (ENET0_SOF_RX),
- .EMIOENET0SOFTX (ENET0_SOF_TX),
- .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
- .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
- .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
- .EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
- .EMIOENET1MDIOO (ENET1_MDIO_O ),
- .EMIOENET1MDIOTN (ENET1_MDIO_T_n),
- .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
- .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
- .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
- .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
- .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
- .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
- .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
- .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
- .EMIOENET1SOFRX (ENET1_SOF_RX),
- .EMIOENET1SOFTX (ENET1_SOF_TX),
- .EMIOGPIOO (gpio_out),
- .EMIOGPIOTN (gpio_out_t_n),
- .EMIOI2C0SCLO (I2C0_SCL_O),
- .EMIOI2C0SCLTN (I2C0_SCL_T_n),
- .EMIOI2C0SDAO (I2C0_SDA_O),
- .EMIOI2C0SDATN (I2C0_SDA_T_n),
- .EMIOI2C1SCLO (I2C1_SCL_O),
- .EMIOI2C1SCLTN (I2C1_SCL_T_n),
- .EMIOI2C1SDAO (I2C1_SDA_O),
- .EMIOI2C1SDATN (I2C1_SDA_T_n),
- .EMIOPJTAGTDO (PJTAG_TDO_O),
- .EMIOPJTAGTDTN (PJTAG_TDO_T_n),
- .EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
- .EMIOSDIO0CLK (SDIO0_CLK ),
- .EMIOSDIO0CMDO (SDIO0_CMD_O ),
- .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
- .EMIOSDIO0DATAO (SDIO0_DATA_O),
- .EMIOSDIO0DATATN (SDIO0_DATA_T_n),
- .EMIOSDIO0LED (SDIO0_LED),
- .EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
- .EMIOSDIO1CLK (SDIO1_CLK ),
- .EMIOSDIO1CMDO (SDIO1_CMD_O ),
- .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
- .EMIOSDIO1DATAO (SDIO1_DATA_O),
- .EMIOSDIO1DATATN (SDIO1_DATA_T_n),
- .EMIOSDIO1LED (SDIO1_LED),
- .EMIOSPI0MO (SPI0_MOSI_O),
- .EMIOSPI0MOTN (SPI0_MOSI_T_n),
- .EMIOSPI0SCLKO (SPI0_SCLK_O),
- .EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
- .EMIOSPI0SO (SPI0_MISO_O),
- .EMIOSPI0STN (SPI0_MISO_T_n),
- .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
- .EMIOSPI0SSNTN (SPI0_SS_T_n),
- .EMIOSPI1MO (SPI1_MOSI_O),
- .EMIOSPI1MOTN (SPI1_MOSI_T_n),
- .EMIOSPI1SCLKO (SPI1_SCLK_O),
- .EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
- .EMIOSPI1SO (SPI1_MISO_O),
- .EMIOSPI1STN (SPI1_MISO_T_n),
- .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
- .EMIOSPI1SSNTN (SPI1_SS_T_n),
- .EMIOTRACECTL (TRACE_CTL_i),
- .EMIOTRACEDATA (TRACE_DATA_i),
- .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
- .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
- .EMIOUART0DTRN (UART0_DTRN),
- .EMIOUART0RTSN (UART0_RTSN),
- .EMIOUART0TX (UART0_TX ),
- .EMIOUART1DTRN (UART1_DTRN),
- .EMIOUART1RTSN (UART1_RTSN),
- .EMIOUART1TX (UART1_TX ),
- .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
- .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
- .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
- .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
- .EMIOWDTRSTO (WDT_RST_OUT),
- .EVENTEVENTO (EVENT_EVENTO),
- .EVENTSTANDBYWFE (EVENT_STANDBYWFE),
- .EVENTSTANDBYWFI (EVENT_STANDBYWFI),
- .FCLKCLK (FCLK_CLK_unbuffered),
- .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
- .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
- .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
- .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
- .FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
- .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
- .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
- .MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
- .MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
- .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t),
- .MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
- .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
- .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
- .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
- .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
- .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
- .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
- .MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
- .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
- .MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
- .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t),
- .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
- .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
- .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
- .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
- .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
- .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
- .MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
- .MAXIGP0BREADY (M_AXI_GP0_BREADY ),
- .MAXIGP0RREADY (M_AXI_GP0_RREADY ),
- .MAXIGP0WDATA (M_AXI_GP0_WDATA ),
- .MAXIGP0WID (M_AXI_GP0_WID_FULL ),
- .MAXIGP0WLAST (M_AXI_GP0_WLAST ),
- .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
- .MAXIGP0WVALID (M_AXI_GP0_WVALID ),
- .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
- .MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
- .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t),
- .MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
- .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
- .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
- .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
- .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
- .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
- .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
- .MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
- .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
- .MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
- .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t),
- .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
- .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
- .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
- .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
- .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
- .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
- .MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
- .MAXIGP1BREADY (M_AXI_GP1_BREADY ),
- .MAXIGP1RREADY (M_AXI_GP1_RREADY ),
- .MAXIGP1WDATA (M_AXI_GP1_WDATA ),
- .MAXIGP1WID (M_AXI_GP1_WID_FULL ),
- .MAXIGP1WLAST (M_AXI_GP1_WLAST ),
- .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
- .MAXIGP1WVALID (M_AXI_GP1_WVALID ),
- .SAXIACPARESETN (S_AXI_ACP_ARESETN),
- .SAXIACPARREADY (SAXIACPARREADY_W),
- .SAXIACPAWREADY (SAXIACPAWREADY_W),
- .SAXIACPBID (S_AXI_ACP_BID_out ),
- .SAXIACPBRESP (SAXIACPBRESP_W ),
- .SAXIACPBVALID (SAXIACPBVALID_W ),
- .SAXIACPRDATA (SAXIACPRDATA_W ),
- .SAXIACPRID (S_AXI_ACP_RID_out),
- .SAXIACPRLAST (SAXIACPRLAST_W ),
- .SAXIACPRRESP (SAXIACPRRESP_W ),
- .SAXIACPRVALID (SAXIACPRVALID_W ),
- .SAXIACPWREADY (SAXIACPWREADY_W ),
- .SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
- .SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
- .SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
- .SAXIGP0BID (S_AXI_GP0_BID_out),
- .SAXIGP0BRESP (S_AXI_GP0_BRESP ),
- .SAXIGP0BVALID (S_AXI_GP0_BVALID ),
- .SAXIGP0RDATA (S_AXI_GP0_RDATA ),
- .SAXIGP0RID (S_AXI_GP0_RID_out ),
- .SAXIGP0RLAST (S_AXI_GP0_RLAST ),
- .SAXIGP0RRESP (S_AXI_GP0_RRESP ),
- .SAXIGP0RVALID (S_AXI_GP0_RVALID ),
- .SAXIGP0WREADY (S_AXI_GP0_WREADY ),
- .SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
- .SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
- .SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
- .SAXIGP1BID (S_AXI_GP1_BID_out ),
- .SAXIGP1BRESP (S_AXI_GP1_BRESP ),
- .SAXIGP1BVALID (S_AXI_GP1_BVALID ),
- .SAXIGP1RDATA (S_AXI_GP1_RDATA ),
- .SAXIGP1RID (S_AXI_GP1_RID_out ),
- .SAXIGP1RLAST (S_AXI_GP1_RLAST ),
- .SAXIGP1RRESP (S_AXI_GP1_RRESP ),
- .SAXIGP1RVALID (S_AXI_GP1_RVALID ),
- .SAXIGP1WREADY (S_AXI_GP1_WREADY ),
- .SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
- .SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
- .SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
- .SAXIHP0BID (S_AXI_HP0_BID_out ),
- .SAXIHP0BRESP (S_AXI_HP0_BRESP ),
- .SAXIHP0BVALID (S_AXI_HP0_BVALID ),
- .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
- .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
- .SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
- .SAXIHP0RID (S_AXI_HP0_RID_out ),
- .SAXIHP0RLAST (S_AXI_HP0_RLAST),
- .SAXIHP0RRESP (S_AXI_HP0_RRESP),
- .SAXIHP0RVALID (S_AXI_HP0_RVALID),
- .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
- .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
- .SAXIHP0WREADY (S_AXI_HP0_WREADY),
- .SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
- .SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
- .SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
- .SAXIHP1BID (S_AXI_HP1_BID_out ),
- .SAXIHP1BRESP (S_AXI_HP1_BRESP ),
- .SAXIHP1BVALID (S_AXI_HP1_BVALID ),
- .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
- .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
- .SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
- .SAXIHP1RID (S_AXI_HP1_RID_out ),
- .SAXIHP1RLAST (S_AXI_HP1_RLAST ),
- .SAXIHP1RRESP (S_AXI_HP1_RRESP ),
- .SAXIHP1RVALID (S_AXI_HP1_RVALID),
- .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
- .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
- .SAXIHP1WREADY (S_AXI_HP1_WREADY),
- .SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
- .SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
- .SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
- .SAXIHP2BID (S_AXI_HP2_BID_out ),
- .SAXIHP2BRESP (S_AXI_HP2_BRESP),
- .SAXIHP2BVALID (S_AXI_HP2_BVALID),
- .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
- .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
- .SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
- .SAXIHP2RID (S_AXI_HP2_RID_out ),
- .SAXIHP2RLAST (S_AXI_HP2_RLAST),
- .SAXIHP2RRESP (S_AXI_HP2_RRESP),
- .SAXIHP2RVALID (S_AXI_HP2_RVALID),
- .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
- .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
- .SAXIHP2WREADY (S_AXI_HP2_WREADY),
- .SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
- .SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
- .SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
- .SAXIHP3BID (S_AXI_HP3_BID_out),
- .SAXIHP3BRESP (S_AXI_HP3_BRESP),
- .SAXIHP3BVALID (S_AXI_HP3_BVALID),
- .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
- .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
- .SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
- .SAXIHP3RID (S_AXI_HP3_RID_out),
- .SAXIHP3RLAST (S_AXI_HP3_RLAST),
- .SAXIHP3RRESP (S_AXI_HP3_RRESP),
- .SAXIHP3RVALID (S_AXI_HP3_RVALID),
- .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
- .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
- .SAXIHP3WREADY (S_AXI_HP3_WREADY),
- .DDRARB (DDR_ARB),
- .DMA0ACLK (DMA0_ACLK ),
- .DMA0DAREADY (DMA0_DAREADY),
- .DMA0DRLAST (DMA0_DRLAST ),
- .DMA0DRTYPE (DMA0_DRTYPE),
- .DMA0DRVALID (DMA0_DRVALID),
- .DMA1ACLK (DMA1_ACLK ),
- .DMA1DAREADY (DMA1_DAREADY),
- .DMA1DRLAST (DMA1_DRLAST ),
- .DMA1DRTYPE (DMA1_DRTYPE),
- .DMA1DRVALID (DMA1_DRVALID),
- .DMA2ACLK (DMA2_ACLK ),
- .DMA2DAREADY (DMA2_DAREADY),
- .DMA2DRLAST (DMA2_DRLAST ),
- .DMA2DRTYPE (DMA2_DRTYPE),
- .DMA2DRVALID (DMA2_DRVALID),
- .DMA3ACLK (DMA3_ACLK ),
- .DMA3DAREADY (DMA3_DAREADY),
- .DMA3DRLAST (DMA3_DRLAST ),
- .DMA3DRTYPE (DMA3_DRTYPE),
- .DMA3DRVALID (DMA3_DRVALID),
- .EMIOCAN0PHYRX (CAN0_PHY_RX),
- .EMIOCAN1PHYRX (CAN1_PHY_RX),
- .EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
- .EMIOENET0GMIICOL (ENET0_GMII_COL_i),
- .EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
- .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
- .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
- .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
- .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
- .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
- .EMIOENET0MDIOI (ENET0_MDIO_I),
- .EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
- .EMIOENET1GMIICOL (ENET1_GMII_COL_i),
- .EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
- .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
- .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
- .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
- .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
- .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
- .EMIOENET1MDIOI (ENET1_MDIO_I),
- .EMIOGPIOI (gpio_in63_0 ),
- .EMIOI2C0SCLI (I2C0_SCL_I),
- .EMIOI2C0SDAI (I2C0_SDA_I),
- .EMIOI2C1SCLI (I2C1_SCL_I),
- .EMIOI2C1SDAI (I2C1_SDA_I),
- .EMIOPJTAGTCK (PJTAG_TCK),
- .EMIOPJTAGTDI (PJTAG_TDI),
- .EMIOPJTAGTMS (PJTAG_TMS),
- .EMIOSDIO0CDN (SDIO0_CDN),
- .EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
- .EMIOSDIO0CMDI (SDIO0_CMD_I ),
- .EMIOSDIO0DATAI (SDIO0_DATA_I ),
- .EMIOSDIO0WP (SDIO0_WP),
- .EMIOSDIO1CDN (SDIO1_CDN),
- .EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
- .EMIOSDIO1CMDI (SDIO1_CMD_I ),
- .EMIOSDIO1DATAI (SDIO1_DATA_I ),
- .EMIOSDIO1WP (SDIO1_WP),
- .EMIOSPI0MI (SPI0_MISO_I),
- .EMIOSPI0SCLKI (SPI0_SCLK_I),
- .EMIOSPI0SI (SPI0_MOSI_I),
- .EMIOSPI0SSIN (SPI0_SS_I),
- .EMIOSPI1MI (SPI1_MISO_I),
- .EMIOSPI1SCLKI (SPI1_SCLK_I),
- .EMIOSPI1SI (SPI1_MOSI_I),
- .EMIOSPI1SSIN (SPI1_SS_I),
- .EMIOSRAMINTIN (SRAM_INTIN),
- .EMIOTRACECLK (TRACE_CLK),
- .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
- .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
- .EMIOUART0CTSN (UART0_CTSN),
- .EMIOUART0DCDN (UART0_DCDN),
- .EMIOUART0DSRN (UART0_DSRN),
- .EMIOUART0RIN (UART0_RIN ),
- .EMIOUART0RX (UART0_RX ),
- .EMIOUART1CTSN (UART1_CTSN),
- .EMIOUART1DCDN (UART1_DCDN),
- .EMIOUART1DSRN (UART1_DSRN),
- .EMIOUART1RIN (UART1_RIN ),
- .EMIOUART1RX (UART1_RX ),
- .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
- .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
- .EMIOWDTCLKI (WDT_CLK_IN),
- .EVENTEVENTI (EVENT_EVENTI),
- .FCLKCLKTRIGN (fclk_clktrig_gnd),
- .FPGAIDLEN (FPGA_IDLE_N),
- .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
- .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
- .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
- .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
- .FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
- .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
- .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
- .IRQF2P (irq_f2p_i),
- .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
- .MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
- .MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
- .MAXIGP0BID (M_AXI_GP0_BID_FULL ),
- .MAXIGP0BRESP (M_AXI_GP0_BRESP ),
- .MAXIGP0BVALID (M_AXI_GP0_BVALID ),
- .MAXIGP0RDATA (M_AXI_GP0_RDATA ),
- .MAXIGP0RID (M_AXI_GP0_RID_FULL ),
- .MAXIGP0RLAST (M_AXI_GP0_RLAST ),
- .MAXIGP0RRESP (M_AXI_GP0_RRESP ),
- .MAXIGP0RVALID (M_AXI_GP0_RVALID ),
- .MAXIGP0WREADY (M_AXI_GP0_WREADY ),
- .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
- .MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
- .MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
- .MAXIGP1BID (M_AXI_GP1_BID_FULL ),
- .MAXIGP1BRESP (M_AXI_GP1_BRESP ),
- .MAXIGP1BVALID (M_AXI_GP1_BVALID ),
- .MAXIGP1RDATA (M_AXI_GP1_RDATA ),
- .MAXIGP1RID (M_AXI_GP1_RID_FULL ),
- .MAXIGP1RLAST (M_AXI_GP1_RLAST ),
- .MAXIGP1RRESP (M_AXI_GP1_RRESP ),
- .MAXIGP1RVALID (M_AXI_GP1_RVALID ),
- .MAXIGP1WREADY (M_AXI_GP1_WREADY ),
- .SAXIACPACLK (S_AXI_ACP_ACLK_temp),
- .SAXIACPARADDR (SAXIACPARADDR_W ),
- .SAXIACPARBURST (SAXIACPARBURST_W),
- .SAXIACPARCACHE (SAXIACPARCACHE_W),
- .SAXIACPARID (S_AXI_ACP_ARID_in ),
- .SAXIACPARLEN (SAXIACPARLEN_W ),
- .SAXIACPARLOCK (SAXIACPARLOCK_W ),
- .SAXIACPARPROT (SAXIACPARPROT_W ),
- .SAXIACPARQOS (S_AXI_ACP_ARQOS ),
- .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
- .SAXIACPARUSER (SAXIACPARUSER_W ),
- .SAXIACPARVALID (SAXIACPARVALID_W),
- .SAXIACPAWADDR (SAXIACPAWADDR_W ),
- .SAXIACPAWBURST (SAXIACPAWBURST_W),
- .SAXIACPAWCACHE (SAXIACPAWCACHE_W),
- .SAXIACPAWID (S_AXI_ACP_AWID_in ),
- .SAXIACPAWLEN (SAXIACPAWLEN_W ),
- .SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
- .SAXIACPAWPROT (SAXIACPAWPROT_W ),
- .SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
- .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
- .SAXIACPAWUSER (SAXIACPAWUSER_W ),
- .SAXIACPAWVALID (SAXIACPAWVALID_W),
- .SAXIACPBREADY (SAXIACPBREADY_W ),
- .SAXIACPRREADY (SAXIACPRREADY_W ),
- .SAXIACPWDATA (SAXIACPWDATA_W ),
- .SAXIACPWID (S_AXI_ACP_WID_in ),
- .SAXIACPWLAST (SAXIACPWLAST_W ),
- .SAXIACPWSTRB (SAXIACPWSTRB_W ),
- .SAXIACPWVALID (SAXIACPWVALID_W ),
- .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
- .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
- .SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
- .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
- .SAXIGP0ARID (S_AXI_GP0_ARID_in ),
- .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
- .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
- .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
- .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
- .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
- .SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
- .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
- .SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
- .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
- .SAXIGP0AWID (S_AXI_GP0_AWID_in ),
- .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
- .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
- .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
- .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
- .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
- .SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
- .SAXIGP0BREADY (S_AXI_GP0_BREADY ),
- .SAXIGP0RREADY (S_AXI_GP0_RREADY ),
- .SAXIGP0WDATA (S_AXI_GP0_WDATA ),
- .SAXIGP0WID (S_AXI_GP0_WID_in ),
- .SAXIGP0WLAST (S_AXI_GP0_WLAST ),
- .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
- .SAXIGP0WVALID (S_AXI_GP0_WVALID ),
- .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
- .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
- .SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
- .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
- .SAXIGP1ARID (S_AXI_GP1_ARID_in ),
- .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
- .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
- .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
- .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
- .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
- .SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
- .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
- .SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
- .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
- .SAXIGP1AWID (S_AXI_GP1_AWID_in ),
- .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
- .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
- .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
- .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
- .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
- .SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
- .SAXIGP1BREADY (S_AXI_GP1_BREADY ),
- .SAXIGP1RREADY (S_AXI_GP1_RREADY ),
- .SAXIGP1WDATA (S_AXI_GP1_WDATA ),
- .SAXIGP1WID (S_AXI_GP1_WID_in ),
- .SAXIGP1WLAST (S_AXI_GP1_WLAST ),
- .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
- .SAXIGP1WVALID (S_AXI_GP1_WVALID ),
- .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
- .SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
- .SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
- .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
- .SAXIHP0ARID (S_AXI_HP0_ARID_in),
- .SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
- .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
- .SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
- .SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
- .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
- .SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
- .SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
- .SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
- .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
- .SAXIHP0AWID (S_AXI_HP0_AWID_in),
- .SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
- .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
- .SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
- .SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
- .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
- .SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
- .SAXIHP0BREADY (S_AXI_HP0_BREADY),
- .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
- .SAXIHP0RREADY (S_AXI_HP0_RREADY),
- .SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
- .SAXIHP0WID (S_AXI_HP0_WID_in),
- .SAXIHP0WLAST (S_AXI_HP0_WLAST),
- .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
- .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
- .SAXIHP0WVALID (S_AXI_HP0_WVALID),
- .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
- .SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
- .SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
- .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
- .SAXIHP1ARID (S_AXI_HP1_ARID_in),
- .SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
- .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
- .SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
- .SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
- .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
- .SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
- .SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
- .SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
- .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
- .SAXIHP1AWID (S_AXI_HP1_AWID_in),
- .SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
- .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
- .SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
- .SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
- .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
- .SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
- .SAXIHP1BREADY (S_AXI_HP1_BREADY),
- .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
- .SAXIHP1RREADY (S_AXI_HP1_RREADY),
- .SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
- .SAXIHP1WID (S_AXI_HP1_WID_in),
- .SAXIHP1WLAST (S_AXI_HP1_WLAST),
- .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
- .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
- .SAXIHP1WVALID (S_AXI_HP1_WVALID),
- .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
- .SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
- .SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
- .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
- .SAXIHP2ARID (S_AXI_HP2_ARID_in),
- .SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
- .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
- .SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
- .SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
- .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
- .SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
- .SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
- .SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
- .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
- .SAXIHP2AWID (S_AXI_HP2_AWID_in),
- .SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
- .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
- .SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
- .SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
- .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
- .SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
- .SAXIHP2BREADY (S_AXI_HP2_BREADY),
- .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
- .SAXIHP2RREADY (S_AXI_HP2_RREADY),
- .SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
- .SAXIHP2WID (S_AXI_HP2_WID_in),
- .SAXIHP2WLAST (S_AXI_HP2_WLAST),
- .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
- .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
- .SAXIHP2WVALID (S_AXI_HP2_WVALID),
- .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
- .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
- .SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
- .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
- .SAXIHP3ARID (S_AXI_HP3_ARID_in ),
- .SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
- .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
- .SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
- .SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
- .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
- .SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
- .SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
- .SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
- .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
- .SAXIHP3AWID (S_AXI_HP3_AWID_in),
- .SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
- .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
- .SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
- .SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
- .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
- .SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
- .SAXIHP3BREADY (S_AXI_HP3_BREADY),
- .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
- .SAXIHP3RREADY (S_AXI_HP3_RREADY),
- .SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
- .SAXIHP3WID (S_AXI_HP3_WID_in),
- .SAXIHP3WLAST (S_AXI_HP3_WLAST),
- .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
- .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
- .SAXIHP3WVALID (S_AXI_HP3_WVALID),
- .DDRA (buffered_DDR_Addr),
- .DDRBA (buffered_DDR_BankAddr),
- .DDRCASB (buffered_DDR_CAS_n),
- .DDRCKE (buffered_DDR_CKE),
- .DDRCKN (buffered_DDR_Clk_n),
- .DDRCKP (buffered_DDR_Clk),
- .DDRCSB (buffered_DDR_CS_n),
- .DDRDM (buffered_DDR_DM),
- .DDRDQ (buffered_DDR_DQ),
- .DDRDQSN (buffered_DDR_DQS_n),
- .DDRDQSP (buffered_DDR_DQS),
- .DDRDRSTB (buffered_DDR_DRSTB),
- .DDRODT (buffered_DDR_ODT),
- .DDRRASB (buffered_DDR_RAS_n),
- .DDRVRN (buffered_DDR_VRN),
- .DDRVRP (buffered_DDR_VRP),
- .DDRWEB (buffered_DDR_WEB),
- .MIO (buffered_MIO),
- .PSCLK (buffered_PS_CLK),
- .PSPORB (buffered_PS_PORB),
- .PSSRSTB (buffered_PS_SRSTB)
-
-
- );
-
- end
- endgenerate
-
-
-// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
-// Otherwise a master connected to the ACP port will drive the AxUSER Ports
-assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
-assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
-
- assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
- assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
- assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
- assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
- assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
- assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
- assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
- //assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
- assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
-
- assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
- assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
- assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
-
-
- assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
- assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
- assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
- assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
- assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
- //assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
- assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
- assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
- assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
- assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
- assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
- assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
- assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
- assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
-
- assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
- assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
- assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
-
-
- generate
- if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
-
- assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
- assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
- assign S_AXI_ACP_BID = SAXIACPBID_W;
- assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
- assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
- assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
- assign S_AXI_ACP_RID = SAXIACPRID_W;
- assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
- assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
- assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
- assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
-
-
- end else begin : gen_atc
-
- processing_system7_v5_5_atc #(
- .C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
- .C_AXI_AWUSER_WIDTH (5),
- .C_AXI_ARUSER_WIDTH (5)
- )
-
- atc_i (
-
- // Global Signals
- .ACLK (S_AXI_ACP_ACLK_temp),
- .ARESETN (S_AXI_ACP_ARESETN),
-
- // Slave Interface Write Address Ports
- .S_AXI_AWID (S_AXI_ACP_AWID),
- .S_AXI_AWADDR (S_AXI_ACP_AWADDR),
- .S_AXI_AWLEN (S_AXI_ACP_AWLEN),
- .S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
- .S_AXI_AWBURST (S_AXI_ACP_AWBURST),
- .S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
- .S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
- .S_AXI_AWPROT (S_AXI_ACP_AWPROT),
- //.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
- .S_AXI_AWUSER (param_awuser),
- .S_AXI_AWVALID (S_AXI_ACP_AWVALID),
- .S_AXI_AWREADY (S_AXI_ACP_AWREADY),
- // Slave Interface Write Data Ports
- .S_AXI_WID (S_AXI_ACP_WID),
- .S_AXI_WDATA (S_AXI_ACP_WDATA),
- .S_AXI_WSTRB (S_AXI_ACP_WSTRB),
- .S_AXI_WLAST (S_AXI_ACP_WLAST),
- .S_AXI_WUSER (),
- .S_AXI_WVALID (S_AXI_ACP_WVALID),
- .S_AXI_WREADY (S_AXI_ACP_WREADY),
- // Slave Interface Write Response Ports
- .S_AXI_BID (S_AXI_ACP_BID),
- .S_AXI_BRESP (S_AXI_ACP_BRESP),
- .S_AXI_BUSER (),
- .S_AXI_BVALID (S_AXI_ACP_BVALID),
- .S_AXI_BREADY (S_AXI_ACP_BREADY),
- // Slave Interface Read Address Ports
- .S_AXI_ARID (S_AXI_ACP_ARID),
- .S_AXI_ARADDR (S_AXI_ACP_ARADDR),
- .S_AXI_ARLEN (S_AXI_ACP_ARLEN),
- .S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
- .S_AXI_ARBURST (S_AXI_ACP_ARBURST),
- .S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
- .S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
- .S_AXI_ARPROT (S_AXI_ACP_ARPROT),
- //.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
- .S_AXI_ARUSER (param_aruser),
- .S_AXI_ARVALID (S_AXI_ACP_ARVALID),
- .S_AXI_ARREADY (S_AXI_ACP_ARREADY),
- // Slave Interface Read Data Ports
- .S_AXI_RID (S_AXI_ACP_RID),
- .S_AXI_RDATA (S_AXI_ACP_RDATA),
- .S_AXI_RRESP (S_AXI_ACP_RRESP),
- .S_AXI_RLAST (S_AXI_ACP_RLAST),
- .S_AXI_RUSER (),
- .S_AXI_RVALID (S_AXI_ACP_RVALID),
- .S_AXI_RREADY (S_AXI_ACP_RREADY),
-
- // Slave Interface Write Address Ports
- .M_AXI_AWID (S_AXI_ATC_AWID),
- .M_AXI_AWADDR (S_AXI_ATC_AWADDR),
- .M_AXI_AWLEN (S_AXI_ATC_AWLEN),
- .M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
- .M_AXI_AWBURST (S_AXI_ATC_AWBURST),
- .M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
- .M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
- .M_AXI_AWPROT (S_AXI_ATC_AWPROT),
- .M_AXI_AWUSER (S_AXI_ATC_AWUSER),
- .M_AXI_AWVALID (S_AXI_ATC_AWVALID),
- .M_AXI_AWREADY (SAXIACPAWREADY_W),
- // Slave Interface Write Data Ports
- .M_AXI_WID (S_AXI_ATC_WID),
- .M_AXI_WDATA (S_AXI_ATC_WDATA),
- .M_AXI_WSTRB (S_AXI_ATC_WSTRB),
- .M_AXI_WLAST (S_AXI_ATC_WLAST),
- .M_AXI_WUSER (),
- .M_AXI_WVALID (S_AXI_ATC_WVALID),
- .M_AXI_WREADY (SAXIACPWREADY_W),
- // Slave Interface Write Response Ports
- .M_AXI_BID (SAXIACPBID_W),
- .M_AXI_BRESP (SAXIACPBRESP_W),
- .M_AXI_BUSER (),
- .M_AXI_BVALID (SAXIACPBVALID_W),
- .M_AXI_BREADY (S_AXI_ATC_BREADY),
- // Slave Interface Read Address Ports
- .M_AXI_ARID (S_AXI_ATC_ARID),
- .M_AXI_ARADDR (S_AXI_ATC_ARADDR),
- .M_AXI_ARLEN (S_AXI_ATC_ARLEN),
- .M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
- .M_AXI_ARBURST (S_AXI_ATC_ARBURST),
- .M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
- .M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
- .M_AXI_ARPROT (S_AXI_ATC_ARPROT),
- .M_AXI_ARUSER (S_AXI_ATC_ARUSER),
- .M_AXI_ARVALID (S_AXI_ATC_ARVALID),
- .M_AXI_ARREADY (SAXIACPARREADY_W),
- // Slave Interface Read Data Ports
- .M_AXI_RID (SAXIACPRID_W),
- .M_AXI_RDATA (SAXIACPRDATA_W),
- .M_AXI_RRESP (SAXIACPRRESP_W),
- .M_AXI_RLAST (SAXIACPRLAST_W),
- .M_AXI_RUSER (),
- .M_AXI_RVALID (SAXIACPRVALID_W),
- .M_AXI_RREADY (S_AXI_ATC_RREADY),
-
-
- .ERROR_TRIGGER(),
- .ERROR_TRANSACTION_ID()
- );
-
-
-
- end
- endgenerate
-
-
-
-
-endmodule
-
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.c b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.c
deleted file mode 100644
index f16072f7cb5c2ad10b16c9ce27382ef46e1f2aa2..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.c
+++ /dev/null
@@ -1,12433 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this
-* software and associated documentation files (the "Software"), to deal in the Software
-* without restriction, including without limitation the rights to use, copy, modify, merge,
-* publish, distribute, sublicense, and/or sell copies of the Software, and to permit
-* persons to whom the Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
-* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000110[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000114[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000118[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x113
- // .. .. ==> 0XF8000118[21:12] = 0x00000113U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00113000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x00113220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x23
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000023U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00023000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00023000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x31
- // .. ==> 0XF8000128[13:8] = 0x00000031U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003100U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203101U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0xe
- // .. ==> 0XF8000140[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100E01U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xd
- // .. ==> 0XF800014C[13:8] = 0x0000000DU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000D00U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000D01U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000150[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000150[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000150[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001202U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000154[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001203U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000158[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000158[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000158[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xb
- // .. ==> 0XF8000158[13:8] = 0x0000000BU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000B00U
- // ..
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000B03U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF800015C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF800015C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x12
- // .. ==> 0XF800015C[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF800015C[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00101202U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x9
- // .. .. ==> 0XF8000168[13:8] = 0x00000009U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x7
- // .. .. ==> 0XF8000170[13:8] = 0x00000007U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200700U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. SDI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[11:11] = 0x00000001U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. .. SPI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. SPI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FEC84DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x79
- // .. .. ==> 0XF8006004[11:0] = 0x00000079U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000079U
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001079U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x19
- // .. .. ==> 0XF8006014[5:0] = 0x00000019U
- // .. .. ==> MASK : 0x0000003FU VAL : 0x00000019U
- // .. .. reg_ddrc_t_rfc_min = 0x50
- // .. .. ==> 0XF8006014[13:6] = 0x00000050U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001400U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041419U),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x14
- // .. .. ==> 0XF8006018[15:10] = 0x00000014U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005000U
- // .. .. reg_ddrc_t_ras_max = 0x22
- // .. .. ==> 0XF8006018[21:16] = 0x00000022U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00220000U
- // .. .. reg_ddrc_t_ras_min = 0x12
- // .. .. ==> 0XF8006018[26:22] = 0x00000012U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04800000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44A250D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x5
- // .. .. ==> 0XF8006020[7:5] = 0x00000005U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872B0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x156
- // .. .. ==> 0XF8006034[13:4] = 0x00000156U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001560U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011564U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x6
- // .. .. ==> 0XF800603C[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x6
- // .. .. ==> 0XF800603C[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x6
- // .. .. ==> 0XF800603C[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0xf
- // .. .. ==> 0XF8006040[19:16] = 0x0000000FU
- // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x5
- // .. .. ==> 0XF8006044[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x5
- // .. .. ==> 0XF8006044[7:4] = 0x00000005U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5
- // .. .. ==> 0XF8006044[11:8] = 0x00000005U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x5
- // .. .. ==> 0XF8006044[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x5
- // .. .. ==> 0XF8006044[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF55555U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x5
- // .. .. ==> 0XF8006078[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_t_cksrx = 0x5
- // .. .. ==> 0XF8006078[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xbebc
- // .. .. ==> 0XF80060A8[19:0] = 0x0000BEBCU
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000BEBCU
- // .. .. dram_rstn_x1024 = 0x62
- // .. .. ==> 0XF80060A8[27:20] = 0x00000062U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0620BEBCU),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xf5
- // .. .. ==> 0XF80060AC[8:1] = 0x000000F5U
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001EAU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001EAU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000000U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006124[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF800612C[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006134[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006154[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006158[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF800615C[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006160[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006168[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006170[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x11
- // .. .. ==> 0XF80062B0[11:4] = 0x00000011U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000110U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005115U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0x9e
- // .. .. ==> 0XF80062B4[7:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000000FFU VAL : 0x0000009EU
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x11
- // .. .. ==> 0XF80062B4[17:8] = 0x00000011U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001100U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x0000119EU),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B4C[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B4C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B4C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B4C[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B4C[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B54[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B54[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B54[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B54[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B54[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B5C[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B5C[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B60[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B60[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B64[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B64[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B68[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B68[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x1
- // .. ==> 0XF8000B6C[6:5] = 0x00000001U
- // .. ==> MASK : 0x00000060U VAL : 0x00000020U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000724[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003F01U ,0x00001601U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000728[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800072C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000730[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000734[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000738[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800073C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000740[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000740[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000744[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000744[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000748[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000748[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800074C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800074C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000750[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000750[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000754[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000754[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000758[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000758[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800075C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800075C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000760[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000760[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000764[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000764[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000768[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000768[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800076C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800076C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000770[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000770[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000774[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000774[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000778[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000778[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800077C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800077C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000780[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000780[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000784[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000784[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000788[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000788[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800078C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800078C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000790[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000790[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000794[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000794[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000798[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000798[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800079C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800079C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A0[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A8[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007AC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007AC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007AC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007B4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007B8[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007BC[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007BC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007CC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D0[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001420U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007D4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D4[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001421U),
- // .. SDIO1_WP_SEL = 57
- // .. ==> 0XF8000834[5:0] = 0x00000039U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000039U
- // .. SDIO1_CD_SEL = 9
- // .. ==> 0XF8000834[21:16] = 0x00000009U
- // .. ==> MASK : 0x003F0000U VAL : 0x00090000U
- // ..
- EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00090039U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. .. START: AFI2 SECURE REGISTER
- // .. .. FINISH: AFI2 SECURE REGISTER
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000110[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000114[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000118[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x113
- // .. .. ==> 0XF8000118[21:12] = 0x00000113U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00113000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x00113220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x23
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000023U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00023000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00023000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x31
- // .. ==> 0XF8000128[13:8] = 0x00000031U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003100U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203101U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0xe
- // .. ==> 0XF8000140[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100E01U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xd
- // .. ==> 0XF800014C[13:8] = 0x0000000DU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000D00U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000D01U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000150[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000150[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000150[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001202U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000154[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001203U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000158[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000158[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000158[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xb
- // .. ==> 0XF8000158[13:8] = 0x0000000BU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000B00U
- // ..
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000B03U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF800015C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF800015C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x12
- // .. ==> 0XF800015C[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF800015C[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00101202U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x9
- // .. .. ==> 0XF8000168[13:8] = 0x00000009U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x7
- // .. .. ==> 0XF8000170[13:8] = 0x00000007U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200700U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. SDI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[11:11] = 0x00000001U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. .. SPI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. SPI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FEC84DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x79
- // .. .. ==> 0XF8006004[11:0] = 0x00000079U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000079U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081079U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x19
- // .. .. ==> 0XF8006014[5:0] = 0x00000019U
- // .. .. ==> MASK : 0x0000003FU VAL : 0x00000019U
- // .. .. reg_ddrc_t_rfc_min = 0x50
- // .. .. ==> 0XF8006014[13:6] = 0x00000050U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001400U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041419U),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x14
- // .. .. ==> 0XF8006018[15:10] = 0x00000014U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005000U
- // .. .. reg_ddrc_t_ras_max = 0x22
- // .. .. ==> 0XF8006018[21:16] = 0x00000022U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00220000U
- // .. .. reg_ddrc_t_ras_min = 0x12
- // .. .. ==> 0XF8006018[26:22] = 0x00000012U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04800000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44A250D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x5
- // .. .. ==> 0XF8006020[7:5] = 0x00000005U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872B0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x156
- // .. .. ==> 0XF8006034[13:4] = 0x00000156U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001560U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011564U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x6
- // .. .. ==> 0XF800603C[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x6
- // .. .. ==> 0XF800603C[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x6
- // .. .. ==> 0XF800603C[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0xf
- // .. .. ==> 0XF8006040[19:16] = 0x0000000FU
- // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x5
- // .. .. ==> 0XF8006044[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x5
- // .. .. ==> 0XF8006044[7:4] = 0x00000005U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5
- // .. .. ==> 0XF8006044[11:8] = 0x00000005U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x5
- // .. .. ==> 0XF8006044[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x5
- // .. .. ==> 0XF8006044[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF55555U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x5
- // .. .. ==> 0XF8006078[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_t_cksrx = 0x5
- // .. .. ==> 0XF8006078[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xbebc
- // .. .. ==> 0XF80060A8[19:0] = 0x0000BEBCU
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000BEBCU
- // .. .. dram_rstn_x1024 = 0x62
- // .. .. ==> 0XF80060A8[27:20] = 0x00000062U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0620BEBCU),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xf5
- // .. .. ==> 0XF80060AC[8:1] = 0x000000F5U
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001EAU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001EAU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006124[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF800612C[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006134[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006154[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006158[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF800615C[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006160[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006168[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006170[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x11
- // .. .. ==> 0XF80062B0[11:4] = 0x00000011U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000110U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005115U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0x9e
- // .. .. ==> 0XF80062B4[7:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000000FFU VAL : 0x0000009EU
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x11
- // .. .. ==> 0XF80062B4[17:8] = 0x00000011U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001100U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x0000119EU),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B4C[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B4C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B4C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B4C[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B4C[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B54[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B54[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B54[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B54[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B54[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B5C[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B5C[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B60[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B60[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B64[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B64[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B68[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B68[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x1
- // .. ==> 0XF8000B6C[6:5] = 0x00000001U
- // .. ==> MASK : 0x00000060U VAL : 0x00000020U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000724[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003F01U ,0x00001601U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000728[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800072C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000730[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000734[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000738[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800073C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000740[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000740[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000744[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000744[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000748[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000748[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800074C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800074C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000750[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000750[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000754[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000754[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000758[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000758[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800075C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800075C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000760[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000760[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000764[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000764[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000768[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000768[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800076C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800076C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000770[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000770[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000774[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000774[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000778[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000778[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800077C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800077C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000780[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000780[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000784[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000784[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000788[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000788[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800078C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800078C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000790[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000790[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000794[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000794[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000798[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000798[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800079C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800079C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A0[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A8[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007AC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007AC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007AC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007B4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007B8[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007BC[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007BC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007CC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D0[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001420U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007D4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D4[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001421U),
- // .. SDIO1_WP_SEL = 57
- // .. ==> 0XF8000834[5:0] = 0x00000039U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000039U
- // .. SDIO1_CD_SEL = 9
- // .. ==> 0XF8000834[21:16] = 0x00000009U
- // .. ==> MASK : 0x003F0000U VAL : 0x00090000U
- // ..
- EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00090039U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000110[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000114[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000118[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x113
- // .. .. ==> 0XF8000118[21:12] = 0x00000113U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00113000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x00113220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x23
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000023U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00023000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00023000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x31
- // .. ==> 0XF8000128[13:8] = 0x00000031U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003100U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203101U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0xe
- // .. ==> 0XF8000140[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100E01U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xd
- // .. ==> 0XF800014C[13:8] = 0x0000000DU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000D00U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000D01U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000150[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000150[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000150[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001202U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000154[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001203U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000158[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000158[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000158[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xb
- // .. ==> 0XF8000158[13:8] = 0x0000000BU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000B00U
- // ..
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000B03U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF800015C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF800015C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x12
- // .. ==> 0XF800015C[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF800015C[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00101202U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x9
- // .. .. ==> 0XF8000168[13:8] = 0x00000009U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x7
- // .. .. ==> 0XF8000170[13:8] = 0x00000007U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200700U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. SDI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[11:11] = 0x00000001U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. .. SPI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. SPI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FEC84DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x79
- // .. .. ==> 0XF8006004[11:0] = 0x00000079U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000079U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081079U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x19
- // .. .. ==> 0XF8006014[5:0] = 0x00000019U
- // .. .. ==> MASK : 0x0000003FU VAL : 0x00000019U
- // .. .. reg_ddrc_t_rfc_min = 0x50
- // .. .. ==> 0XF8006014[13:6] = 0x00000050U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001400U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041419U),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x14
- // .. .. ==> 0XF8006018[15:10] = 0x00000014U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005000U
- // .. .. reg_ddrc_t_ras_max = 0x22
- // .. .. ==> 0XF8006018[21:16] = 0x00000022U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00220000U
- // .. .. reg_ddrc_t_ras_min = 0x12
- // .. .. ==> 0XF8006018[26:22] = 0x00000012U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04800000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44A250D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x5
- // .. .. ==> 0XF8006020[7:5] = 0x00000005U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872B0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x156
- // .. .. ==> 0XF8006034[13:4] = 0x00000156U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001560U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011564U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x6
- // .. .. ==> 0XF800603C[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x6
- // .. .. ==> 0XF800603C[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x6
- // .. .. ==> 0XF800603C[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0xf
- // .. .. ==> 0XF8006040[19:16] = 0x0000000FU
- // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x5
- // .. .. ==> 0XF8006044[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x5
- // .. .. ==> 0XF8006044[7:4] = 0x00000005U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5
- // .. .. ==> 0XF8006044[11:8] = 0x00000005U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x5
- // .. .. ==> 0XF8006044[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x5
- // .. .. ==> 0XF8006044[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF55555U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xbebc
- // .. .. ==> 0XF80060A8[19:0] = 0x0000BEBCU
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000BEBCU
- // .. .. dram_rstn_x1024 = 0x62
- // .. .. ==> 0XF80060A8[27:20] = 0x00000062U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0620BEBCU),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xf5
- // .. .. ==> 0XF80060AC[8:1] = 0x000000F5U
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001EAU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001EAU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006124[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF800612C[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006134[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006154[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006158[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF800615C[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006160[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006168[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006170[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x11
- // .. .. ==> 0XF80062B0[11:4] = 0x00000011U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000110U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005115U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0x9e
- // .. .. ==> 0XF80062B4[7:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000000FFU VAL : 0x0000009EU
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x11
- // .. .. ==> 0XF80062B4[17:8] = 0x00000011U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001100U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x0000119EU),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B4C[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B4C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B4C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B4C[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B4C[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B54[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B54[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B54[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B54[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B54[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B5C[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B5C[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B60[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B60[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B64[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B64[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B68[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B68[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x1
- // .. ==> 0XF8000B6C[6:5] = 0x00000001U
- // .. ==> MASK : 0x00000060U VAL : 0x00000020U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000220U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000724[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003F01U ,0x00001601U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000728[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800072C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000730[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000734[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000738[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800073C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000740[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000740[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000744[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000744[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000748[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000748[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800074C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800074C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000750[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000750[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000754[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000754[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000758[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000758[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800075C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800075C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000760[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000760[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000764[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000764[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000768[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000768[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800076C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800076C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000770[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000770[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000774[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000774[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000778[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000778[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800077C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800077C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000780[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000780[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000784[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000784[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000788[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000788[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800078C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800078C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000790[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000790[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000794[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000794[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000798[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000798[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800079C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800079C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A0[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A8[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007AC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007AC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007AC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007B4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007B8[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007BC[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007BC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007CC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D0[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001420U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007D4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D4[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001421U),
- // .. SDIO1_WP_SEL = 57
- // .. ==> 0XF8000834[5:0] = 0x00000039U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000039U
- // .. SDIO1_CD_SEL = 9
- // .. ==> 0XF8000834[21:16] = 0x00000009U
- // .. ==> MASK : 0x003F0000U VAL : 0x00090000U
- // ..
- EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00090039U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- {
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
-
-
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.h
deleted file mode 100644
index c2236f6c2d56cef8bdf61caedc9bb70257760236..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010-2019 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 750000000
-#define DDR_FREQ 500000000
-#define DCI_FREQ 10204082
-#define QSPI_FREQ 134615387
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 97222221
-#define UART_FREQ 97222221
-#define SPI_FREQ 159090912
-#define I2C_FREQ 125000000
-#define WDT_FREQ 125000000
-#define TTC_FREQ 50000000
-#define CAN_FREQ 97222221
-#define PCAP_FREQ 194444443
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 125000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.tcl
deleted file mode 100644
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.c b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.c
deleted file mode 100644
index 7fed4b70f5f90c221afb35134fcf8641b0ae03e4..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.c
+++ /dev/null
@@ -1,12431 +0,0 @@
-/******************************************************************************
-* Copyright (C) 2010-2019 <Xilinx Inc.>
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.c
-*
-* This file is automatically generated
-*
-*****************************************************************************/
-
-#include "ps7_init_gpl.h"
-
-unsigned long ps7_pll_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000110[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000114[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000118[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x113
- // .. .. ==> 0XF8000118[21:12] = 0x00000113U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00113000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x00113220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x23
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000023U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00023000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00023000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x31
- // .. ==> 0XF8000128[13:8] = 0x00000031U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003100U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203101U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0xe
- // .. ==> 0XF8000140[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100E01U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xd
- // .. ==> 0XF800014C[13:8] = 0x0000000DU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000D00U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000D01U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000150[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000150[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000150[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001202U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000154[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001203U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000158[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000158[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000158[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xb
- // .. ==> 0XF8000158[13:8] = 0x0000000BU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000B00U
- // ..
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000B03U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF800015C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF800015C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x12
- // .. ==> 0XF800015C[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF800015C[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00101202U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x9
- // .. .. ==> 0XF8000168[13:8] = 0x00000009U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x7
- // .. .. ==> 0XF8000170[13:8] = 0x00000007U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200700U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. SDI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[11:11] = 0x00000001U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. .. SPI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. SPI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FEC84DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_3_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x79
- // .. .. ==> 0XF8006004[11:0] = 0x00000079U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000079U
- // .. .. reserved_reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001079U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x19
- // .. .. ==> 0XF8006014[5:0] = 0x00000019U
- // .. .. ==> MASK : 0x0000003FU VAL : 0x00000019U
- // .. .. reg_ddrc_t_rfc_min = 0x50
- // .. .. ==> 0XF8006014[13:6] = 0x00000050U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001400U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041419U),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x14
- // .. .. ==> 0XF8006018[15:10] = 0x00000014U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005000U
- // .. .. reg_ddrc_t_ras_max = 0x22
- // .. .. ==> 0XF8006018[21:16] = 0x00000022U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00220000U
- // .. .. reg_ddrc_t_ras_min = 0x12
- // .. .. ==> 0XF8006018[26:22] = 0x00000012U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04800000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44A250D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x5
- // .. .. ==> 0XF8006020[7:5] = 0x00000005U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872B0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x156
- // .. .. ==> 0XF8006034[13:4] = 0x00000156U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001560U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011564U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x6
- // .. .. ==> 0XF800603C[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x6
- // .. .. ==> 0XF800603C[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x6
- // .. .. ==> 0XF800603C[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0xf
- // .. .. ==> 0XF8006040[19:16] = 0x0000000FU
- // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x5
- // .. .. ==> 0XF8006044[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x5
- // .. .. ==> 0XF8006044[7:4] = 0x00000005U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5
- // .. .. ==> 0XF8006044[11:8] = 0x00000005U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x5
- // .. .. ==> 0XF8006044[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x5
- // .. .. ==> 0XF8006044[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF55555U),
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x5
- // .. .. ==> 0XF8006078[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_t_cksrx = 0x5
- // .. .. ==> 0XF8006078[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xbebc
- // .. .. ==> 0XF80060A8[19:0] = 0x0000BEBCU
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000BEBCU
- // .. .. dram_rstn_x1024 = 0x62
- // .. .. ==> 0XF80060A8[27:20] = 0x00000062U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0620BEBCU),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xf5
- // .. .. ==> 0XF80060AC[8:1] = 0x000000F5U
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001EAU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001EAU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000000U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006124[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF800612C[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006134[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006154[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006158[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF800615C[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006160[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006168[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006170[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x11
- // .. .. ==> 0XF80062B0[11:4] = 0x00000011U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000110U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005115U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0x9e
- // .. .. ==> 0XF80062B4[7:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000000FFU VAL : 0x0000009EU
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x11
- // .. .. ==> 0XF80062B4[17:8] = 0x00000011U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001100U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x0000119EU),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B4C[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B4C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B4C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B4C[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B4C[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCI_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B54[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B54[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B54[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B54[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B54[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U),
- // .. reserved_INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE_B = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCI_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B5C[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B5C[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. reserved_SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B60[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B60[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B64[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B64[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
- // .. reserved_DRIVE_P = 0x68
- // .. ==> 0XF8000B68[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. reserved_DRIVE_N = 0x0
- // .. ==> 0XF8000B68[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. reserved_SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. reserved_SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. reserved_GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. reserved_RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x1
- // .. ==> 0XF8000B6C[6:5] = 0x00000001U
- // .. ==> MASK : 0x00000060U VAL : 0x00000020U
- // .. reserved_VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. reserved_REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. reserved_REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reserved_VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reserved_VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reserved_VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reserved_VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reserved_INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reserved_TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reserved_TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reserved_TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. reserved_TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reserved_INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000724[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003F01U ,0x00001601U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000728[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800072C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000730[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000734[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000738[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800073C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000740[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000740[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000744[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000744[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000748[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000748[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800074C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800074C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000750[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000750[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000754[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000754[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000758[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000758[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800075C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800075C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000760[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000760[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000764[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000764[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000768[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000768[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800076C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800076C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000770[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000770[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000774[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000774[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000778[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000778[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800077C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800077C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000780[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000780[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000784[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000784[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000788[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000788[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800078C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800078C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000790[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000790[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000794[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000794[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000798[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000798[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800079C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800079C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A0[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A8[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007AC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007AC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007AC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007B4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007B8[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007BC[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007BC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007CC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D0[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001420U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007D4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D4[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001421U),
- // .. SDIO1_WP_SEL = 57
- // .. ==> 0XF8000834[5:0] = 0x00000039U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000039U
- // .. SDIO1_CD_SEL = 9
- // .. ==> 0XF8000834[21:16] = 0x00000009U
- // .. ==> MASK : 0x003F0000U VAL : 0x00090000U
- // ..
- EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00090039U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_3_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_LVL_INP_EN_0 = 1
- // .. ==> 0XF8000900[3:3] = 0x00000001U
- // .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. USER_LVL_OUT_EN_0 = 1
- // .. ==> 0XF8000900[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. USER_LVL_INP_EN_1 = 1
- // .. ==> 0XF8000900[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. USER_LVL_OUT_EN_1 = 1
- // .. ==> 0XF8000900[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. reserved_FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. reserved_FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. reserved_FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. reserved_FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. reserved_FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. reserved_FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. reserved_FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. reserved_FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. reserved_FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. .. START: AFI2 SECURE REGISTER
- // .. .. FINISH: AFI2 SECURE REGISTER
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_3_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000110[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000114[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000118[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x113
- // .. .. ==> 0XF8000118[21:12] = 0x00000113U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00113000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x00113220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x23
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000023U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00023000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00023000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x31
- // .. ==> 0XF8000128[13:8] = 0x00000031U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003100U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203101U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0xe
- // .. ==> 0XF8000140[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100E01U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xd
- // .. ==> 0XF800014C[13:8] = 0x0000000DU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000D00U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000D01U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000150[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000150[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000150[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001202U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000154[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001203U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000158[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000158[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000158[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xb
- // .. ==> 0XF8000158[13:8] = 0x0000000BU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000B00U
- // ..
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000B03U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF800015C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF800015C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x12
- // .. ==> 0XF800015C[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF800015C[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00101202U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x9
- // .. .. ==> 0XF8000168[13:8] = 0x00000009U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x7
- // .. .. ==> 0XF8000170[13:8] = 0x00000007U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200700U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. SDI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[11:11] = 0x00000001U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. .. SPI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. SPI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FEC84DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_2_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x79
- // .. .. ==> 0XF8006004[11:0] = 0x00000079U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000079U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081079U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x19
- // .. .. ==> 0XF8006014[5:0] = 0x00000019U
- // .. .. ==> MASK : 0x0000003FU VAL : 0x00000019U
- // .. .. reg_ddrc_t_rfc_min = 0x50
- // .. .. ==> 0XF8006014[13:6] = 0x00000050U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001400U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041419U),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x14
- // .. .. ==> 0XF8006018[15:10] = 0x00000014U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005000U
- // .. .. reg_ddrc_t_ras_max = 0x22
- // .. .. ==> 0XF8006018[21:16] = 0x00000022U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00220000U
- // .. .. reg_ddrc_t_ras_min = 0x12
- // .. .. ==> 0XF8006018[26:22] = 0x00000012U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04800000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44A250D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x5
- // .. .. ==> 0XF8006020[7:5] = 0x00000005U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872B0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x156
- // .. .. ==> 0XF8006034[13:4] = 0x00000156U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001560U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011564U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x6
- // .. .. ==> 0XF800603C[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x6
- // .. .. ==> 0XF800603C[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x6
- // .. .. ==> 0XF800603C[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0xf
- // .. .. ==> 0XF8006040[19:16] = 0x0000000FU
- // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x5
- // .. .. ==> 0XF8006044[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x5
- // .. .. ==> 0XF8006044[7:4] = 0x00000005U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5
- // .. .. ==> 0XF8006044[11:8] = 0x00000005U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x5
- // .. .. ==> 0XF8006044[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x5
- // .. .. ==> 0XF8006044[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF55555U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
- // .. .. ==> 0XF8006078[3:0] = 0x00000001U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U
- // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
- // .. .. ==> 0XF8006078[7:4] = 0x00000001U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U
- // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
- // .. .. ==> 0XF8006078[11:8] = 0x00000001U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U
- // .. .. reg_ddrc_t_cksre = 0x5
- // .. .. ==> 0XF8006078[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_t_cksrx = 0x5
- // .. .. ==> 0XF8006078[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_t_ckesr = 0x4
- // .. .. ==> 0XF8006078[25:20] = 0x00000004U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U
- // .. ..
- EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00455111U),
- // .. .. reg_ddrc_t_ckpde = 0x2
- // .. .. ==> 0XF800607C[3:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U
- // .. .. reg_ddrc_t_ckpdx = 0x2
- // .. .. ==> 0XF800607C[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. reg_ddrc_t_ckdpde = 0x2
- // .. .. ==> 0XF800607C[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_ckdpdx = 0x2
- // .. .. ==> 0XF800607C[15:12] = 0x00000002U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U
- // .. .. reg_ddrc_t_ckcsx = 0x3
- // .. .. ==> 0XF800607C[19:16] = 0x00000003U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U
- // .. ..
- EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xbebc
- // .. .. ==> 0XF80060A8[19:0] = 0x0000BEBCU
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000BEBCU
- // .. .. dram_rstn_x1024 = 0x62
- // .. .. ==> 0XF80060A8[27:20] = 0x00000062U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0620BEBCU),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xf5
- // .. .. ==> 0XF80060AC[8:1] = 0x000000F5U
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001EAU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001EAU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006124[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF800612C[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006134[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006154[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006158[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF800615C[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006160[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006168[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006170[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x11
- // .. .. ==> 0XF80062B0[11:4] = 0x00000011U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000110U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005115U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0x9e
- // .. .. ==> 0XF80062B4[7:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000000FFU VAL : 0x0000009EU
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x11
- // .. .. ==> 0XF80062B4[17:8] = 0x00000011U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001100U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x0000119EU),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B4C[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B4C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B4C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B4C[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B4C[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B54[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B54[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B54[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B54[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B54[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B5C[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B5C[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B60[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B60[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B64[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B64[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B68[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B68[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x1
- // .. ==> 0XF8000B6C[6:5] = 0x00000001U
- // .. ==> MASK : 0x00000060U VAL : 0x00000020U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_TEST = 0x0
- // .. ==> 0XF8000B6C[11:10] = 0x00000000U
- // .. ==> MASK : 0x00000C00U VAL : 0x00000000U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000724[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003F01U ,0x00001601U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000728[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800072C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000730[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000734[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000738[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800073C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000740[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000740[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000744[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000744[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000748[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000748[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800074C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800074C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000750[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000750[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000754[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000754[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000758[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000758[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800075C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800075C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000760[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000760[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000764[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000764[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000768[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000768[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800076C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800076C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000770[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000770[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000774[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000774[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000778[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000778[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800077C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800077C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000780[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000780[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000784[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000784[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000788[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000788[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800078C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800078C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000790[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000790[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000794[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000794[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000798[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000798[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800079C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800079C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A0[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A8[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007AC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007AC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007AC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007B4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007B8[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007BC[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007BC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007CC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D0[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001420U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007D4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D4[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001421U),
- // .. SDIO1_WP_SEL = 57
- // .. ==> 0XF8000834[5:0] = 0x00000039U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000039U
- // .. SDIO1_CD_SEL = 9
- // .. ==> 0XF8000834[21:16] = 0x00000009U
- // .. ==> MASK : 0x003F0000U VAL : 0x00090000U
- // ..
- EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00090039U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_2_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_2_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_pll_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: PLL SLCR REGISTERS
- // .. .. START: ARM PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000110[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000110[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x145
- // .. .. ==> 0XF8000110[21:12] = 0x00000145U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
- // .. ..
- EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001452C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x1e
- // .. .. .. ==> 0XF8000100[18:12] = 0x0000001EU
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001E000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. ARM_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000001U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. SRCSEL = 0x0
- // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. .. DIVISOR = 0x2
- // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
- // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U
- // .. .. .. CPU_6OR4XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
- // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. .. .. CPU_3OR2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
- // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U
- // .. .. .. CPU_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
- // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. .. CPU_1XCLKACT = 0x1
- // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
- // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. .. CPU_PERI_CLKACT = 0x1
- // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
- // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
- // .. .. FINISH: ARM PLL INIT
- // .. .. START: DDR PLL INIT
- // .. .. PLL_RES = 0xc
- // .. .. ==> 0XF8000114[7:4] = 0x0000000CU
- // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000114[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x1f4
- // .. .. ==> 0XF8000114[21:12] = 0x000001F4U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U
- // .. ..
- EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001F42C0U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x14
- // .. .. .. ==> 0XF8000104[18:12] = 0x00000014U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00014000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. DDR_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000002U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. .. DDR_3XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. .. DDR_2XCLKACT = 0x1
- // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. .. DDR_3XCLK_DIVISOR = 0x2
- // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
- // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. .. .. DDR_2XCLK_DIVISOR = 0x3
- // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
- // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
- // .. .. FINISH: DDR PLL INIT
- // .. .. START: IO PLL INIT
- // .. .. PLL_RES = 0x2
- // .. .. ==> 0XF8000118[7:4] = 0x00000002U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U
- // .. .. PLL_CP = 0x2
- // .. .. ==> 0XF8000118[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. LOCK_CNT = 0x113
- // .. .. ==> 0XF8000118[21:12] = 0x00000113U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00113000U
- // .. ..
- EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x00113220U),
- // .. .. .. START: UPDATE FB_DIV
- // .. .. .. PLL_FDIV = 0x23
- // .. .. .. ==> 0XF8000108[18:12] = 0x00000023U
- // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00023000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00023000U),
- // .. .. .. FINISH: UPDATE FB_DIV
- // .. .. .. START: BY PASS PLL
- // .. .. .. PLL_BYPASS_FORCE = 1
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
- // .. .. .. FINISH: BY PASS PLL
- // .. .. .. START: ASSERT RESET
- // .. .. .. PLL_RESET = 1
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
- // .. .. .. FINISH: ASSERT RESET
- // .. .. .. START: DEASSERT RESET
- // .. .. .. PLL_RESET = 0
- // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
- // .. .. .. FINISH: DEASSERT RESET
- // .. .. .. START: CHECK PLL STATUS
- // .. .. .. IO_PLL_LOCK = 1
- // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
- // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. ..
- EMIT_MASKPOLL(0XF800010C, 0x00000004U),
- // .. .. .. FINISH: CHECK PLL STATUS
- // .. .. .. START: REMOVE PLL BY PASS
- // .. .. .. PLL_BYPASS_FORCE = 0
- // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
- // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. ..
- EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
- // .. .. .. FINISH: REMOVE PLL BY PASS
- // .. .. FINISH: IO PLL INIT
- // .. FINISH: PLL SLCR REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_clock_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: CLOCK CONTROL SLCR REGISTERS
- // .. CLKACT = 0x1
- // .. ==> 0XF8000128[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. DIVISOR0 = 0x31
- // .. ==> 0XF8000128[13:8] = 0x00000031U
- // .. ==> MASK : 0x00003F00U VAL : 0x00003100U
- // .. DIVISOR1 = 0x2
- // .. ==> 0XF8000128[25:20] = 0x00000002U
- // .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // ..
- EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00203101U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000138[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000138[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
- // .. CLKACT = 0x1
- // .. ==> 0XF8000140[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000140[6:4] = 0x00000000U
- // .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. DIVISOR = 0xe
- // .. ==> 0XF8000140[13:8] = 0x0000000EU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF8000140[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00100E01U),
- // .. CLKACT = 0x1
- // .. ==> 0XF800014C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800014C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xd
- // .. ==> 0XF800014C[13:8] = 0x0000000DU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000D00U
- // ..
- EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000D01U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF8000150[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000150[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000150[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000150[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001202U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000154[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000154[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000154[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0x12
- // .. ==> 0XF8000154[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // ..
- EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001203U),
- // .. CLKACT0 = 0x1
- // .. ==> 0XF8000158[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF8000158[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF8000158[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR = 0xb
- // .. ==> 0XF8000158[13:8] = 0x0000000BU
- // .. ==> MASK : 0x00003F00U VAL : 0x00000B00U
- // ..
- EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000B03U),
- // .. CLKACT0 = 0x0
- // .. ==> 0XF800015C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. CLKACT1 = 0x1
- // .. ==> 0XF800015C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. SRCSEL = 0x0
- // .. ==> 0XF800015C[5:4] = 0x00000000U
- // .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. DIVISOR0 = 0x12
- // .. ==> 0XF800015C[13:8] = 0x00000012U
- // .. ==> MASK : 0x00003F00U VAL : 0x00001200U
- // .. DIVISOR1 = 0x1
- // .. ==> 0XF800015C[25:20] = 0x00000001U
- // .. ==> MASK : 0x03F00000U VAL : 0x00100000U
- // ..
- EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00101202U),
- // .. CAN0_MUX = 0x0
- // .. ==> 0XF8000160[5:0] = 0x00000000U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000000U
- // .. CAN0_REF_SEL = 0x0
- // .. ==> 0XF8000160[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. CAN1_MUX = 0x0
- // .. ==> 0XF8000160[21:16] = 0x00000000U
- // .. ==> MASK : 0x003F0000U VAL : 0x00000000U
- // .. CAN1_REF_SEL = 0x0
- // .. ==> 0XF8000160[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
- // .. .. START: TRACE CLOCK
- // .. .. FINISH: TRACE CLOCK
- // .. .. CLKACT = 0x1
- // .. .. ==> 0XF8000168[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000168[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR = 0x9
- // .. .. ==> 0XF8000168[13:8] = 0x00000009U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
- // .. ..
- EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
- // .. .. SRCSEL = 0x0
- // .. .. ==> 0XF8000170[5:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
- // .. .. DIVISOR0 = 0x7
- // .. .. ==> 0XF8000170[13:8] = 0x00000007U
- // .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U
- // .. .. DIVISOR1 = 0x2
- // .. .. ==> 0XF8000170[25:20] = 0x00000002U
- // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200700U),
- // .. .. CLK_621_TRUE = 0x1
- // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. ..
- EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
- // .. .. DMA_CPU_2XCLKACT = 0x1
- // .. .. ==> 0XF800012C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. USB0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[2:2] = 0x00000001U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. .. USB1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. .. GEM0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[6:6] = 0x00000001U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U
- // .. .. GEM1_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. SDI0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. SDI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[11:11] = 0x00000001U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // .. .. SPI0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. SPI1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. CAN0_CPU_1XCLKACT = 0x0
- // .. .. ==> 0XF800012C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. CAN1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. .. I2C0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[18:18] = 0x00000001U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U
- // .. .. I2C1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. .. UART0_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[20:20] = 0x00000001U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U
- // .. .. UART1_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. GPIO_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[22:22] = 0x00000001U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U
- // .. .. LQSPI_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[23:23] = 0x00000001U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U
- // .. .. SMC_CPU_1XCLKACT = 0x1
- // .. .. ==> 0XF800012C[24:24] = 0x00000001U
- // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
- // .. ..
- EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FEC84DU),
- // .. FINISH: CLOCK CONTROL SLCR REGISTERS
- // .. START: THIS SHOULD BE BLANK
- // .. FINISH: THIS SHOULD BE BLANK
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_ddr_init_data_1_0[] = {
- // START: top
- // .. START: DDR INITIALIZATION
- // .. .. START: LOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0
- // .. .. ==> 0XF8006000[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 0x1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U),
- // .. .. FINISH: LOCK DDR
- // .. .. reg_ddrc_t_rfc_nom_x32 = 0x79
- // .. .. ==> 0XF8006004[11:0] = 0x00000079U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000079U
- // .. .. reg_ddrc_active_ranks = 0x1
- // .. .. ==> 0XF8006004[13:12] = 0x00000001U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U
- // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
- // .. .. ==> 0XF8006004[18:14] = 0x00000000U
- // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_block = 0x1
- // .. .. ==> 0XF8006004[20:19] = 0x00000001U
- // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U
- // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
- // .. .. ==> 0XF8006004[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
- // .. .. ==> 0XF8006004[26:22] = 0x00000000U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_open_bank = 0x0
- // .. .. ==> 0XF8006004[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
- // .. .. ==> 0XF8006004[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081079U),
- // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
- // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
- // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU
- // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
- // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U
- // .. .. reg_ddrc_hpr_xact_run_length = 0xf
- // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
- // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U
- // .. ..
- EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
- // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF800600C[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
- // .. .. ==> 0XF800600C[21:11] = 0x00000002U
- // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U
- // .. .. reg_ddrc_lpr_xact_run_length = 0x8
- // .. .. ==> 0XF800600C[25:22] = 0x00000008U
- // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U
- // .. ..
- EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
- // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
- // .. .. ==> 0XF8006010[10:0] = 0x00000001U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U
- // .. .. reg_ddrc_w_xact_run_length = 0x8
- // .. .. ==> 0XF8006010[14:11] = 0x00000008U
- // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U
- // .. .. reg_ddrc_w_max_starve_x32 = 0x2
- // .. .. ==> 0XF8006010[25:15] = 0x00000002U
- // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U
- // .. ..
- EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
- // .. .. reg_ddrc_t_rc = 0x19
- // .. .. ==> 0XF8006014[5:0] = 0x00000019U
- // .. .. ==> MASK : 0x0000003FU VAL : 0x00000019U
- // .. .. reg_ddrc_t_rfc_min = 0x50
- // .. .. ==> 0XF8006014[13:6] = 0x00000050U
- // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001400U
- // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
- // .. .. ==> 0XF8006014[20:14] = 0x00000010U
- // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x00041419U),
- // .. .. reg_ddrc_wr2pre = 0x12
- // .. .. ==> 0XF8006018[4:0] = 0x00000012U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U
- // .. .. reg_ddrc_powerdown_to_x32 = 0x6
- // .. .. ==> 0XF8006018[9:5] = 0x00000006U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U
- // .. .. reg_ddrc_t_faw = 0x14
- // .. .. ==> 0XF8006018[15:10] = 0x00000014U
- // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005000U
- // .. .. reg_ddrc_t_ras_max = 0x22
- // .. .. ==> 0XF8006018[21:16] = 0x00000022U
- // .. .. ==> MASK : 0x003F0000U VAL : 0x00220000U
- // .. .. reg_ddrc_t_ras_min = 0x12
- // .. .. ==> 0XF8006018[26:22] = 0x00000012U
- // .. .. ==> MASK : 0x07C00000U VAL : 0x04800000U
- // .. .. reg_ddrc_t_cke = 0x4
- // .. .. ==> 0XF8006018[31:28] = 0x00000004U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44A250D2U),
- // .. .. reg_ddrc_write_latency = 0x5
- // .. .. ==> 0XF800601C[4:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U
- // .. .. reg_ddrc_rd2wr = 0x7
- // .. .. ==> 0XF800601C[9:5] = 0x00000007U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U
- // .. .. reg_ddrc_wr2rd = 0xe
- // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
- // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U
- // .. .. reg_ddrc_t_xp = 0x4
- // .. .. ==> 0XF800601C[19:15] = 0x00000004U
- // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U
- // .. .. reg_ddrc_pad_pd = 0x0
- // .. .. ==> 0XF800601C[22:20] = 0x00000000U
- // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U
- // .. .. reg_ddrc_rd2pre = 0x4
- // .. .. ==> 0XF800601C[27:23] = 0x00000004U
- // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U
- // .. .. reg_ddrc_t_rcd = 0x7
- // .. .. ==> 0XF800601C[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
- // .. .. reg_ddrc_t_ccd = 0x4
- // .. .. ==> 0XF8006020[4:2] = 0x00000004U
- // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U
- // .. .. reg_ddrc_t_rrd = 0x5
- // .. .. ==> 0XF8006020[7:5] = 0x00000005U
- // .. .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. .. reg_ddrc_refresh_margin = 0x2
- // .. .. ==> 0XF8006020[11:8] = 0x00000002U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
- // .. .. reg_ddrc_t_rp = 0x7
- // .. .. ==> 0XF8006020[15:12] = 0x00000007U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U
- // .. .. reg_ddrc_refresh_to_x32 = 0x8
- // .. .. ==> 0XF8006020[20:16] = 0x00000008U
- // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U
- // .. .. reg_ddrc_sdram = 0x1
- // .. .. ==> 0XF8006020[21:21] = 0x00000001U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U
- // .. .. reg_ddrc_mobile = 0x0
- // .. .. ==> 0XF8006020[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. reg_ddrc_clock_stop_en = 0x0
- // .. .. ==> 0XF8006020[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. reg_ddrc_read_latency = 0x7
- // .. .. ==> 0XF8006020[28:24] = 0x00000007U
- // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U
- // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
- // .. .. ==> 0XF8006020[29:29] = 0x00000001U
- // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U
- // .. .. reg_ddrc_dis_pad_pd = 0x0
- // .. .. ==> 0XF8006020[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_ddrc_loopback = 0x0
- // .. .. ==> 0XF8006020[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872B0U),
- // .. .. reg_ddrc_en_2t_timing_mode = 0x0
- // .. .. ==> 0XF8006024[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_prefer_write = 0x0
- // .. .. ==> 0XF8006024[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_max_rank_rd = 0xf
- // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
- // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU
- // .. .. reg_ddrc_mr_wr = 0x0
- // .. .. ==> 0XF8006024[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_addr = 0x0
- // .. .. ==> 0XF8006024[8:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_data = 0x0
- // .. .. ==> 0XF8006024[24:9] = 0x00000000U
- // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U
- // .. .. ddrc_reg_mr_wr_busy = 0x0
- // .. .. ==> 0XF8006024[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_type = 0x0
- // .. .. ==> 0XF8006024[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. .. reg_ddrc_mr_rdata_valid = 0x0
- // .. .. ==> 0XF8006024[27:27] = 0x00000000U
- // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
- // .. .. reg_ddrc_final_wait_x32 = 0x7
- // .. .. ==> 0XF8006028[6:0] = 0x00000007U
- // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U
- // .. .. reg_ddrc_pre_ocd_x32 = 0x0
- // .. .. ==> 0XF8006028[10:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U
- // .. .. reg_ddrc_t_mrd = 0x4
- // .. .. ==> 0XF8006028[13:11] = 0x00000004U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U
- // .. ..
- EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
- // .. .. reg_ddrc_emr2 = 0x8
- // .. .. ==> 0XF800602C[15:0] = 0x00000008U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U
- // .. .. reg_ddrc_emr3 = 0x0
- // .. .. ==> 0XF800602C[31:16] = 0x00000000U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
- // .. .. reg_ddrc_mr = 0x930
- // .. .. ==> 0XF8006030[15:0] = 0x00000930U
- // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U
- // .. .. reg_ddrc_emr = 0x4
- // .. .. ==> 0XF8006030[31:16] = 0x00000004U
- // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U
- // .. ..
- EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
- // .. .. reg_ddrc_burst_rdwr = 0x4
- // .. .. ==> 0XF8006034[3:0] = 0x00000004U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U
- // .. .. reg_ddrc_pre_cke_x1024 = 0x156
- // .. .. ==> 0XF8006034[13:4] = 0x00000156U
- // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001560U
- // .. .. reg_ddrc_post_cke_x1024 = 0x1
- // .. .. ==> 0XF8006034[25:16] = 0x00000001U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U
- // .. .. reg_ddrc_burstchop = 0x0
- // .. .. ==> 0XF8006034[28:28] = 0x00000000U
- // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011564U),
- // .. .. reg_ddrc_force_low_pri_n = 0x0
- // .. .. ==> 0XF8006038[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_dq = 0x0
- // .. .. ==> 0XF8006038[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_debug_mode = 0x0
- // .. .. ==> 0XF8006038[6:6] = 0x00000000U
- // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. .. reg_phy_wr_level_start = 0x0
- // .. .. ==> 0XF8006038[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_phy_rd_level_start = 0x0
- // .. .. ==> 0XF8006038[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_dq0_wait_t = 0x0
- // .. .. ==> 0XF8006038[12:9] = 0x00000000U
- // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
- // .. .. reg_ddrc_addrmap_bank_b0 = 0x6
- // .. .. ==> 0XF800603C[3:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U
- // .. .. reg_ddrc_addrmap_bank_b1 = 0x6
- // .. .. ==> 0XF800603C[7:4] = 0x00000006U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U
- // .. .. reg_ddrc_addrmap_bank_b2 = 0x6
- // .. .. ==> 0XF800603C[11:8] = 0x00000006U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U
- // .. .. reg_ddrc_addrmap_col_b5 = 0x0
- // .. .. ==> 0XF800603C[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b6 = 0x0
- // .. .. ==> 0XF800603C[19:16] = 0x00000000U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U),
- // .. .. reg_ddrc_addrmap_col_b2 = 0x0
- // .. .. ==> 0XF8006040[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b3 = 0x0
- // .. .. ==> 0XF8006040[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b4 = 0x0
- // .. .. ==> 0XF8006040[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b7 = 0x0
- // .. .. ==> 0XF8006040[15:12] = 0x00000000U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U
- // .. .. reg_ddrc_addrmap_col_b8 = 0xf
- // .. .. ==> 0XF8006040[19:16] = 0x0000000FU
- // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U
- // .. .. reg_ddrc_addrmap_col_b9 = 0xf
- // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_col_b10 = 0xf
- // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. .. reg_ddrc_addrmap_col_b11 = 0xf
- // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
- // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U),
- // .. .. reg_ddrc_addrmap_row_b0 = 0x5
- // .. .. ==> 0XF8006044[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_addrmap_row_b1 = 0x5
- // .. .. ==> 0XF8006044[7:4] = 0x00000005U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U
- // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5
- // .. .. ==> 0XF8006044[11:8] = 0x00000005U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U
- // .. .. reg_ddrc_addrmap_row_b12 = 0x5
- // .. .. ==> 0XF8006044[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. .. reg_ddrc_addrmap_row_b13 = 0x5
- // .. .. ==> 0XF8006044[19:16] = 0x00000005U
- // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U
- // .. .. reg_ddrc_addrmap_row_b14 = 0xf
- // .. .. ==> 0XF8006044[23:20] = 0x0000000FU
- // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U
- // .. .. reg_ddrc_addrmap_row_b15 = 0xf
- // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
- // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0FF55555U),
- // .. .. reg_ddrc_rank0_rd_odt = 0x0
- // .. .. ==> 0XF8006048[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_rank0_wr_odt = 0x1
- // .. .. ==> 0XF8006048[5:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U
- // .. .. reg_ddrc_rank1_rd_odt = 0x1
- // .. .. ==> 0XF8006048[8:6] = 0x00000001U
- // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U
- // .. .. reg_ddrc_rank1_wr_odt = 0x1
- // .. .. ==> 0XF8006048[11:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U
- // .. .. reg_phy_rd_local_odt = 0x0
- // .. .. ==> 0XF8006048[13:12] = 0x00000000U
- // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U
- // .. .. reg_phy_wr_local_odt = 0x3
- // .. .. ==> 0XF8006048[15:14] = 0x00000003U
- // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U
- // .. .. reg_phy_idle_local_odt = 0x3
- // .. .. ==> 0XF8006048[17:16] = 0x00000003U
- // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U
- // .. .. reg_ddrc_rank2_rd_odt = 0x0
- // .. .. ==> 0XF8006048[20:18] = 0x00000000U
- // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank2_wr_odt = 0x0
- // .. .. ==> 0XF8006048[23:21] = 0x00000000U
- // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_rd_odt = 0x0
- // .. .. ==> 0XF8006048[26:24] = 0x00000000U
- // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. .. reg_ddrc_rank3_wr_odt = 0x0
- // .. .. ==> 0XF8006048[29:27] = 0x00000000U
- // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
- // .. .. reg_phy_rd_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_wr_cmd_to_data = 0x0
- // .. .. ==> 0XF8006050[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_phy_rdc_we_to_re_delay = 0x8
- // .. .. ==> 0XF8006050[11:8] = 0x00000008U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U
- // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
- // .. .. ==> 0XF8006050[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_phy_use_fixed_re = 0x1
- // .. .. ==> 0XF8006050[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
- // .. .. ==> 0XF8006050[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
- // .. .. ==> 0XF8006050[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_phy_clk_stall_level = 0x0
- // .. .. ==> 0XF8006050[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[27:24] = 0x00000007U
- // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U
- // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
- // .. .. ==> 0XF8006050[31:28] = 0x00000007U
- // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
- // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
- // .. .. ==> 0XF8006058[7:0] = 0x00000001U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U
- // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
- // .. .. ==> 0XF8006058[15:8] = 0x00000001U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U
- // .. .. reg_ddrc_dis_dll_calib = 0x0
- // .. .. ==> 0XF8006058[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
- // .. .. reg_ddrc_rd_odt_delay = 0x3
- // .. .. ==> 0XF800605C[3:0] = 0x00000003U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U
- // .. .. reg_ddrc_wr_odt_delay = 0x0
- // .. .. ==> 0XF800605C[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. .. reg_ddrc_rd_odt_hold = 0x0
- // .. .. ==> 0XF800605C[11:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U
- // .. .. reg_ddrc_wr_odt_hold = 0x5
- // .. .. ==> 0XF800605C[15:12] = 0x00000005U
- // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
- // .. .. reg_ddrc_pageclose = 0x0
- // .. .. ==> 0XF8006060[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_lpr_num_entries = 0x1f
- // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
- // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU
- // .. .. reg_ddrc_auto_pre_en = 0x0
- // .. .. ==> 0XF8006060[7:7] = 0x00000000U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. .. reg_ddrc_refresh_update_level = 0x0
- // .. .. ==> 0XF8006060[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_wc = 0x0
- // .. .. ==> 0XF8006060[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_collision_page_opt = 0x0
- // .. .. ==> 0XF8006060[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_ddrc_selfref_en = 0x0
- // .. .. ==> 0XF8006060[12:12] = 0x00000000U
- // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
- // .. .. reg_ddrc_go2critical_hysteresis = 0x0
- // .. .. ==> 0XF8006064[12:5] = 0x00000000U
- // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U
- // .. .. reg_arb_go2critical_en = 0x1
- // .. .. ==> 0XF8006064[17:17] = 0x00000001U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U
- // .. ..
- EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
- // .. .. reg_ddrc_wrlvl_ww = 0x41
- // .. .. ==> 0XF8006068[7:0] = 0x00000041U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U
- // .. .. reg_ddrc_rdlvl_rr = 0x41
- // .. .. ==> 0XF8006068[15:8] = 0x00000041U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U
- // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
- // .. .. ==> 0XF8006068[25:16] = 0x00000028U
- // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U
- // .. ..
- EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
- // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
- // .. .. ==> 0XF800606C[7:0] = 0x00000010U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U
- // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
- // .. .. ==> 0XF800606C[15:8] = 0x00000016U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U
- // .. ..
- EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
- // .. .. refresh_timer0_start_value_x32 = 0x0
- // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U
- // .. .. refresh_timer1_start_value_x32 = 0x8
- // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
- // .. .. reg_ddrc_dis_auto_zq = 0x0
- // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_ddr3 = 0x1
- // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. reg_ddrc_t_mod = 0x200
- // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
- // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U
- // .. .. reg_ddrc_t_zq_long_nop = 0x200
- // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U
- // .. .. reg_ddrc_t_zq_short_nop = 0x40
- // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
- // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
- // .. .. t_zq_short_interval_x1024 = 0xbebc
- // .. .. ==> 0XF80060A8[19:0] = 0x0000BEBCU
- // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000BEBCU
- // .. .. dram_rstn_x1024 = 0x62
- // .. .. ==> 0XF80060A8[27:20] = 0x00000062U
- // .. .. ==> MASK : 0x0FF00000U VAL : 0x06200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0620BEBCU),
- // .. .. deeppowerdown_en = 0x0
- // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. deeppowerdown_to_x1024 = 0xf5
- // .. .. ==> 0XF80060AC[8:1] = 0x000000F5U
- // .. .. ==> MASK : 0x000001FEU VAL : 0x000001EAU
- // .. ..
- EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001EAU),
- // .. .. dfi_wrlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
- // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU
- // .. .. dfi_rdlvl_max_x1024 = 0xfff
- // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
- // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U
- // .. .. ddrc_reg_twrlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. ddrc_reg_trdlvl_max_error = 0x0
- // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. reg_ddrc_dfi_wr_level_en = 0x1
- // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
- // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U
- // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
- // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U
- // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
- // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
- // .. .. reg_ddrc_2t_delay = 0x0
- // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
- // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U
- // .. .. reg_ddrc_skip_ocd = 0x1
- // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. .. reg_ddrc_dis_pre_bypass = 0x0
- // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
- // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
- // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U
- // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
- // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
- // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U
- // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
- // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
- // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U
- // .. ..
- EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
- // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
- // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
- // .. .. CORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. ECC_CORRECTED_BIT_NUM = 0x0
- // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
- // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
- // .. .. UNCORR_ECC_LOG_VALID = 0x0
- // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
- // .. .. STAT_NUM_CORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
- // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U
- // .. .. STAT_NUM_UNCORR_ERR = 0x0
- // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
- // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
- // .. .. reg_ddrc_ecc_mode = 0x0
- // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_scrub = 0x1
- // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U
- // .. ..
- EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
- // .. .. reg_phy_dif_on = 0x0
- // .. .. ==> 0XF8006114[3:0] = 0x00000000U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U
- // .. .. reg_phy_dif_off = 0x0
- // .. .. ==> 0XF8006114[7:4] = 0x00000000U
- // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF8006118[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006118[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006118[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006118[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006118[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006118[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006118[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x1
- // .. .. ==> 0XF800611C[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF800611C[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF800611C[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF800611C[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF800611C[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF800611C[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF800611C[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006120[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006120[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006120[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006120[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006120[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006120[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006120[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_data_slice_in_use = 0x0
- // .. .. ==> 0XF8006124[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_rdlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_wrlvl_inc_mode = 0x0
- // .. .. ==> 0XF8006124[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_tx = 0x0
- // .. .. ==> 0XF8006124[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_board_lpbk_rx = 0x0
- // .. .. ==> 0XF8006124[5:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. .. reg_phy_bist_shift_dq = 0x0
- // .. .. ==> 0XF8006124[14:6] = 0x00000000U
- // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U
- // .. .. reg_phy_bist_err_clr = 0x0
- // .. .. ==> 0XF8006124[23:15] = 0x00000000U
- // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U
- // .. .. reg_phy_dq_offset = 0x40
- // .. .. ==> 0XF8006124[30:24] = 0x00000040U
- // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF800612C[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF800612C[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006130[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006134[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006134[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_wrlvl_init_ratio = 0x0
- // .. .. ==> 0XF8006138[9:0] = 0x00000000U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U
- // .. .. reg_phy_gatelvl_init_ratio = 0xa0
- // .. .. ==> 0XF8006138[19:10] = 0x000000A0U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U
- // .. ..
- EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00028000U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006140[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006140[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006140[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006144[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006144[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006144[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF8006148[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006148[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006148[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
- // .. .. ==> 0XF800614C[9:0] = 0x00000035U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U
- // .. .. reg_phy_rd_dqs_slave_force = 0x0
- // .. .. ==> 0XF800614C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_rd_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800614C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006154[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006154[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006154[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006158[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006158[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006158[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF800615C[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF800615C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF800615C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_wr_dqs_slave_ratio = 0x80
- // .. .. ==> 0XF8006160[9:0] = 0x00000080U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U
- // .. .. reg_phy_wr_dqs_slave_force = 0x0
- // .. .. ==> 0XF8006160[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_dqs_slave_delay = 0x0
- // .. .. ==> 0XF8006160[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006168[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006168[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006168[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF800616C[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF800616C[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006170[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006170[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006170[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
- // .. .. ==> 0XF8006174[10:0] = 0x000000F5U
- // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U
- // .. .. reg_phy_fifo_we_in_force = 0x0
- // .. .. ==> 0XF8006174[11:11] = 0x00000000U
- // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. .. reg_phy_fifo_we_in_delay = 0x0
- // .. .. ==> 0XF8006174[20:12] = 0x00000000U
- // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F5U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF800617C[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF800617C[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF800617C[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006180[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006180[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006180[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006184[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006184[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006184[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_wr_data_slave_ratio = 0xc0
- // .. .. ==> 0XF8006188[9:0] = 0x000000C0U
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U
- // .. .. reg_phy_wr_data_slave_force = 0x0
- // .. .. ==> 0XF8006188[10:10] = 0x00000000U
- // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. .. reg_phy_wr_data_slave_delay = 0x0
- // .. .. ==> 0XF8006188[19:11] = 0x00000000U
- // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U),
- // .. .. reg_phy_loopback = 0x0
- // .. .. ==> 0XF8006190[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_phy_bl2 = 0x0
- // .. .. ==> 0XF8006190[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_phy_at_spd_atpg = 0x0
- // .. .. ==> 0XF8006190[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_phy_bist_enable = 0x0
- // .. .. ==> 0XF8006190[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. reg_phy_bist_force_err = 0x0
- // .. .. ==> 0XF8006190[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. reg_phy_bist_mode = 0x0
- // .. .. ==> 0XF8006190[6:5] = 0x00000000U
- // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. .. reg_phy_invert_clkout = 0x1
- // .. .. ==> 0XF8006190[7:7] = 0x00000001U
- // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
- // .. .. ==> 0XF8006190[8:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. .. reg_phy_sel_logic = 0x0
- // .. .. ==> 0XF8006190[9:9] = 0x00000000U
- // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_ratio = 0x100
- // .. .. ==> 0XF8006190[19:10] = 0x00000100U
- // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U
- // .. .. reg_phy_ctrl_slave_force = 0x0
- // .. .. ==> 0XF8006190[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006190[27:21] = 0x00000000U
- // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U
- // .. .. reg_phy_use_rank0_delays = 0x1
- // .. .. ==> 0XF8006190[28:28] = 0x00000001U
- // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U
- // .. .. reg_phy_lpddr = 0x0
- // .. .. ==> 0XF8006190[29:29] = 0x00000000U
- // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // .. .. reg_phy_cmd_latency = 0x0
- // .. .. ==> 0XF8006190[30:30] = 0x00000000U
- // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U
- // .. .. reg_phy_int_lpbk = 0x0
- // .. .. ==> 0XF8006190[31:31] = 0x00000000U
- // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
- // .. .. reg_phy_wr_rl_delay = 0x2
- // .. .. ==> 0XF8006194[4:0] = 0x00000002U
- // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U
- // .. .. reg_phy_rd_rl_delay = 0x4
- // .. .. ==> 0XF8006194[9:5] = 0x00000004U
- // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U
- // .. .. reg_phy_dll_lock_diff = 0xf
- // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
- // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U
- // .. .. reg_phy_use_wr_level = 0x1
- // .. .. ==> 0XF8006194[14:14] = 0x00000001U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
- // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
- // .. .. ==> 0XF8006194[15:15] = 0x00000001U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U
- // .. .. reg_phy_use_rd_data_eye_level = 0x1
- // .. .. ==> 0XF8006194[16:16] = 0x00000001U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U
- // .. .. reg_phy_dis_calib_rst = 0x0
- // .. .. ==> 0XF8006194[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_phy_ctrl_slave_delay = 0x0
- // .. .. ==> 0XF8006194[19:18] = 0x00000000U
- // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
- // .. .. reg_arb_page_addr_mask = 0x0
- // .. .. ==> 0XF8006204[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006208[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006208[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006208[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006208[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF800620C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF800620C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF800620C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF800620C[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006210[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006210[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006210[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006210[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_wr_portn = 0x3ff
- // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_wr_portn = 0x0
- // .. .. ==> 0XF8006214[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_wr_portn = 0x0
- // .. .. ==> 0XF8006214[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_wr_portn = 0x0
- // .. .. ==> 0XF8006214[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_dis_rmw_portn = 0x1
- // .. .. ==> 0XF8006214[19:19] = 0x00000001U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // .. ..
- EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006218[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006218[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006218[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006218[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF800621C[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF800621C[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF800621C[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF800621C[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006220[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006220[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006220[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006220[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_arb_pri_rd_portn = 0x3ff
- // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
- // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU
- // .. .. reg_arb_disable_aging_rd_portn = 0x0
- // .. .. ==> 0XF8006224[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. .. reg_arb_disable_urgent_rd_portn = 0x0
- // .. .. ==> 0XF8006224[17:17] = 0x00000000U
- // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. .. reg_arb_dis_page_match_rd_portn = 0x0
- // .. .. ==> 0XF8006224[18:18] = 0x00000000U
- // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U
- // .. .. reg_arb_set_hpr_rd_portn = 0x0
- // .. .. ==> 0XF8006224[19:19] = 0x00000000U
- // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
- // .. .. reg_ddrc_lpddr2 = 0x0
- // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. reg_ddrc_per_bank_refresh = 0x0
- // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_derate_enable = 0x0
- // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. reg_ddrc_mr4_margin = 0x0
- // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
- // .. .. reg_ddrc_mr4_read_interval = 0x0
- // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
- // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
- // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
- // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U
- // .. .. reg_ddrc_idle_after_reset_x32 = 0x11
- // .. .. ==> 0XF80062B0[11:4] = 0x00000011U
- // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000110U
- // .. .. reg_ddrc_t_mrw = 0x5
- // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
- // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U
- // .. ..
- EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005115U),
- // .. .. reg_ddrc_max_auto_init_x1024 = 0x9e
- // .. .. ==> 0XF80062B4[7:0] = 0x0000009EU
- // .. .. ==> MASK : 0x000000FFU VAL : 0x0000009EU
- // .. .. reg_ddrc_dev_zqinit_x32 = 0x11
- // .. .. ==> 0XF80062B4[17:8] = 0x00000011U
- // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001100U
- // .. ..
- EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x0000119EU),
- // .. .. START: POLL ON DCI STATUS
- // .. .. DONE = 1
- // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
- // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U
- // .. ..
- EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
- // .. .. FINISH: POLL ON DCI STATUS
- // .. .. START: UNLOCK DDR
- // .. .. reg_ddrc_soft_rstb = 0x1
- // .. .. ==> 0XF8006000[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. reg_ddrc_powerdown_en = 0x0
- // .. .. ==> 0XF8006000[1:1] = 0x00000000U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. .. reg_ddrc_data_bus_width = 0x1
- // .. .. ==> 0XF8006000[3:2] = 0x00000001U
- // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U
- // .. .. reg_ddrc_burst8_refresh = 0x0
- // .. .. ==> 0XF8006000[6:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U
- // .. .. reg_ddrc_rdwr_idle_gap = 1
- // .. .. ==> 0XF8006000[13:7] = 0x00000001U
- // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U
- // .. .. reg_ddrc_dis_rd_bypass = 0x0
- // .. .. ==> 0XF8006000[14:14] = 0x00000000U
- // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_act_bypass = 0x0
- // .. .. ==> 0XF8006000[15:15] = 0x00000000U
- // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
- // .. .. reg_ddrc_dis_auto_refresh = 0x0
- // .. .. ==> 0XF8006000[16:16] = 0x00000000U
- // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U),
- // .. .. FINISH: UNLOCK DDR
- // .. .. START: CHECK DDR STATUS
- // .. .. ddrc_reg_operating_mode = 1
- // .. .. ==> 0XF8006054[2:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U
- // .. ..
- EMIT_MASKPOLL(0XF8006054, 0x00000007U),
- // .. .. FINISH: CHECK DDR STATUS
- // .. FINISH: DDR INITIALIZATION
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_mio_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: OCM REMAPPING
- // .. FINISH: OCM REMAPPING
- // .. START: DDRIOB SETTINGS
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B40[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B40[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B40[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B40[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B40[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B40[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B40[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B40[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B44[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B44[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B44[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B44[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B44[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B44[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B44[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B44[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B48[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x1
- // .. ==> 0XF8000B48[2:1] = 0x00000001U
- // .. ==> MASK : 0x00000006U VAL : 0x00000002U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B48[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B48[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B48[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B48[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B48[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B48[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B4C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B4C[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B4C[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B4C[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B4C[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B4C[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B4C[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B50[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x2
- // .. ==> 0XF8000B50[2:1] = 0x00000002U
- // .. ==> MASK : 0x00000006U VAL : 0x00000004U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B50[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x1
- // .. ==> 0XF8000B50[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. DCR_TYPE = 0x3
- // .. ==> 0XF8000B50[6:5] = 0x00000003U
- // .. ==> MASK : 0x00000060U VAL : 0x00000060U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B50[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B50[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B50[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B54[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B54[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B54[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B54[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B54[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x0
- // .. ==> 0XF8000B54[10:9] = 0x00000000U
- // .. ==> MASK : 0x00000600U VAL : 0x00000000U
- // .. PULLUP_EN = 0x1
- // .. ==> 0XF8000B54[11:11] = 0x00000001U
- // .. ==> MASK : 0x00000800U VAL : 0x00000800U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U),
- // .. INP_POWER = 0x0
- // .. ==> 0XF8000B58[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. INP_TYPE = 0x0
- // .. ==> 0XF8000B58[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. DCI_UPDATE = 0x0
- // .. ==> 0XF8000B58[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. TERM_EN = 0x0
- // .. ==> 0XF8000B58[4:4] = 0x00000000U
- // .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. DCR_TYPE = 0x0
- // .. ==> 0XF8000B58[6:5] = 0x00000000U
- // .. ==> MASK : 0x00000060U VAL : 0x00000000U
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B58[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. OUTPUT_EN = 0x3
- // .. ==> 0XF8000B58[10:9] = 0x00000003U
- // .. ==> MASK : 0x00000600U VAL : 0x00000600U
- // .. PULLUP_EN = 0x0
- // .. ==> 0XF8000B58[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B5C[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B5C[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x3
- // .. ==> 0XF8000B5C[18:14] = 0x00000003U
- // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U
- // .. SLEW_N = 0x3
- // .. ==> 0XF8000B5C[23:19] = 0x00000003U
- // .. ==> MASK : 0x00F80000U VAL : 0x00180000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B5C[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B5C[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B60[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B60[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B60[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B60[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B60[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B60[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B64[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B64[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B64[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B64[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B64[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B64[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U),
- // .. DRIVE_P = 0x68
- // .. ==> 0XF8000B68[6:0] = 0x00000068U
- // .. ==> MASK : 0x0000007FU VAL : 0x00000068U
- // .. DRIVE_N = 0x0
- // .. ==> 0XF8000B68[13:7] = 0x00000000U
- // .. ==> MASK : 0x00003F80U VAL : 0x00000000U
- // .. SLEW_P = 0x6
- // .. ==> 0XF8000B68[18:14] = 0x00000006U
- // .. ==> MASK : 0x0007C000U VAL : 0x00018000U
- // .. SLEW_N = 0x1f
- // .. ==> 0XF8000B68[23:19] = 0x0000001FU
- // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U
- // .. GTL = 0x0
- // .. ==> 0XF8000B68[26:24] = 0x00000000U
- // .. ==> MASK : 0x07000000U VAL : 0x00000000U
- // .. RTERM = 0x0
- // .. ==> 0XF8000B68[31:27] = 0x00000000U
- // .. ==> MASK : 0xF8000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U),
- // .. VREF_INT_EN = 0x0
- // .. ==> 0XF8000B6C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. VREF_SEL = 0x0
- // .. ==> 0XF8000B6C[4:1] = 0x00000000U
- // .. ==> MASK : 0x0000001EU VAL : 0x00000000U
- // .. VREF_EXT_EN = 0x1
- // .. ==> 0XF8000B6C[6:5] = 0x00000001U
- // .. ==> MASK : 0x00000060U VAL : 0x00000020U
- // .. VREF_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[8:7] = 0x00000000U
- // .. ==> MASK : 0x00000180U VAL : 0x00000000U
- // .. REFIO_EN = 0x1
- // .. ==> 0XF8000B6C[9:9] = 0x00000001U
- // .. ==> MASK : 0x00000200U VAL : 0x00000200U
- // .. REFIO_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DRST_B_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. CKE_PULLUP_EN = 0x0
- // .. ==> 0XF8000B6C[14:14] = 0x00000000U
- // .. ==> MASK : 0x00004000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000220U),
- // .. .. START: ASSERT RESET
- // .. .. RESET = 1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
- // .. .. FINISH: ASSERT RESET
- // .. .. START: DEASSERT RESET
- // .. .. RESET = 0
- // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
- // .. .. FINISH: DEASSERT RESET
- // .. .. RESET = 0x1
- // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
- // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. .. ENABLE = 0x1
- // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
- // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. .. VRP_TRI = 0x0
- // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
- // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. .. VRN_TRI = 0x0
- // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
- // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. .. VRP_OUT = 0x0
- // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
- // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U
- // .. .. VRN_OUT = 0x1
- // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
- // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U
- // .. .. NREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
- // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. .. NREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
- // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U
- // .. .. NREF_OPT4 = 0x1
- // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
- // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U
- // .. .. PREF_OPT1 = 0x0
- // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
- // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U
- // .. .. PREF_OPT2 = 0x0
- // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
- // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U
- // .. .. UPDATE_CONTROL = 0x0
- // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
- // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. .. INIT_COMPLETE = 0x0
- // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
- // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. .. TST_CLK = 0x0
- // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
- // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. .. TST_HLN = 0x0
- // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
- // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. .. TST_HLP = 0x0
- // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
- // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. .. TST_RST = 0x0
- // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
- // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U
- // .. .. INT_DCI_EN = 0x0
- // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
- // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U
- // .. ..
- EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
- // .. FINISH: DDRIOB SETTINGS
- // .. START: MIO PROGRAMMING
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000700[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000700[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000700[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000700[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000700[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000700[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000700[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000700[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000700[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00001600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000704[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000704[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000704[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000704[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000704[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000704[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000704[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000704[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000704[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000708[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000708[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000708[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000708[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000708[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000708[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000708[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000708[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000708[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800070C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800070C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800070C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800070C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800070C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800070C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800070C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800070C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800070C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000710[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000710[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000710[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000710[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000710[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000710[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000710[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000710[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000710[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000714[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000714[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000714[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000714[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000714[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000714[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000714[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000714[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000714[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000718[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000718[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000718[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000718[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000718[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000718[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000718[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000718[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000718[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800071C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800071C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800071C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800071C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800071C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800071C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800071C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF800071C[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800071C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000720[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000720[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000720[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000720[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000720[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000720[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000720[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 0
- // .. ==> 0XF8000720[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000720[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000600U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000724[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. Speed = 0
- // .. ==> 0XF8000724[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000724[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000724[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000724[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000724, 0x00003F01U ,0x00001601U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000728[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000728[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000728[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000728[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000728[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000728[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000728[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000728[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000728[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800072C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800072C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800072C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800072C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800072C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800072C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800072C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800072C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800072C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000730[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000730[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000730[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000730[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000730[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000730[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000730[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000730[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000730[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000734[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000734[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000734[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000734[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000734[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000734[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000734[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000734[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000734[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000738[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000738[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF8000738[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000738[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF8000738[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF8000738[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF8000738[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF8000738[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000738[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800073C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800073C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF800073C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800073C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 4
- // .. ==> 0XF800073C[7:5] = 0x00000004U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000080U
- // .. Speed = 0
- // .. ==> 0XF800073C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 3
- // .. ==> 0XF800073C[11:9] = 0x00000003U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000600U
- // .. PULLUP = 1
- // .. ==> 0XF800073C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800073C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00001680U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000740[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000740[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000740[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000740[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000740[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000740[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000740[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000740[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000740[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000744[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000744[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000744[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000744[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000744[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000744[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000744[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000744[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000744[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000748[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000748[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000748[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000748[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000748[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000748[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000748[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000748[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000748[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800074C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF800074C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800074C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800074C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800074C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800074C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800074C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800074C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800074C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000750[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000750[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000750[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000750[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000750[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000750[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000750[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000750[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000750[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000754[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 1
- // .. ==> 0XF8000754[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000754[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000754[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000754[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000754[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000754[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000754[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000754[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001402U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000758[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000758[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000758[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000758[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000758[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000758[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000758[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000758[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000758[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800075C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800075C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800075C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800075C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800075C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800075C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800075C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800075C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800075C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000760[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000760[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000760[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000760[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000760[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000760[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000760[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000760[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000760[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000764[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000764[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000764[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000764[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000764[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000764[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000764[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000764[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000764[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000768[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF8000768[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF8000768[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF8000768[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000768[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000768[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000768[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000768[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000768[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800076C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 1
- // .. ==> 0XF800076C[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. L1_SEL = 0
- // .. ==> 0XF800076C[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF800076C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800076C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800076C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800076C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800076C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800076C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00001403U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000770[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000770[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000770[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000770[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000770[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000770[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000770[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000770[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000770[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000774[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000774[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000774[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000774[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000774[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000774[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000774[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000774[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000774[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000778[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000778[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000778[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000778[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000778[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000778[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000778[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000778[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000778[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF800077C[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF800077C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800077C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800077C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800077C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800077C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800077C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800077C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800077C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000780[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000780[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000780[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000780[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000780[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000780[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000780[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000780[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000780[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000784[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000784[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000784[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000784[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000784[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000784[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000784[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000784[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000784[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000788[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000788[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000788[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000788[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000788[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000788[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000788[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000788[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000788[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800078C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800078C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800078C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800078C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800078C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800078C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800078C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800078C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800078C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF8000790[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF8000790[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000790[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000790[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000790[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000790[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000790[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000790[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000790[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001405U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000794[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000794[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000794[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000794[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000794[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000794[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000794[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000794[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000794[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF8000798[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF8000798[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF8000798[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF8000798[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF8000798[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF8000798[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF8000798[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF8000798[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF8000798[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF800079C[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF800079C[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 1
- // .. ==> 0XF800079C[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. L2_SEL = 0
- // .. ==> 0XF800079C[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF800079C[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF800079C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF800079C[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF800079C[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF800079C[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001404U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A0[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007A8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007A8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007A8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007A8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007A8[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007A8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007A8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007A8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007A8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007AC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007AC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007AC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007AC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007AC[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007AC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007AC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007AC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007AC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 0
- // .. ==> 0XF80007B0[7:5] = 0x00000000U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000000U
- // .. Speed = 0
- // .. ==> 0XF80007B0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00001400U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007B4[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 5
- // .. ==> 0XF80007B4[7:5] = 0x00000005U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000A0U
- // .. Speed = 0
- // .. ==> 0XF80007B4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x000014A0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007B8[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007B8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007B8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007B8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007B8[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007B8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007B8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007B8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007B8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007BC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007BC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007BC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007BC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007BC[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007BC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007BC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007BC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007BC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C0[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000014E0U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007C4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 7
- // .. ==> 0XF80007C4[7:5] = 0x00000007U
- // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U
- // .. Speed = 0
- // .. ==> 0XF80007C4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000014E1U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007C8[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007C8[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007C8[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007C8[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007C8[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007C8[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007C8[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007C8[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007C8[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007CC[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007CC[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007CC[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007CC[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 2
- // .. ==> 0XF80007CC[7:5] = 0x00000002U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000040U
- // .. Speed = 0
- // .. ==> 0XF80007CC[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007CC[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007CC[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007CC[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001440U),
- // .. TRI_ENABLE = 0
- // .. ==> 0XF80007D0[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D0[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D0[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D0[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D0[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D0[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D0[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D0[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D0[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001420U),
- // .. TRI_ENABLE = 1
- // .. ==> 0XF80007D4[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // .. L0_SEL = 0
- // .. ==> 0XF80007D4[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. L1_SEL = 0
- // .. ==> 0XF80007D4[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. L2_SEL = 0
- // .. ==> 0XF80007D4[4:3] = 0x00000000U
- // .. ==> MASK : 0x00000018U VAL : 0x00000000U
- // .. L3_SEL = 1
- // .. ==> 0XF80007D4[7:5] = 0x00000001U
- // .. ==> MASK : 0x000000E0U VAL : 0x00000020U
- // .. Speed = 0
- // .. ==> 0XF80007D4[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. IO_Type = 2
- // .. ==> 0XF80007D4[11:9] = 0x00000002U
- // .. ==> MASK : 0x00000E00U VAL : 0x00000400U
- // .. PULLUP = 1
- // .. ==> 0XF80007D4[12:12] = 0x00000001U
- // .. ==> MASK : 0x00001000U VAL : 0x00001000U
- // .. DisableRcvr = 0
- // .. ==> 0XF80007D4[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001421U),
- // .. SDIO1_WP_SEL = 57
- // .. ==> 0XF8000834[5:0] = 0x00000039U
- // .. ==> MASK : 0x0000003FU VAL : 0x00000039U
- // .. SDIO1_CD_SEL = 9
- // .. ==> 0XF8000834[21:16] = 0x00000009U
- // .. ==> MASK : 0x003F0000U VAL : 0x00090000U
- // ..
- EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00090039U),
- // .. FINISH: MIO PROGRAMMING
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_peripherals_init_data_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B48[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B4C[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U),
- // .. IBUF_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[7:7] = 0x00000001U
- // .. ==> MASK : 0x00000080U VAL : 0x00000080U
- // .. TERM_DISABLE_MODE = 0x1
- // .. ==> 0XF8000B50[8:8] = 0x00000001U
- // .. ==> MASK : 0x00000100U VAL : 0x00000100U
- // ..
- EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
- // .. IBUF_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. TERM_DISABLE_MODE = 0x0
- // .. ==> 0XF8000B54[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U),
- // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // .. START: SRAM/NOR SET OPMODE
- // .. FINISH: SRAM/NOR SET OPMODE
- // .. START: UART REGISTERS
- // .. BDIV = 0x6
- // .. ==> 0XE0001034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0001018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0001000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0001000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0001000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0001000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0001000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0001000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0001000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0001000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0001000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0001004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0001004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0001004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0001004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0001004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0001004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0001004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
- // .. BDIV = 0x6
- // .. ==> 0XE0000034[7:0] = 0x00000006U
- // .. ==> MASK : 0x000000FFU VAL : 0x00000006U
- // ..
- EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U),
- // .. CD = 0x7c
- // .. ==> 0XE0000018[15:0] = 0x0000007CU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU
- // ..
- EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU),
- // .. STPBRK = 0x0
- // .. ==> 0XE0000000[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. STTBRK = 0x0
- // .. ==> 0XE0000000[7:7] = 0x00000000U
- // .. ==> MASK : 0x00000080U VAL : 0x00000000U
- // .. RSTTO = 0x0
- // .. ==> 0XE0000000[6:6] = 0x00000000U
- // .. ==> MASK : 0x00000040U VAL : 0x00000000U
- // .. TXDIS = 0x0
- // .. ==> 0XE0000000[5:5] = 0x00000000U
- // .. ==> MASK : 0x00000020U VAL : 0x00000000U
- // .. TXEN = 0x1
- // .. ==> 0XE0000000[4:4] = 0x00000001U
- // .. ==> MASK : 0x00000010U VAL : 0x00000010U
- // .. RXDIS = 0x0
- // .. ==> 0XE0000000[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. RXEN = 0x1
- // .. ==> 0XE0000000[2:2] = 0x00000001U
- // .. ==> MASK : 0x00000004U VAL : 0x00000004U
- // .. TXRES = 0x1
- // .. ==> 0XE0000000[1:1] = 0x00000001U
- // .. ==> MASK : 0x00000002U VAL : 0x00000002U
- // .. RXRES = 0x1
- // .. ==> 0XE0000000[0:0] = 0x00000001U
- // .. ==> MASK : 0x00000001U VAL : 0x00000001U
- // ..
- EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U),
- // .. IRMODE = 0x0
- // .. ==> 0XE0000004[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. UCLKEN = 0x0
- // .. ==> 0XE0000004[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. CHMODE = 0x0
- // .. ==> 0XE0000004[9:8] = 0x00000000U
- // .. ==> MASK : 0x00000300U VAL : 0x00000000U
- // .. NBSTOP = 0x0
- // .. ==> 0XE0000004[7:6] = 0x00000000U
- // .. ==> MASK : 0x000000C0U VAL : 0x00000000U
- // .. PAR = 0x4
- // .. ==> 0XE0000004[5:3] = 0x00000004U
- // .. ==> MASK : 0x00000038U VAL : 0x00000020U
- // .. CHRL = 0x0
- // .. ==> 0XE0000004[2:1] = 0x00000000U
- // .. ==> MASK : 0x00000006U VAL : 0x00000000U
- // .. CLKS = 0x0
- // .. ==> 0XE0000004[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U),
- // .. FINISH: UART REGISTERS
- // .. START: QSPI REGISTERS
- // .. Holdb_dr = 1
- // .. ==> 0XE000D000[19:19] = 0x00000001U
- // .. ==> MASK : 0x00080000U VAL : 0x00080000U
- // ..
- EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
- // .. FINISH: QSPI REGISTERS
- // .. START: PL POWER ON RESET REGISTERS
- // .. PCFG_POR_CNT_4K = 0
- // .. ==> 0XF8007000[29:29] = 0x00000000U
- // .. ==> MASK : 0x20000000U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
- // .. FINISH: PL POWER ON RESET REGISTERS
- // .. START: SMC TIMING CALCULATION REGISTER UPDATE
- // .. .. START: NAND SET CYCLE
- // .. .. FINISH: NAND SET CYCLE
- // .. .. START: OPMODE
- // .. .. FINISH: OPMODE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: SRAM/NOR CS0 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS0 BASE ADDRESS
- // .. .. FINISH: NOR CS0 BASE ADDRESS
- // .. .. START: SRAM/NOR CS1 SET CYCLE
- // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
- // .. .. START: DIRECT COMMAND
- // .. .. FINISH: DIRECT COMMAND
- // .. .. START: NOR CS1 BASE ADDRESS
- // .. .. FINISH: NOR CS1 BASE ADDRESS
- // .. .. START: USB RESET
- // .. .. FINISH: USB RESET
- // .. .. START: ENET RESET
- // .. .. FINISH: ENET RESET
- // .. .. START: I2C RESET
- // .. .. FINISH: I2C RESET
- // .. .. START: NOR CHIP SELECT
- // .. .. .. START: DIR MODE BANK 0
- // .. .. .. FINISH: DIR MODE BANK 0
- // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
- // .. .. .. START: OUTPUT ENABLE BANK 0
- // .. .. .. FINISH: OUTPUT ENABLE BANK 0
- // .. .. FINISH: NOR CHIP SELECT
- // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_post_config_1_0[] = {
- // START: top
- // .. START: SLCR SETTINGS
- // .. UNLOCK_KEY = 0XDF0D
- // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU
- // ..
- EMIT_WRITE(0XF8000008, 0x0000DF0DU),
- // .. FINISH: SLCR SETTINGS
- // .. START: ENABLING LEVEL SHIFTER
- // .. USER_INP_ICT_EN_0 = 3
- // .. ==> 0XF8000900[1:0] = 0x00000003U
- // .. ==> MASK : 0x00000003U VAL : 0x00000003U
- // .. USER_INP_ICT_EN_1 = 3
- // .. ==> 0XF8000900[3:2] = 0x00000003U
- // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU
- // ..
- EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
- // .. FINISH: ENABLING LEVEL SHIFTER
- // .. START: FPGA RESETS TO 0
- // .. reserved_3 = 0
- // .. ==> 0XF8000240[31:25] = 0x00000000U
- // .. ==> MASK : 0xFE000000U VAL : 0x00000000U
- // .. FPGA_ACP_RST = 0
- // .. ==> 0XF8000240[24:24] = 0x00000000U
- // .. ==> MASK : 0x01000000U VAL : 0x00000000U
- // .. FPGA_AXDS3_RST = 0
- // .. ==> 0XF8000240[23:23] = 0x00000000U
- // .. ==> MASK : 0x00800000U VAL : 0x00000000U
- // .. FPGA_AXDS2_RST = 0
- // .. ==> 0XF8000240[22:22] = 0x00000000U
- // .. ==> MASK : 0x00400000U VAL : 0x00000000U
- // .. FPGA_AXDS1_RST = 0
- // .. ==> 0XF8000240[21:21] = 0x00000000U
- // .. ==> MASK : 0x00200000U VAL : 0x00000000U
- // .. FPGA_AXDS0_RST = 0
- // .. ==> 0XF8000240[20:20] = 0x00000000U
- // .. ==> MASK : 0x00100000U VAL : 0x00000000U
- // .. reserved_2 = 0
- // .. ==> 0XF8000240[19:18] = 0x00000000U
- // .. ==> MASK : 0x000C0000U VAL : 0x00000000U
- // .. FSSW1_FPGA_RST = 0
- // .. ==> 0XF8000240[17:17] = 0x00000000U
- // .. ==> MASK : 0x00020000U VAL : 0x00000000U
- // .. FSSW0_FPGA_RST = 0
- // .. ==> 0XF8000240[16:16] = 0x00000000U
- // .. ==> MASK : 0x00010000U VAL : 0x00000000U
- // .. reserved_1 = 0
- // .. ==> 0XF8000240[15:14] = 0x00000000U
- // .. ==> MASK : 0x0000C000U VAL : 0x00000000U
- // .. FPGA_FMSW1_RST = 0
- // .. ==> 0XF8000240[13:13] = 0x00000000U
- // .. ==> MASK : 0x00002000U VAL : 0x00000000U
- // .. FPGA_FMSW0_RST = 0
- // .. ==> 0XF8000240[12:12] = 0x00000000U
- // .. ==> MASK : 0x00001000U VAL : 0x00000000U
- // .. FPGA_DMA3_RST = 0
- // .. ==> 0XF8000240[11:11] = 0x00000000U
- // .. ==> MASK : 0x00000800U VAL : 0x00000000U
- // .. FPGA_DMA2_RST = 0
- // .. ==> 0XF8000240[10:10] = 0x00000000U
- // .. ==> MASK : 0x00000400U VAL : 0x00000000U
- // .. FPGA_DMA1_RST = 0
- // .. ==> 0XF8000240[9:9] = 0x00000000U
- // .. ==> MASK : 0x00000200U VAL : 0x00000000U
- // .. FPGA_DMA0_RST = 0
- // .. ==> 0XF8000240[8:8] = 0x00000000U
- // .. ==> MASK : 0x00000100U VAL : 0x00000000U
- // .. reserved = 0
- // .. ==> 0XF8000240[7:4] = 0x00000000U
- // .. ==> MASK : 0x000000F0U VAL : 0x00000000U
- // .. FPGA3_OUT_RST = 0
- // .. ==> 0XF8000240[3:3] = 0x00000000U
- // .. ==> MASK : 0x00000008U VAL : 0x00000000U
- // .. FPGA2_OUT_RST = 0
- // .. ==> 0XF8000240[2:2] = 0x00000000U
- // .. ==> MASK : 0x00000004U VAL : 0x00000000U
- // .. FPGA1_OUT_RST = 0
- // .. ==> 0XF8000240[1:1] = 0x00000000U
- // .. ==> MASK : 0x00000002U VAL : 0x00000000U
- // .. FPGA0_OUT_RST = 0
- // .. ==> 0XF8000240[0:0] = 0x00000000U
- // .. ==> MASK : 0x00000001U VAL : 0x00000000U
- // ..
- EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
- // .. FINISH: FPGA RESETS TO 0
- // .. START: AFI REGISTERS
- // .. .. START: AFI0 REGISTERS
- // .. .. FINISH: AFI0 REGISTERS
- // .. .. START: AFI1 REGISTERS
- // .. .. FINISH: AFI1 REGISTERS
- // .. .. START: AFI2 REGISTERS
- // .. .. FINISH: AFI2 REGISTERS
- // .. .. START: AFI3 REGISTERS
- // .. .. FINISH: AFI3 REGISTERS
- // .. FINISH: AFI REGISTERS
- // .. START: LOCK IT BACK
- // .. LOCK_KEY = 0X767B
- // .. ==> 0XF8000004[15:0] = 0x0000767BU
- // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU
- // ..
- EMIT_WRITE(0XF8000004, 0x0000767BU),
- // .. FINISH: LOCK IT BACK
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-unsigned long ps7_debug_1_0[] = {
- // START: top
- // .. START: CROSS TRIGGER CONFIGURATIONS
- // .. .. START: UNLOCKING CTI REGISTERS
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U),
- // .. .. KEY = 0XC5ACCE55
- // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
- // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U
- // .. ..
- EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U),
- // .. .. FINISH: UNLOCKING CTI REGISTERS
- // .. .. START: ENABLING CTI MODULES AND CHANNELS
- // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
- // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
- // .. FINISH: CROSS TRIGGER CONFIGURATIONS
- // FINISH: top
- //
- EMIT_EXIT(),
-
- //
-};
-
-
-#include "xil_io.h"
-#define PS7_MASK_POLL_TIME 100000000
-
-char*
-getPS7MessageInfo(unsigned key) {
-
- char* err_msg = "";
- switch (key) {
- case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break;
- case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break;
- case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break;
- case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break;
- case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break;
- case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break;
- default: err_msg = "Undefined error status"; break;
- }
-
- return err_msg;
-}
-
-unsigned long
-ps7GetSiliconVersion () {
- // Read PS version from MCTRL register [31:28]
- unsigned long mask = 0xF0000000;
- unsigned long *addr = (unsigned long*) 0XF8007080;
- unsigned long ps_version = (*addr & mask) >> 28;
- return ps_version;
-}
-
-void mask_write (unsigned long add , unsigned long mask, unsigned long val ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- *addr = ( val & mask ) | ( *addr & ~mask);
- //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
-}
-
-
-int mask_poll(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- int i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- return -1;
- }
- i++;
- }
- return 1;
- //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
-}
-
-unsigned long mask_read(unsigned long add , unsigned long mask ) {
- volatile unsigned long *addr = (volatile unsigned long*) add;
- unsigned long val = (*addr & mask);
- //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
- return val;
-}
-
-
-
-int
-ps7_config(unsigned long * ps7_config_init)
-{
- unsigned long *ptr = ps7_config_init;
-
- unsigned long opcode; // current instruction ..
- unsigned long args[16]; // no opcode has so many args ...
- int numargs; // number of arguments of this instruction
- int j; // general purpose index
-
- volatile unsigned long *addr; // some variable to make code readable
- unsigned long val,mask; // some variable to make code readable
-
- int finish = -1 ; // loop while this is negative !
- int i = 0; // Timeout variable
-
- while( finish < 0 ) {
- numargs = ptr[0] & 0xF;
- opcode = ptr[0] >> 4;
-
- for( j = 0 ; j < numargs ; j ++ )
- args[j] = ptr[j+1];
- ptr += numargs + 1;
-
-
- switch ( opcode ) {
-
- case OPCODE_EXIT:
- finish = PS7_INIT_SUCCESS;
- break;
-
- case OPCODE_CLEAR:
- addr = (unsigned long*) args[0];
- *addr = 0;
- break;
-
- case OPCODE_WRITE:
- addr = (unsigned long*) args[0];
- val = args[1];
- *addr = val;
- break;
-
- case OPCODE_MASKWRITE:
- addr = (unsigned long*) args[0];
- mask = args[1];
- val = args[2];
- *addr = ( val & mask ) | ( *addr & ~mask);
- break;
-
- case OPCODE_MASKPOLL:
- addr = (unsigned long*) args[0];
- mask = args[1];
- i = 0;
- while (!(*addr & mask)) {
- if (i == PS7_MASK_POLL_TIME) {
- finish = PS7_INIT_TIMEOUT;
- break;
- }
- i++;
- }
- break;
- case OPCODE_MASKDELAY:
- {
- addr = (unsigned long*) args[0];
- mask = args[1];
- int delay = get_number_of_cycles_for_delay(mask);
- perf_reset_and_start_timer();
- while ((*addr < delay)) {
- }
- }
- break;
- default:
- finish = PS7_INIT_CORRUPT;
- break;
- }
- }
- return finish;
-}
-
-unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
-unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
-unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
-unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
-unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
-
-int
-ps7_post_config()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_post_config_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_post_config_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_post_config_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-int
-ps7_debug()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret = -1;
- if (si_ver == PCW_SILICON_VERSION_1) {
- ret = ps7_config (ps7_debug_1_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ret = ps7_config (ps7_debug_2_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- } else {
- ret = ps7_config (ps7_debug_3_0);
- if (ret != PS7_INIT_SUCCESS) return ret;
- }
- return PS7_INIT_SUCCESS;
-}
-
-
-int
-ps7_init()
-{
- // Get the PS_VERSION on run time
- unsigned long si_ver = ps7GetSiliconVersion ();
- int ret;
- //int pcw_ver = 0;
-
- if (si_ver == PCW_SILICON_VERSION_1) {
- ps7_mio_init_data = ps7_mio_init_data_1_0;
- ps7_pll_init_data = ps7_pll_init_data_1_0;
- ps7_clock_init_data = ps7_clock_init_data_1_0;
- ps7_ddr_init_data = ps7_ddr_init_data_1_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
- //pcw_ver = 1;
-
- } else if (si_ver == PCW_SILICON_VERSION_2) {
- ps7_mio_init_data = ps7_mio_init_data_2_0;
- ps7_pll_init_data = ps7_pll_init_data_2_0;
- ps7_clock_init_data = ps7_clock_init_data_2_0;
- ps7_ddr_init_data = ps7_ddr_init_data_2_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
- //pcw_ver = 2;
-
- } else {
- ps7_mio_init_data = ps7_mio_init_data_3_0;
- ps7_pll_init_data = ps7_pll_init_data_3_0;
- ps7_clock_init_data = ps7_clock_init_data_3_0;
- ps7_ddr_init_data = ps7_ddr_init_data_3_0;
- ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
- //pcw_ver = 3;
- }
-
- // MIO init
- ret = ps7_config (ps7_mio_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // PLL init
- ret = ps7_config (ps7_pll_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // Clock init
- ret = ps7_config (ps7_clock_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
- // DDR init
- ret = ps7_config (ps7_ddr_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
-
-
-
- // Peripherals init
- ret = ps7_config (ps7_peripherals_init_data);
- if (ret != PS7_INIT_SUCCESS) return ret;
- //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
- return PS7_INIT_SUCCESS;
-}
-
-
-
-
-/* For delay calculation using global timer */
-
-/* start timer */
- void perf_start_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
- (1 << 3) | // Auto-increment
- (0 << 8) // Pre-scale
- );
-}
-
-/* stop timer and reset timer count regs */
- void perf_reset_clock(void)
-{
- perf_disable_clock();
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
-}
-
-/* Compute mask for given delay in miliseconds*/
-int get_number_of_cycles_for_delay(unsigned int delay)
-{
- // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- return (APU_FREQ*delay/(2*1000));
-
-}
-
-/* stop timer */
- void perf_disable_clock(void)
-{
- *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
-}
-
-void perf_reset_and_start_timer()
-{
- perf_reset_clock();
- perf_start_clock();
-}
-
-
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.h
deleted file mode 100644
index e5c0eecc480fe0619c4952bb110f82c8c22e12f7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2010-2019 <Xilinx Inc.>
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; either version 2 of the License, or
-* (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, see <http://www.gnu.org/licenses/>
-*
-*
-******************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file ps7_init_gpl.h
-*
-* This file can be included in FSBL code
-* to get prototype of ps7_init() function
-* and error codes
-*
-*****************************************************************************/
-
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-//typedef unsigned int u32;
-
-
-/** do we need to make this name more unique ? **/
-//extern u32 ps7_init_data[];
-extern unsigned long * ps7_ddr_init_data;
-extern unsigned long * ps7_mio_init_data;
-extern unsigned long * ps7_pll_init_data;
-extern unsigned long * ps7_clock_init_data;
-extern unsigned long * ps7_peripherals_init_data;
-
-
-
-#define OPCODE_EXIT 0U
-#define OPCODE_CLEAR 1U
-#define OPCODE_WRITE 2U
-#define OPCODE_MASKWRITE 3U
-#define OPCODE_MASKPOLL 4U
-#define OPCODE_MASKDELAY 5U
-#define NEW_PS7_ERR_CODE 1
-
-/* Encode number of arguments in last nibble */
-#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
-#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
-#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
-#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
-#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
-#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
-
-/* Returns codes of PS7_Init */
-#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
-#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
-#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
-#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
-#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
-#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
-
-
-/* Silicon Versions */
-#define PCW_SILICON_VERSION_1 0
-#define PCW_SILICON_VERSION_2 1
-#define PCW_SILICON_VERSION_3 2
-
-/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
-#define PS7_POST_CONFIG
-
-/* Freq of all peripherals */
-
-#define APU_FREQ 750000000
-#define DDR_FREQ 500000000
-#define DCI_FREQ 10204082
-#define QSPI_FREQ 134615387
-#define SMC_FREQ 10000000
-#define ENET0_FREQ 125000000
-#define ENET1_FREQ 10000000
-#define USB0_FREQ 60000000
-#define USB1_FREQ 60000000
-#define SDIO_FREQ 97222221
-#define UART_FREQ 97222221
-#define SPI_FREQ 159090912
-#define I2C_FREQ 125000000
-#define WDT_FREQ 125000000
-#define TTC_FREQ 50000000
-#define CAN_FREQ 97222221
-#define PCAP_FREQ 194444443
-#define TPIU_FREQ 200000000
-#define FPGA0_FREQ 125000000
-#define FPGA1_FREQ 10000000
-#define FPGA2_FREQ 10000000
-#define FPGA3_FREQ 10000000
-
-
-/* For delay calculation using global registers*/
-#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
-#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
-#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
-#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
-
-int ps7_config( unsigned long*);
-int ps7_init();
-int ps7_post_config();
-int ps7_debug();
-char* getPS7MessageInfo(unsigned key);
-
-void perf_start_clock(void);
-void perf_disable_clock(void);
-void perf_reset_clock(void);
-void perf_reset_and_start_timer();
-int get_number_of_cycles_for_delay(unsigned int delay);
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_parameters.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_parameters.xml
deleted file mode 100644
index ed6484427f799b8b6bfa1f487b0e7d42c787d1de..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_parameters.xml
+++ /dev/null
@@ -1,643 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
-<designInfo version="1.0" >
- <MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
- <PARAMETERS >
- <PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
- <PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="750" />
- <PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="30" />
- <PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
- <PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
- <PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
- <PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
- <PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="MIO 52 .. 53" />
- <PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
- <PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
- <PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
- <PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="18" />
- <PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
- <PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
- <PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1500.000" />
- <PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
- <PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
- <PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="50" />
- <PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
- <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="49" />
- <PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="2" />
- <PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
- <PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="20" />
- <PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1000.000" />
- <PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
- <PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
- <PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
- <PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
- <PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
- <PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
- <PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
- <PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
- <PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
- <PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
- <PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
- <PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
- <PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="14" />
- <PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
- <PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
- <PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
- <PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
- <PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
- <PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
- <PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
- <PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
- <PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
- <PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="Share reset pin" />
- <PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
- <PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
- <PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
- <PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
- <PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
- <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="7" />
- <PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
- <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
- <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
- <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
- <PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
- <PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
- <PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
- <PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
- <PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="125" />
- <PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
- <PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
- <PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
- <PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
- <PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
- <PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
- <PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
- <PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
- <PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
- <PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
- <PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
- <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="" />
- <PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
- <PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
- <PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="MIO 50 .. 51" />
- <PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
- <PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
- <PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
- <PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
- <PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
- <PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="Share reset pin" />
- <PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="35" />
- <PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1750.000" />
- <PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
- <PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
- <PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
- <PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
- <PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
- <PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
- <PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
- <PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
- <PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
- <PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
- <PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="in" />
- <PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="enabled" />
- <PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
- <PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
- <PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
- <PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
- <PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
- <PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
- <PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
- <PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
- <PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
- <PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
- <PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
- <PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
- <PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
- <PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
- <PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
- <PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
- <PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
- <PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="9" />
- <PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
- <PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
- <PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
- <PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 2.5V" />
- <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
- <PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
- <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
- <PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
- <PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
- <PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="13" />
- <PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="133" />
- <PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
- <PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
- <PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
- <PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
- <PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
- <PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="MIO 9" />
- <PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
- <PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
- <PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="MIO 10 .. 15" />
- <PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="18" />
- <PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
- <PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
- <PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
- <PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="MIO 42" />
- <PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
- <PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
- <PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="MIO 40 .. 45" />
- <PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="EMIO" />
- <PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="EMIO" />
- <PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="EMIO" />
- <PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="EMIO" />
- <PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="11" />
- <PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
- <PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
- <PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
- <PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
- <PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
- <PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
- <PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
- <PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
- <PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
- <PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
- <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
- <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
- <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
- <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
- <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
- <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
- <PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
- <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
- <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
- <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
- <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
- <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
- <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
- <PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
- <PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
- <PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
- <PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
- <PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="MIO 46 .. 47" />
- <PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
- <PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
- <PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
- <PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
- <PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="18" />
- <PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="16 Bit" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="76.428" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="76.428" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="76.428" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="76.428" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="2048 MBits" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="76.687" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="77.8025" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="72.8405" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="111.904" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="73.119" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="63.8935" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="77.045" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="111.903" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="500" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3 (Low Voltage)" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K128M16 JT-125" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="14" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
- <PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
- <PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
- <PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
- <PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="MIO 28 .. 39" />
- <PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
- <PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
- <PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
- <PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
- <PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="1" />
- <PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
- <PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="Share reset pin" />
- <PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
- <PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
- <PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
- <PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
- <PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
- <PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
- <PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
- <PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
- <PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
- <PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
- <PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
- <PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
- <PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
- <PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
- <PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
- <PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
- </PARAMETERS>
- <BUSINTERFACES >
- <BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
- <BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
- <BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
- <BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
- <BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
- <BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
- <BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
- <BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
- </BUSINTERFACES>
- <CLOCKOUTS >
- <CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="125.000000" />
- <CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
- <CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
- <CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
- </CLOCKOUTS>
- </MODULE>
-</designInfo>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.dcp
deleted file mode 100644
index e81d6690a9a631b5127cd968836d28866827def0..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci
deleted file mode 100644
index 7bf63fcaae0995711263174bd1389d01ba5199e6..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci
+++ /dev/null
@@ -1,1925 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
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- <spirit:componentInstance>
- <spirit:instanceName>scalp_zynqps_processing_system7_0_0</spirit:instanceName>
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- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3.WUSER_WIDTH">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.ASSOCIATED_RESET"/>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.CLK_DOMAIN"/>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_HP3_ACLK.PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">scalp_zynqps_processing_system7_0_0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_APU_PERIPHERAL_FREQMHZ">750.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN_PERIPHERAL_FREQMHZ">97.222221</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_DCI_PERIPHERAL_FREQMHZ">10.204082</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_I2C_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ">194.444443</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ">134.615387</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ">97.222221</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_SMC_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_SPI_PERIPHERAL_FREQMHZ">159.090912</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ">200.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_UART_PERIPHERAL_FREQMHZ">97.222221</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_USB0_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_USB1_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_WDT_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_APU_CLK_RATIO_ENABLE">6:2:1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_APU_PERIPHERAL_FREQMHZ">750</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ARMPLL_CTRL_FBDIV">30</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_BASEADDR">0xE0008000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_CAN0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_GRP_CLK_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_GRP_CLK_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_HIGHADDR">0xE0008FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_FREQMHZ">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_BASEADDR">0xE0009000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_CAN1_IO">MIO 52 .. 53</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_GRP_CLK_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_GRP_CLK_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_HIGHADDR">0xE0009FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_FREQMHZ">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR0">18</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK0_FREQ">125000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK1_FREQ">10000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK2_FREQ">10000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK3_FREQ">10000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE0_FIQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE0_IRQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE1_FIQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE1_IRQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_CPU_6X4X_MAX_RANGE">767</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_CPU_PLL_FREQMHZ">1500.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_PERIPHERAL_CLKSRC">ARM PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_PERIPHERAL_DIVISOR0">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CRYSTAL_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_CLKSRC">DDR PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_DIVISOR0">49</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_DIVISOR1">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_FREQMHZ">10.159</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDRPLL_CTRL_FBDIV">20</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_DDR_PLL_FREQMHZ">1000.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_HPRLPR_QUEUE_PARTITION">HPR(0)/LPR(32)</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL">15</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PERIPHERAL_CLKSRC">DDR PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PERIPHERAL_DIVISOR0">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT0_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT1_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT2_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT3_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_0"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_1"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_2"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_3"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_0"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_1"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_2"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_3"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_RAM_BASEADDR">0x00100000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_RAM_HIGHADDR">0x0FFFFFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DM_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DQS_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DQ_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DUAL_PARALLEL_QSPI_DATA_MODE"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DUAL_STACK_QSPI_DATA_MODE"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_BASEADDR">0xE000B000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_ENET0_IO">MIO 16 .. 27</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_HIGHADDR">0xE000BFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_DIVISOR0">14</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_FREQMHZ">1000 Mbps</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_BASEADDR">0xE000C000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_ENET1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_GRP_MDIO_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_GRP_MDIO_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_HIGHADDR">0xE000CFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_FREQMHZ">1000 Mbps</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET_RESET_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET_RESET_POLARITY">Active Low</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET_RESET_SELECT">Share reset pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_4K_TIMER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CAN0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CAN1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK0_PORT">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK1_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK2_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK3_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG0_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG1_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG2_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG3_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_DDR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CAN0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CAN1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_ENET0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_ENET1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_GPIO">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_I2C0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_I2C1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_MODEM_UART0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_MODEM_UART1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_PJTAG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SDIO1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SPI0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SPI1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SRAM_INT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_TRACE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_TTC0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_TTC1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_UART0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_UART1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WDT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_ENET0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_ENET1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_GPIO">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_I2C0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_I2C1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_MODEM_UART0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_MODEM_UART1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_PJTAG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_PTP_ENET0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_PTP_ENET1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_QSPI">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST0_PORT">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST1_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST2_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST3_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SDIO1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SMC">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SPI0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SPI1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_TRACE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_TTC0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_TTC1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_UART0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_UART1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_USB0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_USB1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_WDT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_DIVISOR0">7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_DIVISOR1">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK0_BUF">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK1_BUF">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK2_BUF">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK3_BUF">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA0_PERIPHERAL_FREQMHZ">125</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA1_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA2_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA3_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK0_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK2_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK3_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN0">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN1">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN2">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN3">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT0">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT1">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT2">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT3">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP0_EN_MODIFIABLE_TXN">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP0_NUM_READ_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP0_NUM_WRITE_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP1_EN_MODIFIABLE_TXN">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP1_NUM_READ_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP1_NUM_WRITE_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_BASEADDR">0xE000A000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_HIGHADDR">0xE000AFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_MIO_GPIO_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_MIO_GPIO_IO">MIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_BASEADDR">0xE0004000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_GRP_INT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_GRP_INT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_HIGHADDR">0xE0004FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_I2C0_IO">MIO 50 .. 51</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_BASEADDR">0xE0005000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_GRP_INT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_GRP_INT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_HIGHADDR">0xE0005FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_I2C1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_RESET_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_RESET_POLARITY">Active Low</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_RESET_SELECT">Share reset pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IMPORT_BOARD_PRESET">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_INCLUDE_ACP_TRANS_CHECK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_INCLUDE_TRACE_BUFFER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IOPLL_CTRL_FBDIV">35</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IO_IO_PLL_FREQMHZ">1750.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IRQ_F2P_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IRQ_F2P_MODE">DIRECT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_PRIMITIVE">54</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_TREE_PERIPHERALS">GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#SPI 0#UART 0#UART 0#UART 1#UART 1#I2C 0#I2C 0#CAN 1#CAN 1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_TREE_SIGNALS">gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_FREQMHZ">125</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_THREAD_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_THREAD_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_AR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_CLR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_REA">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_RR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_GRP_D8_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_GRP_D8_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_NAND_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_A25_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_A25_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS0_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_NOR_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NUM_F2P_INTR_INPUTS">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_OVERRIDE_BASIC_CLOCK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_CAN0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_CAN1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_CTI_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC2_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC3_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC4_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC5_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC6_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC7_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC_ABORT_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_ENET0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_ENET1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_GPIO_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_I2C0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_I2C1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_QSPI_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SDIO0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SDIO1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SMC_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SPI0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SPI1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_UART0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_UART1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_USB0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_USB1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY0">0.075</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY1">0.070</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY2">0.077</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY3">0.094</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0">-0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1">-0.001</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2">0.004</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3">-0.035</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_NAME">clg485</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_DIVISOR0">9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_FREQMHZ">200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PERIPHERAL_BOARD_PRESET">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PJTAG_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PJTAG_PJTAG_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PLL_BYPASSMODE_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PRESET_BANK0_VOLTAGE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PRESET_BANK1_VOLTAGE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PS7_SI_REV">PRODUCTION</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_IO1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_IO1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_IO">MIO 1 .. 6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_INTERNAL_HIGHADDRESS">0xFCFFFFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_DIVISOR0">13</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_FREQMHZ">133</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_QSPI_IO">MIO 1 .. 6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_CD_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_CD_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_POW_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_POW_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_SD0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_IO">MIO 9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_POW_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_POW_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_WP_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_WP_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_SD1_IO">MIO 10 .. 15</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO0_BASEADDR">0xE0100000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO0_HIGHADDR">0xE0100FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO1_BASEADDR">0xE0101000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO1_HIGHADDR">0xE0101FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_DIVISOR0">18</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SINGLE_QSPI_DATA_MODE">x4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T0">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T1">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T2">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T3">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T4">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T5">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T6">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_VALID">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_BASEADDR">0xE0006000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_IO">MIO 42</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_HIGHADDR">0xE0006FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_SPI0_IO">MIO 40 .. 45</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_BASEADDR">0xE0007000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_HIGHADDR">0xE0007FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_SPI1_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_DIVISOR0">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_FREQMHZ">166.666666</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_ARUSER_VAL">31</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_AWUSER_VAL">31</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_ID_WIDTH">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_FREQMHZ">200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_BUFFER_CLOCK_DELAY">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_BUFFER_FIFO_SIZE">128</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_16BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_16BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_2BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_2BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_32BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_32BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_4BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_4BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_8BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_8BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_INTERNAL_WIDTH">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_PIPELINE_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_TRACE_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_BASEADDR">0xE0104000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_HIGHADDR">0xE0104fff</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_TTC0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_BASEADDR">0xE0105000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_HIGHADDR">0xE0105fff</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_TTC1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_BASEADDR">0xE0000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_BAUD_RATE">115200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_GRP_FULL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_GRP_FULL_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_HIGHADDR">0xE0000FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_UART0_IO">MIO 46 .. 47</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_BASEADDR">0xE0001000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_BAUD_RATE">115200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_GRP_FULL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_GRP_FULL_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_HIGHADDR">0xE0001FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_UART1_IO">MIO 48 .. 49</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_DIVISOR0">18</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_ACT_DDR_FREQ_MHZ">500.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ADV_ENABLE">0</spirit:configurableElementValue>
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- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_POW_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_WP_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_SD1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_VALID" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SINGLE_QSPI_DATA_MODE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_SPI0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_SPI1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_VALID" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_GRP_FULL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_UART0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_GRP_FULL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_UART1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_VALID" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BL" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BUS_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CL" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_COL_ADDR_COUNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CWL" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DEVICE_CAPACITY" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DRAM_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ECC" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_FREQ_MHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_MEMORY_TYPE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_PARTNO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_SPEED_BIN" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_FAW" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RAS_MIN" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RC" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RCD" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RP" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_USB0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_SELECT" xilinx:valueSource="user"/>
- </xilinx:configElementInfos>
- </xilinx:componentInstanceExtensions>
- </spirit:vendorExtensions>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc
deleted file mode 100644
index deea2aea807934c931c0a4f6bd1678f73e0d3819..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc
+++ /dev/null
@@ -1,723 +0,0 @@
-############################################################################
-##
-## Xilinx, Inc. 2006 www.xilinx.com
-############################################################################
-## File name : ps7_constraints.xdc
-##
-## Details : Constraints file
-## FPGA family: zynq
-## FPGA: xc7z015clg485-2
-## Device Size: xc7z015
-## Package: clg485
-## Speedgrade: -2
-##
-##
-############################################################################
-############################################################################
-############################################################################
-# Clock constraints #
-############################################################################
-create_clock -name clk_fpga_0 -period "8" [get_pins "PS7_i/FCLKCLK[0]"]
-set_input_jitter clk_fpga_0 0.24
-#The clocks are asynchronous, user should constrain them appropriately.#
-
-
-############################################################################
-# I/O STANDARDS and Location Constraints #
-############################################################################
-
-# CAN 1 / rx / MIO[53]
-set_property iostandard "LVCMOS25" [get_ports "MIO[53]"]
-set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
-set_property slew "slow" [get_ports "MIO[53]"]
-set_property drive "8" [get_ports "MIO[53]"]
-set_property pullup "TRUE" [get_ports "MIO[53]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[53]"]
-# CAN 1 / tx / MIO[52]
-set_property iostandard "LVCMOS25" [get_ports "MIO[52]"]
-set_property PACKAGE_PIN "D13" [get_ports "MIO[52]"]
-set_property slew "slow" [get_ports "MIO[52]"]
-set_property drive "8" [get_ports "MIO[52]"]
-set_property pullup "TRUE" [get_ports "MIO[52]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[52]"]
-# I2C 0 / sda / MIO[51]
-set_property iostandard "LVCMOS25" [get_ports "MIO[51]"]
-set_property PACKAGE_PIN "C13" [get_ports "MIO[51]"]
-set_property slew "slow" [get_ports "MIO[51]"]
-set_property drive "8" [get_ports "MIO[51]"]
-set_property pullup "TRUE" [get_ports "MIO[51]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
-# I2C 0 / scl / MIO[50]
-set_property iostandard "LVCMOS25" [get_ports "MIO[50]"]
-set_property PACKAGE_PIN "D10" [get_ports "MIO[50]"]
-set_property slew "slow" [get_ports "MIO[50]"]
-set_property drive "8" [get_ports "MIO[50]"]
-set_property pullup "TRUE" [get_ports "MIO[50]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
-# UART 1 / rx / MIO[49]
-set_property iostandard "LVCMOS25" [get_ports "MIO[49]"]
-set_property PACKAGE_PIN "C9" [get_ports "MIO[49]"]
-set_property slew "slow" [get_ports "MIO[49]"]
-set_property drive "8" [get_ports "MIO[49]"]
-set_property pullup "TRUE" [get_ports "MIO[49]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[49]"]
-# UART 1 / tx / MIO[48]
-set_property iostandard "LVCMOS25" [get_ports "MIO[48]"]
-set_property PACKAGE_PIN "D12" [get_ports "MIO[48]"]
-set_property slew "slow" [get_ports "MIO[48]"]
-set_property drive "8" [get_ports "MIO[48]"]
-set_property pullup "TRUE" [get_ports "MIO[48]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[48]"]
-# UART 0 / tx / MIO[47]
-set_property iostandard "LVCMOS25" [get_ports "MIO[47]"]
-set_property PACKAGE_PIN "B13" [get_ports "MIO[47]"]
-set_property slew "slow" [get_ports "MIO[47]"]
-set_property drive "8" [get_ports "MIO[47]"]
-set_property pullup "TRUE" [get_ports "MIO[47]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[47]"]
-# UART 0 / rx / MIO[46]
-set_property iostandard "LVCMOS25" [get_ports "MIO[46]"]
-set_property PACKAGE_PIN "D11" [get_ports "MIO[46]"]
-set_property slew "slow" [get_ports "MIO[46]"]
-set_property drive "8" [get_ports "MIO[46]"]
-set_property pullup "TRUE" [get_ports "MIO[46]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[46]"]
-# SPI 0 / mosi / MIO[45]
-set_property iostandard "LVCMOS25" [get_ports "MIO[45]"]
-set_property PACKAGE_PIN "B14" [get_ports "MIO[45]"]
-set_property slew "slow" [get_ports "MIO[45]"]
-set_property drive "8" [get_ports "MIO[45]"]
-set_property pullup "TRUE" [get_ports "MIO[45]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
-# GPIO / gpio[44] / MIO[44]
-set_property iostandard "LVCMOS25" [get_ports "MIO[44]"]
-set_property PACKAGE_PIN "E10" [get_ports "MIO[44]"]
-set_property slew "slow" [get_ports "MIO[44]"]
-set_property drive "8" [get_ports "MIO[44]"]
-set_property pullup "TRUE" [get_ports "MIO[44]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
-# GPIO / gpio[43] / MIO[43]
-set_property iostandard "LVCMOS25" [get_ports "MIO[43]"]
-set_property PACKAGE_PIN "B12" [get_ports "MIO[43]"]
-set_property slew "slow" [get_ports "MIO[43]"]
-set_property drive "8" [get_ports "MIO[43]"]
-set_property pullup "TRUE" [get_ports "MIO[43]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
-# SPI 0 / ss[0] / MIO[42]
-set_property iostandard "LVCMOS25" [get_ports "MIO[42]"]
-set_property PACKAGE_PIN "D15" [get_ports "MIO[42]"]
-set_property slew "slow" [get_ports "MIO[42]"]
-set_property drive "8" [get_ports "MIO[42]"]
-set_property pullup "TRUE" [get_ports "MIO[42]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
-# SPI 0 / miso / MIO[41]
-set_property iostandard "LVCMOS25" [get_ports "MIO[41]"]
-set_property PACKAGE_PIN "C15" [get_ports "MIO[41]"]
-set_property slew "slow" [get_ports "MIO[41]"]
-set_property drive "8" [get_ports "MIO[41]"]
-set_property pullup "TRUE" [get_ports "MIO[41]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
-# SPI 0 / sclk / MIO[40]
-set_property iostandard "LVCMOS25" [get_ports "MIO[40]"]
-set_property PACKAGE_PIN "E9" [get_ports "MIO[40]"]
-set_property slew "slow" [get_ports "MIO[40]"]
-set_property drive "8" [get_ports "MIO[40]"]
-set_property pullup "TRUE" [get_ports "MIO[40]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
-# USB 0 / data[7] / MIO[39]
-set_property iostandard "LVCMOS25" [get_ports "MIO[39]"]
-set_property PACKAGE_PIN "C10" [get_ports "MIO[39]"]
-set_property slew "slow" [get_ports "MIO[39]"]
-set_property drive "8" [get_ports "MIO[39]"]
-set_property pullup "TRUE" [get_ports "MIO[39]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
-# USB 0 / data[6] / MIO[38]
-set_property iostandard "LVCMOS25" [get_ports "MIO[38]"]
-set_property PACKAGE_PIN "F10" [get_ports "MIO[38]"]
-set_property slew "slow" [get_ports "MIO[38]"]
-set_property drive "8" [get_ports "MIO[38]"]
-set_property pullup "TRUE" [get_ports "MIO[38]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
-# USB 0 / data[5] / MIO[37]
-set_property iostandard "LVCMOS25" [get_ports "MIO[37]"]
-set_property PACKAGE_PIN "B9" [get_ports "MIO[37]"]
-set_property slew "slow" [get_ports "MIO[37]"]
-set_property drive "8" [get_ports "MIO[37]"]
-set_property pullup "TRUE" [get_ports "MIO[37]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
-# USB 0 / clk / MIO[36]
-set_property iostandard "LVCMOS25" [get_ports "MIO[36]"]
-set_property PACKAGE_PIN "A14" [get_ports "MIO[36]"]
-set_property slew "slow" [get_ports "MIO[36]"]
-set_property drive "8" [get_ports "MIO[36]"]
-set_property pullup "TRUE" [get_ports "MIO[36]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[36]"]
-# USB 0 / data[3] / MIO[35]
-set_property iostandard "LVCMOS25" [get_ports "MIO[35]"]
-set_property PACKAGE_PIN "F9" [get_ports "MIO[35]"]
-set_property slew "slow" [get_ports "MIO[35]"]
-set_property drive "8" [get_ports "MIO[35]"]
-set_property pullup "TRUE" [get_ports "MIO[35]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
-# USB 0 / data[2] / MIO[34]
-set_property iostandard "LVCMOS25" [get_ports "MIO[34]"]
-set_property PACKAGE_PIN "B11" [get_ports "MIO[34]"]
-set_property slew "slow" [get_ports "MIO[34]"]
-set_property drive "8" [get_ports "MIO[34]"]
-set_property pullup "TRUE" [get_ports "MIO[34]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
-# USB 0 / data[1] / MIO[33]
-set_property iostandard "LVCMOS25" [get_ports "MIO[33]"]
-set_property PACKAGE_PIN "G11" [get_ports "MIO[33]"]
-set_property slew "slow" [get_ports "MIO[33]"]
-set_property drive "8" [get_ports "MIO[33]"]
-set_property pullup "TRUE" [get_ports "MIO[33]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
-# USB 0 / data[0] / MIO[32]
-set_property iostandard "LVCMOS25" [get_ports "MIO[32]"]
-set_property PACKAGE_PIN "C16" [get_ports "MIO[32]"]
-set_property slew "slow" [get_ports "MIO[32]"]
-set_property drive "8" [get_ports "MIO[32]"]
-set_property pullup "TRUE" [get_ports "MIO[32]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
-# USB 0 / nxt / MIO[31]
-set_property iostandard "LVCMOS25" [get_ports "MIO[31]"]
-set_property PACKAGE_PIN "F14" [get_ports "MIO[31]"]
-set_property slew "slow" [get_ports "MIO[31]"]
-set_property drive "8" [get_ports "MIO[31]"]
-set_property pullup "TRUE" [get_ports "MIO[31]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[31]"]
-# USB 0 / stp / MIO[30]
-set_property iostandard "LVCMOS25" [get_ports "MIO[30]"]
-set_property PACKAGE_PIN "A12" [get_ports "MIO[30]"]
-set_property slew "slow" [get_ports "MIO[30]"]
-set_property drive "8" [get_ports "MIO[30]"]
-set_property pullup "TRUE" [get_ports "MIO[30]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[30]"]
-# USB 0 / dir / MIO[29]
-set_property iostandard "LVCMOS25" [get_ports "MIO[29]"]
-set_property PACKAGE_PIN "E15" [get_ports "MIO[29]"]
-set_property slew "slow" [get_ports "MIO[29]"]
-set_property drive "8" [get_ports "MIO[29]"]
-set_property pullup "TRUE" [get_ports "MIO[29]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[29]"]
-# USB 0 / data[4] / MIO[28]
-set_property iostandard "LVCMOS25" [get_ports "MIO[28]"]
-set_property PACKAGE_PIN "A11" [get_ports "MIO[28]"]
-set_property slew "slow" [get_ports "MIO[28]"]
-set_property drive "8" [get_ports "MIO[28]"]
-set_property pullup "TRUE" [get_ports "MIO[28]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
-# Enet 0 / rx_ctl / MIO[27]
-set_property iostandard "LVCMOS25" [get_ports "MIO[27]"]
-set_property PACKAGE_PIN "D16" [get_ports "MIO[27]"]
-set_property slew "slow" [get_ports "MIO[27]"]
-set_property drive "8" [get_ports "MIO[27]"]
-set_property pullup "TRUE" [get_ports "MIO[27]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[27]"]
-# Enet 0 / rxd[3] / MIO[26]
-set_property iostandard "LVCMOS25" [get_ports "MIO[26]"]
-set_property PACKAGE_PIN "A10" [get_ports "MIO[26]"]
-set_property slew "slow" [get_ports "MIO[26]"]
-set_property drive "8" [get_ports "MIO[26]"]
-set_property pullup "TRUE" [get_ports "MIO[26]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[26]"]
-# Enet 0 / rxd[2] / MIO[25]
-set_property iostandard "LVCMOS25" [get_ports "MIO[25]"]
-set_property PACKAGE_PIN "F11" [get_ports "MIO[25]"]
-set_property slew "slow" [get_ports "MIO[25]"]
-set_property drive "8" [get_ports "MIO[25]"]
-set_property pullup "TRUE" [get_ports "MIO[25]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[25]"]
-# Enet 0 / rxd[1] / MIO[24]
-set_property iostandard "LVCMOS25" [get_ports "MIO[24]"]
-set_property PACKAGE_PIN "B16" [get_ports "MIO[24]"]
-set_property slew "slow" [get_ports "MIO[24]"]
-set_property drive "8" [get_ports "MIO[24]"]
-set_property pullup "TRUE" [get_ports "MIO[24]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"]
-# Enet 0 / rxd[0] / MIO[23]
-set_property iostandard "LVCMOS25" [get_ports "MIO[23]"]
-set_property PACKAGE_PIN "E12" [get_ports "MIO[23]"]
-set_property slew "slow" [get_ports "MIO[23]"]
-set_property drive "8" [get_ports "MIO[23]"]
-set_property pullup "TRUE" [get_ports "MIO[23]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[23]"]
-# Enet 0 / rx_clk / MIO[22]
-set_property iostandard "LVCMOS25" [get_ports "MIO[22]"]
-set_property PACKAGE_PIN "A9" [get_ports "MIO[22]"]
-set_property slew "slow" [get_ports "MIO[22]"]
-set_property drive "8" [get_ports "MIO[22]"]
-set_property pullup "TRUE" [get_ports "MIO[22]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[22]"]
-# Enet 0 / tx_ctl / MIO[21]
-set_property iostandard "LVCMOS25" [get_ports "MIO[21]"]
-set_property PACKAGE_PIN "F12" [get_ports "MIO[21]"]
-set_property slew "slow" [get_ports "MIO[21]"]
-set_property drive "8" [get_ports "MIO[21]"]
-set_property pullup "TRUE" [get_ports "MIO[21]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[21]"]
-# Enet 0 / txd[3] / MIO[20]
-set_property iostandard "LVCMOS25" [get_ports "MIO[20]"]
-set_property PACKAGE_PIN "A15" [get_ports "MIO[20]"]
-set_property slew "slow" [get_ports "MIO[20]"]
-set_property drive "8" [get_ports "MIO[20]"]
-set_property pullup "TRUE" [get_ports "MIO[20]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[20]"]
-# Enet 0 / txd[2] / MIO[19]
-set_property iostandard "LVCMOS25" [get_ports "MIO[19]"]
-set_property PACKAGE_PIN "E13" [get_ports "MIO[19]"]
-set_property slew "slow" [get_ports "MIO[19]"]
-set_property drive "8" [get_ports "MIO[19]"]
-set_property pullup "TRUE" [get_ports "MIO[19]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[19]"]
-# Enet 0 / txd[1] / MIO[18]
-set_property iostandard "LVCMOS25" [get_ports "MIO[18]"]
-set_property PACKAGE_PIN "A16" [get_ports "MIO[18]"]
-set_property slew "slow" [get_ports "MIO[18]"]
-set_property drive "8" [get_ports "MIO[18]"]
-set_property pullup "TRUE" [get_ports "MIO[18]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"]
-# Enet 0 / txd[0] / MIO[17]
-set_property iostandard "LVCMOS25" [get_ports "MIO[17]"]
-set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
-set_property slew "slow" [get_ports "MIO[17]"]
-set_property drive "8" [get_ports "MIO[17]"]
-set_property pullup "TRUE" [get_ports "MIO[17]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[17]"]
-# Enet 0 / tx_clk / MIO[16]
-set_property iostandard "LVCMOS25" [get_ports "MIO[16]"]
-set_property PACKAGE_PIN "D17" [get_ports "MIO[16]"]
-set_property slew "slow" [get_ports "MIO[16]"]
-set_property drive "8" [get_ports "MIO[16]"]
-set_property pullup "TRUE" [get_ports "MIO[16]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[16]"]
-# SD 1 / data[3] / MIO[15]
-set_property iostandard "LVCMOS33" [get_ports "MIO[15]"]
-set_property PACKAGE_PIN "E17" [get_ports "MIO[15]"]
-set_property slew "slow" [get_ports "MIO[15]"]
-set_property drive "8" [get_ports "MIO[15]"]
-set_property pullup "TRUE" [get_ports "MIO[15]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
-# SD 1 / data[2] / MIO[14]
-set_property iostandard "LVCMOS33" [get_ports "MIO[14]"]
-set_property PACKAGE_PIN "B17" [get_ports "MIO[14]"]
-set_property slew "slow" [get_ports "MIO[14]"]
-set_property drive "8" [get_ports "MIO[14]"]
-set_property pullup "TRUE" [get_ports "MIO[14]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
-# SD 1 / data[1] / MIO[13]
-set_property iostandard "LVCMOS33" [get_ports "MIO[13]"]
-set_property PACKAGE_PIN "A17" [get_ports "MIO[13]"]
-set_property slew "slow" [get_ports "MIO[13]"]
-set_property drive "8" [get_ports "MIO[13]"]
-set_property pullup "TRUE" [get_ports "MIO[13]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
-# SD 1 / clk / MIO[12]
-set_property iostandard "LVCMOS33" [get_ports "MIO[12]"]
-set_property PACKAGE_PIN "C18" [get_ports "MIO[12]"]
-set_property slew "slow" [get_ports "MIO[12]"]
-set_property drive "8" [get_ports "MIO[12]"]
-set_property pullup "TRUE" [get_ports "MIO[12]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
-# SD 1 / cmd / MIO[11]
-set_property iostandard "LVCMOS33" [get_ports "MIO[11]"]
-set_property PACKAGE_PIN "B19" [get_ports "MIO[11]"]
-set_property slew "slow" [get_ports "MIO[11]"]
-set_property drive "8" [get_ports "MIO[11]"]
-set_property pullup "TRUE" [get_ports "MIO[11]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
-# SD 1 / data[0] / MIO[10]
-set_property iostandard "LVCMOS33" [get_ports "MIO[10]"]
-set_property PACKAGE_PIN "G16" [get_ports "MIO[10]"]
-set_property slew "slow" [get_ports "MIO[10]"]
-set_property drive "8" [get_ports "MIO[10]"]
-set_property pullup "TRUE" [get_ports "MIO[10]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
-# SD 1 / cd / MIO[9]
-set_property iostandard "LVCMOS33" [get_ports "MIO[9]"]
-set_property PACKAGE_PIN "C19" [get_ports "MIO[9]"]
-set_property slew "slow" [get_ports "MIO[9]"]
-set_property drive "8" [get_ports "MIO[9]"]
-set_property pullup "TRUE" [get_ports "MIO[9]"]
-set_property PIO_DIRECTION "INPUT" [get_ports "MIO[9]"]
-# GPIO / gpio[8] / MIO[8]
-set_property iostandard "LVCMOS33" [get_ports "MIO[8]"]
-set_property PACKAGE_PIN "E18" [get_ports "MIO[8]"]
-set_property slew "slow" [get_ports "MIO[8]"]
-set_property drive "8" [get_ports "MIO[8]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
-# GPIO / gpio[7] / MIO[7]
-set_property iostandard "LVCMOS33" [get_ports "MIO[7]"]
-set_property PACKAGE_PIN "D18" [get_ports "MIO[7]"]
-set_property slew "slow" [get_ports "MIO[7]"]
-set_property drive "8" [get_ports "MIO[7]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
-# Quad SPI Flash / qspi0_sclk / MIO[6]
-set_property iostandard "LVCMOS33" [get_ports "MIO[6]"]
-set_property PACKAGE_PIN "A19" [get_ports "MIO[6]"]
-set_property slew "slow" [get_ports "MIO[6]"]
-set_property drive "8" [get_ports "MIO[6]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
-# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
-set_property iostandard "LVCMOS33" [get_ports "MIO[5]"]
-set_property PACKAGE_PIN "A20" [get_ports "MIO[5]"]
-set_property slew "slow" [get_ports "MIO[5]"]
-set_property drive "8" [get_ports "MIO[5]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
-# Quad SPI Flash / qspi0_io[2] / MIO[4]
-set_property iostandard "LVCMOS33" [get_ports "MIO[4]"]
-set_property PACKAGE_PIN "E19" [get_ports "MIO[4]"]
-set_property slew "slow" [get_ports "MIO[4]"]
-set_property drive "8" [get_ports "MIO[4]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
-# Quad SPI Flash / qspi0_io[1] / MIO[3]
-set_property iostandard "LVCMOS33" [get_ports "MIO[3]"]
-set_property PACKAGE_PIN "F17" [get_ports "MIO[3]"]
-set_property slew "slow" [get_ports "MIO[3]"]
-set_property drive "8" [get_ports "MIO[3]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
-# Quad SPI Flash / qspi0_io[0] / MIO[2]
-set_property iostandard "LVCMOS33" [get_ports "MIO[2]"]
-set_property PACKAGE_PIN "A21" [get_ports "MIO[2]"]
-set_property slew "slow" [get_ports "MIO[2]"]
-set_property drive "8" [get_ports "MIO[2]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
-# Quad SPI Flash / qspi0_ss_b / MIO[1]
-set_property iostandard "LVCMOS33" [get_ports "MIO[1]"]
-set_property PACKAGE_PIN "A22" [get_ports "MIO[1]"]
-set_property slew "slow" [get_ports "MIO[1]"]
-set_property drive "8" [get_ports "MIO[1]"]
-set_property pullup "TRUE" [get_ports "MIO[1]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
-# GPIO / gpio[0] / MIO[0]
-set_property iostandard "LVCMOS33" [get_ports "MIO[0]"]
-set_property PACKAGE_PIN "G17" [get_ports "MIO[0]"]
-set_property slew "slow" [get_ports "MIO[0]"]
-set_property drive "8" [get_ports "MIO[0]"]
-set_property pullup "TRUE" [get_ports "MIO[0]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"]
-set_property PACKAGE_PIN "N16" [get_ports "DDR_VRP"]
-set_property slew "FAST" [get_ports "DDR_VRP"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"]
-set_property PACKAGE_PIN "M16" [get_ports "DDR_VRN"]
-set_property slew "FAST" [get_ports "DDR_VRN"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
-set_property iostandard "SSTL135" [get_ports "DDR_WEB"]
-set_property PACKAGE_PIN "R19" [get_ports "DDR_WEB"]
-set_property slew "SLOW" [get_ports "DDR_WEB"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
-set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"]
-set_property PACKAGE_PIN "R18" [get_ports "DDR_RAS_n"]
-set_property slew "SLOW" [get_ports "DDR_RAS_n"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
-set_property iostandard "SSTL135" [get_ports "DDR_ODT"]
-set_property PACKAGE_PIN "P18" [get_ports "DDR_ODT"]
-set_property slew "SLOW" [get_ports "DDR_ODT"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
-set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"]
-set_property PACKAGE_PIN "F20" [get_ports "DDR_DRSTB"]
-set_property slew "FAST" [get_ports "DDR_DRSTB"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[3]"]
-set_property PACKAGE_PIN "V21" [get_ports "DDR_DQS[3]"]
-set_property slew "FAST" [get_ports "DDR_DQS[3]"]
-set_property pullup "TRUE" [get_ports "DDR_DQS[3]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[2]"]
-set_property PACKAGE_PIN "N21" [get_ports "DDR_DQS[2]"]
-set_property slew "FAST" [get_ports "DDR_DQS[2]"]
-set_property pullup "TRUE" [get_ports "DDR_DQS[2]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"]
-set_property PACKAGE_PIN "H21" [get_ports "DDR_DQS[1]"]
-set_property slew "FAST" [get_ports "DDR_DQS[1]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"]
-set_property PACKAGE_PIN "C21" [get_ports "DDR_DQS[0]"]
-set_property slew "FAST" [get_ports "DDR_DQS[0]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[3]"]
-set_property PACKAGE_PIN "W21" [get_ports "DDR_DQS_n[3]"]
-set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
-set_property pullup "TRUE" [get_ports "DDR_DQS_n[3]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[2]"]
-set_property PACKAGE_PIN "P21" [get_ports "DDR_DQS_n[2]"]
-set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
-set_property pullup "TRUE" [get_ports "DDR_DQS_n[2]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"]
-set_property PACKAGE_PIN "J21" [get_ports "DDR_DQS_n[1]"]
-set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
-set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"]
-set_property PACKAGE_PIN "D21" [get_ports "DDR_DQS_n[0]"]
-set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"]
-set_property PACKAGE_PIN "G22" [get_ports "DDR_DQ[9]"]
-set_property slew "FAST" [get_ports "DDR_DQ[9]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"]
-set_property PACKAGE_PIN "G21" [get_ports "DDR_DQ[8]"]
-set_property slew "FAST" [get_ports "DDR_DQ[8]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"]
-set_property PACKAGE_PIN "F22" [get_ports "DDR_DQ[7]"]
-set_property slew "FAST" [get_ports "DDR_DQ[7]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"]
-set_property PACKAGE_PIN "F21" [get_ports "DDR_DQ[6]"]
-set_property slew "FAST" [get_ports "DDR_DQ[6]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"]
-set_property PACKAGE_PIN "E22" [get_ports "DDR_DQ[5]"]
-set_property slew "FAST" [get_ports "DDR_DQ[5]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"]
-set_property PACKAGE_PIN "E20" [get_ports "DDR_DQ[4]"]
-set_property slew "FAST" [get_ports "DDR_DQ[4]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"]
-set_property PACKAGE_PIN "D20" [get_ports "DDR_DQ[3]"]
-set_property slew "FAST" [get_ports "DDR_DQ[3]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[31]"]
-set_property PACKAGE_PIN "Y22" [get_ports "DDR_DQ[31]"]
-set_property slew "FAST" [get_ports "DDR_DQ[31]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[31]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[30]"]
-set_property PACKAGE_PIN "V20" [get_ports "DDR_DQ[30]"]
-set_property slew "FAST" [get_ports "DDR_DQ[30]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[30]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"]
-set_property PACKAGE_PIN "B21" [get_ports "DDR_DQ[2]"]
-set_property slew "FAST" [get_ports "DDR_DQ[2]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[29]"]
-set_property PACKAGE_PIN "W20" [get_ports "DDR_DQ[29]"]
-set_property slew "FAST" [get_ports "DDR_DQ[29]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[29]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[28]"]
-set_property PACKAGE_PIN "W22" [get_ports "DDR_DQ[28]"]
-set_property slew "FAST" [get_ports "DDR_DQ[28]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[28]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[27]"]
-set_property PACKAGE_PIN "U21" [get_ports "DDR_DQ[27]"]
-set_property slew "FAST" [get_ports "DDR_DQ[27]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[27]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[26]"]
-set_property PACKAGE_PIN "AA22" [get_ports "DDR_DQ[26]"]
-set_property slew "FAST" [get_ports "DDR_DQ[26]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[26]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[25]"]
-set_property PACKAGE_PIN "U22" [get_ports "DDR_DQ[25]"]
-set_property slew "FAST" [get_ports "DDR_DQ[25]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[25]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[24]"]
-set_property PACKAGE_PIN "Y20" [get_ports "DDR_DQ[24]"]
-set_property slew "FAST" [get_ports "DDR_DQ[24]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[24]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[23]"]
-set_property PACKAGE_PIN "R22" [get_ports "DDR_DQ[23]"]
-set_property slew "FAST" [get_ports "DDR_DQ[23]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[23]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[22]"]
-set_property PACKAGE_PIN "M21" [get_ports "DDR_DQ[22]"]
-set_property slew "FAST" [get_ports "DDR_DQ[22]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[22]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[21]"]
-set_property PACKAGE_PIN "T21" [get_ports "DDR_DQ[21]"]
-set_property slew "FAST" [get_ports "DDR_DQ[21]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[21]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[20]"]
-set_property PACKAGE_PIN "R20" [get_ports "DDR_DQ[20]"]
-set_property slew "FAST" [get_ports "DDR_DQ[20]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[20]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"]
-set_property PACKAGE_PIN "C20" [get_ports "DDR_DQ[1]"]
-set_property slew "FAST" [get_ports "DDR_DQ[1]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[19]"]
-set_property PACKAGE_PIN "T22" [get_ports "DDR_DQ[19]"]
-set_property slew "FAST" [get_ports "DDR_DQ[19]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[19]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[18]"]
-set_property PACKAGE_PIN "N20" [get_ports "DDR_DQ[18]"]
-set_property slew "FAST" [get_ports "DDR_DQ[18]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[18]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[17]"]
-set_property PACKAGE_PIN "T20" [get_ports "DDR_DQ[17]"]
-set_property slew "FAST" [get_ports "DDR_DQ[17]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[17]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[16]"]
-set_property PACKAGE_PIN "M22" [get_ports "DDR_DQ[16]"]
-set_property slew "FAST" [get_ports "DDR_DQ[16]"]
-set_property pullup "TRUE" [get_ports "DDR_DQ[16]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"]
-set_property PACKAGE_PIN "K20" [get_ports "DDR_DQ[15]"]
-set_property slew "FAST" [get_ports "DDR_DQ[15]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"]
-set_property PACKAGE_PIN "J22" [get_ports "DDR_DQ[14]"]
-set_property slew "FAST" [get_ports "DDR_DQ[14]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"]
-set_property PACKAGE_PIN "K22" [get_ports "DDR_DQ[13]"]
-set_property slew "FAST" [get_ports "DDR_DQ[13]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"]
-set_property PACKAGE_PIN "L20" [get_ports "DDR_DQ[12]"]
-set_property slew "FAST" [get_ports "DDR_DQ[12]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"]
-set_property PACKAGE_PIN "L21" [get_ports "DDR_DQ[11]"]
-set_property slew "FAST" [get_ports "DDR_DQ[11]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"]
-set_property PACKAGE_PIN "L22" [get_ports "DDR_DQ[10]"]
-set_property slew "FAST" [get_ports "DDR_DQ[10]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"]
-set_property PACKAGE_PIN "D22" [get_ports "DDR_DQ[0]"]
-set_property slew "FAST" [get_ports "DDR_DQ[0]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[3]"]
-set_property PACKAGE_PIN "AA21" [get_ports "DDR_DM[3]"]
-set_property slew "FAST" [get_ports "DDR_DM[3]"]
-set_property pullup "TRUE" [get_ports "DDR_DM[3]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[2]"]
-set_property PACKAGE_PIN "P22" [get_ports "DDR_DM[2]"]
-set_property slew "FAST" [get_ports "DDR_DM[2]"]
-set_property pullup "TRUE" [get_ports "DDR_DM[2]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"]
-set_property PACKAGE_PIN "H20" [get_ports "DDR_DM[1]"]
-set_property slew "FAST" [get_ports "DDR_DM[1]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
-set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"]
-set_property PACKAGE_PIN "B22" [get_ports "DDR_DM[0]"]
-set_property slew "FAST" [get_ports "DDR_DM[0]"]
-set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
-set_property iostandard "SSTL135" [get_ports "DDR_CS_n"]
-set_property PACKAGE_PIN "P17" [get_ports "DDR_CS_n"]
-set_property slew "SLOW" [get_ports "DDR_CS_n"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
-set_property iostandard "SSTL135" [get_ports "DDR_CKE"]
-set_property PACKAGE_PIN "T19" [get_ports "DDR_CKE"]
-set_property slew "SLOW" [get_ports "DDR_CKE"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
-set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"]
-set_property PACKAGE_PIN "N19" [get_ports "DDR_Clk"]
-set_property slew "FAST" [get_ports "DDR_Clk"]
-set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
-set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"]
-set_property PACKAGE_PIN "N18" [get_ports "DDR_Clk_n"]
-set_property slew "FAST" [get_ports "DDR_Clk_n"]
-set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
-set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"]
-set_property PACKAGE_PIN "P20" [get_ports "DDR_CAS_n"]
-set_property slew "SLOW" [get_ports "DDR_CAS_n"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
-set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"]
-set_property PACKAGE_PIN "M17" [get_ports "DDR_BankAddr[2]"]
-set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
-set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"]
-set_property PACKAGE_PIN "L17" [get_ports "DDR_BankAddr[1]"]
-set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
-set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"]
-set_property PACKAGE_PIN "L16" [get_ports "DDR_BankAddr[0]"]
-set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"]
-set_property PACKAGE_PIN "H18" [get_ports "DDR_Addr[9]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"]
-set_property PACKAGE_PIN "J18" [get_ports "DDR_Addr[8]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"]
-set_property PACKAGE_PIN "J17" [get_ports "DDR_Addr[7]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"]
-set_property PACKAGE_PIN "J16" [get_ports "DDR_Addr[6]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"]
-set_property PACKAGE_PIN "K18" [get_ports "DDR_Addr[5]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"]
-set_property PACKAGE_PIN "K17" [get_ports "DDR_Addr[4]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"]
-set_property PACKAGE_PIN "L19" [get_ports "DDR_Addr[3]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"]
-set_property PACKAGE_PIN "K19" [get_ports "DDR_Addr[2]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"]
-set_property PACKAGE_PIN "M18" [get_ports "DDR_Addr[1]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"]
-set_property PACKAGE_PIN "G19" [get_ports "DDR_Addr[14]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"]
-set_property PACKAGE_PIN "F19" [get_ports "DDR_Addr[13]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"]
-set_property PACKAGE_PIN "H19" [get_ports "DDR_Addr[12]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"]
-set_property PACKAGE_PIN "G18" [get_ports "DDR_Addr[11]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"]
-set_property PACKAGE_PIN "J20" [get_ports "DDR_Addr[10]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
-set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"]
-set_property PACKAGE_PIN "M19" [get_ports "DDR_Addr[0]"]
-set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
-set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
-set_property iostandard "LVCMOS33" [get_ports "PS_PORB"]
-set_property PACKAGE_PIN "B18" [get_ports "PS_PORB"]
-set_property slew "fast" [get_ports "PS_PORB"]
-set_property iostandard "LVCMOS25" [get_ports "PS_SRSTB"]
-set_property PACKAGE_PIN "C14" [get_ports "PS_SRSTB"]
-set_property slew "fast" [get_ports "PS_SRSTB"]
-set_property iostandard "LVCMOS33" [get_ports "PS_CLK"]
-set_property PACKAGE_PIN "F16" [get_ports "PS_CLK"]
-set_property slew "fast" [get_ports "PS_CLK"]
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xml
deleted file mode 100644
index 43a71a2d6f2407b8381ef0f393659ec12fa5383c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xml
+++ /dev/null
@@ -1,40057 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>customized_ip</spirit:library>
- <spirit:name>scalp_zynqps_processing_system7_0_0</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:busInterfaces>
- <spirit:busInterface>
- <spirit:name>GMII_ETHERNET_0</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gmii" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gmii_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TX_EN</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_TX_EN</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TX_ER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_TX_ER</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TXD</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_TXD</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>COL</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_COL</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>CRS</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_CRS</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RX_CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_RX_CLK</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RX_DV</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_RX_DV</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RX_ER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_RX_ER</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TX_CLK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_TX_CLK</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RXD</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_GMII_RXD</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GMII_ETHERNET_0" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_ENET0)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>MDIO_ETHERNET_0</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mdio" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mdio_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>MDC</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_MDIO_MDC</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>MDIO_O</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_MDIO_O</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>MDIO_T</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_MDIO_T</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>MDIO_I</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_MDIO_I</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>CAN_DEBUG</spirit:name>
- <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.MDIO_ETHERNET_0.CAN_DEBUG">false</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>none</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.MDIO_ETHERNET_0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_ENET0_GRP_MDIO_IO)) = 'EMIO') && (spirit:decode(id(PARAM_VALUE.PCW_ENET0_GRP_MDIO_ENABLE)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>PTP_ETHERNET_0</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ptp" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ptp_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DELAY_REQ_RX</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_PTP_DELAY_REQ_RX</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>DELAY_REQ_TX</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_PTP_DELAY_REQ_TX</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>PDELAY_REQ_RX</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>ENET0_PTP_PDELAY_REQ_RX</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
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- <xilinx:parameterUsage>none</xilinx:parameterUsage>
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- <xilinx:parameterUsage>none</xilinx:parameterUsage>
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- <spirit:name>CAS_LATENCY</spirit:name>
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- <xilinx:parameterUsage>none</xilinx:parameterUsage>
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- <xilinx:parameterUsage>none</xilinx:parameterUsage>
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- <spirit:name>UART1_CTSN</spirit:name>
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- <spirit:name>DCDn</spirit:name>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.IIC_0" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_I2C0)) = 1)">false</xilinx:isEnabled>
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- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_REQ.FREQ_HZ">100000000</spirit:value>
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- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.TDEST_WIDTH">0</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.TID_WIDTH">0</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.HAS_TREADY">1</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.HAS_TKEEP">0</spirit:value>
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- <spirit:name>HAS_TLAST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.HAS_TLAST">0</spirit:value>
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- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.FREQ_HZ">100000000</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.PHASE">0.000</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.CLK_DOMAIN"/>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DMA0_ACK.INSERT_VIP">0</spirit:value>
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- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TLAST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA1_DRLAST</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA1_DRVALID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA1_DRTYPE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>TDATA_NUM_BYTES</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.TDATA_NUM_BYTES">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TDEST_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.TDEST_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.TID_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.TUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TREADY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.HAS_TREADY">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.HAS_TSTRB">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TKEEP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.HAS_TKEEP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TLAST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.HAS_TLAST">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>LAYERED_METADATA</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.LAYERED_METADATA">undef</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DMA1_REQ.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DMA1_REQ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>DMA1_ACK</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA1_DATYPE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA1_DAVALID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA1_DAREADY</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>TDATA_NUM_BYTES</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.TDATA_NUM_BYTES">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TDEST_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.TDEST_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.TID_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.TUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TREADY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.HAS_TREADY">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.HAS_TSTRB">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TKEEP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.HAS_TKEEP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TLAST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.HAS_TLAST">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>LAYERED_METADATA</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.LAYERED_METADATA">undef</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DMA1_ACK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DMA1_ACK" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>DMA2_REQ</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA2_DRREADY</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TLAST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA2_DRLAST</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA2_DRVALID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA2_DRTYPE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>TDATA_NUM_BYTES</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.TDATA_NUM_BYTES">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TDEST_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.TDEST_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.TID_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.TUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TREADY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.HAS_TREADY">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.HAS_TSTRB">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TKEEP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.HAS_TKEEP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_TLAST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.HAS_TLAST">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>LAYERED_METADATA</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.LAYERED_METADATA">undef</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DMA2_REQ.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
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- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DMA2_REQ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>DMA2_ACK</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA2_DATYPE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA2_DAVALID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA2_DAREADY</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>TDATA_NUM_BYTES</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.TDATA_NUM_BYTES">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TDEST_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.TDEST_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.TID_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.TUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_TREADY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.HAS_TREADY">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_TSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.HAS_TSTRB">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_TKEEP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.HAS_TKEEP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_TLAST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.HAS_TLAST">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>LAYERED_METADATA</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.LAYERED_METADATA">undef</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DMA2_ACK.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DMA2_ACK" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>DMA3_REQ</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:slave/>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA3_DRREADY</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TLAST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA3_DRLAST</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA3_DRVALID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA3_DRTYPE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
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- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>TDATA_NUM_BYTES</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.TDATA_NUM_BYTES">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>TDEST_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.TDEST_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>TID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.TID_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>TUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.TUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_TREADY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.HAS_TREADY">1</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_TSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.HAS_TSTRB">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_TKEEP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.HAS_TKEEP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
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- <spirit:parameter>
- <spirit:name>HAS_TLAST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.HAS_TLAST">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>LAYERED_METADATA</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.LAYERED_METADATA">undef</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DMA3_REQ.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DMA3_REQ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>DMA3_ACK</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
- <spirit:master/>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TUSER</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA3_DATYPE</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA3_DAVALID</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>TREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>DMA3_DAREADY</spirit:name>
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- <spirit:parameter>
- <spirit:name>TDATA_NUM_BYTES</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.TDATA_NUM_BYTES">1</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>TDEST_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.TDEST_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>TID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.TID_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>TUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.TUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_TREADY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.HAS_TREADY">1</spirit:value>
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- <spirit:name>HAS_TSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.HAS_TSTRB">0</spirit:value>
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- <spirit:name>HAS_TKEEP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.HAS_TKEEP">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_TLAST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.HAS_TLAST">0</spirit:value>
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- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.FREQ_HZ">100000000</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.CLK_DOMAIN"/>
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- <spirit:name>LAYERED_METADATA</spirit:name>
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- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DMA3_ACK.INSERT_VIP">0</spirit:value>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.DMA3_ACK" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)">false</xilinx:isEnabled>
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- <spirit:name>FTM_TRACE_DATA</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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- <spirit:name>FTMD_TRACEIN_DATA</spirit:name>
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- <spirit:name>TVALID</spirit:name>
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- <spirit:name>FTMD_TRACEIN_VALID</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FTM_TRACE_DATA.FREQ_HZ">100000000</spirit:value>
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- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FTM_TRACE_DATA.PHASE">0.000</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_LOCK">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_PROT</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_PROT">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_CACHE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_CACHE">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_QOS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_QOS">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>HAS_REGION</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_REGION">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_WSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_WSTRB">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_BRESP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_BRESP">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_RRESP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.HAS_RRESP">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.SUPPORTS_NARROW_BURST">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>MAX_BURST_LENGTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.MAX_BURST_LENGTH">256</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>NUM_READ_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.NUM_READ_THREADS">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>NUM_WRITE_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.NUM_WRITE_THREADS">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.RUSER_BITS_PER_BYTE">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.WUSER_BITS_PER_BYTE">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP0.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_GP0" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_GP0)) = 1)">false</xilinx:isEnabled>
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- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>S_AXI_GP1</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
- <spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_GP1"/>
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- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARREADY</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWREADY</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_BVALID</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RLAST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_RLAST</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_RVALID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_WREADY</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BRESP</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_BRESP</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RRESP</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_RRESP</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RDATA</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_RDATA</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_BID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_RID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARVALID</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWVALID</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_BREADY</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_RREADY</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WLAST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_WLAST</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_WVALID</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARBURST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARBURST</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLOCK</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARLOCK</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARSIZE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARSIZE</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWBURST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWBURST</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWLOCK</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWLOCK</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWSIZE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWSIZE</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARPROT</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARPROT</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWPROT</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWPROT</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARADDR</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARADDR</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWADDR</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWADDR</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WDATA</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_WDATA</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARCACHE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARCACHE</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLEN</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARLEN</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARQOS</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARQOS</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWCACHE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWCACHE</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWLEN</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWLEN</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWQOS</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWQOS</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>WSTRB</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_WSTRB</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_ARID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_AWID</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_GP1_WID</spirit:name>
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- </spirit:portMap>
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- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
- <spirit:displayName>NUM WRITE OUTSTANDING</spirit:displayName>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.NUM_WRITE_OUTSTANDING" spirit:order="87894">8</spirit:value>
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- <spirit:parameter>
- <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
- <spirit:displayName>NUM READ OUTSTANDING</spirit:displayName>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.NUM_READ_OUTSTANDING" spirit:order="87895">8</spirit:value>
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- <spirit:parameter>
- <spirit:name>DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.DATA_WIDTH">32</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>PROTOCOL</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.PROTOCOL">AXI4</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.ID_WIDTH">0</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>ADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.ADDR_WIDTH">32</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>AWUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.AWUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>ARUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.ARUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>WUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.WUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>RUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.RUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>BUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.BUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>READ_WRITE_MODE</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_GP1.READ_WRITE_MODE">READ_WRITE</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.BUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>READ_WRITE_MODE</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.READ_WRITE_MODE">READ_WRITE</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_BURST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_BURST">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_LOCK</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_LOCK">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>HAS_PROT</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_PROT">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_CACHE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_CACHE">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>HAS_QOS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_QOS">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_REGION</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_REGION">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_WSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_WSTRB">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_BRESP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_BRESP">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>HAS_RRESP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.HAS_RRESP">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.SUPPORTS_NARROW_BURST">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>MAX_BURST_LENGTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.MAX_BURST_LENGTH">256</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>NUM_READ_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.NUM_READ_THREADS">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>NUM_WRITE_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.NUM_WRITE_THREADS">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.RUSER_BITS_PER_BYTE">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.WUSER_BITS_PER_BYTE">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP0.INSERT_VIP">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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- <spirit:vendorExtensions>
- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_HP0" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP0)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:busInterfaceInfo>
- </spirit:vendorExtensions>
- </spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>S_AXI_HP1</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
- <spirit:slave>
- <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_HP1"/>
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- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARREADY</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWREADY</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_BVALID</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RLAST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_RLAST</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_RVALID</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_WREADY</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BRESP</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_BRESP</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RRESP</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_RRESP</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_BID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_RID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_RDATA</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARVALID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWVALID</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>BREADY</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_BREADY</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RREADY</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_RREADY</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WLAST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_WLAST</spirit:name>
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- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WVALID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_WVALID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARBURST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARBURST</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLOCK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARLOCK</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARSIZE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARSIZE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWBURST</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWBURST</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWLOCK</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWLOCK</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWSIZE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWSIZE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARPROT</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARPROT</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWPROT</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWPROT</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARADDR</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARADDR</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWADDR</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWADDR</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARCACHE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARCACHE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLEN</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARLEN</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARQOS</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARQOS</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWCACHE</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWCACHE</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWLEN</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWLEN</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWQOS</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWQOS</spirit:name>
- </spirit:physicalPort>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_ARID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_AWID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WID</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_WID</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WDATA</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_WDATA</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WSTRB</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>S_AXI_HP1_WSTRB</spirit:name>
- </spirit:physicalPort>
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- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
- <spirit:displayName>NUM WRITE OUTSTANDING</spirit:displayName>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.NUM_WRITE_OUTSTANDING" spirit:order="87886">8</spirit:value>
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- <spirit:parameter>
- <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
- <spirit:displayName>NUM READ OUTSTANDING</spirit:displayName>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.NUM_READ_OUTSTANDING" spirit:order="87887">8</spirit:value>
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- <spirit:parameter>
- <spirit:name>DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.DATA_WIDTH">32</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>PROTOCOL</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.PROTOCOL">AXI4</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.FREQ_HZ">100000000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.ID_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>ADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.ADDR_WIDTH">32</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>AWUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.AWUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>ARUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.ARUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>WUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP1.WUSER_WIDTH">0</spirit:value>
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- <spirit:name>WUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.WUSER_WIDTH">0</spirit:value>
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- <spirit:name>RUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.RUSER_WIDTH">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>BUSER_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.BUSER_WIDTH">0</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>READ_WRITE_MODE</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.READ_WRITE_MODE">READ_WRITE</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_BURST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_BURST">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>HAS_LOCK</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_LOCK">1</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_PROT</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_PROT">1</spirit:value>
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- <spirit:name>HAS_CACHE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_CACHE">1</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_QOS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_QOS">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>HAS_REGION</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_REGION">1</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_WSTRB</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_WSTRB">1</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_BRESP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_BRESP">1</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>HAS_RRESP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.HAS_RRESP">1</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.SUPPORTS_NARROW_BURST">1</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>MAX_BURST_LENGTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.MAX_BURST_LENGTH">256</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>PHASE</spirit:name>
- <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.PHASE">0.000</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.CLK_DOMAIN"/>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>NUM_READ_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.NUM_READ_THREADS">1</spirit:value>
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- <spirit:name>NUM_WRITE_THREADS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.NUM_WRITE_THREADS">1</spirit:value>
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- <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.RUSER_BITS_PER_BYTE">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.WUSER_BITS_PER_BYTE">0</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>INSERT_VIP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP2.INSERT_VIP">0</spirit:value>
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- <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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- <xilinx:busInterfaceInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.S_AXI_HP2" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP2)) = 1)">false</xilinx:isEnabled>
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- <spirit:busInterface>
- <spirit:name>S_AXI_HP3</spirit:name>
- <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
- <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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- <spirit:memoryMapRef spirit:memoryMapRef="S_AXI_HP3"/>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARREADY</spirit:name>
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- <spirit:name>S_AXI_HP3_ARREADY</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWREADY</spirit:name>
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- <spirit:name>S_AXI_HP3_AWREADY</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>BVALID</spirit:name>
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- <spirit:name>S_AXI_HP3_BVALID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>RLAST</spirit:name>
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- <spirit:name>S_AXI_HP3_RLAST</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>RVALID</spirit:name>
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- <spirit:name>S_AXI_HP3_RVALID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WREADY</spirit:name>
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- <spirit:name>S_AXI_HP3_WREADY</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>BRESP</spirit:name>
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- <spirit:name>S_AXI_HP3_BRESP</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>RRESP</spirit:name>
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- <spirit:name>S_AXI_HP3_RRESP</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>BID</spirit:name>
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- <spirit:name>S_AXI_HP3_BID</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>RID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_RID</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>RDATA</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_RDATA</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>ARVALID</spirit:name>
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- <spirit:name>S_AXI_HP3_ARVALID</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWVALID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWVALID</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>BREADY</spirit:name>
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- <spirit:name>S_AXI_HP3_BREADY</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>RREADY</spirit:name>
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- <spirit:name>S_AXI_HP3_RREADY</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>WLAST</spirit:name>
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- <spirit:name>S_AXI_HP3_WLAST</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>WVALID</spirit:name>
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- <spirit:name>S_AXI_HP3_WVALID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARBURST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARBURST</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLOCK</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARLOCK</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARSIZE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARSIZE</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWBURST</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWBURST</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWLOCK</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWLOCK</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWSIZE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWSIZE</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>ARPROT</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARPROT</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWPROT</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWPROT</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARADDR</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARADDR</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWADDR</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWADDR</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARCACHE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARCACHE</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARLEN</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARLEN</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>ARQOS</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARQOS</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWCACHE</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWCACHE</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWLEN</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWLEN</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>AWQOS</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWQOS</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>ARID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_ARID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>AWID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_AWID</spirit:name>
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- <spirit:logicalPort>
- <spirit:name>WID</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_WID</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WDATA</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_WDATA</spirit:name>
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- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>WSTRB</spirit:name>
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- <spirit:physicalPort>
- <spirit:name>S_AXI_HP3_WSTRB</spirit:name>
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- <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
- <spirit:displayName>NUM WRITE OUTSTANDING</spirit:displayName>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_HP3.NUM_WRITE_OUTSTANDING" spirit:order="87890">8</spirit:value>
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- <spirit:parameter>
- <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
- <spirit:displayName>NUM READ OUTSTANDING</spirit:displayName>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_HP3.NUM_READ_OUTSTANDING" spirit:order="87891">8</spirit:value>
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- <spirit:parameter>
- <spirit:name>DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP3.DATA_WIDTH">32</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>PROTOCOL</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP3.PROTOCOL">AXI4</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:parameter>
- <spirit:name>FREQ_HZ</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP3.FREQ_HZ">100000000</spirit:value>
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- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP3.ID_WIDTH">0</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
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- <spirit:name>ADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_HP3.ADDR_WIDTH">32</spirit:value>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.IRQ_P2F_ENET_WAKE0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_P2F_ENET0_INTR)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1))">false</xilinx:isEnabled>
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- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_HIGH_OCM" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_HIGH_OCM)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_QSPI_LINEAR</spirit:name>
- <spirit:displayName>GP0 QSPI LINEAR</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xfc000000</spirit:baseAddress>
- <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(PARAM_VALUE.PCW_QSPI_INTERNAL_HIGHADDRESS))) - 0xfbffffff )">16777216</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>memory</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_QSPI_LINEAR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE)) = 1)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_SRAM_NOR0</spirit:name>
- <spirit:displayName>GP0 SRAM NOR 0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe2000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x02000000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>memory</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_SRAM_NOR0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE)) = 1) && ((spirit:decode(id(PARAM_VALUE.PCW_NOR_GRP_CS0_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_ENABLE)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_SRAM_NOR1</spirit:name>
- <spirit:displayName>GP0 SRAM NOR 1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe4000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x02000000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>memory</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_SRAM_NOR1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE)) = 1) && ((spirit:decode(id(PARAM_VALUE.PCW_NOR_GRP_CS1_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NOR_GRP_A25_ENABLE)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_NAND</spirit:name>
- <spirit:displayName>GP0 NAND</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe1000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x01000000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>memory</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_NAND" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_IOP</spirit:name>
- <spirit:displayName>GP0 IOP</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00400000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_IOP" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 0) && ((spirit:decode(id(PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_USB1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_ENET1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE)) = 1)))">true</xilinx:isEnabled>
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- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_UART0</spirit:name>
- <spirit:displayName>GP0 UART0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_UART0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_UART1</spirit:name>
- <spirit:displayName>GP0 UART0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0001000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_UART1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_USB0</spirit:name>
- <spirit:displayName>GP0 USB0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0002000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_USB0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_USB1</spirit:name>
- <spirit:displayName>GP0 USB1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0003000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_USB1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USB1_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_IIC0</spirit:name>
- <spirit:displayName>GP0 IIC0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0004000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_IIC0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_IIC1</spirit:name>
- <spirit:displayName>GP0 IIC1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0005000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_IIC1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_SPI0</spirit:name>
- <spirit:displayName>GP0 SPI0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0006000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_SPI0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_SPI1</spirit:name>
- <spirit:displayName>GP0 SPI1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0007000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_SPI1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_CAN0</spirit:name>
- <spirit:displayName>GP0 CAN0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0008000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_CAN0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_CAN1</spirit:name>
- <spirit:displayName>GP0 CAN1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0009000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_CAN1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_GPIO</spirit:name>
- <spirit:displayName>GP0 GPIO</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000A000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_GPIO" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_ENET0</spirit:name>
- <spirit:displayName>GP0 ENET0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000B000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_ENET0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_ENET1</spirit:name>
- <spirit:displayName>GP0 ENET1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000C000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_ENET1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_ENET1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
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- <spirit:addressBlock>
- <spirit:name>GP0_QSPI</spirit:name>
- <spirit:displayName>GP0 QSPI</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000D000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_QSPI" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP0_SMC</spirit:name>
- <spirit:displayName>GP0 SMC</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000e000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_SMC" xilinx:dependency="(((spirit:decode(id(PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE)) = 1)) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_SDIO0</spirit:name>
- <spirit:displayName>GP0 SDIO0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0100000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_SDIO0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
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- <spirit:addressBlock>
- <spirit:name>GP0_SDIO1</spirit:name>
- <spirit:displayName>GP0 SDIO1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0101000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP0.GP0_SDIO1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP0_PS_SLCR_REGS</spirit:name>
- <spirit:displayName>GP0 PS REG</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xf8000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00010000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_NAND" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP1_IOP</spirit:name>
- <spirit:displayName>GP1 IOP</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00400000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_IOP" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 0) && ((spirit:decode(id(PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_USB1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_ENET1_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE)) = 1)))">true</xilinx:isEnabled>
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- <spirit:name>GP1_UART0</spirit:name>
- <spirit:displayName>GP1 UART0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_UART0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:name>GP1_UART1</spirit:name>
- <spirit:displayName>GP1 UART0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0001000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_UART1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
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- <spirit:addressBlock>
- <spirit:name>GP1_USB0</spirit:name>
- <spirit:displayName>GP1 USB0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0002000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_USB0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:name>GP1_USB1</spirit:name>
- <spirit:displayName>GP1 USB1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0003000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_USB1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USB1_PERIPHERAL_ENABLE)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP1_IIC0</spirit:name>
- <spirit:displayName>GP1 IIC0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0004000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_IIC0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP1_IIC1</spirit:name>
- <spirit:displayName>GP1 IIC1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0005000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
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- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_IIC1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP1_SPI0</spirit:name>
- <spirit:displayName>GP1 SPI0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0006000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_SPI0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- </xilinx:addressBlockInfo>
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- <spirit:addressBlock>
- <spirit:name>GP1_SPI1</spirit:name>
- <spirit:displayName>GP1 SPI1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0007000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_SPI1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP1_CAN0</spirit:name>
- <spirit:displayName>GP1 CAN0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0008000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_CAN0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
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- <spirit:addressBlock>
- <spirit:name>GP1_CAN1</spirit:name>
- <spirit:displayName>GP1 CAN1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0009000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_CAN1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP1_GPIO</spirit:name>
- <spirit:displayName>GP1 GPIO</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000A000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_GPIO" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP1_ENET0</spirit:name>
- <spirit:displayName>GP1 ENET0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000B000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_ENET0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP1_ENET1</spirit:name>
- <spirit:displayName>GP1 ENET1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000C000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_ENET1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_ENET1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:addressBlockInfo>
- </spirit:vendorExtensions>
- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP1_QSPI</spirit:name>
- <spirit:displayName>GP1 QSPI</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000D000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_QSPI" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- </spirit:addressBlock>
- <spirit:addressBlock>
- <spirit:name>GP1_SMC</spirit:name>
- <spirit:displayName>GP1 SMC</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe000e000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_SMC" xilinx:dependency="(((spirit:decode(id(PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE)) = 1) || (spirit:decode(id(PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE)) = 1)) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP1_SDIO0</spirit:name>
- <spirit:displayName>GP1 SDIO0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0100000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
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- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_SDIO0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:name>GP1_SDIO1</spirit:name>
- <spirit:displayName>GP1 SDIO1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xe0101000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_SDIO1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_IOP)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP1_PS_SLCR_REGS</spirit:name>
- <spirit:displayName>GP1 PS REG</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xf8000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00010000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_PS_SLCR_REGS" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_PS_SLCR_REGISTERS)) = 0))">false</xilinx:isEnabled>
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- <spirit:name>GP1_SLCR</spirit:name>
- <spirit:displayName>GP1 SLCR</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xf8000000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
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- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_SLCR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_PS_SLCR_REGISTERS)) = 1))">false</xilinx:isEnabled>
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- <spirit:name>GP1_TTC0</spirit:name>
- <spirit:displayName>GP1 TTC0</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xf8001000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
- <spirit:vendorExtensions>
- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_TTC0" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_TTC0_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_PS_SLCR_REGISTERS)) = 1))">false</xilinx:isEnabled>
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- <spirit:name>GP1_TTC1</spirit:name>
- <spirit:displayName>GP1 TTC1</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xf8002000</spirit:baseAddress>
- <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00001000</spirit:range>
- <spirit:width spirit:format="long">32</spirit:width>
- <spirit:usage>register</spirit:usage>
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- <xilinx:addressBlockInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.S_AXI_GP1.GP1_TTC1" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_TTC1_PERIPHERAL_ENABLE)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS)) = 1) && (spirit:decode(id(PARAM_VALUE.PCW_USE_EXPANDED_PS_SLCR_REGISTERS)) = 1))">false</xilinx:isEnabled>
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- <spirit:addressBlock>
- <spirit:name>GP1_DMAC_S</spirit:name>
- <spirit:displayName>GP1 DMAC S</spirit:displayName>
- <spirit:baseAddress spirit:format="bitString" spirit:bitStringLength="32">0xf8003000</spirit:baseAddress>
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- <spirit:name>S_AXI_GP0_wr_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>wr_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_GP1_rd_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>rd_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_GP1_wr_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>wr_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP0_rd_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>rd_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP0_wr_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>wr_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP1_rd_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>rd_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP1_wr_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>wr_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP2_rd_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>rd_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP2_wr_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>wr_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP3_rd_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>rd_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_HP3_wr_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>wr_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_ACP_rd_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>rd_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- <spirit:port>
- <spirit:name>S_AXI_ACP_wr_socket</spirit:name>
- <spirit:transactional>
- <spirit:transTypeDef>
- <spirit:typeName>xtlm::xtlm_aximm_target_socket</spirit:typeName>
- <spirit:typeDefinition>xtlm.h</spirit:typeDefinition>
- </spirit:transTypeDef>
- <spirit:service>
- <spirit:initiative>provides</spirit:initiative>
- <spirit:serviceTypeDefs>
- <spirit:serviceTypeDef>
- <spirit:typeName>tlm</spirit:typeName>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>name</spirit:name>
- <spirit:value>wr_socket</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>width</spirit:name>
- <spirit:value>32</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </spirit:serviceTypeDef>
- </spirit:serviceTypeDefs>
- </spirit:service>
- <spirit:connection>
- <spirit:maxConnections>1</spirit:maxConnections>
- </spirit:connection>
- </spirit:transactional>
- </spirit:port>
- </spirit:ports>
- <spirit:modelParameters>
- <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="INTEGER">
- <spirit:name>C_EN_EMIO_PJTAG</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_EN_EMIO_PJTAG" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_PJTAG))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_EN_EMIO_ENET0</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_EN_EMIO_ENET0" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_ENET0))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_EN_EMIO_ENET1</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_EN_EMIO_ENET1" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_ENET1))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_EN_EMIO_TRACE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_EN_EMIO_TRACE" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_TRACE))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_INCLUDE_TRACE_BUFFER</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_INCLUDE_TRACE_BUFFER" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_INCLUDE_TRACE_BUFFER))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_TRACE_BUFFER_FIFO_SIZE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_TRACE_BUFFER_FIFO_SIZE" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_TRACE_BUFFER_FIFO_SIZE))">128</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>USE_TRACE_DATA_EDGE_DETECTOR</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.USE_TRACE_DATA_EDGE_DETECTOR" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_TRACE_DATA_EDGE_DETECTOR))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_TRACE_PIPELINE_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_TRACE_PIPELINE_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_TRACE_PIPELINE_WIDTH))">8</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_TRACE_BUFFER_CLOCK_DELAY</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_TRACE_BUFFER_CLOCK_DELAY" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_TRACE_BUFFER_CLOCK_DELAY))">12</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_EMIO_GPIO_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_EMIO_GPIO_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_GPIO_EMIO_GPIO_WIDTH))">64</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_INCLUDE_ACP_TRANS_CHECK</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_INCLUDE_ACP_TRANS_CHECK" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_INCLUDE_ACP_TRANS_CHECK))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_DEFAULT_ACP_USER_VAL</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_DEFAULT_ACP_USER_VAL" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_DEFAULT_ACP_USER_VAL))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_ACP_ARUSER_VAL</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_ACP_ARUSER_VAL" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_ACP_ARUSER_VAL))">31</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_ACP_AWUSER_VAL</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_ACP_AWUSER_VAL" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_ACP_AWUSER_VAL))">31</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_M_AXI_GP0_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_M_AXI_GP0_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_M_AXI_GP0_ID_WIDTH))">12</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_M_AXI_GP0_ENABLE_STATIC_REMAP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_M_AXI_GP0_ENABLE_STATIC_REMAP" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_M_AXI_GP1_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_M_AXI_GP1_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_M_AXI_GP1_ID_WIDTH))">12</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_M_AXI_GP1_ENABLE_STATIC_REMAP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_M_AXI_GP1_ENABLE_STATIC_REMAP" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_GP0_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_GP0_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_GP0_ID_WIDTH))">6</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_GP1_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_GP1_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_GP1_ID_WIDTH))">6</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_ACP_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_ACP_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_ACP_ID_WIDTH))">3</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP0_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP0_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP0_ID_WIDTH))">6</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP0_DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP0_DATA_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP0_DATA_WIDTH))">64</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP1_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP1_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP1_ID_WIDTH))">6</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP1_DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP1_DATA_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP1_DATA_WIDTH))">64</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP2_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP2_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP2_ID_WIDTH))">6</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP2_DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP2_DATA_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP2_DATA_WIDTH))">64</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP3_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP3_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP3_ID_WIDTH))">6</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_S_AXI_HP3_DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_S_AXI_HP3_DATA_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_S_AXI_HP3_DATA_WIDTH))">64</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_M_AXI_GP0_THREAD_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_M_AXI_GP0_THREAD_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_M_AXI_GP0_THREAD_ID_WIDTH))">12</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_M_AXI_GP1_THREAD_ID_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_M_AXI_GP1_THREAD_ID_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_M_AXI_GP1_THREAD_ID_WIDTH))">12</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_NUM_F2P_INTR_INPUTS</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_NUM_F2P_INTR_INPUTS" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_NUM_F2P_INTR_INPUTS))">1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_IRQ_F2P_MODE</spirit:name>
- <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_IRQ_F2P_MODE" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_IRQ_F2P_MODE))">DIRECT</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_DQ_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_DQ_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_DQ_WIDTH))">32</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_DQS_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_DQS_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_DQS_WIDTH))">4</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_DM_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_DM_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_DM_WIDTH))">4</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_MIO_PRIMITIVE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_MIO_PRIMITIVE" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_MIO_PRIMITIVE))">54</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_TRACE_INTERNAL_WIDTH</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_TRACE_INTERNAL_WIDTH" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_TRACE_INTERNAL_WIDTH))">2</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_AXI_NONSECURE</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_AXI_NONSECURE" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_AXI_NONSECURE))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_M_AXI_GP0</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_M_AXI_GP0" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP0))">1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_M_AXI_GP1</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_M_AXI_GP1" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP1))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_S_AXI_GP0</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_S_AXI_GP0" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_GP0))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_S_AXI_GP1</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_S_AXI_GP1" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_GP1))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_S_AXI_HP0</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_S_AXI_HP0" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP0))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_S_AXI_HP1</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_S_AXI_HP1" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP1))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_S_AXI_HP2</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_S_AXI_HP2" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP2))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_S_AXI_HP3</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_S_AXI_HP3" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP3))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="INTEGER">
- <spirit:name>C_USE_S_AXI_ACP</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_USE_S_AXI_ACP" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_ACP))">0</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_PS7_SI_REV</spirit:name>
- <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_PS7_SI_REV" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_PS7_SI_REV))">PRODUCTION</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_FCLK_CLK0_BUF</spirit:name>
- <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_FCLK_CLK0_BUF" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_FCLK_CLK0_BUF))">TRUE</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_FCLK_CLK1_BUF</spirit:name>
- <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_FCLK_CLK1_BUF" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_FCLK_CLK1_BUF))">FALSE</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_FCLK_CLK2_BUF</spirit:name>
- <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_FCLK_CLK2_BUF" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_FCLK_CLK2_BUF))">FALSE</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_FCLK_CLK3_BUF</spirit:name>
- <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_FCLK_CLK3_BUF" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_FCLK_CLK3_BUF))">FALSE</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_PACKAGE_NAME</spirit:name>
- <spirit:value spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_PACKAGE_NAME" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_PACKAGE_NAME))">clg485</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_GP0_EN_MODIFIABLE_TXN</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_GP0_EN_MODIFIABLE_TXN" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_GP0_EN_MODIFIABLE_TXN))">1</spirit:value>
- </spirit:modelParameter>
- <spirit:modelParameter spirit:dataType="STRING">
- <spirit:name>C_GP1_EN_MODIFIABLE_TXN</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="dependent" spirit:id="MODELPARAM_VALUE.C_GP1_EN_MODIFIABLE_TXN" spirit:dependency="spirit:decode(id(PARAM_VALUE.PCW_GP1_EN_MODIFIABLE_TXN))">1</spirit:value>
- </spirit:modelParameter>
- </spirit:modelParameters>
- </spirit:model>
- <spirit:choices>
- <spirit:choice>
- <spirit:name>choice_list_020b381d</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>MIO 40 .. 51</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_070fff2f</spirit:name>
- <spirit:enumeration>1</spirit:enumeration>
- <spirit:enumeration>2</spirit:enumeration>
- <spirit:enumeration>3</spirit:enumeration>
- <spirit:enumeration>4</spirit:enumeration>
- <spirit:enumeration>5</spirit:enumeration>
- <spirit:enumeration>6</spirit:enumeration>
- <spirit:enumeration>7</spirit:enumeration>
- <spirit:enumeration>8</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_0d7de060</spirit:name>
- <spirit:enumeration>ARM PLL</spirit:enumeration>
- <spirit:enumeration>DDR PLL</spirit:enumeration>
- <spirit:enumeration>IO PLL</spirit:enumeration>
- <spirit:enumeration>External</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_0f5c91ba</spirit:name>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 8 .. 9</spirit:enumeration>
- <spirit:enumeration>MIO 12 .. 13</spirit:enumeration>
- <spirit:enumeration>MIO 16 .. 17</spirit:enumeration>
- <spirit:enumeration>MIO 20 .. 21</spirit:enumeration>
- <spirit:enumeration>MIO 24 .. 25</spirit:enumeration>
- <spirit:enumeration>MIO 28 .. 29</spirit:enumeration>
- <spirit:enumeration>MIO 32 .. 33</spirit:enumeration>
- <spirit:enumeration>MIO 36 .. 37</spirit:enumeration>
- <spirit:enumeration>MIO 40 .. 41</spirit:enumeration>
- <spirit:enumeration>MIO 44 .. 45</spirit:enumeration>
- <spirit:enumeration>MIO 48 .. 49</spirit:enumeration>
- <spirit:enumeration>MIO 52 .. 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_1075ca33</spirit:name>
- <spirit:enumeration>4</spirit:enumeration>
- <spirit:enumeration>2</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_13f07802</spirit:name>
- <spirit:enumeration>DISABLED</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_1622b516</spirit:name>
- <spirit:enumeration>MIO 28 .. 39</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_1a80fa5a</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 18 .. 19</spirit:enumeration>
- <spirit:enumeration>MIO 30 .. 31</spirit:enumeration>
- <spirit:enumeration>MIO 42 .. 43</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_2091a159</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>MIO 0 2.. 14</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_20dc6536</spirit:name>
- <spirit:enumeration>32</spirit:enumeration>
- <spirit:enumeration>16</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_2328412a</spirit:name>
- <spirit:enumeration>HPR(0)/LPR(32)</spirit:enumeration>
- <spirit:enumeration>HPR(8)/LPR(24)</spirit:enumeration>
- <spirit:enumeration>HPR(16)/LPR(16)</spirit:enumeration>
- <spirit:enumeration>HPR(24)/LPR(8)</spirit:enumeration>
- <spirit:enumeration>HPR(32)/LPR(0)</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_27376075</spirit:name>
- <spirit:enumeration>12</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_2d7daef4</spirit:name>
- <spirit:enumeration>disabled</spirit:enumeration>
- <spirit:enumeration>enabled</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_2e355d8b</spirit:name>
- <spirit:enumeration>Normal (0-85)</spirit:enumeration>
- <spirit:enumeration>High (95 Max)</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_303d848a</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>MIO 1</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_30d18a73</spirit:name>
- <spirit:enumeration>0xE0105fff</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_319636fe</spirit:name>
- <spirit:enumeration>0xE0104fff</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_32c7371b</spirit:name>
- <spirit:enumeration>128 MBits</spirit:enumeration>
- <spirit:enumeration>256 MBits</spirit:enumeration>
- <spirit:enumeration>512 MBits</spirit:enumeration>
- <spirit:enumeration>1024 MBits</spirit:enumeration>
- <spirit:enumeration>2048 MBits</spirit:enumeration>
- <spirit:enumeration>4096 MBits</spirit:enumeration>
- <spirit:enumeration>8192 MBits</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_353a343d</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>MIO 3 .. 39</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_35b40bd0</spirit:name>
- <spirit:enumeration>6</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_3607bdd0</spirit:name>
- <spirit:enumeration>0xE0102fff</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_3740015d</spirit:name>
- <spirit:enumeration>0xE0103fff</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_390b0393</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 16 .. 21</spirit:enumeration>
- <spirit:enumeration>MIO 28 .. 33</spirit:enumeration>
- <spirit:enumeration>MIO 40 .. 45</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_3b9f1944</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>x8</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_3c74058c</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>MIO 0</spirit:enumeration>
- <spirit:enumeration>MIO 2</spirit:enumeration>
- <spirit:enumeration>MIO 4</spirit:enumeration>
- <spirit:enumeration>MIO 6</spirit:enumeration>
- <spirit:enumeration>MIO 8</spirit:enumeration>
- <spirit:enumeration>MIO 10</spirit:enumeration>
- <spirit:enumeration>MIO 12</spirit:enumeration>
- <spirit:enumeration>MIO 14</spirit:enumeration>
- <spirit:enumeration>MIO 16</spirit:enumeration>
- <spirit:enumeration>MIO 18</spirit:enumeration>
- <spirit:enumeration>MIO 20</spirit:enumeration>
- <spirit:enumeration>MIO 22</spirit:enumeration>
- <spirit:enumeration>MIO 24</spirit:enumeration>
- <spirit:enumeration>MIO 26</spirit:enumeration>
- <spirit:enumeration>MIO 28</spirit:enumeration>
- <spirit:enumeration>MIO 30</spirit:enumeration>
- <spirit:enumeration>MIO 32</spirit:enumeration>
- <spirit:enumeration>MIO 34</spirit:enumeration>
- <spirit:enumeration>MIO 36</spirit:enumeration>
- <spirit:enumeration>MIO 38</spirit:enumeration>
- <spirit:enumeration>MIO 40</spirit:enumeration>
- <spirit:enumeration>MIO 42</spirit:enumeration>
- <spirit:enumeration>MIO 44</spirit:enumeration>
- <spirit:enumeration>MIO 46</spirit:enumeration>
- <spirit:enumeration>MIO 48</spirit:enumeration>
- <spirit:enumeration>MIO 50</spirit:enumeration>
- <spirit:enumeration>MIO 52</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_3f5f808e</spirit:name>
- <spirit:enumeration>LVCMOS 3.3V</spirit:enumeration>
- <spirit:enumeration>LVCMOS 2.5V</spirit:enumeration>
- <spirit:enumeration>HSTL 1.8V</spirit:enumeration>
- <spirit:enumeration>LVCMOS 1.8V</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_45a0fd9c</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 14 .. 15</spirit:enumeration>
- <spirit:enumeration>MIO 26 .. 27</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_46eb370a</spirit:name>
- <spirit:enumeration>DIRECT</spirit:enumeration>
- <spirit:enumeration>REVERSE</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_49727578</spirit:name>
- <spirit:enumeration>0x00100000</spirit:enumeration>
- <spirit:enumeration>0x00040000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_4b3359e9</spirit:name>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 15</spirit:enumeration>
- <spirit:enumeration>MIO 27</spirit:enumeration>
- <spirit:enumeration>MIO 39</spirit:enumeration>
- <spirit:enumeration>MIO 51</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_4d36a164</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>Low</spirit:enumeration>
- <spirit:enumeration>Medium</spirit:enumeration>
- <spirit:enumeration>High</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_56e9f994</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 10 .. 13</spirit:enumeration>
- <spirit:enumeration>MIO 22 .. 25</spirit:enumeration>
- <spirit:enumeration>MIO 34 .. 37</spirit:enumeration>
- <spirit:enumeration>MIO 46 .. 49</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_5beb845c</spirit:name>
- <spirit:enumeration>x1</spirit:enumeration>
- <spirit:enumeration>x2</spirit:enumeration>
- <spirit:enumeration>x4</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_5d0f73c4</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 10 .. 11</spirit:enumeration>
- <spirit:enumeration>MIO 14 .. 15</spirit:enumeration>
- <spirit:enumeration>MIO 18 .. 19</spirit:enumeration>
- <spirit:enumeration>MIO 22 .. 23</spirit:enumeration>
- <spirit:enumeration>MIO 26 .. 27</spirit:enumeration>
- <spirit:enumeration>MIO 30 .. 31</spirit:enumeration>
- <spirit:enumeration>MIO 34 .. 35</spirit:enumeration>
- <spirit:enumeration>MIO 38 .. 39</spirit:enumeration>
- <spirit:enumeration>MIO 42 .. 43</spirit:enumeration>
- <spirit:enumeration>MIO 46 .. 47</spirit:enumeration>
- <spirit:enumeration>MIO 50 .. 51</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_5d70a6b7</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>1</spirit:enumeration>
- <spirit:enumeration>2</spirit:enumeration>
- <spirit:enumeration>3</spirit:enumeration>
- <spirit:enumeration>4</spirit:enumeration>
- <spirit:enumeration>5</spirit:enumeration>
- <spirit:enumeration>6</spirit:enumeration>
- <spirit:enumeration>7</spirit:enumeration>
- <spirit:enumeration>8</spirit:enumeration>
- <spirit:enumeration>9</spirit:enumeration>
- <spirit:enumeration>10</spirit:enumeration>
- <spirit:enumeration>11</spirit:enumeration>
- <spirit:enumeration>12</spirit:enumeration>
- <spirit:enumeration>13</spirit:enumeration>
- <spirit:enumeration>14</spirit:enumeration>
- <spirit:enumeration>15</spirit:enumeration>
- <spirit:enumeration>16</spirit:enumeration>
- <spirit:enumeration>17</spirit:enumeration>
- <spirit:enumeration>18</spirit:enumeration>
- <spirit:enumeration>19</spirit:enumeration>
- <spirit:enumeration>20</spirit:enumeration>
- <spirit:enumeration>21</spirit:enumeration>
- <spirit:enumeration>22</spirit:enumeration>
- <spirit:enumeration>23</spirit:enumeration>
- <spirit:enumeration>24</spirit:enumeration>
- <spirit:enumeration>25</spirit:enumeration>
- <spirit:enumeration>26</spirit:enumeration>
- <spirit:enumeration>27</spirit:enumeration>
- <spirit:enumeration>28</spirit:enumeration>
- <spirit:enumeration>29</spirit:enumeration>
- <spirit:enumeration>30</spirit:enumeration>
- <spirit:enumeration>31</spirit:enumeration>
- <spirit:enumeration>32</spirit:enumeration>
- <spirit:enumeration>33</spirit:enumeration>
- <spirit:enumeration>34</spirit:enumeration>
- <spirit:enumeration>35</spirit:enumeration>
- <spirit:enumeration>36</spirit:enumeration>
- <spirit:enumeration>37</spirit:enumeration>
- <spirit:enumeration>38</spirit:enumeration>
- <spirit:enumeration>39</spirit:enumeration>
- <spirit:enumeration>40</spirit:enumeration>
- <spirit:enumeration>41</spirit:enumeration>
- <spirit:enumeration>42</spirit:enumeration>
- <spirit:enumeration>43</spirit:enumeration>
- <spirit:enumeration>44</spirit:enumeration>
- <spirit:enumeration>45</spirit:enumeration>
- <spirit:enumeration>46</spirit:enumeration>
- <spirit:enumeration>47</spirit:enumeration>
- <spirit:enumeration>48</spirit:enumeration>
- <spirit:enumeration>49</spirit:enumeration>
- <spirit:enumeration>50</spirit:enumeration>
- <spirit:enumeration>51</spirit:enumeration>
- <spirit:enumeration>52</spirit:enumeration>
- <spirit:enumeration>53</spirit:enumeration>
- <spirit:enumeration>54</spirit:enumeration>
- <spirit:enumeration>55</spirit:enumeration>
- <spirit:enumeration>56</spirit:enumeration>
- <spirit:enumeration>57</spirit:enumeration>
- <spirit:enumeration>58</spirit:enumeration>
- <spirit:enumeration>59</spirit:enumeration>
- <spirit:enumeration>60</spirit:enumeration>
- <spirit:enumeration>61</spirit:enumeration>
- <spirit:enumeration>62</spirit:enumeration>
- <spirit:enumeration>63</spirit:enumeration>
- <spirit:enumeration>64</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_606c1634</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 52 .. 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_6727dfa6</spirit:name>
- <spirit:enumeration>1</spirit:enumeration>
- <spirit:enumeration>0</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_6a282484</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 0</spirit:enumeration>
- <spirit:enumeration>MIO 1</spirit:enumeration>
- <spirit:enumeration>MIO 2</spirit:enumeration>
- <spirit:enumeration>MIO 3</spirit:enumeration>
- <spirit:enumeration>MIO 4</spirit:enumeration>
- <spirit:enumeration>MIO 5</spirit:enumeration>
- <spirit:enumeration>MIO 6</spirit:enumeration>
- <spirit:enumeration>MIO 9</spirit:enumeration>
- <spirit:enumeration>MIO 10</spirit:enumeration>
- <spirit:enumeration>MIO 11</spirit:enumeration>
- <spirit:enumeration>MIO 12</spirit:enumeration>
- <spirit:enumeration>MIO 13</spirit:enumeration>
- <spirit:enumeration>MIO 14</spirit:enumeration>
- <spirit:enumeration>MIO 15</spirit:enumeration>
- <spirit:enumeration>MIO 16</spirit:enumeration>
- <spirit:enumeration>MIO 17</spirit:enumeration>
- <spirit:enumeration>MIO 18</spirit:enumeration>
- <spirit:enumeration>MIO 19</spirit:enumeration>
- <spirit:enumeration>MIO 20</spirit:enumeration>
- <spirit:enumeration>MIO 21</spirit:enumeration>
- <spirit:enumeration>MIO 22</spirit:enumeration>
- <spirit:enumeration>MIO 23</spirit:enumeration>
- <spirit:enumeration>MIO 24</spirit:enumeration>
- <spirit:enumeration>MIO 25</spirit:enumeration>
- <spirit:enumeration>MIO 26</spirit:enumeration>
- <spirit:enumeration>MIO 27</spirit:enumeration>
- <spirit:enumeration>MIO 28</spirit:enumeration>
- <spirit:enumeration>MIO 29</spirit:enumeration>
- <spirit:enumeration>MIO 30</spirit:enumeration>
- <spirit:enumeration>MIO 31</spirit:enumeration>
- <spirit:enumeration>MIO 32</spirit:enumeration>
- <spirit:enumeration>MIO 33</spirit:enumeration>
- <spirit:enumeration>MIO 34</spirit:enumeration>
- <spirit:enumeration>MIO 35</spirit:enumeration>
- <spirit:enumeration>MIO 36</spirit:enumeration>
- <spirit:enumeration>MIO 37</spirit:enumeration>
- <spirit:enumeration>MIO 38</spirit:enumeration>
- <spirit:enumeration>MIO 39</spirit:enumeration>
- <spirit:enumeration>MIO 40</spirit:enumeration>
- <spirit:enumeration>MIO 41</spirit:enumeration>
- <spirit:enumeration>MIO 42</spirit:enumeration>
- <spirit:enumeration>MIO 43</spirit:enumeration>
- <spirit:enumeration>MIO 44</spirit:enumeration>
- <spirit:enumeration>MIO 45</spirit:enumeration>
- <spirit:enumeration>MIO 46</spirit:enumeration>
- <spirit:enumeration>MIO 47</spirit:enumeration>
- <spirit:enumeration>MIO 48</spirit:enumeration>
- <spirit:enumeration>MIO 49</spirit:enumeration>
- <spirit:enumeration>MIO 50</spirit:enumeration>
- <spirit:enumeration>MIO 51</spirit:enumeration>
- <spirit:enumeration>MIO 52</spirit:enumeration>
- <spirit:enumeration>MIO 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_6a48f1e0</spirit:name>
- <spirit:enumeration>MIO</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_6b183472</spirit:name>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 14</spirit:enumeration>
- <spirit:enumeration>MIO 26</spirit:enumeration>
- <spirit:enumeration>MIO 38</spirit:enumeration>
- <spirit:enumeration>MIO 50</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_6bc4d474</spirit:name>
- <spirit:enumeration>LVCMOS 3.3V</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_6bd7fb73</spirit:name>
- <spirit:enumeration>Active High</spirit:enumeration>
- <spirit:enumeration>Active Low</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_6e6efe45</spirit:name>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 13</spirit:enumeration>
- <spirit:enumeration>MIO 25</spirit:enumeration>
- <spirit:enumeration>MIO 37</spirit:enumeration>
- <spirit:enumeration>MIO 49</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_72f3e128</spirit:name>
- <spirit:enumeration>LVCMOS 1.8V</spirit:enumeration>
- <spirit:enumeration>LVCMOS 2.5V</spirit:enumeration>
- <spirit:enumeration>LVCMOS 3.3V</spirit:enumeration>
- <spirit:enumeration>HSTL 1.8V</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_75a9626b</spirit:name>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 0</spirit:enumeration>
- <spirit:enumeration>MIO 1</spirit:enumeration>
- <spirit:enumeration>MIO 2</spirit:enumeration>
- <spirit:enumeration>MIO 3</spirit:enumeration>
- <spirit:enumeration>MIO 4</spirit:enumeration>
- <spirit:enumeration>MIO 5</spirit:enumeration>
- <spirit:enumeration>MIO 6</spirit:enumeration>
- <spirit:enumeration>MIO 9</spirit:enumeration>
- <spirit:enumeration>MIO 10</spirit:enumeration>
- <spirit:enumeration>MIO 11</spirit:enumeration>
- <spirit:enumeration>MIO 12</spirit:enumeration>
- <spirit:enumeration>MIO 13</spirit:enumeration>
- <spirit:enumeration>MIO 14</spirit:enumeration>
- <spirit:enumeration>MIO 15</spirit:enumeration>
- <spirit:enumeration>MIO 16</spirit:enumeration>
- <spirit:enumeration>MIO 17</spirit:enumeration>
- <spirit:enumeration>MIO 18</spirit:enumeration>
- <spirit:enumeration>MIO 19</spirit:enumeration>
- <spirit:enumeration>MIO 20</spirit:enumeration>
- <spirit:enumeration>MIO 21</spirit:enumeration>
- <spirit:enumeration>MIO 22</spirit:enumeration>
- <spirit:enumeration>MIO 23</spirit:enumeration>
- <spirit:enumeration>MIO 24</spirit:enumeration>
- <spirit:enumeration>MIO 25</spirit:enumeration>
- <spirit:enumeration>MIO 26</spirit:enumeration>
- <spirit:enumeration>MIO 27</spirit:enumeration>
- <spirit:enumeration>MIO 28</spirit:enumeration>
- <spirit:enumeration>MIO 29</spirit:enumeration>
- <spirit:enumeration>MIO 30</spirit:enumeration>
- <spirit:enumeration>MIO 31</spirit:enumeration>
- <spirit:enumeration>MIO 32</spirit:enumeration>
- <spirit:enumeration>MIO 33</spirit:enumeration>
- <spirit:enumeration>MIO 34</spirit:enumeration>
- <spirit:enumeration>MIO 35</spirit:enumeration>
- <spirit:enumeration>MIO 36</spirit:enumeration>
- <spirit:enumeration>MIO 37</spirit:enumeration>
- <spirit:enumeration>MIO 38</spirit:enumeration>
- <spirit:enumeration>MIO 39</spirit:enumeration>
- <spirit:enumeration>MIO 40</spirit:enumeration>
- <spirit:enumeration>MIO 41</spirit:enumeration>
- <spirit:enumeration>MIO 42</spirit:enumeration>
- <spirit:enumeration>MIO 43</spirit:enumeration>
- <spirit:enumeration>MIO 44</spirit:enumeration>
- <spirit:enumeration>MIO 45</spirit:enumeration>
- <spirit:enumeration>MIO 46</spirit:enumeration>
- <spirit:enumeration>MIO 47</spirit:enumeration>
- <spirit:enumeration>MIO 48</spirit:enumeration>
- <spirit:enumeration>MIO 49</spirit:enumeration>
- <spirit:enumeration>MIO 50</spirit:enumeration>
- <spirit:enumeration>MIO 51</spirit:enumeration>
- <spirit:enumeration>MIO 52</spirit:enumeration>
- <spirit:enumeration>MIO 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_767f870c</spirit:name>
- <spirit:enumeration>External</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_78fdaebe</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>MIO 43</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_7abc2131</spirit:name>
- <spirit:enumeration>16 Bit</spirit:enumeration>
- <spirit:enumeration>32 Bit</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_7d098ed6</spirit:name>
- <spirit:enumeration>ARM PLL</spirit:enumeration>
- <spirit:enumeration>IO PLL</spirit:enumeration>
- <spirit:enumeration>DDR PLL</spirit:enumeration>
- <spirit:enumeration>External</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_7d6d1b3f</spirit:name>
- <spirit:enumeration>1</spirit:enumeration>
- <spirit:enumeration>2</spirit:enumeration>
- <spirit:enumeration>3</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_82c3921b</spirit:name>
- <spirit:enumeration>0xE0008FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_83072ce2</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>MIO 1</spirit:enumeration>
- <spirit:enumeration>MIO 3</spirit:enumeration>
- <spirit:enumeration>MIO 5</spirit:enumeration>
- <spirit:enumeration>MIO 7</spirit:enumeration>
- <spirit:enumeration>MIO 9</spirit:enumeration>
- <spirit:enumeration>MIO 11</spirit:enumeration>
- <spirit:enumeration>MIO 13</spirit:enumeration>
- <spirit:enumeration>MIO 15</spirit:enumeration>
- <spirit:enumeration>MIO 17</spirit:enumeration>
- <spirit:enumeration>MIO 19</spirit:enumeration>
- <spirit:enumeration>MIO 21</spirit:enumeration>
- <spirit:enumeration>MIO 23</spirit:enumeration>
- <spirit:enumeration>MIO 25</spirit:enumeration>
- <spirit:enumeration>MIO 27</spirit:enumeration>
- <spirit:enumeration>MIO 29</spirit:enumeration>
- <spirit:enumeration>MIO 31</spirit:enumeration>
- <spirit:enumeration>MIO 33</spirit:enumeration>
- <spirit:enumeration>MIO 35</spirit:enumeration>
- <spirit:enumeration>MIO 37</spirit:enumeration>
- <spirit:enumeration>MIO 39</spirit:enumeration>
- <spirit:enumeration>MIO 41</spirit:enumeration>
- <spirit:enumeration>MIO 43</spirit:enumeration>
- <spirit:enumeration>MIO 45</spirit:enumeration>
- <spirit:enumeration>MIO 47</spirit:enumeration>
- <spirit:enumeration>MIO 49</spirit:enumeration>
- <spirit:enumeration>MIO 51</spirit:enumeration>
- <spirit:enumeration>MIO 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_83842e96</spirit:name>
- <spirit:enumeration>0xE0009FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_8436647b</spirit:name>
- <spirit:enumeration>MIO 42</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_86458347</spirit:name>
- <spirit:enumeration>fast</spirit:enumeration>
- <spirit:enumeration>slow</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_86cc57ee</spirit:name>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 16 .. 27</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_88a617f1</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 12 .. 13</spirit:enumeration>
- <spirit:enumeration>MIO 16 .. 17</spirit:enumeration>
- <spirit:enumeration>MIO 20 .. 21</spirit:enumeration>
- <spirit:enumeration>MIO 24 .. 25</spirit:enumeration>
- <spirit:enumeration>MIO 28 .. 29</spirit:enumeration>
- <spirit:enumeration>MIO 32 .. 33</spirit:enumeration>
- <spirit:enumeration>MIO 36 .. 37</spirit:enumeration>
- <spirit:enumeration>MIO 40 .. 41</spirit:enumeration>
- <spirit:enumeration>MIO 44 .. 45</spirit:enumeration>
- <spirit:enumeration>MIO 48 .. 49</spirit:enumeration>
- <spirit:enumeration>MIO 52 .. 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_88fe7673</spirit:name>
- <spirit:enumeration>0xE0000FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_89b9cafe</spirit:name>
- <spirit:enumeration>0xE0001FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_8af5a703</spirit:name>
- <spirit:enumeration>0</spirit:enumeration>
- <spirit:enumeration>1</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_8ca738ca</spirit:name>
- <spirit:enumeration>0xE0005FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_8de08447</spirit:name>
- <spirit:enumeration>0xE0004FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_8e2841d0</spirit:name>
- <spirit:enumeration>0xE0007FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_8f11124f</spirit:name>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 16 .. 21</spirit:enumeration>
- <spirit:enumeration>MIO 28 .. 33</spirit:enumeration>
- <spirit:enumeration>MIO 40 .. 45</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_8f6ffd5d</spirit:name>
- <spirit:enumeration>0xE0006FFF</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_908f40dd</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 16 .. 19</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_92aefd84</spirit:name>
- <spirit:enumeration>0xE0104000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_935a3e6e</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 12 .. 13</spirit:enumeration>
- <spirit:enumeration>MIO 24 .. 25</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_93e94109</spirit:name>
- <spirit:enumeration>0xE0105000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_9478ca27</spirit:name>
- <spirit:enumeration>0xE0103000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_953f76aa</spirit:name>
- <spirit:enumeration>0xE0102000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_95a9da0c</spirit:name>
- <spirit:enumeration>in</spirit:enumeration>
- <spirit:enumeration>out</spirit:enumeration>
- <spirit:enumeration>inout</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_96d47805</spirit:name>
- <spirit:enumeration>32</spirit:enumeration>
- <spirit:enumeration>64</spirit:enumeration>
- <spirit:enumeration>128</spirit:enumeration>
- <spirit:enumeration>256</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_96f7b33d</spirit:name>
- <spirit:enumeration>0xE0101000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_97b00fb0</spirit:name>
- <spirit:enumeration>0xE0100000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_99ba8646</spirit:name>
- <spirit:enumeration>32</spirit:enumeration>
- <spirit:enumeration>64</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_9e358632</spirit:name>
- <spirit:enumeration>None</spirit:enumeration>
- <spirit:enumeration>Default</spirit:enumeration>
- <spirit:enumeration>ZC702</spirit:enumeration>
- <spirit:enumeration>ZC706</spirit:enumeration>
- <spirit:enumeration>ZedBoard</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_a0318123</spirit:name>
- <spirit:enumeration>54</spirit:enumeration>
- <spirit:enumeration>32</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_a0c775a9</spirit:name>
- <spirit:enumeration>clg484</spirit:enumeration>
- <spirit:enumeration>clg225</spirit:enumeration>
- <spirit:enumeration>clg400</spirit:enumeration>
- <spirit:enumeration>ffg676</spirit:enumeration>
- <spirit:enumeration>fbg676</spirit:enumeration>
- <spirit:enumeration>fbg484</spirit:enumeration>
- <spirit:enumeration>ffg900</spirit:enumeration>
- <spirit:enumeration>cl400</spirit:enumeration>
- <spirit:enumeration>cl484</spirit:enumeration>
- <spirit:enumeration>rf676</spirit:enumeration>
- <spirit:enumeration>fb484</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_a841b9a1</spirit:name>
- <spirit:enumeration>1000 Mbps</spirit:enumeration>
- <spirit:enumeration>100 Mbps</spirit:enumeration>
- <spirit:enumeration>10 Mbps</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_a8e6d6fb</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 14 .. 15</spirit:enumeration>
- <spirit:enumeration>MIO 26 .. 27</spirit:enumeration>
- <spirit:enumeration>MIO 38 .. 39</spirit:enumeration>
- <spirit:enumeration>MIO 50 .. 51</spirit:enumeration>
- <spirit:enumeration>MIO 52 .. 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_ae9f88f6</spirit:name>
- <spirit:enumeration>1</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_af9e7a8f</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 10 .. 11</spirit:enumeration>
- <spirit:enumeration>MIO 22 .. 23</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_b3ee7919</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 0</spirit:enumeration>
- <spirit:enumeration>MIO 1</spirit:enumeration>
- <spirit:enumeration>MIO 2</spirit:enumeration>
- <spirit:enumeration>MIO 3</spirit:enumeration>
- <spirit:enumeration>MIO 4</spirit:enumeration>
- <spirit:enumeration>MIO 5</spirit:enumeration>
- <spirit:enumeration>MIO 6</spirit:enumeration>
- <spirit:enumeration>MIO 7</spirit:enumeration>
- <spirit:enumeration>MIO 8</spirit:enumeration>
- <spirit:enumeration>MIO 9</spirit:enumeration>
- <spirit:enumeration>MIO 10</spirit:enumeration>
- <spirit:enumeration>MIO 11</spirit:enumeration>
- <spirit:enumeration>MIO 12</spirit:enumeration>
- <spirit:enumeration>MIO 13</spirit:enumeration>
- <spirit:enumeration>MIO 14</spirit:enumeration>
- <spirit:enumeration>MIO 15</spirit:enumeration>
- <spirit:enumeration>MIO 16</spirit:enumeration>
- <spirit:enumeration>MIO 17</spirit:enumeration>
- <spirit:enumeration>MIO 18</spirit:enumeration>
- <spirit:enumeration>MIO 19</spirit:enumeration>
- <spirit:enumeration>MIO 20</spirit:enumeration>
- <spirit:enumeration>MIO 21</spirit:enumeration>
- <spirit:enumeration>MIO 22</spirit:enumeration>
- <spirit:enumeration>MIO 23</spirit:enumeration>
- <spirit:enumeration>MIO 24</spirit:enumeration>
- <spirit:enumeration>MIO 25</spirit:enumeration>
- <spirit:enumeration>MIO 26</spirit:enumeration>
- <spirit:enumeration>MIO 27</spirit:enumeration>
- <spirit:enumeration>MIO 28</spirit:enumeration>
- <spirit:enumeration>MIO 29</spirit:enumeration>
- <spirit:enumeration>MIO 30</spirit:enumeration>
- <spirit:enumeration>MIO 31</spirit:enumeration>
- <spirit:enumeration>MIO 32</spirit:enumeration>
- <spirit:enumeration>MIO 33</spirit:enumeration>
- <spirit:enumeration>MIO 34</spirit:enumeration>
- <spirit:enumeration>MIO 35</spirit:enumeration>
- <spirit:enumeration>MIO 36</spirit:enumeration>
- <spirit:enumeration>MIO 37</spirit:enumeration>
- <spirit:enumeration>MIO 38</spirit:enumeration>
- <spirit:enumeration>MIO 39</spirit:enumeration>
- <spirit:enumeration>MIO 40</spirit:enumeration>
- <spirit:enumeration>MIO 41</spirit:enumeration>
- <spirit:enumeration>MIO 42</spirit:enumeration>
- <spirit:enumeration>MIO 43</spirit:enumeration>
- <spirit:enumeration>MIO 44</spirit:enumeration>
- <spirit:enumeration>MIO 45</spirit:enumeration>
- <spirit:enumeration>MIO 46</spirit:enumeration>
- <spirit:enumeration>MIO 47</spirit:enumeration>
- <spirit:enumeration>MIO 48</spirit:enumeration>
- <spirit:enumeration>MIO 49</spirit:enumeration>
- <spirit:enumeration>MIO 50</spirit:enumeration>
- <spirit:enumeration>MIO 51</spirit:enumeration>
- <spirit:enumeration>MIO 52</spirit:enumeration>
- <spirit:enumeration>MIO 53</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_b4a6147c</spirit:name>
- <spirit:enumeration>0xE000B000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_b5e1a8f1</spirit:name>
- <spirit:enumeration>0xE000C000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_b66926f4</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 28 .. 39</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_b76ed1eb</spirit:name>
- <spirit:enumeration>0xE000A000</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_ba65fe0e</spirit:name>
- <spirit:enumeration><Select></spirit:enumeration>
- <spirit:enumeration>EMIO</spirit:enumeration>
- <spirit:enumeration>MIO 2 .. 9</spirit:enumeration>
- </spirit:choice>
- <spirit:choice>
- <spirit:name>choice_list_bbba28a6</spirit:name>
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- <spirit:parameter>
- <spirit:name>PCW_CAN1_HIGHADDR</spirit:name>
- <spirit:displayName>PCW CAN1 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_HIGHADDR" spirit:choiceRef="choice_list_83842e96" spirit:order="51100" spirit:bitStringLength="32">0xE0009FFF</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_GPIO_BASEADDR</spirit:name>
- <spirit:displayName>PCW GPIO BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_BASEADDR" spirit:choiceRef="choice_list_b76ed1eb" spirit:order="51200" spirit:bitStringLength="32">0xE000A000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_GPIO_HIGHADDR</spirit:name>
- <spirit:displayName>PCW GPIO HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_HIGHADDR" spirit:choiceRef="choice_list_e4dab0ce" spirit:order="51300" spirit:bitStringLength="32">0xE000AFFF</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ENET0_BASEADDR</spirit:name>
- <spirit:displayName>PCW ENET0 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_BASEADDR" spirit:choiceRef="choice_list_b4a6147c" spirit:order="51400" spirit:bitStringLength="32">0xE000B000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ENET0_HIGHADDR</spirit:name>
- <spirit:displayName>PCW ENET0 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_HIGHADDR" spirit:choiceRef="choice_list_e7127559" spirit:order="51500" spirit:bitStringLength="32">0xE000BFFF</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ENET1_BASEADDR</spirit:name>
- <spirit:displayName>PCW ENET1 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_BASEADDR" spirit:choiceRef="choice_list_b5e1a8f1" spirit:order="51600" spirit:bitStringLength="32">0xE000C000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ENET1_HIGHADDR</spirit:name>
- <spirit:displayName>PCW ENET1 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_HIGHADDR" spirit:choiceRef="choice_list_e655c9d4" spirit:order="51700" spirit:bitStringLength="32">0xE000CFFF</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_ENET1_HIGHADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_ENET1)) = 1) ">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_SDIO0_BASEADDR</spirit:name>
- <spirit:displayName>PCW SDIO0 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SDIO0_BASEADDR" spirit:choiceRef="choice_list_97b00fb0" spirit:order="51800" spirit:bitStringLength="32">0xE0100000</spirit:value>
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- </xilinx:enablement>
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- <spirit:parameter>
- <spirit:name>PCW_SDIO0_HIGHADDR</spirit:name>
- <spirit:displayName>PCW SDIO0 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SDIO0_HIGHADDR" spirit:choiceRef="choice_list_c4046e95" spirit:order="51900" spirit:bitStringLength="32">0xE0100FFF</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_SDIO0_HIGHADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_SDIO0)) = 1) ">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_SDIO1_BASEADDR</spirit:name>
- <spirit:displayName>PCW SDIO1 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SDIO1_BASEADDR" spirit:choiceRef="choice_list_96f7b33d" spirit:order="52000" spirit:bitStringLength="32">0xE0101000</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_SDIO1_BASEADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_SDIO1)) = 1) ">true</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_SDIO1_HIGHADDR</spirit:name>
- <spirit:displayName>PCW SDIO1 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SDIO1_HIGHADDR" spirit:choiceRef="choice_list_c543d218" spirit:order="52100" spirit:bitStringLength="32">0xE0101FFF</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_SDIO1_HIGHADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_SDIO1)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
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- <spirit:parameter>
- <spirit:name>PCW_USB0_BASEADDR</spirit:name>
- <spirit:displayName>PCW USB0 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB0_BASEADDR" spirit:choiceRef="choice_list_953f76aa" spirit:order="52200" spirit:bitStringLength="32">0xE0102000</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_USB0_BASEADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_USB0)) = 1) ">true</xilinx:isEnabled>
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- <spirit:name>PCW_USB0_HIGHADDR</spirit:name>
- <spirit:displayName>PCW USB0 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB0_HIGHADDR" spirit:choiceRef="choice_list_3607bdd0" spirit:order="52300" spirit:bitStringLength="32">0xE0102fff</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_USB0_HIGHADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_USB0)) = 1) ">true</xilinx:isEnabled>
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- <spirit:name>PCW_USB1_BASEADDR</spirit:name>
- <spirit:displayName>PCW USB1 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB1_BASEADDR" spirit:choiceRef="choice_list_9478ca27" spirit:order="52400" spirit:bitStringLength="32">0xE0103000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_USB1_BASEADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_USB1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB1_HIGHADDR</spirit:name>
- <spirit:displayName>PCW USB1 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB1_HIGHADDR" spirit:choiceRef="choice_list_3740015d" spirit:order="52500" spirit:bitStringLength="32">0xE0103fff</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_USB1_HIGHADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_USB1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC0_BASEADDR</spirit:name>
- <spirit:displayName>PCW TTC0 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_BASEADDR" spirit:choiceRef="choice_list_92aefd84" spirit:order="52600" spirit:bitStringLength="32">0xE0104000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_TTC0_BASEADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_TTC0)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC0_HIGHADDR</spirit:name>
- <spirit:displayName>PCW TTC0 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_HIGHADDR" spirit:choiceRef="choice_list_319636fe" spirit:order="52700" spirit:bitStringLength="32">0xE0104fff</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_TTC0_HIGHADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_TTC0)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- <spirit:parameter>
- <spirit:name>PCW_TTC1_BASEADDR</spirit:name>
- <spirit:displayName>PCW TTC1 BASEADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC1_BASEADDR" spirit:choiceRef="choice_list_93e94109" spirit:order="52800" spirit:bitStringLength="32">0xE0105000</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_TTC1_BASEADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_TTC1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- <spirit:parameter>
- <spirit:name>PCW_TTC1_HIGHADDR</spirit:name>
- <spirit:displayName>PCW TTC1 HIGHADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC1_HIGHADDR" spirit:choiceRef="choice_list_30d18a73" spirit:order="52900" spirit:bitStringLength="32">0xE0105fff</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_TTC1_HIGHADDR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_TTC1)) = 1) ">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_FCLK_CLK0_BUF</spirit:name>
- <spirit:displayName>PCW FCLK CLK0 BUF</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK_CLK0_BUF" spirit:choiceRef="choice_list_d10f4555" spirit:order="63000">TRUE</spirit:value>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FCLK_CLK0_BUF" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK0_PORT)) == 1)) ">true</xilinx:isEnabled>
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- <spirit:name>PCW_FCLK_CLK1_BUF</spirit:name>
- <spirit:displayName>PCW FCLK CLK1 BUF</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK_CLK1_BUF" spirit:choiceRef="choice_list_d10f4555" spirit:order="63100">FALSE</spirit:value>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FCLK_CLK1_BUF" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK1_PORT)) == 1)) ">false</xilinx:isEnabled>
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- <spirit:name>PCW_FCLK_CLK2_BUF</spirit:name>
- <spirit:displayName>PCW FCLK CLK2 BUF</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK_CLK2_BUF" spirit:choiceRef="choice_list_d10f4555" spirit:order="63200">FALSE</spirit:value>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FCLK_CLK2_BUF" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK2_PORT)) == 1)) ">false</xilinx:isEnabled>
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- <spirit:name>PCW_FCLK_CLK3_BUF</spirit:name>
- <spirit:displayName>PCW FCLK CLK3 BUF</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK_CLK3_BUF" spirit:choiceRef="choice_list_d10f4555" spirit:order="63300">FALSE</spirit:value>
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- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FCLK_CLK3_BUF" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK3_PORT)) == 1)) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_FREQ_MHZ</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR FREQ MHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_FREQ_MHZ" spirit:order="13500" spirit:minimum="200.000000" spirit:maximum="534.000000">500</spirit:value>
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- <spirit:name>PCW_UIPARAM_DDR_BANK_ADDR_COUNT</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR BANK ADDR COUNT</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" spirit:order="14100" spirit:minimum="2.000000" spirit:maximum="3.000000">3</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_BANK_ADDR_COUNT">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_ROW_ADDR_COUNT</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR ROW ADDR COUNT</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" spirit:order="14200" spirit:minimum="12.000000" spirit:maximum="15.000000">14</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_ROW_ADDR_COUNT">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_COL_ADDR_COUNT</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR COL ADDR COUNT</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_COL_ADDR_COUNT" spirit:order="14300" spirit:minimum="8.000000" spirit:maximum="13.000000">10</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_COL_ADDR_COUNT">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CL</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CL</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CL" spirit:order="14400">7</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_CL">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CWL</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CWL</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CWL" spirit:order="14500">6</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_CWL">false</xilinx:isEnabled>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_T_RCD</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR T RCD</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_T_RCD" spirit:order="14600" spirit:minimum="0.000000" spirit:maximum="16.000000">7</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_T_RCD">false</xilinx:isEnabled>
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- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_T_RP</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR T RP</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_T_RP" spirit:order="14700" spirit:minimum="0.000000" spirit:maximum="16.000000">7</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_T_RP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_T_RC</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR T RC</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_T_RC" spirit:order="14800" spirit:minimum="0.000000" spirit:maximum="100.000000">48.75</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_T_RC">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_T_RAS_MIN</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR T RAS MIN</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_T_RAS_MIN" spirit:order="14900" spirit:minimum="0.000000" spirit:maximum="100.000000">35.0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_T_RAS_MIN">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_T_FAW</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR T FAW</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_T_FAW" spirit:order="15000" spirit:minimum="0.000000" spirit:maximum="100.000000">40.0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_T_FAW">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_AL</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR AL</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_AL" spirit:order="15100" spirit:minimum="0.000000" spirit:maximum="20.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS TO CLK DELAY 0</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" spirit:order="15200" spirit:minimum="-0.100000" spirit:maximum="100.000000">0.0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS TO CLK DELAY 1</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" spirit:order="15300" spirit:minimum="-0.100000" spirit:maximum="100.000000">0.0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS TO CLK DELAY 2</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" spirit:order="15400" spirit:minimum="-0.100000" spirit:maximum="100.000000">0.0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS TO CLK DELAY 3</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" spirit:order="15500" spirit:minimum="-0.100000" spirit:maximum="100.000000">0.0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_BOARD_DELAY0</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR BOARD DELAY0</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY0" spirit:order="16100" spirit:minimum="0.007000" spirit:maximum="100.000000">0.25</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_BOARD_DELAY1</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR BOARD DELAY1</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY1" spirit:order="16200" spirit:minimum="0.007000" spirit:maximum="100.000000">0.25</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_BOARD_DELAY2</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR BOARD DELAY2</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY2" spirit:order="16300" spirit:minimum="0.007000" spirit:maximum="100.000000">0.25</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_BOARD_DELAY3</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR BOARD DELAY3</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY3" spirit:order="16400" spirit:minimum="0.007000" spirit:maximum="100.000000">0.25</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_0_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 0 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" spirit:order="16500" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_1_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 1 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" spirit:order="16600" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_2_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 2 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" spirit:order="16700" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_3_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 3 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" spirit:order="16800" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_0_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 0 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" spirit:order="16900" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_1_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 1 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" spirit:order="17000" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_2_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 2 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" spirit:order="17100" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_3_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 3 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" spirit:order="17200" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 0 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" spirit:order="17300" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 1 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" spirit:order="17400" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 2 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" spirit:order="17500" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 3 LENGTH MM</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" spirit:order="17600" spirit:minimum="0.000000" spirit:maximum="10000.000000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 0 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" spirit:order="17700" spirit:minimum="0.000000" spirit:maximum="10000.000000">76.687</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 1 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" spirit:order="17800" spirit:minimum="0.000000" spirit:maximum="10000.000000">77.8025</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 2 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" spirit:order="17900" spirit:minimum="0.000000" spirit:maximum="10000.000000">72.8405</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 3 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" spirit:order="18000" spirit:minimum="0.000000" spirit:maximum="10000.000000">111.904</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 0 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" spirit:order="18100" spirit:minimum="0.000000" spirit:maximum="10000.000000">73.119</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 1 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" spirit:order="18200" spirit:minimum="0.000000" spirit:maximum="10000.000000">63.8935</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 2 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" spirit:order="18300" spirit:minimum="0.000000" spirit:maximum="10000.000000">77.045</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 3 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" spirit:order="18400" spirit:minimum="0.000000" spirit:maximum="10000.000000">111.903</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 0 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" spirit:order="18500" spirit:minimum="0.000000" spirit:maximum="10000.000000">76.428</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 1 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" spirit:order="18600" spirit:minimum="0.000000" spirit:maximum="10000.000000">76.428</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 2 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" spirit:order="18700" spirit:minimum="0.000000" spirit:maximum="10000.000000">76.428</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 3 PACKAGE LENGTH</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" spirit:order="18800" spirit:minimum="0.000000" spirit:maximum="10000.000000">76.428</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 0 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" spirit:order="18900" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 1 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" spirit:order="19000" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 2 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" spirit:order="19100" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQS 3 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" spirit:order="19200" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 0 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" spirit:order="19300" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 1 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" spirit:order="19400" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 2 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" spirit:order="19500" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DQ 3 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" spirit:order="19600" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 0 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" spirit:order="19700" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 1 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" spirit:order="19800" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 2 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" spirit:order="19900" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK 3 PROPOGATION DELAY</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" spirit:order="20000" spirit:minimum="0.000000" spirit:maximum="10000.000000">160</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0</spirit:name>
- <spirit:displayName>PCW PACKAGE DDR DQS TO CLK DELAY 0</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" spirit:order="20100" spirit:minimum="-0.100000" spirit:maximum="100.000000">-0.000</spirit:value>
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- <spirit:parameter>
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- <spirit:name>PCW_QSPI_PERIPHERAL_FREQMHZ</spirit:name>
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- <spirit:name>PCW_SMC_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW SMC PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:parameter>
- <spirit:name>PCW_USB0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW USB0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB0_PERIPHERAL_FREQMHZ" spirit:order="24100" spirit:minimum="5.000000" spirit:maximum="60.000000">60</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_SDIO_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW SDIO PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SDIO_PERIPHERAL_FREQMHZ" spirit:order="24300" spirit:minimum="10.000000" spirit:maximum="125.000000">100</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_UART_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW UART PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART_PERIPHERAL_FREQMHZ" spirit:order="24400" spirit:minimum="10.000000" spirit:maximum="100.000000">100</spirit:value>
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- <spirit:name>PCW_SPI_PERIPHERAL_FREQMHZ</spirit:name>
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- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI_PERIPHERAL_FREQMHZ" spirit:order="24500" spirit:minimum="0.000000" spirit:maximum="200.000000">166.666666</spirit:value>
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- <spirit:name>PCW_CAN_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW CAN PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN_PERIPHERAL_FREQMHZ" spirit:order="24600" spirit:minimum="0.100000" spirit:maximum="100.000000">100</spirit:value>
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- <spirit:name>PCW_CAN0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW CAN0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN0_PERIPHERAL_FREQMHZ" spirit:order="24700" spirit:minimum="-2" spirit:maximum="-1">-1</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN0_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- <spirit:name>PCW_CAN1_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW CAN1 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_PERIPHERAL_FREQMHZ" spirit:order="24800" spirit:minimum="-2" spirit:maximum="-1">-1</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN1_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_I2C_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW I2C PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C_PERIPHERAL_FREQMHZ" spirit:order="24900" spirit:minimum="0.100000" spirit:maximum="200.000000">125.000000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_WDT_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW WDT PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_WDT_PERIPHERAL_FREQMHZ" spirit:order="25000" spirit:minimum="0.100000" spirit:maximum="200.000000">133.333333</spirit:value>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_WDT_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>PCW_TTC_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW TTC PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC_PERIPHERAL_FREQMHZ" spirit:order="25100" spirit:minimum="0.100000" spirit:maximum="100.000000">50</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TTC_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- <spirit:name>PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW TTC0 CLK0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" spirit:order="25200" spirit:minimum="0.100000" spirit:maximum="200.000000">133.333333</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- <spirit:name>PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW TTC0 CLK1 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW TTC0 CLK2 PERIPHERAL FREQMHZ</spirit:displayName>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- <spirit:name>PCW_TPIU_PERIPHERAL_FREQMHZ</spirit:name>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TPIU_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_FPGA0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW FPGA0 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_FPGA3_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW FPGA3 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:displayName>PCW ACT APU PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_UIPARAM_ACT_DDR_FREQ_MHZ</spirit:name>
- <spirit:displayName>PCW UIPARAM ACT DDR FREQ MHZ</spirit:displayName>
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- <spirit:name>PCW_ACT_ENET0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT ENET0 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_ACT_ENET1_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT ENET1 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_ACT_USB0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT USB0 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:displayName>PCW ACT USB1 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_ACT_SDIO_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT SDIO PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ" spirit:order="27300" spirit:minimum="10.000000" spirit:maximum="125.000000">97.222221</spirit:value>
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- <spirit:displayName>PCW ACT UART PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:displayName>PCW ACT SPI PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_SPI_PERIPHERAL_FREQMHZ" spirit:order="27500" spirit:minimum="0.000000" spirit:maximum="200.000000">159.090912</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_CAN_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT CAN PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_CAN_PERIPHERAL_FREQMHZ" spirit:order="27600" spirit:minimum="0.100000" spirit:maximum="100.000000">97.222221</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_CAN0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT CAN0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ" spirit:order="27600" spirit:minimum="0.1" spirit:maximum="100">23.8095</spirit:value>
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- <spirit:name>PCW_ACT_CAN1_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT CAN0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ" spirit:order="27600" spirit:minimum="0.1" spirit:maximum="100">23.8095</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_I2C_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT I2C PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_I2C_PERIPHERAL_FREQMHZ" spirit:order="27700" spirit:minimum="0.1" spirit:maximum="100">50</spirit:value>
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- <spirit:name>PCW_ACT_WDT_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT WDT PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_WDT_PERIPHERAL_FREQMHZ" spirit:order="27800" spirit:minimum="0.100000" spirit:maximum="200.000000">125.000000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_TTC_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT TTC PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_TTC_PERIPHERAL_FREQMHZ" spirit:order="27900" spirit:minimum="0.100000" spirit:maximum="100.000000">50</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_PCAP_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT PCAP PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ" spirit:order="28000" spirit:minimum="10.000000" spirit:maximum="200.000000">194.444443</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_TPIU_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT TPIU PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ" spirit:order="28100" spirit:minimum="10.000000" spirit:maximum="300.000000">200.000000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT FPGA0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ" spirit:order="28200" spirit:minimum="0.100000" spirit:maximum="250.000000">125.000000</spirit:value>
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- <spirit:name>PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT FPGA1 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT FPGA2 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT FPGA3 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ" spirit:order="28500" spirit:minimum="0.100000" spirit:maximum="250.000000">10.000000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ" spirit:order="28600" spirit:minimum="0.100000" spirit:maximum="200.000000">125.000000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ" spirit:order="28700" spirit:minimum="0.100000" spirit:maximum="200.000000">125.000000</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ" spirit:order="28800" spirit:minimum="0.100000" spirit:maximum="200.000000">125.000000</spirit:value>
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- <spirit:name>PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ</spirit:displayName>
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- <spirit:name>PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ</spirit:name>
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- <spirit:name>PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ</spirit:name>
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- <spirit:name>PCW_CLK0_FREQ</spirit:name>
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- <spirit:name>PCW_CLK1_FREQ</spirit:name>
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- <spirit:name>PCW_CLK2_FREQ</spirit:name>
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- <spirit:name>PCW_CLK3_FREQ</spirit:name>
- <spirit:displayName>PCW CLK3 FREQ</spirit:displayName>
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- <spirit:name>PCW_OVERRIDE_BASIC_CLOCK</spirit:name>
- <spirit:displayName>PCW OVERRIDE FREQ</spirit:displayName>
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- <spirit:name>PCW_CPU_PERIPHERAL_DIVISOR0</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CPU_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_DDR_PERIPHERAL_DIVISOR0</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PERIPHERAL_DIVISOR0" spirit:order="62900">2</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_SMC_PERIPHERAL_DIVISOR0</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_PERIPHERAL_DIVISOR0" spirit:order="62900">1</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SMC_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_QSPI_PERIPHERAL_DIVISOR0</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_PERIPHERAL_DIVISOR0" spirit:order="62900">13</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_QSPI_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_SDIO_PERIPHERAL_DIVISOR0</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SDIO_PERIPHERAL_DIVISOR0" spirit:order="62900">18</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SDIO_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UART_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_SPI_PERIPHERAL_DIVISOR0</spirit:name>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:name>PCW_CAN_PERIPHERAL_DIVISOR0</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR0" spirit:order="62900">18</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_CAN_PERIPHERAL_DIVISOR1</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR1" spirit:order="62900">1</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN_PERIPHERAL_DIVISOR1">false</xilinx:isEnabled>
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- <spirit:name>PCW_FCLK0_PERIPHERAL_DIVISOR0</spirit:name>
- <spirit:displayName>CLKPARAM</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_DIVISOR0" spirit:order="62900">7</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_FCLK0_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_FCLK1_PERIPHERAL_DIVISOR0</spirit:name>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_FCLK1_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_FCLK2_PERIPHERAL_DIVISOR0">false</xilinx:isEnabled>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_FCLK3_PERIPHERAL_DIVISOR1">false</xilinx:isEnabled>
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- <spirit:displayName>CLKPARAM</spirit:displayName>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DCI_PERIPHERAL_DIVISOR1">false</xilinx:isEnabled>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_WDT_PERIPHERAL_DIVISOR0" spirit:order="62900">1</spirit:value>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ARMPLL_CTRL_FBDIV" spirit:order="62900">30</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ARMPLL_CTRL_FBDIV">false</xilinx:isEnabled>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_IOPLL_CTRL_FBDIV" spirit:order="62900">35</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_IOPLL_CTRL_FBDIV">false</xilinx:isEnabled>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDRPLL_CTRL_FBDIV">false</xilinx:isEnabled>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CPU_CPU_PLL_FREQMHZ" spirit:order="62900">1500.000</spirit:value>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CPU_CPU_PLL_FREQMHZ">false</xilinx:isEnabled>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_IO_IO_PLL_FREQMHZ">false</xilinx:isEnabled>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_DDR_PLL_FREQMHZ">false</xilinx:isEnabled>
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- <spirit:name>PCW_SMC_PERIPHERAL_VALID</spirit:name>
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- <spirit:name>PCW_SDIO_PERIPHERAL_VALID</spirit:name>
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- <spirit:name>PCW_SPI_PERIPHERAL_VALID</spirit:name>
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- <spirit:name>PCW_CAN_PERIPHERAL_VALID</spirit:name>
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- <spirit:name>PCW_UART_PERIPHERAL_VALID</spirit:name>
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- <spirit:name>PCW_EN_EMIO_CAN0</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_CAN0" spirit:choiceRef="choice_list_8af5a703" spirit:order="10500">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_CAN1</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_CAN1" spirit:choiceRef="choice_list_8af5a703" spirit:order="10600">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_ENET0</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_ENET0" spirit:choiceRef="choice_list_8af5a703" spirit:order="10700">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_ENET1</spirit:name>
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- <spirit:name>PCW_EN_PTP_ENET0</spirit:name>
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- <spirit:name>PCW_EN_PTP_ENET1</spirit:name>
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- <spirit:name>PCW_EN_EMIO_GPIO</spirit:name>
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- <spirit:name>PCW_EN_EMIO_I2C0</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_I2C0" spirit:choiceRef="choice_list_8af5a703" spirit:order="11000">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_I2C1</spirit:name>
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- <spirit:name>PCW_EN_EMIO_PJTAG</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_PJTAG" spirit:choiceRef="choice_list_8af5a703" spirit:order="11200">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_SDIO0</spirit:name>
- <spirit:displayName>PCW EN EMIO SDIO0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_SDIO0" spirit:choiceRef="choice_list_8af5a703" spirit:order="11300">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_CD_SDIO0</spirit:name>
- <spirit:displayName>PCW EN EMIO CD SDIO0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO0" spirit:choiceRef="choice_list_8af5a703" spirit:order="11400">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_WP_SDIO0</spirit:name>
- <spirit:displayName>PCW EN EMIO WP SDIO0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO0" spirit:choiceRef="choice_list_8af5a703" spirit:order="11500">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_SDIO1</spirit:name>
- <spirit:displayName>PCW EN EMIO SDIO1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_SDIO1" spirit:choiceRef="choice_list_8af5a703" spirit:order="11600">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_CD_SDIO1</spirit:name>
- <spirit:displayName>PCW EN EMIO CD SDIO1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO1" spirit:choiceRef="choice_list_8af5a703" spirit:order="11700">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_WP_SDIO1</spirit:name>
- <spirit:displayName>PCW EN EMIO WP SDIO1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO1" spirit:choiceRef="choice_list_8af5a703" spirit:order="11800">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_SPI0</spirit:name>
- <spirit:displayName>PCW EN EMIO SPI0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_SPI0" spirit:choiceRef="choice_list_8af5a703" spirit:order="11900">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_SPI1</spirit:name>
- <spirit:displayName>PCW EN EMIO SPI1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_SPI1" spirit:choiceRef="choice_list_8af5a703" spirit:order="12000">1</spirit:value>
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- <spirit:name>PCW_EN_EMIO_UART0</spirit:name>
- <spirit:displayName>PCW EN EMIO UART0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_UART0" spirit:choiceRef="choice_list_8af5a703" spirit:order="12100">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_UART1</spirit:name>
- <spirit:displayName>PCW EN EMIO UART1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_UART1" spirit:choiceRef="choice_list_8af5a703" spirit:order="12200">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_MODEM_UART0</spirit:name>
- <spirit:displayName>PCW EN EMIO MODEM UART0</spirit:displayName>
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- <spirit:name>PCW_EN_EMIO_MODEM_UART1</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_MODEM_UART1" spirit:choiceRef="choice_list_8af5a703" spirit:order="12400">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_TTC0</spirit:name>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_TTC0" spirit:choiceRef="choice_list_8af5a703" spirit:order="12500">0</spirit:value>
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- <spirit:name>PCW_EN_EMIO_TTC1</spirit:name>
- <spirit:displayName>PCW EN EMIO TTC1</spirit:displayName>
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- <spirit:name>PCW_EN_EMIO_WDT</spirit:name>
- <spirit:displayName>PCW EN EMIO WDT</spirit:displayName>
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- <spirit:name>PCW_EN_EMIO_TRACE</spirit:name>
- <spirit:displayName>PCW EN EMIO TRACE</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_TRACE" spirit:choiceRef="choice_list_8af5a703" spirit:order="12800">0</spirit:value>
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- <spirit:name>PCW_USE_AXI_NONSECURE</spirit:name>
- <spirit:displayName>PCW USE AXI NON SECURE</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_AXI_NONSECURE" spirit:choiceRef="choice_list_6727dfa6" spirit:order="45600">0</spirit:value>
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- <spirit:name>PCW_USE_M_AXI_GP0</spirit:name>
- <spirit:displayName>PCW USE M AXI GP0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_M_AXI_GP0" spirit:choiceRef="choice_list_8af5a703" spirit:order="45600">1</spirit:value>
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- <spirit:name>PCW_USE_M_AXI_GP1</spirit:name>
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- <spirit:name>PCW_USE_S_AXI_GP0</spirit:name>
- <spirit:displayName>PCW USE S AXI GP0</spirit:displayName>
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- <spirit:name>PCW_USE_S_AXI_GP1</spirit:name>
- <spirit:displayName>PCW USE S AXI GP1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_S_AXI_GP1" spirit:choiceRef="choice_list_8af5a703" spirit:order="45900">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_S_AXI_ACP</spirit:name>
- <spirit:displayName>PCW USE S AXI ACP</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_S_AXI_ACP" spirit:choiceRef="choice_list_8af5a703" spirit:order="46000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_S_AXI_HP0</spirit:name>
- <spirit:displayName>PCW USE S AXI HP0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_S_AXI_HP0" spirit:choiceRef="choice_list_8af5a703" spirit:order="46100">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_S_AXI_HP1</spirit:name>
- <spirit:displayName>PCW USE S AXI HP1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_S_AXI_HP1" spirit:choiceRef="choice_list_8af5a703" spirit:order="46200">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_S_AXI_HP2</spirit:name>
- <spirit:displayName>PCW USE S AXI HP2</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_S_AXI_HP2" spirit:choiceRef="choice_list_8af5a703" spirit:order="46300">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_S_AXI_HP3</spirit:name>
- <spirit:displayName>PCW USE S AXI HP3</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_S_AXI_HP3" spirit:choiceRef="choice_list_8af5a703" spirit:order="46400">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP0_FREQMHZ</spirit:name>
- <spirit:displayName>PCW M AXI GP0 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP0_FREQMHZ" spirit:order="45601">125</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP0_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP0)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP1_FREQMHZ</spirit:name>
- <spirit:displayName>PCW M AXI GP1 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP1_FREQMHZ" spirit:order="45701">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP1_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_GP0_FREQMHZ</spirit:name>
- <spirit:displayName>PCW S AXI GP0 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_GP0_FREQMHZ" spirit:order="45801">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_GP0_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_GP0)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_GP1_FREQMHZ</spirit:name>
- <spirit:displayName>PCW S AXI GP1 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_GP1_FREQMHZ" spirit:order="45901">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_GP1_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_GP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_ACP_FREQMHZ</spirit:name>
- <spirit:displayName>PCW S AXI ACP FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ" spirit:order="46001">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_ACP_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_ACP)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP0_FREQMHZ</spirit:name>
- <spirit:displayName>PCW S AXI HP0 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP0_FREQMHZ" spirit:order="46101">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP0_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP0)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP1_FREQMHZ</spirit:name>
- <spirit:displayName>PCW S AXI HP1 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP1_FREQMHZ" spirit:order="46201">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP1_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP2_FREQMHZ</spirit:name>
- <spirit:displayName>PCW S AXI HP2 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP2_FREQMHZ" spirit:order="46301">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP2_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP2)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP3_FREQMHZ</spirit:name>
- <spirit:displayName>PCW S AXI HP3 FREQMHZ</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP3_FREQMHZ" spirit:order="46401">10</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP3_FREQMHZ" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP3)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_DMA0</spirit:name>
- <spirit:displayName>PCW USE DMA0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_DMA0" spirit:choiceRef="choice_list_8af5a703" spirit:order="47200">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_DMA1</spirit:name>
- <spirit:displayName>PCW USE DMA1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_DMA1" spirit:choiceRef="choice_list_8af5a703" spirit:order="47300">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_DMA2</spirit:name>
- <spirit:displayName>PCW USE DMA2</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_DMA2" spirit:choiceRef="choice_list_8af5a703" spirit:order="47400">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_DMA3</spirit:name>
- <spirit:displayName>PCW USE DMA3</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_DMA3" spirit:choiceRef="choice_list_8af5a703" spirit:order="47500">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_TRACE</spirit:name>
- <spirit:displayName>PCW USE TRACE</spirit:displayName>
- <spirit:description>Enable FTM Trace interface used to capture data from PL to PS debug system</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_TRACE" spirit:choiceRef="choice_list_8af5a703" spirit:order="47600">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_PIPELINE_WIDTH</spirit:name>
- <spirit:displayName>PCW TRACE PIPELINE WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_PIPELINE_WIDTH" spirit:choiceRef="choice_list_070fff2f" spirit:order="47601">8</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_PIPELINE_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_TRACE)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_INCLUDE_TRACE_BUFFER</spirit:name>
- <spirit:displayName>PCW INCLUDE TRACE BUFFER</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_INCLUDE_TRACE_BUFFER" spirit:choiceRef="choice_list_8af5a703" spirit:order="47700">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_INCLUDE_TRACE_BUFFER" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_TRACE)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_BUFFER_FIFO_SIZE</spirit:name>
- <spirit:displayName>PCW TRACE BUFFER FIFO SIZE</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_BUFFER_FIFO_SIZE" spirit:choiceRef="choice_list_96d47805" spirit:order="47800">128</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_BUFFER_FIFO_SIZE" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_TRACE)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_TRACE_DATA_EDGE_DETECTOR</spirit:name>
- <spirit:displayName>PCW USE TRACE DATA EDGE DETECTOR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_TRACE_DATA_EDGE_DETECTOR" spirit:choiceRef="choice_list_8af5a703" spirit:order="47900">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_USE_TRACE_DATA_EDGE_DETECTOR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_TRACE)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_BUFFER_CLOCK_DELAY</spirit:name>
- <spirit:displayName>PCW TRACE BUFFER CLOCK DELAY</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_BUFFER_CLOCK_DELAY" spirit:choiceRef="choice_list_27376075" spirit:order="48000">12</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_BUFFER_CLOCK_DELAY" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_TRACE)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_CROSS_TRIGGER</spirit:name>
- <spirit:displayName>PCW USE CROSS TRIGGER</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_CROSS_TRIGGER" spirit:choiceRef="choice_list_8af5a703" spirit:order="48100">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_IN0</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_IN0" spirit:choiceRef="choice_list_13f07802" spirit:order="48102">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_IN0" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_IN1</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_IN1" spirit:choiceRef="choice_list_13f07802" spirit:order="48103">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_IN1" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_IN2</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_IN2" spirit:choiceRef="choice_list_13f07802" spirit:order="48104">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_IN2" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_IN3</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_IN3" spirit:choiceRef="choice_list_13f07802" spirit:order="48105">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_IN3" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_OUT0</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_OUT0" spirit:choiceRef="choice_list_13f07802" spirit:order="48106">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_OUT0" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_OUT1</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_OUT1" spirit:choiceRef="choice_list_13f07802" spirit:order="48107">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_OUT1" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_OUT2</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_OUT2" spirit:choiceRef="choice_list_13f07802" spirit:order="48108">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_OUT2" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FTM_CTI_OUT3</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FTM_CTI_OUT3" spirit:choiceRef="choice_list_13f07802" spirit:order="48109">DISABLED</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FTM_CTI_OUT3" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_DEBUG</spirit:name>
- <spirit:displayName>PCW USE DEBUG</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_DEBUG" spirit:choiceRef="choice_list_8af5a703" spirit:order="48101">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_CR_FABRIC</spirit:name>
- <spirit:displayName>PCW USE CR FABRIC</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_CR_FABRIC" spirit:choiceRef="choice_list_8af5a703" spirit:order="48200">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_AXI_FABRIC_IDLE</spirit:name>
- <spirit:displayName>PCW USE AXI FABRIC IDLE</spirit:displayName>
- <spirit:description>Enables idle AXI signal to the PS used to indicate that there are no outstanding AXI transactions in the PL</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_AXI_FABRIC_IDLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="48300">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_DDR_BYPASS</spirit:name>
- <spirit:displayName>PCW USE DDR BYPASS</spirit:displayName>
- <spirit:description>Enables DDR urgent/arb signal used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_DDR_BYPASS" spirit:choiceRef="choice_list_8af5a703" spirit:order="48400">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_FABRIC_INTERRUPT</spirit:name>
- <spirit:displayName>PCW USE FABRIC INTERRUPT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT" spirit:choiceRef="choice_list_8af5a703" spirit:order="48500">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_PROC_EVENT_BUS</spirit:name>
- <spirit:displayName>PCW USE PROC EVENT BUS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_PROC_EVENT_BUS" spirit:choiceRef="choice_list_8af5a703" spirit:order="48600">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_EXPANDED_IOP</spirit:name>
- <spirit:displayName>PCW USE EXPANDED IOP</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_EXPANDED_IOP" spirit:choiceRef="choice_list_8af5a703" spirit:order="48650">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_HIGH_OCM</spirit:name>
- <spirit:displayName>PCW USE HIGH OCM</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_HIGH_OCM" spirit:choiceRef="choice_list_8af5a703" spirit:order="48651">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_PS_SLCR_REGISTERS</spirit:name>
- <spirit:displayName>PCW USE PS SLCR REGISTERS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS" spirit:choiceRef="choice_list_8af5a703" spirit:order="48652">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_EXPANDED_PS_SLCR_REGISTERS</spirit:name>
- <spirit:displayName>PCW USE EXPANDED PS SLCR REGISTERS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_EXPANDED_PS_SLCR_REGISTERS" spirit:choiceRef="choice_list_8af5a703" spirit:order="48653">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_USE_EXPANDED_PS_SLCR_REGISTERS" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_CORESIGHT</spirit:name>
- <spirit:displayName>PCW USE CORESIGHT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_CORESIGHT" spirit:choiceRef="choice_list_8af5a703" spirit:order="48654">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_EMIO_SRAM_INT</spirit:name>
- <spirit:displayName>PCW EN EMIO SRAM INT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_EMIO_SRAM_INT" spirit:choiceRef="choice_list_8af5a703" spirit:order="48700">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GPIO_EMIO_GPIO_WIDTH</spirit:name>
- <spirit:displayName>PCW EMIO GPIO WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_WIDTH" spirit:order="48800" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">64</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_GPIO_EMIO_GPIO_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_EMIO_GPIO)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GP0_NUM_WRITE_THREADS</spirit:name>
- <spirit:displayName>GP0 NUM WRITE THREADS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GP0_NUM_WRITE_THREADS" spirit:order="48810" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GP0_NUM_READ_THREADS</spirit:name>
- <spirit:displayName>GP0 NUM READ THREADS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GP0_NUM_READ_THREADS" spirit:order="48820" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GP1_NUM_WRITE_THREADS</spirit:name>
- <spirit:displayName>GP1 NUM WRITE THREADS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GP1_NUM_WRITE_THREADS" spirit:order="48830" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GP1_NUM_READ_THREADS</spirit:name>
- <spirit:displayName>GP1 NUM READ THREADS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GP1_NUM_READ_THREADS" spirit:order="48840" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART0_BAUD_RATE</spirit:name>
- <spirit:displayName>PCW UART0 BAUD RATE</spirit:displayName>
- <spirit:description>Configure baud rate to determine UART0 operating frequency</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART0_BAUD_RATE" spirit:choiceRef="choice_list_f585525a" spirit:order="49299">115200</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_UART0_BAUD_RATE" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_UART0)) = 1)">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART1_BAUD_RATE</spirit:name>
- <spirit:displayName>PCW UART1 BAUD RATE</spirit:displayName>
- <spirit:description>Configure baud rate to determine UART1 operating frequency</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART1_BAUD_RATE" spirit:choiceRef="choice_list_f585525a" spirit:order="49297">115200</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_UART1_BAUD_RATE" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_EN_UART1)) = 1)">true</xilinx:isEnabled>
- </xilinx:enablement>
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- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_4K_TIMER</spirit:name>
- <spirit:displayName>PCW EN 4K TIMER</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_4K_TIMER" spirit:choiceRef="choice_list_8af5a703" spirit:order="49298">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP0_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW M AXI GP0 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP0_ID_WIDTH" spirit:choiceRef="choice_list_27376075" spirit:order="53100">12</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP0_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP0)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP0_ENABLE_STATIC_REMAP</spirit:name>
- <spirit:displayName>PCW M AXI GP0 ENABLE STATIC REMAP</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" spirit:choiceRef="choice_list_8af5a703" spirit:order="53400">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP0)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP0_SUPPORT_NARROW_BURST</spirit:name>
- <spirit:displayName>PCW M AXI GP0 SUPPORT NARROW BURST</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703" spirit:order="53500">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP0)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP0_THREAD_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW M AXI GP0 THREAD ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP0_THREAD_ID_WIDTH" spirit:choiceRef="choice_list_f5e7200e" spirit:order="62200">12</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP0_THREAD_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP0)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP1_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW M AXI GP1 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP1_ID_WIDTH" spirit:choiceRef="choice_list_27376075" spirit:order="54000">12</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP1_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP1_ENABLE_STATIC_REMAP</spirit:name>
- <spirit:displayName>PCW M AXI GP1 ENABLE STATIC REMAP</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" spirit:choiceRef="choice_list_8af5a703" spirit:order="54300">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP1_SUPPORT_NARROW_BURST</spirit:name>
- <spirit:displayName>PCW M AXI GP1 SUPPORT NARROW BURST</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" spirit:choiceRef="choice_list_8af5a703" spirit:order="54400">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_M_AXI_GP1_THREAD_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW M AXI GP1 THREAD ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_M_AXI_GP1_THREAD_ID_WIDTH" spirit:choiceRef="choice_list_f5e7200e" spirit:order="62400">12</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_M_AXI_GP1_THREAD_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_M_AXI_GP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_GP0_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI GP0 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_GP0_ID_WIDTH" spirit:choiceRef="choice_list_35b40bd0" spirit:order="54900">6</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_GP0_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_GP0)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_GP1_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI GP1 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_GP1_ID_WIDTH" spirit:choiceRef="choice_list_35b40bd0" spirit:order="55500">6</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_GP1_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_GP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_ACP_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI ACP ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_ACP_ID_WIDTH" spirit:order="56100" spirit:minimum="1" spirit:maximum="3" spirit:rangeType="long">3</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_ACP_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_ACP)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_INCLUDE_ACP_TRANS_CHECK</spirit:name>
- <spirit:displayName>PCW INCLUDE ACP TRANS CHECK</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_INCLUDE_ACP_TRANS_CHECK" spirit:choiceRef="choice_list_8af5a703" spirit:order="48900">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USE_DEFAULT_ACP_USER_VAL</spirit:name>
- <spirit:displayName>PCW USE DEFAULT ACP USER VAL</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USE_DEFAULT_ACP_USER_VAL" spirit:choiceRef="choice_list_8af5a703" spirit:order="49000">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_USE_DEFAULT_ACP_USER_VAL" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_ACP)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_ACP_ARUSER_VAL</spirit:name>
- <spirit:displayName>PCW S AXI ACP ARUSER VAL</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_ACP_ARUSER_VAL" spirit:order="49100" spirit:minimum="0" spirit:maximum="31" spirit:rangeType="long">31</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_ACP_ARUSER_VAL" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_ACP)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_DEFAULT_ACP_USER_VAL)) = 1)) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_ACP_AWUSER_VAL</spirit:name>
- <spirit:displayName>PCW S AXI ACP AWUSER VAL</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_ACP_AWUSER_VAL" spirit:order="49200" spirit:minimum="0" spirit:maximum="31" spirit:rangeType="long">31</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_ACP_AWUSER_VAL" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_ACP)) = 1) &&(spirit:decode(id(PARAM_VALUE.PCW_USE_DEFAULT_ACP_USER_VAL)) = 1)) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP0_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP0 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP0_ID_WIDTH" spirit:choiceRef="choice_list_35b40bd0" spirit:order="57000">6</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP0_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP0)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP0_DATA_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP0 DATA WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP0_DATA_WIDTH" spirit:choiceRef="choice_list_99ba8646" spirit:order="57200">64</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP0_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP0)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP1_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP1 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP1_ID_WIDTH" spirit:choiceRef="choice_list_35b40bd0" spirit:order="57600">6</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP1_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP1)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP1_DATA_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP1 DATA WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP1_DATA_WIDTH" spirit:choiceRef="choice_list_99ba8646" spirit:order="57800">64</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP1_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP1)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP2_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP2 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP2_ID_WIDTH" spirit:choiceRef="choice_list_35b40bd0" spirit:order="58200">6</spirit:value>
- <spirit:vendorExtensions>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP2_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP2)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP2_DATA_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP2 DATA WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP2_DATA_WIDTH" spirit:choiceRef="choice_list_99ba8646" spirit:order="58400">64</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP2_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP2)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP3_ID_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP3 ID WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP3_ID_WIDTH" spirit:choiceRef="choice_list_35b40bd0" spirit:order="58800">6</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP3_ID_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP3)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_S_AXI_HP3_DATA_WIDTH</spirit:name>
- <spirit:displayName>PCW S AXI HP3 DATA WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_S_AXI_HP3_DATA_WIDTH" spirit:choiceRef="choice_list_99ba8646" spirit:order="59000">64</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_S_AXI_HP3_DATA_WIDTH" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_S_AXI_HP3)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NUM_F2P_INTR_INPUTS</spirit:name>
- <spirit:displayName>PCW NUM F2P INTR INPUTS</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NUM_F2P_INTR_INPUTS" spirit:order="62500" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_NUM_F2P_INTR_INPUTS" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_IRQ_F2P_INTR)) = 1) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_DDR</spirit:name>
- <spirit:displayName>PCW EN DDR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_DDR" spirit:choiceRef="choice_list_8af5a703" spirit:order="8000">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_SMC</spirit:name>
- <spirit:displayName>PCW EN SMC</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_SMC" spirit:choiceRef="choice_list_8af5a703" spirit:order="8100">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_QSPI</spirit:name>
- <spirit:displayName>PCW EN QSPI</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_QSPI" spirit:choiceRef="choice_list_8af5a703" spirit:order="8200">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CAN0</spirit:name>
- <spirit:displayName>PCW EN CAN0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CAN0" spirit:choiceRef="choice_list_8af5a703" spirit:order="8300">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CAN1</spirit:name>
- <spirit:displayName>PCW EN CAN1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CAN1" spirit:choiceRef="choice_list_8af5a703" spirit:order="8400">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_ENET0</spirit:name>
- <spirit:displayName>PCW EN ENET0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_ENET0" spirit:choiceRef="choice_list_8af5a703" spirit:order="8500">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_ENET1</spirit:name>
- <spirit:displayName>PCW EN ENET1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_ENET1" spirit:choiceRef="choice_list_8af5a703" spirit:order="8600">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_GPIO</spirit:name>
- <spirit:displayName>PCW EN GPIO</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_GPIO" spirit:choiceRef="choice_list_8af5a703" spirit:order="8700">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_I2C0</spirit:name>
- <spirit:displayName>PCW EN I2C0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_I2C0" spirit:choiceRef="choice_list_8af5a703" spirit:order="8800">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_I2C1</spirit:name>
- <spirit:displayName>PCW EN I2C1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_I2C1" spirit:choiceRef="choice_list_8af5a703" spirit:order="8900">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_PJTAG</spirit:name>
- <spirit:displayName>PCW EN PJTAG</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_PJTAG" spirit:choiceRef="choice_list_8af5a703" spirit:order="9000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_SDIO0</spirit:name>
- <spirit:displayName>PCW EN SDIO0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_SDIO0" spirit:choiceRef="choice_list_8af5a703" spirit:order="9100">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_SDIO1</spirit:name>
- <spirit:displayName>PCW EN SDIO1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_SDIO1" spirit:choiceRef="choice_list_8af5a703" spirit:order="9200">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_SPI0</spirit:name>
- <spirit:displayName>PCW EN SPI0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_SPI0" spirit:choiceRef="choice_list_8af5a703" spirit:order="9300">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_SPI1</spirit:name>
- <spirit:displayName>PCW EN SPI1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_SPI1" spirit:choiceRef="choice_list_8af5a703" spirit:order="9400">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_UART0</spirit:name>
- <spirit:displayName>PCW EN UART0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_UART0" spirit:choiceRef="choice_list_8af5a703" spirit:order="9500">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_UART1</spirit:name>
- <spirit:displayName>PCW EN UART1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_UART1" spirit:choiceRef="choice_list_8af5a703" spirit:order="9600">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_MODEM_UART0</spirit:name>
- <spirit:displayName>PCW EN MODEM UART0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_MODEM_UART0" spirit:choiceRef="choice_list_8af5a703" spirit:order="9700">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_MODEM_UART1</spirit:name>
- <spirit:displayName>PCW EN MODEM UART1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_MODEM_UART1" spirit:choiceRef="choice_list_8af5a703" spirit:order="9800">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_TTC0</spirit:name>
- <spirit:displayName>PCW EN TTC0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_TTC0" spirit:choiceRef="choice_list_8af5a703" spirit:order="9900">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_TTC1</spirit:name>
- <spirit:displayName>PCW EN TTC1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_TTC1" spirit:choiceRef="choice_list_8af5a703" spirit:order="10000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_WDT</spirit:name>
- <spirit:displayName>PCW EN WDT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_WDT" spirit:choiceRef="choice_list_8af5a703" spirit:order="10100">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_TRACE</spirit:name>
- <spirit:displayName>PCW EN TRACE</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_TRACE" spirit:choiceRef="choice_list_8af5a703" spirit:order="10200">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_USB0</spirit:name>
- <spirit:displayName>PCW EN USB0</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_USB0" spirit:choiceRef="choice_list_8af5a703" spirit:order="10300">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_USB1</spirit:name>
- <spirit:displayName>PCW EN USB1</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_USB1" spirit:choiceRef="choice_list_8af5a703" spirit:order="10400">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DQ_WIDTH</spirit:name>
- <spirit:displayName>PCW DQ WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DQ_WIDTH" spirit:choiceRef="choice_list_20dc6536" spirit:order="15">32</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DQS_WIDTH</spirit:name>
- <spirit:displayName>PCW DQS WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DQS_WIDTH" spirit:choiceRef="choice_list_1075ca33" spirit:order="14">4</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DM_WIDTH</spirit:name>
- <spirit:displayName>PCW DM WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DM_WIDTH" spirit:choiceRef="choice_list_1075ca33" spirit:order="13">4</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_PRIMITIVE</spirit:name>
- <spirit:displayName>PCW MIO PRIMITIVE</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_PRIMITIVE" spirit:choiceRef="choice_list_a0318123" spirit:order="12">54</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLK0_PORT</spirit:name>
- <spirit:displayName>PCW EN CLK0 PORT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLK0_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60241">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLK0_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLK1_PORT</spirit:name>
- <spirit:displayName>PCW EN CLK1 PORT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLK1_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60242">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLK1_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLK2_PORT</spirit:name>
- <spirit:displayName>PCW EN CLK2 PORT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLK2_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60243">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLK2_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLK3_PORT</spirit:name>
- <spirit:displayName>PCW EN CLK3 PORT</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLK3_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60244">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLK3_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_RST0_PORT</spirit:name>
- <spirit:displayName>PCW EN RST0 PORT</spirit:displayName>
- <spirit:description>Enables general purpose reset signal 0 for PL logic</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_RST0_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60245">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_RST0_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_RST1_PORT</spirit:name>
- <spirit:displayName>PCW EN RST1 PORT</spirit:displayName>
- <spirit:description>Enables general purpose reset signal 1 for PL logic</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_RST1_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60246">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_RST1_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_RST2_PORT</spirit:name>
- <spirit:displayName>PCW EN RST2 PORT</spirit:displayName>
- <spirit:description>Enables general purpose reset signal 2 for PL logic</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_RST2_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60247">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_RST2_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_RST3_PORT</spirit:name>
- <spirit:displayName>PCW EN RST3 PORT</spirit:displayName>
- <spirit:description>Enables general purpose reset signal 3 for PL logic</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_RST3_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60248">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_RST3_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLKTRIG0_PORT</spirit:name>
- <spirit:displayName>PCW EN CLKTRIG0 PORT</spirit:displayName>
- <spirit:description>Enables PL clock trigger signal 0 used to halt the PL clock when counting a programmed number of clock pulses</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLKTRIG0_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60249">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLKTRIG0_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLKTRIG1_PORT</spirit:name>
- <spirit:displayName>PCW EN CLKTRIG1 PORT</spirit:displayName>
- <spirit:description>Enables PL clock trigger signal 1 used to halt the PL clock when counting a programmed number of clock pulses</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLKTRIG1_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60250">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLKTRIG1_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLKTRIG2_PORT</spirit:name>
- <spirit:displayName>PCW EN CLKTRIG2 PORT</spirit:displayName>
- <spirit:description>Enables PL clock trigger signal 2 used to halt the PL clock when counting a programmed number of clock pulses</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLKTRIG2_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60251">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLKTRIG2_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_EN_CLKTRIG3_PORT</spirit:name>
- <spirit:displayName>PCW EN CLKTRIG3 PORT</spirit:displayName>
- <spirit:description>Enables PL clock trigger signal 3 used to halt the PL clock when counting a programmed number of clock pulses</spirit:description>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_EN_CLKTRIG3_PORT" spirit:choiceRef="choice_list_8af5a703" spirit:order="60252">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_EN_CLKTRIG3_PORT" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_CR_FABRIC)) == 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC_ABORT_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC ABORT INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC_ABORT_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60253">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC_ABORT_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC0_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60254">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC1_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60255">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC2_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC2 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC2_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60256">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC2_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC3_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC3 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC3_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60257">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC3_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC4_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC4 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC4_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60258">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC4_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC5_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC5 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC5_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60259">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC5_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC6_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC6 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC6_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60260">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC6_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_DMAC7_INTR</spirit:name>
- <spirit:displayName>PCW P2F DMAC7 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_DMAC7_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60261">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_DMAC7_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&((spirit:decode(id(PARAM_VALUE.PCW_USE_DMA0)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA1)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA2)) = 1)||(spirit:decode(id(PARAM_VALUE.PCW_USE_DMA3)) = 1)))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_SMC_INTR</spirit:name>
- <spirit:displayName>PCW P2F SMC INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_SMC_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60262">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_SMC_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_SMC)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_QSPI_INTR</spirit:name>
- <spirit:displayName>PCW P2F QSPI INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_QSPI_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60263">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_QSPI_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_QSPI)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_CTI_INTR</spirit:name>
- <spirit:displayName>PCW P2F CTI INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_CTI_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60264">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_CTI_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_USE_CROSS_TRIGGER)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_GPIO_INTR</spirit:name>
- <spirit:displayName>PCW P2F GPIO INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_GPIO_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60265">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_GPIO_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_GPIO)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_USB0_INTR</spirit:name>
- <spirit:displayName>PCW P2F USB0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_USB0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60266">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_USB0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_USB0)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_ENET0_INTR</spirit:name>
- <spirit:displayName>PCW P2F ENET0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_ENET0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60267">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_ENET0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_ENET0)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_SDIO0_INTR</spirit:name>
- <spirit:displayName>PCW P2F SDIO0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_SDIO0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60268">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_SDIO0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_SDIO0)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_I2C0_INTR</spirit:name>
- <spirit:displayName>PCW P2F I2C0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_I2C0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60269">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_I2C0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_I2C0)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_SPI0_INTR</spirit:name>
- <spirit:displayName>PCW P2F SPI0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_SPI0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60270">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_SPI0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_SPI0)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_UART0_INTR</spirit:name>
- <spirit:displayName>PCW P2F UART0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_UART0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60271">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_UART0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_UART0)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_CAN0_INTR</spirit:name>
- <spirit:displayName>PCW P2F CAN0 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_CAN0_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60272">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_CAN0_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CAN0)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_USB1_INTR</spirit:name>
- <spirit:displayName>PCW P2F USB1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_USB1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60273">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_USB1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_USB1)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_ENET1_INTR</spirit:name>
- <spirit:displayName>PCW P2F ENET1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_ENET1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60274">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_ENET1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_ENET1)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_SDIO1_INTR</spirit:name>
- <spirit:displayName>PCW P2F SDIO1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_SDIO1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60275">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_SDIO1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_SDIO1)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_I2C1_INTR</spirit:name>
- <spirit:displayName>PCW P2F I2C1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_I2C1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60276">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_I2C1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_I2C1)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_SPI1_INTR</spirit:name>
- <spirit:displayName>PCW P2F SPI1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_SPI1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60277">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_SPI1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_SPI1)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_UART1_INTR</spirit:name>
- <spirit:displayName>PCW P2F UART1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_UART1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60278">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_UART1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_UART1)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_P2F_CAN1_INTR</spirit:name>
- <spirit:displayName>PCW P2F CAN1 INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_P2F_CAN1_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60279">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_P2F_CAN1_INTR" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CAN1)) = 1))">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_IRQ_F2P_INTR</spirit:name>
- <spirit:displayName>PCW IRQ F2P INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_IRQ_F2P_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60280">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_IRQ_F2P_INTR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_IRQ_F2P_MODE</spirit:name>
- <spirit:displayName>PCW IRQ F2P MODE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_IRQ_F2P_MODE" spirit:choiceRef="choice_list_46eb370a" spirit:order="60281">DIRECT</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_IRQ_F2P_MODE" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_IRQ_F2P_INTR)) = 1) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CORE0_FIQ_INTR</spirit:name>
- <spirit:displayName>PCW CORE0 FIQ INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CORE0_FIQ_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60281">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_CORE0_FIQ_INTR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CORE0_IRQ_INTR</spirit:name>
- <spirit:displayName>PCW CORE0 IRQ INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CORE0_IRQ_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60282">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_CORE0_IRQ_INTR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CORE1_FIQ_INTR</spirit:name>
- <spirit:displayName>PCW CORE1 FIQ INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CORE1_FIQ_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60283">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_CORE1_FIQ_INTR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CORE1_IRQ_INTR</spirit:name>
- <spirit:displayName>PCW CORE1 IRQ INTR</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CORE1_IRQ_INTR" spirit:choiceRef="choice_list_8af5a703" spirit:order="60284">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_CORE1_IRQ_INTR" xilinx:dependency="(spirit:decode(id(PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT)) = 1)">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_VALUE_SILVERSION</spirit:name>
- <spirit:displayName>PCW VALUE SILVERSION</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_VALUE_SILVERSION" spirit:choiceRef="choice_list_7d6d1b3f" spirit:order="60285">3</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GP0_EN_MODIFIABLE_TXN</spirit:name>
- <spirit:displayName>PCW GP0 EN MODIFIABLE TXN</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GP0_EN_MODIFIABLE_TXN" spirit:choiceRef="choice_list_ae9f88f6" spirit:order="63400">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GP1_EN_MODIFIABLE_TXN</spirit:name>
- <spirit:displayName>PCW GP1 EN MODIFIABLE TXN</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GP1_EN_MODIFIABLE_TXN" spirit:choiceRef="choice_list_ae9f88f6" spirit:order="63400">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_IMPORT_BOARD_PRESET</spirit:name>
- <spirit:displayName>PCW IMPORT BOARD PRESET</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_IMPORT_BOARD_PRESET" spirit:order="10">None</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PERIPHERAL_BOARD_PRESET</spirit:name>
- <spirit:displayName>PCW PERIPHERAL BOARD PRESET</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PERIPHERAL_BOARD_PRESET" spirit:order="16">None</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PRESET_BANK0_VOLTAGE</spirit:name>
- <spirit:displayName>PCW PRESET BANK0 VOLTAGE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PRESET_BANK0_VOLTAGE" spirit:choiceRef="choice_list_3f5f808e" spirit:order="29200">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PRESET_BANK1_VOLTAGE</spirit:name>
- <spirit:displayName>PCW PRESET BANK1 VOLTAGE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PRESET_BANK1_VOLTAGE" spirit:choiceRef="choice_list_72f3e128" spirit:order="29300">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_ENABLE</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7999">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_ADV_ENABLE</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR ADV ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_ADV_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7999">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_MEMORY_TYPE</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR MEMORY TYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_MEMORY_TYPE" spirit:choiceRef="choice_list_c5ebb0ea" spirit:order="13000">DDR 3 (Low Voltage)</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_ECC</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR ECC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_ECC" spirit:choiceRef="choice_list_fc3456a9" spirit:order="13200">Disabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_BUS_WIDTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR BUS WIDTH</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BUS_WIDTH" spirit:choiceRef="choice_list_7abc2131" spirit:order="13100">16 Bit</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_BL</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR BL</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BL" spirit:choiceRef="choice_list_fd37a6fb" spirit:order="13300">8</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_HIGH_TEMP</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR HIGH TEMP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_HIGH_TEMP" spirit:choiceRef="choice_list_2e355d8b" spirit:order="13400">Normal (0-85)</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_PARTNO</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR PARTNO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_PARTNO" spirit:choiceRef="choice_list_be8ca58c" spirit:order="13600">MT41K128M16 JT-125</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DRAM_WIDTH</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DRAM WIDTH</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DRAM_WIDTH" spirit:choiceRef="choice_list_eaad72ce" spirit:order="13700">16 Bits</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_DRAM_WIDTH">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_DEVICE_CAPACITY</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR DEVICE CAPACITY</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_DEVICE_CAPACITY" spirit:choiceRef="choice_list_32c7371b" spirit:order="13800">2048 MBits</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_DEVICE_CAPACITY">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_SPEED_BIN</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR SPEED BIN</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_SPEED_BIN" spirit:choiceRef="choice_list_bbba28a6" spirit:order="14000">DDR3_1066F</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UIPARAM_DDR_SPEED_BIN">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR TRAIN WRITE LEVEL</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" spirit:choiceRef="choice_list_8af5a703" spirit:order="15600">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_TRAIN_READ_GATE</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR TRAIN READ GATE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_TRAIN_READ_GATE" spirit:choiceRef="choice_list_8af5a703" spirit:order="15700">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_TRAIN_DATA_EYE</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR TRAIN DATA EYE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_TRAIN_DATA_EYE" spirit:choiceRef="choice_list_8af5a703" spirit:order="15800">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_CLOCK_STOP_EN</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR CLOCK STOP EN</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_STOP_EN" spirit:choiceRef="choice_list_8af5a703" spirit:order="15900">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_DDR_USE_INTERNAL_VREF</spirit:name>
- <spirit:displayName>PCW UIPARAM DDR USE INTERNAL VREF</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_USE_INTERNAL_VREF" spirit:choiceRef="choice_list_8af5a703" spirit:order="16000">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_WRITEPORT_0</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY WRITEPORT 0</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_0" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_WRITEPORT_0">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_WRITEPORT_1</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY WRITEPORT 0</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_1" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_WRITEPORT_1">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_WRITEPORT_2</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY WRITEPORT 0</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_2" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_WRITEPORT_2">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_WRITEPORT_3</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY WRITEPORT 0</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_3" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_WRITEPORT_3">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_READPORT_0</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY READPORT 0</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_0" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_READPORT_0">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_READPORT_1</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY READPORT 1</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_1" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_READPORT_1">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_READPORT_2</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY READPORT 2</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_2" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_READPORT_2">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PRIORITY_READPORT_3</spirit:name>
- <spirit:displayName>PCW DDR PRIORITY READPORT 3</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_3" spirit:choiceRef="choice_list_4d36a164" spirit:order="16000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PRIORITY_READPORT_3">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PORT0_HPR_ENABLE</spirit:name>
- <spirit:displayName>PCW DDR PORT0 ENABLE HPR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PORT0_HPR_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="16000">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PORT0_HPR_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PORT1_HPR_ENABLE</spirit:name>
- <spirit:displayName>PCW DDR PORT1 ENABLE HPR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PORT1_HPR_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="16000">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PORT1_HPR_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PORT2_HPR_ENABLE</spirit:name>
- <spirit:displayName>PCW DDR PORT2 ENABLE HPR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PORT2_HPR_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="16000">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PORT2_HPR_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PORT3_HPR_ENABLE</spirit:name>
- <spirit:displayName>PCW DDR PORT3 ENABLE HPR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PORT3_HPR_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="16000">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_PORT3_HPR_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_HPRLPR_QUEUE_PARTITION</spirit:name>
- <spirit:displayName>PCW DDR HPRLPR QUEUE PARTITION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_HPRLPR_QUEUE_PARTITION" spirit:choiceRef="choice_list_2328412a" spirit:order="16000">HPR(0)/LPR(32)</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_HPRLPR_QUEUE_PARTITION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL</spirit:name>
- <spirit:displayName>PCW DDR LPR TO CRITICAL PRIORITY LEVEL</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" spirit:order="16000" spirit:minimum="0.000000" spirit:maximum="2047.000000">2</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL</spirit:name>
- <spirit:displayName>PCW DDR HPR TO CRITICAL PRIORITY LEVEL</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" spirit:order="16000" spirit:minimum="0.000000" spirit:maximum="2047.000000">15</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL</spirit:name>
- <spirit:displayName>PCW DDR WRITE TO CRITICAL PRIORITY LEVEL</spirit:displayName>
- <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" spirit:order="16000" spirit:minimum="0.000000" spirit:maximum="2047.000000">2</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW NAND PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="100">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NAND_PERIPHERAL_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_NAND_IO</spirit:name>
- <spirit:displayName>PCW NAND NAND IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_NAND_IO" spirit:choiceRef="choice_list_2091a159" spirit:order="6000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NAND_NAND_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_GRP_D8_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_GRP_D8_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6001">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NAND_GRP_D8_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_GRP_D8_IO</spirit:name>
- <spirit:displayName>PCW NAND GRP D8 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_GRP_D8_IO" spirit:choiceRef="choice_list_fb1b25ef" spirit:order="6002"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NAND_GRP_D8_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW NOR PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="200">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_PERIPHERAL_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_NOR_IO</spirit:name>
- <spirit:displayName>PCW NOR NOR IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_NOR_IO" spirit:choiceRef="choice_list_353a343d" spirit:order="5900"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_NOR_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_A25_ENABLE</spirit:name>
- <spirit:displayName>PCW NOR GRP A25 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_A25_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5901">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_A25_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_A25_IO</spirit:name>
- <spirit:displayName>PCW NOR GRP CS0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_A25_IO" spirit:choiceRef="choice_list_303d848a" spirit:order="5902"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_A25_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_CS0_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_CS0_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5903">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_CS0_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_CS0_IO</spirit:name>
- <spirit:displayName>PCW NOR GRP CS1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_CS0_IO" spirit:choiceRef="choice_list_e14dbfa8" spirit:order="5904"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_CS0_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_SRAM_CS0_ENABLE</spirit:name>
- <spirit:displayName>PCW NOR GRP SRAM CS0 ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5905">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_SRAM_CS0_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_SRAM_CS0_IO</spirit:name>
- <spirit:displayName>PCW NOR GRP SRAM CS1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_IO" spirit:choiceRef="choice_list_e14dbfa8" spirit:order="5906"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_SRAM_CS0_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_CS1_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_CS1_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5907">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_CS1_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_CS1_IO</spirit:name>
- <spirit:displayName>PCW NOR GRP SRAM CS0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_CS1_IO" spirit:choiceRef="choice_list_303d848a" spirit:order="5908"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_CS1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_SRAM_CS1_ENABLE</spirit:name>
- <spirit:displayName>PCW NOR GRP SRAM CS1 ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5909">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_SRAM_CS1_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_SRAM_CS1_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_IO" spirit:choiceRef="choice_list_303d848a" spirit:order="5910"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_SRAM_CS1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_SRAM_INT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5911">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_SRAM_INT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_GRP_SRAM_INT_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_IO" spirit:choiceRef="choice_list_f7b6ff1b" spirit:order="5912"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_NOR_GRP_SRAM_INT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW QSPI PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="300">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_QSPI_IO</spirit:name>
- <spirit:displayName>PCW QSPI QSPI IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_QSPI_IO" spirit:choiceRef="choice_list_cbbe7bdf" spirit:order="5800">MIO 1 .. 6</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_SINGLE_SS_ENABLE</spirit:name>
- <spirit:displayName>PCW QSPI GRP SINGLE SS ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5808">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_SINGLE_SS_IO</spirit:name>
- <spirit:displayName>PCW QSPI GRP SINGLE SS IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_IO" spirit:choiceRef="choice_list_cbbe7bdf" spirit:order="5809">MIO 1 .. 6</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_SS1_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_SS1_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5801">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_SS1_IO</spirit:name>
- <spirit:displayName>PCW QSPI GRP SS1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_SS1_IO" spirit:choiceRef="choice_list_e14dbfa8" spirit:order="5802"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_QSPI_GRP_SS1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SINGLE_QSPI_DATA_MODE</spirit:name>
- <spirit:displayName>Single QSPI Data Mode</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SINGLE_QSPI_DATA_MODE" spirit:choiceRef="choice_list_5beb845c" spirit:order="5802">x4</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DUAL_STACK_QSPI_DATA_MODE</spirit:name>
- <spirit:displayName>Dual Stack QSPI Data Mode</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DUAL_STACK_QSPI_DATA_MODE" spirit:choiceRef="choice_list_bc805c93" spirit:order="5802"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DUAL_STACK_QSPI_DATA_MODE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DUAL_PARALLEL_QSPI_DATA_MODE</spirit:name>
- <spirit:displayName>Dual Parallel QSPI Data Mode</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DUAL_PARALLEL_QSPI_DATA_MODE" spirit:choiceRef="choice_list_3b9f1944" spirit:order="5802"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_DUAL_PARALLEL_QSPI_DATA_MODE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_IO1_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_IO1_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5803">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_IO1_IO</spirit:name>
- <spirit:displayName>PCW QSPI GRP IO1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_IO1_IO" spirit:choiceRef="choice_list_d2f51b63" spirit:order="5804"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_QSPI_GRP_IO1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_FBCLK_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5805">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_GRP_FBCLK_IO</spirit:name>
- <spirit:displayName>PCW QSPI GRP FBCLK IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_IO" spirit:choiceRef="choice_list_dc7979fd" spirit:order="5806"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_QSPI_GRP_FBCLK_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_INTERNAL_HIGHADDRESS</spirit:name>
- <spirit:displayName>PCW QSPI INTERNAL HIGHADDRESS</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_INTERNAL_HIGHADDRESS" spirit:choiceRef="choice_list_d525dd8e" spirit:order="5807" spirit:bitStringLength="32">0xFCFFFFFF</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW ENET0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="400">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_ENET0_IO</spirit:name>
- <spirit:displayName>PCW ENET0 ENET0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_ENET0_IO" spirit:choiceRef="choice_list_86cc57ee" spirit:order="6100">MIO 16 .. 27</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_GRP_MDIO_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_GRP_MDIO_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6101">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_GRP_MDIO_IO</spirit:name>
- <spirit:displayName>PCW ENET0 GRP MDIO IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_GRP_MDIO_IO" spirit:choiceRef="choice_list_606c1634" spirit:order="6102"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET0_GRP_MDIO_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6103">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET_RESET_SELECT</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET_RESET_SELECT" spirit:choiceRef="choice_list_ce2e47bd" spirit:order="6103">Share reset pin</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6103">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_RESET_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6104"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET0_RESET_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW ENET1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="500">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_ENET1_IO</spirit:name>
- <spirit:displayName>PCW ENET1 ENET1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_ENET1_IO" spirit:choiceRef="choice_list_b66926f4" spirit:order="6200"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET1_ENET1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_GRP_MDIO_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_GRP_MDIO_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6201">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET1_GRP_MDIO_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_GRP_MDIO_IO</spirit:name>
- <spirit:displayName>PCW ENET1 GRP MDIO IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_GRP_MDIO_IO" spirit:choiceRef="choice_list_606c1634" spirit:order="6202"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET1_GRP_MDIO_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6203">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET1_RESET_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_RESET_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6204"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET1_RESET_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW SD0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="600">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_SD0_IO</spirit:name>
- <spirit:displayName>PCW SD0 SD0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_SD0_IO" spirit:choiceRef="choice_list_390b0393" spirit:order="6500"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD0_SD0_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_GRP_CD_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_GRP_CD_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6501">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD0_GRP_CD_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_GRP_CD_IO</spirit:name>
- <spirit:displayName>PCW SD0 GRP CD IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_GRP_CD_IO" spirit:choiceRef="choice_list_6a282484" spirit:order="6502"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD0_GRP_CD_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_GRP_WP_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_GRP_WP_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6503">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD0_GRP_WP_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_GRP_WP_IO</spirit:name>
- <spirit:displayName>PCW SD0 GRP WP IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_GRP_WP_IO" spirit:choiceRef="choice_list_6a282484" spirit:order="6504"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD0_GRP_WP_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_GRP_POW_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_GRP_POW_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6505">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD0_GRP_POW_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD0_GRP_POW_IO</spirit:name>
- <spirit:displayName>PCW SD0 GRP POW IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD0_GRP_POW_IO" spirit:choiceRef="choice_list_3c74058c" spirit:order="6506"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD0_GRP_POW_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW SD1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="700">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_SD1_IO</spirit:name>
- <spirit:displayName>PCW SD1 SD1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_SD1_IO" spirit:choiceRef="choice_list_d8fa963a" spirit:order="6600">MIO 10 .. 15</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_GRP_CD_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_GRP_CD_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6601">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_GRP_CD_IO</spirit:name>
- <spirit:displayName>PCW SD1 GRP CD IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_GRP_CD_IO" spirit:choiceRef="choice_list_75a9626b" spirit:order="6602">MIO 9</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_GRP_WP_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_GRP_WP_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6603">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_GRP_WP_IO</spirit:name>
- <spirit:displayName>PCW SD1 GRP WP IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_GRP_WP_IO" spirit:choiceRef="choice_list_6a282484" spirit:order="6604"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD1_GRP_WP_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_GRP_POW_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_GRP_POW_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6605">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SD1_GRP_POW_IO</spirit:name>
- <spirit:displayName>PCW SD1 GRP POW IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SD1_GRP_POW_IO" spirit:choiceRef="choice_list_83072ce2" spirit:order="6606"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SD1_GRP_POW_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW UART0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="800">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART0_UART0_IO</spirit:name>
- <spirit:displayName>PCW UART0 UART0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART0_UART0_IO" spirit:choiceRef="choice_list_f632ce2e" spirit:order="6700">MIO 46 .. 47</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART0_GRP_FULL_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART0_GRP_FULL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6701">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART0_GRP_FULL_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART0_GRP_FULL_IO" spirit:choiceRef="choice_list_f7b6ff1b" spirit:order="6702"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UART0_GRP_FULL_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW UART1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="900">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART1_UART1_IO</spirit:name>
- <spirit:displayName>PCW UART1 UART1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART1_UART1_IO" spirit:choiceRef="choice_list_0f5c91ba" spirit:order="6800">MIO 48 .. 49</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART1_GRP_FULL_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART1_GRP_FULL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6801">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART1_GRP_FULL_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART1_GRP_FULL_IO" spirit:choiceRef="choice_list_f7b6ff1b" spirit:order="6802"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_UART1_GRP_FULL_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW SPI0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1000">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_SPI0_IO</spirit:name>
- <spirit:displayName>PCW SPI0 SPI0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_SPI0_IO" spirit:choiceRef="choice_list_8f11124f" spirit:order="7100">MIO 40 .. 45</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_GRP_SS0_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_GRP_SS0_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7105">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI0_GRP_SS0_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_GRP_SS0_IO</spirit:name>
- <spirit:displayName>PCW SPI0 GRP SS0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_GRP_SS0_IO" spirit:choiceRef="choice_list_8436647b" spirit:order="7106">MIO 42</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI0_GRP_SS0_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_GRP_SS1_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_GRP_SS1_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7103">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_GRP_SS1_IO</spirit:name>
- <spirit:displayName>PCW SPI0 GRP SS1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_GRP_SS1_IO" spirit:choiceRef="choice_list_78fdaebe" spirit:order="7104"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI0_GRP_SS1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_GRP_SS2_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_GRP_SS2_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7101">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI0_GRP_SS2_IO</spirit:name>
- <spirit:displayName>PCW SPI0 GRP SS2 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI0_GRP_SS2_IO" spirit:choiceRef="choice_list_ec5c3204" spirit:order="7102"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI0_GRP_SS2_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW SPI1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1100">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_SPI1_IO</spirit:name>
- <spirit:displayName>PCW SPI1 SPI1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_SPI1_IO" spirit:choiceRef="choice_list_d8fa963a" spirit:order="7200">EMIO</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_GRP_SS0_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_GRP_SS0_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7205">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI1_GRP_SS0_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_GRP_SS0_IO</spirit:name>
- <spirit:displayName>PCW SPI1 GRP SS0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_GRP_SS0_IO" spirit:choiceRef="choice_list_6e6efe45" spirit:order="7206">EMIO</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI1_GRP_SS0_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_GRP_SS1_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_GRP_SS1_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7203">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI1_GRP_SS1_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_GRP_SS1_IO</spirit:name>
- <spirit:displayName>PCW SPI1 GRP SS1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_GRP_SS1_IO" spirit:choiceRef="choice_list_6b183472" spirit:order="7204">EMIO</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI1_GRP_SS1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_GRP_SS2_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_GRP_SS2_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7201">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI1_GRP_SS2_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI1_GRP_SS2_IO</spirit:name>
- <spirit:displayName>PCW SPI1 GRP SS2 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI1_GRP_SS2_IO" spirit:choiceRef="choice_list_4b3359e9" spirit:order="7202">EMIO</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_SPI1_GRP_SS2_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW CAN0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1200">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN0_CAN0_IO</spirit:name>
- <spirit:displayName>PCW CAN0 CAN0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN0_CAN0_IO" spirit:choiceRef="choice_list_5d0f73c4" spirit:order="7300"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN0_CAN0_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN0_GRP_CLK_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN0_GRP_CLK_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7301">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN0_GRP_CLK_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN0_GRP_CLK_IO</spirit:name>
- <spirit:displayName>PCW CAN0 GRP CLK IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN0_GRP_CLK_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="7302"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN0_GRP_CLK_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW CAN1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1300">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN1_CAN1_IO</spirit:name>
- <spirit:displayName>PCW CAN1 CAN1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_CAN1_IO" spirit:choiceRef="choice_list_0f5c91ba" spirit:order="7400">MIO 52 .. 53</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN1_GRP_CLK_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_GRP_CLK_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7401">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN1_GRP_CLK_IO</spirit:name>
- <spirit:displayName>PCW CAN1 GRP CLK IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_GRP_CLK_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="7402"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_CAN1_GRP_CLK_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW TRACE PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1400">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_TRACE_IO</spirit:name>
- <spirit:displayName>PCW TRACE TRACE IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_TRACE_IO" spirit:choiceRef="choice_list_935a3e6e" spirit:order="7500"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_TRACE_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_2BIT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_2BIT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7501">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_2BIT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_2BIT_IO</spirit:name>
- <spirit:displayName>PCW TRACE GRP 2BIT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_2BIT_IO" spirit:choiceRef="choice_list_45a0fd9c" spirit:order="7502"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_2BIT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_4BIT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_4BIT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7503">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_4BIT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_4BIT_IO</spirit:name>
- <spirit:displayName>PCW TRACE GRP 4BIT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_4BIT_IO" spirit:choiceRef="choice_list_af9e7a8f" spirit:order="7504"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_4BIT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_8BIT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_8BIT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7505">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_8BIT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_8BIT_IO</spirit:name>
- <spirit:displayName>PCW TRACE GRP 8BIT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_8BIT_IO" spirit:choiceRef="choice_list_908f40dd" spirit:order="7506"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_8BIT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_16BIT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_16BIT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7507">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_16BIT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_16BIT_IO</spirit:name>
- <spirit:displayName>PCW TRACE GRP 16BIT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_16BIT_IO" spirit:choiceRef="choice_list_ba65fe0e" spirit:order="7508"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_16BIT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_32BIT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_32BIT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7509">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_32BIT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_GRP_32BIT_IO</spirit:name>
- <spirit:displayName>PCW TRACE GRP 32BIT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_GRP_32BIT_IO" spirit:choiceRef="choice_list_f7b6ff1b" spirit:order="7510"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TRACE_GRP_32BIT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TRACE_INTERNAL_WIDTH</spirit:name>
- <spirit:displayName>PCW TRACE INTERNAL WIDTH</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TRACE_INTERNAL_WIDTH" spirit:choiceRef="choice_list_ca108395" spirit:order="7511">2</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_WDT_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW WDT PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_WDT_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1500">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_WDT_WDT_IO</spirit:name>
- <spirit:displayName>PCW WDT WDT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_WDT_WDT_IO" spirit:choiceRef="choice_list_a8e6d6fb" spirit:order="7800"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_WDT_WDT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW TTC0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1600">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC0_TTC0_IO</spirit:name>
- <spirit:displayName>PCW TTC0 TTC0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_TTC0_IO" spirit:choiceRef="choice_list_1a80fa5a" spirit:order="7600"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TTC0_TTC0_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW TTC1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1700">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC1_TTC1_IO</spirit:name>
- <spirit:displayName>PCW TTC1 TTC1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC1_TTC1_IO" spirit:choiceRef="choice_list_d282f9a2" spirit:order="7700"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_TTC1_TTC1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PJTAG_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW PJTAG PERIPHERAL ENABLE </spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PJTAG_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1750">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PJTAG_PJTAG_IO</spirit:name>
- <spirit:displayName>PCW PJTAG PJTAG IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PJTAG_PJTAG_IO" spirit:choiceRef="choice_list_56e9f994" spirit:order="7900"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_PJTAG_PJTAG_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW USB0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1800">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB0_USB0_IO</spirit:name>
- <spirit:displayName>PCW USB0 USB0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB0_USB0_IO" spirit:choiceRef="choice_list_1622b516" spirit:order="6300">MIO 28 .. 39</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6103">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB_RESET_SELECT</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB_RESET_SELECT" spirit:choiceRef="choice_list_ce2e47bd" spirit:order="6103">Share reset pin</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB0_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB0_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6301">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB0_RESET_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6302"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_USB0_RESET_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW USB1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1900">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB1_USB1_IO</spirit:name>
- <spirit:displayName>PCW USB1 USB1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB1_USB1_IO" spirit:choiceRef="choice_list_020b381d" spirit:order="6400"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_USB1_USB1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB1_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB1_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6401">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_USB1_RESET_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB1_RESET_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB1_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6402"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_USB1_RESET_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C0_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW I2C0 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="2000">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C0_I2C0_IO</spirit:name>
- <spirit:displayName>PCW I2C0 I2C0 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_I2C0_IO" spirit:choiceRef="choice_list_f632ce2e" spirit:order="6900">MIO 50 .. 51</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C0_GRP_INT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_GRP_INT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6901">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C0_GRP_INT_IO</spirit:name>
- <spirit:displayName>PCW I2C0 GRP INT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_GRP_INT_IO" spirit:choiceRef="choice_list_b3ee7919" spirit:order="6902"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C0_GRP_INT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C0_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6903">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C0_RESET_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C0_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="6904"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C0_RESET_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C1_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW I2C1 PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="2100">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C1_I2C1_IO</spirit:name>
- <spirit:displayName>PCW I2C1 I2C1 IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C1_I2C1_IO" spirit:choiceRef="choice_list_88a617f1" spirit:order="7000"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C1_I2C1_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C1_GRP_INT_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C1_GRP_INT_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7001">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C1_GRP_INT_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C1_GRP_INT_IO</spirit:name>
- <spirit:displayName>PCW I2C1 GRP INT IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C1_GRP_INT_IO" spirit:choiceRef="choice_list_b3ee7919" spirit:order="7002"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C1_GRP_INT_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="6103">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C_RESET_SELECT</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C_RESET_SELECT" spirit:choiceRef="choice_list_ce2e47bd" spirit:order="6103">Share reset pin</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C1_RESET_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C1_RESET_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="7003">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C1_RESET_ENABLE">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C1_RESET_IO</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C1_RESET_IO" spirit:choiceRef="choice_list_d679c87d" spirit:order="7004"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_I2C1_RESET_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GPIO_PERIPHERAL_ENABLE</spirit:name>
- <spirit:displayName>PCW GPIO PERIPHERAL ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="2200">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GPIO_MIO_GPIO_ENABLE</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_MIO_GPIO_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5499">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GPIO_MIO_GPIO_IO</spirit:name>
- <spirit:displayName>PCW GPIO MIO GPIO IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_MIO_GPIO_IO" spirit:choiceRef="choice_list_6a48f1e0" spirit:order="5500">MIO</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GPIO_EMIO_GPIO_ENABLE</spirit:name>
- <spirit:displayName>PCW GPIO EMIO GPIO ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="5599">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_GPIO_EMIO_GPIO_IO</spirit:name>
- <spirit:displayName>PCW GPIO EMIO GPIO IO</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_IO" spirit:choiceRef="choice_list_5d70a6b7" spirit:order="5600"><Select></spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_GPIO_EMIO_GPIO_IO">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_APU_CLK_RATIO_ENABLE</spirit:name>
- <spirit:displayName>PCW APU CLK RATIO ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_APU_CLK_RATIO_ENABLE" spirit:choiceRef="choice_list_bd8e4b31" spirit:order="23400">6:2:1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ENET0 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_PERIPHERAL_FREQMHZ" spirit:choiceRef="choice_list_a841b9a1" spirit:order="23900">1000 Mbps</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_PERIPHERAL_FREQMHZ</spirit:name>
- <spirit:displayName>PCW ENET1 PERIPHERAL FREQMHZ</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_PERIPHERAL_FREQMHZ" spirit:choiceRef="choice_list_a841b9a1" spirit:order="24000">1000 Mbps</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_ENET1_PERIPHERAL_FREQMHZ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CPU_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW CPU PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CPU_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="20900">ARM PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DDR_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW DDR PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DDR_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_e743b0fa" spirit:order="20901">DDR PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW SMC PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21000">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_QSPI_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW QSPI PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_QSPI_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21100">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SDIO_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW SDIO PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SDIO_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21200">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UART_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW UART PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21300">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SPI_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW SPI PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SPI_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21400">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW CAN PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21500">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FCLK0_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW FCLK0 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21600">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FCLK1_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW FCLK1 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21700">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FCLK2_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW FCLK2 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21800">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FCLK3_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW FCLK3 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_ea556125" spirit:order="21900">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET0_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW ENET0 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET0_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_7d098ed6" spirit:order="22000">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET1_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW ENET1 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET1_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_dc85a6c5" spirit:order="22100">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN0_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW CAN0 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN0_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_767f870c" spirit:order="22200">External</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_CAN1_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW CAN1 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_CAN1_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_767f870c" spirit:order="22300">External</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TPIU_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW TPIU PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TPIU_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_0d7de060" spirit:order="22400">External</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC0_CLK0_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW TTC0 CLK0 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_d2a5f697" spirit:order="22500">CPU_1X</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC0_CLK1_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW TTC0 CLK1 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_d2a5f697" spirit:order="22600">CPU_1X</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC0_CLK2_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW TTC0 CLK2 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_d2a5f697" spirit:order="22700">CPU_1X</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC1_CLK0_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW TTC1 CLK0 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_d2a5f697" spirit:order="22800">CPU_1X</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC1_CLK1_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW TTC1 CLK1 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_d2a5f697" spirit:order="22900">CPU_1X</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_TTC1_CLK2_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW TTC1 CLK2 PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_d2a5f697" spirit:order="23000">CPU_1X</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_WDT_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW WDT PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_WDT_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_d2a5f697" spirit:order="23100">CPU_1X</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_DCI_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW DCI PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_DCI_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_e743b0fa" spirit:order="23100">DDR PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PCAP_PERIPHERAL_CLKSRC</spirit:name>
- <spirit:displayName>PCW PCAP PERIPHERAL CLKSRC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PCAP_PERIPHERAL_CLKSRC" spirit:choiceRef="choice_list_f591e16e" spirit:order="23100">IO PLL</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_USB_RESET_POLARITY</spirit:name>
- <spirit:displayName>PCW USB RESET POLARITY</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_USB_RESET_POLARITY" spirit:choiceRef="choice_list_6bd7fb73" spirit:order="34800">Active Low</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_ENET_RESET_POLARITY</spirit:name>
- <spirit:displayName>PCW USB RESET POLARITY</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_ENET_RESET_POLARITY" spirit:choiceRef="choice_list_6bd7fb73" spirit:order="34800">Active Low</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_I2C_RESET_POLARITY</spirit:name>
- <spirit:displayName>PCW USB RESET POLARITY</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_I2C_RESET_POLARITY" spirit:choiceRef="choice_list_6bd7fb73" spirit:order="34800">Active Low</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_0_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 0 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_0_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29400">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_0_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 0 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_0_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34800">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_0_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 0 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_0_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40200">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_0_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_0_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 0 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_0_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40300">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_1_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 1 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_1_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29401">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_1_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 1 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_1_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34801">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_1_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 1 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_1_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40201">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_1_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_1_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 1 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_1_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40301">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_2_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 2 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_2_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29402">disabled</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_2_PULLUP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_2_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 2 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_2_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34802">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_2_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 2 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_2_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40202">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_2_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_2_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 2 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_2_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40302">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_3_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 3 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_3_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29403">disabled</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_3_PULLUP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_3_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 3 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_3_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34803">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_3_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 3 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_3_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40203">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_3_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_3_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 3 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_3_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40303">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_4_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 4 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_4_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29404">disabled</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_4_PULLUP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_4_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 4 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_4_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34804">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_4_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 4 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_4_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40204">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_4_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_4_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 4 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_4_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40304">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_5_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 5 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_5_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29405">disabled</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_5_PULLUP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_5_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 5 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_5_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34805">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_5_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 5 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_5_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40205">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_5_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_5_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 5 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_5_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40305">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_6_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 6 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_6_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29406">disabled</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_6_PULLUP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_6_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 6 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_6_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34806">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_6_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 6 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_6_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40206">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_6_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_6_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 6 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_6_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40306">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_7_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 7 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_7_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29407">disabled</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_7_PULLUP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_7_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 7 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_7_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34807">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_7_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 7 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_7_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40207">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_7_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_7_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 7 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_7_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40307">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_8_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 8 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_8_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29408">disabled</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_8_PULLUP">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_8_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 8 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_8_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34808">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_8_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 8 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_8_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40208">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_8_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_8_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 8 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_8_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40308">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_9_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 9 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_9_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29409">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_9_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 9 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_9_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34809">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_9_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 9 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_9_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40209">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_9_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_9_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 9 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_9_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40309">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_10_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 10 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_10_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29410">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_10_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 10 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_10_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34810">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_10_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 10 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_10_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40210">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_10_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_10_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 10 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_10_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40310">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_11_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 11 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_11_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29411">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_11_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 11 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_11_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34811">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_11_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 11 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_11_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40211">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_11_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_11_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 11 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_11_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40311">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_12_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 12 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_12_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29412">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_12_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 12 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_12_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34812">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_12_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 12 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_12_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40212">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_12_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_12_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 12 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_12_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40312">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_13_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 13 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_13_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29413">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_13_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 13 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_13_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34813">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_13_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 13 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_13_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40213">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_13_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_13_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 13 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_13_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40313">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_14_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 14 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_14_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29414">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_14_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 14 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_14_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34814">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_14_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 14 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_14_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40214">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_14_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_14_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 14 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_14_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40314">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_15_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 15 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_15_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29415">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_15_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 15 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_15_IOTYPE" spirit:choiceRef="choice_list_6bc4d474" spirit:order="34815">LVCMOS 3.3V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_15_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 15 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_15_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40215">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_15_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_15_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 15 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_15_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40315">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_16_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 16 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_16_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29416">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_16_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 16 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_16_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34816">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_16_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 16 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_16_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40216">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_16_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_16_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 16 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_16_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40316">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_17_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 17 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_17_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29417">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_17_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 17 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_17_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34817">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_17_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 17 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_17_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40217">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_17_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_17_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 17 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_17_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40317">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_18_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 18 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_18_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29418">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_18_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 18 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_18_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34818">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_18_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 18 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_18_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40218">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_18_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_18_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 18 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_18_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40318">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_19_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 19 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_19_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29419">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_19_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 19 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_19_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34819">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_19_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 19 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_19_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40219">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_19_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_19_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 19 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_19_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40319">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_20_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 20 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_20_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29420">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_20_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 20 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_20_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34820">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_20_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 20 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_20_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40220">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_20_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_20_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 20 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_20_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40320">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_21_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 21 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_21_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29421">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_21_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 21 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_21_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34821">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_21_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 21 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_21_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40221">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_21_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_21_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 21 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_21_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40321">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_22_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 22 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_22_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29422">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_22_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 22 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_22_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34822">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_22_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 22 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_22_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40222">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_22_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_22_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 22 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_22_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40322">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_23_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 23 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_23_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29423">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_23_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 23 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_23_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34823">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_23_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 23 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_23_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40223">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_23_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_23_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 23 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_23_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40323">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_24_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 24 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_24_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29424">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_24_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 24 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_24_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34824">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_24_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 24 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_24_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40224">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_24_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_24_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 24 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_24_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40324">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_25_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 25 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_25_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29425">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_25_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 25 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_25_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34825">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_25_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 25 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_25_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40225">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_25_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_25_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 25 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_25_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40325">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_26_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 26 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_26_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29426">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_26_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 26 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_26_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34826">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_26_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 26 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_26_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40226">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_26_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_26_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 26 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_26_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40326">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_27_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 27 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_27_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29427">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_27_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 27 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_27_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34827">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_27_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 27 DIRECTION</spirit:displayName>
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- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_27_DIRECTION">false</xilinx:isEnabled>
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- <spirit:name>PCW_MIO_27_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 27 SLEW</spirit:displayName>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_28_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 28 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_28_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29428">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_28_IOTYPE</spirit:name>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_28_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34828">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_28_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 28 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_28_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40228">inout</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_28_DIRECTION">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_28_SLEW</spirit:name>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_28_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40328">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_29_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 29 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_29_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29429">enabled</spirit:value>
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- <spirit:name>PCW_MIO_29_IOTYPE</spirit:name>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_29_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34829">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_29_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 29 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_29_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40229">in</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_29_DIRECTION">false</xilinx:isEnabled>
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- <spirit:name>PCW_MIO_29_SLEW</spirit:name>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_29_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40329">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_30_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 30 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_30_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29430">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_30_IOTYPE</spirit:name>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_30_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34830">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_30_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 30 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_30_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40230">out</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_30_DIRECTION">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_30_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 30 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_30_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40330">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_31_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 31 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_31_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29431">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_31_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 31 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_31_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34831">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_31_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 31 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_31_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40231">in</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_31_DIRECTION">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_31_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 31 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_31_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40331">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_32_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 32 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_32_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29432">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_32_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 32 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_32_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34832">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_32_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 32 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_32_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40232">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_32_DIRECTION">false</xilinx:isEnabled>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_32_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 32 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_32_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40332">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_33_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 33 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_33_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29433">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_33_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 33 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_33_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34833">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_33_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 33 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_33_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40233">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_33_DIRECTION">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_33_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 33 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_33_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40333">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_34_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 34 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_34_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29434">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_34_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 34 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_34_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34834">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_34_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 34 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_34_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40234">inout</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_34_DIRECTION">false</xilinx:isEnabled>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_34_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 34 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_34_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40334">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_35_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 35 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_35_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29435">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_35_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 35 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_35_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34835">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_35_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 35 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_35_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40235">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_35_DIRECTION">false</xilinx:isEnabled>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_35_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 35 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_35_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40335">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_36_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 36 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_36_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29436">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_36_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 36 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_36_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34836">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_36_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 36 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_36_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40236">in</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_36_DIRECTION">false</xilinx:isEnabled>
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- <spirit:name>PCW_MIO_36_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 36 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_36_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40336">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_37_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 37 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_37_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29437">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_37_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 37 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_37_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34837">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_37_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 37 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_37_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40237">inout</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_37_DIRECTION">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_37_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 37 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_37_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40337">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_38_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 38 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_38_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29438">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_38_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 38 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_38_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34838">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_38_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 38 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_38_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40238">inout</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_38_DIRECTION">false</xilinx:isEnabled>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_38_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 38 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_38_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40338">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_39_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 39 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_39_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29439">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_39_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 39 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_39_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34839">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_39_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 39 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_39_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40239">inout</spirit:value>
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- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_39_DIRECTION">false</xilinx:isEnabled>
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- <spirit:name>PCW_MIO_39_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 39 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_39_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40339">slow</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_40_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 40 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_40_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29440">enabled</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_40_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 40 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_40_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34840">LVCMOS 2.5V</spirit:value>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_40_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 40 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_40_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40240">inout</spirit:value>
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- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_40_DIRECTION">false</xilinx:isEnabled>
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- </spirit:vendorExtensions>
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- <spirit:parameter>
- <spirit:name>PCW_MIO_40_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 40 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_40_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40340">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_41_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 41 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_41_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29441">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_41_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 41 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_41_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34841">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_41_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 41 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_41_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40241">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_41_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_41_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 41 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_41_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40341">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_42_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 42 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_42_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29442">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_42_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 42 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_42_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34842">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_42_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 42 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_42_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40242">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_42_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_42_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 42 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_42_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40342">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_43_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 43 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_43_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29443">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_43_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 43 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_43_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34843">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_43_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 43 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_43_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40243">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_43_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_43_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 43 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_43_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40343">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_44_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 44 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_44_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29444">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_44_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 44 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_44_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34844">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_44_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 44 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_44_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40244">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_44_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_44_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 44 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_44_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40344">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_45_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 45 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_45_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29445">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_45_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 45 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_45_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34845">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_45_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 45 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_45_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40245">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_45_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_45_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 45 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_45_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40345">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_46_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 46 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_46_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29446">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_46_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 46 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_46_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34846">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_46_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 46 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_46_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40246">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_46_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_46_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 46 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_46_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40346">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_47_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 47 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_47_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29447">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_47_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 47 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_47_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34847">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_47_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 47 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_47_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40247">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_47_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_47_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 47 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_47_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40347">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_48_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 48 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_48_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29448">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_48_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 48 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_48_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34848">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_48_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 48 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_48_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40248">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_48_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_48_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 48 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_48_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40348">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_49_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 49 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_49_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29449">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_49_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 49 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_49_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34849">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_49_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 49 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_49_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40249">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_49_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_49_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 49 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_49_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40349">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_50_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 50 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_50_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29450">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_50_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 50 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_50_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34850">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_50_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 50 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_50_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40250">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_50_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_50_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 50 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_50_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40350">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_51_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 51 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_51_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29451">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_51_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 51 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_51_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34851">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_51_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 51 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_51_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40251">inout</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_51_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_51_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 51 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_51_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40351">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_52_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 52 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_52_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29452">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_52_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 52 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_52_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34852">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_52_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 52 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_52_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40252">out</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_52_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_52_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 52 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_52_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40352">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_53_PULLUP</spirit:name>
- <spirit:displayName>PCW MIO 53 PULLUP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_53_PULLUP" spirit:choiceRef="choice_list_2d7daef4" spirit:order="29453">enabled</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_53_IOTYPE</spirit:name>
- <spirit:displayName>PCW MIO 53 IOTYPE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_53_IOTYPE" spirit:choiceRef="choice_list_d388ceb0" spirit:order="34853">LVCMOS 2.5V</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_53_DIRECTION</spirit:name>
- <spirit:displayName>PCW MIO 53 DIRECTION</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_53_DIRECTION" spirit:choiceRef="choice_list_95a9da0c" spirit:order="40253">in</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.PCW_MIO_53_DIRECTION">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_53_SLEW</spirit:name>
- <spirit:displayName>PCW MIO 53 SLEW</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_53_SLEW" spirit:choiceRef="choice_list_86458347" spirit:order="40353">slow</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>preset</spirit:name>
- <spirit:displayName>preset</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.preset" spirit:choiceRef="choice_list_9e358632" spirit:order="40354">None</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_UIPARAM_GENERATE_SUMMARY</spirit:name>
- <spirit:displayName>PCW UIPARAM GENERATE SUMMARY</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_GENERATE_SUMMARY" spirit:order="210001">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_TREE_PERIPHERALS</spirit:name>
- <spirit:displayName>PCW MIO TREE PERIPHERALS</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_TREE_PERIPHERALS" spirit:order="210000">GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#SPI 0#UART 0#UART 0#UART 1#UART 1#I2C 0#I2C 0#CAN 1#CAN 1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_MIO_TREE_SIGNALS</spirit:name>
- <spirit:displayName>PCW MIO TREE SIGNALS</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_MIO_TREE_SIGNALS" spirit:order="220000">gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PS7_SI_REV</spirit:name>
- <spirit:displayName>PCW PS7 SI REV</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PS7_SI_REV" spirit:choiceRef="choice_list_bed41605" spirit:order="49300">PRODUCTION</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FPGA_FCLK0_ENABLE</spirit:name>
- <spirit:displayName>PCW FPGA FCLK0 ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FPGA_FCLK0_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="63001">1</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FPGA_FCLK0_ENABLE" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK0_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK0_PORT)) == 1)) ">true</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FPGA_FCLK1_ENABLE</spirit:name>
- <spirit:displayName>PCW FPGA FCLK1 ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FPGA_FCLK1_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="63101">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FPGA_FCLK1_ENABLE" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK1_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK1_PORT)) == 1)) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FPGA_FCLK2_ENABLE</spirit:name>
- <spirit:displayName>PCW FPGA FCLK2 ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FPGA_FCLK2_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="63201">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FPGA_FCLK2_ENABLE" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK2_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK2_PORT)) == 1)) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_FPGA_FCLK3_ENABLE</spirit:name>
- <spirit:displayName>PCW FPGA FCLK3 ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FPGA_FCLK3_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="63301">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.PCW_FPGA_FCLK3_ENABLE" xilinx:dependency="((spirit:decode(id(PARAM_VALUE.PCW_CLK3_FREQ)) > 0)&&(spirit:decode(id(PARAM_VALUE.PCW_EN_CLK3_PORT)) == 1)) ">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS0_T_TR</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS0 T TR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_TR" spirit:order="3531">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS0_T_PC</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS0 T PC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_PC" spirit:order="3532">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS0_T_WP</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS0 T WP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WP" spirit:order="3533">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS0_T_CEOE</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS0 T CEOE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_CEOE" spirit:order="3534">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS0_T_WC</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS0 T WC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WC" spirit:order="3535">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS0_T_RC</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS0 T RC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_RC" spirit:order="3536">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS0_WE_TIME</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS0 WE TIME</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS0_WE_TIME" spirit:order="3537">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS1_T_TR</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS1 T TR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_TR" spirit:order="3538">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS1_T_PC</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS1 T PC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_PC" spirit:order="3539">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS1_T_WP</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS1 T WP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WP" spirit:order="3540">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS1_T_CEOE</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS1 T CEOE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_CEOE" spirit:order="3541">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS1_T_WC</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS1 T WC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WC" spirit:order="3542">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS1_T_RC</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS1 T RC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_RC" spirit:order="3543">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_SRAM_CS1_WE_TIME</spirit:name>
- <spirit:displayName>PCW NOR SRAM CS1 WE TIME</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_SRAM_CS1_WE_TIME" spirit:order="3544">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS0_T_TR</spirit:name>
- <spirit:displayName>PCW NOR CS0 T TR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS0_T_TR" spirit:order="3545">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS0_T_PC</spirit:name>
- <spirit:displayName>PCW NOR CS0 T PC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS0_T_PC" spirit:order="3546">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS0_T_WP</spirit:name>
- <spirit:displayName>PCW NOR CS0 T WP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS0_T_WP" spirit:order="3547">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS0_T_CEOE</spirit:name>
- <spirit:displayName>PCW NOR CS0 T CEOE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS0_T_CEOE" spirit:order="3548">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS0_T_WC</spirit:name>
- <spirit:displayName>PCW NOR CS0 T WC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS0_T_WC" spirit:order="3549">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS0_T_RC</spirit:name>
- <spirit:displayName>PCW NOR CS0 T RC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS0_T_RC" spirit:order="3550">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS0_WE_TIME</spirit:name>
- <spirit:displayName>PCW NOR CS0 WE TIME</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS0_WE_TIME" spirit:order="3551">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS1_T_TR</spirit:name>
- <spirit:displayName>PCW NOR CS1 T TR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS1_T_TR" spirit:order="3552">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS1_T_PC</spirit:name>
- <spirit:displayName>PCW NOR CS1 T PC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS1_T_PC" spirit:order="3553">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS1_T_WP</spirit:name>
- <spirit:displayName>PCW NOR CS1 T WP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS1_T_WP" spirit:order="3554">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS1_T_CEOE</spirit:name>
- <spirit:displayName>PCW NOR CS1 T CEOE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS1_T_CEOE" spirit:order="3555">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS1_T_WC</spirit:name>
- <spirit:displayName>PCW NOR CS1 T WC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS1_T_WC" spirit:order="3556">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS1_T_RC</spirit:name>
- <spirit:displayName>PCW NOR CS1 T RC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS1_T_RC" spirit:order="3557">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NOR_CS1_WE_TIME</spirit:name>
- <spirit:displayName>PCW NOR CS1 WE TIME</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NOR_CS1_WE_TIME" spirit:order="3558">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_CYCLES_T_RR</spirit:name>
- <spirit:displayName>PCW NAND CYCLES T RR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_CYCLES_T_RR" spirit:order="3559">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_CYCLES_T_AR</spirit:name>
- <spirit:displayName>PCW NAND CYCLES T AR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_CYCLES_T_AR" spirit:order="3560">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_CYCLES_T_CLR</spirit:name>
- <spirit:displayName>PCW NAND CYCLES T CLR</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_CYCLES_T_CLR" spirit:order="3561">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_CYCLES_T_WP</spirit:name>
- <spirit:displayName>PCW NAND CYCLES T WP</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_CYCLES_T_WP" spirit:order="3562">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_CYCLES_T_REA</spirit:name>
- <spirit:displayName>PCW NAND CYCLES T REA</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_CYCLES_T_REA" spirit:order="3563">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_CYCLES_T_WC</spirit:name>
- <spirit:displayName>PCW NAND CYCLES T WC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_CYCLES_T_WC" spirit:order="3564">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_NAND_CYCLES_T_RC</spirit:name>
- <spirit:displayName>PCW NAND CYCLES T RC</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_NAND_CYCLES_T_RC" spirit:order="3565">11</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_CYCLE_T0</spirit:name>
- <spirit:displayName>PCW SMC CYCLE T0</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_CYCLE_T0" spirit:order="3566">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_CYCLE_T1</spirit:name>
- <spirit:displayName>PCW SMC CYCLE T1</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_CYCLE_T1" spirit:order="3567">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_CYCLE_T2</spirit:name>
- <spirit:displayName>PCW SMC CYCLE T2</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_CYCLE_T2" spirit:order="3568">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_CYCLE_T3</spirit:name>
- <spirit:displayName>PCW SMC CYCLE T3</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_CYCLE_T3" spirit:order="3569">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_CYCLE_T4</spirit:name>
- <spirit:displayName>PCW SMC CYCLE T4</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_CYCLE_T4" spirit:order="3570">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_CYCLE_T5</spirit:name>
- <spirit:displayName>PCW SMC CYCLE T5</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_CYCLE_T5" spirit:order="3571">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_SMC_CYCLE_T6</spirit:name>
- <spirit:displayName>PCW SMC CYCLE T6</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_SMC_CYCLE_T6" spirit:order="3572">NA</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PACKAGE_NAME</spirit:name>
- <spirit:displayName>PCW PACKAGE NAME</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PACKAGE_NAME" spirit:choiceRef="choice_list_a0c775a9" spirit:order="11">clg485</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>PCW_PLL_BYPASSMODE_ENABLE</spirit:name>
- <spirit:displayName>PCW PLL BYPASSMODE ENABLE</spirit:displayName>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_PLL_BYPASSMODE_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="1800">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">scalp_zynqps_processing_system7_0_0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:coreExtensions>
- <xilinx:displayName>ZYNQ7 Processing System</xilinx:displayName>
- <xilinx:systemCLibraries>
- <xilinx:systemCLibrary>remote_port_c_v4</xilinx:systemCLibrary>
- <xilinx:systemCLibrary>remote_port_sc_v4</xilinx:systemCLibrary>
- <xilinx:systemCLibrary>xtlm</xilinx:systemCLibrary>
- </xilinx:systemCLibraries>
- <xilinx:coreRevision>6</xilinx:coreRevision>
- <xilinx:requiresVIP>true</xilinx:requiresVIP>
- <xilinx:configElementInfos>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.AXI_ARBITRATION_SCHEME" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.BURST_LENGTH" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.CAN_DEBUG" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.CAS_LATENCY" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.CAS_WRITE_LATENCY" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.CS_ENABLED" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.CUSTOM_PARTS" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.DATA_MASK_ENABLED" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.DATA_WIDTH" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.MEMORY_PART" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.MEMORY_TYPE" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.MEM_ADDR_MAP" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.SLOT" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.DDR.TIMEPERIOD_PS" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.CLK_DOMAIN" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
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- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_A25_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS0_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_NUM_F2P_INTR_INPUTS" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_PRESET_BANK1_VOLTAGE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_IO1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SS1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_QSPI_QSPI_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_POW_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_GRP_WP_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SD1_SD1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_VALID" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SINGLE_QSPI_DATA_MODE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI0_SPI0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI1_SPI1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_VALID" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_FREQMHZ" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_GRP_FULL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART0_UART0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_GRP_FULL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART1_UART1_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_DIVISOR0" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_VALID" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_ACT_DDR_FREQ_MHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BANK_ADDR_COUNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BL" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BUS_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CL" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_COL_ADDR_COUNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CWL" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DEVICE_CAPACITY" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DRAM_WIDTH" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ECC" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_FREQ_MHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_MEMORY_TYPE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_PARTNO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ROW_ADDR_COUNT" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_SPEED_BIN" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_FAW" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RAS_MIN" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RC" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RCD" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RP" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_FREQMHZ" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB0_USB0_IO" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB1_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_ENABLE" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PCW_USB_RESET_SELECT" xilinx:valueSource="user"/>
- </xilinx:configElementInfos>
- </xilinx:coreExtensions>
- <xilinx:packagingInfo>
- <xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
- </xilinx:packagingInfo>
- </spirit:vendorExtensions>
-</spirit:component>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.v
deleted file mode 100644
index 272122970e7e3768b595a9b368f84f3032029115..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.v
+++ /dev/null
@@ -1,5232 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:39 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.v
-// Design : scalp_zynqps_processing_system7_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module scalp_zynqps_processing_system7_0_0
- (SPI1_SCLK_I,
- SPI1_SCLK_O,
- SPI1_SCLK_T,
- SPI1_MOSI_I,
- SPI1_MOSI_O,
- SPI1_MOSI_T,
- SPI1_MISO_I,
- SPI1_MISO_O,
- SPI1_MISO_T,
- SPI1_SS_I,
- SPI1_SS_O,
- SPI1_SS1_O,
- SPI1_SS2_O,
- SPI1_SS_T,
- USB0_PORT_INDCTL,
- USB0_VBUS_PWRSELECT,
- USB0_VBUS_PWRFAULT,
- M_AXI_GP0_ARVALID,
- M_AXI_GP0_AWVALID,
- M_AXI_GP0_BREADY,
- M_AXI_GP0_RREADY,
- M_AXI_GP0_WLAST,
- M_AXI_GP0_WVALID,
- M_AXI_GP0_ARID,
- M_AXI_GP0_AWID,
- M_AXI_GP0_WID,
- M_AXI_GP0_ARBURST,
- M_AXI_GP0_ARLOCK,
- M_AXI_GP0_ARSIZE,
- M_AXI_GP0_AWBURST,
- M_AXI_GP0_AWLOCK,
- M_AXI_GP0_AWSIZE,
- M_AXI_GP0_ARPROT,
- M_AXI_GP0_AWPROT,
- M_AXI_GP0_ARADDR,
- M_AXI_GP0_AWADDR,
- M_AXI_GP0_WDATA,
- M_AXI_GP0_ARCACHE,
- M_AXI_GP0_ARLEN,
- M_AXI_GP0_ARQOS,
- M_AXI_GP0_AWCACHE,
- M_AXI_GP0_AWLEN,
- M_AXI_GP0_AWQOS,
- M_AXI_GP0_WSTRB,
- M_AXI_GP0_ACLK,
- M_AXI_GP0_ARREADY,
- M_AXI_GP0_AWREADY,
- M_AXI_GP0_BVALID,
- M_AXI_GP0_RLAST,
- M_AXI_GP0_RVALID,
- M_AXI_GP0_WREADY,
- M_AXI_GP0_BID,
- M_AXI_GP0_RID,
- M_AXI_GP0_BRESP,
- M_AXI_GP0_RRESP,
- M_AXI_GP0_RDATA,
- FCLK_CLK0,
- FCLK_RESET0_N,
- MIO,
- DDR_CAS_n,
- DDR_CKE,
- DDR_Clk_n,
- DDR_Clk,
- DDR_CS_n,
- DDR_DRSTB,
- DDR_ODT,
- DDR_RAS_n,
- DDR_WEB,
- DDR_BankAddr,
- DDR_Addr,
- DDR_VRN,
- DDR_VRP,
- DDR_DM,
- DDR_DQ,
- DDR_DQS_n,
- DDR_DQS,
- PS_SRSTB,
- PS_CLK,
- PS_PORB);
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) input SPI1_SCLK_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) output SPI1_SCLK_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) output SPI1_SCLK_T;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) input SPI1_MOSI_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) output SPI1_MOSI_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) output SPI1_MOSI_T;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) input SPI1_MISO_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) output SPI1_MISO_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) output SPI1_MISO_T;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) input SPI1_SS_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) output SPI1_SS_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) output SPI1_SS1_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) output SPI1_SS2_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) output SPI1_SS_T;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
- (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input M_AXI_GP0_ACLK;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 125000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA;
- (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
- (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
-
- wire [14:0]DDR_Addr;
- wire [2:0]DDR_BankAddr;
- wire DDR_CAS_n;
- wire DDR_CKE;
- wire DDR_CS_n;
- wire DDR_Clk;
- wire DDR_Clk_n;
- wire [3:0]DDR_DM;
- wire [31:0]DDR_DQ;
- wire [3:0]DDR_DQS;
- wire [3:0]DDR_DQS_n;
- wire DDR_DRSTB;
- wire DDR_ODT;
- wire DDR_RAS_n;
- wire DDR_VRN;
- wire DDR_VRP;
- wire DDR_WEB;
- wire FCLK_CLK0;
- wire FCLK_RESET0_N;
- wire [53:0]MIO;
- wire M_AXI_GP0_ACLK;
- wire [31:0]M_AXI_GP0_ARADDR;
- wire [1:0]M_AXI_GP0_ARBURST;
- wire [3:0]M_AXI_GP0_ARCACHE;
- wire [11:0]M_AXI_GP0_ARID;
- wire [3:0]M_AXI_GP0_ARLEN;
- wire [1:0]M_AXI_GP0_ARLOCK;
- wire [2:0]M_AXI_GP0_ARPROT;
- wire [3:0]M_AXI_GP0_ARQOS;
- wire M_AXI_GP0_ARREADY;
- wire [2:0]M_AXI_GP0_ARSIZE;
- wire M_AXI_GP0_ARVALID;
- wire [31:0]M_AXI_GP0_AWADDR;
- wire [1:0]M_AXI_GP0_AWBURST;
- wire [3:0]M_AXI_GP0_AWCACHE;
- wire [11:0]M_AXI_GP0_AWID;
- wire [3:0]M_AXI_GP0_AWLEN;
- wire [1:0]M_AXI_GP0_AWLOCK;
- wire [2:0]M_AXI_GP0_AWPROT;
- wire [3:0]M_AXI_GP0_AWQOS;
- wire M_AXI_GP0_AWREADY;
- wire [2:0]M_AXI_GP0_AWSIZE;
- wire M_AXI_GP0_AWVALID;
- wire [11:0]M_AXI_GP0_BID;
- wire M_AXI_GP0_BREADY;
- wire [1:0]M_AXI_GP0_BRESP;
- wire M_AXI_GP0_BVALID;
- wire [31:0]M_AXI_GP0_RDATA;
- wire [11:0]M_AXI_GP0_RID;
- wire M_AXI_GP0_RLAST;
- wire M_AXI_GP0_RREADY;
- wire [1:0]M_AXI_GP0_RRESP;
- wire M_AXI_GP0_RVALID;
- wire [31:0]M_AXI_GP0_WDATA;
- wire [11:0]M_AXI_GP0_WID;
- wire M_AXI_GP0_WLAST;
- wire M_AXI_GP0_WREADY;
- wire [3:0]M_AXI_GP0_WSTRB;
- wire M_AXI_GP0_WVALID;
- wire PS_CLK;
- wire PS_PORB;
- wire PS_SRSTB;
- wire SPI1_MISO_I;
- wire SPI1_MISO_O;
- wire SPI1_MISO_T;
- wire SPI1_MOSI_I;
- wire SPI1_MOSI_O;
- wire SPI1_MOSI_T;
- wire SPI1_SCLK_I;
- wire SPI1_SCLK_O;
- wire SPI1_SCLK_T;
- wire SPI1_SS1_O;
- wire SPI1_SS2_O;
- wire SPI1_SS_I;
- wire SPI1_SS_O;
- wire SPI1_SS_T;
- wire [1:0]USB0_PORT_INDCTL;
- wire USB0_VBUS_PWRFAULT;
- wire USB0_VBUS_PWRSELECT;
- wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
- wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
- wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA0_RSTN_UNCONNECTED;
- wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA1_RSTN_UNCONNECTED;
- wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA2_RSTN_UNCONNECTED;
- wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA3_RSTN_UNCONNECTED;
- wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
- wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
- wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
- wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
- wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
- wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
- wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
- wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
- wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
- wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
- wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
- wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
- wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
- wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
- wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
- wire NLW_inst_FCLK_CLK1_UNCONNECTED;
- wire NLW_inst_FCLK_CLK2_UNCONNECTED;
- wire NLW_inst_FCLK_CLK3_UNCONNECTED;
- wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
- wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
- wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
- wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
- wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
- wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
- wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
- wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
- wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
- wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
- wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
- wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
- wire NLW_inst_PJTAG_TDO_UNCONNECTED;
- wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
- wire NLW_inst_SDIO0_CLK_UNCONNECTED;
- wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
- wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
- wire NLW_inst_SDIO0_LED_UNCONNECTED;
- wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
- wire NLW_inst_SDIO1_CLK_UNCONNECTED;
- wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
- wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
- wire NLW_inst_SDIO1_LED_UNCONNECTED;
- wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
- wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
- wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
- wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
- wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
- wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
- wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
- wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
- wire NLW_inst_SPI0_SS_O_UNCONNECTED;
- wire NLW_inst_SPI0_SS_T_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
- wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
- wire NLW_inst_TRACE_CTL_UNCONNECTED;
- wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
- wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
- wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
- wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
- wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
- wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
- wire NLW_inst_UART0_DTRN_UNCONNECTED;
- wire NLW_inst_UART0_RTSN_UNCONNECTED;
- wire NLW_inst_UART0_TX_UNCONNECTED;
- wire NLW_inst_UART1_DTRN_UNCONNECTED;
- wire NLW_inst_UART1_RTSN_UNCONNECTED;
- wire NLW_inst_UART1_TX_UNCONNECTED;
- wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
- wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
- wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
- wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
- wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
- wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
- wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
- wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
- wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
- wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
- wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
- wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
- wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
- wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
- wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
- wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
- wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
- wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
- wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
- wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
- wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
- wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
- wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
- wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
- wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
-
- (* C_DM_WIDTH = "4" *)
- (* C_DQS_WIDTH = "4" *)
- (* C_DQ_WIDTH = "32" *)
- (* C_EMIO_GPIO_WIDTH = "64" *)
- (* C_EN_EMIO_ENET0 = "0" *)
- (* C_EN_EMIO_ENET1 = "0" *)
- (* C_EN_EMIO_PJTAG = "0" *)
- (* C_EN_EMIO_TRACE = "0" *)
- (* C_FCLK_CLK0_BUF = "TRUE" *)
- (* C_FCLK_CLK1_BUF = "FALSE" *)
- (* C_FCLK_CLK2_BUF = "FALSE" *)
- (* C_FCLK_CLK3_BUF = "FALSE" *)
- (* C_GP0_EN_MODIFIABLE_TXN = "1" *)
- (* C_GP1_EN_MODIFIABLE_TXN = "1" *)
- (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
- (* C_INCLUDE_TRACE_BUFFER = "0" *)
- (* C_IRQ_F2P_MODE = "DIRECT" *)
- (* C_MIO_PRIMITIVE = "54" *)
- (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
- (* C_M_AXI_GP0_ID_WIDTH = "12" *)
- (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
- (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
- (* C_M_AXI_GP1_ID_WIDTH = "12" *)
- (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
- (* C_NUM_F2P_INTR_INPUTS = "1" *)
- (* C_PACKAGE_NAME = "clg485" *)
- (* C_PS7_SI_REV = "PRODUCTION" *)
- (* C_S_AXI_ACP_ARUSER_VAL = "31" *)
- (* C_S_AXI_ACP_AWUSER_VAL = "31" *)
- (* C_S_AXI_ACP_ID_WIDTH = "3" *)
- (* C_S_AXI_GP0_ID_WIDTH = "6" *)
- (* C_S_AXI_GP1_ID_WIDTH = "6" *)
- (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP0_ID_WIDTH = "6" *)
- (* C_S_AXI_HP1_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP1_ID_WIDTH = "6" *)
- (* C_S_AXI_HP2_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP2_ID_WIDTH = "6" *)
- (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP3_ID_WIDTH = "6" *)
- (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
- (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
- (* C_TRACE_INTERNAL_WIDTH = "2" *)
- (* C_TRACE_PIPELINE_WIDTH = "8" *)
- (* C_USE_AXI_NONSECURE = "0" *)
- (* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
- (* C_USE_M_AXI_GP0 = "1" *)
- (* C_USE_M_AXI_GP1 = "0" *)
- (* C_USE_S_AXI_ACP = "0" *)
- (* C_USE_S_AXI_GP0 = "0" *)
- (* C_USE_S_AXI_GP1 = "0" *)
- (* C_USE_S_AXI_HP0 = "0" *)
- (* C_USE_S_AXI_HP1 = "0" *)
- (* C_USE_S_AXI_HP2 = "0" *)
- (* C_USE_S_AXI_HP3 = "0" *)
- (* HW_HANDOFF = "scalp_zynqps_processing_system7_0_0.hwdef" *)
- (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={750} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SPI} ioStandard={} bidis={2} ioBank={} clockFreq={159.090912} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS25} bidis={5} ioBank={Vcco_p1} clockFreq={159.090912} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={97.222221} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={133} usageRate={0.5} /><PLL domain={Processor} vco={1500.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1750.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>" *)
- (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
- scalp_zynqps_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
- (.CAN0_PHY_RX(1'b0),
- .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
- .CAN1_PHY_RX(1'b0),
- .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
- .Core0_nFIQ(1'b0),
- .Core0_nIRQ(1'b0),
- .Core1_nFIQ(1'b0),
- .Core1_nIRQ(1'b0),
- .DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
- .DDR_Addr(DDR_Addr),
- .DDR_BankAddr(DDR_BankAddr),
- .DDR_CAS_n(DDR_CAS_n),
- .DDR_CKE(DDR_CKE),
- .DDR_CS_n(DDR_CS_n),
- .DDR_Clk(DDR_Clk),
- .DDR_Clk_n(DDR_Clk_n),
- .DDR_DM(DDR_DM),
- .DDR_DQ(DDR_DQ),
- .DDR_DQS(DDR_DQS),
- .DDR_DQS_n(DDR_DQS_n),
- .DDR_DRSTB(DDR_DRSTB),
- .DDR_ODT(DDR_ODT),
- .DDR_RAS_n(DDR_RAS_n),
- .DDR_VRN(DDR_VRN),
- .DDR_VRP(DDR_VRP),
- .DDR_WEB(DDR_WEB),
- .DMA0_ACLK(1'b0),
- .DMA0_DAREADY(1'b0),
- .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
- .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
- .DMA0_DRLAST(1'b0),
- .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
- .DMA0_DRTYPE({1'b0,1'b0}),
- .DMA0_DRVALID(1'b0),
- .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
- .DMA1_ACLK(1'b0),
- .DMA1_DAREADY(1'b0),
- .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
- .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
- .DMA1_DRLAST(1'b0),
- .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
- .DMA1_DRTYPE({1'b0,1'b0}),
- .DMA1_DRVALID(1'b0),
- .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
- .DMA2_ACLK(1'b0),
- .DMA2_DAREADY(1'b0),
- .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
- .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
- .DMA2_DRLAST(1'b0),
- .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
- .DMA2_DRTYPE({1'b0,1'b0}),
- .DMA2_DRVALID(1'b0),
- .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
- .DMA3_ACLK(1'b0),
- .DMA3_DAREADY(1'b0),
- .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
- .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
- .DMA3_DRLAST(1'b0),
- .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
- .DMA3_DRTYPE({1'b0,1'b0}),
- .DMA3_DRVALID(1'b0),
- .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
- .ENET0_EXT_INTIN(1'b0),
- .ENET0_GMII_COL(1'b0),
- .ENET0_GMII_CRS(1'b0),
- .ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ENET0_GMII_RX_CLK(1'b0),
- .ENET0_GMII_RX_DV(1'b0),
- .ENET0_GMII_RX_ER(1'b0),
- .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
- .ENET0_GMII_TX_CLK(1'b0),
- .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
- .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
- .ENET0_MDIO_I(1'b0),
- .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
- .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
- .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
- .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
- .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
- .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
- .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
- .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
- .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
- .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
- .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
- .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
- .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
- .ENET1_EXT_INTIN(1'b0),
- .ENET1_GMII_COL(1'b0),
- .ENET1_GMII_CRS(1'b0),
- .ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ENET1_GMII_RX_CLK(1'b0),
- .ENET1_GMII_RX_DV(1'b0),
- .ENET1_GMII_RX_ER(1'b0),
- .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
- .ENET1_GMII_TX_CLK(1'b0),
- .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
- .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
- .ENET1_MDIO_I(1'b0),
- .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
- .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
- .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
- .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
- .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
- .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
- .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
- .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
- .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
- .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
- .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
- .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
- .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
- .EVENT_EVENTI(1'b0),
- .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
- .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
- .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
- .FCLK_CLK0(FCLK_CLK0),
- .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
- .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
- .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
- .FCLK_CLKTRIG0_N(1'b0),
- .FCLK_CLKTRIG1_N(1'b0),
- .FCLK_CLKTRIG2_N(1'b0),
- .FCLK_CLKTRIG3_N(1'b0),
- .FCLK_RESET0_N(FCLK_RESET0_N),
- .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
- .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
- .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
- .FPGA_IDLE_N(1'b0),
- .FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
- .FTMD_TRACEIN_CLK(1'b0),
- .FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .FTMD_TRACEIN_VALID(1'b0),
- .FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
- .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
- .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
- .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
- .FTMT_F2P_TRIG_0(1'b0),
- .FTMT_F2P_TRIG_1(1'b0),
- .FTMT_F2P_TRIG_2(1'b0),
- .FTMT_F2P_TRIG_3(1'b0),
- .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
- .FTMT_P2F_TRIGACK_0(1'b0),
- .FTMT_P2F_TRIGACK_1(1'b0),
- .FTMT_P2F_TRIGACK_2(1'b0),
- .FTMT_P2F_TRIGACK_3(1'b0),
- .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
- .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
- .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
- .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
- .GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
- .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
- .I2C0_SCL_I(1'b0),
- .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
- .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
- .I2C0_SDA_I(1'b0),
- .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
- .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
- .I2C1_SCL_I(1'b0),
- .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
- .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
- .I2C1_SDA_I(1'b0),
- .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
- .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
- .IRQ_F2P(1'b0),
- .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
- .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
- .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
- .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
- .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
- .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
- .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
- .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
- .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
- .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
- .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
- .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
- .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
- .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
- .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
- .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
- .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
- .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
- .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
- .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
- .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
- .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
- .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
- .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
- .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
- .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
- .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
- .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
- .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
- .MIO(MIO),
- .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
- .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
- .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
- .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
- .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
- .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
- .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
- .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
- .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
- .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
- .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
- .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
- .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
- .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
- .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
- .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
- .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
- .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
- .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
- .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
- .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
- .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
- .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
- .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
- .M_AXI_GP0_BID(M_AXI_GP0_BID),
- .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
- .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
- .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
- .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
- .M_AXI_GP0_RID(M_AXI_GP0_RID),
- .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
- .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
- .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
- .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
- .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
- .M_AXI_GP0_WID(M_AXI_GP0_WID),
- .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
- .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
- .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
- .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
- .M_AXI_GP1_ACLK(1'b0),
- .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
- .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
- .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
- .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
- .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
- .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
- .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
- .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
- .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
- .M_AXI_GP1_ARREADY(1'b0),
- .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
- .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
- .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
- .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
- .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
- .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
- .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
- .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
- .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
- .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
- .M_AXI_GP1_AWREADY(1'b0),
- .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
- .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
- .M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
- .M_AXI_GP1_BRESP({1'b0,1'b0}),
- .M_AXI_GP1_BVALID(1'b0),
- .M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .M_AXI_GP1_RLAST(1'b0),
- .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
- .M_AXI_GP1_RRESP({1'b0,1'b0}),
- .M_AXI_GP1_RVALID(1'b0),
- .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
- .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
- .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
- .M_AXI_GP1_WREADY(1'b0),
- .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
- .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
- .PJTAG_TCK(1'b0),
- .PJTAG_TDI(1'b0),
- .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
- .PJTAG_TMS(1'b0),
- .PS_CLK(PS_CLK),
- .PS_PORB(PS_PORB),
- .PS_SRSTB(PS_SRSTB),
- .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
- .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
- .SDIO0_CDN(1'b0),
- .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
- .SDIO0_CLK_FB(1'b0),
- .SDIO0_CMD_I(1'b0),
- .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
- .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
- .SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
- .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
- .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
- .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
- .SDIO0_WP(1'b0),
- .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
- .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
- .SDIO1_CDN(1'b0),
- .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
- .SDIO1_CLK_FB(1'b0),
- .SDIO1_CMD_I(1'b0),
- .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
- .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
- .SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
- .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
- .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
- .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
- .SDIO1_WP(1'b0),
- .SPI0_MISO_I(1'b0),
- .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
- .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
- .SPI0_MOSI_I(1'b0),
- .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
- .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
- .SPI0_SCLK_I(1'b0),
- .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
- .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
- .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
- .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
- .SPI0_SS_I(1'b0),
- .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
- .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
- .SPI1_MISO_I(SPI1_MISO_I),
- .SPI1_MISO_O(SPI1_MISO_O),
- .SPI1_MISO_T(SPI1_MISO_T),
- .SPI1_MOSI_I(SPI1_MOSI_I),
- .SPI1_MOSI_O(SPI1_MOSI_O),
- .SPI1_MOSI_T(SPI1_MOSI_T),
- .SPI1_SCLK_I(SPI1_SCLK_I),
- .SPI1_SCLK_O(SPI1_SCLK_O),
- .SPI1_SCLK_T(SPI1_SCLK_T),
- .SPI1_SS1_O(SPI1_SS1_O),
- .SPI1_SS2_O(SPI1_SS2_O),
- .SPI1_SS_I(SPI1_SS_I),
- .SPI1_SS_O(SPI1_SS_O),
- .SPI1_SS_T(SPI1_SS_T),
- .SRAM_INTIN(1'b0),
- .S_AXI_ACP_ACLK(1'b0),
- .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARBURST({1'b0,1'b0}),
- .S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
- .S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARLOCK({1'b0,1'b0}),
- .S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
- .S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARVALID(1'b0),
- .S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWBURST({1'b0,1'b0}),
- .S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWLOCK({1'b0,1'b0}),
- .S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
- .S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWVALID(1'b0),
- .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
- .S_AXI_ACP_BREADY(1'b0),
- .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
- .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
- .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
- .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
- .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
- .S_AXI_ACP_RREADY(1'b0),
- .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
- .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
- .S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_WLAST(1'b0),
- .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
- .S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_WVALID(1'b0),
- .S_AXI_GP0_ACLK(1'b0),
- .S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARBURST({1'b0,1'b0}),
- .S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
- .S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARLOCK({1'b0,1'b0}),
- .S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
- .S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARVALID(1'b0),
- .S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWBURST({1'b0,1'b0}),
- .S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWLOCK({1'b0,1'b0}),
- .S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
- .S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWVALID(1'b0),
- .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
- .S_AXI_GP0_BREADY(1'b0),
- .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
- .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
- .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
- .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
- .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
- .S_AXI_GP0_RREADY(1'b0),
- .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
- .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
- .S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_WLAST(1'b0),
- .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
- .S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_WVALID(1'b0),
- .S_AXI_GP1_ACLK(1'b0),
- .S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARBURST({1'b0,1'b0}),
- .S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
- .S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARLOCK({1'b0,1'b0}),
- .S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
- .S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARVALID(1'b0),
- .S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWBURST({1'b0,1'b0}),
- .S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWLOCK({1'b0,1'b0}),
- .S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
- .S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWVALID(1'b0),
- .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
- .S_AXI_GP1_BREADY(1'b0),
- .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
- .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
- .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
- .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
- .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
- .S_AXI_GP1_RREADY(1'b0),
- .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
- .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
- .S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_WLAST(1'b0),
- .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
- .S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_WVALID(1'b0),
- .S_AXI_HP0_ACLK(1'b0),
- .S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARBURST({1'b0,1'b0}),
- .S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
- .S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
- .S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARVALID(1'b0),
- .S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWBURST({1'b0,1'b0}),
- .S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
- .S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWVALID(1'b0),
- .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
- .S_AXI_HP0_BREADY(1'b0),
- .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
- .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP0_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
- .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
- .S_AXI_HP0_RREADY(1'b0),
- .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
- .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_WLAST(1'b0),
- .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
- .S_AXI_HP0_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_WVALID(1'b0),
- .S_AXI_HP1_ACLK(1'b0),
- .S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARBURST({1'b0,1'b0}),
- .S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
- .S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
- .S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARVALID(1'b0),
- .S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWBURST({1'b0,1'b0}),
- .S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
- .S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWVALID(1'b0),
- .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
- .S_AXI_HP1_BREADY(1'b0),
- .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
- .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP1_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
- .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
- .S_AXI_HP1_RREADY(1'b0),
- .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
- .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_WLAST(1'b0),
- .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
- .S_AXI_HP1_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_WVALID(1'b0),
- .S_AXI_HP2_ACLK(1'b0),
- .S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARBURST({1'b0,1'b0}),
- .S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
- .S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
- .S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARVALID(1'b0),
- .S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWBURST({1'b0,1'b0}),
- .S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
- .S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWVALID(1'b0),
- .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
- .S_AXI_HP2_BREADY(1'b0),
- .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
- .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP2_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
- .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
- .S_AXI_HP2_RREADY(1'b0),
- .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
- .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_WLAST(1'b0),
- .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
- .S_AXI_HP2_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_WVALID(1'b0),
- .S_AXI_HP3_ACLK(1'b0),
- .S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARBURST({1'b0,1'b0}),
- .S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
- .S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
- .S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARVALID(1'b0),
- .S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWBURST({1'b0,1'b0}),
- .S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
- .S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWVALID(1'b0),
- .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
- .S_AXI_HP3_BREADY(1'b0),
- .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
- .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP3_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
- .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
- .S_AXI_HP3_RREADY(1'b0),
- .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
- .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_WLAST(1'b0),
- .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
- .S_AXI_HP3_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_WVALID(1'b0),
- .TRACE_CLK(1'b0),
- .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
- .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
- .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
- .TTC0_CLK0_IN(1'b0),
- .TTC0_CLK1_IN(1'b0),
- .TTC0_CLK2_IN(1'b0),
- .TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
- .TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
- .TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
- .TTC1_CLK0_IN(1'b0),
- .TTC1_CLK1_IN(1'b0),
- .TTC1_CLK2_IN(1'b0),
- .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
- .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
- .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
- .UART0_CTSN(1'b0),
- .UART0_DCDN(1'b0),
- .UART0_DSRN(1'b0),
- .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
- .UART0_RIN(1'b0),
- .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
- .UART0_RX(1'b1),
- .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
- .UART1_CTSN(1'b0),
- .UART1_DCDN(1'b0),
- .UART1_DSRN(1'b0),
- .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
- .UART1_RIN(1'b0),
- .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
- .UART1_RX(1'b1),
- .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
- .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
- .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
- .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
- .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
- .USB1_VBUS_PWRFAULT(1'b0),
- .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
- .WDT_CLK_IN(1'b0),
- .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
-endmodule
-
-(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
-(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
-(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
-(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
-(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
-(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
-(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
-(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
-(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg485" *) (* C_PS7_SI_REV = "PRODUCTION" *)
-(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
-(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
-(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
-(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
-(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
-(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
-(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
-(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
-(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
-(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "scalp_zynqps_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
-(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={750} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SPI} ioStandard={} bidis={2} ioBank={} clockFreq={159.090912} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS25} bidis={5} ioBank={Vcco_p1} clockFreq={159.090912} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={97.222221} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={133} usageRate={0.5} /><PLL domain={Processor} vco={1500.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1750.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
-module scalp_zynqps_processing_system7_0_0_processing_system7_v5_5_processing_system7
- (CAN0_PHY_TX,
- CAN0_PHY_RX,
- CAN1_PHY_TX,
- CAN1_PHY_RX,
- ENET0_GMII_TX_EN,
- ENET0_GMII_TX_ER,
- ENET0_MDIO_MDC,
- ENET0_MDIO_O,
- ENET0_MDIO_T,
- ENET0_PTP_DELAY_REQ_RX,
- ENET0_PTP_DELAY_REQ_TX,
- ENET0_PTP_PDELAY_REQ_RX,
- ENET0_PTP_PDELAY_REQ_TX,
- ENET0_PTP_PDELAY_RESP_RX,
- ENET0_PTP_PDELAY_RESP_TX,
- ENET0_PTP_SYNC_FRAME_RX,
- ENET0_PTP_SYNC_FRAME_TX,
- ENET0_SOF_RX,
- ENET0_SOF_TX,
- ENET0_GMII_TXD,
- ENET0_GMII_COL,
- ENET0_GMII_CRS,
- ENET0_GMII_RX_CLK,
- ENET0_GMII_RX_DV,
- ENET0_GMII_RX_ER,
- ENET0_GMII_TX_CLK,
- ENET0_MDIO_I,
- ENET0_EXT_INTIN,
- ENET0_GMII_RXD,
- ENET1_GMII_TX_EN,
- ENET1_GMII_TX_ER,
- ENET1_MDIO_MDC,
- ENET1_MDIO_O,
- ENET1_MDIO_T,
- ENET1_PTP_DELAY_REQ_RX,
- ENET1_PTP_DELAY_REQ_TX,
- ENET1_PTP_PDELAY_REQ_RX,
- ENET1_PTP_PDELAY_REQ_TX,
- ENET1_PTP_PDELAY_RESP_RX,
- ENET1_PTP_PDELAY_RESP_TX,
- ENET1_PTP_SYNC_FRAME_RX,
- ENET1_PTP_SYNC_FRAME_TX,
- ENET1_SOF_RX,
- ENET1_SOF_TX,
- ENET1_GMII_TXD,
- ENET1_GMII_COL,
- ENET1_GMII_CRS,
- ENET1_GMII_RX_CLK,
- ENET1_GMII_RX_DV,
- ENET1_GMII_RX_ER,
- ENET1_GMII_TX_CLK,
- ENET1_MDIO_I,
- ENET1_EXT_INTIN,
- ENET1_GMII_RXD,
- GPIO_I,
- GPIO_O,
- GPIO_T,
- I2C0_SDA_I,
- I2C0_SDA_O,
- I2C0_SDA_T,
- I2C0_SCL_I,
- I2C0_SCL_O,
- I2C0_SCL_T,
- I2C1_SDA_I,
- I2C1_SDA_O,
- I2C1_SDA_T,
- I2C1_SCL_I,
- I2C1_SCL_O,
- I2C1_SCL_T,
- PJTAG_TCK,
- PJTAG_TMS,
- PJTAG_TDI,
- PJTAG_TDO,
- SDIO0_CLK,
- SDIO0_CLK_FB,
- SDIO0_CMD_O,
- SDIO0_CMD_I,
- SDIO0_CMD_T,
- SDIO0_DATA_I,
- SDIO0_DATA_O,
- SDIO0_DATA_T,
- SDIO0_LED,
- SDIO0_CDN,
- SDIO0_WP,
- SDIO0_BUSPOW,
- SDIO0_BUSVOLT,
- SDIO1_CLK,
- SDIO1_CLK_FB,
- SDIO1_CMD_O,
- SDIO1_CMD_I,
- SDIO1_CMD_T,
- SDIO1_DATA_I,
- SDIO1_DATA_O,
- SDIO1_DATA_T,
- SDIO1_LED,
- SDIO1_CDN,
- SDIO1_WP,
- SDIO1_BUSPOW,
- SDIO1_BUSVOLT,
- SPI0_SCLK_I,
- SPI0_SCLK_O,
- SPI0_SCLK_T,
- SPI0_MOSI_I,
- SPI0_MOSI_O,
- SPI0_MOSI_T,
- SPI0_MISO_I,
- SPI0_MISO_O,
- SPI0_MISO_T,
- SPI0_SS_I,
- SPI0_SS_O,
- SPI0_SS1_O,
- SPI0_SS2_O,
- SPI0_SS_T,
- SPI1_SCLK_I,
- SPI1_SCLK_O,
- SPI1_SCLK_T,
- SPI1_MOSI_I,
- SPI1_MOSI_O,
- SPI1_MOSI_T,
- SPI1_MISO_I,
- SPI1_MISO_O,
- SPI1_MISO_T,
- SPI1_SS_I,
- SPI1_SS_O,
- SPI1_SS1_O,
- SPI1_SS2_O,
- SPI1_SS_T,
- UART0_DTRN,
- UART0_RTSN,
- UART0_TX,
- UART0_CTSN,
- UART0_DCDN,
- UART0_DSRN,
- UART0_RIN,
- UART0_RX,
- UART1_DTRN,
- UART1_RTSN,
- UART1_TX,
- UART1_CTSN,
- UART1_DCDN,
- UART1_DSRN,
- UART1_RIN,
- UART1_RX,
- TTC0_WAVE0_OUT,
- TTC0_WAVE1_OUT,
- TTC0_WAVE2_OUT,
- TTC0_CLK0_IN,
- TTC0_CLK1_IN,
- TTC0_CLK2_IN,
- TTC1_WAVE0_OUT,
- TTC1_WAVE1_OUT,
- TTC1_WAVE2_OUT,
- TTC1_CLK0_IN,
- TTC1_CLK1_IN,
- TTC1_CLK2_IN,
- WDT_CLK_IN,
- WDT_RST_OUT,
- TRACE_CLK,
- TRACE_CTL,
- TRACE_DATA,
- TRACE_CLK_OUT,
- USB0_PORT_INDCTL,
- USB0_VBUS_PWRSELECT,
- USB0_VBUS_PWRFAULT,
- USB1_PORT_INDCTL,
- USB1_VBUS_PWRSELECT,
- USB1_VBUS_PWRFAULT,
- SRAM_INTIN,
- M_AXI_GP0_ARESETN,
- M_AXI_GP0_ARVALID,
- M_AXI_GP0_AWVALID,
- M_AXI_GP0_BREADY,
- M_AXI_GP0_RREADY,
- M_AXI_GP0_WLAST,
- M_AXI_GP0_WVALID,
- M_AXI_GP0_ARID,
- M_AXI_GP0_AWID,
- M_AXI_GP0_WID,
- M_AXI_GP0_ARBURST,
- M_AXI_GP0_ARLOCK,
- M_AXI_GP0_ARSIZE,
- M_AXI_GP0_AWBURST,
- M_AXI_GP0_AWLOCK,
- M_AXI_GP0_AWSIZE,
- M_AXI_GP0_ARPROT,
- M_AXI_GP0_AWPROT,
- M_AXI_GP0_ARADDR,
- M_AXI_GP0_AWADDR,
- M_AXI_GP0_WDATA,
- M_AXI_GP0_ARCACHE,
- M_AXI_GP0_ARLEN,
- M_AXI_GP0_ARQOS,
- M_AXI_GP0_AWCACHE,
- M_AXI_GP0_AWLEN,
- M_AXI_GP0_AWQOS,
- M_AXI_GP0_WSTRB,
- M_AXI_GP0_ACLK,
- M_AXI_GP0_ARREADY,
- M_AXI_GP0_AWREADY,
- M_AXI_GP0_BVALID,
- M_AXI_GP0_RLAST,
- M_AXI_GP0_RVALID,
- M_AXI_GP0_WREADY,
- M_AXI_GP0_BID,
- M_AXI_GP0_RID,
- M_AXI_GP0_BRESP,
- M_AXI_GP0_RRESP,
- M_AXI_GP0_RDATA,
- M_AXI_GP1_ARESETN,
- M_AXI_GP1_ARVALID,
- M_AXI_GP1_AWVALID,
- M_AXI_GP1_BREADY,
- M_AXI_GP1_RREADY,
- M_AXI_GP1_WLAST,
- M_AXI_GP1_WVALID,
- M_AXI_GP1_ARID,
- M_AXI_GP1_AWID,
- M_AXI_GP1_WID,
- M_AXI_GP1_ARBURST,
- M_AXI_GP1_ARLOCK,
- M_AXI_GP1_ARSIZE,
- M_AXI_GP1_AWBURST,
- M_AXI_GP1_AWLOCK,
- M_AXI_GP1_AWSIZE,
- M_AXI_GP1_ARPROT,
- M_AXI_GP1_AWPROT,
- M_AXI_GP1_ARADDR,
- M_AXI_GP1_AWADDR,
- M_AXI_GP1_WDATA,
- M_AXI_GP1_ARCACHE,
- M_AXI_GP1_ARLEN,
- M_AXI_GP1_ARQOS,
- M_AXI_GP1_AWCACHE,
- M_AXI_GP1_AWLEN,
- M_AXI_GP1_AWQOS,
- M_AXI_GP1_WSTRB,
- M_AXI_GP1_ACLK,
- M_AXI_GP1_ARREADY,
- M_AXI_GP1_AWREADY,
- M_AXI_GP1_BVALID,
- M_AXI_GP1_RLAST,
- M_AXI_GP1_RVALID,
- M_AXI_GP1_WREADY,
- M_AXI_GP1_BID,
- M_AXI_GP1_RID,
- M_AXI_GP1_BRESP,
- M_AXI_GP1_RRESP,
- M_AXI_GP1_RDATA,
- S_AXI_GP0_ARESETN,
- S_AXI_GP0_ARREADY,
- S_AXI_GP0_AWREADY,
- S_AXI_GP0_BVALID,
- S_AXI_GP0_RLAST,
- S_AXI_GP0_RVALID,
- S_AXI_GP0_WREADY,
- S_AXI_GP0_BRESP,
- S_AXI_GP0_RRESP,
- S_AXI_GP0_RDATA,
- S_AXI_GP0_BID,
- S_AXI_GP0_RID,
- S_AXI_GP0_ACLK,
- S_AXI_GP0_ARVALID,
- S_AXI_GP0_AWVALID,
- S_AXI_GP0_BREADY,
- S_AXI_GP0_RREADY,
- S_AXI_GP0_WLAST,
- S_AXI_GP0_WVALID,
- S_AXI_GP0_ARBURST,
- S_AXI_GP0_ARLOCK,
- S_AXI_GP0_ARSIZE,
- S_AXI_GP0_AWBURST,
- S_AXI_GP0_AWLOCK,
- S_AXI_GP0_AWSIZE,
- S_AXI_GP0_ARPROT,
- S_AXI_GP0_AWPROT,
- S_AXI_GP0_ARADDR,
- S_AXI_GP0_AWADDR,
- S_AXI_GP0_WDATA,
- S_AXI_GP0_ARCACHE,
- S_AXI_GP0_ARLEN,
- S_AXI_GP0_ARQOS,
- S_AXI_GP0_AWCACHE,
- S_AXI_GP0_AWLEN,
- S_AXI_GP0_AWQOS,
- S_AXI_GP0_WSTRB,
- S_AXI_GP0_ARID,
- S_AXI_GP0_AWID,
- S_AXI_GP0_WID,
- S_AXI_GP1_ARESETN,
- S_AXI_GP1_ARREADY,
- S_AXI_GP1_AWREADY,
- S_AXI_GP1_BVALID,
- S_AXI_GP1_RLAST,
- S_AXI_GP1_RVALID,
- S_AXI_GP1_WREADY,
- S_AXI_GP1_BRESP,
- S_AXI_GP1_RRESP,
- S_AXI_GP1_RDATA,
- S_AXI_GP1_BID,
- S_AXI_GP1_RID,
- S_AXI_GP1_ACLK,
- S_AXI_GP1_ARVALID,
- S_AXI_GP1_AWVALID,
- S_AXI_GP1_BREADY,
- S_AXI_GP1_RREADY,
- S_AXI_GP1_WLAST,
- S_AXI_GP1_WVALID,
- S_AXI_GP1_ARBURST,
- S_AXI_GP1_ARLOCK,
- S_AXI_GP1_ARSIZE,
- S_AXI_GP1_AWBURST,
- S_AXI_GP1_AWLOCK,
- S_AXI_GP1_AWSIZE,
- S_AXI_GP1_ARPROT,
- S_AXI_GP1_AWPROT,
- S_AXI_GP1_ARADDR,
- S_AXI_GP1_AWADDR,
- S_AXI_GP1_WDATA,
- S_AXI_GP1_ARCACHE,
- S_AXI_GP1_ARLEN,
- S_AXI_GP1_ARQOS,
- S_AXI_GP1_AWCACHE,
- S_AXI_GP1_AWLEN,
- S_AXI_GP1_AWQOS,
- S_AXI_GP1_WSTRB,
- S_AXI_GP1_ARID,
- S_AXI_GP1_AWID,
- S_AXI_GP1_WID,
- S_AXI_ACP_ARESETN,
- S_AXI_ACP_ARREADY,
- S_AXI_ACP_AWREADY,
- S_AXI_ACP_BVALID,
- S_AXI_ACP_RLAST,
- S_AXI_ACP_RVALID,
- S_AXI_ACP_WREADY,
- S_AXI_ACP_BRESP,
- S_AXI_ACP_RRESP,
- S_AXI_ACP_BID,
- S_AXI_ACP_RID,
- S_AXI_ACP_RDATA,
- S_AXI_ACP_ACLK,
- S_AXI_ACP_ARVALID,
- S_AXI_ACP_AWVALID,
- S_AXI_ACP_BREADY,
- S_AXI_ACP_RREADY,
- S_AXI_ACP_WLAST,
- S_AXI_ACP_WVALID,
- S_AXI_ACP_ARID,
- S_AXI_ACP_ARPROT,
- S_AXI_ACP_AWID,
- S_AXI_ACP_AWPROT,
- S_AXI_ACP_WID,
- S_AXI_ACP_ARADDR,
- S_AXI_ACP_AWADDR,
- S_AXI_ACP_ARCACHE,
- S_AXI_ACP_ARLEN,
- S_AXI_ACP_ARQOS,
- S_AXI_ACP_AWCACHE,
- S_AXI_ACP_AWLEN,
- S_AXI_ACP_AWQOS,
- S_AXI_ACP_ARBURST,
- S_AXI_ACP_ARLOCK,
- S_AXI_ACP_ARSIZE,
- S_AXI_ACP_AWBURST,
- S_AXI_ACP_AWLOCK,
- S_AXI_ACP_AWSIZE,
- S_AXI_ACP_ARUSER,
- S_AXI_ACP_AWUSER,
- S_AXI_ACP_WDATA,
- S_AXI_ACP_WSTRB,
- S_AXI_HP0_ARESETN,
- S_AXI_HP0_ARREADY,
- S_AXI_HP0_AWREADY,
- S_AXI_HP0_BVALID,
- S_AXI_HP0_RLAST,
- S_AXI_HP0_RVALID,
- S_AXI_HP0_WREADY,
- S_AXI_HP0_BRESP,
- S_AXI_HP0_RRESP,
- S_AXI_HP0_BID,
- S_AXI_HP0_RID,
- S_AXI_HP0_RDATA,
- S_AXI_HP0_RCOUNT,
- S_AXI_HP0_WCOUNT,
- S_AXI_HP0_RACOUNT,
- S_AXI_HP0_WACOUNT,
- S_AXI_HP0_ACLK,
- S_AXI_HP0_ARVALID,
- S_AXI_HP0_AWVALID,
- S_AXI_HP0_BREADY,
- S_AXI_HP0_RDISSUECAP1_EN,
- S_AXI_HP0_RREADY,
- S_AXI_HP0_WLAST,
- S_AXI_HP0_WRISSUECAP1_EN,
- S_AXI_HP0_WVALID,
- S_AXI_HP0_ARBURST,
- S_AXI_HP0_ARLOCK,
- S_AXI_HP0_ARSIZE,
- S_AXI_HP0_AWBURST,
- S_AXI_HP0_AWLOCK,
- S_AXI_HP0_AWSIZE,
- S_AXI_HP0_ARPROT,
- S_AXI_HP0_AWPROT,
- S_AXI_HP0_ARADDR,
- S_AXI_HP0_AWADDR,
- S_AXI_HP0_ARCACHE,
- S_AXI_HP0_ARLEN,
- S_AXI_HP0_ARQOS,
- S_AXI_HP0_AWCACHE,
- S_AXI_HP0_AWLEN,
- S_AXI_HP0_AWQOS,
- S_AXI_HP0_ARID,
- S_AXI_HP0_AWID,
- S_AXI_HP0_WID,
- S_AXI_HP0_WDATA,
- S_AXI_HP0_WSTRB,
- S_AXI_HP1_ARESETN,
- S_AXI_HP1_ARREADY,
- S_AXI_HP1_AWREADY,
- S_AXI_HP1_BVALID,
- S_AXI_HP1_RLAST,
- S_AXI_HP1_RVALID,
- S_AXI_HP1_WREADY,
- S_AXI_HP1_BRESP,
- S_AXI_HP1_RRESP,
- S_AXI_HP1_BID,
- S_AXI_HP1_RID,
- S_AXI_HP1_RDATA,
- S_AXI_HP1_RCOUNT,
- S_AXI_HP1_WCOUNT,
- S_AXI_HP1_RACOUNT,
- S_AXI_HP1_WACOUNT,
- S_AXI_HP1_ACLK,
- S_AXI_HP1_ARVALID,
- S_AXI_HP1_AWVALID,
- S_AXI_HP1_BREADY,
- S_AXI_HP1_RDISSUECAP1_EN,
- S_AXI_HP1_RREADY,
- S_AXI_HP1_WLAST,
- S_AXI_HP1_WRISSUECAP1_EN,
- S_AXI_HP1_WVALID,
- S_AXI_HP1_ARBURST,
- S_AXI_HP1_ARLOCK,
- S_AXI_HP1_ARSIZE,
- S_AXI_HP1_AWBURST,
- S_AXI_HP1_AWLOCK,
- S_AXI_HP1_AWSIZE,
- S_AXI_HP1_ARPROT,
- S_AXI_HP1_AWPROT,
- S_AXI_HP1_ARADDR,
- S_AXI_HP1_AWADDR,
- S_AXI_HP1_ARCACHE,
- S_AXI_HP1_ARLEN,
- S_AXI_HP1_ARQOS,
- S_AXI_HP1_AWCACHE,
- S_AXI_HP1_AWLEN,
- S_AXI_HP1_AWQOS,
- S_AXI_HP1_ARID,
- S_AXI_HP1_AWID,
- S_AXI_HP1_WID,
- S_AXI_HP1_WDATA,
- S_AXI_HP1_WSTRB,
- S_AXI_HP2_ARESETN,
- S_AXI_HP2_ARREADY,
- S_AXI_HP2_AWREADY,
- S_AXI_HP2_BVALID,
- S_AXI_HP2_RLAST,
- S_AXI_HP2_RVALID,
- S_AXI_HP2_WREADY,
- S_AXI_HP2_BRESP,
- S_AXI_HP2_RRESP,
- S_AXI_HP2_BID,
- S_AXI_HP2_RID,
- S_AXI_HP2_RDATA,
- S_AXI_HP2_RCOUNT,
- S_AXI_HP2_WCOUNT,
- S_AXI_HP2_RACOUNT,
- S_AXI_HP2_WACOUNT,
- S_AXI_HP2_ACLK,
- S_AXI_HP2_ARVALID,
- S_AXI_HP2_AWVALID,
- S_AXI_HP2_BREADY,
- S_AXI_HP2_RDISSUECAP1_EN,
- S_AXI_HP2_RREADY,
- S_AXI_HP2_WLAST,
- S_AXI_HP2_WRISSUECAP1_EN,
- S_AXI_HP2_WVALID,
- S_AXI_HP2_ARBURST,
- S_AXI_HP2_ARLOCK,
- S_AXI_HP2_ARSIZE,
- S_AXI_HP2_AWBURST,
- S_AXI_HP2_AWLOCK,
- S_AXI_HP2_AWSIZE,
- S_AXI_HP2_ARPROT,
- S_AXI_HP2_AWPROT,
- S_AXI_HP2_ARADDR,
- S_AXI_HP2_AWADDR,
- S_AXI_HP2_ARCACHE,
- S_AXI_HP2_ARLEN,
- S_AXI_HP2_ARQOS,
- S_AXI_HP2_AWCACHE,
- S_AXI_HP2_AWLEN,
- S_AXI_HP2_AWQOS,
- S_AXI_HP2_ARID,
- S_AXI_HP2_AWID,
- S_AXI_HP2_WID,
- S_AXI_HP2_WDATA,
- S_AXI_HP2_WSTRB,
- S_AXI_HP3_ARESETN,
- S_AXI_HP3_ARREADY,
- S_AXI_HP3_AWREADY,
- S_AXI_HP3_BVALID,
- S_AXI_HP3_RLAST,
- S_AXI_HP3_RVALID,
- S_AXI_HP3_WREADY,
- S_AXI_HP3_BRESP,
- S_AXI_HP3_RRESP,
- S_AXI_HP3_BID,
- S_AXI_HP3_RID,
- S_AXI_HP3_RDATA,
- S_AXI_HP3_RCOUNT,
- S_AXI_HP3_WCOUNT,
- S_AXI_HP3_RACOUNT,
- S_AXI_HP3_WACOUNT,
- S_AXI_HP3_ACLK,
- S_AXI_HP3_ARVALID,
- S_AXI_HP3_AWVALID,
- S_AXI_HP3_BREADY,
- S_AXI_HP3_RDISSUECAP1_EN,
- S_AXI_HP3_RREADY,
- S_AXI_HP3_WLAST,
- S_AXI_HP3_WRISSUECAP1_EN,
- S_AXI_HP3_WVALID,
- S_AXI_HP3_ARBURST,
- S_AXI_HP3_ARLOCK,
- S_AXI_HP3_ARSIZE,
- S_AXI_HP3_AWBURST,
- S_AXI_HP3_AWLOCK,
- S_AXI_HP3_AWSIZE,
- S_AXI_HP3_ARPROT,
- S_AXI_HP3_AWPROT,
- S_AXI_HP3_ARADDR,
- S_AXI_HP3_AWADDR,
- S_AXI_HP3_ARCACHE,
- S_AXI_HP3_ARLEN,
- S_AXI_HP3_ARQOS,
- S_AXI_HP3_AWCACHE,
- S_AXI_HP3_AWLEN,
- S_AXI_HP3_AWQOS,
- S_AXI_HP3_ARID,
- S_AXI_HP3_AWID,
- S_AXI_HP3_WID,
- S_AXI_HP3_WDATA,
- S_AXI_HP3_WSTRB,
- IRQ_P2F_DMAC_ABORT,
- IRQ_P2F_DMAC0,
- IRQ_P2F_DMAC1,
- IRQ_P2F_DMAC2,
- IRQ_P2F_DMAC3,
- IRQ_P2F_DMAC4,
- IRQ_P2F_DMAC5,
- IRQ_P2F_DMAC6,
- IRQ_P2F_DMAC7,
- IRQ_P2F_SMC,
- IRQ_P2F_QSPI,
- IRQ_P2F_CTI,
- IRQ_P2F_GPIO,
- IRQ_P2F_USB0,
- IRQ_P2F_ENET0,
- IRQ_P2F_ENET_WAKE0,
- IRQ_P2F_SDIO0,
- IRQ_P2F_I2C0,
- IRQ_P2F_SPI0,
- IRQ_P2F_UART0,
- IRQ_P2F_CAN0,
- IRQ_P2F_USB1,
- IRQ_P2F_ENET1,
- IRQ_P2F_ENET_WAKE1,
- IRQ_P2F_SDIO1,
- IRQ_P2F_I2C1,
- IRQ_P2F_SPI1,
- IRQ_P2F_UART1,
- IRQ_P2F_CAN1,
- IRQ_F2P,
- Core0_nFIQ,
- Core0_nIRQ,
- Core1_nFIQ,
- Core1_nIRQ,
- DMA0_DATYPE,
- DMA0_DAVALID,
- DMA0_DRREADY,
- DMA0_RSTN,
- DMA1_DATYPE,
- DMA1_DAVALID,
- DMA1_DRREADY,
- DMA1_RSTN,
- DMA2_DATYPE,
- DMA2_DAVALID,
- DMA2_DRREADY,
- DMA2_RSTN,
- DMA3_DATYPE,
- DMA3_DAVALID,
- DMA3_DRREADY,
- DMA3_RSTN,
- DMA0_ACLK,
- DMA0_DAREADY,
- DMA0_DRLAST,
- DMA0_DRVALID,
- DMA1_ACLK,
- DMA1_DAREADY,
- DMA1_DRLAST,
- DMA1_DRVALID,
- DMA2_ACLK,
- DMA2_DAREADY,
- DMA2_DRLAST,
- DMA2_DRVALID,
- DMA3_ACLK,
- DMA3_DAREADY,
- DMA3_DRLAST,
- DMA3_DRVALID,
- DMA0_DRTYPE,
- DMA1_DRTYPE,
- DMA2_DRTYPE,
- DMA3_DRTYPE,
- FCLK_CLK3,
- FCLK_CLK2,
- FCLK_CLK1,
- FCLK_CLK0,
- FCLK_CLKTRIG3_N,
- FCLK_CLKTRIG2_N,
- FCLK_CLKTRIG1_N,
- FCLK_CLKTRIG0_N,
- FCLK_RESET3_N,
- FCLK_RESET2_N,
- FCLK_RESET1_N,
- FCLK_RESET0_N,
- FTMD_TRACEIN_DATA,
- FTMD_TRACEIN_VALID,
- FTMD_TRACEIN_CLK,
- FTMD_TRACEIN_ATID,
- FTMT_F2P_TRIG_0,
- FTMT_F2P_TRIGACK_0,
- FTMT_F2P_TRIG_1,
- FTMT_F2P_TRIGACK_1,
- FTMT_F2P_TRIG_2,
- FTMT_F2P_TRIGACK_2,
- FTMT_F2P_TRIG_3,
- FTMT_F2P_TRIGACK_3,
- FTMT_F2P_DEBUG,
- FTMT_P2F_TRIGACK_0,
- FTMT_P2F_TRIG_0,
- FTMT_P2F_TRIGACK_1,
- FTMT_P2F_TRIG_1,
- FTMT_P2F_TRIGACK_2,
- FTMT_P2F_TRIG_2,
- FTMT_P2F_TRIGACK_3,
- FTMT_P2F_TRIG_3,
- FTMT_P2F_DEBUG,
- FPGA_IDLE_N,
- EVENT_EVENTO,
- EVENT_STANDBYWFE,
- EVENT_STANDBYWFI,
- EVENT_EVENTI,
- DDR_ARB,
- MIO,
- DDR_CAS_n,
- DDR_CKE,
- DDR_Clk_n,
- DDR_Clk,
- DDR_CS_n,
- DDR_DRSTB,
- DDR_ODT,
- DDR_RAS_n,
- DDR_WEB,
- DDR_BankAddr,
- DDR_Addr,
- DDR_VRN,
- DDR_VRP,
- DDR_DM,
- DDR_DQ,
- DDR_DQS_n,
- DDR_DQS,
- PS_SRSTB,
- PS_CLK,
- PS_PORB);
- output CAN0_PHY_TX;
- input CAN0_PHY_RX;
- output CAN1_PHY_TX;
- input CAN1_PHY_RX;
- output ENET0_GMII_TX_EN;
- output ENET0_GMII_TX_ER;
- output ENET0_MDIO_MDC;
- output ENET0_MDIO_O;
- output ENET0_MDIO_T;
- output ENET0_PTP_DELAY_REQ_RX;
- output ENET0_PTP_DELAY_REQ_TX;
- output ENET0_PTP_PDELAY_REQ_RX;
- output ENET0_PTP_PDELAY_REQ_TX;
- output ENET0_PTP_PDELAY_RESP_RX;
- output ENET0_PTP_PDELAY_RESP_TX;
- output ENET0_PTP_SYNC_FRAME_RX;
- output ENET0_PTP_SYNC_FRAME_TX;
- output ENET0_SOF_RX;
- output ENET0_SOF_TX;
- output [7:0]ENET0_GMII_TXD;
- input ENET0_GMII_COL;
- input ENET0_GMII_CRS;
- input ENET0_GMII_RX_CLK;
- input ENET0_GMII_RX_DV;
- input ENET0_GMII_RX_ER;
- input ENET0_GMII_TX_CLK;
- input ENET0_MDIO_I;
- input ENET0_EXT_INTIN;
- input [7:0]ENET0_GMII_RXD;
- output ENET1_GMII_TX_EN;
- output ENET1_GMII_TX_ER;
- output ENET1_MDIO_MDC;
- output ENET1_MDIO_O;
- output ENET1_MDIO_T;
- output ENET1_PTP_DELAY_REQ_RX;
- output ENET1_PTP_DELAY_REQ_TX;
- output ENET1_PTP_PDELAY_REQ_RX;
- output ENET1_PTP_PDELAY_REQ_TX;
- output ENET1_PTP_PDELAY_RESP_RX;
- output ENET1_PTP_PDELAY_RESP_TX;
- output ENET1_PTP_SYNC_FRAME_RX;
- output ENET1_PTP_SYNC_FRAME_TX;
- output ENET1_SOF_RX;
- output ENET1_SOF_TX;
- output [7:0]ENET1_GMII_TXD;
- input ENET1_GMII_COL;
- input ENET1_GMII_CRS;
- input ENET1_GMII_RX_CLK;
- input ENET1_GMII_RX_DV;
- input ENET1_GMII_RX_ER;
- input ENET1_GMII_TX_CLK;
- input ENET1_MDIO_I;
- input ENET1_EXT_INTIN;
- input [7:0]ENET1_GMII_RXD;
- input [63:0]GPIO_I;
- output [63:0]GPIO_O;
- output [63:0]GPIO_T;
- input I2C0_SDA_I;
- output I2C0_SDA_O;
- output I2C0_SDA_T;
- input I2C0_SCL_I;
- output I2C0_SCL_O;
- output I2C0_SCL_T;
- input I2C1_SDA_I;
- output I2C1_SDA_O;
- output I2C1_SDA_T;
- input I2C1_SCL_I;
- output I2C1_SCL_O;
- output I2C1_SCL_T;
- input PJTAG_TCK;
- input PJTAG_TMS;
- input PJTAG_TDI;
- output PJTAG_TDO;
- output SDIO0_CLK;
- input SDIO0_CLK_FB;
- output SDIO0_CMD_O;
- input SDIO0_CMD_I;
- output SDIO0_CMD_T;
- input [3:0]SDIO0_DATA_I;
- output [3:0]SDIO0_DATA_O;
- output [3:0]SDIO0_DATA_T;
- output SDIO0_LED;
- input SDIO0_CDN;
- input SDIO0_WP;
- output SDIO0_BUSPOW;
- output [2:0]SDIO0_BUSVOLT;
- output SDIO1_CLK;
- input SDIO1_CLK_FB;
- output SDIO1_CMD_O;
- input SDIO1_CMD_I;
- output SDIO1_CMD_T;
- input [3:0]SDIO1_DATA_I;
- output [3:0]SDIO1_DATA_O;
- output [3:0]SDIO1_DATA_T;
- output SDIO1_LED;
- input SDIO1_CDN;
- input SDIO1_WP;
- output SDIO1_BUSPOW;
- output [2:0]SDIO1_BUSVOLT;
- input SPI0_SCLK_I;
- output SPI0_SCLK_O;
- output SPI0_SCLK_T;
- input SPI0_MOSI_I;
- output SPI0_MOSI_O;
- output SPI0_MOSI_T;
- input SPI0_MISO_I;
- output SPI0_MISO_O;
- output SPI0_MISO_T;
- input SPI0_SS_I;
- output SPI0_SS_O;
- output SPI0_SS1_O;
- output SPI0_SS2_O;
- output SPI0_SS_T;
- input SPI1_SCLK_I;
- output SPI1_SCLK_O;
- output SPI1_SCLK_T;
- input SPI1_MOSI_I;
- output SPI1_MOSI_O;
- output SPI1_MOSI_T;
- input SPI1_MISO_I;
- output SPI1_MISO_O;
- output SPI1_MISO_T;
- input SPI1_SS_I;
- output SPI1_SS_O;
- output SPI1_SS1_O;
- output SPI1_SS2_O;
- output SPI1_SS_T;
- output UART0_DTRN;
- output UART0_RTSN;
- output UART0_TX;
- input UART0_CTSN;
- input UART0_DCDN;
- input UART0_DSRN;
- input UART0_RIN;
- input UART0_RX;
- output UART1_DTRN;
- output UART1_RTSN;
- output UART1_TX;
- input UART1_CTSN;
- input UART1_DCDN;
- input UART1_DSRN;
- input UART1_RIN;
- input UART1_RX;
- output TTC0_WAVE0_OUT;
- output TTC0_WAVE1_OUT;
- output TTC0_WAVE2_OUT;
- input TTC0_CLK0_IN;
- input TTC0_CLK1_IN;
- input TTC0_CLK2_IN;
- output TTC1_WAVE0_OUT;
- output TTC1_WAVE1_OUT;
- output TTC1_WAVE2_OUT;
- input TTC1_CLK0_IN;
- input TTC1_CLK1_IN;
- input TTC1_CLK2_IN;
- input WDT_CLK_IN;
- output WDT_RST_OUT;
- input TRACE_CLK;
- output TRACE_CTL;
- output [1:0]TRACE_DATA;
- output TRACE_CLK_OUT;
- output [1:0]USB0_PORT_INDCTL;
- output USB0_VBUS_PWRSELECT;
- input USB0_VBUS_PWRFAULT;
- output [1:0]USB1_PORT_INDCTL;
- output USB1_VBUS_PWRSELECT;
- input USB1_VBUS_PWRFAULT;
- input SRAM_INTIN;
- output M_AXI_GP0_ARESETN;
- output M_AXI_GP0_ARVALID;
- output M_AXI_GP0_AWVALID;
- output M_AXI_GP0_BREADY;
- output M_AXI_GP0_RREADY;
- output M_AXI_GP0_WLAST;
- output M_AXI_GP0_WVALID;
- output [11:0]M_AXI_GP0_ARID;
- output [11:0]M_AXI_GP0_AWID;
- output [11:0]M_AXI_GP0_WID;
- output [1:0]M_AXI_GP0_ARBURST;
- output [1:0]M_AXI_GP0_ARLOCK;
- output [2:0]M_AXI_GP0_ARSIZE;
- output [1:0]M_AXI_GP0_AWBURST;
- output [1:0]M_AXI_GP0_AWLOCK;
- output [2:0]M_AXI_GP0_AWSIZE;
- output [2:0]M_AXI_GP0_ARPROT;
- output [2:0]M_AXI_GP0_AWPROT;
- output [31:0]M_AXI_GP0_ARADDR;
- output [31:0]M_AXI_GP0_AWADDR;
- output [31:0]M_AXI_GP0_WDATA;
- output [3:0]M_AXI_GP0_ARCACHE;
- output [3:0]M_AXI_GP0_ARLEN;
- output [3:0]M_AXI_GP0_ARQOS;
- output [3:0]M_AXI_GP0_AWCACHE;
- output [3:0]M_AXI_GP0_AWLEN;
- output [3:0]M_AXI_GP0_AWQOS;
- output [3:0]M_AXI_GP0_WSTRB;
- input M_AXI_GP0_ACLK;
- input M_AXI_GP0_ARREADY;
- input M_AXI_GP0_AWREADY;
- input M_AXI_GP0_BVALID;
- input M_AXI_GP0_RLAST;
- input M_AXI_GP0_RVALID;
- input M_AXI_GP0_WREADY;
- input [11:0]M_AXI_GP0_BID;
- input [11:0]M_AXI_GP0_RID;
- input [1:0]M_AXI_GP0_BRESP;
- input [1:0]M_AXI_GP0_RRESP;
- input [31:0]M_AXI_GP0_RDATA;
- output M_AXI_GP1_ARESETN;
- output M_AXI_GP1_ARVALID;
- output M_AXI_GP1_AWVALID;
- output M_AXI_GP1_BREADY;
- output M_AXI_GP1_RREADY;
- output M_AXI_GP1_WLAST;
- output M_AXI_GP1_WVALID;
- output [11:0]M_AXI_GP1_ARID;
- output [11:0]M_AXI_GP1_AWID;
- output [11:0]M_AXI_GP1_WID;
- output [1:0]M_AXI_GP1_ARBURST;
- output [1:0]M_AXI_GP1_ARLOCK;
- output [2:0]M_AXI_GP1_ARSIZE;
- output [1:0]M_AXI_GP1_AWBURST;
- output [1:0]M_AXI_GP1_AWLOCK;
- output [2:0]M_AXI_GP1_AWSIZE;
- output [2:0]M_AXI_GP1_ARPROT;
- output [2:0]M_AXI_GP1_AWPROT;
- output [31:0]M_AXI_GP1_ARADDR;
- output [31:0]M_AXI_GP1_AWADDR;
- output [31:0]M_AXI_GP1_WDATA;
- output [3:0]M_AXI_GP1_ARCACHE;
- output [3:0]M_AXI_GP1_ARLEN;
- output [3:0]M_AXI_GP1_ARQOS;
- output [3:0]M_AXI_GP1_AWCACHE;
- output [3:0]M_AXI_GP1_AWLEN;
- output [3:0]M_AXI_GP1_AWQOS;
- output [3:0]M_AXI_GP1_WSTRB;
- input M_AXI_GP1_ACLK;
- input M_AXI_GP1_ARREADY;
- input M_AXI_GP1_AWREADY;
- input M_AXI_GP1_BVALID;
- input M_AXI_GP1_RLAST;
- input M_AXI_GP1_RVALID;
- input M_AXI_GP1_WREADY;
- input [11:0]M_AXI_GP1_BID;
- input [11:0]M_AXI_GP1_RID;
- input [1:0]M_AXI_GP1_BRESP;
- input [1:0]M_AXI_GP1_RRESP;
- input [31:0]M_AXI_GP1_RDATA;
- output S_AXI_GP0_ARESETN;
- output S_AXI_GP0_ARREADY;
- output S_AXI_GP0_AWREADY;
- output S_AXI_GP0_BVALID;
- output S_AXI_GP0_RLAST;
- output S_AXI_GP0_RVALID;
- output S_AXI_GP0_WREADY;
- output [1:0]S_AXI_GP0_BRESP;
- output [1:0]S_AXI_GP0_RRESP;
- output [31:0]S_AXI_GP0_RDATA;
- output [5:0]S_AXI_GP0_BID;
- output [5:0]S_AXI_GP0_RID;
- input S_AXI_GP0_ACLK;
- input S_AXI_GP0_ARVALID;
- input S_AXI_GP0_AWVALID;
- input S_AXI_GP0_BREADY;
- input S_AXI_GP0_RREADY;
- input S_AXI_GP0_WLAST;
- input S_AXI_GP0_WVALID;
- input [1:0]S_AXI_GP0_ARBURST;
- input [1:0]S_AXI_GP0_ARLOCK;
- input [2:0]S_AXI_GP0_ARSIZE;
- input [1:0]S_AXI_GP0_AWBURST;
- input [1:0]S_AXI_GP0_AWLOCK;
- input [2:0]S_AXI_GP0_AWSIZE;
- input [2:0]S_AXI_GP0_ARPROT;
- input [2:0]S_AXI_GP0_AWPROT;
- input [31:0]S_AXI_GP0_ARADDR;
- input [31:0]S_AXI_GP0_AWADDR;
- input [31:0]S_AXI_GP0_WDATA;
- input [3:0]S_AXI_GP0_ARCACHE;
- input [3:0]S_AXI_GP0_ARLEN;
- input [3:0]S_AXI_GP0_ARQOS;
- input [3:0]S_AXI_GP0_AWCACHE;
- input [3:0]S_AXI_GP0_AWLEN;
- input [3:0]S_AXI_GP0_AWQOS;
- input [3:0]S_AXI_GP0_WSTRB;
- input [5:0]S_AXI_GP0_ARID;
- input [5:0]S_AXI_GP0_AWID;
- input [5:0]S_AXI_GP0_WID;
- output S_AXI_GP1_ARESETN;
- output S_AXI_GP1_ARREADY;
- output S_AXI_GP1_AWREADY;
- output S_AXI_GP1_BVALID;
- output S_AXI_GP1_RLAST;
- output S_AXI_GP1_RVALID;
- output S_AXI_GP1_WREADY;
- output [1:0]S_AXI_GP1_BRESP;
- output [1:0]S_AXI_GP1_RRESP;
- output [31:0]S_AXI_GP1_RDATA;
- output [5:0]S_AXI_GP1_BID;
- output [5:0]S_AXI_GP1_RID;
- input S_AXI_GP1_ACLK;
- input S_AXI_GP1_ARVALID;
- input S_AXI_GP1_AWVALID;
- input S_AXI_GP1_BREADY;
- input S_AXI_GP1_RREADY;
- input S_AXI_GP1_WLAST;
- input S_AXI_GP1_WVALID;
- input [1:0]S_AXI_GP1_ARBURST;
- input [1:0]S_AXI_GP1_ARLOCK;
- input [2:0]S_AXI_GP1_ARSIZE;
- input [1:0]S_AXI_GP1_AWBURST;
- input [1:0]S_AXI_GP1_AWLOCK;
- input [2:0]S_AXI_GP1_AWSIZE;
- input [2:0]S_AXI_GP1_ARPROT;
- input [2:0]S_AXI_GP1_AWPROT;
- input [31:0]S_AXI_GP1_ARADDR;
- input [31:0]S_AXI_GP1_AWADDR;
- input [31:0]S_AXI_GP1_WDATA;
- input [3:0]S_AXI_GP1_ARCACHE;
- input [3:0]S_AXI_GP1_ARLEN;
- input [3:0]S_AXI_GP1_ARQOS;
- input [3:0]S_AXI_GP1_AWCACHE;
- input [3:0]S_AXI_GP1_AWLEN;
- input [3:0]S_AXI_GP1_AWQOS;
- input [3:0]S_AXI_GP1_WSTRB;
- input [5:0]S_AXI_GP1_ARID;
- input [5:0]S_AXI_GP1_AWID;
- input [5:0]S_AXI_GP1_WID;
- output S_AXI_ACP_ARESETN;
- output S_AXI_ACP_ARREADY;
- output S_AXI_ACP_AWREADY;
- output S_AXI_ACP_BVALID;
- output S_AXI_ACP_RLAST;
- output S_AXI_ACP_RVALID;
- output S_AXI_ACP_WREADY;
- output [1:0]S_AXI_ACP_BRESP;
- output [1:0]S_AXI_ACP_RRESP;
- output [2:0]S_AXI_ACP_BID;
- output [2:0]S_AXI_ACP_RID;
- output [63:0]S_AXI_ACP_RDATA;
- input S_AXI_ACP_ACLK;
- input S_AXI_ACP_ARVALID;
- input S_AXI_ACP_AWVALID;
- input S_AXI_ACP_BREADY;
- input S_AXI_ACP_RREADY;
- input S_AXI_ACP_WLAST;
- input S_AXI_ACP_WVALID;
- input [2:0]S_AXI_ACP_ARID;
- input [2:0]S_AXI_ACP_ARPROT;
- input [2:0]S_AXI_ACP_AWID;
- input [2:0]S_AXI_ACP_AWPROT;
- input [2:0]S_AXI_ACP_WID;
- input [31:0]S_AXI_ACP_ARADDR;
- input [31:0]S_AXI_ACP_AWADDR;
- input [3:0]S_AXI_ACP_ARCACHE;
- input [3:0]S_AXI_ACP_ARLEN;
- input [3:0]S_AXI_ACP_ARQOS;
- input [3:0]S_AXI_ACP_AWCACHE;
- input [3:0]S_AXI_ACP_AWLEN;
- input [3:0]S_AXI_ACP_AWQOS;
- input [1:0]S_AXI_ACP_ARBURST;
- input [1:0]S_AXI_ACP_ARLOCK;
- input [2:0]S_AXI_ACP_ARSIZE;
- input [1:0]S_AXI_ACP_AWBURST;
- input [1:0]S_AXI_ACP_AWLOCK;
- input [2:0]S_AXI_ACP_AWSIZE;
- input [4:0]S_AXI_ACP_ARUSER;
- input [4:0]S_AXI_ACP_AWUSER;
- input [63:0]S_AXI_ACP_WDATA;
- input [7:0]S_AXI_ACP_WSTRB;
- output S_AXI_HP0_ARESETN;
- output S_AXI_HP0_ARREADY;
- output S_AXI_HP0_AWREADY;
- output S_AXI_HP0_BVALID;
- output S_AXI_HP0_RLAST;
- output S_AXI_HP0_RVALID;
- output S_AXI_HP0_WREADY;
- output [1:0]S_AXI_HP0_BRESP;
- output [1:0]S_AXI_HP0_RRESP;
- output [5:0]S_AXI_HP0_BID;
- output [5:0]S_AXI_HP0_RID;
- output [63:0]S_AXI_HP0_RDATA;
- output [7:0]S_AXI_HP0_RCOUNT;
- output [7:0]S_AXI_HP0_WCOUNT;
- output [2:0]S_AXI_HP0_RACOUNT;
- output [5:0]S_AXI_HP0_WACOUNT;
- input S_AXI_HP0_ACLK;
- input S_AXI_HP0_ARVALID;
- input S_AXI_HP0_AWVALID;
- input S_AXI_HP0_BREADY;
- input S_AXI_HP0_RDISSUECAP1_EN;
- input S_AXI_HP0_RREADY;
- input S_AXI_HP0_WLAST;
- input S_AXI_HP0_WRISSUECAP1_EN;
- input S_AXI_HP0_WVALID;
- input [1:0]S_AXI_HP0_ARBURST;
- input [1:0]S_AXI_HP0_ARLOCK;
- input [2:0]S_AXI_HP0_ARSIZE;
- input [1:0]S_AXI_HP0_AWBURST;
- input [1:0]S_AXI_HP0_AWLOCK;
- input [2:0]S_AXI_HP0_AWSIZE;
- input [2:0]S_AXI_HP0_ARPROT;
- input [2:0]S_AXI_HP0_AWPROT;
- input [31:0]S_AXI_HP0_ARADDR;
- input [31:0]S_AXI_HP0_AWADDR;
- input [3:0]S_AXI_HP0_ARCACHE;
- input [3:0]S_AXI_HP0_ARLEN;
- input [3:0]S_AXI_HP0_ARQOS;
- input [3:0]S_AXI_HP0_AWCACHE;
- input [3:0]S_AXI_HP0_AWLEN;
- input [3:0]S_AXI_HP0_AWQOS;
- input [5:0]S_AXI_HP0_ARID;
- input [5:0]S_AXI_HP0_AWID;
- input [5:0]S_AXI_HP0_WID;
- input [63:0]S_AXI_HP0_WDATA;
- input [7:0]S_AXI_HP0_WSTRB;
- output S_AXI_HP1_ARESETN;
- output S_AXI_HP1_ARREADY;
- output S_AXI_HP1_AWREADY;
- output S_AXI_HP1_BVALID;
- output S_AXI_HP1_RLAST;
- output S_AXI_HP1_RVALID;
- output S_AXI_HP1_WREADY;
- output [1:0]S_AXI_HP1_BRESP;
- output [1:0]S_AXI_HP1_RRESP;
- output [5:0]S_AXI_HP1_BID;
- output [5:0]S_AXI_HP1_RID;
- output [63:0]S_AXI_HP1_RDATA;
- output [7:0]S_AXI_HP1_RCOUNT;
- output [7:0]S_AXI_HP1_WCOUNT;
- output [2:0]S_AXI_HP1_RACOUNT;
- output [5:0]S_AXI_HP1_WACOUNT;
- input S_AXI_HP1_ACLK;
- input S_AXI_HP1_ARVALID;
- input S_AXI_HP1_AWVALID;
- input S_AXI_HP1_BREADY;
- input S_AXI_HP1_RDISSUECAP1_EN;
- input S_AXI_HP1_RREADY;
- input S_AXI_HP1_WLAST;
- input S_AXI_HP1_WRISSUECAP1_EN;
- input S_AXI_HP1_WVALID;
- input [1:0]S_AXI_HP1_ARBURST;
- input [1:0]S_AXI_HP1_ARLOCK;
- input [2:0]S_AXI_HP1_ARSIZE;
- input [1:0]S_AXI_HP1_AWBURST;
- input [1:0]S_AXI_HP1_AWLOCK;
- input [2:0]S_AXI_HP1_AWSIZE;
- input [2:0]S_AXI_HP1_ARPROT;
- input [2:0]S_AXI_HP1_AWPROT;
- input [31:0]S_AXI_HP1_ARADDR;
- input [31:0]S_AXI_HP1_AWADDR;
- input [3:0]S_AXI_HP1_ARCACHE;
- input [3:0]S_AXI_HP1_ARLEN;
- input [3:0]S_AXI_HP1_ARQOS;
- input [3:0]S_AXI_HP1_AWCACHE;
- input [3:0]S_AXI_HP1_AWLEN;
- input [3:0]S_AXI_HP1_AWQOS;
- input [5:0]S_AXI_HP1_ARID;
- input [5:0]S_AXI_HP1_AWID;
- input [5:0]S_AXI_HP1_WID;
- input [63:0]S_AXI_HP1_WDATA;
- input [7:0]S_AXI_HP1_WSTRB;
- output S_AXI_HP2_ARESETN;
- output S_AXI_HP2_ARREADY;
- output S_AXI_HP2_AWREADY;
- output S_AXI_HP2_BVALID;
- output S_AXI_HP2_RLAST;
- output S_AXI_HP2_RVALID;
- output S_AXI_HP2_WREADY;
- output [1:0]S_AXI_HP2_BRESP;
- output [1:0]S_AXI_HP2_RRESP;
- output [5:0]S_AXI_HP2_BID;
- output [5:0]S_AXI_HP2_RID;
- output [63:0]S_AXI_HP2_RDATA;
- output [7:0]S_AXI_HP2_RCOUNT;
- output [7:0]S_AXI_HP2_WCOUNT;
- output [2:0]S_AXI_HP2_RACOUNT;
- output [5:0]S_AXI_HP2_WACOUNT;
- input S_AXI_HP2_ACLK;
- input S_AXI_HP2_ARVALID;
- input S_AXI_HP2_AWVALID;
- input S_AXI_HP2_BREADY;
- input S_AXI_HP2_RDISSUECAP1_EN;
- input S_AXI_HP2_RREADY;
- input S_AXI_HP2_WLAST;
- input S_AXI_HP2_WRISSUECAP1_EN;
- input S_AXI_HP2_WVALID;
- input [1:0]S_AXI_HP2_ARBURST;
- input [1:0]S_AXI_HP2_ARLOCK;
- input [2:0]S_AXI_HP2_ARSIZE;
- input [1:0]S_AXI_HP2_AWBURST;
- input [1:0]S_AXI_HP2_AWLOCK;
- input [2:0]S_AXI_HP2_AWSIZE;
- input [2:0]S_AXI_HP2_ARPROT;
- input [2:0]S_AXI_HP2_AWPROT;
- input [31:0]S_AXI_HP2_ARADDR;
- input [31:0]S_AXI_HP2_AWADDR;
- input [3:0]S_AXI_HP2_ARCACHE;
- input [3:0]S_AXI_HP2_ARLEN;
- input [3:0]S_AXI_HP2_ARQOS;
- input [3:0]S_AXI_HP2_AWCACHE;
- input [3:0]S_AXI_HP2_AWLEN;
- input [3:0]S_AXI_HP2_AWQOS;
- input [5:0]S_AXI_HP2_ARID;
- input [5:0]S_AXI_HP2_AWID;
- input [5:0]S_AXI_HP2_WID;
- input [63:0]S_AXI_HP2_WDATA;
- input [7:0]S_AXI_HP2_WSTRB;
- output S_AXI_HP3_ARESETN;
- output S_AXI_HP3_ARREADY;
- output S_AXI_HP3_AWREADY;
- output S_AXI_HP3_BVALID;
- output S_AXI_HP3_RLAST;
- output S_AXI_HP3_RVALID;
- output S_AXI_HP3_WREADY;
- output [1:0]S_AXI_HP3_BRESP;
- output [1:0]S_AXI_HP3_RRESP;
- output [5:0]S_AXI_HP3_BID;
- output [5:0]S_AXI_HP3_RID;
- output [63:0]S_AXI_HP3_RDATA;
- output [7:0]S_AXI_HP3_RCOUNT;
- output [7:0]S_AXI_HP3_WCOUNT;
- output [2:0]S_AXI_HP3_RACOUNT;
- output [5:0]S_AXI_HP3_WACOUNT;
- input S_AXI_HP3_ACLK;
- input S_AXI_HP3_ARVALID;
- input S_AXI_HP3_AWVALID;
- input S_AXI_HP3_BREADY;
- input S_AXI_HP3_RDISSUECAP1_EN;
- input S_AXI_HP3_RREADY;
- input S_AXI_HP3_WLAST;
- input S_AXI_HP3_WRISSUECAP1_EN;
- input S_AXI_HP3_WVALID;
- input [1:0]S_AXI_HP3_ARBURST;
- input [1:0]S_AXI_HP3_ARLOCK;
- input [2:0]S_AXI_HP3_ARSIZE;
- input [1:0]S_AXI_HP3_AWBURST;
- input [1:0]S_AXI_HP3_AWLOCK;
- input [2:0]S_AXI_HP3_AWSIZE;
- input [2:0]S_AXI_HP3_ARPROT;
- input [2:0]S_AXI_HP3_AWPROT;
- input [31:0]S_AXI_HP3_ARADDR;
- input [31:0]S_AXI_HP3_AWADDR;
- input [3:0]S_AXI_HP3_ARCACHE;
- input [3:0]S_AXI_HP3_ARLEN;
- input [3:0]S_AXI_HP3_ARQOS;
- input [3:0]S_AXI_HP3_AWCACHE;
- input [3:0]S_AXI_HP3_AWLEN;
- input [3:0]S_AXI_HP3_AWQOS;
- input [5:0]S_AXI_HP3_ARID;
- input [5:0]S_AXI_HP3_AWID;
- input [5:0]S_AXI_HP3_WID;
- input [63:0]S_AXI_HP3_WDATA;
- input [7:0]S_AXI_HP3_WSTRB;
- output IRQ_P2F_DMAC_ABORT;
- output IRQ_P2F_DMAC0;
- output IRQ_P2F_DMAC1;
- output IRQ_P2F_DMAC2;
- output IRQ_P2F_DMAC3;
- output IRQ_P2F_DMAC4;
- output IRQ_P2F_DMAC5;
- output IRQ_P2F_DMAC6;
- output IRQ_P2F_DMAC7;
- output IRQ_P2F_SMC;
- output IRQ_P2F_QSPI;
- output IRQ_P2F_CTI;
- output IRQ_P2F_GPIO;
- output IRQ_P2F_USB0;
- output IRQ_P2F_ENET0;
- output IRQ_P2F_ENET_WAKE0;
- output IRQ_P2F_SDIO0;
- output IRQ_P2F_I2C0;
- output IRQ_P2F_SPI0;
- output IRQ_P2F_UART0;
- output IRQ_P2F_CAN0;
- output IRQ_P2F_USB1;
- output IRQ_P2F_ENET1;
- output IRQ_P2F_ENET_WAKE1;
- output IRQ_P2F_SDIO1;
- output IRQ_P2F_I2C1;
- output IRQ_P2F_SPI1;
- output IRQ_P2F_UART1;
- output IRQ_P2F_CAN1;
- input [0:0]IRQ_F2P;
- input Core0_nFIQ;
- input Core0_nIRQ;
- input Core1_nFIQ;
- input Core1_nIRQ;
- output [1:0]DMA0_DATYPE;
- output DMA0_DAVALID;
- output DMA0_DRREADY;
- output DMA0_RSTN;
- output [1:0]DMA1_DATYPE;
- output DMA1_DAVALID;
- output DMA1_DRREADY;
- output DMA1_RSTN;
- output [1:0]DMA2_DATYPE;
- output DMA2_DAVALID;
- output DMA2_DRREADY;
- output DMA2_RSTN;
- output [1:0]DMA3_DATYPE;
- output DMA3_DAVALID;
- output DMA3_DRREADY;
- output DMA3_RSTN;
- input DMA0_ACLK;
- input DMA0_DAREADY;
- input DMA0_DRLAST;
- input DMA0_DRVALID;
- input DMA1_ACLK;
- input DMA1_DAREADY;
- input DMA1_DRLAST;
- input DMA1_DRVALID;
- input DMA2_ACLK;
- input DMA2_DAREADY;
- input DMA2_DRLAST;
- input DMA2_DRVALID;
- input DMA3_ACLK;
- input DMA3_DAREADY;
- input DMA3_DRLAST;
- input DMA3_DRVALID;
- input [1:0]DMA0_DRTYPE;
- input [1:0]DMA1_DRTYPE;
- input [1:0]DMA2_DRTYPE;
- input [1:0]DMA3_DRTYPE;
- output FCLK_CLK3;
- output FCLK_CLK2;
- output FCLK_CLK1;
- output FCLK_CLK0;
- input FCLK_CLKTRIG3_N;
- input FCLK_CLKTRIG2_N;
- input FCLK_CLKTRIG1_N;
- input FCLK_CLKTRIG0_N;
- output FCLK_RESET3_N;
- output FCLK_RESET2_N;
- output FCLK_RESET1_N;
- output FCLK_RESET0_N;
- input [31:0]FTMD_TRACEIN_DATA;
- input FTMD_TRACEIN_VALID;
- input FTMD_TRACEIN_CLK;
- input [3:0]FTMD_TRACEIN_ATID;
- input FTMT_F2P_TRIG_0;
- output FTMT_F2P_TRIGACK_0;
- input FTMT_F2P_TRIG_1;
- output FTMT_F2P_TRIGACK_1;
- input FTMT_F2P_TRIG_2;
- output FTMT_F2P_TRIGACK_2;
- input FTMT_F2P_TRIG_3;
- output FTMT_F2P_TRIGACK_3;
- input [31:0]FTMT_F2P_DEBUG;
- input FTMT_P2F_TRIGACK_0;
- output FTMT_P2F_TRIG_0;
- input FTMT_P2F_TRIGACK_1;
- output FTMT_P2F_TRIG_1;
- input FTMT_P2F_TRIGACK_2;
- output FTMT_P2F_TRIG_2;
- input FTMT_P2F_TRIGACK_3;
- output FTMT_P2F_TRIG_3;
- output [31:0]FTMT_P2F_DEBUG;
- input FPGA_IDLE_N;
- output EVENT_EVENTO;
- output [1:0]EVENT_STANDBYWFE;
- output [1:0]EVENT_STANDBYWFI;
- input EVENT_EVENTI;
- input [3:0]DDR_ARB;
- inout [53:0]MIO;
- inout DDR_CAS_n;
- inout DDR_CKE;
- inout DDR_Clk_n;
- inout DDR_Clk;
- inout DDR_CS_n;
- inout DDR_DRSTB;
- inout DDR_ODT;
- inout DDR_RAS_n;
- inout DDR_WEB;
- inout [2:0]DDR_BankAddr;
- inout [14:0]DDR_Addr;
- inout DDR_VRN;
- inout DDR_VRP;
- inout [3:0]DDR_DM;
- inout [31:0]DDR_DQ;
- inout [3:0]DDR_DQS_n;
- inout [3:0]DDR_DQS;
- inout PS_SRSTB;
- inout PS_CLK;
- inout PS_PORB;
-
- wire \<const0> ;
- wire \<const1> ;
- wire CAN0_PHY_RX;
- wire CAN0_PHY_TX;
- wire CAN1_PHY_RX;
- wire CAN1_PHY_TX;
- wire Core0_nFIQ;
- wire Core0_nIRQ;
- wire Core1_nFIQ;
- wire Core1_nIRQ;
- wire [3:0]DDR_ARB;
- wire [14:0]DDR_Addr;
- wire [2:0]DDR_BankAddr;
- wire DDR_CAS_n;
- wire DDR_CKE;
- wire DDR_CS_n;
- wire DDR_Clk;
- wire DDR_Clk_n;
- wire [3:0]DDR_DM;
- wire [31:0]DDR_DQ;
- wire [3:0]DDR_DQS;
- wire [3:0]DDR_DQS_n;
- wire DDR_DRSTB;
- wire DDR_ODT;
- wire DDR_RAS_n;
- wire DDR_VRN;
- wire DDR_VRP;
- wire DDR_WEB;
- wire DMA0_ACLK;
- wire DMA0_DAREADY;
- wire [1:0]DMA0_DATYPE;
- wire DMA0_DAVALID;
- wire DMA0_DRLAST;
- wire DMA0_DRREADY;
- wire [1:0]DMA0_DRTYPE;
- wire DMA0_DRVALID;
- wire DMA0_RSTN;
- wire DMA1_ACLK;
- wire DMA1_DAREADY;
- wire [1:0]DMA1_DATYPE;
- wire DMA1_DAVALID;
- wire DMA1_DRLAST;
- wire DMA1_DRREADY;
- wire [1:0]DMA1_DRTYPE;
- wire DMA1_DRVALID;
- wire DMA1_RSTN;
- wire DMA2_ACLK;
- wire DMA2_DAREADY;
- wire [1:0]DMA2_DATYPE;
- wire DMA2_DAVALID;
- wire DMA2_DRLAST;
- wire DMA2_DRREADY;
- wire [1:0]DMA2_DRTYPE;
- wire DMA2_DRVALID;
- wire DMA2_RSTN;
- wire DMA3_ACLK;
- wire DMA3_DAREADY;
- wire [1:0]DMA3_DATYPE;
- wire DMA3_DAVALID;
- wire DMA3_DRLAST;
- wire DMA3_DRREADY;
- wire [1:0]DMA3_DRTYPE;
- wire DMA3_DRVALID;
- wire DMA3_RSTN;
- wire ENET0_EXT_INTIN;
- wire ENET0_GMII_RX_CLK;
- wire ENET0_GMII_TX_CLK;
- wire ENET0_MDIO_I;
- wire ENET0_MDIO_MDC;
- wire ENET0_MDIO_O;
- wire ENET0_MDIO_T;
- wire ENET0_MDIO_T_n;
- wire ENET0_PTP_DELAY_REQ_RX;
- wire ENET0_PTP_DELAY_REQ_TX;
- wire ENET0_PTP_PDELAY_REQ_RX;
- wire ENET0_PTP_PDELAY_REQ_TX;
- wire ENET0_PTP_PDELAY_RESP_RX;
- wire ENET0_PTP_PDELAY_RESP_TX;
- wire ENET0_PTP_SYNC_FRAME_RX;
- wire ENET0_PTP_SYNC_FRAME_TX;
- wire ENET0_SOF_RX;
- wire ENET0_SOF_TX;
- wire ENET1_EXT_INTIN;
- wire ENET1_GMII_RX_CLK;
- wire ENET1_GMII_TX_CLK;
- wire ENET1_MDIO_I;
- wire ENET1_MDIO_MDC;
- wire ENET1_MDIO_O;
- wire ENET1_MDIO_T;
- wire ENET1_MDIO_T_n;
- wire ENET1_PTP_DELAY_REQ_RX;
- wire ENET1_PTP_DELAY_REQ_TX;
- wire ENET1_PTP_PDELAY_REQ_RX;
- wire ENET1_PTP_PDELAY_REQ_TX;
- wire ENET1_PTP_PDELAY_RESP_RX;
- wire ENET1_PTP_PDELAY_RESP_TX;
- wire ENET1_PTP_SYNC_FRAME_RX;
- wire ENET1_PTP_SYNC_FRAME_TX;
- wire ENET1_SOF_RX;
- wire ENET1_SOF_TX;
- wire EVENT_EVENTI;
- wire EVENT_EVENTO;
- wire [1:0]EVENT_STANDBYWFE;
- wire [1:0]EVENT_STANDBYWFI;
- wire FCLK_CLK0;
- wire FCLK_CLK1;
- wire FCLK_CLK2;
- wire FCLK_CLK3;
- wire [0:0]FCLK_CLK_unbuffered;
- wire FCLK_RESET0_N;
- wire FCLK_RESET1_N;
- wire FCLK_RESET2_N;
- wire FCLK_RESET3_N;
- wire FPGA_IDLE_N;
- wire FTMD_TRACEIN_CLK;
- wire [31:0]FTMT_F2P_DEBUG;
- wire FTMT_F2P_TRIGACK_0;
- wire FTMT_F2P_TRIGACK_1;
- wire FTMT_F2P_TRIGACK_2;
- wire FTMT_F2P_TRIGACK_3;
- wire FTMT_F2P_TRIG_0;
- wire FTMT_F2P_TRIG_1;
- wire FTMT_F2P_TRIG_2;
- wire FTMT_F2P_TRIG_3;
- wire [31:0]FTMT_P2F_DEBUG;
- wire FTMT_P2F_TRIGACK_0;
- wire FTMT_P2F_TRIGACK_1;
- wire FTMT_P2F_TRIGACK_2;
- wire FTMT_P2F_TRIGACK_3;
- wire FTMT_P2F_TRIG_0;
- wire FTMT_P2F_TRIG_1;
- wire FTMT_P2F_TRIG_2;
- wire FTMT_P2F_TRIG_3;
- wire [63:0]GPIO_I;
- wire [63:0]GPIO_O;
- wire [63:0]GPIO_T;
- wire I2C0_SCL_I;
- wire I2C0_SCL_O;
- wire I2C0_SCL_T;
- wire I2C0_SCL_T_n;
- wire I2C0_SDA_I;
- wire I2C0_SDA_O;
- wire I2C0_SDA_T;
- wire I2C0_SDA_T_n;
- wire I2C1_SCL_I;
- wire I2C1_SCL_O;
- wire I2C1_SCL_T;
- wire I2C1_SCL_T_n;
- wire I2C1_SDA_I;
- wire I2C1_SDA_O;
- wire I2C1_SDA_T;
- wire I2C1_SDA_T_n;
- wire [0:0]IRQ_F2P;
- wire IRQ_P2F_CAN0;
- wire IRQ_P2F_CAN1;
- wire IRQ_P2F_CTI;
- wire IRQ_P2F_DMAC0;
- wire IRQ_P2F_DMAC1;
- wire IRQ_P2F_DMAC2;
- wire IRQ_P2F_DMAC3;
- wire IRQ_P2F_DMAC4;
- wire IRQ_P2F_DMAC5;
- wire IRQ_P2F_DMAC6;
- wire IRQ_P2F_DMAC7;
- wire IRQ_P2F_DMAC_ABORT;
- wire IRQ_P2F_ENET0;
- wire IRQ_P2F_ENET1;
- wire IRQ_P2F_ENET_WAKE0;
- wire IRQ_P2F_ENET_WAKE1;
- wire IRQ_P2F_GPIO;
- wire IRQ_P2F_I2C0;
- wire IRQ_P2F_I2C1;
- wire IRQ_P2F_QSPI;
- wire IRQ_P2F_SDIO0;
- wire IRQ_P2F_SDIO1;
- wire IRQ_P2F_SMC;
- wire IRQ_P2F_SPI0;
- wire IRQ_P2F_SPI1;
- wire IRQ_P2F_UART0;
- wire IRQ_P2F_UART1;
- wire IRQ_P2F_USB0;
- wire IRQ_P2F_USB1;
- wire [53:0]MIO;
- wire M_AXI_GP0_ACLK;
- wire [31:0]M_AXI_GP0_ARADDR;
- wire [1:0]M_AXI_GP0_ARBURST;
- wire [3:0]\^M_AXI_GP0_ARCACHE ;
- wire M_AXI_GP0_ARESETN;
- wire [11:0]M_AXI_GP0_ARID;
- wire [3:0]M_AXI_GP0_ARLEN;
- wire [1:0]M_AXI_GP0_ARLOCK;
- wire [2:0]M_AXI_GP0_ARPROT;
- wire [3:0]M_AXI_GP0_ARQOS;
- wire M_AXI_GP0_ARREADY;
- wire [1:0]\^M_AXI_GP0_ARSIZE ;
- wire M_AXI_GP0_ARVALID;
- wire [31:0]M_AXI_GP0_AWADDR;
- wire [1:0]M_AXI_GP0_AWBURST;
- wire [3:0]\^M_AXI_GP0_AWCACHE ;
- wire [11:0]M_AXI_GP0_AWID;
- wire [3:0]M_AXI_GP0_AWLEN;
- wire [1:0]M_AXI_GP0_AWLOCK;
- wire [2:0]M_AXI_GP0_AWPROT;
- wire [3:0]M_AXI_GP0_AWQOS;
- wire M_AXI_GP0_AWREADY;
- wire [1:0]\^M_AXI_GP0_AWSIZE ;
- wire M_AXI_GP0_AWVALID;
- wire [11:0]M_AXI_GP0_BID;
- wire M_AXI_GP0_BREADY;
- wire [1:0]M_AXI_GP0_BRESP;
- wire M_AXI_GP0_BVALID;
- wire [31:0]M_AXI_GP0_RDATA;
- wire [11:0]M_AXI_GP0_RID;
- wire M_AXI_GP0_RLAST;
- wire M_AXI_GP0_RREADY;
- wire [1:0]M_AXI_GP0_RRESP;
- wire M_AXI_GP0_RVALID;
- wire [31:0]M_AXI_GP0_WDATA;
- wire [11:0]M_AXI_GP0_WID;
- wire M_AXI_GP0_WLAST;
- wire M_AXI_GP0_WREADY;
- wire [3:0]M_AXI_GP0_WSTRB;
- wire M_AXI_GP0_WVALID;
- wire M_AXI_GP1_ACLK;
- wire [31:0]M_AXI_GP1_ARADDR;
- wire [1:0]M_AXI_GP1_ARBURST;
- wire [3:0]\^M_AXI_GP1_ARCACHE ;
- wire M_AXI_GP1_ARESETN;
- wire [11:0]M_AXI_GP1_ARID;
- wire [3:0]M_AXI_GP1_ARLEN;
- wire [1:0]M_AXI_GP1_ARLOCK;
- wire [2:0]M_AXI_GP1_ARPROT;
- wire [3:0]M_AXI_GP1_ARQOS;
- wire M_AXI_GP1_ARREADY;
- wire [1:0]\^M_AXI_GP1_ARSIZE ;
- wire M_AXI_GP1_ARVALID;
- wire [31:0]M_AXI_GP1_AWADDR;
- wire [1:0]M_AXI_GP1_AWBURST;
- wire [3:0]\^M_AXI_GP1_AWCACHE ;
- wire [11:0]M_AXI_GP1_AWID;
- wire [3:0]M_AXI_GP1_AWLEN;
- wire [1:0]M_AXI_GP1_AWLOCK;
- wire [2:0]M_AXI_GP1_AWPROT;
- wire [3:0]M_AXI_GP1_AWQOS;
- wire M_AXI_GP1_AWREADY;
- wire [1:0]\^M_AXI_GP1_AWSIZE ;
- wire M_AXI_GP1_AWVALID;
- wire [11:0]M_AXI_GP1_BID;
- wire M_AXI_GP1_BREADY;
- wire [1:0]M_AXI_GP1_BRESP;
- wire M_AXI_GP1_BVALID;
- wire [31:0]M_AXI_GP1_RDATA;
- wire [11:0]M_AXI_GP1_RID;
- wire M_AXI_GP1_RLAST;
- wire M_AXI_GP1_RREADY;
- wire [1:0]M_AXI_GP1_RRESP;
- wire M_AXI_GP1_RVALID;
- wire [31:0]M_AXI_GP1_WDATA;
- wire [11:0]M_AXI_GP1_WID;
- wire M_AXI_GP1_WLAST;
- wire M_AXI_GP1_WREADY;
- wire [3:0]M_AXI_GP1_WSTRB;
- wire M_AXI_GP1_WVALID;
- wire PJTAG_TCK;
- wire PJTAG_TDI;
- wire PJTAG_TMS;
- wire PS_CLK;
- wire PS_PORB;
- wire PS_SRSTB;
- wire SDIO0_BUSPOW;
- wire [2:0]SDIO0_BUSVOLT;
- wire SDIO0_CDN;
- wire SDIO0_CLK;
- wire SDIO0_CLK_FB;
- wire SDIO0_CMD_I;
- wire SDIO0_CMD_O;
- wire SDIO0_CMD_T;
- wire SDIO0_CMD_T_n;
- wire [3:0]SDIO0_DATA_I;
- wire [3:0]SDIO0_DATA_O;
- wire [3:0]SDIO0_DATA_T;
- wire [3:0]SDIO0_DATA_T_n;
- wire SDIO0_LED;
- wire SDIO0_WP;
- wire SDIO1_BUSPOW;
- wire [2:0]SDIO1_BUSVOLT;
- wire SDIO1_CDN;
- wire SDIO1_CLK;
- wire SDIO1_CLK_FB;
- wire SDIO1_CMD_I;
- wire SDIO1_CMD_O;
- wire SDIO1_CMD_T;
- wire SDIO1_CMD_T_n;
- wire [3:0]SDIO1_DATA_I;
- wire [3:0]SDIO1_DATA_O;
- wire [3:0]SDIO1_DATA_T;
- wire [3:0]SDIO1_DATA_T_n;
- wire SDIO1_LED;
- wire SDIO1_WP;
- wire SPI0_MISO_I;
- wire SPI0_MISO_O;
- wire SPI0_MISO_T;
- wire SPI0_MISO_T_n;
- wire SPI0_MOSI_I;
- wire SPI0_MOSI_O;
- wire SPI0_MOSI_T;
- wire SPI0_MOSI_T_n;
- wire SPI0_SCLK_I;
- wire SPI0_SCLK_O;
- wire SPI0_SCLK_T;
- wire SPI0_SCLK_T_n;
- wire SPI0_SS1_O;
- wire SPI0_SS2_O;
- wire SPI0_SS_I;
- wire SPI0_SS_O;
- wire SPI0_SS_T;
- wire SPI0_SS_T_n;
- wire SPI1_MISO_I;
- wire SPI1_MISO_O;
- wire SPI1_MISO_T;
- wire SPI1_MISO_T_n;
- wire SPI1_MOSI_I;
- wire SPI1_MOSI_O;
- wire SPI1_MOSI_T;
- wire SPI1_MOSI_T_n;
- wire SPI1_SCLK_I;
- wire SPI1_SCLK_O;
- wire SPI1_SCLK_T;
- wire SPI1_SCLK_T_n;
- wire SPI1_SS1_O;
- wire SPI1_SS2_O;
- wire SPI1_SS_I;
- wire SPI1_SS_O;
- wire SPI1_SS_T;
- wire SPI1_SS_T_n;
- wire SRAM_INTIN;
- wire S_AXI_ACP_ACLK;
- wire [31:0]S_AXI_ACP_ARADDR;
- wire [1:0]S_AXI_ACP_ARBURST;
- wire [3:0]S_AXI_ACP_ARCACHE;
- wire S_AXI_ACP_ARESETN;
- wire [2:0]S_AXI_ACP_ARID;
- wire [3:0]S_AXI_ACP_ARLEN;
- wire [1:0]S_AXI_ACP_ARLOCK;
- wire [2:0]S_AXI_ACP_ARPROT;
- wire [3:0]S_AXI_ACP_ARQOS;
- wire S_AXI_ACP_ARREADY;
- wire [2:0]S_AXI_ACP_ARSIZE;
- wire [4:0]S_AXI_ACP_ARUSER;
- wire S_AXI_ACP_ARVALID;
- wire [31:0]S_AXI_ACP_AWADDR;
- wire [1:0]S_AXI_ACP_AWBURST;
- wire [3:0]S_AXI_ACP_AWCACHE;
- wire [2:0]S_AXI_ACP_AWID;
- wire [3:0]S_AXI_ACP_AWLEN;
- wire [1:0]S_AXI_ACP_AWLOCK;
- wire [2:0]S_AXI_ACP_AWPROT;
- wire [3:0]S_AXI_ACP_AWQOS;
- wire S_AXI_ACP_AWREADY;
- wire [2:0]S_AXI_ACP_AWSIZE;
- wire [4:0]S_AXI_ACP_AWUSER;
- wire S_AXI_ACP_AWVALID;
- wire [2:0]S_AXI_ACP_BID;
- wire S_AXI_ACP_BREADY;
- wire [1:0]S_AXI_ACP_BRESP;
- wire S_AXI_ACP_BVALID;
- wire [63:0]S_AXI_ACP_RDATA;
- wire [2:0]S_AXI_ACP_RID;
- wire S_AXI_ACP_RLAST;
- wire S_AXI_ACP_RREADY;
- wire [1:0]S_AXI_ACP_RRESP;
- wire S_AXI_ACP_RVALID;
- wire [63:0]S_AXI_ACP_WDATA;
- wire [2:0]S_AXI_ACP_WID;
- wire S_AXI_ACP_WLAST;
- wire S_AXI_ACP_WREADY;
- wire [7:0]S_AXI_ACP_WSTRB;
- wire S_AXI_ACP_WVALID;
- wire S_AXI_GP0_ACLK;
- wire [31:0]S_AXI_GP0_ARADDR;
- wire [1:0]S_AXI_GP0_ARBURST;
- wire [3:0]S_AXI_GP0_ARCACHE;
- wire S_AXI_GP0_ARESETN;
- wire [5:0]S_AXI_GP0_ARID;
- wire [3:0]S_AXI_GP0_ARLEN;
- wire [1:0]S_AXI_GP0_ARLOCK;
- wire [2:0]S_AXI_GP0_ARPROT;
- wire [3:0]S_AXI_GP0_ARQOS;
- wire S_AXI_GP0_ARREADY;
- wire [2:0]S_AXI_GP0_ARSIZE;
- wire S_AXI_GP0_ARVALID;
- wire [31:0]S_AXI_GP0_AWADDR;
- wire [1:0]S_AXI_GP0_AWBURST;
- wire [3:0]S_AXI_GP0_AWCACHE;
- wire [5:0]S_AXI_GP0_AWID;
- wire [3:0]S_AXI_GP0_AWLEN;
- wire [1:0]S_AXI_GP0_AWLOCK;
- wire [2:0]S_AXI_GP0_AWPROT;
- wire [3:0]S_AXI_GP0_AWQOS;
- wire S_AXI_GP0_AWREADY;
- wire [2:0]S_AXI_GP0_AWSIZE;
- wire S_AXI_GP0_AWVALID;
- wire [5:0]S_AXI_GP0_BID;
- wire S_AXI_GP0_BREADY;
- wire [1:0]S_AXI_GP0_BRESP;
- wire S_AXI_GP0_BVALID;
- wire [31:0]S_AXI_GP0_RDATA;
- wire [5:0]S_AXI_GP0_RID;
- wire S_AXI_GP0_RLAST;
- wire S_AXI_GP0_RREADY;
- wire [1:0]S_AXI_GP0_RRESP;
- wire S_AXI_GP0_RVALID;
- wire [31:0]S_AXI_GP0_WDATA;
- wire [5:0]S_AXI_GP0_WID;
- wire S_AXI_GP0_WLAST;
- wire S_AXI_GP0_WREADY;
- wire [3:0]S_AXI_GP0_WSTRB;
- wire S_AXI_GP0_WVALID;
- wire S_AXI_GP1_ACLK;
- wire [31:0]S_AXI_GP1_ARADDR;
- wire [1:0]S_AXI_GP1_ARBURST;
- wire [3:0]S_AXI_GP1_ARCACHE;
- wire S_AXI_GP1_ARESETN;
- wire [5:0]S_AXI_GP1_ARID;
- wire [3:0]S_AXI_GP1_ARLEN;
- wire [1:0]S_AXI_GP1_ARLOCK;
- wire [2:0]S_AXI_GP1_ARPROT;
- wire [3:0]S_AXI_GP1_ARQOS;
- wire S_AXI_GP1_ARREADY;
- wire [2:0]S_AXI_GP1_ARSIZE;
- wire S_AXI_GP1_ARVALID;
- wire [31:0]S_AXI_GP1_AWADDR;
- wire [1:0]S_AXI_GP1_AWBURST;
- wire [3:0]S_AXI_GP1_AWCACHE;
- wire [5:0]S_AXI_GP1_AWID;
- wire [3:0]S_AXI_GP1_AWLEN;
- wire [1:0]S_AXI_GP1_AWLOCK;
- wire [2:0]S_AXI_GP1_AWPROT;
- wire [3:0]S_AXI_GP1_AWQOS;
- wire S_AXI_GP1_AWREADY;
- wire [2:0]S_AXI_GP1_AWSIZE;
- wire S_AXI_GP1_AWVALID;
- wire [5:0]S_AXI_GP1_BID;
- wire S_AXI_GP1_BREADY;
- wire [1:0]S_AXI_GP1_BRESP;
- wire S_AXI_GP1_BVALID;
- wire [31:0]S_AXI_GP1_RDATA;
- wire [5:0]S_AXI_GP1_RID;
- wire S_AXI_GP1_RLAST;
- wire S_AXI_GP1_RREADY;
- wire [1:0]S_AXI_GP1_RRESP;
- wire S_AXI_GP1_RVALID;
- wire [31:0]S_AXI_GP1_WDATA;
- wire [5:0]S_AXI_GP1_WID;
- wire S_AXI_GP1_WLAST;
- wire S_AXI_GP1_WREADY;
- wire [3:0]S_AXI_GP1_WSTRB;
- wire S_AXI_GP1_WVALID;
- wire S_AXI_HP0_ACLK;
- wire [31:0]S_AXI_HP0_ARADDR;
- wire [1:0]S_AXI_HP0_ARBURST;
- wire [3:0]S_AXI_HP0_ARCACHE;
- wire S_AXI_HP0_ARESETN;
- wire [5:0]S_AXI_HP0_ARID;
- wire [3:0]S_AXI_HP0_ARLEN;
- wire [1:0]S_AXI_HP0_ARLOCK;
- wire [2:0]S_AXI_HP0_ARPROT;
- wire [3:0]S_AXI_HP0_ARQOS;
- wire S_AXI_HP0_ARREADY;
- wire [2:0]S_AXI_HP0_ARSIZE;
- wire S_AXI_HP0_ARVALID;
- wire [31:0]S_AXI_HP0_AWADDR;
- wire [1:0]S_AXI_HP0_AWBURST;
- wire [3:0]S_AXI_HP0_AWCACHE;
- wire [5:0]S_AXI_HP0_AWID;
- wire [3:0]S_AXI_HP0_AWLEN;
- wire [1:0]S_AXI_HP0_AWLOCK;
- wire [2:0]S_AXI_HP0_AWPROT;
- wire [3:0]S_AXI_HP0_AWQOS;
- wire S_AXI_HP0_AWREADY;
- wire [2:0]S_AXI_HP0_AWSIZE;
- wire S_AXI_HP0_AWVALID;
- wire [5:0]S_AXI_HP0_BID;
- wire S_AXI_HP0_BREADY;
- wire [1:0]S_AXI_HP0_BRESP;
- wire S_AXI_HP0_BVALID;
- wire [2:0]S_AXI_HP0_RACOUNT;
- wire [7:0]S_AXI_HP0_RCOUNT;
- wire [63:0]S_AXI_HP0_RDATA;
- wire S_AXI_HP0_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP0_RID;
- wire S_AXI_HP0_RLAST;
- wire S_AXI_HP0_RREADY;
- wire [1:0]S_AXI_HP0_RRESP;
- wire S_AXI_HP0_RVALID;
- wire [5:0]S_AXI_HP0_WACOUNT;
- wire [7:0]S_AXI_HP0_WCOUNT;
- wire [63:0]S_AXI_HP0_WDATA;
- wire [5:0]S_AXI_HP0_WID;
- wire S_AXI_HP0_WLAST;
- wire S_AXI_HP0_WREADY;
- wire S_AXI_HP0_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP0_WSTRB;
- wire S_AXI_HP0_WVALID;
- wire S_AXI_HP1_ACLK;
- wire [31:0]S_AXI_HP1_ARADDR;
- wire [1:0]S_AXI_HP1_ARBURST;
- wire [3:0]S_AXI_HP1_ARCACHE;
- wire S_AXI_HP1_ARESETN;
- wire [5:0]S_AXI_HP1_ARID;
- wire [3:0]S_AXI_HP1_ARLEN;
- wire [1:0]S_AXI_HP1_ARLOCK;
- wire [2:0]S_AXI_HP1_ARPROT;
- wire [3:0]S_AXI_HP1_ARQOS;
- wire S_AXI_HP1_ARREADY;
- wire [2:0]S_AXI_HP1_ARSIZE;
- wire S_AXI_HP1_ARVALID;
- wire [31:0]S_AXI_HP1_AWADDR;
- wire [1:0]S_AXI_HP1_AWBURST;
- wire [3:0]S_AXI_HP1_AWCACHE;
- wire [5:0]S_AXI_HP1_AWID;
- wire [3:0]S_AXI_HP1_AWLEN;
- wire [1:0]S_AXI_HP1_AWLOCK;
- wire [2:0]S_AXI_HP1_AWPROT;
- wire [3:0]S_AXI_HP1_AWQOS;
- wire S_AXI_HP1_AWREADY;
- wire [2:0]S_AXI_HP1_AWSIZE;
- wire S_AXI_HP1_AWVALID;
- wire [5:0]S_AXI_HP1_BID;
- wire S_AXI_HP1_BREADY;
- wire [1:0]S_AXI_HP1_BRESP;
- wire S_AXI_HP1_BVALID;
- wire [2:0]S_AXI_HP1_RACOUNT;
- wire [7:0]S_AXI_HP1_RCOUNT;
- wire [63:0]S_AXI_HP1_RDATA;
- wire S_AXI_HP1_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP1_RID;
- wire S_AXI_HP1_RLAST;
- wire S_AXI_HP1_RREADY;
- wire [1:0]S_AXI_HP1_RRESP;
- wire S_AXI_HP1_RVALID;
- wire [5:0]S_AXI_HP1_WACOUNT;
- wire [7:0]S_AXI_HP1_WCOUNT;
- wire [63:0]S_AXI_HP1_WDATA;
- wire [5:0]S_AXI_HP1_WID;
- wire S_AXI_HP1_WLAST;
- wire S_AXI_HP1_WREADY;
- wire S_AXI_HP1_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP1_WSTRB;
- wire S_AXI_HP1_WVALID;
- wire S_AXI_HP2_ACLK;
- wire [31:0]S_AXI_HP2_ARADDR;
- wire [1:0]S_AXI_HP2_ARBURST;
- wire [3:0]S_AXI_HP2_ARCACHE;
- wire S_AXI_HP2_ARESETN;
- wire [5:0]S_AXI_HP2_ARID;
- wire [3:0]S_AXI_HP2_ARLEN;
- wire [1:0]S_AXI_HP2_ARLOCK;
- wire [2:0]S_AXI_HP2_ARPROT;
- wire [3:0]S_AXI_HP2_ARQOS;
- wire S_AXI_HP2_ARREADY;
- wire [2:0]S_AXI_HP2_ARSIZE;
- wire S_AXI_HP2_ARVALID;
- wire [31:0]S_AXI_HP2_AWADDR;
- wire [1:0]S_AXI_HP2_AWBURST;
- wire [3:0]S_AXI_HP2_AWCACHE;
- wire [5:0]S_AXI_HP2_AWID;
- wire [3:0]S_AXI_HP2_AWLEN;
- wire [1:0]S_AXI_HP2_AWLOCK;
- wire [2:0]S_AXI_HP2_AWPROT;
- wire [3:0]S_AXI_HP2_AWQOS;
- wire S_AXI_HP2_AWREADY;
- wire [2:0]S_AXI_HP2_AWSIZE;
- wire S_AXI_HP2_AWVALID;
- wire [5:0]S_AXI_HP2_BID;
- wire S_AXI_HP2_BREADY;
- wire [1:0]S_AXI_HP2_BRESP;
- wire S_AXI_HP2_BVALID;
- wire [2:0]S_AXI_HP2_RACOUNT;
- wire [7:0]S_AXI_HP2_RCOUNT;
- wire [63:0]S_AXI_HP2_RDATA;
- wire S_AXI_HP2_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP2_RID;
- wire S_AXI_HP2_RLAST;
- wire S_AXI_HP2_RREADY;
- wire [1:0]S_AXI_HP2_RRESP;
- wire S_AXI_HP2_RVALID;
- wire [5:0]S_AXI_HP2_WACOUNT;
- wire [7:0]S_AXI_HP2_WCOUNT;
- wire [63:0]S_AXI_HP2_WDATA;
- wire [5:0]S_AXI_HP2_WID;
- wire S_AXI_HP2_WLAST;
- wire S_AXI_HP2_WREADY;
- wire S_AXI_HP2_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP2_WSTRB;
- wire S_AXI_HP2_WVALID;
- wire S_AXI_HP3_ACLK;
- wire [31:0]S_AXI_HP3_ARADDR;
- wire [1:0]S_AXI_HP3_ARBURST;
- wire [3:0]S_AXI_HP3_ARCACHE;
- wire S_AXI_HP3_ARESETN;
- wire [5:0]S_AXI_HP3_ARID;
- wire [3:0]S_AXI_HP3_ARLEN;
- wire [1:0]S_AXI_HP3_ARLOCK;
- wire [2:0]S_AXI_HP3_ARPROT;
- wire [3:0]S_AXI_HP3_ARQOS;
- wire S_AXI_HP3_ARREADY;
- wire [2:0]S_AXI_HP3_ARSIZE;
- wire S_AXI_HP3_ARVALID;
- wire [31:0]S_AXI_HP3_AWADDR;
- wire [1:0]S_AXI_HP3_AWBURST;
- wire [3:0]S_AXI_HP3_AWCACHE;
- wire [5:0]S_AXI_HP3_AWID;
- wire [3:0]S_AXI_HP3_AWLEN;
- wire [1:0]S_AXI_HP3_AWLOCK;
- wire [2:0]S_AXI_HP3_AWPROT;
- wire [3:0]S_AXI_HP3_AWQOS;
- wire S_AXI_HP3_AWREADY;
- wire [2:0]S_AXI_HP3_AWSIZE;
- wire S_AXI_HP3_AWVALID;
- wire [5:0]S_AXI_HP3_BID;
- wire S_AXI_HP3_BREADY;
- wire [1:0]S_AXI_HP3_BRESP;
- wire S_AXI_HP3_BVALID;
- wire [2:0]S_AXI_HP3_RACOUNT;
- wire [7:0]S_AXI_HP3_RCOUNT;
- wire [63:0]S_AXI_HP3_RDATA;
- wire S_AXI_HP3_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP3_RID;
- wire S_AXI_HP3_RLAST;
- wire S_AXI_HP3_RREADY;
- wire [1:0]S_AXI_HP3_RRESP;
- wire S_AXI_HP3_RVALID;
- wire [5:0]S_AXI_HP3_WACOUNT;
- wire [7:0]S_AXI_HP3_WCOUNT;
- wire [63:0]S_AXI_HP3_WDATA;
- wire [5:0]S_AXI_HP3_WID;
- wire S_AXI_HP3_WLAST;
- wire S_AXI_HP3_WREADY;
- wire S_AXI_HP3_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP3_WSTRB;
- wire S_AXI_HP3_WVALID;
- wire TRACE_CLK;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
- wire TTC0_CLK0_IN;
- wire TTC0_CLK1_IN;
- wire TTC0_CLK2_IN;
- wire TTC0_WAVE0_OUT;
- wire TTC0_WAVE1_OUT;
- wire TTC0_WAVE2_OUT;
- wire TTC1_CLK0_IN;
- wire TTC1_CLK1_IN;
- wire TTC1_CLK2_IN;
- wire TTC1_WAVE0_OUT;
- wire TTC1_WAVE1_OUT;
- wire TTC1_WAVE2_OUT;
- wire UART0_CTSN;
- wire UART0_DCDN;
- wire UART0_DSRN;
- wire UART0_DTRN;
- wire UART0_RIN;
- wire UART0_RTSN;
- wire UART0_RX;
- wire UART0_TX;
- wire UART1_CTSN;
- wire UART1_DCDN;
- wire UART1_DSRN;
- wire UART1_DTRN;
- wire UART1_RIN;
- wire UART1_RTSN;
- wire UART1_RX;
- wire UART1_TX;
- wire [1:0]USB0_PORT_INDCTL;
- wire USB0_VBUS_PWRFAULT;
- wire USB0_VBUS_PWRSELECT;
- wire [1:0]USB1_PORT_INDCTL;
- wire USB1_VBUS_PWRFAULT;
- wire USB1_VBUS_PWRSELECT;
- wire WDT_CLK_IN;
- wire WDT_RST_OUT;
- wire [14:0]buffered_DDR_Addr;
- wire [2:0]buffered_DDR_BankAddr;
- wire buffered_DDR_CAS_n;
- wire buffered_DDR_CKE;
- wire buffered_DDR_CS_n;
- wire buffered_DDR_Clk;
- wire buffered_DDR_Clk_n;
- wire [3:0]buffered_DDR_DM;
- wire [31:0]buffered_DDR_DQ;
- wire [3:0]buffered_DDR_DQS;
- wire [3:0]buffered_DDR_DQS_n;
- wire buffered_DDR_DRSTB;
- wire buffered_DDR_ODT;
- wire buffered_DDR_RAS_n;
- wire buffered_DDR_VRN;
- wire buffered_DDR_VRP;
- wire buffered_DDR_WEB;
- wire [53:0]buffered_MIO;
- wire buffered_PS_CLK;
- wire buffered_PS_PORB;
- wire buffered_PS_SRSTB;
- wire [63:0]gpio_out_t_n;
- wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
- wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
- wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
- wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
- wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
- wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
- wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
- wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
- wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
- wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
-
- assign ENET0_GMII_TXD[7] = \<const0> ;
- assign ENET0_GMII_TXD[6] = \<const0> ;
- assign ENET0_GMII_TXD[5] = \<const0> ;
- assign ENET0_GMII_TXD[4] = \<const0> ;
- assign ENET0_GMII_TXD[3] = \<const0> ;
- assign ENET0_GMII_TXD[2] = \<const0> ;
- assign ENET0_GMII_TXD[1] = \<const0> ;
- assign ENET0_GMII_TXD[0] = \<const0> ;
- assign ENET0_GMII_TX_EN = \<const0> ;
- assign ENET0_GMII_TX_ER = \<const0> ;
- assign ENET1_GMII_TXD[7] = \<const0> ;
- assign ENET1_GMII_TXD[6] = \<const0> ;
- assign ENET1_GMII_TXD[5] = \<const0> ;
- assign ENET1_GMII_TXD[4] = \<const0> ;
- assign ENET1_GMII_TXD[3] = \<const0> ;
- assign ENET1_GMII_TXD[2] = \<const0> ;
- assign ENET1_GMII_TXD[1] = \<const0> ;
- assign ENET1_GMII_TXD[0] = \<const0> ;
- assign ENET1_GMII_TX_EN = \<const0> ;
- assign ENET1_GMII_TX_ER = \<const0> ;
- assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
- assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
- assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
- assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
- assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
- assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
- assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
- assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
- assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
- assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
- assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
- assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
- assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
- assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
- assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
- assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
- assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
- assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
- assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
- assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
- assign PJTAG_TDO = \<const0> ;
- assign TRACE_CLK_OUT = \<const0> ;
- assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
- assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_CAS_n_BIBUF
- (.IO(buffered_DDR_CAS_n),
- .PAD(DDR_CAS_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_CKE_BIBUF
- (.IO(buffered_DDR_CKE),
- .PAD(DDR_CKE));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_CS_n_BIBUF
- (.IO(buffered_DDR_CS_n),
- .PAD(DDR_CS_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_Clk_BIBUF
- (.IO(buffered_DDR_Clk),
- .PAD(DDR_Clk));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_Clk_n_BIBUF
- (.IO(buffered_DDR_Clk_n),
- .PAD(DDR_Clk_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_DRSTB_BIBUF
- (.IO(buffered_DDR_DRSTB),
- .PAD(DDR_DRSTB));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_ODT_BIBUF
- (.IO(buffered_DDR_ODT),
- .PAD(DDR_ODT));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_RAS_n_BIBUF
- (.IO(buffered_DDR_RAS_n),
- .PAD(DDR_RAS_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_VRN_BIBUF
- (.IO(buffered_DDR_VRN),
- .PAD(DDR_VRN));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_VRP_BIBUF
- (.IO(buffered_DDR_VRP),
- .PAD(DDR_VRP));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_WEB_BIBUF
- (.IO(buffered_DDR_WEB),
- .PAD(DDR_WEB));
- LUT1 #(
- .INIT(2'h1))
- ENET0_MDIO_T_INST_0
- (.I0(ENET0_MDIO_T_n),
- .O(ENET0_MDIO_T));
- LUT1 #(
- .INIT(2'h1))
- ENET1_MDIO_T_INST_0
- (.I0(ENET1_MDIO_T_n),
- .O(ENET1_MDIO_T));
- GND GND
- (.G(\<const0> ));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[0]_INST_0
- (.I0(gpio_out_t_n[0]),
- .O(GPIO_T[0]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[10]_INST_0
- (.I0(gpio_out_t_n[10]),
- .O(GPIO_T[10]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[11]_INST_0
- (.I0(gpio_out_t_n[11]),
- .O(GPIO_T[11]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[12]_INST_0
- (.I0(gpio_out_t_n[12]),
- .O(GPIO_T[12]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[13]_INST_0
- (.I0(gpio_out_t_n[13]),
- .O(GPIO_T[13]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[14]_INST_0
- (.I0(gpio_out_t_n[14]),
- .O(GPIO_T[14]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[15]_INST_0
- (.I0(gpio_out_t_n[15]),
- .O(GPIO_T[15]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[16]_INST_0
- (.I0(gpio_out_t_n[16]),
- .O(GPIO_T[16]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[17]_INST_0
- (.I0(gpio_out_t_n[17]),
- .O(GPIO_T[17]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[18]_INST_0
- (.I0(gpio_out_t_n[18]),
- .O(GPIO_T[18]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[19]_INST_0
- (.I0(gpio_out_t_n[19]),
- .O(GPIO_T[19]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[1]_INST_0
- (.I0(gpio_out_t_n[1]),
- .O(GPIO_T[1]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[20]_INST_0
- (.I0(gpio_out_t_n[20]),
- .O(GPIO_T[20]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[21]_INST_0
- (.I0(gpio_out_t_n[21]),
- .O(GPIO_T[21]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[22]_INST_0
- (.I0(gpio_out_t_n[22]),
- .O(GPIO_T[22]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[23]_INST_0
- (.I0(gpio_out_t_n[23]),
- .O(GPIO_T[23]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[24]_INST_0
- (.I0(gpio_out_t_n[24]),
- .O(GPIO_T[24]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[25]_INST_0
- (.I0(gpio_out_t_n[25]),
- .O(GPIO_T[25]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[26]_INST_0
- (.I0(gpio_out_t_n[26]),
- .O(GPIO_T[26]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[27]_INST_0
- (.I0(gpio_out_t_n[27]),
- .O(GPIO_T[27]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[28]_INST_0
- (.I0(gpio_out_t_n[28]),
- .O(GPIO_T[28]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[29]_INST_0
- (.I0(gpio_out_t_n[29]),
- .O(GPIO_T[29]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[2]_INST_0
- (.I0(gpio_out_t_n[2]),
- .O(GPIO_T[2]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[30]_INST_0
- (.I0(gpio_out_t_n[30]),
- .O(GPIO_T[30]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[31]_INST_0
- (.I0(gpio_out_t_n[31]),
- .O(GPIO_T[31]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[32]_INST_0
- (.I0(gpio_out_t_n[32]),
- .O(GPIO_T[32]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[33]_INST_0
- (.I0(gpio_out_t_n[33]),
- .O(GPIO_T[33]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[34]_INST_0
- (.I0(gpio_out_t_n[34]),
- .O(GPIO_T[34]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[35]_INST_0
- (.I0(gpio_out_t_n[35]),
- .O(GPIO_T[35]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[36]_INST_0
- (.I0(gpio_out_t_n[36]),
- .O(GPIO_T[36]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[37]_INST_0
- (.I0(gpio_out_t_n[37]),
- .O(GPIO_T[37]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[38]_INST_0
- (.I0(gpio_out_t_n[38]),
- .O(GPIO_T[38]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[39]_INST_0
- (.I0(gpio_out_t_n[39]),
- .O(GPIO_T[39]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[3]_INST_0
- (.I0(gpio_out_t_n[3]),
- .O(GPIO_T[3]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[40]_INST_0
- (.I0(gpio_out_t_n[40]),
- .O(GPIO_T[40]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[41]_INST_0
- (.I0(gpio_out_t_n[41]),
- .O(GPIO_T[41]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[42]_INST_0
- (.I0(gpio_out_t_n[42]),
- .O(GPIO_T[42]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[43]_INST_0
- (.I0(gpio_out_t_n[43]),
- .O(GPIO_T[43]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[44]_INST_0
- (.I0(gpio_out_t_n[44]),
- .O(GPIO_T[44]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[45]_INST_0
- (.I0(gpio_out_t_n[45]),
- .O(GPIO_T[45]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[46]_INST_0
- (.I0(gpio_out_t_n[46]),
- .O(GPIO_T[46]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[47]_INST_0
- (.I0(gpio_out_t_n[47]),
- .O(GPIO_T[47]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[48]_INST_0
- (.I0(gpio_out_t_n[48]),
- .O(GPIO_T[48]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[49]_INST_0
- (.I0(gpio_out_t_n[49]),
- .O(GPIO_T[49]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[4]_INST_0
- (.I0(gpio_out_t_n[4]),
- .O(GPIO_T[4]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[50]_INST_0
- (.I0(gpio_out_t_n[50]),
- .O(GPIO_T[50]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[51]_INST_0
- (.I0(gpio_out_t_n[51]),
- .O(GPIO_T[51]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[52]_INST_0
- (.I0(gpio_out_t_n[52]),
- .O(GPIO_T[52]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[53]_INST_0
- (.I0(gpio_out_t_n[53]),
- .O(GPIO_T[53]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[54]_INST_0
- (.I0(gpio_out_t_n[54]),
- .O(GPIO_T[54]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[55]_INST_0
- (.I0(gpio_out_t_n[55]),
- .O(GPIO_T[55]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[56]_INST_0
- (.I0(gpio_out_t_n[56]),
- .O(GPIO_T[56]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[57]_INST_0
- (.I0(gpio_out_t_n[57]),
- .O(GPIO_T[57]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[58]_INST_0
- (.I0(gpio_out_t_n[58]),
- .O(GPIO_T[58]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[59]_INST_0
- (.I0(gpio_out_t_n[59]),
- .O(GPIO_T[59]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[5]_INST_0
- (.I0(gpio_out_t_n[5]),
- .O(GPIO_T[5]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[60]_INST_0
- (.I0(gpio_out_t_n[60]),
- .O(GPIO_T[60]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[61]_INST_0
- (.I0(gpio_out_t_n[61]),
- .O(GPIO_T[61]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[62]_INST_0
- (.I0(gpio_out_t_n[62]),
- .O(GPIO_T[62]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[63]_INST_0
- (.I0(gpio_out_t_n[63]),
- .O(GPIO_T[63]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[6]_INST_0
- (.I0(gpio_out_t_n[6]),
- .O(GPIO_T[6]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[7]_INST_0
- (.I0(gpio_out_t_n[7]),
- .O(GPIO_T[7]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[8]_INST_0
- (.I0(gpio_out_t_n[8]),
- .O(GPIO_T[8]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[9]_INST_0
- (.I0(gpio_out_t_n[9]),
- .O(GPIO_T[9]));
- LUT1 #(
- .INIT(2'h1))
- I2C0_SCL_T_INST_0
- (.I0(I2C0_SCL_T_n),
- .O(I2C0_SCL_T));
- LUT1 #(
- .INIT(2'h1))
- I2C0_SDA_T_INST_0
- (.I0(I2C0_SDA_T_n),
- .O(I2C0_SDA_T));
- LUT1 #(
- .INIT(2'h1))
- I2C1_SCL_T_INST_0
- (.I0(I2C1_SCL_T_n),
- .O(I2C1_SCL_T));
- LUT1 #(
- .INIT(2'h1))
- I2C1_SDA_T_INST_0
- (.I0(I2C1_SDA_T_n),
- .O(I2C1_SDA_T));
- (* BOX_TYPE = "PRIMITIVE" *)
- PS7 PS7_i
- (.DDRA(buffered_DDR_Addr),
- .DDRARB(DDR_ARB),
- .DDRBA(buffered_DDR_BankAddr),
- .DDRCASB(buffered_DDR_CAS_n),
- .DDRCKE(buffered_DDR_CKE),
- .DDRCKN(buffered_DDR_Clk_n),
- .DDRCKP(buffered_DDR_Clk),
- .DDRCSB(buffered_DDR_CS_n),
- .DDRDM(buffered_DDR_DM),
- .DDRDQ(buffered_DDR_DQ),
- .DDRDQSN(buffered_DDR_DQS_n),
- .DDRDQSP(buffered_DDR_DQS),
- .DDRDRSTB(buffered_DDR_DRSTB),
- .DDRODT(buffered_DDR_ODT),
- .DDRRASB(buffered_DDR_RAS_n),
- .DDRVRN(buffered_DDR_VRN),
- .DDRVRP(buffered_DDR_VRP),
- .DDRWEB(buffered_DDR_WEB),
- .DMA0ACLK(DMA0_ACLK),
- .DMA0DAREADY(DMA0_DAREADY),
- .DMA0DATYPE(DMA0_DATYPE),
- .DMA0DAVALID(DMA0_DAVALID),
- .DMA0DRLAST(DMA0_DRLAST),
- .DMA0DRREADY(DMA0_DRREADY),
- .DMA0DRTYPE(DMA0_DRTYPE),
- .DMA0DRVALID(DMA0_DRVALID),
- .DMA0RSTN(DMA0_RSTN),
- .DMA1ACLK(DMA1_ACLK),
- .DMA1DAREADY(DMA1_DAREADY),
- .DMA1DATYPE(DMA1_DATYPE),
- .DMA1DAVALID(DMA1_DAVALID),
- .DMA1DRLAST(DMA1_DRLAST),
- .DMA1DRREADY(DMA1_DRREADY),
- .DMA1DRTYPE(DMA1_DRTYPE),
- .DMA1DRVALID(DMA1_DRVALID),
- .DMA1RSTN(DMA1_RSTN),
- .DMA2ACLK(DMA2_ACLK),
- .DMA2DAREADY(DMA2_DAREADY),
- .DMA2DATYPE(DMA2_DATYPE),
- .DMA2DAVALID(DMA2_DAVALID),
- .DMA2DRLAST(DMA2_DRLAST),
- .DMA2DRREADY(DMA2_DRREADY),
- .DMA2DRTYPE(DMA2_DRTYPE),
- .DMA2DRVALID(DMA2_DRVALID),
- .DMA2RSTN(DMA2_RSTN),
- .DMA3ACLK(DMA3_ACLK),
- .DMA3DAREADY(DMA3_DAREADY),
- .DMA3DATYPE(DMA3_DATYPE),
- .DMA3DAVALID(DMA3_DAVALID),
- .DMA3DRLAST(DMA3_DRLAST),
- .DMA3DRREADY(DMA3_DRREADY),
- .DMA3DRTYPE(DMA3_DRTYPE),
- .DMA3DRVALID(DMA3_DRVALID),
- .DMA3RSTN(DMA3_RSTN),
- .EMIOCAN0PHYRX(CAN0_PHY_RX),
- .EMIOCAN0PHYTX(CAN0_PHY_TX),
- .EMIOCAN1PHYRX(CAN1_PHY_RX),
- .EMIOCAN1PHYTX(CAN1_PHY_TX),
- .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
- .EMIOENET0GMIICOL(1'b0),
- .EMIOENET0GMIICRS(1'b0),
- .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
- .EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .EMIOENET0GMIIRXDV(1'b0),
- .EMIOENET0GMIIRXER(1'b0),
- .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
- .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
- .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
- .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
- .EMIOENET0MDIOI(ENET0_MDIO_I),
- .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
- .EMIOENET0MDIOO(ENET0_MDIO_O),
- .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
- .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
- .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
- .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
- .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
- .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
- .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
- .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
- .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
- .EMIOENET0SOFRX(ENET0_SOF_RX),
- .EMIOENET0SOFTX(ENET0_SOF_TX),
- .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
- .EMIOENET1GMIICOL(1'b0),
- .EMIOENET1GMIICRS(1'b0),
- .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
- .EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .EMIOENET1GMIIRXDV(1'b0),
- .EMIOENET1GMIIRXER(1'b0),
- .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
- .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
- .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
- .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
- .EMIOENET1MDIOI(ENET1_MDIO_I),
- .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
- .EMIOENET1MDIOO(ENET1_MDIO_O),
- .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
- .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
- .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
- .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
- .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
- .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
- .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
- .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
- .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
- .EMIOENET1SOFRX(ENET1_SOF_RX),
- .EMIOENET1SOFTX(ENET1_SOF_TX),
- .EMIOGPIOI(GPIO_I),
- .EMIOGPIOO(GPIO_O),
- .EMIOGPIOTN(gpio_out_t_n),
- .EMIOI2C0SCLI(I2C0_SCL_I),
- .EMIOI2C0SCLO(I2C0_SCL_O),
- .EMIOI2C0SCLTN(I2C0_SCL_T_n),
- .EMIOI2C0SDAI(I2C0_SDA_I),
- .EMIOI2C0SDAO(I2C0_SDA_O),
- .EMIOI2C0SDATN(I2C0_SDA_T_n),
- .EMIOI2C1SCLI(I2C1_SCL_I),
- .EMIOI2C1SCLO(I2C1_SCL_O),
- .EMIOI2C1SCLTN(I2C1_SCL_T_n),
- .EMIOI2C1SDAI(I2C1_SDA_I),
- .EMIOI2C1SDAO(I2C1_SDA_O),
- .EMIOI2C1SDATN(I2C1_SDA_T_n),
- .EMIOPJTAGTCK(PJTAG_TCK),
- .EMIOPJTAGTDI(PJTAG_TDI),
- .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
- .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
- .EMIOPJTAGTMS(PJTAG_TMS),
- .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
- .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
- .EMIOSDIO0CDN(SDIO0_CDN),
- .EMIOSDIO0CLK(SDIO0_CLK),
- .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
- .EMIOSDIO0CMDI(SDIO0_CMD_I),
- .EMIOSDIO0CMDO(SDIO0_CMD_O),
- .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
- .EMIOSDIO0DATAI(SDIO0_DATA_I),
- .EMIOSDIO0DATAO(SDIO0_DATA_O),
- .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
- .EMIOSDIO0LED(SDIO0_LED),
- .EMIOSDIO0WP(SDIO0_WP),
- .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
- .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
- .EMIOSDIO1CDN(SDIO1_CDN),
- .EMIOSDIO1CLK(SDIO1_CLK),
- .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
- .EMIOSDIO1CMDI(SDIO1_CMD_I),
- .EMIOSDIO1CMDO(SDIO1_CMD_O),
- .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
- .EMIOSDIO1DATAI(SDIO1_DATA_I),
- .EMIOSDIO1DATAO(SDIO1_DATA_O),
- .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
- .EMIOSDIO1LED(SDIO1_LED),
- .EMIOSDIO1WP(SDIO1_WP),
- .EMIOSPI0MI(SPI0_MISO_I),
- .EMIOSPI0MO(SPI0_MOSI_O),
- .EMIOSPI0MOTN(SPI0_MOSI_T_n),
- .EMIOSPI0SCLKI(SPI0_SCLK_I),
- .EMIOSPI0SCLKO(SPI0_SCLK_O),
- .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
- .EMIOSPI0SI(SPI0_MOSI_I),
- .EMIOSPI0SO(SPI0_MISO_O),
- .EMIOSPI0SSIN(SPI0_SS_I),
- .EMIOSPI0SSNTN(SPI0_SS_T_n),
- .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
- .EMIOSPI0STN(SPI0_MISO_T_n),
- .EMIOSPI1MI(SPI1_MISO_I),
- .EMIOSPI1MO(SPI1_MOSI_O),
- .EMIOSPI1MOTN(SPI1_MOSI_T_n),
- .EMIOSPI1SCLKI(SPI1_SCLK_I),
- .EMIOSPI1SCLKO(SPI1_SCLK_O),
- .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
- .EMIOSPI1SI(SPI1_MOSI_I),
- .EMIOSPI1SO(SPI1_MISO_O),
- .EMIOSPI1SSIN(SPI1_SS_I),
- .EMIOSPI1SSNTN(SPI1_SS_T_n),
- .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
- .EMIOSPI1STN(SPI1_MISO_T_n),
- .EMIOSRAMINTIN(SRAM_INTIN),
- .EMIOTRACECLK(TRACE_CLK),
- .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
- .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
- .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
- .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
- .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
- .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
- .EMIOUART0CTSN(UART0_CTSN),
- .EMIOUART0DCDN(UART0_DCDN),
- .EMIOUART0DSRN(UART0_DSRN),
- .EMIOUART0DTRN(UART0_DTRN),
- .EMIOUART0RIN(UART0_RIN),
- .EMIOUART0RTSN(UART0_RTSN),
- .EMIOUART0RX(UART0_RX),
- .EMIOUART0TX(UART0_TX),
- .EMIOUART1CTSN(UART1_CTSN),
- .EMIOUART1DCDN(UART1_DCDN),
- .EMIOUART1DSRN(UART1_DSRN),
- .EMIOUART1DTRN(UART1_DTRN),
- .EMIOUART1RIN(UART1_RIN),
- .EMIOUART1RTSN(UART1_RTSN),
- .EMIOUART1RX(UART1_RX),
- .EMIOUART1TX(UART1_TX),
- .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
- .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
- .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
- .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
- .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
- .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
- .EMIOWDTCLKI(WDT_CLK_IN),
- .EMIOWDTRSTO(WDT_RST_OUT),
- .EVENTEVENTI(EVENT_EVENTI),
- .EVENTEVENTO(EVENT_EVENTO),
- .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
- .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
- .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
- .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
- .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
- .FPGAIDLEN(FPGA_IDLE_N),
- .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
- .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
- .FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .FTMDTRACEINVALID(1'b0),
- .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
- .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
- .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
- .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
- .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
- .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
- .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
- .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
- .MAXIGP0ACLK(M_AXI_GP0_ACLK),
- .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
- .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
- .MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
- .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
- .MAXIGP0ARID(M_AXI_GP0_ARID),
- .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
- .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
- .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
- .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
- .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
- .MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
- .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
- .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
- .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
- .MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
- .MAXIGP0AWID(M_AXI_GP0_AWID),
- .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
- .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
- .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
- .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
- .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
- .MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
- .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
- .MAXIGP0BID(M_AXI_GP0_BID),
- .MAXIGP0BREADY(M_AXI_GP0_BREADY),
- .MAXIGP0BRESP(M_AXI_GP0_BRESP),
- .MAXIGP0BVALID(M_AXI_GP0_BVALID),
- .MAXIGP0RDATA(M_AXI_GP0_RDATA),
- .MAXIGP0RID(M_AXI_GP0_RID),
- .MAXIGP0RLAST(M_AXI_GP0_RLAST),
- .MAXIGP0RREADY(M_AXI_GP0_RREADY),
- .MAXIGP0RRESP(M_AXI_GP0_RRESP),
- .MAXIGP0RVALID(M_AXI_GP0_RVALID),
- .MAXIGP0WDATA(M_AXI_GP0_WDATA),
- .MAXIGP0WID(M_AXI_GP0_WID),
- .MAXIGP0WLAST(M_AXI_GP0_WLAST),
- .MAXIGP0WREADY(M_AXI_GP0_WREADY),
- .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
- .MAXIGP0WVALID(M_AXI_GP0_WVALID),
- .MAXIGP1ACLK(M_AXI_GP1_ACLK),
- .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
- .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
- .MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
- .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
- .MAXIGP1ARID(M_AXI_GP1_ARID),
- .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
- .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
- .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
- .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
- .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
- .MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
- .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
- .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
- .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
- .MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
- .MAXIGP1AWID(M_AXI_GP1_AWID),
- .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
- .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
- .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
- .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
- .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
- .MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
- .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
- .MAXIGP1BID(M_AXI_GP1_BID),
- .MAXIGP1BREADY(M_AXI_GP1_BREADY),
- .MAXIGP1BRESP(M_AXI_GP1_BRESP),
- .MAXIGP1BVALID(M_AXI_GP1_BVALID),
- .MAXIGP1RDATA(M_AXI_GP1_RDATA),
- .MAXIGP1RID(M_AXI_GP1_RID),
- .MAXIGP1RLAST(M_AXI_GP1_RLAST),
- .MAXIGP1RREADY(M_AXI_GP1_RREADY),
- .MAXIGP1RRESP(M_AXI_GP1_RRESP),
- .MAXIGP1RVALID(M_AXI_GP1_RVALID),
- .MAXIGP1WDATA(M_AXI_GP1_WDATA),
- .MAXIGP1WID(M_AXI_GP1_WID),
- .MAXIGP1WLAST(M_AXI_GP1_WLAST),
- .MAXIGP1WREADY(M_AXI_GP1_WREADY),
- .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
- .MAXIGP1WVALID(M_AXI_GP1_WVALID),
- .MIO(buffered_MIO),
- .PSCLK(buffered_PS_CLK),
- .PSPORB(buffered_PS_PORB),
- .PSSRSTB(buffered_PS_SRSTB),
- .SAXIACPACLK(S_AXI_ACP_ACLK),
- .SAXIACPARADDR(S_AXI_ACP_ARADDR),
- .SAXIACPARBURST(S_AXI_ACP_ARBURST),
- .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
- .SAXIACPARESETN(S_AXI_ACP_ARESETN),
- .SAXIACPARID(S_AXI_ACP_ARID),
- .SAXIACPARLEN(S_AXI_ACP_ARLEN),
- .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
- .SAXIACPARPROT(S_AXI_ACP_ARPROT),
- .SAXIACPARQOS(S_AXI_ACP_ARQOS),
- .SAXIACPARREADY(S_AXI_ACP_ARREADY),
- .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
- .SAXIACPARUSER(S_AXI_ACP_ARUSER),
- .SAXIACPARVALID(S_AXI_ACP_ARVALID),
- .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
- .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
- .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
- .SAXIACPAWID(S_AXI_ACP_AWID),
- .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
- .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
- .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
- .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
- .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
- .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
- .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
- .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
- .SAXIACPBID(S_AXI_ACP_BID),
- .SAXIACPBREADY(S_AXI_ACP_BREADY),
- .SAXIACPBRESP(S_AXI_ACP_BRESP),
- .SAXIACPBVALID(S_AXI_ACP_BVALID),
- .SAXIACPRDATA(S_AXI_ACP_RDATA),
- .SAXIACPRID(S_AXI_ACP_RID),
- .SAXIACPRLAST(S_AXI_ACP_RLAST),
- .SAXIACPRREADY(S_AXI_ACP_RREADY),
- .SAXIACPRRESP(S_AXI_ACP_RRESP),
- .SAXIACPRVALID(S_AXI_ACP_RVALID),
- .SAXIACPWDATA(S_AXI_ACP_WDATA),
- .SAXIACPWID(S_AXI_ACP_WID),
- .SAXIACPWLAST(S_AXI_ACP_WLAST),
- .SAXIACPWREADY(S_AXI_ACP_WREADY),
- .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
- .SAXIACPWVALID(S_AXI_ACP_WVALID),
- .SAXIGP0ACLK(S_AXI_GP0_ACLK),
- .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
- .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
- .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
- .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
- .SAXIGP0ARID(S_AXI_GP0_ARID),
- .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
- .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
- .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
- .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
- .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
- .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
- .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
- .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
- .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
- .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
- .SAXIGP0AWID(S_AXI_GP0_AWID),
- .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
- .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
- .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
- .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
- .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
- .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
- .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
- .SAXIGP0BID(S_AXI_GP0_BID),
- .SAXIGP0BREADY(S_AXI_GP0_BREADY),
- .SAXIGP0BRESP(S_AXI_GP0_BRESP),
- .SAXIGP0BVALID(S_AXI_GP0_BVALID),
- .SAXIGP0RDATA(S_AXI_GP0_RDATA),
- .SAXIGP0RID(S_AXI_GP0_RID),
- .SAXIGP0RLAST(S_AXI_GP0_RLAST),
- .SAXIGP0RREADY(S_AXI_GP0_RREADY),
- .SAXIGP0RRESP(S_AXI_GP0_RRESP),
- .SAXIGP0RVALID(S_AXI_GP0_RVALID),
- .SAXIGP0WDATA(S_AXI_GP0_WDATA),
- .SAXIGP0WID(S_AXI_GP0_WID),
- .SAXIGP0WLAST(S_AXI_GP0_WLAST),
- .SAXIGP0WREADY(S_AXI_GP0_WREADY),
- .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
- .SAXIGP0WVALID(S_AXI_GP0_WVALID),
- .SAXIGP1ACLK(S_AXI_GP1_ACLK),
- .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
- .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
- .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
- .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
- .SAXIGP1ARID(S_AXI_GP1_ARID),
- .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
- .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
- .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
- .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
- .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
- .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
- .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
- .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
- .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
- .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
- .SAXIGP1AWID(S_AXI_GP1_AWID),
- .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
- .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
- .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
- .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
- .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
- .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
- .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
- .SAXIGP1BID(S_AXI_GP1_BID),
- .SAXIGP1BREADY(S_AXI_GP1_BREADY),
- .SAXIGP1BRESP(S_AXI_GP1_BRESP),
- .SAXIGP1BVALID(S_AXI_GP1_BVALID),
- .SAXIGP1RDATA(S_AXI_GP1_RDATA),
- .SAXIGP1RID(S_AXI_GP1_RID),
- .SAXIGP1RLAST(S_AXI_GP1_RLAST),
- .SAXIGP1RREADY(S_AXI_GP1_RREADY),
- .SAXIGP1RRESP(S_AXI_GP1_RRESP),
- .SAXIGP1RVALID(S_AXI_GP1_RVALID),
- .SAXIGP1WDATA(S_AXI_GP1_WDATA),
- .SAXIGP1WID(S_AXI_GP1_WID),
- .SAXIGP1WLAST(S_AXI_GP1_WLAST),
- .SAXIGP1WREADY(S_AXI_GP1_WREADY),
- .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
- .SAXIGP1WVALID(S_AXI_GP1_WVALID),
- .SAXIHP0ACLK(S_AXI_HP0_ACLK),
- .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
- .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
- .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
- .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
- .SAXIHP0ARID(S_AXI_HP0_ARID),
- .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
- .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
- .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
- .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
- .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
- .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
- .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
- .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
- .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
- .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
- .SAXIHP0AWID(S_AXI_HP0_AWID),
- .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
- .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
- .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
- .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
- .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
- .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
- .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
- .SAXIHP0BID(S_AXI_HP0_BID),
- .SAXIHP0BREADY(S_AXI_HP0_BREADY),
- .SAXIHP0BRESP(S_AXI_HP0_BRESP),
- .SAXIHP0BVALID(S_AXI_HP0_BVALID),
- .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
- .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
- .SAXIHP0RDATA(S_AXI_HP0_RDATA),
- .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
- .SAXIHP0RID(S_AXI_HP0_RID),
- .SAXIHP0RLAST(S_AXI_HP0_RLAST),
- .SAXIHP0RREADY(S_AXI_HP0_RREADY),
- .SAXIHP0RRESP(S_AXI_HP0_RRESP),
- .SAXIHP0RVALID(S_AXI_HP0_RVALID),
- .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
- .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
- .SAXIHP0WDATA(S_AXI_HP0_WDATA),
- .SAXIHP0WID(S_AXI_HP0_WID),
- .SAXIHP0WLAST(S_AXI_HP0_WLAST),
- .SAXIHP0WREADY(S_AXI_HP0_WREADY),
- .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
- .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
- .SAXIHP0WVALID(S_AXI_HP0_WVALID),
- .SAXIHP1ACLK(S_AXI_HP1_ACLK),
- .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
- .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
- .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
- .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
- .SAXIHP1ARID(S_AXI_HP1_ARID),
- .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
- .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
- .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
- .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
- .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
- .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
- .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
- .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
- .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
- .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
- .SAXIHP1AWID(S_AXI_HP1_AWID),
- .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
- .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
- .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
- .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
- .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
- .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
- .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
- .SAXIHP1BID(S_AXI_HP1_BID),
- .SAXIHP1BREADY(S_AXI_HP1_BREADY),
- .SAXIHP1BRESP(S_AXI_HP1_BRESP),
- .SAXIHP1BVALID(S_AXI_HP1_BVALID),
- .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
- .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
- .SAXIHP1RDATA(S_AXI_HP1_RDATA),
- .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
- .SAXIHP1RID(S_AXI_HP1_RID),
- .SAXIHP1RLAST(S_AXI_HP1_RLAST),
- .SAXIHP1RREADY(S_AXI_HP1_RREADY),
- .SAXIHP1RRESP(S_AXI_HP1_RRESP),
- .SAXIHP1RVALID(S_AXI_HP1_RVALID),
- .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
- .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
- .SAXIHP1WDATA(S_AXI_HP1_WDATA),
- .SAXIHP1WID(S_AXI_HP1_WID),
- .SAXIHP1WLAST(S_AXI_HP1_WLAST),
- .SAXIHP1WREADY(S_AXI_HP1_WREADY),
- .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
- .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
- .SAXIHP1WVALID(S_AXI_HP1_WVALID),
- .SAXIHP2ACLK(S_AXI_HP2_ACLK),
- .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
- .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
- .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
- .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
- .SAXIHP2ARID(S_AXI_HP2_ARID),
- .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
- .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
- .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
- .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
- .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
- .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
- .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
- .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
- .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
- .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
- .SAXIHP2AWID(S_AXI_HP2_AWID),
- .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
- .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
- .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
- .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
- .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
- .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
- .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
- .SAXIHP2BID(S_AXI_HP2_BID),
- .SAXIHP2BREADY(S_AXI_HP2_BREADY),
- .SAXIHP2BRESP(S_AXI_HP2_BRESP),
- .SAXIHP2BVALID(S_AXI_HP2_BVALID),
- .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
- .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
- .SAXIHP2RDATA(S_AXI_HP2_RDATA),
- .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
- .SAXIHP2RID(S_AXI_HP2_RID),
- .SAXIHP2RLAST(S_AXI_HP2_RLAST),
- .SAXIHP2RREADY(S_AXI_HP2_RREADY),
- .SAXIHP2RRESP(S_AXI_HP2_RRESP),
- .SAXIHP2RVALID(S_AXI_HP2_RVALID),
- .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
- .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
- .SAXIHP2WDATA(S_AXI_HP2_WDATA),
- .SAXIHP2WID(S_AXI_HP2_WID),
- .SAXIHP2WLAST(S_AXI_HP2_WLAST),
- .SAXIHP2WREADY(S_AXI_HP2_WREADY),
- .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
- .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
- .SAXIHP2WVALID(S_AXI_HP2_WVALID),
- .SAXIHP3ACLK(S_AXI_HP3_ACLK),
- .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
- .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
- .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
- .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
- .SAXIHP3ARID(S_AXI_HP3_ARID),
- .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
- .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
- .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
- .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
- .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
- .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
- .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
- .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
- .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
- .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
- .SAXIHP3AWID(S_AXI_HP3_AWID),
- .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
- .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
- .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
- .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
- .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
- .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
- .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
- .SAXIHP3BID(S_AXI_HP3_BID),
- .SAXIHP3BREADY(S_AXI_HP3_BREADY),
- .SAXIHP3BRESP(S_AXI_HP3_BRESP),
- .SAXIHP3BVALID(S_AXI_HP3_BVALID),
- .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
- .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
- .SAXIHP3RDATA(S_AXI_HP3_RDATA),
- .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
- .SAXIHP3RID(S_AXI_HP3_RID),
- .SAXIHP3RLAST(S_AXI_HP3_RLAST),
- .SAXIHP3RREADY(S_AXI_HP3_RREADY),
- .SAXIHP3RRESP(S_AXI_HP3_RRESP),
- .SAXIHP3RVALID(S_AXI_HP3_RVALID),
- .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
- .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
- .SAXIHP3WDATA(S_AXI_HP3_WDATA),
- .SAXIHP3WID(S_AXI_HP3_WID),
- .SAXIHP3WLAST(S_AXI_HP3_WLAST),
- .SAXIHP3WREADY(S_AXI_HP3_WREADY),
- .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
- .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
- .SAXIHP3WVALID(S_AXI_HP3_WVALID));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF PS_CLK_BIBUF
- (.IO(buffered_PS_CLK),
- .PAD(PS_CLK));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF PS_PORB_BIBUF
- (.IO(buffered_PS_PORB),
- .PAD(PS_PORB));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF PS_SRSTB_BIBUF
- (.IO(buffered_PS_SRSTB),
- .PAD(PS_SRSTB));
- LUT1 #(
- .INIT(2'h1))
- SDIO0_CMD_T_INST_0
- (.I0(SDIO0_CMD_T_n),
- .O(SDIO0_CMD_T));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[0]_INST_0
- (.I0(SDIO0_DATA_T_n[0]),
- .O(SDIO0_DATA_T[0]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[1]_INST_0
- (.I0(SDIO0_DATA_T_n[1]),
- .O(SDIO0_DATA_T[1]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[2]_INST_0
- (.I0(SDIO0_DATA_T_n[2]),
- .O(SDIO0_DATA_T[2]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[3]_INST_0
- (.I0(SDIO0_DATA_T_n[3]),
- .O(SDIO0_DATA_T[3]));
- LUT1 #(
- .INIT(2'h1))
- SDIO1_CMD_T_INST_0
- (.I0(SDIO1_CMD_T_n),
- .O(SDIO1_CMD_T));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[0]_INST_0
- (.I0(SDIO1_DATA_T_n[0]),
- .O(SDIO1_DATA_T[0]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[1]_INST_0
- (.I0(SDIO1_DATA_T_n[1]),
- .O(SDIO1_DATA_T[1]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[2]_INST_0
- (.I0(SDIO1_DATA_T_n[2]),
- .O(SDIO1_DATA_T[2]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[3]_INST_0
- (.I0(SDIO1_DATA_T_n[3]),
- .O(SDIO1_DATA_T[3]));
- LUT1 #(
- .INIT(2'h1))
- SPI0_MISO_T_INST_0
- (.I0(SPI0_MISO_T_n),
- .O(SPI0_MISO_T));
- LUT1 #(
- .INIT(2'h1))
- SPI0_MOSI_T_INST_0
- (.I0(SPI0_MOSI_T_n),
- .O(SPI0_MOSI_T));
- LUT1 #(
- .INIT(2'h1))
- SPI0_SCLK_T_INST_0
- (.I0(SPI0_SCLK_T_n),
- .O(SPI0_SCLK_T));
- LUT1 #(
- .INIT(2'h1))
- SPI0_SS_T_INST_0
- (.I0(SPI0_SS_T_n),
- .O(SPI0_SS_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_MISO_T_INST_0
- (.I0(SPI1_MISO_T_n),
- .O(SPI1_MISO_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_MOSI_T_INST_0
- (.I0(SPI1_MOSI_T_n),
- .O(SPI1_MOSI_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_SCLK_T_INST_0
- (.I0(SPI1_SCLK_T_n),
- .O(SPI1_SCLK_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_SS_T_INST_0
- (.I0(SPI1_SS_T_n),
- .O(SPI1_SS_T));
- VCC VCC
- (.P(\<const1> ));
- (* BOX_TYPE = "PRIMITIVE" *)
- BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
- (.I(FCLK_CLK_unbuffered),
- .O(FCLK_CLK0));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[0].MIO_BIBUF
- (.IO(buffered_MIO[0]),
- .PAD(MIO[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[10].MIO_BIBUF
- (.IO(buffered_MIO[10]),
- .PAD(MIO[10]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[11].MIO_BIBUF
- (.IO(buffered_MIO[11]),
- .PAD(MIO[11]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[12].MIO_BIBUF
- (.IO(buffered_MIO[12]),
- .PAD(MIO[12]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[13].MIO_BIBUF
- (.IO(buffered_MIO[13]),
- .PAD(MIO[13]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[14].MIO_BIBUF
- (.IO(buffered_MIO[14]),
- .PAD(MIO[14]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[15].MIO_BIBUF
- (.IO(buffered_MIO[15]),
- .PAD(MIO[15]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[16].MIO_BIBUF
- (.IO(buffered_MIO[16]),
- .PAD(MIO[16]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[17].MIO_BIBUF
- (.IO(buffered_MIO[17]),
- .PAD(MIO[17]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[18].MIO_BIBUF
- (.IO(buffered_MIO[18]),
- .PAD(MIO[18]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[19].MIO_BIBUF
- (.IO(buffered_MIO[19]),
- .PAD(MIO[19]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[1].MIO_BIBUF
- (.IO(buffered_MIO[1]),
- .PAD(MIO[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[20].MIO_BIBUF
- (.IO(buffered_MIO[20]),
- .PAD(MIO[20]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[21].MIO_BIBUF
- (.IO(buffered_MIO[21]),
- .PAD(MIO[21]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[22].MIO_BIBUF
- (.IO(buffered_MIO[22]),
- .PAD(MIO[22]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[23].MIO_BIBUF
- (.IO(buffered_MIO[23]),
- .PAD(MIO[23]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[24].MIO_BIBUF
- (.IO(buffered_MIO[24]),
- .PAD(MIO[24]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[25].MIO_BIBUF
- (.IO(buffered_MIO[25]),
- .PAD(MIO[25]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[26].MIO_BIBUF
- (.IO(buffered_MIO[26]),
- .PAD(MIO[26]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[27].MIO_BIBUF
- (.IO(buffered_MIO[27]),
- .PAD(MIO[27]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[28].MIO_BIBUF
- (.IO(buffered_MIO[28]),
- .PAD(MIO[28]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[29].MIO_BIBUF
- (.IO(buffered_MIO[29]),
- .PAD(MIO[29]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[2].MIO_BIBUF
- (.IO(buffered_MIO[2]),
- .PAD(MIO[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[30].MIO_BIBUF
- (.IO(buffered_MIO[30]),
- .PAD(MIO[30]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[31].MIO_BIBUF
- (.IO(buffered_MIO[31]),
- .PAD(MIO[31]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[32].MIO_BIBUF
- (.IO(buffered_MIO[32]),
- .PAD(MIO[32]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[33].MIO_BIBUF
- (.IO(buffered_MIO[33]),
- .PAD(MIO[33]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[34].MIO_BIBUF
- (.IO(buffered_MIO[34]),
- .PAD(MIO[34]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[35].MIO_BIBUF
- (.IO(buffered_MIO[35]),
- .PAD(MIO[35]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[36].MIO_BIBUF
- (.IO(buffered_MIO[36]),
- .PAD(MIO[36]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[37].MIO_BIBUF
- (.IO(buffered_MIO[37]),
- .PAD(MIO[37]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[38].MIO_BIBUF
- (.IO(buffered_MIO[38]),
- .PAD(MIO[38]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[39].MIO_BIBUF
- (.IO(buffered_MIO[39]),
- .PAD(MIO[39]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[3].MIO_BIBUF
- (.IO(buffered_MIO[3]),
- .PAD(MIO[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[40].MIO_BIBUF
- (.IO(buffered_MIO[40]),
- .PAD(MIO[40]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[41].MIO_BIBUF
- (.IO(buffered_MIO[41]),
- .PAD(MIO[41]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[42].MIO_BIBUF
- (.IO(buffered_MIO[42]),
- .PAD(MIO[42]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[43].MIO_BIBUF
- (.IO(buffered_MIO[43]),
- .PAD(MIO[43]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[44].MIO_BIBUF
- (.IO(buffered_MIO[44]),
- .PAD(MIO[44]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[45].MIO_BIBUF
- (.IO(buffered_MIO[45]),
- .PAD(MIO[45]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[46].MIO_BIBUF
- (.IO(buffered_MIO[46]),
- .PAD(MIO[46]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[47].MIO_BIBUF
- (.IO(buffered_MIO[47]),
- .PAD(MIO[47]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[48].MIO_BIBUF
- (.IO(buffered_MIO[48]),
- .PAD(MIO[48]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[49].MIO_BIBUF
- (.IO(buffered_MIO[49]),
- .PAD(MIO[49]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[4].MIO_BIBUF
- (.IO(buffered_MIO[4]),
- .PAD(MIO[4]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[50].MIO_BIBUF
- (.IO(buffered_MIO[50]),
- .PAD(MIO[50]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[51].MIO_BIBUF
- (.IO(buffered_MIO[51]),
- .PAD(MIO[51]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[52].MIO_BIBUF
- (.IO(buffered_MIO[52]),
- .PAD(MIO[52]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[53].MIO_BIBUF
- (.IO(buffered_MIO[53]),
- .PAD(MIO[53]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[5].MIO_BIBUF
- (.IO(buffered_MIO[5]),
- .PAD(MIO[5]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[6].MIO_BIBUF
- (.IO(buffered_MIO[6]),
- .PAD(MIO[6]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[7].MIO_BIBUF
- (.IO(buffered_MIO[7]),
- .PAD(MIO[7]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[8].MIO_BIBUF
- (.IO(buffered_MIO[8]),
- .PAD(MIO[8]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[9].MIO_BIBUF
- (.IO(buffered_MIO[9]),
- .PAD(MIO[9]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk14[0].DDR_BankAddr_BIBUF
- (.IO(buffered_DDR_BankAddr[0]),
- .PAD(DDR_BankAddr[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk14[1].DDR_BankAddr_BIBUF
- (.IO(buffered_DDR_BankAddr[1]),
- .PAD(DDR_BankAddr[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk14[2].DDR_BankAddr_BIBUF
- (.IO(buffered_DDR_BankAddr[2]),
- .PAD(DDR_BankAddr[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[0].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[0]),
- .PAD(DDR_Addr[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[10].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[10]),
- .PAD(DDR_Addr[10]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[11].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[11]),
- .PAD(DDR_Addr[11]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[12].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[12]),
- .PAD(DDR_Addr[12]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[13].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[13]),
- .PAD(DDR_Addr[13]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[14].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[14]),
- .PAD(DDR_Addr[14]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[1].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[1]),
- .PAD(DDR_Addr[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[2].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[2]),
- .PAD(DDR_Addr[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[3].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[3]),
- .PAD(DDR_Addr[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[4].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[4]),
- .PAD(DDR_Addr[4]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[5].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[5]),
- .PAD(DDR_Addr[5]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[6].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[6]),
- .PAD(DDR_Addr[6]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[7].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[7]),
- .PAD(DDR_Addr[7]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[8].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[8]),
- .PAD(DDR_Addr[8]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[9].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[9]),
- .PAD(DDR_Addr[9]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[0].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[0]),
- .PAD(DDR_DM[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[1].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[1]),
- .PAD(DDR_DM[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[2].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[2]),
- .PAD(DDR_DM[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[3].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[3]),
- .PAD(DDR_DM[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[0].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[0]),
- .PAD(DDR_DQ[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[10].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[10]),
- .PAD(DDR_DQ[10]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[11].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[11]),
- .PAD(DDR_DQ[11]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[12].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[12]),
- .PAD(DDR_DQ[12]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[13].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[13]),
- .PAD(DDR_DQ[13]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[14].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[14]),
- .PAD(DDR_DQ[14]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[15].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[15]),
- .PAD(DDR_DQ[15]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[16].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[16]),
- .PAD(DDR_DQ[16]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[17].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[17]),
- .PAD(DDR_DQ[17]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[18].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[18]),
- .PAD(DDR_DQ[18]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[19].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[19]),
- .PAD(DDR_DQ[19]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[1].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[1]),
- .PAD(DDR_DQ[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[20].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[20]),
- .PAD(DDR_DQ[20]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[21].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[21]),
- .PAD(DDR_DQ[21]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[22].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[22]),
- .PAD(DDR_DQ[22]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[23].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[23]),
- .PAD(DDR_DQ[23]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[24].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[24]),
- .PAD(DDR_DQ[24]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[25].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[25]),
- .PAD(DDR_DQ[25]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[26].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[26]),
- .PAD(DDR_DQ[26]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[27].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[27]),
- .PAD(DDR_DQ[27]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[28].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[28]),
- .PAD(DDR_DQ[28]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[29].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[29]),
- .PAD(DDR_DQ[29]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[2].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[2]),
- .PAD(DDR_DQ[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[30].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[30]),
- .PAD(DDR_DQ[30]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[31].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[31]),
- .PAD(DDR_DQ[31]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[3].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[3]),
- .PAD(DDR_DQ[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[4].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[4]),
- .PAD(DDR_DQ[4]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[5].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[5]),
- .PAD(DDR_DQ[5]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[6].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[6]),
- .PAD(DDR_DQ[6]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[7].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[7]),
- .PAD(DDR_DQ[7]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[8].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[8]),
- .PAD(DDR_DQ[8]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[9].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[9]),
- .PAD(DDR_DQ[9]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[0].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[0]),
- .PAD(DDR_DQS_n[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[1].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[1]),
- .PAD(DDR_DQS_n[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[2].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[2]),
- .PAD(DDR_DQS_n[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[3].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[3]),
- .PAD(DDR_DQS_n[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[0].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[0]),
- .PAD(DDR_DQS[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[1].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[1]),
- .PAD(DDR_DQS[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[2].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[2]),
- .PAD(DDR_DQS[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[3].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[3]),
- .PAD(DDR_DQS[3]));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[0] ));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[0] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_10
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[7] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_11
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[7] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_12
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[6] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_13
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[6] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_14
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[5] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_15
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[5] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_16
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[4] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_17
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[4] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_18
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[3] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_19
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[3] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_2
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[0] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_20
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[2] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_21
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[2] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_22
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[1] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_23
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[1] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_3
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[7] ));
- LUT1 #(
- .INIT(2'h2))
- i_4
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[6] ));
- LUT1 #(
- .INIT(2'h2))
- i_5
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[5] ));
- LUT1 #(
- .INIT(2'h2))
- i_6
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[4] ));
- LUT1 #(
- .INIT(2'h2))
- i_7
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[3] ));
- LUT1 #(
- .INIT(2'h2))
- i_8
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[2] ));
- LUT1 #(
- .INIT(2'h2))
- i_9
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[1] ));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.v
deleted file mode 100644
index 9f1c3f68abc0821ddc67ba76bba9b3e71799f0e6..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.v
+++ /dev/null
@@ -1,111 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:39 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.v
-// Design : scalp_zynqps_processing_system7_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.2" *)
-module scalp_zynqps_processing_system7_0_0(SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T,
- SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I,
- SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
- USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
- M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
- M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
- M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
- M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
- M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
- M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
- M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
- M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
- DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
- DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
-/* synthesis syn_black_box black_box_pad_pin="SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
- input SPI1_SCLK_I;
- output SPI1_SCLK_O;
- output SPI1_SCLK_T;
- input SPI1_MOSI_I;
- output SPI1_MOSI_O;
- output SPI1_MOSI_T;
- input SPI1_MISO_I;
- output SPI1_MISO_O;
- output SPI1_MISO_T;
- input SPI1_SS_I;
- output SPI1_SS_O;
- output SPI1_SS1_O;
- output SPI1_SS2_O;
- output SPI1_SS_T;
- output [1:0]USB0_PORT_INDCTL;
- output USB0_VBUS_PWRSELECT;
- input USB0_VBUS_PWRFAULT;
- output M_AXI_GP0_ARVALID;
- output M_AXI_GP0_AWVALID;
- output M_AXI_GP0_BREADY;
- output M_AXI_GP0_RREADY;
- output M_AXI_GP0_WLAST;
- output M_AXI_GP0_WVALID;
- output [11:0]M_AXI_GP0_ARID;
- output [11:0]M_AXI_GP0_AWID;
- output [11:0]M_AXI_GP0_WID;
- output [1:0]M_AXI_GP0_ARBURST;
- output [1:0]M_AXI_GP0_ARLOCK;
- output [2:0]M_AXI_GP0_ARSIZE;
- output [1:0]M_AXI_GP0_AWBURST;
- output [1:0]M_AXI_GP0_AWLOCK;
- output [2:0]M_AXI_GP0_AWSIZE;
- output [2:0]M_AXI_GP0_ARPROT;
- output [2:0]M_AXI_GP0_AWPROT;
- output [31:0]M_AXI_GP0_ARADDR;
- output [31:0]M_AXI_GP0_AWADDR;
- output [31:0]M_AXI_GP0_WDATA;
- output [3:0]M_AXI_GP0_ARCACHE;
- output [3:0]M_AXI_GP0_ARLEN;
- output [3:0]M_AXI_GP0_ARQOS;
- output [3:0]M_AXI_GP0_AWCACHE;
- output [3:0]M_AXI_GP0_AWLEN;
- output [3:0]M_AXI_GP0_AWQOS;
- output [3:0]M_AXI_GP0_WSTRB;
- input M_AXI_GP0_ACLK;
- input M_AXI_GP0_ARREADY;
- input M_AXI_GP0_AWREADY;
- input M_AXI_GP0_BVALID;
- input M_AXI_GP0_RLAST;
- input M_AXI_GP0_RVALID;
- input M_AXI_GP0_WREADY;
- input [11:0]M_AXI_GP0_BID;
- input [11:0]M_AXI_GP0_RID;
- input [1:0]M_AXI_GP0_BRESP;
- input [1:0]M_AXI_GP0_RRESP;
- input [31:0]M_AXI_GP0_RDATA;
- output FCLK_CLK0;
- output FCLK_RESET0_N;
- inout [53:0]MIO;
- inout DDR_CAS_n;
- inout DDR_CKE;
- inout DDR_Clk_n;
- inout DDR_Clk;
- inout DDR_CS_n;
- inout DDR_DRSTB;
- inout DDR_ODT;
- inout DDR_RAS_n;
- inout DDR_WEB;
- inout [2:0]DDR_BankAddr;
- inout [14:0]DDR_Addr;
- inout DDR_VRN;
- inout DDR_VRP;
- inout [3:0]DDR_DM;
- inout [31:0]DDR_DQ;
- inout [3:0]DDR_DQS_n;
- inout [3:0]DDR_DQS;
- inout PS_SRSTB;
- inout PS_CLK;
- inout PS_PORB;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100644
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v
deleted file mode 100644
index 561083ed29e20fa15b7673a7dc2201820954d69d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v
+++ /dev/null
@@ -1,612 +0,0 @@
-
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-
-`timescale 1ns/1ps
-
-module scalp_zynqps_processing_system7_0_0 (
-SPI1_SCLK_I,
-SPI1_SCLK_O,
-SPI1_SCLK_T,
-SPI1_MOSI_I,
-SPI1_MOSI_O,
-SPI1_MOSI_T,
-SPI1_MISO_I,
-SPI1_MISO_O,
-SPI1_MISO_T,
-SPI1_SS_I,
-SPI1_SS_O,
-SPI1_SS1_O,
-SPI1_SS2_O,
-SPI1_SS_T,
-USB0_PORT_INDCTL,
-USB0_VBUS_PWRSELECT,
-USB0_VBUS_PWRFAULT,
-M_AXI_GP0_ARVALID,
-M_AXI_GP0_AWVALID,
-M_AXI_GP0_BREADY,
-M_AXI_GP0_RREADY,
-M_AXI_GP0_WLAST,
-M_AXI_GP0_WVALID,
-M_AXI_GP0_ARID,
-M_AXI_GP0_AWID,
-M_AXI_GP0_WID,
-M_AXI_GP0_ARBURST,
-M_AXI_GP0_ARLOCK,
-M_AXI_GP0_ARSIZE,
-M_AXI_GP0_AWBURST,
-M_AXI_GP0_AWLOCK,
-M_AXI_GP0_AWSIZE,
-M_AXI_GP0_ARPROT,
-M_AXI_GP0_AWPROT,
-M_AXI_GP0_ARADDR,
-M_AXI_GP0_AWADDR,
-M_AXI_GP0_WDATA,
-M_AXI_GP0_ARCACHE,
-M_AXI_GP0_ARLEN,
-M_AXI_GP0_ARQOS,
-M_AXI_GP0_AWCACHE,
-M_AXI_GP0_AWLEN,
-M_AXI_GP0_AWQOS,
-M_AXI_GP0_WSTRB,
-M_AXI_GP0_ACLK,
-M_AXI_GP0_ARREADY,
-M_AXI_GP0_AWREADY,
-M_AXI_GP0_BVALID,
-M_AXI_GP0_RLAST,
-M_AXI_GP0_RVALID,
-M_AXI_GP0_WREADY,
-M_AXI_GP0_BID,
-M_AXI_GP0_RID,
-M_AXI_GP0_BRESP,
-M_AXI_GP0_RRESP,
-M_AXI_GP0_RDATA,
-FCLK_CLK0,
-FCLK_RESET0_N,
-MIO,
-DDR_CAS_n,
-DDR_CKE,
-DDR_Clk_n,
-DDR_Clk,
-DDR_CS_n,
-DDR_DRSTB,
-DDR_ODT,
-DDR_RAS_n,
-DDR_WEB,
-DDR_BankAddr,
-DDR_Addr,
-DDR_VRN,
-DDR_VRP,
-DDR_DM,
-DDR_DQ,
-DDR_DQS_n,
-DDR_DQS,
-PS_SRSTB,
-PS_CLK,
-PS_PORB
-);
-input SPI1_SCLK_I;
-output SPI1_SCLK_O;
-output SPI1_SCLK_T;
-input SPI1_MOSI_I;
-output SPI1_MOSI_O;
-output SPI1_MOSI_T;
-input SPI1_MISO_I;
-output SPI1_MISO_O;
-output SPI1_MISO_T;
-input SPI1_SS_I;
-output SPI1_SS_O;
-output SPI1_SS1_O;
-output SPI1_SS2_O;
-output SPI1_SS_T;
-output [1 : 0] USB0_PORT_INDCTL;
-output USB0_VBUS_PWRSELECT;
-input USB0_VBUS_PWRFAULT;
-output M_AXI_GP0_ARVALID;
-output M_AXI_GP0_AWVALID;
-output M_AXI_GP0_BREADY;
-output M_AXI_GP0_RREADY;
-output M_AXI_GP0_WLAST;
-output M_AXI_GP0_WVALID;
-output [11 : 0] M_AXI_GP0_ARID;
-output [11 : 0] M_AXI_GP0_AWID;
-output [11 : 0] M_AXI_GP0_WID;
-output [1 : 0] M_AXI_GP0_ARBURST;
-output [1 : 0] M_AXI_GP0_ARLOCK;
-output [2 : 0] M_AXI_GP0_ARSIZE;
-output [1 : 0] M_AXI_GP0_AWBURST;
-output [1 : 0] M_AXI_GP0_AWLOCK;
-output [2 : 0] M_AXI_GP0_AWSIZE;
-output [2 : 0] M_AXI_GP0_ARPROT;
-output [2 : 0] M_AXI_GP0_AWPROT;
-output [31 : 0] M_AXI_GP0_ARADDR;
-output [31 : 0] M_AXI_GP0_AWADDR;
-output [31 : 0] M_AXI_GP0_WDATA;
-output [3 : 0] M_AXI_GP0_ARCACHE;
-output [3 : 0] M_AXI_GP0_ARLEN;
-output [3 : 0] M_AXI_GP0_ARQOS;
-output [3 : 0] M_AXI_GP0_AWCACHE;
-output [3 : 0] M_AXI_GP0_AWLEN;
-output [3 : 0] M_AXI_GP0_AWQOS;
-output [3 : 0] M_AXI_GP0_WSTRB;
-input M_AXI_GP0_ACLK;
-input M_AXI_GP0_ARREADY;
-input M_AXI_GP0_AWREADY;
-input M_AXI_GP0_BVALID;
-input M_AXI_GP0_RLAST;
-input M_AXI_GP0_RVALID;
-input M_AXI_GP0_WREADY;
-input [11 : 0] M_AXI_GP0_BID;
-input [11 : 0] M_AXI_GP0_RID;
-input [1 : 0] M_AXI_GP0_BRESP;
-input [1 : 0] M_AXI_GP0_RRESP;
-input [31 : 0] M_AXI_GP0_RDATA;
-output FCLK_CLK0;
-output FCLK_RESET0_N;
-input [53 : 0] MIO;
-input DDR_CAS_n;
-input DDR_CKE;
-input DDR_Clk_n;
-input DDR_Clk;
-input DDR_CS_n;
-input DDR_DRSTB;
-input DDR_ODT;
-input DDR_RAS_n;
-input DDR_WEB;
-input [2 : 0] DDR_BankAddr;
-input [14 : 0] DDR_Addr;
-input DDR_VRN;
-input DDR_VRP;
-input [3 : 0] DDR_DM;
-input [31 : 0] DDR_DQ;
-input [3 : 0] DDR_DQS_n;
-input [3 : 0] DDR_DQS;
-input PS_SRSTB;
-input PS_CLK;
-input PS_PORB;
-
- processing_system7_vip_v1_0_8 #(
- .C_USE_M_AXI_GP0(1),
- .C_USE_M_AXI_GP1(0),
- .C_USE_S_AXI_ACP(0),
- .C_USE_S_AXI_GP0(0),
- .C_USE_S_AXI_GP1(0),
- .C_USE_S_AXI_HP0(0),
- .C_USE_S_AXI_HP1(0),
- .C_USE_S_AXI_HP2(0),
- .C_USE_S_AXI_HP3(0),
- .C_S_AXI_HP0_DATA_WIDTH(64),
- .C_S_AXI_HP1_DATA_WIDTH(64),
- .C_S_AXI_HP2_DATA_WIDTH(64),
- .C_S_AXI_HP3_DATA_WIDTH(64),
- .C_HIGH_OCM_EN(0),
- .C_FCLK_CLK0_FREQ(125.0),
- .C_FCLK_CLK1_FREQ(10.0),
- .C_FCLK_CLK2_FREQ(10.0),
- .C_FCLK_CLK3_FREQ(10.0),
- .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
- .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
- .C_M_AXI_GP0_THREAD_ID_WIDTH (12),
- .C_M_AXI_GP1_THREAD_ID_WIDTH (12)
- ) inst (
- .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
- .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
- .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
- .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
- .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
- .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
- .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
- .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
- .M_AXI_GP0_WID(M_AXI_GP0_WID),
- .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
- .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
- .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
- .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
- .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
- .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
- .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
- .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
- .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
- .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
- .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
- .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
- .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
- .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
- .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
- .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
- .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
- .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
- .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
- .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
- .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
- .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
- .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
- .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
- .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
- .M_AXI_GP0_BID(M_AXI_GP0_BID),
- .M_AXI_GP0_RID(M_AXI_GP0_RID),
- .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
- .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
- .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
- .M_AXI_GP1_ARVALID(),
- .M_AXI_GP1_AWVALID(),
- .M_AXI_GP1_BREADY(),
- .M_AXI_GP1_RREADY(),
- .M_AXI_GP1_WLAST(),
- .M_AXI_GP1_WVALID(),
- .M_AXI_GP1_ARID(),
- .M_AXI_GP1_AWID(),
- .M_AXI_GP1_WID(),
- .M_AXI_GP1_ARBURST(),
- .M_AXI_GP1_ARLOCK(),
- .M_AXI_GP1_ARSIZE(),
- .M_AXI_GP1_AWBURST(),
- .M_AXI_GP1_AWLOCK(),
- .M_AXI_GP1_AWSIZE(),
- .M_AXI_GP1_ARPROT(),
- .M_AXI_GP1_AWPROT(),
- .M_AXI_GP1_ARADDR(),
- .M_AXI_GP1_AWADDR(),
- .M_AXI_GP1_WDATA(),
- .M_AXI_GP1_ARCACHE(),
- .M_AXI_GP1_ARLEN(),
- .M_AXI_GP1_ARQOS(),
- .M_AXI_GP1_AWCACHE(),
- .M_AXI_GP1_AWLEN(),
- .M_AXI_GP1_AWQOS(),
- .M_AXI_GP1_WSTRB(),
- .M_AXI_GP1_ACLK(1'B0),
- .M_AXI_GP1_ARREADY(1'B0),
- .M_AXI_GP1_AWREADY(1'B0),
- .M_AXI_GP1_BVALID(1'B0),
- .M_AXI_GP1_RLAST(1'B0),
- .M_AXI_GP1_RVALID(1'B0),
- .M_AXI_GP1_WREADY(1'B0),
- .M_AXI_GP1_BID(12'B0),
- .M_AXI_GP1_RID(12'B0),
- .M_AXI_GP1_BRESP(2'B0),
- .M_AXI_GP1_RRESP(2'B0),
- .M_AXI_GP1_RDATA(32'B0),
- .S_AXI_GP0_ARREADY(),
- .S_AXI_GP0_AWREADY(),
- .S_AXI_GP0_BVALID(),
- .S_AXI_GP0_RLAST(),
- .S_AXI_GP0_RVALID(),
- .S_AXI_GP0_WREADY(),
- .S_AXI_GP0_BRESP(),
- .S_AXI_GP0_RRESP(),
- .S_AXI_GP0_RDATA(),
- .S_AXI_GP0_BID(),
- .S_AXI_GP0_RID(),
- .S_AXI_GP0_ACLK(1'B0),
- .S_AXI_GP0_ARVALID(1'B0),
- .S_AXI_GP0_AWVALID(1'B0),
- .S_AXI_GP0_BREADY(1'B0),
- .S_AXI_GP0_RREADY(1'B0),
- .S_AXI_GP0_WLAST(1'B0),
- .S_AXI_GP0_WVALID(1'B0),
- .S_AXI_GP0_ARBURST(2'B0),
- .S_AXI_GP0_ARLOCK(2'B0),
- .S_AXI_GP0_ARSIZE(3'B0),
- .S_AXI_GP0_AWBURST(2'B0),
- .S_AXI_GP0_AWLOCK(2'B0),
- .S_AXI_GP0_AWSIZE(3'B0),
- .S_AXI_GP0_ARPROT(3'B0),
- .S_AXI_GP0_AWPROT(3'B0),
- .S_AXI_GP0_ARADDR(32'B0),
- .S_AXI_GP0_AWADDR(32'B0),
- .S_AXI_GP0_WDATA(32'B0),
- .S_AXI_GP0_ARCACHE(4'B0),
- .S_AXI_GP0_ARLEN(4'B0),
- .S_AXI_GP0_ARQOS(4'B0),
- .S_AXI_GP0_AWCACHE(4'B0),
- .S_AXI_GP0_AWLEN(4'B0),
- .S_AXI_GP0_AWQOS(4'B0),
- .S_AXI_GP0_WSTRB(4'B0),
- .S_AXI_GP0_ARID(6'B0),
- .S_AXI_GP0_AWID(6'B0),
- .S_AXI_GP0_WID(6'B0),
- .S_AXI_GP1_ARREADY(),
- .S_AXI_GP1_AWREADY(),
- .S_AXI_GP1_BVALID(),
- .S_AXI_GP1_RLAST(),
- .S_AXI_GP1_RVALID(),
- .S_AXI_GP1_WREADY(),
- .S_AXI_GP1_BRESP(),
- .S_AXI_GP1_RRESP(),
- .S_AXI_GP1_RDATA(),
- .S_AXI_GP1_BID(),
- .S_AXI_GP1_RID(),
- .S_AXI_GP1_ACLK(1'B0),
- .S_AXI_GP1_ARVALID(1'B0),
- .S_AXI_GP1_AWVALID(1'B0),
- .S_AXI_GP1_BREADY(1'B0),
- .S_AXI_GP1_RREADY(1'B0),
- .S_AXI_GP1_WLAST(1'B0),
- .S_AXI_GP1_WVALID(1'B0),
- .S_AXI_GP1_ARBURST(2'B0),
- .S_AXI_GP1_ARLOCK(2'B0),
- .S_AXI_GP1_ARSIZE(3'B0),
- .S_AXI_GP1_AWBURST(2'B0),
- .S_AXI_GP1_AWLOCK(2'B0),
- .S_AXI_GP1_AWSIZE(3'B0),
- .S_AXI_GP1_ARPROT(3'B0),
- .S_AXI_GP1_AWPROT(3'B0),
- .S_AXI_GP1_ARADDR(32'B0),
- .S_AXI_GP1_AWADDR(32'B0),
- .S_AXI_GP1_WDATA(32'B0),
- .S_AXI_GP1_ARCACHE(4'B0),
- .S_AXI_GP1_ARLEN(4'B0),
- .S_AXI_GP1_ARQOS(4'B0),
- .S_AXI_GP1_AWCACHE(4'B0),
- .S_AXI_GP1_AWLEN(4'B0),
- .S_AXI_GP1_AWQOS(4'B0),
- .S_AXI_GP1_WSTRB(4'B0),
- .S_AXI_GP1_ARID(6'B0),
- .S_AXI_GP1_AWID(6'B0),
- .S_AXI_GP1_WID(6'B0),
- .S_AXI_ACP_ARREADY(),
- .S_AXI_ACP_AWREADY(),
- .S_AXI_ACP_BVALID(),
- .S_AXI_ACP_RLAST(),
- .S_AXI_ACP_RVALID(),
- .S_AXI_ACP_WREADY(),
- .S_AXI_ACP_BRESP(),
- .S_AXI_ACP_RRESP(),
- .S_AXI_ACP_BID(),
- .S_AXI_ACP_RID(),
- .S_AXI_ACP_RDATA(),
- .S_AXI_ACP_ACLK(1'B0),
- .S_AXI_ACP_ARVALID(1'B0),
- .S_AXI_ACP_AWVALID(1'B0),
- .S_AXI_ACP_BREADY(1'B0),
- .S_AXI_ACP_RREADY(1'B0),
- .S_AXI_ACP_WLAST(1'B0),
- .S_AXI_ACP_WVALID(1'B0),
- .S_AXI_ACP_ARID(3'B0),
- .S_AXI_ACP_ARPROT(3'B0),
- .S_AXI_ACP_AWID(3'B0),
- .S_AXI_ACP_AWPROT(3'B0),
- .S_AXI_ACP_WID(3'B0),
- .S_AXI_ACP_ARADDR(32'B0),
- .S_AXI_ACP_AWADDR(32'B0),
- .S_AXI_ACP_ARCACHE(4'B0),
- .S_AXI_ACP_ARLEN(4'B0),
- .S_AXI_ACP_ARQOS(4'B0),
- .S_AXI_ACP_AWCACHE(4'B0),
- .S_AXI_ACP_AWLEN(4'B0),
- .S_AXI_ACP_AWQOS(4'B0),
- .S_AXI_ACP_ARBURST(2'B0),
- .S_AXI_ACP_ARLOCK(2'B0),
- .S_AXI_ACP_ARSIZE(3'B0),
- .S_AXI_ACP_AWBURST(2'B0),
- .S_AXI_ACP_AWLOCK(2'B0),
- .S_AXI_ACP_AWSIZE(3'B0),
- .S_AXI_ACP_ARUSER(5'B0),
- .S_AXI_ACP_AWUSER(5'B0),
- .S_AXI_ACP_WDATA(64'B0),
- .S_AXI_ACP_WSTRB(8'B0),
- .S_AXI_HP0_ARREADY(),
- .S_AXI_HP0_AWREADY(),
- .S_AXI_HP0_BVALID(),
- .S_AXI_HP0_RLAST(),
- .S_AXI_HP0_RVALID(),
- .S_AXI_HP0_WREADY(),
- .S_AXI_HP0_BRESP(),
- .S_AXI_HP0_RRESP(),
- .S_AXI_HP0_BID(),
- .S_AXI_HP0_RID(),
- .S_AXI_HP0_RDATA(),
- .S_AXI_HP0_ACLK(1'B0),
- .S_AXI_HP0_ARVALID(1'B0),
- .S_AXI_HP0_AWVALID(1'B0),
- .S_AXI_HP0_BREADY(1'B0),
- .S_AXI_HP0_RREADY(1'B0),
- .S_AXI_HP0_WLAST(1'B0),
- .S_AXI_HP0_WVALID(1'B0),
- .S_AXI_HP0_ARBURST(2'B0),
- .S_AXI_HP0_ARLOCK(2'B0),
- .S_AXI_HP0_ARSIZE(3'B0),
- .S_AXI_HP0_AWBURST(2'B0),
- .S_AXI_HP0_AWLOCK(2'B0),
- .S_AXI_HP0_AWSIZE(3'B0),
- .S_AXI_HP0_ARPROT(3'B0),
- .S_AXI_HP0_AWPROT(3'B0),
- .S_AXI_HP0_ARADDR(32'B0),
- .S_AXI_HP0_AWADDR(32'B0),
- .S_AXI_HP0_ARCACHE(4'B0),
- .S_AXI_HP0_ARLEN(4'B0),
- .S_AXI_HP0_ARQOS(4'B0),
- .S_AXI_HP0_AWCACHE(4'B0),
- .S_AXI_HP0_AWLEN(4'B0),
- .S_AXI_HP0_AWQOS(4'B0),
- .S_AXI_HP0_ARID(6'B0),
- .S_AXI_HP0_AWID(6'B0),
- .S_AXI_HP0_WID(6'B0),
- .S_AXI_HP0_WDATA(64'B0),
- .S_AXI_HP0_WSTRB(8'B0),
- .S_AXI_HP1_ARREADY(),
- .S_AXI_HP1_AWREADY(),
- .S_AXI_HP1_BVALID(),
- .S_AXI_HP1_RLAST(),
- .S_AXI_HP1_RVALID(),
- .S_AXI_HP1_WREADY(),
- .S_AXI_HP1_BRESP(),
- .S_AXI_HP1_RRESP(),
- .S_AXI_HP1_BID(),
- .S_AXI_HP1_RID(),
- .S_AXI_HP1_RDATA(),
- .S_AXI_HP1_ACLK(1'B0),
- .S_AXI_HP1_ARVALID(1'B0),
- .S_AXI_HP1_AWVALID(1'B0),
- .S_AXI_HP1_BREADY(1'B0),
- .S_AXI_HP1_RREADY(1'B0),
- .S_AXI_HP1_WLAST(1'B0),
- .S_AXI_HP1_WVALID(1'B0),
- .S_AXI_HP1_ARBURST(2'B0),
- .S_AXI_HP1_ARLOCK(2'B0),
- .S_AXI_HP1_ARSIZE(3'B0),
- .S_AXI_HP1_AWBURST(2'B0),
- .S_AXI_HP1_AWLOCK(2'B0),
- .S_AXI_HP1_AWSIZE(3'B0),
- .S_AXI_HP1_ARPROT(3'B0),
- .S_AXI_HP1_AWPROT(3'B0),
- .S_AXI_HP1_ARADDR(32'B0),
- .S_AXI_HP1_AWADDR(32'B0),
- .S_AXI_HP1_ARCACHE(4'B0),
- .S_AXI_HP1_ARLEN(4'B0),
- .S_AXI_HP1_ARQOS(4'B0),
- .S_AXI_HP1_AWCACHE(4'B0),
- .S_AXI_HP1_AWLEN(4'B0),
- .S_AXI_HP1_AWQOS(4'B0),
- .S_AXI_HP1_ARID(6'B0),
- .S_AXI_HP1_AWID(6'B0),
- .S_AXI_HP1_WID(6'B0),
- .S_AXI_HP1_WDATA(64'B0),
- .S_AXI_HP1_WSTRB(8'B0),
- .S_AXI_HP2_ARREADY(),
- .S_AXI_HP2_AWREADY(),
- .S_AXI_HP2_BVALID(),
- .S_AXI_HP2_RLAST(),
- .S_AXI_HP2_RVALID(),
- .S_AXI_HP2_WREADY(),
- .S_AXI_HP2_BRESP(),
- .S_AXI_HP2_RRESP(),
- .S_AXI_HP2_BID(),
- .S_AXI_HP2_RID(),
- .S_AXI_HP2_RDATA(),
- .S_AXI_HP2_ACLK(1'B0),
- .S_AXI_HP2_ARVALID(1'B0),
- .S_AXI_HP2_AWVALID(1'B0),
- .S_AXI_HP2_BREADY(1'B0),
- .S_AXI_HP2_RREADY(1'B0),
- .S_AXI_HP2_WLAST(1'B0),
- .S_AXI_HP2_WVALID(1'B0),
- .S_AXI_HP2_ARBURST(2'B0),
- .S_AXI_HP2_ARLOCK(2'B0),
- .S_AXI_HP2_ARSIZE(3'B0),
- .S_AXI_HP2_AWBURST(2'B0),
- .S_AXI_HP2_AWLOCK(2'B0),
- .S_AXI_HP2_AWSIZE(3'B0),
- .S_AXI_HP2_ARPROT(3'B0),
- .S_AXI_HP2_AWPROT(3'B0),
- .S_AXI_HP2_ARADDR(32'B0),
- .S_AXI_HP2_AWADDR(32'B0),
- .S_AXI_HP2_ARCACHE(4'B0),
- .S_AXI_HP2_ARLEN(4'B0),
- .S_AXI_HP2_ARQOS(4'B0),
- .S_AXI_HP2_AWCACHE(4'B0),
- .S_AXI_HP2_AWLEN(4'B0),
- .S_AXI_HP2_AWQOS(4'B0),
- .S_AXI_HP2_ARID(6'B0),
- .S_AXI_HP2_AWID(6'B0),
- .S_AXI_HP2_WID(6'B0),
- .S_AXI_HP2_WDATA(64'B0),
- .S_AXI_HP2_WSTRB(8'B0),
- .S_AXI_HP3_ARREADY(),
- .S_AXI_HP3_AWREADY(),
- .S_AXI_HP3_BVALID(),
- .S_AXI_HP3_RLAST(),
- .S_AXI_HP3_RVALID(),
- .S_AXI_HP3_WREADY(),
- .S_AXI_HP3_BRESP(),
- .S_AXI_HP3_RRESP(),
- .S_AXI_HP3_BID(),
- .S_AXI_HP3_RID(),
- .S_AXI_HP3_RDATA(),
- .S_AXI_HP3_ACLK(1'B0),
- .S_AXI_HP3_ARVALID(1'B0),
- .S_AXI_HP3_AWVALID(1'B0),
- .S_AXI_HP3_BREADY(1'B0),
- .S_AXI_HP3_RREADY(1'B0),
- .S_AXI_HP3_WLAST(1'B0),
- .S_AXI_HP3_WVALID(1'B0),
- .S_AXI_HP3_ARBURST(2'B0),
- .S_AXI_HP3_ARLOCK(2'B0),
- .S_AXI_HP3_ARSIZE(3'B0),
- .S_AXI_HP3_AWBURST(2'B0),
- .S_AXI_HP3_AWLOCK(2'B0),
- .S_AXI_HP3_AWSIZE(3'B0),
- .S_AXI_HP3_ARPROT(3'B0),
- .S_AXI_HP3_AWPROT(3'B0),
- .S_AXI_HP3_ARADDR(32'B0),
- .S_AXI_HP3_AWADDR(32'B0),
- .S_AXI_HP3_ARCACHE(4'B0),
- .S_AXI_HP3_ARLEN(4'B0),
- .S_AXI_HP3_ARQOS(4'B0),
- .S_AXI_HP3_AWCACHE(4'B0),
- .S_AXI_HP3_AWLEN(4'B0),
- .S_AXI_HP3_AWQOS(4'B0),
- .S_AXI_HP3_ARID(6'B0),
- .S_AXI_HP3_AWID(6'B0),
- .S_AXI_HP3_WID(6'B0),
- .S_AXI_HP3_WDATA(64'B0),
- .S_AXI_HP3_WSTRB(8'B0),
- .FCLK_CLK0(FCLK_CLK0),
-
- .FCLK_CLK1(),
-
- .FCLK_CLK2(),
-
- .FCLK_CLK3(),
- .FCLK_RESET0_N(FCLK_RESET0_N),
- .FCLK_RESET1_N(),
- .FCLK_RESET2_N(),
- .FCLK_RESET3_N(),
- .IRQ_F2P(16'B0),
- .PS_SRSTB(PS_SRSTB),
- .PS_CLK(PS_CLK),
- .PS_PORB(PS_PORB)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100644
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h
deleted file mode 100644
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim_tlm/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/synth/scalp_zynqps_processing_system7_0_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/synth/scalp_zynqps_processing_system7_0_0.v
deleted file mode 100644
index 539eab09f6928b3bd233880ca3b77ec335ed1f9a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/synth/scalp_zynqps_processing_system7_0_0.v
+++ /dev/null
@@ -1,1039 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7:5.5
-// IP Revision: 6
-
-(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.2" *)
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
-(* CORE_GENERATION_INFO = "scalp_zynqps_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_C\
-HECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,\
-C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg485,C_GP0_EN_MODIFIABLE_T\
-XN=1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_processing_system7_0_0 (
- SPI1_SCLK_I,
- SPI1_SCLK_O,
- SPI1_SCLK_T,
- SPI1_MOSI_I,
- SPI1_MOSI_O,
- SPI1_MOSI_T,
- SPI1_MISO_I,
- SPI1_MISO_O,
- SPI1_MISO_T,
- SPI1_SS_I,
- SPI1_SS_O,
- SPI1_SS1_O,
- SPI1_SS2_O,
- SPI1_SS_T,
- USB0_PORT_INDCTL,
- USB0_VBUS_PWRSELECT,
- USB0_VBUS_PWRFAULT,
- M_AXI_GP0_ARVALID,
- M_AXI_GP0_AWVALID,
- M_AXI_GP0_BREADY,
- M_AXI_GP0_RREADY,
- M_AXI_GP0_WLAST,
- M_AXI_GP0_WVALID,
- M_AXI_GP0_ARID,
- M_AXI_GP0_AWID,
- M_AXI_GP0_WID,
- M_AXI_GP0_ARBURST,
- M_AXI_GP0_ARLOCK,
- M_AXI_GP0_ARSIZE,
- M_AXI_GP0_AWBURST,
- M_AXI_GP0_AWLOCK,
- M_AXI_GP0_AWSIZE,
- M_AXI_GP0_ARPROT,
- M_AXI_GP0_AWPROT,
- M_AXI_GP0_ARADDR,
- M_AXI_GP0_AWADDR,
- M_AXI_GP0_WDATA,
- M_AXI_GP0_ARCACHE,
- M_AXI_GP0_ARLEN,
- M_AXI_GP0_ARQOS,
- M_AXI_GP0_AWCACHE,
- M_AXI_GP0_AWLEN,
- M_AXI_GP0_AWQOS,
- M_AXI_GP0_WSTRB,
- M_AXI_GP0_ACLK,
- M_AXI_GP0_ARREADY,
- M_AXI_GP0_AWREADY,
- M_AXI_GP0_BVALID,
- M_AXI_GP0_RLAST,
- M_AXI_GP0_RVALID,
- M_AXI_GP0_WREADY,
- M_AXI_GP0_BID,
- M_AXI_GP0_RID,
- M_AXI_GP0_BRESP,
- M_AXI_GP0_RRESP,
- M_AXI_GP0_RDATA,
- FCLK_CLK0,
- FCLK_RESET0_N,
- MIO,
- DDR_CAS_n,
- DDR_CKE,
- DDR_Clk_n,
- DDR_Clk,
- DDR_CS_n,
- DDR_DRSTB,
- DDR_ODT,
- DDR_RAS_n,
- DDR_WEB,
- DDR_BankAddr,
- DDR_Addr,
- DDR_VRN,
- DDR_VRP,
- DDR_DM,
- DDR_DQ,
- DDR_DQS_n,
- DDR_DQS,
- PS_SRSTB,
- PS_CLK,
- PS_PORB
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *)
-input wire SPI1_SCLK_I;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *)
-output wire SPI1_SCLK_O;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *)
-output wire SPI1_SCLK_T;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *)
-input wire SPI1_MOSI_I;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *)
-output wire SPI1_MOSI_O;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *)
-output wire SPI1_MOSI_T;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *)
-input wire SPI1_MISO_I;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *)
-output wire SPI1_MISO_O;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *)
-output wire SPI1_MISO_T;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *)
-input wire SPI1_SS_I;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *)
-output wire SPI1_SS_O;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *)
-output wire SPI1_SS1_O;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *)
-output wire SPI1_SS2_O;
-(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *)
-output wire SPI1_SS_T;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
-output wire [1 : 0] USB0_PORT_INDCTL;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
-output wire USB0_VBUS_PWRSELECT;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
-input wire USB0_VBUS_PWRFAULT;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
-output wire M_AXI_GP0_ARVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
-output wire M_AXI_GP0_AWVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
-output wire M_AXI_GP0_BREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
-output wire M_AXI_GP0_RREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
-output wire M_AXI_GP0_WLAST;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
-output wire M_AXI_GP0_WVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
-output wire [11 : 0] M_AXI_GP0_ARID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
-output wire [11 : 0] M_AXI_GP0_AWID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
-output wire [11 : 0] M_AXI_GP0_WID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
-output wire [1 : 0] M_AXI_GP0_ARBURST;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
-output wire [1 : 0] M_AXI_GP0_ARLOCK;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
-output wire [2 : 0] M_AXI_GP0_ARSIZE;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
-output wire [1 : 0] M_AXI_GP0_AWBURST;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
-output wire [1 : 0] M_AXI_GP0_AWLOCK;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
-output wire [2 : 0] M_AXI_GP0_AWSIZE;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
-output wire [2 : 0] M_AXI_GP0_ARPROT;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
-output wire [2 : 0] M_AXI_GP0_AWPROT;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
-output wire [31 : 0] M_AXI_GP0_ARADDR;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
-output wire [31 : 0] M_AXI_GP0_AWADDR;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
-output wire [31 : 0] M_AXI_GP0_WDATA;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
-output wire [3 : 0] M_AXI_GP0_ARCACHE;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
-output wire [3 : 0] M_AXI_GP0_ARLEN;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
-output wire [3 : 0] M_AXI_GP0_ARQOS;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
-output wire [3 : 0] M_AXI_GP0_AWCACHE;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
-output wire [3 : 0] M_AXI_GP0_AWLEN;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
-output wire [3 : 0] M_AXI_GP0_AWQOS;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
-output wire [3 : 0] M_AXI_GP0_WSTRB;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
-input wire M_AXI_GP0_ACLK;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
-input wire M_AXI_GP0_ARREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
-input wire M_AXI_GP0_AWREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
-input wire M_AXI_GP0_BVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
-input wire M_AXI_GP0_RLAST;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
-input wire M_AXI_GP0_RVALID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
-input wire M_AXI_GP0_WREADY;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
-input wire [11 : 0] M_AXI_GP0_BID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
-input wire [11 : 0] M_AXI_GP0_RID;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
-input wire [1 : 0] M_AXI_GP0_BRESP;
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
-input wire [1 : 0] M_AXI_GP0_RRESP;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 125000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, NUM_READ_\
-THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
-input wire [31 : 0] M_AXI_GP0_RDATA;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
-output wire FCLK_CLK0;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
-(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
-output wire FCLK_RESET0_N;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
-inout wire [53 : 0] MIO;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
-inout wire DDR_CAS_n;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
-inout wire DDR_CKE;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
-inout wire DDR_Clk_n;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
-inout wire DDR_Clk;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
-inout wire DDR_CS_n;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
-inout wire DDR_DRSTB;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
-inout wire DDR_ODT;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
-inout wire DDR_RAS_n;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
-inout wire DDR_WEB;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
-inout wire [2 : 0] DDR_BankAddr;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
-inout wire [14 : 0] DDR_Addr;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
-inout wire DDR_VRN;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
-inout wire DDR_VRP;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
-inout wire [3 : 0] DDR_DM;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
-inout wire [31 : 0] DDR_DQ;
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
-inout wire [3 : 0] DDR_DQS_n;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
-inout wire [3 : 0] DDR_DQS;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
-inout wire PS_SRSTB;
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
-inout wire PS_CLK;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *)
-(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
-inout wire PS_PORB;
-
- processing_system7_v5_5_processing_system7 #(
- .C_EN_EMIO_PJTAG(0),
- .C_EN_EMIO_ENET0(0),
- .C_EN_EMIO_ENET1(0),
- .C_EN_EMIO_TRACE(0),
- .C_INCLUDE_TRACE_BUFFER(0),
- .C_TRACE_BUFFER_FIFO_SIZE(128),
- .USE_TRACE_DATA_EDGE_DETECTOR(0),
- .C_TRACE_PIPELINE_WIDTH(8),
- .C_TRACE_BUFFER_CLOCK_DELAY(12),
- .C_EMIO_GPIO_WIDTH(64),
- .C_INCLUDE_ACP_TRANS_CHECK(0),
- .C_USE_DEFAULT_ACP_USER_VAL(0),
- .C_S_AXI_ACP_ARUSER_VAL(31),
- .C_S_AXI_ACP_AWUSER_VAL(31),
- .C_M_AXI_GP0_ID_WIDTH(12),
- .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
- .C_M_AXI_GP1_ID_WIDTH(12),
- .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
- .C_S_AXI_GP0_ID_WIDTH(6),
- .C_S_AXI_GP1_ID_WIDTH(6),
- .C_S_AXI_ACP_ID_WIDTH(3),
- .C_S_AXI_HP0_ID_WIDTH(6),
- .C_S_AXI_HP0_DATA_WIDTH(64),
- .C_S_AXI_HP1_ID_WIDTH(6),
- .C_S_AXI_HP1_DATA_WIDTH(64),
- .C_S_AXI_HP2_ID_WIDTH(6),
- .C_S_AXI_HP2_DATA_WIDTH(64),
- .C_S_AXI_HP3_ID_WIDTH(6),
- .C_S_AXI_HP3_DATA_WIDTH(64),
- .C_M_AXI_GP0_THREAD_ID_WIDTH(12),
- .C_M_AXI_GP1_THREAD_ID_WIDTH(12),
- .C_NUM_F2P_INTR_INPUTS(1),
- .C_IRQ_F2P_MODE("DIRECT"),
- .C_DQ_WIDTH(32),
- .C_DQS_WIDTH(4),
- .C_DM_WIDTH(4),
- .C_MIO_PRIMITIVE(54),
- .C_TRACE_INTERNAL_WIDTH(2),
- .C_USE_AXI_NONSECURE(0),
- .C_USE_M_AXI_GP0(1),
- .C_USE_M_AXI_GP1(0),
- .C_USE_S_AXI_GP0(0),
- .C_USE_S_AXI_GP1(0),
- .C_USE_S_AXI_HP0(0),
- .C_USE_S_AXI_HP1(0),
- .C_USE_S_AXI_HP2(0),
- .C_USE_S_AXI_HP3(0),
- .C_USE_S_AXI_ACP(0),
- .C_PS7_SI_REV("PRODUCTION"),
- .C_FCLK_CLK0_BUF("TRUE"),
- .C_FCLK_CLK1_BUF("FALSE"),
- .C_FCLK_CLK2_BUF("FALSE"),
- .C_FCLK_CLK3_BUF("FALSE"),
- .C_PACKAGE_NAME("clg485"),
- .C_GP0_EN_MODIFIABLE_TXN(1),
- .C_GP1_EN_MODIFIABLE_TXN(1)
- ) inst (
- .CAN0_PHY_TX(),
- .CAN0_PHY_RX(1'B0),
- .CAN1_PHY_TX(),
- .CAN1_PHY_RX(1'B0),
- .ENET0_GMII_TX_EN(),
- .ENET0_GMII_TX_ER(),
- .ENET0_MDIO_MDC(),
- .ENET0_MDIO_O(),
- .ENET0_MDIO_T(),
- .ENET0_PTP_DELAY_REQ_RX(),
- .ENET0_PTP_DELAY_REQ_TX(),
- .ENET0_PTP_PDELAY_REQ_RX(),
- .ENET0_PTP_PDELAY_REQ_TX(),
- .ENET0_PTP_PDELAY_RESP_RX(),
- .ENET0_PTP_PDELAY_RESP_TX(),
- .ENET0_PTP_SYNC_FRAME_RX(),
- .ENET0_PTP_SYNC_FRAME_TX(),
- .ENET0_SOF_RX(),
- .ENET0_SOF_TX(),
- .ENET0_GMII_TXD(),
- .ENET0_GMII_COL(1'B0),
- .ENET0_GMII_CRS(1'B0),
- .ENET0_GMII_RX_CLK(1'B0),
- .ENET0_GMII_RX_DV(1'B0),
- .ENET0_GMII_RX_ER(1'B0),
- .ENET0_GMII_TX_CLK(1'B0),
- .ENET0_MDIO_I(1'B0),
- .ENET0_EXT_INTIN(1'B0),
- .ENET0_GMII_RXD(8'B0),
- .ENET1_GMII_TX_EN(),
- .ENET1_GMII_TX_ER(),
- .ENET1_MDIO_MDC(),
- .ENET1_MDIO_O(),
- .ENET1_MDIO_T(),
- .ENET1_PTP_DELAY_REQ_RX(),
- .ENET1_PTP_DELAY_REQ_TX(),
- .ENET1_PTP_PDELAY_REQ_RX(),
- .ENET1_PTP_PDELAY_REQ_TX(),
- .ENET1_PTP_PDELAY_RESP_RX(),
- .ENET1_PTP_PDELAY_RESP_TX(),
- .ENET1_PTP_SYNC_FRAME_RX(),
- .ENET1_PTP_SYNC_FRAME_TX(),
- .ENET1_SOF_RX(),
- .ENET1_SOF_TX(),
- .ENET1_GMII_TXD(),
- .ENET1_GMII_COL(1'B0),
- .ENET1_GMII_CRS(1'B0),
- .ENET1_GMII_RX_CLK(1'B0),
- .ENET1_GMII_RX_DV(1'B0),
- .ENET1_GMII_RX_ER(1'B0),
- .ENET1_GMII_TX_CLK(1'B0),
- .ENET1_MDIO_I(1'B0),
- .ENET1_EXT_INTIN(1'B0),
- .ENET1_GMII_RXD(8'B0),
- .GPIO_I(64'B0),
- .GPIO_O(),
- .GPIO_T(),
- .I2C0_SDA_I(1'B0),
- .I2C0_SDA_O(),
- .I2C0_SDA_T(),
- .I2C0_SCL_I(1'B0),
- .I2C0_SCL_O(),
- .I2C0_SCL_T(),
- .I2C1_SDA_I(1'B0),
- .I2C1_SDA_O(),
- .I2C1_SDA_T(),
- .I2C1_SCL_I(1'B0),
- .I2C1_SCL_O(),
- .I2C1_SCL_T(),
- .PJTAG_TCK(1'B0),
- .PJTAG_TMS(1'B0),
- .PJTAG_TDI(1'B0),
- .PJTAG_TDO(),
- .SDIO0_CLK(),
- .SDIO0_CLK_FB(1'B0),
- .SDIO0_CMD_O(),
- .SDIO0_CMD_I(1'B0),
- .SDIO0_CMD_T(),
- .SDIO0_DATA_I(4'B0),
- .SDIO0_DATA_O(),
- .SDIO0_DATA_T(),
- .SDIO0_LED(),
- .SDIO0_CDN(1'B0),
- .SDIO0_WP(1'B0),
- .SDIO0_BUSPOW(),
- .SDIO0_BUSVOLT(),
- .SDIO1_CLK(),
- .SDIO1_CLK_FB(1'B0),
- .SDIO1_CMD_O(),
- .SDIO1_CMD_I(1'B0),
- .SDIO1_CMD_T(),
- .SDIO1_DATA_I(4'B0),
- .SDIO1_DATA_O(),
- .SDIO1_DATA_T(),
- .SDIO1_LED(),
- .SDIO1_CDN(1'B0),
- .SDIO1_WP(1'B0),
- .SDIO1_BUSPOW(),
- .SDIO1_BUSVOLT(),
- .SPI0_SCLK_I(1'B0),
- .SPI0_SCLK_O(),
- .SPI0_SCLK_T(),
- .SPI0_MOSI_I(1'B0),
- .SPI0_MOSI_O(),
- .SPI0_MOSI_T(),
- .SPI0_MISO_I(1'B0),
- .SPI0_MISO_O(),
- .SPI0_MISO_T(),
- .SPI0_SS_I(1'B0),
- .SPI0_SS_O(),
- .SPI0_SS1_O(),
- .SPI0_SS2_O(),
- .SPI0_SS_T(),
- .SPI1_SCLK_I(SPI1_SCLK_I),
- .SPI1_SCLK_O(SPI1_SCLK_O),
- .SPI1_SCLK_T(SPI1_SCLK_T),
- .SPI1_MOSI_I(SPI1_MOSI_I),
- .SPI1_MOSI_O(SPI1_MOSI_O),
- .SPI1_MOSI_T(SPI1_MOSI_T),
- .SPI1_MISO_I(SPI1_MISO_I),
- .SPI1_MISO_O(SPI1_MISO_O),
- .SPI1_MISO_T(SPI1_MISO_T),
- .SPI1_SS_I(SPI1_SS_I),
- .SPI1_SS_O(SPI1_SS_O),
- .SPI1_SS1_O(SPI1_SS1_O),
- .SPI1_SS2_O(SPI1_SS2_O),
- .SPI1_SS_T(SPI1_SS_T),
- .UART0_DTRN(),
- .UART0_RTSN(),
- .UART0_TX(),
- .UART0_CTSN(1'B0),
- .UART0_DCDN(1'B0),
- .UART0_DSRN(1'B0),
- .UART0_RIN(1'B0),
- .UART0_RX(1'B1),
- .UART1_DTRN(),
- .UART1_RTSN(),
- .UART1_TX(),
- .UART1_CTSN(1'B0),
- .UART1_DCDN(1'B0),
- .UART1_DSRN(1'B0),
- .UART1_RIN(1'B0),
- .UART1_RX(1'B1),
- .TTC0_WAVE0_OUT(),
- .TTC0_WAVE1_OUT(),
- .TTC0_WAVE2_OUT(),
- .TTC0_CLK0_IN(1'B0),
- .TTC0_CLK1_IN(1'B0),
- .TTC0_CLK2_IN(1'B0),
- .TTC1_WAVE0_OUT(),
- .TTC1_WAVE1_OUT(),
- .TTC1_WAVE2_OUT(),
- .TTC1_CLK0_IN(1'B0),
- .TTC1_CLK1_IN(1'B0),
- .TTC1_CLK2_IN(1'B0),
- .WDT_CLK_IN(1'B0),
- .WDT_RST_OUT(),
- .TRACE_CLK(1'B0),
- .TRACE_CLK_OUT(),
- .TRACE_CTL(),
- .TRACE_DATA(),
- .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
- .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
- .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
- .USB1_PORT_INDCTL(),
- .USB1_VBUS_PWRSELECT(),
- .USB1_VBUS_PWRFAULT(1'B0),
- .SRAM_INTIN(1'B0),
- .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
- .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
- .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
- .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
- .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
- .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
- .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
- .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
- .M_AXI_GP0_WID(M_AXI_GP0_WID),
- .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
- .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
- .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
- .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
- .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
- .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
- .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
- .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
- .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
- .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
- .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
- .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
- .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
- .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
- .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
- .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
- .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
- .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
- .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
- .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
- .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
- .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
- .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
- .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
- .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
- .M_AXI_GP0_BID(M_AXI_GP0_BID),
- .M_AXI_GP0_RID(M_AXI_GP0_RID),
- .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
- .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
- .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
- .M_AXI_GP1_ARVALID(),
- .M_AXI_GP1_AWVALID(),
- .M_AXI_GP1_BREADY(),
- .M_AXI_GP1_RREADY(),
- .M_AXI_GP1_WLAST(),
- .M_AXI_GP1_WVALID(),
- .M_AXI_GP1_ARID(),
- .M_AXI_GP1_AWID(),
- .M_AXI_GP1_WID(),
- .M_AXI_GP1_ARBURST(),
- .M_AXI_GP1_ARLOCK(),
- .M_AXI_GP1_ARSIZE(),
- .M_AXI_GP1_AWBURST(),
- .M_AXI_GP1_AWLOCK(),
- .M_AXI_GP1_AWSIZE(),
- .M_AXI_GP1_ARPROT(),
- .M_AXI_GP1_AWPROT(),
- .M_AXI_GP1_ARADDR(),
- .M_AXI_GP1_AWADDR(),
- .M_AXI_GP1_WDATA(),
- .M_AXI_GP1_ARCACHE(),
- .M_AXI_GP1_ARLEN(),
- .M_AXI_GP1_ARQOS(),
- .M_AXI_GP1_AWCACHE(),
- .M_AXI_GP1_AWLEN(),
- .M_AXI_GP1_AWQOS(),
- .M_AXI_GP1_WSTRB(),
- .M_AXI_GP1_ACLK(1'B0),
- .M_AXI_GP1_ARREADY(1'B0),
- .M_AXI_GP1_AWREADY(1'B0),
- .M_AXI_GP1_BVALID(1'B0),
- .M_AXI_GP1_RLAST(1'B0),
- .M_AXI_GP1_RVALID(1'B0),
- .M_AXI_GP1_WREADY(1'B0),
- .M_AXI_GP1_BID(12'B0),
- .M_AXI_GP1_RID(12'B0),
- .M_AXI_GP1_BRESP(2'B0),
- .M_AXI_GP1_RRESP(2'B0),
- .M_AXI_GP1_RDATA(32'B0),
- .S_AXI_GP0_ARREADY(),
- .S_AXI_GP0_AWREADY(),
- .S_AXI_GP0_BVALID(),
- .S_AXI_GP0_RLAST(),
- .S_AXI_GP0_RVALID(),
- .S_AXI_GP0_WREADY(),
- .S_AXI_GP0_BRESP(),
- .S_AXI_GP0_RRESP(),
- .S_AXI_GP0_RDATA(),
- .S_AXI_GP0_BID(),
- .S_AXI_GP0_RID(),
- .S_AXI_GP0_ACLK(1'B0),
- .S_AXI_GP0_ARVALID(1'B0),
- .S_AXI_GP0_AWVALID(1'B0),
- .S_AXI_GP0_BREADY(1'B0),
- .S_AXI_GP0_RREADY(1'B0),
- .S_AXI_GP0_WLAST(1'B0),
- .S_AXI_GP0_WVALID(1'B0),
- .S_AXI_GP0_ARBURST(2'B0),
- .S_AXI_GP0_ARLOCK(2'B0),
- .S_AXI_GP0_ARSIZE(3'B0),
- .S_AXI_GP0_AWBURST(2'B0),
- .S_AXI_GP0_AWLOCK(2'B0),
- .S_AXI_GP0_AWSIZE(3'B0),
- .S_AXI_GP0_ARPROT(3'B0),
- .S_AXI_GP0_AWPROT(3'B0),
- .S_AXI_GP0_ARADDR(32'B0),
- .S_AXI_GP0_AWADDR(32'B0),
- .S_AXI_GP0_WDATA(32'B0),
- .S_AXI_GP0_ARCACHE(4'B0),
- .S_AXI_GP0_ARLEN(4'B0),
- .S_AXI_GP0_ARQOS(4'B0),
- .S_AXI_GP0_AWCACHE(4'B0),
- .S_AXI_GP0_AWLEN(4'B0),
- .S_AXI_GP0_AWQOS(4'B0),
- .S_AXI_GP0_WSTRB(4'B0),
- .S_AXI_GP0_ARID(6'B0),
- .S_AXI_GP0_AWID(6'B0),
- .S_AXI_GP0_WID(6'B0),
- .S_AXI_GP1_ARREADY(),
- .S_AXI_GP1_AWREADY(),
- .S_AXI_GP1_BVALID(),
- .S_AXI_GP1_RLAST(),
- .S_AXI_GP1_RVALID(),
- .S_AXI_GP1_WREADY(),
- .S_AXI_GP1_BRESP(),
- .S_AXI_GP1_RRESP(),
- .S_AXI_GP1_RDATA(),
- .S_AXI_GP1_BID(),
- .S_AXI_GP1_RID(),
- .S_AXI_GP1_ACLK(1'B0),
- .S_AXI_GP1_ARVALID(1'B0),
- .S_AXI_GP1_AWVALID(1'B0),
- .S_AXI_GP1_BREADY(1'B0),
- .S_AXI_GP1_RREADY(1'B0),
- .S_AXI_GP1_WLAST(1'B0),
- .S_AXI_GP1_WVALID(1'B0),
- .S_AXI_GP1_ARBURST(2'B0),
- .S_AXI_GP1_ARLOCK(2'B0),
- .S_AXI_GP1_ARSIZE(3'B0),
- .S_AXI_GP1_AWBURST(2'B0),
- .S_AXI_GP1_AWLOCK(2'B0),
- .S_AXI_GP1_AWSIZE(3'B0),
- .S_AXI_GP1_ARPROT(3'B0),
- .S_AXI_GP1_AWPROT(3'B0),
- .S_AXI_GP1_ARADDR(32'B0),
- .S_AXI_GP1_AWADDR(32'B0),
- .S_AXI_GP1_WDATA(32'B0),
- .S_AXI_GP1_ARCACHE(4'B0),
- .S_AXI_GP1_ARLEN(4'B0),
- .S_AXI_GP1_ARQOS(4'B0),
- .S_AXI_GP1_AWCACHE(4'B0),
- .S_AXI_GP1_AWLEN(4'B0),
- .S_AXI_GP1_AWQOS(4'B0),
- .S_AXI_GP1_WSTRB(4'B0),
- .S_AXI_GP1_ARID(6'B0),
- .S_AXI_GP1_AWID(6'B0),
- .S_AXI_GP1_WID(6'B0),
- .S_AXI_ACP_ARREADY(),
- .S_AXI_ACP_AWREADY(),
- .S_AXI_ACP_BVALID(),
- .S_AXI_ACP_RLAST(),
- .S_AXI_ACP_RVALID(),
- .S_AXI_ACP_WREADY(),
- .S_AXI_ACP_BRESP(),
- .S_AXI_ACP_RRESP(),
- .S_AXI_ACP_BID(),
- .S_AXI_ACP_RID(),
- .S_AXI_ACP_RDATA(),
- .S_AXI_ACP_ACLK(1'B0),
- .S_AXI_ACP_ARVALID(1'B0),
- .S_AXI_ACP_AWVALID(1'B0),
- .S_AXI_ACP_BREADY(1'B0),
- .S_AXI_ACP_RREADY(1'B0),
- .S_AXI_ACP_WLAST(1'B0),
- .S_AXI_ACP_WVALID(1'B0),
- .S_AXI_ACP_ARID(3'B0),
- .S_AXI_ACP_ARPROT(3'B0),
- .S_AXI_ACP_AWID(3'B0),
- .S_AXI_ACP_AWPROT(3'B0),
- .S_AXI_ACP_WID(3'B0),
- .S_AXI_ACP_ARADDR(32'B0),
- .S_AXI_ACP_AWADDR(32'B0),
- .S_AXI_ACP_ARCACHE(4'B0),
- .S_AXI_ACP_ARLEN(4'B0),
- .S_AXI_ACP_ARQOS(4'B0),
- .S_AXI_ACP_AWCACHE(4'B0),
- .S_AXI_ACP_AWLEN(4'B0),
- .S_AXI_ACP_AWQOS(4'B0),
- .S_AXI_ACP_ARBURST(2'B0),
- .S_AXI_ACP_ARLOCK(2'B0),
- .S_AXI_ACP_ARSIZE(3'B0),
- .S_AXI_ACP_AWBURST(2'B0),
- .S_AXI_ACP_AWLOCK(2'B0),
- .S_AXI_ACP_AWSIZE(3'B0),
- .S_AXI_ACP_ARUSER(5'B0),
- .S_AXI_ACP_AWUSER(5'B0),
- .S_AXI_ACP_WDATA(64'B0),
- .S_AXI_ACP_WSTRB(8'B0),
- .S_AXI_HP0_ARREADY(),
- .S_AXI_HP0_AWREADY(),
- .S_AXI_HP0_BVALID(),
- .S_AXI_HP0_RLAST(),
- .S_AXI_HP0_RVALID(),
- .S_AXI_HP0_WREADY(),
- .S_AXI_HP0_BRESP(),
- .S_AXI_HP0_RRESP(),
- .S_AXI_HP0_BID(),
- .S_AXI_HP0_RID(),
- .S_AXI_HP0_RDATA(),
- .S_AXI_HP0_RCOUNT(),
- .S_AXI_HP0_WCOUNT(),
- .S_AXI_HP0_RACOUNT(),
- .S_AXI_HP0_WACOUNT(),
- .S_AXI_HP0_ACLK(1'B0),
- .S_AXI_HP0_ARVALID(1'B0),
- .S_AXI_HP0_AWVALID(1'B0),
- .S_AXI_HP0_BREADY(1'B0),
- .S_AXI_HP0_RDISSUECAP1_EN(1'B0),
- .S_AXI_HP0_RREADY(1'B0),
- .S_AXI_HP0_WLAST(1'B0),
- .S_AXI_HP0_WRISSUECAP1_EN(1'B0),
- .S_AXI_HP0_WVALID(1'B0),
- .S_AXI_HP0_ARBURST(2'B0),
- .S_AXI_HP0_ARLOCK(2'B0),
- .S_AXI_HP0_ARSIZE(3'B0),
- .S_AXI_HP0_AWBURST(2'B0),
- .S_AXI_HP0_AWLOCK(2'B0),
- .S_AXI_HP0_AWSIZE(3'B0),
- .S_AXI_HP0_ARPROT(3'B0),
- .S_AXI_HP0_AWPROT(3'B0),
- .S_AXI_HP0_ARADDR(32'B0),
- .S_AXI_HP0_AWADDR(32'B0),
- .S_AXI_HP0_ARCACHE(4'B0),
- .S_AXI_HP0_ARLEN(4'B0),
- .S_AXI_HP0_ARQOS(4'B0),
- .S_AXI_HP0_AWCACHE(4'B0),
- .S_AXI_HP0_AWLEN(4'B0),
- .S_AXI_HP0_AWQOS(4'B0),
- .S_AXI_HP0_ARID(6'B0),
- .S_AXI_HP0_AWID(6'B0),
- .S_AXI_HP0_WID(6'B0),
- .S_AXI_HP0_WDATA(64'B0),
- .S_AXI_HP0_WSTRB(8'B0),
- .S_AXI_HP1_ARREADY(),
- .S_AXI_HP1_AWREADY(),
- .S_AXI_HP1_BVALID(),
- .S_AXI_HP1_RLAST(),
- .S_AXI_HP1_RVALID(),
- .S_AXI_HP1_WREADY(),
- .S_AXI_HP1_BRESP(),
- .S_AXI_HP1_RRESP(),
- .S_AXI_HP1_BID(),
- .S_AXI_HP1_RID(),
- .S_AXI_HP1_RDATA(),
- .S_AXI_HP1_RCOUNT(),
- .S_AXI_HP1_WCOUNT(),
- .S_AXI_HP1_RACOUNT(),
- .S_AXI_HP1_WACOUNT(),
- .S_AXI_HP1_ACLK(1'B0),
- .S_AXI_HP1_ARVALID(1'B0),
- .S_AXI_HP1_AWVALID(1'B0),
- .S_AXI_HP1_BREADY(1'B0),
- .S_AXI_HP1_RDISSUECAP1_EN(1'B0),
- .S_AXI_HP1_RREADY(1'B0),
- .S_AXI_HP1_WLAST(1'B0),
- .S_AXI_HP1_WRISSUECAP1_EN(1'B0),
- .S_AXI_HP1_WVALID(1'B0),
- .S_AXI_HP1_ARBURST(2'B0),
- .S_AXI_HP1_ARLOCK(2'B0),
- .S_AXI_HP1_ARSIZE(3'B0),
- .S_AXI_HP1_AWBURST(2'B0),
- .S_AXI_HP1_AWLOCK(2'B0),
- .S_AXI_HP1_AWSIZE(3'B0),
- .S_AXI_HP1_ARPROT(3'B0),
- .S_AXI_HP1_AWPROT(3'B0),
- .S_AXI_HP1_ARADDR(32'B0),
- .S_AXI_HP1_AWADDR(32'B0),
- .S_AXI_HP1_ARCACHE(4'B0),
- .S_AXI_HP1_ARLEN(4'B0),
- .S_AXI_HP1_ARQOS(4'B0),
- .S_AXI_HP1_AWCACHE(4'B0),
- .S_AXI_HP1_AWLEN(4'B0),
- .S_AXI_HP1_AWQOS(4'B0),
- .S_AXI_HP1_ARID(6'B0),
- .S_AXI_HP1_AWID(6'B0),
- .S_AXI_HP1_WID(6'B0),
- .S_AXI_HP1_WDATA(64'B0),
- .S_AXI_HP1_WSTRB(8'B0),
- .S_AXI_HP2_ARREADY(),
- .S_AXI_HP2_AWREADY(),
- .S_AXI_HP2_BVALID(),
- .S_AXI_HP2_RLAST(),
- .S_AXI_HP2_RVALID(),
- .S_AXI_HP2_WREADY(),
- .S_AXI_HP2_BRESP(),
- .S_AXI_HP2_RRESP(),
- .S_AXI_HP2_BID(),
- .S_AXI_HP2_RID(),
- .S_AXI_HP2_RDATA(),
- .S_AXI_HP2_RCOUNT(),
- .S_AXI_HP2_WCOUNT(),
- .S_AXI_HP2_RACOUNT(),
- .S_AXI_HP2_WACOUNT(),
- .S_AXI_HP2_ACLK(1'B0),
- .S_AXI_HP2_ARVALID(1'B0),
- .S_AXI_HP2_AWVALID(1'B0),
- .S_AXI_HP2_BREADY(1'B0),
- .S_AXI_HP2_RDISSUECAP1_EN(1'B0),
- .S_AXI_HP2_RREADY(1'B0),
- .S_AXI_HP2_WLAST(1'B0),
- .S_AXI_HP2_WRISSUECAP1_EN(1'B0),
- .S_AXI_HP2_WVALID(1'B0),
- .S_AXI_HP2_ARBURST(2'B0),
- .S_AXI_HP2_ARLOCK(2'B0),
- .S_AXI_HP2_ARSIZE(3'B0),
- .S_AXI_HP2_AWBURST(2'B0),
- .S_AXI_HP2_AWLOCK(2'B0),
- .S_AXI_HP2_AWSIZE(3'B0),
- .S_AXI_HP2_ARPROT(3'B0),
- .S_AXI_HP2_AWPROT(3'B0),
- .S_AXI_HP2_ARADDR(32'B0),
- .S_AXI_HP2_AWADDR(32'B0),
- .S_AXI_HP2_ARCACHE(4'B0),
- .S_AXI_HP2_ARLEN(4'B0),
- .S_AXI_HP2_ARQOS(4'B0),
- .S_AXI_HP2_AWCACHE(4'B0),
- .S_AXI_HP2_AWLEN(4'B0),
- .S_AXI_HP2_AWQOS(4'B0),
- .S_AXI_HP2_ARID(6'B0),
- .S_AXI_HP2_AWID(6'B0),
- .S_AXI_HP2_WID(6'B0),
- .S_AXI_HP2_WDATA(64'B0),
- .S_AXI_HP2_WSTRB(8'B0),
- .S_AXI_HP3_ARREADY(),
- .S_AXI_HP3_AWREADY(),
- .S_AXI_HP3_BVALID(),
- .S_AXI_HP3_RLAST(),
- .S_AXI_HP3_RVALID(),
- .S_AXI_HP3_WREADY(),
- .S_AXI_HP3_BRESP(),
- .S_AXI_HP3_RRESP(),
- .S_AXI_HP3_BID(),
- .S_AXI_HP3_RID(),
- .S_AXI_HP3_RDATA(),
- .S_AXI_HP3_RCOUNT(),
- .S_AXI_HP3_WCOUNT(),
- .S_AXI_HP3_RACOUNT(),
- .S_AXI_HP3_WACOUNT(),
- .S_AXI_HP3_ACLK(1'B0),
- .S_AXI_HP3_ARVALID(1'B0),
- .S_AXI_HP3_AWVALID(1'B0),
- .S_AXI_HP3_BREADY(1'B0),
- .S_AXI_HP3_RDISSUECAP1_EN(1'B0),
- .S_AXI_HP3_RREADY(1'B0),
- .S_AXI_HP3_WLAST(1'B0),
- .S_AXI_HP3_WRISSUECAP1_EN(1'B0),
- .S_AXI_HP3_WVALID(1'B0),
- .S_AXI_HP3_ARBURST(2'B0),
- .S_AXI_HP3_ARLOCK(2'B0),
- .S_AXI_HP3_ARSIZE(3'B0),
- .S_AXI_HP3_AWBURST(2'B0),
- .S_AXI_HP3_AWLOCK(2'B0),
- .S_AXI_HP3_AWSIZE(3'B0),
- .S_AXI_HP3_ARPROT(3'B0),
- .S_AXI_HP3_AWPROT(3'B0),
- .S_AXI_HP3_ARADDR(32'B0),
- .S_AXI_HP3_AWADDR(32'B0),
- .S_AXI_HP3_ARCACHE(4'B0),
- .S_AXI_HP3_ARLEN(4'B0),
- .S_AXI_HP3_ARQOS(4'B0),
- .S_AXI_HP3_AWCACHE(4'B0),
- .S_AXI_HP3_AWLEN(4'B0),
- .S_AXI_HP3_AWQOS(4'B0),
- .S_AXI_HP3_ARID(6'B0),
- .S_AXI_HP3_AWID(6'B0),
- .S_AXI_HP3_WID(6'B0),
- .S_AXI_HP3_WDATA(64'B0),
- .S_AXI_HP3_WSTRB(8'B0),
- .IRQ_P2F_DMAC_ABORT(),
- .IRQ_P2F_DMAC0(),
- .IRQ_P2F_DMAC1(),
- .IRQ_P2F_DMAC2(),
- .IRQ_P2F_DMAC3(),
- .IRQ_P2F_DMAC4(),
- .IRQ_P2F_DMAC5(),
- .IRQ_P2F_DMAC6(),
- .IRQ_P2F_DMAC7(),
- .IRQ_P2F_SMC(),
- .IRQ_P2F_QSPI(),
- .IRQ_P2F_CTI(),
- .IRQ_P2F_GPIO(),
- .IRQ_P2F_USB0(),
- .IRQ_P2F_ENET0(),
- .IRQ_P2F_ENET_WAKE0(),
- .IRQ_P2F_SDIO0(),
- .IRQ_P2F_I2C0(),
- .IRQ_P2F_SPI0(),
- .IRQ_P2F_UART0(),
- .IRQ_P2F_CAN0(),
- .IRQ_P2F_USB1(),
- .IRQ_P2F_ENET1(),
- .IRQ_P2F_ENET_WAKE1(),
- .IRQ_P2F_SDIO1(),
- .IRQ_P2F_I2C1(),
- .IRQ_P2F_SPI1(),
- .IRQ_P2F_UART1(),
- .IRQ_P2F_CAN1(),
- .IRQ_F2P(1'B0),
- .Core0_nFIQ(1'B0),
- .Core0_nIRQ(1'B0),
- .Core1_nFIQ(1'B0),
- .Core1_nIRQ(1'B0),
- .DMA0_DATYPE(),
- .DMA0_DAVALID(),
- .DMA0_DRREADY(),
- .DMA1_DATYPE(),
- .DMA1_DAVALID(),
- .DMA1_DRREADY(),
- .DMA2_DATYPE(),
- .DMA2_DAVALID(),
- .DMA2_DRREADY(),
- .DMA3_DATYPE(),
- .DMA3_DAVALID(),
- .DMA3_DRREADY(),
- .DMA0_ACLK(1'B0),
- .DMA0_DAREADY(1'B0),
- .DMA0_DRLAST(1'B0),
- .DMA0_DRVALID(1'B0),
- .DMA1_ACLK(1'B0),
- .DMA1_DAREADY(1'B0),
- .DMA1_DRLAST(1'B0),
- .DMA1_DRVALID(1'B0),
- .DMA2_ACLK(1'B0),
- .DMA2_DAREADY(1'B0),
- .DMA2_DRLAST(1'B0),
- .DMA2_DRVALID(1'B0),
- .DMA3_ACLK(1'B0),
- .DMA3_DAREADY(1'B0),
- .DMA3_DRLAST(1'B0),
- .DMA3_DRVALID(1'B0),
- .DMA0_DRTYPE(2'B0),
- .DMA1_DRTYPE(2'B0),
- .DMA2_DRTYPE(2'B0),
- .DMA3_DRTYPE(2'B0),
- .FCLK_CLK0(FCLK_CLK0),
- .FCLK_CLK1(),
- .FCLK_CLK2(),
- .FCLK_CLK3(),
- .FCLK_CLKTRIG0_N(1'B0),
- .FCLK_CLKTRIG1_N(1'B0),
- .FCLK_CLKTRIG2_N(1'B0),
- .FCLK_CLKTRIG3_N(1'B0),
- .FCLK_RESET0_N(FCLK_RESET0_N),
- .FCLK_RESET1_N(),
- .FCLK_RESET2_N(),
- .FCLK_RESET3_N(),
- .FTMD_TRACEIN_DATA(32'B0),
- .FTMD_TRACEIN_VALID(1'B0),
- .FTMD_TRACEIN_CLK(1'B0),
- .FTMD_TRACEIN_ATID(4'B0),
- .FTMT_F2P_TRIG_0(1'B0),
- .FTMT_F2P_TRIGACK_0(),
- .FTMT_F2P_TRIG_1(1'B0),
- .FTMT_F2P_TRIGACK_1(),
- .FTMT_F2P_TRIG_2(1'B0),
- .FTMT_F2P_TRIGACK_2(),
- .FTMT_F2P_TRIG_3(1'B0),
- .FTMT_F2P_TRIGACK_3(),
- .FTMT_F2P_DEBUG(32'B0),
- .FTMT_P2F_TRIGACK_0(1'B0),
- .FTMT_P2F_TRIG_0(),
- .FTMT_P2F_TRIGACK_1(1'B0),
- .FTMT_P2F_TRIG_1(),
- .FTMT_P2F_TRIGACK_2(1'B0),
- .FTMT_P2F_TRIG_2(),
- .FTMT_P2F_TRIGACK_3(1'B0),
- .FTMT_P2F_TRIG_3(),
- .FTMT_P2F_DEBUG(),
- .FPGA_IDLE_N(1'B0),
- .EVENT_EVENTO(),
- .EVENT_STANDBYWFE(),
- .EVENT_STANDBYWFI(),
- .EVENT_EVENTI(1'B0),
- .DDR_ARB(4'B0),
- .MIO(MIO),
- .DDR_CAS_n(DDR_CAS_n),
- .DDR_CKE(DDR_CKE),
- .DDR_Clk_n(DDR_Clk_n),
- .DDR_Clk(DDR_Clk),
- .DDR_CS_n(DDR_CS_n),
- .DDR_DRSTB(DDR_DRSTB),
- .DDR_ODT(DDR_ODT),
- .DDR_RAS_n(DDR_RAS_n),
- .DDR_WEB(DDR_WEB),
- .DDR_BankAddr(DDR_BankAddr),
- .DDR_Addr(DDR_Addr),
- .DDR_VRN(DDR_VRN),
- .DDR_VRP(DDR_VRP),
- .DDR_DM(DDR_DM),
- .DDR_DQ(DDR_DQ),
- .DDR_DQS_n(DDR_DQS_n),
- .DDR_DQS(DDR_DQS),
- .PS_SRSTB(PS_SRSTB),
- .PS_CLK(PS_CLK),
- .PS_PORB(PS_PORB)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.dcp
deleted file mode 100644
index 9f2b6ef7a33fc2e214f7c42aab5a238f645faaa9..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci
deleted file mode 100644
index b53cafdfc33343faee675e29704e77aad35ed410..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci
+++ /dev/null
@@ -1,51 +0,0 @@
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+++ /dev/null
@@ -1,324 +0,0 @@
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
deleted file mode 100644
index 7a38996ceefd4185354e5a7acbfea1c0fcedb83a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
+++ /dev/null
@@ -1,105 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:29 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
-// Design : scalp_zynqps_util_vector_logic_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module scalp_zynqps_util_vector_logic_0_0
- (Op1,
- Op2,
- Res);
- input [0:0]Op1;
- input [0:0]Op2;
- output [0:0]Res;
-
- wire [0:0]Op1;
- wire [0:0]Op2;
- wire [0:0]Res;
-
- LUT2 #(
- .INIT(4'hE))
- \Res[0]_INST_0
- (.I0(Op1),
- .I1(Op2),
- .O(Res));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.v
deleted file mode 100644
index f5ff1cec7f7af592d243505f2cbdf27bbc453485..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.v
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:28 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.v
-// Design : scalp_zynqps_util_vector_logic_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-module scalp_zynqps_util_vector_logic_0_0(Op1, Op2, Res)
-/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
- input [0:0]Op1;
- input [0:0]Op2;
- output [0:0]Res;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v
deleted file mode 100644
index 065a5263fe61893f53dc350541bd9f82a5797211..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v
+++ /dev/null
@@ -1,74 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-// IP Revision: 1
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_util_vector_logic_0_0 (
- Op1,
- Op2,
- Res
-);
-
-input wire [0 : 0] Op1;
-input wire [0 : 0] Op2;
-output wire [0 : 0] Res;
-
- util_vector_logic_v2_0_1_util_vector_logic #(
- .C_OPERATION("or"),
- .C_SIZE(1)
- ) inst (
- .Op1(Op1),
- .Op2(Op2),
- .Res(Res)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/synth/scalp_zynqps_util_vector_logic_0_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/synth/scalp_zynqps_util_vector_logic_0_0.v
deleted file mode 100644
index 1ce4ccf31993840ba6b7439c90f0ea751fd90062..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/synth/scalp_zynqps_util_vector_logic_0_0.v
+++ /dev/null
@@ -1,75 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-// IP Revision: 1
-
-(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *)
-(* CORE_GENERATION_INFO = "scalp_zynqps_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=or,C_SIZE=1}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_util_vector_logic_0_0 (
- Op1,
- Op2,
- Res
-);
-
-input wire [0 : 0] Op1;
-input wire [0 : 0] Op2;
-output wire [0 : 0] Res;
-
- util_vector_logic_v2_0_1_util_vector_logic #(
- .C_OPERATION("or"),
- .C_SIZE(1)
- ) inst (
- .Op1(Op1),
- .Op2(Op2),
- .Res(Res)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.dcp
deleted file mode 100644
index 62f466899c0664a4928dca81e66e553e3e156de1..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci
deleted file mode 100644
index 061f810c36a30036ea2bdd5862fd4d5ef302cd6e..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci
+++ /dev/null
@@ -1,51 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xml
deleted file mode 100644
index c7eb19d76742eca2ba8b1089a2cbdf1fb53ecb4f..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xml
+++ /dev/null
@@ -1,324 +0,0 @@
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- <spirit:fileType>verilogSource</spirit:fileType>
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- <spirit:userFileType>dcp</spirit:userFileType>
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- <spirit:fileType>verilogSource</spirit:fileType>
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- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOGO_FILE" spirit:order="5">data/sym_notgate.png</spirit:value>
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
deleted file mode 100644
index ebf986fa524a0445e2e955cab5e0d78366522afe..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
+++ /dev/null
@@ -1,101 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:29 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
-// Design : scalp_zynqps_util_vector_logic_1_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_util_vector_logic_1_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module scalp_zynqps_util_vector_logic_1_0
- (Op1,
- Res);
- input [0:0]Op1;
- output [0:0]Res;
-
- wire [0:0]Op1;
- wire [0:0]Res;
-
- LUT1 #(
- .INIT(2'h1))
- \Res[0]_INST_0
- (.I0(Op1),
- .O(Res));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.v
deleted file mode 100644
index 3313139ad0fc05be66cf4331e436090ec3788426..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.v
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:28 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.v
-// Design : scalp_zynqps_util_vector_logic_1_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-module scalp_zynqps_util_vector_logic_1_0(Op1, Res)
-/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Res[0:0]" */;
- input [0:0]Op1;
- output [0:0]Res;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v
deleted file mode 100644
index 7a36d0de7ed6ecff815ed13285e8a76934e637d5..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v
+++ /dev/null
@@ -1,72 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-// IP Revision: 1
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_util_vector_logic_1_0 (
- Op1,
- Res
-);
-
-input wire [0 : 0] Op1;
-output wire [0 : 0] Res;
-
- util_vector_logic_v2_0_1_util_vector_logic #(
- .C_OPERATION("not"),
- .C_SIZE(1)
- ) inst (
- .Op1(Op1),
- .Op2(1'B0),
- .Res(Res)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/synth/scalp_zynqps_util_vector_logic_1_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/synth/scalp_zynqps_util_vector_logic_1_0.v
deleted file mode 100644
index 5f74e975081c0838990157e48ea761011b99d682..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/synth/scalp_zynqps_util_vector_logic_1_0.v
+++ /dev/null
@@ -1,73 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-// IP Revision: 1
-
-(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_util_vector_logic_1_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *)
-(* CORE_GENERATION_INFO = "scalp_zynqps_util_vector_logic_1_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_util_vector_logic_1_0 (
- Op1,
- Res
-);
-
-input wire [0 : 0] Op1;
-output wire [0 : 0] Res;
-
- util_vector_logic_v2_0_1_util_vector_logic #(
- .C_OPERATION("not"),
- .C_SIZE(1)
- ) inst (
- .Op1(Op1),
- .Op2(1'B0),
- .Res(Res)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.dcp
deleted file mode 100644
index 4a0e84e0f7ae92d858b9b9a6fadd94bb49cb45b7..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci
deleted file mode 100644
index 8a9903fe78c6e2a59c1e7a0b67749deaf3848819..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci
+++ /dev/null
@@ -1,832 +0,0 @@
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- <spirit:name>unknown</spirit:name>
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xdc b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xdc
deleted file mode 100644
index e67db69223b67b53f5bcb1cc7636d54242b61ffb..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xdc
+++ /dev/null
@@ -1,67 +0,0 @@
-# file: scalp_zynqps_vio_0_0.xdc
-#////////////////////////////////////////////////////////////////////////////
-#/$Date: 2012/02/06 10:34:16 $
-#/$RCSfile: $
-#/$Revision: 1.2 $
-#//////////////////////////////////////////////////////////////////////////////
-#/ ____ ____
-#/ / /\/ /
-#/ /___/ \ / Vendor: Xilinx
-#/ \ \ \/ Version : 2.00
-#/ \ \ Application : VIO V2.00a
-#/ / / Filename : scalp_zynqps_vio_0_0.xdc
-#/ /___/ /\
-#/ \ \ / \
-#/ \___\/\___\
-#/
-#/ (c) Copyright 2010 Xilinx, Inc. All rights reserved.
-#/
-#/ This file contains confidential and proprietary information
-#/ of Xilinx, Inc. and is protected under U.S. and
-#/ international copyright and other intellectual property
-#/ laws.
-#/
-#/ DISCLAIMER
-#/ This disclaimer is not a license and does not grant any
-#/ rights to the materials distributed herewith. Except as
-#/ otherwise provided in a valid license issued to you by
-#/ Xilinx, and to the maximum extent permitted by applicable
-#/ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-#/ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-#/ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-#/ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-#/ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-#/ (2) Xilinx shall not be liable (whether in contract or tort,
-#/ including negligence, or under any other theory of
-#/ liability) for any loss or damage of any kind or nature
-#/ related to, arising under or in connection with these
-#/ materials, including for any direct, or any indirect,
-#/ special, incidental, or consequential loss or damage
-#/ (including loss of data, profits, goodwill, or any type of
-#/ loss or damage suffered as a result of any action brought
-#/ by a third party) even if such damage or loss was
-#/ reasonably foreseeable or Xilinx had been advised of the
-#/ possibility of the same.
-#/
-#/ CRITICAL APPLICATIONS
-#/ Xilinx products are not designed or intended to be fail-
-#/ safe, or for use in any application requiring fail-safe
-#/ performance, such as life-support or safety devices or
-#/ systems, Class III medical devices, nuclear facilities,
-#/ applications related to the deployment of airbags, or any
-#/ other applications that could lead to death, personal
-#/ injury, or severe property or environmental damage
-#/ (individually and collectively, "Critical
-#/ Applications"). Customer assumes the sole risk and
-#/ liability of any use of Xilinx products in Critical
-#/ Applications, subject only to applicable laws and
-#/ regulations governing limitations on product liability.
-#/
-#/ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-#/ PART OF THIS FILE AT ALL TIMES.
-#Created by Constraints Editor
-
- set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*committ_int*" && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter { NAME =~ "*Committ_1*" && IS_SEQUENTIAL} ]
- set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*clear_int*" && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter { NAME =~ "*Probe_out*" && IS_SEQUENTIAL}]
- set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*clear_int*" && IS_SEQUENTIAL }] -to [get_cells -hierarchical -filter { NAME =~ "*PROBE_OUT_ALL_INST/G_PROBE_OUT[*].PROBE_OUT0_INST/data_int*" && IS_SEQUENTIAL}]
- set_false_path -from [get_cells -hierarchical -filter { NAME =~ "*data_int_*" && IS_SEQUENTIAL } ] -to [get_cells -hierarchical -filter { NAME =~ "*Probe_out_*" && IS_SEQUENTIAL} ]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xml
deleted file mode 100644
index 3b63f364643cb1d0a2d78f230e23aaa676665600..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xml
+++ /dev/null
@@ -1,20730 +0,0 @@
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- <spirit:displayName>PROBE OUT122 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT122_WIDTH" spirit:order="39300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT121_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT121 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT121_WIDTH" spirit:order="39200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT120_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT120 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT120_WIDTH" spirit:order="39100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT119_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT119 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT119_WIDTH" spirit:order="39000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT118_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT118 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT118_WIDTH" spirit:order="38900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT117_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT117 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT117_WIDTH" spirit:order="38800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT116_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT116 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT116_WIDTH" spirit:order="38700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT115_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT115 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT115_WIDTH" spirit:order="38600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT114_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT114 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT114_WIDTH" spirit:order="38500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT113_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT113 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT113_WIDTH" spirit:order="38400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT112_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT112 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT112_WIDTH" spirit:order="38300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT111_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT111 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT111_WIDTH" spirit:order="38200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT110_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT110 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT110_WIDTH" spirit:order="38100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT109_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT109 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT109_WIDTH" spirit:order="38000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT108_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT108 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT108_WIDTH" spirit:order="37900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT107_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT107 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT107_WIDTH" spirit:order="37800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT106_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT106 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT106_WIDTH" spirit:order="37700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT105_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT105 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT105_WIDTH" spirit:order="37600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT104_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT104 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT104_WIDTH" spirit:order="37500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT103_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT103 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT103_WIDTH" spirit:order="37400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT102_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT102 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT102_WIDTH" spirit:order="37300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT101_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT101 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT101_WIDTH" spirit:order="37200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT100_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT100 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT100_WIDTH" spirit:order="37100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT99_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT99 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT99_WIDTH" spirit:order="37000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT98_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT98 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT98_WIDTH" spirit:order="36900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT97_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT97 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT97_WIDTH" spirit:order="36800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT96_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT96 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT96_WIDTH" spirit:order="36700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT95_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT95 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT95_WIDTH" spirit:order="36600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT94_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT94 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT94_WIDTH" spirit:order="36500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT93_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT93 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT93_WIDTH" spirit:order="36400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT92_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT92 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT92_WIDTH" spirit:order="36300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT91_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT91 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT91_WIDTH" spirit:order="36200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT90_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT90 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT90_WIDTH" spirit:order="36100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT89_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT89 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT89_WIDTH" spirit:order="36000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT88_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT88 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT88_WIDTH" spirit:order="35900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT87_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT87 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT87_WIDTH" spirit:order="35800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT86_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT86 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT86_WIDTH" spirit:order="35700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT85_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT85 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT85_WIDTH" spirit:order="35600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT84_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT84 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT84_WIDTH" spirit:order="35500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT83_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT83 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT83_WIDTH" spirit:order="35400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT82_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT82 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT82_WIDTH" spirit:order="35300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT81_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT81 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT81_WIDTH" spirit:order="35200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT80_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT80 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT80_WIDTH" spirit:order="35100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT79_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT79 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT79_WIDTH" spirit:order="35000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT78_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT78 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT78_WIDTH" spirit:order="34900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT77_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT77 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT77_WIDTH" spirit:order="34800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT76_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT76 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT76_WIDTH" spirit:order="34700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT75_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT75 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT75_WIDTH" spirit:order="34600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT74_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT74 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT74_WIDTH" spirit:order="34500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT73_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT73 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT73_WIDTH" spirit:order="34400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT72_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT72 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT72_WIDTH" spirit:order="34300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT71_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT71 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT71_WIDTH" spirit:order="34200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT70_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT70 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT70_WIDTH" spirit:order="34100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT69_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT69 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT69_WIDTH" spirit:order="34000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT68_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT68 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT68_WIDTH" spirit:order="33900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT67_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT67 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT67_WIDTH" spirit:order="33800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT66_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT66 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT66_WIDTH" spirit:order="33700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT65_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT65 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT65_WIDTH" spirit:order="33600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT64_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT64 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT64_WIDTH" spirit:order="33500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT63_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT63 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT63_WIDTH" spirit:order="33400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT62_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT62 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT62_WIDTH" spirit:order="33300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT61_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT61 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT61_WIDTH" spirit:order="33200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT60_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT60 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT60_WIDTH" spirit:order="33100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_OUT59_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT59 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT59_WIDTH" spirit:order="33000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:displayName>PROBE OUT57 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT56 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT55 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT54 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT53 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT51 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT48 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT47 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT45 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT44 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT43 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT43_WIDTH" spirit:order="31400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:displayName>PROBE OUT42 WIDTH</spirit:displayName>
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- <spirit:displayName>PROBE OUT41 WIDTH</spirit:displayName>
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- <spirit:name>C_PROBE_OUT40_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT40 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT40_WIDTH" spirit:order="31100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT39_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT39 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT39_WIDTH" spirit:order="31000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT38_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT38 WIDTH</spirit:displayName>
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- <spirit:name>C_PROBE_OUT37_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT37 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT37_WIDTH" spirit:order="30800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT36_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT36 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT36_WIDTH" spirit:order="30700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT35_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT35 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT35_WIDTH" spirit:order="30600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT34_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT34 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT34_WIDTH" spirit:order="30500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT33_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT33 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT33_WIDTH" spirit:order="30400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT32_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT32 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT32_WIDTH" spirit:order="30300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT31_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT31 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT31_WIDTH" spirit:order="30200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT30_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT30 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT30_WIDTH" spirit:order="30100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT29_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT29 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT29_WIDTH" spirit:order="30000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT28_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT28 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT28_WIDTH" spirit:order="29900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT27_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT27 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT27_WIDTH" spirit:order="29800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT26_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT26 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT26_WIDTH" spirit:order="29700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT25_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT25 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT25_WIDTH" spirit:order="29600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT24_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT24 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT24_WIDTH" spirit:order="29500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT23_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT23 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT23_WIDTH" spirit:order="29400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT22_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT22 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT22_WIDTH" spirit:order="29300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT21_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT21 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT21_WIDTH" spirit:order="29200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT20_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT20 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT20_WIDTH" spirit:order="29100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT19_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT19 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT19_WIDTH" spirit:order="29000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT18_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT18 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT18_WIDTH" spirit:order="28900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT17_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT17 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT17_WIDTH" spirit:order="28800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT16_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT16 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT16_WIDTH" spirit:order="28700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT15_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT15 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT15_WIDTH" spirit:order="28600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT14_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT14 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT14_WIDTH" spirit:order="28500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT13_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT13 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT13_WIDTH" spirit:order="28400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:name>C_PROBE_OUT12_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT12 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT12_WIDTH" spirit:order="28300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT11_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT11 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT11_WIDTH" spirit:order="28200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT10_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT10 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT10_WIDTH" spirit:order="28100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT9_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT9 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT9_WIDTH" spirit:order="28000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT8_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT8 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT8_WIDTH" spirit:order="27900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT7_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT7 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT7_WIDTH" spirit:order="27800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT6_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT6 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT6_WIDTH" spirit:order="27700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT5_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT5 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT5_WIDTH" spirit:order="27600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT4_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT4 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT4_WIDTH" spirit:order="27500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT3_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT3 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT3_WIDTH" spirit:order="27400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT2_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT2 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT2_WIDTH" spirit:order="27300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT1_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT1 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT1_WIDTH" spirit:order="27200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_OUT0_WIDTH</spirit:name>
- <spirit:displayName>PROBE OUT0 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_OUT0_WIDTH" spirit:order="27100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN255_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN255 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN255_WIDTH" spirit:order="27000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN254_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN254 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN254_WIDTH" spirit:order="26900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN253_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN253 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN253_WIDTH" spirit:order="26800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN252_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN252 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN252_WIDTH" spirit:order="26700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN61_WIDTH" spirit:order="7600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN60_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN60 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN60_WIDTH" spirit:order="7500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN59_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN59 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN59_WIDTH" spirit:order="7400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN58_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN58 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN58_WIDTH" spirit:order="7300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN57_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN57 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN57_WIDTH" spirit:order="7200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN56_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN56 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN56_WIDTH" spirit:order="7100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN55_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN55 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN55_WIDTH" spirit:order="7000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN54_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN54 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN54_WIDTH" spirit:order="6900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN53_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN53 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN53_WIDTH" spirit:order="6800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN52_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN52 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN52_WIDTH" spirit:order="6700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN51_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN51 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN51_WIDTH" spirit:order="6600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN50_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN50 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN50_WIDTH" spirit:order="6500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN49_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN49 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN49_WIDTH" spirit:order="6400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN48_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN48 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN48_WIDTH" spirit:order="6300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN47_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN47 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN47_WIDTH" spirit:order="6200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN46_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN46 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN46_WIDTH" spirit:order="6100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN45_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN45 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN45_WIDTH" spirit:order="6000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN44_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN44 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN44_WIDTH" spirit:order="5900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN43_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN43 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN43_WIDTH" spirit:order="5800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
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- <spirit:parameter>
- <spirit:name>C_PROBE_IN42_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN42 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN42_WIDTH" spirit:order="5700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN41_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN41 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN41_WIDTH" spirit:order="5600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN40_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN40 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN40_WIDTH" spirit:order="5500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN39_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN39 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN39_WIDTH" spirit:order="5400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN38_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN38 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN38_WIDTH" spirit:order="5300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN37_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN37 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN37_WIDTH" spirit:order="5200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN36_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN36 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN36_WIDTH" spirit:order="5100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN35_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN35 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN35_WIDTH" spirit:order="5000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN34_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN34 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN34_WIDTH" spirit:order="4900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN33_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN33 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN33_WIDTH" spirit:order="4800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN32_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN32 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN32_WIDTH" spirit:order="4700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN31_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN31 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN31_WIDTH" spirit:order="4600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN30_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN30 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN30_WIDTH" spirit:order="4500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN29_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN29 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN29_WIDTH" spirit:order="4400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN28_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN28 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN28_WIDTH" spirit:order="4300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN27_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN27 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN27_WIDTH" spirit:order="4200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN26_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN26 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN26_WIDTH" spirit:order="4100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN25_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN25 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN25_WIDTH" spirit:order="4000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN24_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN24 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN24_WIDTH" spirit:order="3900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN23_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN23 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN23_WIDTH" spirit:order="3800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN22_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN22 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN22_WIDTH" spirit:order="3700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN21_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN21 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN21_WIDTH" spirit:order="3600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN20_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN20 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN20_WIDTH" spirit:order="3500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN19_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN19 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN19_WIDTH" spirit:order="3400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN18_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN18 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN18_WIDTH" spirit:order="3300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN17_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN17 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN17_WIDTH" spirit:order="3200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN16_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN16 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN16_WIDTH" spirit:order="3100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN15_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN15 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN15_WIDTH" spirit:order="3000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN14_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN14 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN14_WIDTH" spirit:order="2900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN13_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN13 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN13_WIDTH" spirit:order="2800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN12_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN12 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN12_WIDTH" spirit:order="2700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN11_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN11 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN11_WIDTH" spirit:order="2600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN10_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN10 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN10_WIDTH" spirit:order="2500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN9_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN9 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN9_WIDTH" spirit:order="2400" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN8_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN8 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN8_WIDTH" spirit:order="2300" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN7_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN7 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN7_WIDTH" spirit:order="2200" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN6_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN6 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN6_WIDTH" spirit:order="2100" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN5_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN5 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN5_WIDTH" spirit:order="2000" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN4_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN4 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN4_WIDTH" spirit:order="1900" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN3_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN3 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN3_WIDTH" spirit:order="1800" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN2_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN2 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN2_WIDTH" spirit:order="1700" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN1_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN1 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN1_WIDTH" spirit:order="1600" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_PROBE_IN0_WIDTH</spirit:name>
- <spirit:displayName>PROBE IN0 WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_PROBE_IN0_WIDTH" spirit:order="1500" spirit:minimum="1" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_EN_SYNCHRONIZATION</spirit:name>
- <spirit:displayName>C En Synchronization</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EN_SYNCHRONIZATION" spirit:order="1400">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_NUM_PROBE_OUT</spirit:name>
- <spirit:displayName>Output Probe Count</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PROBE_OUT" spirit:order="1300" spirit:minimum="0" spirit:maximum="256" spirit:rangeType="long">1</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_EN_PROBE_IN_ACTIVITY</spirit:name>
- <spirit:displayName>Enable Input Probe Activity Detectors</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1200">0</spirit:value>
- <spirit:vendorExtensions>
- <xilinx:parameterInfo>
- <xilinx:enablement>
- <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_EN_PROBE_IN_ACTIVITY">false</xilinx:isEnabled>
- </xilinx:enablement>
- </xilinx:parameterInfo>
- </spirit:vendorExtensions>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>C_NUM_PROBE_IN</spirit:name>
- <spirit:displayName>Input Probe Count</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PROBE_IN" spirit:order="1100" spirit:minimum="0" spirit:maximum="256" spirit:rangeType="long">0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>Component_Name</spirit:name>
- <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">scalp_zynqps_vio_0_0</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <xilinx:coreExtensions>
- <xilinx:displayName>VIO (Virtual Input/Output)</xilinx:displayName>
- <xilinx:coreRevision>19</xilinx:coreRevision>
- <xilinx:configElementInfos>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY" xilinx:valueSource="user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_IN" xilinx:valueSource="user"/>
- </xilinx:configElementInfos>
- </xilinx:coreExtensions>
- <xilinx:packagingInfo>
- <xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="6dc84eee"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cba6f26c"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="c0f7174e"/>
- <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="6eab3a1a"/>
- <xilinx:checksum xilinx:scope="parameters" xilinx:value="740caa1f"/>
- </xilinx:packagingInfo>
- </spirit:vendorExtensions>
-</spirit:component>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_ooc.xdc b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_ooc.xdc
deleted file mode 100644
index 37351243300c961ae1071ef101e8074e7640d9bf..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_ooc.xdc
+++ /dev/null
@@ -1,57 +0,0 @@
-# (c) Copyright 2012-2020 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-# DO NOT MODIFY THIS FILE.
-# #########################################################
-#
-# This XDC is used only in OOC mode for synthesis, implementation
-#
-# #########################################################
-
-
-create_clock -period 8 -name clk [get_ports clk]
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.v
deleted file mode 100644
index 41823dacb8ae42e965e66fdf3526ce9e2be005c9..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.v
+++ /dev/null
@@ -1,7221 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:36 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.v
-// Design : scalp_zynqps_vio_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_vio_0_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module scalp_zynqps_vio_0_0
- (clk,
- probe_out0);
- input clk;
- output [0:0]probe_out0;
-
- wire clk;
- wire [0:0]probe_out0;
- wire [0:0]NLW_inst_probe_out1_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out10_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out100_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out101_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out102_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out103_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out104_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out105_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out106_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out107_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out108_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out109_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out11_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out110_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out111_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out112_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out113_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out114_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out115_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out116_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out117_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out118_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out119_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out12_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out120_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out121_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out122_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out123_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out124_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out125_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out126_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out127_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out128_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out129_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out13_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out130_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out131_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out132_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out133_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out134_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out135_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out136_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out137_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out138_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out139_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out14_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out140_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out141_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out142_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out143_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out144_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out145_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out146_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out147_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out148_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out149_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out15_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out150_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out151_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out152_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out153_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out154_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out155_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out156_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out157_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out158_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out159_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out16_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out160_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out161_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out162_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out163_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out164_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out165_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out166_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out167_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out168_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out169_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out17_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out170_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out171_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out172_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out173_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out174_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out175_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out176_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out177_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out178_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out179_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out18_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out180_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out181_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out182_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out183_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out184_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out185_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out186_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out187_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out188_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out189_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out19_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out190_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out191_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out192_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out193_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out194_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out195_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out196_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out197_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out198_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out199_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out2_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out20_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out200_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out201_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out202_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out203_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out204_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out205_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out206_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out207_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out208_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out209_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out21_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out210_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out211_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out212_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out213_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out214_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out215_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out216_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out217_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out218_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out219_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out22_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out220_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out221_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out222_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out223_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out224_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out225_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out226_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out227_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out228_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out229_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out23_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out230_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out231_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out232_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out233_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out234_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out235_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out236_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out237_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out238_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out239_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out24_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out240_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out241_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out242_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out243_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out244_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out245_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out246_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out247_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out248_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out249_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out25_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out250_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out251_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out252_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out253_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out254_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out255_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out26_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out27_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out28_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out29_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out3_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out30_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out31_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out32_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out33_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out34_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out35_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out36_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out37_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out38_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out39_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out4_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out40_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out41_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out42_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out43_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out44_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out45_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out46_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out47_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out48_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out49_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out5_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out50_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out51_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out52_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out53_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out54_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out55_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out56_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out57_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out58_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out59_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out6_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out60_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out61_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out62_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out63_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out64_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out65_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out66_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out67_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out68_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out69_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out7_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out70_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out71_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out72_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out73_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out74_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out75_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out76_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out77_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out78_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out79_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out8_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out80_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out81_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out82_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out83_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out84_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out85_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out86_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out87_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out88_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out89_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out9_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out90_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out91_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out92_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out93_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out94_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out95_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out96_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out97_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out98_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out99_UNCONNECTED;
- wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;
-
- (* C_BUILD_REVISION = "0" *)
- (* C_BUS_ADDR_WIDTH = "17" *)
- (* C_BUS_DATA_WIDTH = "16" *)
- (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_MAJOR_VER = "2" *)
- (* C_CORE_MINOR_ALPHA_VER = "97" *)
- (* C_CORE_MINOR_VER = "0" *)
- (* C_CORE_TYPE = "2" *)
- (* C_CSE_DRV_VER = "1" *)
- (* C_EN_PROBE_IN_ACTIVITY = "0" *)
- (* C_EN_SYNCHRONIZATION = "1" *)
- (* C_MAJOR_VERSION = "2013" *)
- (* C_MAX_NUM_PROBE = "256" *)
- (* C_MAX_WIDTH_PER_PROBE = "256" *)
- (* C_MINOR_VERSION = "1" *)
- (* C_NEXT_SLAVE = "0" *)
- (* C_NUM_PROBE_IN = "0" *)
- (* C_NUM_PROBE_OUT = "1" *)
- (* C_PIPE_IFACE = "0" *)
- (* C_PROBE_IN0_WIDTH = "1" *)
- (* C_PROBE_IN100_WIDTH = "1" *)
- (* C_PROBE_IN101_WIDTH = "1" *)
- (* C_PROBE_IN102_WIDTH = "1" *)
- (* C_PROBE_IN103_WIDTH = "1" *)
- (* C_PROBE_IN104_WIDTH = "1" *)
- (* C_PROBE_IN105_WIDTH = "1" *)
- (* C_PROBE_IN106_WIDTH = "1" *)
- (* C_PROBE_IN107_WIDTH = "1" *)
- (* C_PROBE_IN108_WIDTH = "1" *)
- (* C_PROBE_IN109_WIDTH = "1" *)
- (* C_PROBE_IN10_WIDTH = "1" *)
- (* C_PROBE_IN110_WIDTH = "1" *)
- (* C_PROBE_IN111_WIDTH = "1" *)
- (* C_PROBE_IN112_WIDTH = "1" *)
- (* C_PROBE_IN113_WIDTH = "1" *)
- (* C_PROBE_IN114_WIDTH = "1" *)
- (* C_PROBE_IN115_WIDTH = "1" *)
- (* C_PROBE_IN116_WIDTH = "1" *)
- (* C_PROBE_IN117_WIDTH = "1" *)
- (* C_PROBE_IN118_WIDTH = "1" *)
- (* C_PROBE_IN119_WIDTH = "1" *)
- (* C_PROBE_IN11_WIDTH = "1" *)
- (* C_PROBE_IN120_WIDTH = "1" *)
- (* C_PROBE_IN121_WIDTH = "1" *)
- (* C_PROBE_IN122_WIDTH = "1" *)
- (* C_PROBE_IN123_WIDTH = "1" *)
- (* C_PROBE_IN124_WIDTH = "1" *)
- (* C_PROBE_IN125_WIDTH = "1" *)
- (* C_PROBE_IN126_WIDTH = "1" *)
- (* C_PROBE_IN127_WIDTH = "1" *)
- (* C_PROBE_IN128_WIDTH = "1" *)
- (* C_PROBE_IN129_WIDTH = "1" *)
- (* C_PROBE_IN12_WIDTH = "1" *)
- (* C_PROBE_IN130_WIDTH = "1" *)
- (* C_PROBE_IN131_WIDTH = "1" *)
- (* C_PROBE_IN132_WIDTH = "1" *)
- (* C_PROBE_IN133_WIDTH = "1" *)
- (* C_PROBE_IN134_WIDTH = "1" *)
- (* C_PROBE_IN135_WIDTH = "1" *)
- (* C_PROBE_IN136_WIDTH = "1" *)
- (* C_PROBE_IN137_WIDTH = "1" *)
- (* C_PROBE_IN138_WIDTH = "1" *)
- (* C_PROBE_IN139_WIDTH = "1" *)
- (* C_PROBE_IN13_WIDTH = "1" *)
- (* C_PROBE_IN140_WIDTH = "1" *)
- (* C_PROBE_IN141_WIDTH = "1" *)
- (* C_PROBE_IN142_WIDTH = "1" *)
- (* C_PROBE_IN143_WIDTH = "1" *)
- (* C_PROBE_IN144_WIDTH = "1" *)
- (* C_PROBE_IN145_WIDTH = "1" *)
- (* C_PROBE_IN146_WIDTH = "1" *)
- (* C_PROBE_IN147_WIDTH = "1" *)
- (* C_PROBE_IN148_WIDTH = "1" *)
- (* C_PROBE_IN149_WIDTH = "1" *)
- (* C_PROBE_IN14_WIDTH = "1" *)
- (* C_PROBE_IN150_WIDTH = "1" *)
- (* C_PROBE_IN151_WIDTH = "1" *)
- (* C_PROBE_IN152_WIDTH = "1" *)
- (* C_PROBE_IN153_WIDTH = "1" *)
- (* C_PROBE_IN154_WIDTH = "1" *)
- (* C_PROBE_IN155_WIDTH = "1" *)
- (* C_PROBE_IN156_WIDTH = "1" *)
- (* C_PROBE_IN157_WIDTH = "1" *)
- (* C_PROBE_IN158_WIDTH = "1" *)
- (* C_PROBE_IN159_WIDTH = "1" *)
- (* C_PROBE_IN15_WIDTH = "1" *)
- (* C_PROBE_IN160_WIDTH = "1" *)
- (* C_PROBE_IN161_WIDTH = "1" *)
- (* C_PROBE_IN162_WIDTH = "1" *)
- (* C_PROBE_IN163_WIDTH = "1" *)
- (* C_PROBE_IN164_WIDTH = "1" *)
- (* C_PROBE_IN165_WIDTH = "1" *)
- (* C_PROBE_IN166_WIDTH = "1" *)
- (* C_PROBE_IN167_WIDTH = "1" *)
- (* C_PROBE_IN168_WIDTH = "1" *)
- (* C_PROBE_IN169_WIDTH = "1" *)
- (* C_PROBE_IN16_WIDTH = "1" *)
- (* C_PROBE_IN170_WIDTH = "1" *)
- (* C_PROBE_IN171_WIDTH = "1" *)
- (* C_PROBE_IN172_WIDTH = "1" *)
- (* C_PROBE_IN173_WIDTH = "1" *)
- (* C_PROBE_IN174_WIDTH = "1" *)
- (* C_PROBE_IN175_WIDTH = "1" *)
- (* C_PROBE_IN176_WIDTH = "1" *)
- (* C_PROBE_IN177_WIDTH = "1" *)
- (* C_PROBE_IN178_WIDTH = "1" *)
- (* C_PROBE_IN179_WIDTH = "1" *)
- (* C_PROBE_IN17_WIDTH = "1" *)
- (* C_PROBE_IN180_WIDTH = "1" *)
- (* C_PROBE_IN181_WIDTH = "1" *)
- (* C_PROBE_IN182_WIDTH = "1" *)
- (* C_PROBE_IN183_WIDTH = "1" *)
- (* C_PROBE_IN184_WIDTH = "1" *)
- (* C_PROBE_IN185_WIDTH = "1" *)
- (* C_PROBE_IN186_WIDTH = "1" *)
- (* C_PROBE_IN187_WIDTH = "1" *)
- (* C_PROBE_IN188_WIDTH = "1" *)
- (* C_PROBE_IN189_WIDTH = "1" *)
- (* C_PROBE_IN18_WIDTH = "1" *)
- (* C_PROBE_IN190_WIDTH = "1" *)
- (* C_PROBE_IN191_WIDTH = "1" *)
- (* C_PROBE_IN192_WIDTH = "1" *)
- (* C_PROBE_IN193_WIDTH = "1" *)
- (* C_PROBE_IN194_WIDTH = "1" *)
- (* C_PROBE_IN195_WIDTH = "1" *)
- (* C_PROBE_IN196_WIDTH = "1" *)
- (* C_PROBE_IN197_WIDTH = "1" *)
- (* C_PROBE_IN198_WIDTH = "1" *)
- (* C_PROBE_IN199_WIDTH = "1" *)
- (* C_PROBE_IN19_WIDTH = "1" *)
- (* C_PROBE_IN1_WIDTH = "1" *)
- (* C_PROBE_IN200_WIDTH = "1" *)
- (* C_PROBE_IN201_WIDTH = "1" *)
- (* C_PROBE_IN202_WIDTH = "1" *)
- (* C_PROBE_IN203_WIDTH = "1" *)
- (* C_PROBE_IN204_WIDTH = "1" *)
- (* C_PROBE_IN205_WIDTH = "1" *)
- (* C_PROBE_IN206_WIDTH = "1" *)
- (* C_PROBE_IN207_WIDTH = "1" *)
- (* C_PROBE_IN208_WIDTH = "1" *)
- (* C_PROBE_IN209_WIDTH = "1" *)
- (* C_PROBE_IN20_WIDTH = "1" *)
- (* C_PROBE_IN210_WIDTH = "1" *)
- (* C_PROBE_IN211_WIDTH = "1" *)
- (* C_PROBE_IN212_WIDTH = "1" *)
- (* C_PROBE_IN213_WIDTH = "1" *)
- (* C_PROBE_IN214_WIDTH = "1" *)
- (* C_PROBE_IN215_WIDTH = "1" *)
- (* C_PROBE_IN216_WIDTH = "1" *)
- (* C_PROBE_IN217_WIDTH = "1" *)
- (* C_PROBE_IN218_WIDTH = "1" *)
- (* C_PROBE_IN219_WIDTH = "1" *)
- (* C_PROBE_IN21_WIDTH = "1" *)
- (* C_PROBE_IN220_WIDTH = "1" *)
- (* C_PROBE_IN221_WIDTH = "1" *)
- (* C_PROBE_IN222_WIDTH = "1" *)
- (* C_PROBE_IN223_WIDTH = "1" *)
- (* C_PROBE_IN224_WIDTH = "1" *)
- (* C_PROBE_IN225_WIDTH = "1" *)
- (* C_PROBE_IN226_WIDTH = "1" *)
- (* C_PROBE_IN227_WIDTH = "1" *)
- (* C_PROBE_IN228_WIDTH = "1" *)
- (* C_PROBE_IN229_WIDTH = "1" *)
- (* C_PROBE_IN22_WIDTH = "1" *)
- (* C_PROBE_IN230_WIDTH = "1" *)
- (* C_PROBE_IN231_WIDTH = "1" *)
- (* C_PROBE_IN232_WIDTH = "1" *)
- (* C_PROBE_IN233_WIDTH = "1" *)
- (* C_PROBE_IN234_WIDTH = "1" *)
- (* C_PROBE_IN235_WIDTH = "1" *)
- (* C_PROBE_IN236_WIDTH = "1" *)
- (* C_PROBE_IN237_WIDTH = "1" *)
- (* C_PROBE_IN238_WIDTH = "1" *)
- (* C_PROBE_IN239_WIDTH = "1" *)
- (* C_PROBE_IN23_WIDTH = "1" *)
- (* C_PROBE_IN240_WIDTH = "1" *)
- (* C_PROBE_IN241_WIDTH = "1" *)
- (* C_PROBE_IN242_WIDTH = "1" *)
- (* C_PROBE_IN243_WIDTH = "1" *)
- (* C_PROBE_IN244_WIDTH = "1" *)
- (* C_PROBE_IN245_WIDTH = "1" *)
- (* C_PROBE_IN246_WIDTH = "1" *)
- (* C_PROBE_IN247_WIDTH = "1" *)
- (* C_PROBE_IN248_WIDTH = "1" *)
- (* C_PROBE_IN249_WIDTH = "1" *)
- (* C_PROBE_IN24_WIDTH = "1" *)
- (* C_PROBE_IN250_WIDTH = "1" *)
- (* C_PROBE_IN251_WIDTH = "1" *)
- (* C_PROBE_IN252_WIDTH = "1" *)
- (* C_PROBE_IN253_WIDTH = "1" *)
- (* C_PROBE_IN254_WIDTH = "1" *)
- (* C_PROBE_IN255_WIDTH = "1" *)
- (* C_PROBE_IN25_WIDTH = "1" *)
- (* C_PROBE_IN26_WIDTH = "1" *)
- (* C_PROBE_IN27_WIDTH = "1" *)
- (* C_PROBE_IN28_WIDTH = "1" *)
- (* C_PROBE_IN29_WIDTH = "1" *)
- (* C_PROBE_IN2_WIDTH = "1" *)
- (* C_PROBE_IN30_WIDTH = "1" *)
- (* C_PROBE_IN31_WIDTH = "1" *)
- (* C_PROBE_IN32_WIDTH = "1" *)
- (* C_PROBE_IN33_WIDTH = "1" *)
- (* C_PROBE_IN34_WIDTH = "1" *)
- (* C_PROBE_IN35_WIDTH = "1" *)
- (* C_PROBE_IN36_WIDTH = "1" *)
- (* C_PROBE_IN37_WIDTH = "1" *)
- (* C_PROBE_IN38_WIDTH = "1" *)
- (* C_PROBE_IN39_WIDTH = "1" *)
- (* C_PROBE_IN3_WIDTH = "1" *)
- (* C_PROBE_IN40_WIDTH = "1" *)
- (* C_PROBE_IN41_WIDTH = "1" *)
- (* C_PROBE_IN42_WIDTH = "1" *)
- (* C_PROBE_IN43_WIDTH = "1" *)
- (* C_PROBE_IN44_WIDTH = "1" *)
- (* C_PROBE_IN45_WIDTH = "1" *)
- (* C_PROBE_IN46_WIDTH = "1" *)
- (* C_PROBE_IN47_WIDTH = "1" *)
- (* C_PROBE_IN48_WIDTH = "1" *)
- (* C_PROBE_IN49_WIDTH = "1" *)
- (* C_PROBE_IN4_WIDTH = "1" *)
- (* C_PROBE_IN50_WIDTH = "1" *)
- (* C_PROBE_IN51_WIDTH = "1" *)
- (* C_PROBE_IN52_WIDTH = "1" *)
- (* C_PROBE_IN53_WIDTH = "1" *)
- (* C_PROBE_IN54_WIDTH = "1" *)
- (* C_PROBE_IN55_WIDTH = "1" *)
- (* C_PROBE_IN56_WIDTH = "1" *)
- (* C_PROBE_IN57_WIDTH = "1" *)
- (* C_PROBE_IN58_WIDTH = "1" *)
- (* C_PROBE_IN59_WIDTH = "1" *)
- (* C_PROBE_IN5_WIDTH = "1" *)
- (* C_PROBE_IN60_WIDTH = "1" *)
- (* C_PROBE_IN61_WIDTH = "1" *)
- (* C_PROBE_IN62_WIDTH = "1" *)
- (* C_PROBE_IN63_WIDTH = "1" *)
- (* C_PROBE_IN64_WIDTH = "1" *)
- (* C_PROBE_IN65_WIDTH = "1" *)
- (* C_PROBE_IN66_WIDTH = "1" *)
- (* C_PROBE_IN67_WIDTH = "1" *)
- (* C_PROBE_IN68_WIDTH = "1" *)
- (* C_PROBE_IN69_WIDTH = "1" *)
- (* C_PROBE_IN6_WIDTH = "1" *)
- (* C_PROBE_IN70_WIDTH = "1" *)
- (* C_PROBE_IN71_WIDTH = "1" *)
- (* C_PROBE_IN72_WIDTH = "1" *)
- (* C_PROBE_IN73_WIDTH = "1" *)
- (* C_PROBE_IN74_WIDTH = "1" *)
- (* C_PROBE_IN75_WIDTH = "1" *)
- (* C_PROBE_IN76_WIDTH = "1" *)
- (* C_PROBE_IN77_WIDTH = "1" *)
- (* C_PROBE_IN78_WIDTH = "1" *)
- (* C_PROBE_IN79_WIDTH = "1" *)
- (* C_PROBE_IN7_WIDTH = "1" *)
- (* C_PROBE_IN80_WIDTH = "1" *)
- (* C_PROBE_IN81_WIDTH = "1" *)
- (* C_PROBE_IN82_WIDTH = "1" *)
- (* C_PROBE_IN83_WIDTH = "1" *)
- (* C_PROBE_IN84_WIDTH = "1" *)
- (* C_PROBE_IN85_WIDTH = "1" *)
- (* C_PROBE_IN86_WIDTH = "1" *)
- (* C_PROBE_IN87_WIDTH = "1" *)
- (* C_PROBE_IN88_WIDTH = "1" *)
- (* C_PROBE_IN89_WIDTH = "1" *)
- (* C_PROBE_IN8_WIDTH = "1" *)
- (* C_PROBE_IN90_WIDTH = "1" *)
- (* C_PROBE_IN91_WIDTH = "1" *)
- (* C_PROBE_IN92_WIDTH = "1" *)
- (* C_PROBE_IN93_WIDTH = "1" *)
- (* C_PROBE_IN94_WIDTH = "1" *)
- (* C_PROBE_IN95_WIDTH = "1" *)
- (* C_PROBE_IN96_WIDTH = "1" *)
- (* C_PROBE_IN97_WIDTH = "1" *)
- (* C_PROBE_IN98_WIDTH = "1" *)
- (* C_PROBE_IN99_WIDTH = "1" *)
- (* C_PROBE_IN9_WIDTH = "1" *)
- (* C_PROBE_OUT0_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT0_WIDTH = "1" *)
- (* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT100_WIDTH = "1" *)
- (* C_PROBE_OUT101_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT101_WIDTH = "1" *)
- (* C_PROBE_OUT102_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT102_WIDTH = "1" *)
- (* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT103_WIDTH = "1" *)
- (* C_PROBE_OUT104_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT104_WIDTH = "1" *)
- (* C_PROBE_OUT105_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT105_WIDTH = "1" *)
- (* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT106_WIDTH = "1" *)
- (* C_PROBE_OUT107_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT107_WIDTH = "1" *)
- (* C_PROBE_OUT108_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT108_WIDTH = "1" *)
- (* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT109_WIDTH = "1" *)
- (* C_PROBE_OUT10_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT10_WIDTH = "1" *)
- (* C_PROBE_OUT110_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT110_WIDTH = "1" *)
- (* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT111_WIDTH = "1" *)
- (* C_PROBE_OUT112_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT112_WIDTH = "1" *)
- (* C_PROBE_OUT113_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT113_WIDTH = "1" *)
- (* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT114_WIDTH = "1" *)
- (* C_PROBE_OUT115_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT115_WIDTH = "1" *)
- (* C_PROBE_OUT116_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT116_WIDTH = "1" *)
- (* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT117_WIDTH = "1" *)
- (* C_PROBE_OUT118_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT118_WIDTH = "1" *)
- (* C_PROBE_OUT119_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT119_WIDTH = "1" *)
- (* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT11_WIDTH = "1" *)
- (* C_PROBE_OUT120_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT120_WIDTH = "1" *)
- (* C_PROBE_OUT121_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT121_WIDTH = "1" *)
- (* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT122_WIDTH = "1" *)
- (* C_PROBE_OUT123_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT123_WIDTH = "1" *)
- (* C_PROBE_OUT124_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT124_WIDTH = "1" *)
- (* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT125_WIDTH = "1" *)
- (* C_PROBE_OUT126_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT126_WIDTH = "1" *)
- (* C_PROBE_OUT127_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT127_WIDTH = "1" *)
- (* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT128_WIDTH = "1" *)
- (* C_PROBE_OUT129_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT129_WIDTH = "1" *)
- (* C_PROBE_OUT12_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT12_WIDTH = "1" *)
- (* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT130_WIDTH = "1" *)
- (* C_PROBE_OUT131_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT131_WIDTH = "1" *)
- (* C_PROBE_OUT132_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT132_WIDTH = "1" *)
- (* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT133_WIDTH = "1" *)
- (* C_PROBE_OUT134_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT134_WIDTH = "1" *)
- (* C_PROBE_OUT135_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT135_WIDTH = "1" *)
- (* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT136_WIDTH = "1" *)
- (* C_PROBE_OUT137_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT137_WIDTH = "1" *)
- (* C_PROBE_OUT138_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT138_WIDTH = "1" *)
- (* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT139_WIDTH = "1" *)
- (* C_PROBE_OUT13_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT13_WIDTH = "1" *)
- (* C_PROBE_OUT140_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT140_WIDTH = "1" *)
- (* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT141_WIDTH = "1" *)
- (* C_PROBE_OUT142_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT142_WIDTH = "1" *)
- (* C_PROBE_OUT143_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT143_WIDTH = "1" *)
- (* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT144_WIDTH = "1" *)
- (* C_PROBE_OUT145_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT145_WIDTH = "1" *)
- (* C_PROBE_OUT146_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT146_WIDTH = "1" *)
- (* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT147_WIDTH = "1" *)
- (* C_PROBE_OUT148_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT148_WIDTH = "1" *)
- (* C_PROBE_OUT149_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT149_WIDTH = "1" *)
- (* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT14_WIDTH = "1" *)
- (* C_PROBE_OUT150_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT150_WIDTH = "1" *)
- (* C_PROBE_OUT151_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT151_WIDTH = "1" *)
- (* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT152_WIDTH = "1" *)
- (* C_PROBE_OUT153_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT153_WIDTH = "1" *)
- (* C_PROBE_OUT154_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT154_WIDTH = "1" *)
- (* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT155_WIDTH = "1" *)
- (* C_PROBE_OUT156_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT156_WIDTH = "1" *)
- (* C_PROBE_OUT157_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT157_WIDTH = "1" *)
- (* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT158_WIDTH = "1" *)
- (* C_PROBE_OUT159_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT159_WIDTH = "1" *)
- (* C_PROBE_OUT15_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT15_WIDTH = "1" *)
- (* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT160_WIDTH = "1" *)
- (* C_PROBE_OUT161_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT161_WIDTH = "1" *)
- (* C_PROBE_OUT162_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT162_WIDTH = "1" *)
- (* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT163_WIDTH = "1" *)
- (* C_PROBE_OUT164_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT164_WIDTH = "1" *)
- (* C_PROBE_OUT165_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT165_WIDTH = "1" *)
- (* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT166_WIDTH = "1" *)
- (* C_PROBE_OUT167_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT167_WIDTH = "1" *)
- (* C_PROBE_OUT168_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT168_WIDTH = "1" *)
- (* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT169_WIDTH = "1" *)
- (* C_PROBE_OUT16_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT16_WIDTH = "1" *)
- (* C_PROBE_OUT170_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT170_WIDTH = "1" *)
- (* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT171_WIDTH = "1" *)
- (* C_PROBE_OUT172_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT172_WIDTH = "1" *)
- (* C_PROBE_OUT173_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT173_WIDTH = "1" *)
- (* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT174_WIDTH = "1" *)
- (* C_PROBE_OUT175_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT175_WIDTH = "1" *)
- (* C_PROBE_OUT176_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT176_WIDTH = "1" *)
- (* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT177_WIDTH = "1" *)
- (* C_PROBE_OUT178_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT178_WIDTH = "1" *)
- (* C_PROBE_OUT179_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT179_WIDTH = "1" *)
- (* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT17_WIDTH = "1" *)
- (* C_PROBE_OUT180_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT180_WIDTH = "1" *)
- (* C_PROBE_OUT181_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT181_WIDTH = "1" *)
- (* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT182_WIDTH = "1" *)
- (* C_PROBE_OUT183_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT183_WIDTH = "1" *)
- (* C_PROBE_OUT184_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT184_WIDTH = "1" *)
- (* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT185_WIDTH = "1" *)
- (* C_PROBE_OUT186_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT186_WIDTH = "1" *)
- (* C_PROBE_OUT187_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT187_WIDTH = "1" *)
- (* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT188_WIDTH = "1" *)
- (* C_PROBE_OUT189_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT189_WIDTH = "1" *)
- (* C_PROBE_OUT18_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT18_WIDTH = "1" *)
- (* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT190_WIDTH = "1" *)
- (* C_PROBE_OUT191_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT191_WIDTH = "1" *)
- (* C_PROBE_OUT192_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT192_WIDTH = "1" *)
- (* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT193_WIDTH = "1" *)
- (* C_PROBE_OUT194_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT194_WIDTH = "1" *)
- (* C_PROBE_OUT195_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT195_WIDTH = "1" *)
- (* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT196_WIDTH = "1" *)
- (* C_PROBE_OUT197_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT197_WIDTH = "1" *)
- (* C_PROBE_OUT198_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT198_WIDTH = "1" *)
- (* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT199_WIDTH = "1" *)
- (* C_PROBE_OUT19_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT19_WIDTH = "1" *)
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- (* C_PROBE_OUT1_WIDTH = "1" *)
- (* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT200_WIDTH = "1" *)
- (* C_PROBE_OUT201_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT201_WIDTH = "1" *)
- (* C_PROBE_OUT202_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT202_WIDTH = "1" *)
- (* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT203_WIDTH = "1" *)
- (* C_PROBE_OUT204_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT204_WIDTH = "1" *)
- (* C_PROBE_OUT205_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT205_WIDTH = "1" *)
- (* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT206_WIDTH = "1" *)
- (* C_PROBE_OUT207_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT207_WIDTH = "1" *)
- (* C_PROBE_OUT208_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT208_WIDTH = "1" *)
- (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT209_WIDTH = "1" *)
- (* C_PROBE_OUT20_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT20_WIDTH = "1" *)
- (* C_PROBE_OUT210_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT210_WIDTH = "1" *)
- (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT211_WIDTH = "1" *)
- (* C_PROBE_OUT212_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT212_WIDTH = "1" *)
- (* C_PROBE_OUT213_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT213_WIDTH = "1" *)
- (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT214_WIDTH = "1" *)
- (* C_PROBE_OUT215_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT215_WIDTH = "1" *)
- (* C_PROBE_OUT216_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT216_WIDTH = "1" *)
- (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT217_WIDTH = "1" *)
- (* C_PROBE_OUT218_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT218_WIDTH = "1" *)
- (* C_PROBE_OUT219_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT219_WIDTH = "1" *)
- (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT21_WIDTH = "1" *)
- (* C_PROBE_OUT220_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT220_WIDTH = "1" *)
- (* C_PROBE_OUT221_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT221_WIDTH = "1" *)
- (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT222_WIDTH = "1" *)
- (* C_PROBE_OUT223_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT223_WIDTH = "1" *)
- (* C_PROBE_OUT224_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT224_WIDTH = "1" *)
- (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT225_WIDTH = "1" *)
- (* C_PROBE_OUT226_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT226_WIDTH = "1" *)
- (* C_PROBE_OUT227_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT227_WIDTH = "1" *)
- (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT228_WIDTH = "1" *)
- (* C_PROBE_OUT229_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT229_WIDTH = "1" *)
- (* C_PROBE_OUT22_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT22_WIDTH = "1" *)
- (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT230_WIDTH = "1" *)
- (* C_PROBE_OUT231_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT231_WIDTH = "1" *)
- (* C_PROBE_OUT232_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT232_WIDTH = "1" *)
- (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT233_WIDTH = "1" *)
- (* C_PROBE_OUT234_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT234_WIDTH = "1" *)
- (* C_PROBE_OUT235_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT235_WIDTH = "1" *)
- (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT236_WIDTH = "1" *)
- (* C_PROBE_OUT237_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT237_WIDTH = "1" *)
- (* C_PROBE_OUT238_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT238_WIDTH = "1" *)
- (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT239_WIDTH = "1" *)
- (* C_PROBE_OUT23_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT23_WIDTH = "1" *)
- (* C_PROBE_OUT240_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT240_WIDTH = "1" *)
- (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT241_WIDTH = "1" *)
- (* C_PROBE_OUT242_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT242_WIDTH = "1" *)
- (* C_PROBE_OUT243_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT243_WIDTH = "1" *)
- (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT244_WIDTH = "1" *)
- (* C_PROBE_OUT245_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT245_WIDTH = "1" *)
- (* C_PROBE_OUT246_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT246_WIDTH = "1" *)
- (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT247_WIDTH = "1" *)
- (* C_PROBE_OUT248_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT248_WIDTH = "1" *)
- (* C_PROBE_OUT249_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT249_WIDTH = "1" *)
- (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT24_WIDTH = "1" *)
- (* C_PROBE_OUT250_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT250_WIDTH = "1" *)
- (* C_PROBE_OUT251_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT251_WIDTH = "1" *)
- (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT252_WIDTH = "1" *)
- (* C_PROBE_OUT253_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT253_WIDTH = "1" *)
- (* C_PROBE_OUT254_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT254_WIDTH = "1" *)
- (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT255_WIDTH = "1" *)
- (* C_PROBE_OUT25_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT25_WIDTH = "1" *)
- (* C_PROBE_OUT26_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT26_WIDTH = "1" *)
- (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT27_WIDTH = "1" *)
- (* C_PROBE_OUT28_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT28_WIDTH = "1" *)
- (* C_PROBE_OUT29_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT29_WIDTH = "1" *)
- (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT2_WIDTH = "1" *)
- (* C_PROBE_OUT30_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT30_WIDTH = "1" *)
- (* C_PROBE_OUT31_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT31_WIDTH = "1" *)
- (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT32_WIDTH = "1" *)
- (* C_PROBE_OUT33_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT33_WIDTH = "1" *)
- (* C_PROBE_OUT34_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT34_WIDTH = "1" *)
- (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT35_WIDTH = "1" *)
- (* C_PROBE_OUT36_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT36_WIDTH = "1" *)
- (* C_PROBE_OUT37_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT37_WIDTH = "1" *)
- (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT38_WIDTH = "1" *)
- (* C_PROBE_OUT39_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT39_WIDTH = "1" *)
- (* C_PROBE_OUT3_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT3_WIDTH = "1" *)
- (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT40_WIDTH = "1" *)
- (* C_PROBE_OUT41_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT41_WIDTH = "1" *)
- (* C_PROBE_OUT42_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT42_WIDTH = "1" *)
- (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT43_WIDTH = "1" *)
- (* C_PROBE_OUT44_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT44_WIDTH = "1" *)
- (* C_PROBE_OUT45_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT45_WIDTH = "1" *)
- (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT46_WIDTH = "1" *)
- (* C_PROBE_OUT47_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT47_WIDTH = "1" *)
- (* C_PROBE_OUT48_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT48_WIDTH = "1" *)
- (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT49_WIDTH = "1" *)
- (* C_PROBE_OUT4_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT4_WIDTH = "1" *)
- (* C_PROBE_OUT50_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT50_WIDTH = "1" *)
- (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT51_WIDTH = "1" *)
- (* C_PROBE_OUT52_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT52_WIDTH = "1" *)
- (* C_PROBE_OUT53_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT53_WIDTH = "1" *)
- (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT54_WIDTH = "1" *)
- (* C_PROBE_OUT55_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT55_WIDTH = "1" *)
- (* C_PROBE_OUT56_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT56_WIDTH = "1" *)
- (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT57_WIDTH = "1" *)
- (* C_PROBE_OUT58_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT58_WIDTH = "1" *)
- (* C_PROBE_OUT59_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT59_WIDTH = "1" *)
- (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT5_WIDTH = "1" *)
- (* C_PROBE_OUT60_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT60_WIDTH = "1" *)
- (* C_PROBE_OUT61_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT61_WIDTH = "1" *)
- (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT62_WIDTH = "1" *)
- (* C_PROBE_OUT63_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT63_WIDTH = "1" *)
- (* C_PROBE_OUT64_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT64_WIDTH = "1" *)
- (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT65_WIDTH = "1" *)
- (* C_PROBE_OUT66_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT66_WIDTH = "1" *)
- (* C_PROBE_OUT67_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT67_WIDTH = "1" *)
- (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT68_WIDTH = "1" *)
- (* C_PROBE_OUT69_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT69_WIDTH = "1" *)
- (* C_PROBE_OUT6_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT6_WIDTH = "1" *)
- (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT70_WIDTH = "1" *)
- (* C_PROBE_OUT71_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT71_WIDTH = "1" *)
- (* C_PROBE_OUT72_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT72_WIDTH = "1" *)
- (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT73_WIDTH = "1" *)
- (* C_PROBE_OUT74_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT74_WIDTH = "1" *)
- (* C_PROBE_OUT75_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT75_WIDTH = "1" *)
- (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT76_WIDTH = "1" *)
- (* C_PROBE_OUT77_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT77_WIDTH = "1" *)
- (* C_PROBE_OUT78_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT78_WIDTH = "1" *)
- (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT79_WIDTH = "1" *)
- (* C_PROBE_OUT7_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT7_WIDTH = "1" *)
- (* C_PROBE_OUT80_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT80_WIDTH = "1" *)
- (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT81_WIDTH = "1" *)
- (* C_PROBE_OUT82_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT82_WIDTH = "1" *)
- (* C_PROBE_OUT83_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT83_WIDTH = "1" *)
- (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT84_WIDTH = "1" *)
- (* C_PROBE_OUT85_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT85_WIDTH = "1" *)
- (* C_PROBE_OUT86_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT86_WIDTH = "1" *)
- (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT87_WIDTH = "1" *)
- (* C_PROBE_OUT88_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT88_WIDTH = "1" *)
- (* C_PROBE_OUT89_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT89_WIDTH = "1" *)
- (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT8_WIDTH = "1" *)
- (* C_PROBE_OUT90_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT90_WIDTH = "1" *)
- (* C_PROBE_OUT91_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT91_WIDTH = "1" *)
- (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT92_WIDTH = "1" *)
- (* C_PROBE_OUT93_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT93_WIDTH = "1" *)
- (* C_PROBE_OUT94_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT94_WIDTH = "1" *)
- (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT95_WIDTH = "1" *)
- (* C_PROBE_OUT96_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT96_WIDTH = "1" *)
- (* C_PROBE_OUT97_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT97_WIDTH = "1" *)
- (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT98_WIDTH = "1" *)
- (* C_PROBE_OUT99_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT99_WIDTH = "1" *)
- (* C_PROBE_OUT9_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT9_WIDTH = "1" *)
- (* C_USE_TEST_REG = "1" *)
- (* C_XDEVICEFAMILY = "zynq" *)
- (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *)
- (* C_XSDB_SLAVE_TYPE = "33" *)
- (* DONT_TOUCH *)
- (* DowngradeIPIdentifiedWarnings = "yes" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
- (* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
- (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
- (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* LC_TOTAL_PROBE_IN_WIDTH = "0" *)
- (* LC_TOTAL_PROBE_OUT_WIDTH = "1" *)
- (* syn_noprune = "1" *)
- scalp_zynqps_vio_0_0_vio_v3_0_19_vio inst
- (.clk(clk),
- .probe_in0(1'b0),
- .probe_in1(1'b0),
- .probe_in10(1'b0),
- .probe_in100(1'b0),
- .probe_in101(1'b0),
- .probe_in102(1'b0),
- .probe_in103(1'b0),
- .probe_in104(1'b0),
- .probe_in105(1'b0),
- .probe_in106(1'b0),
- .probe_in107(1'b0),
- .probe_in108(1'b0),
- .probe_in109(1'b0),
- .probe_in11(1'b0),
- .probe_in110(1'b0),
- .probe_in111(1'b0),
- .probe_in112(1'b0),
- .probe_in113(1'b0),
- .probe_in114(1'b0),
- .probe_in115(1'b0),
- .probe_in116(1'b0),
- .probe_in117(1'b0),
- .probe_in118(1'b0),
- .probe_in119(1'b0),
- .probe_in12(1'b0),
- .probe_in120(1'b0),
- .probe_in121(1'b0),
- .probe_in122(1'b0),
- .probe_in123(1'b0),
- .probe_in124(1'b0),
- .probe_in125(1'b0),
- .probe_in126(1'b0),
- .probe_in127(1'b0),
- .probe_in128(1'b0),
- .probe_in129(1'b0),
- .probe_in13(1'b0),
- .probe_in130(1'b0),
- .probe_in131(1'b0),
- .probe_in132(1'b0),
- .probe_in133(1'b0),
- .probe_in134(1'b0),
- .probe_in135(1'b0),
- .probe_in136(1'b0),
- .probe_in137(1'b0),
- .probe_in138(1'b0),
- .probe_in139(1'b0),
- .probe_in14(1'b0),
- .probe_in140(1'b0),
- .probe_in141(1'b0),
- .probe_in142(1'b0),
- .probe_in143(1'b0),
- .probe_in144(1'b0),
- .probe_in145(1'b0),
- .probe_in146(1'b0),
- .probe_in147(1'b0),
- .probe_in148(1'b0),
- .probe_in149(1'b0),
- .probe_in15(1'b0),
- .probe_in150(1'b0),
- .probe_in151(1'b0),
- .probe_in152(1'b0),
- .probe_in153(1'b0),
- .probe_in154(1'b0),
- .probe_in155(1'b0),
- .probe_in156(1'b0),
- .probe_in157(1'b0),
- .probe_in158(1'b0),
- .probe_in159(1'b0),
- .probe_in16(1'b0),
- .probe_in160(1'b0),
- .probe_in161(1'b0),
- .probe_in162(1'b0),
- .probe_in163(1'b0),
- .probe_in164(1'b0),
- .probe_in165(1'b0),
- .probe_in166(1'b0),
- .probe_in167(1'b0),
- .probe_in168(1'b0),
- .probe_in169(1'b0),
- .probe_in17(1'b0),
- .probe_in170(1'b0),
- .probe_in171(1'b0),
- .probe_in172(1'b0),
- .probe_in173(1'b0),
- .probe_in174(1'b0),
- .probe_in175(1'b0),
- .probe_in176(1'b0),
- .probe_in177(1'b0),
- .probe_in178(1'b0),
- .probe_in179(1'b0),
- .probe_in18(1'b0),
- .probe_in180(1'b0),
- .probe_in181(1'b0),
- .probe_in182(1'b0),
- .probe_in183(1'b0),
- .probe_in184(1'b0),
- .probe_in185(1'b0),
- .probe_in186(1'b0),
- .probe_in187(1'b0),
- .probe_in188(1'b0),
- .probe_in189(1'b0),
- .probe_in19(1'b0),
- .probe_in190(1'b0),
- .probe_in191(1'b0),
- .probe_in192(1'b0),
- .probe_in193(1'b0),
- .probe_in194(1'b0),
- .probe_in195(1'b0),
- .probe_in196(1'b0),
- .probe_in197(1'b0),
- .probe_in198(1'b0),
- .probe_in199(1'b0),
- .probe_in2(1'b0),
- .probe_in20(1'b0),
- .probe_in200(1'b0),
- .probe_in201(1'b0),
- .probe_in202(1'b0),
- .probe_in203(1'b0),
- .probe_in204(1'b0),
- .probe_in205(1'b0),
- .probe_in206(1'b0),
- .probe_in207(1'b0),
- .probe_in208(1'b0),
- .probe_in209(1'b0),
- .probe_in21(1'b0),
- .probe_in210(1'b0),
- .probe_in211(1'b0),
- .probe_in212(1'b0),
- .probe_in213(1'b0),
- .probe_in214(1'b0),
- .probe_in215(1'b0),
- .probe_in216(1'b0),
- .probe_in217(1'b0),
- .probe_in218(1'b0),
- .probe_in219(1'b0),
- .probe_in22(1'b0),
- .probe_in220(1'b0),
- .probe_in221(1'b0),
- .probe_in222(1'b0),
- .probe_in223(1'b0),
- .probe_in224(1'b0),
- .probe_in225(1'b0),
- .probe_in226(1'b0),
- .probe_in227(1'b0),
- .probe_in228(1'b0),
- .probe_in229(1'b0),
- .probe_in23(1'b0),
- .probe_in230(1'b0),
- .probe_in231(1'b0),
- .probe_in232(1'b0),
- .probe_in233(1'b0),
- .probe_in234(1'b0),
- .probe_in235(1'b0),
- .probe_in236(1'b0),
- .probe_in237(1'b0),
- .probe_in238(1'b0),
- .probe_in239(1'b0),
- .probe_in24(1'b0),
- .probe_in240(1'b0),
- .probe_in241(1'b0),
- .probe_in242(1'b0),
- .probe_in243(1'b0),
- .probe_in244(1'b0),
- .probe_in245(1'b0),
- .probe_in246(1'b0),
- .probe_in247(1'b0),
- .probe_in248(1'b0),
- .probe_in249(1'b0),
- .probe_in25(1'b0),
- .probe_in250(1'b0),
- .probe_in251(1'b0),
- .probe_in252(1'b0),
- .probe_in253(1'b0),
- .probe_in254(1'b0),
- .probe_in255(1'b0),
- .probe_in26(1'b0),
- .probe_in27(1'b0),
- .probe_in28(1'b0),
- .probe_in29(1'b0),
- .probe_in3(1'b0),
- .probe_in30(1'b0),
- .probe_in31(1'b0),
- .probe_in32(1'b0),
- .probe_in33(1'b0),
- .probe_in34(1'b0),
- .probe_in35(1'b0),
- .probe_in36(1'b0),
- .probe_in37(1'b0),
- .probe_in38(1'b0),
- .probe_in39(1'b0),
- .probe_in4(1'b0),
- .probe_in40(1'b0),
- .probe_in41(1'b0),
- .probe_in42(1'b0),
- .probe_in43(1'b0),
- .probe_in44(1'b0),
- .probe_in45(1'b0),
- .probe_in46(1'b0),
- .probe_in47(1'b0),
- .probe_in48(1'b0),
- .probe_in49(1'b0),
- .probe_in5(1'b0),
- .probe_in50(1'b0),
- .probe_in51(1'b0),
- .probe_in52(1'b0),
- .probe_in53(1'b0),
- .probe_in54(1'b0),
- .probe_in55(1'b0),
- .probe_in56(1'b0),
- .probe_in57(1'b0),
- .probe_in58(1'b0),
- .probe_in59(1'b0),
- .probe_in6(1'b0),
- .probe_in60(1'b0),
- .probe_in61(1'b0),
- .probe_in62(1'b0),
- .probe_in63(1'b0),
- .probe_in64(1'b0),
- .probe_in65(1'b0),
- .probe_in66(1'b0),
- .probe_in67(1'b0),
- .probe_in68(1'b0),
- .probe_in69(1'b0),
- .probe_in7(1'b0),
- .probe_in70(1'b0),
- .probe_in71(1'b0),
- .probe_in72(1'b0),
- .probe_in73(1'b0),
- .probe_in74(1'b0),
- .probe_in75(1'b0),
- .probe_in76(1'b0),
- .probe_in77(1'b0),
- .probe_in78(1'b0),
- .probe_in79(1'b0),
- .probe_in8(1'b0),
- .probe_in80(1'b0),
- .probe_in81(1'b0),
- .probe_in82(1'b0),
- .probe_in83(1'b0),
- .probe_in84(1'b0),
- .probe_in85(1'b0),
- .probe_in86(1'b0),
- .probe_in87(1'b0),
- .probe_in88(1'b0),
- .probe_in89(1'b0),
- .probe_in9(1'b0),
- .probe_in90(1'b0),
- .probe_in91(1'b0),
- .probe_in92(1'b0),
- .probe_in93(1'b0),
- .probe_in94(1'b0),
- .probe_in95(1'b0),
- .probe_in96(1'b0),
- .probe_in97(1'b0),
- .probe_in98(1'b0),
- .probe_in99(1'b0),
- .probe_out0(probe_out0),
- .probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]),
- .probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]),
- .probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]),
- .probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]),
- .probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]),
- .probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]),
- .probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]),
- .probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]),
- .probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]),
- .probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]),
- .probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]),
- .probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]),
- .probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]),
- .probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]),
- .probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]),
- .probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]),
- .probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]),
- .probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]),
- .probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]),
- .probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]),
- .probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]),
- .probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]),
- .probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]),
- .probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]),
- .probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]),
- .probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]),
- .probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]),
- .probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]),
- .probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]),
- .probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]),
- .probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]),
- .probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]),
- .probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]),
- .probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]),
- .probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]),
- .probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]),
- .probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]),
- .probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]),
- .probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]),
- .probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]),
- .probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]),
- .probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]),
- .probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]),
- .probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]),
- .probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]),
- .probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]),
- .probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]),
- .probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]),
- .probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]),
- .probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]),
- .probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]),
- .probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]),
- .probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]),
- .probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]),
- .probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]),
- .probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]),
- .probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]),
- .probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]),
- .probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]),
- .probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]),
- .probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]),
- .probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]),
- .probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]),
- .probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]),
- .probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]),
- .probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]),
- .probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]),
- .probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]),
- .probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]),
- .probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]),
- .probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]),
- .probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]),
- .probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]),
- .probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]),
- .probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]),
- .probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]),
- .probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]),
- .probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]),
- .probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]),
- .probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]),
- .probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]),
- .probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]),
- .probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]),
- .probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]),
- .probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]),
- .probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]),
- .probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]),
- .probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]),
- .probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]),
- .probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]),
- .probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]),
- .probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]),
- .probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]),
- .probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]),
- .probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]),
- .probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]),
- .probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]),
- .probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]),
- .probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]),
- .probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]),
- .probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]),
- .probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]),
- .probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]),
- .probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]),
- .probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]),
- .probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]),
- .probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]),
- .probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]),
- .probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]),
- .probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]),
- .probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]),
- .probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]),
- .probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]),
- .probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]),
- .probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]),
- .probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]),
- .probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]),
- .probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]),
- .probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]),
- .probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]),
- .probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]),
- .probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]),
- .probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]),
- .probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]),
- .probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]),
- .probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]),
- .probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]),
- .probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]),
- .probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]),
- .probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]),
- .probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]),
- .probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]),
- .probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]),
- .probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]),
- .probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]),
- .probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]),
- .probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]),
- .probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]),
- .probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]),
- .probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]),
- .probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]),
- .probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]),
- .probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]),
- .probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]),
- .probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]),
- .probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]),
- .probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]),
- .probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]),
- .probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]),
- .probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]),
- .probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]),
- .probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]),
- .probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]),
- .probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]),
- .probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]),
- .probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]),
- .probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]),
- .probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]),
- .probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]),
- .probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]),
- .probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]),
- .probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]),
- .probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]),
- .probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]),
- .probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]),
- .probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]),
- .probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]),
- .probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]),
- .probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]),
- .probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]),
- .probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]),
- .probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]),
- .probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]),
- .probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]),
- .probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]),
- .probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]),
- .probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]),
- .probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]),
- .probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]),
- .probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]),
- .probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]),
- .probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]),
- .probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]),
- .probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]),
- .probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]),
- .probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]),
- .probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]),
- .probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]),
- .probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]),
- .probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]),
- .probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]),
- .probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]),
- .probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]),
- .probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]),
- .probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]),
- .probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]),
- .probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]),
- .probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]),
- .probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]),
- .probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]),
- .probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]),
- .probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]),
- .probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]),
- .probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]),
- .probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]),
- .probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]),
- .probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]),
- .probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]),
- .probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]),
- .probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]),
- .probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]),
- .probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]),
- .probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]),
- .probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]),
- .probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]),
- .probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]),
- .probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]),
- .probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]),
- .probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]),
- .probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]),
- .probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]),
- .probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]),
- .probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]),
- .probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]),
- .probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]),
- .probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]),
- .probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]),
- .probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]),
- .probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]),
- .probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]),
- .probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]),
- .probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]),
- .probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]),
- .probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]),
- .probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]),
- .probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]),
- .probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]),
- .probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]),
- .probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]),
- .probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]),
- .probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]),
- .probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]),
- .probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]),
- .probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]),
- .probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]),
- .probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]),
- .probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]),
- .probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]),
- .probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]),
- .probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]),
- .probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]),
- .probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]),
- .probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]),
- .probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]),
- .probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]),
- .sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]));
-endmodule
-
-(* ORIG_REF_NAME = "vio_v3_0_19_decoder" *)
-module scalp_zynqps_vio_0_0_vio_v3_0_19_decoder
- (s_drdy_i,
- in0,
- SR,
- xsdb_wr__0,
- \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ,
- \G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ,
- s_do_i,
- s_rst_o,
- out,
- s_daddr_o,
- s_den_o,
- s_dwe_o,
- Q,
- Probe_out_reg);
- output s_drdy_i;
- output in0;
- output [0:0]SR;
- output xsdb_wr__0;
- output \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ;
- output \G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ;
- output [15:0]s_do_i;
- input s_rst_o;
- input out;
- input [16:0]s_daddr_o;
- input s_den_o;
- input s_dwe_o;
- input [15:0]Q;
- input [0:0]Probe_out_reg;
-
- wire \Bus_data_out[0]_i_1_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ;
- wire [0:0]Probe_out_reg;
- wire [15:0]Q;
- wire [0:0]SR;
- wire clear_int_i_1_n_0;
- wire committ_int_i_1_n_0;
- wire [15:0]data_info_probe_in;
- wire in0;
- wire int_cnt_rst;
- wire int_cnt_rst_i_1_n_0;
- wire out;
- wire [15:0]probe_out_modified;
- wire rd_en_p1;
- wire rd_en_p2;
- wire [16:0]s_daddr_o;
- wire s_den_o;
- wire [15:0]s_do_i;
- wire s_drdy_i;
- wire s_dwe_o;
- wire s_rst_o;
- wire wr_control_reg;
- wire \wr_en[2]_i_1_n_0 ;
- wire \wr_en[2]_i_2_n_0 ;
- wire \wr_en[4]_i_1_n_0 ;
- wire \wr_en[4]_i_2_n_0 ;
- wire \wr_en[4]_i_3_n_0 ;
- wire wr_probe_out_modified;
- wire [2:0]xsdb_addr_2_0_p1;
- wire [2:0]xsdb_addr_2_0_p2;
- wire xsdb_addr_8_p1;
- wire xsdb_addr_8_p2;
- wire xsdb_drdy_i_1_n_0;
- wire xsdb_rd;
- wire xsdb_wr__0;
-
- LUT3 #(
- .INIT(8'hB8))
- \Bus_data_out[0]_i_1
- (.I0(Probe_out_reg),
- .I1(xsdb_addr_8_p2),
- .I2(data_info_probe_in[0]),
- .O(\Bus_data_out[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h054A004A))
- \Bus_data_out[0]_i_2
- (.I0(xsdb_addr_2_0_p2[0]),
- .I1(in0),
- .I2(xsdb_addr_2_0_p2[1]),
- .I3(xsdb_addr_2_0_p2[2]),
- .I4(probe_out_modified[0]),
- .O(data_info_probe_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[10]_i_1
- (.I0(probe_out_modified[10]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[10]));
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[11]_i_1
- (.I0(probe_out_modified[11]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[11]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[12]_i_1
- (.I0(probe_out_modified[12]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[12]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[13]_i_1
- (.I0(probe_out_modified[13]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[13]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[14]_i_1
- (.I0(probe_out_modified[14]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[14]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[15]_i_1
- (.I0(probe_out_modified[15]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[15]));
- LUT5 #(
- .INIT(32'h05400040))
- \Bus_data_out[1]_i_1
- (.I0(xsdb_addr_2_0_p2[0]),
- .I1(probe_out_modified[1]),
- .I2(xsdb_addr_2_0_p2[2]),
- .I3(xsdb_addr_2_0_p2[1]),
- .I4(SR),
- .O(data_info_probe_in[1]));
- LUT5 #(
- .INIT(32'h05400040))
- \Bus_data_out[2]_i_1
- (.I0(xsdb_addr_2_0_p2[0]),
- .I1(probe_out_modified[2]),
- .I2(xsdb_addr_2_0_p2[2]),
- .I3(xsdb_addr_2_0_p2[1]),
- .I4(int_cnt_rst),
- .O(data_info_probe_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[3]_i_1
- (.I0(probe_out_modified[3]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[4]_i_1
- (.I0(probe_out_modified[4]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[5]_i_1
- (.I0(probe_out_modified[5]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[6]_i_1
- (.I0(probe_out_modified[6]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[7]_i_1
- (.I0(probe_out_modified[7]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[7]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[8]_i_1
- (.I0(probe_out_modified[8]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[8]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[9]_i_1
- (.I0(probe_out_modified[9]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[9]));
- FDRE \Bus_data_out_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(\Bus_data_out[0]_i_1_n_0 ),
- .Q(s_do_i[0]),
- .R(1'b0));
- FDRE \Bus_data_out_reg[10]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[10]),
- .Q(s_do_i[10]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[11]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[11]),
- .Q(s_do_i[11]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[12]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[12]),
- .Q(s_do_i[12]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[13]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[13]),
- .Q(s_do_i[13]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[14]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[14]),
- .Q(s_do_i[14]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[15]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[15]),
- .Q(s_do_i[15]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[1]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[1]),
- .Q(s_do_i[1]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[2]),
- .Q(s_do_i[2]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[3]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[3]),
- .Q(s_do_i[3]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[4]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[4]),
- .Q(s_do_i[4]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[5]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[5]),
- .Q(s_do_i[5]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[6]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[6]),
- .Q(s_do_i[6]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[7]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[7]),
- .Q(s_do_i[7]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[8]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[8]),
- .Q(s_do_i[8]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[9]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[9]),
- .Q(s_do_i[9]),
- .R(xsdb_addr_8_p2));
- LUT2 #(
- .INIT(4'h8))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_2
- (.I0(s_den_o),
- .I1(s_dwe_o),
- .O(xsdb_wr__0));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_4
- (.I0(s_daddr_o[14]),
- .I1(s_daddr_o[15]),
- .I2(s_daddr_o[12]),
- .I3(s_daddr_o[13]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_6
- (.I0(s_daddr_o[6]),
- .I1(s_daddr_o[7]),
- .I2(s_daddr_o[4]),
- .I3(s_daddr_o[5]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ));
- LUT3 #(
- .INIT(8'hB8))
- clear_int_i_1
- (.I0(Q[1]),
- .I1(wr_control_reg),
- .I2(SR),
- .O(clear_int_i_1_n_0));
- FDRE clear_int_reg
- (.C(out),
- .CE(1'b1),
- .D(clear_int_i_1_n_0),
- .Q(SR),
- .R(s_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT3 #(
- .INIT(8'hB8))
- committ_int_i_1
- (.I0(Q[0]),
- .I1(wr_control_reg),
- .I2(in0),
- .O(committ_int_i_1_n_0));
- FDRE committ_int_reg
- (.C(out),
- .CE(1'b1),
- .D(committ_int_i_1_n_0),
- .Q(in0),
- .R(s_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT3 #(
- .INIT(8'hB8))
- int_cnt_rst_i_1
- (.I0(Q[2]),
- .I1(wr_control_reg),
- .I2(int_cnt_rst),
- .O(int_cnt_rst_i_1_n_0));
- FDRE int_cnt_rst_reg
- (.C(out),
- .CE(1'b1),
- .D(int_cnt_rst_i_1_n_0),
- .Q(int_cnt_rst),
- .R(s_rst_o));
- FDRE \probe_out_modified_reg[0]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[0]),
- .Q(probe_out_modified[0]),
- .R(SR));
- FDRE \probe_out_modified_reg[10]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[10]),
- .Q(probe_out_modified[10]),
- .R(SR));
- FDRE \probe_out_modified_reg[11]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[11]),
- .Q(probe_out_modified[11]),
- .R(SR));
- FDRE \probe_out_modified_reg[12]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[12]),
- .Q(probe_out_modified[12]),
- .R(SR));
- FDRE \probe_out_modified_reg[13]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[13]),
- .Q(probe_out_modified[13]),
- .R(SR));
- FDRE \probe_out_modified_reg[14]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[14]),
- .Q(probe_out_modified[14]),
- .R(SR));
- FDRE \probe_out_modified_reg[15]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[15]),
- .Q(probe_out_modified[15]),
- .R(SR));
- FDRE \probe_out_modified_reg[1]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[1]),
- .Q(probe_out_modified[1]),
- .R(SR));
- FDRE \probe_out_modified_reg[2]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[2]),
- .Q(probe_out_modified[2]),
- .R(SR));
- FDRE \probe_out_modified_reg[3]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[3]),
- .Q(probe_out_modified[3]),
- .R(SR));
- FDRE \probe_out_modified_reg[4]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[4]),
- .Q(probe_out_modified[4]),
- .R(SR));
- FDRE \probe_out_modified_reg[5]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[5]),
- .Q(probe_out_modified[5]),
- .R(SR));
- FDRE \probe_out_modified_reg[6]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[6]),
- .Q(probe_out_modified[6]),
- .R(SR));
- FDRE \probe_out_modified_reg[7]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[7]),
- .Q(probe_out_modified[7]),
- .R(SR));
- FDRE \probe_out_modified_reg[8]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[8]),
- .Q(probe_out_modified[8]),
- .R(SR));
- FDRE \probe_out_modified_reg[9]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[9]),
- .Q(probe_out_modified[9]),
- .R(SR));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT2 #(
- .INIT(4'h2))
- rd_en_p1_i_1
- (.I0(s_den_o),
- .I1(s_dwe_o),
- .O(xsdb_rd));
- FDRE rd_en_p1_reg
- (.C(out),
- .CE(1'b1),
- .D(xsdb_rd),
- .Q(rd_en_p1),
- .R(s_rst_o));
- FDRE rd_en_p2_reg
- (.C(out),
- .CE(1'b1),
- .D(rd_en_p1),
- .Q(rd_en_p2),
- .R(s_rst_o));
- LUT6 #(
- .INIT(64'h0000000200000000))
- \wr_en[2]_i_1
- (.I0(xsdb_wr__0),
- .I1(\wr_en[4]_i_2_n_0 ),
- .I2(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ),
- .I3(\wr_en[2]_i_2_n_0 ),
- .I4(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ),
- .I5(s_daddr_o[1]),
- .O(\wr_en[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \wr_en[2]_i_2
- (.I0(s_daddr_o[2]),
- .I1(s_daddr_o[3]),
- .I2(s_daddr_o[0]),
- .I3(s_daddr_o[16]),
- .O(\wr_en[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000200000000))
- \wr_en[4]_i_1
- (.I0(xsdb_wr__0),
- .I1(\wr_en[4]_i_2_n_0 ),
- .I2(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ),
- .I3(\wr_en[4]_i_3_n_0 ),
- .I4(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ),
- .I5(s_daddr_o[2]),
- .O(\wr_en[4]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \wr_en[4]_i_2
- (.I0(s_daddr_o[10]),
- .I1(s_daddr_o[11]),
- .I2(s_daddr_o[8]),
- .I3(s_daddr_o[9]),
- .O(\wr_en[4]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \wr_en[4]_i_3
- (.I0(s_daddr_o[16]),
- .I1(s_daddr_o[3]),
- .I2(s_daddr_o[0]),
- .I3(s_daddr_o[1]),
- .O(\wr_en[4]_i_3_n_0 ));
- FDRE \wr_en_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(\wr_en[2]_i_1_n_0 ),
- .Q(wr_control_reg),
- .R(1'b0));
- FDRE \wr_en_reg[4]
- (.C(out),
- .CE(1'b1),
- .D(\wr_en[4]_i_1_n_0 ),
- .Q(wr_probe_out_modified),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p1_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[0]),
- .Q(xsdb_addr_2_0_p1[0]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p1_reg[1]
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[1]),
- .Q(xsdb_addr_2_0_p1[1]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p1_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[2]),
- .Q(xsdb_addr_2_0_p1[2]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p2_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_2_0_p1[0]),
- .Q(xsdb_addr_2_0_p2[0]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p2_reg[1]
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_2_0_p1[1]),
- .Q(xsdb_addr_2_0_p2[1]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p2_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_2_0_p1[2]),
- .Q(xsdb_addr_2_0_p2[2]),
- .R(1'b0));
- FDRE xsdb_addr_8_p1_reg
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[8]),
- .Q(xsdb_addr_8_p1),
- .R(1'b0));
- FDRE xsdb_addr_8_p2_reg
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_8_p1),
- .Q(xsdb_addr_8_p2),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT3 #(
- .INIT(8'hF8))
- xsdb_drdy_i_1
- (.I0(s_dwe_o),
- .I1(s_den_o),
- .I2(rd_en_p2),
- .O(xsdb_drdy_i_1_n_0));
- FDRE xsdb_drdy_reg
- (.C(out),
- .CE(1'b1),
- .D(xsdb_drdy_i_1_n_0),
- .Q(s_drdy_i),
- .R(s_rst_o));
-endmodule
-
-(* ORIG_REF_NAME = "vio_v3_0_19_probe_out_all" *)
-module scalp_zynqps_vio_0_0_vio_v3_0_19_probe_out_all
- (probe_out0,
- Probe_out_reg,
- SR,
- in0,
- clk,
- out,
- xsdb_wr__0,
- \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ,
- \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ,
- s_daddr_o,
- Q);
- output [0:0]probe_out0;
- output [0:0]Probe_out_reg;
- input [0:0]SR;
- input in0;
- input clk;
- input out;
- input xsdb_wr__0;
- input \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ;
- input \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ;
- input [8:0]s_daddr_o;
- input [0:0]Q;
-
- (* async_reg = "true" *) wire Committ_1;
- (* async_reg = "true" *) wire Committ_2;
- wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_1 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_5_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ;
- wire \G_PROBE_OUT[0].wr_probe_out_reg_n_0_[0] ;
- wire [0:0]Probe_out_reg;
- wire [0:0]Q;
- wire [0:0]SR;
- wire clk;
- wire in0;
- wire out;
- wire [0:0]probe_out0;
- wire [8:0]s_daddr_o;
- wire xsdb_wr__0;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- FDRE Committ_1_reg
- (.C(clk),
- .CE(1'b1),
- .D(in0),
- .Q(Committ_1),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- FDRE Committ_2_reg
- (.C(clk),
- .CE(1'b1),
- .D(Committ_1),
- .Q(Committ_2),
- .R(1'b0));
- scalp_zynqps_vio_0_0_vio_v3_0_19_probe_out_one \G_PROBE_OUT[0].PROBE_OUT0_INST
- (.Q(Q),
- .SR(SR),
- .clk(clk),
- .\data_int_reg[0]_0 (\G_PROBE_OUT[0].PROBE_OUT0_INST_n_1 ),
- .\data_int_reg[0]_1 (out),
- .\data_int_reg[0]_2 (\G_PROBE_OUT[0].wr_probe_out_reg_n_0_[0] ),
- .out(Committ_2),
- .probe_out0(probe_out0));
- LUT6 #(
- .INIT(64'h0000000200000000))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_1
- (.I0(xsdb_wr__0),
- .I1(\G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0 ),
- .I2(\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ),
- .I3(\G_PROBE_OUT[0].wr_probe_out[0]_i_5_n_0 ),
- .I4(\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ),
- .I5(s_daddr_o[4]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_3
- (.I0(s_daddr_o[6]),
- .I1(s_daddr_o[7]),
- .I2(s_daddr_o[8]),
- .I3(s_daddr_o[5]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_5
- (.I0(s_daddr_o[2]),
- .I1(s_daddr_o[3]),
- .I2(s_daddr_o[0]),
- .I3(s_daddr_o[1]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_5_n_0 ));
- FDRE \G_PROBE_OUT[0].wr_probe_out_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ),
- .Q(\G_PROBE_OUT[0].wr_probe_out_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \Probe_out_reg_int_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_1 ),
- .Q(Probe_out_reg),
- .R(1'b0));
-endmodule
-
-(* ORIG_REF_NAME = "vio_v3_0_19_probe_out_one" *)
-module scalp_zynqps_vio_0_0_vio_v3_0_19_probe_out_one
- (probe_out0,
- \data_int_reg[0]_0 ,
- SR,
- out,
- clk,
- \data_int_reg[0]_1 ,
- Q,
- \data_int_reg[0]_2 );
- output [0:0]probe_out0;
- output \data_int_reg[0]_0 ;
- input [0:0]SR;
- input out;
- input clk;
- input \data_int_reg[0]_1 ;
- input [0:0]Q;
- input \data_int_reg[0]_2 ;
-
- wire [0:0]Q;
- (* DIRECT_RESET *) wire [0:0]SR;
- wire clk;
- wire \data_int[0]_i_1_n_0 ;
- wire \data_int_reg[0]_0 ;
- wire \data_int_reg[0]_1 ;
- wire \data_int_reg[0]_2 ;
- wire out;
- (* DONT_TOUCH *) wire [0:0]probe_out0;
-
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- FDRE \Probe_out_reg[0]
- (.C(clk),
- .CE(out),
- .D(\data_int_reg[0]_0 ),
- .Q(probe_out0),
- .R(SR));
- LUT3 #(
- .INIT(8'hB8))
- \data_int[0]_i_1
- (.I0(Q),
- .I1(\data_int_reg[0]_2 ),
- .I2(\data_int_reg[0]_0 ),
- .O(\data_int[0]_i_1_n_0 ));
- FDRE \data_int_reg[0]
- (.C(\data_int_reg[0]_1 ),
- .CE(1'b1),
- .D(\data_int[0]_i_1_n_0 ),
- .Q(\data_int_reg[0]_0 ),
- .R(SR));
-endmodule
-
-(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *)
-(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *)
-(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
-(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "0" *) (* C_EN_SYNCHRONIZATION = "1" *)
-(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *)
-(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "0" *)
-(* C_NUM_PROBE_OUT = "1" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *)
-(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *)
-(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *)
-(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *)
-(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *)
-(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *)
-(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *)
-(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *)
-(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *)
-(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *)
-(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *)
-(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *)
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-(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *)
-(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *)
-(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *)
-(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *)
-(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *)
-(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *)
-(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *)
-(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *)
-(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *)
-(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *)
-(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *)
-(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *)
-(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *)
-(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *)
-(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *)
-(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *)
-(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *)
-(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *)
-(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *)
-(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *)
-(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *)
-(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *)
-(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *)
-(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *)
-(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *)
-(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *)
-(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *)
-(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *)
-(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *)
-(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *)
-(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *)
-(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *)
-(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *)
-(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *)
-(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *)
-(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *)
-(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *)
-(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *)
-(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *)
-(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *)
-(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *)
-(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *)
-(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *)
-(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *)
-(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *)
-(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *)
-(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *)
-(* C_XDEVICEFAMILY = "zynq" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
-(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
-(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *)
-(* LC_TOTAL_PROBE_OUT_WIDTH = "1" *) (* ORIG_REF_NAME = "vio_v3_0_19_vio" *) (* dont_touch = "true" *)
-module scalp_zynqps_vio_0_0_vio_v3_0_19_vio
- (clk,
- probe_in0,
- probe_in1,
- probe_in2,
- probe_in3,
- probe_in4,
- probe_in5,
- probe_in6,
- probe_in7,
- probe_in8,
- probe_in9,
- probe_in10,
- probe_in11,
- probe_in12,
- probe_in13,
- probe_in14,
- probe_in15,
- probe_in16,
- probe_in17,
- probe_in18,
- probe_in19,
- probe_in20,
- probe_in21,
- probe_in22,
- probe_in23,
- probe_in24,
- probe_in25,
- probe_in26,
- probe_in27,
- probe_in28,
- probe_in29,
- probe_in30,
- probe_in31,
- probe_in32,
- probe_in33,
- probe_in34,
- probe_in35,
- probe_in36,
- probe_in37,
- probe_in38,
- probe_in39,
- probe_in40,
- probe_in41,
- probe_in42,
- probe_in43,
- probe_in44,
- probe_in45,
- probe_in46,
- probe_in47,
- probe_in48,
- probe_in49,
- probe_in50,
- probe_in51,
- probe_in52,
- probe_in53,
- probe_in54,
- probe_in55,
- probe_in56,
- probe_in57,
- probe_in58,
- probe_in59,
- probe_in60,
- probe_in61,
- probe_in62,
- probe_in63,
- probe_in64,
- probe_in65,
- probe_in66,
- probe_in67,
- probe_in68,
- probe_in69,
- probe_in70,
- probe_in71,
- probe_in72,
- probe_in73,
- probe_in74,
- probe_in75,
- probe_in76,
- probe_in77,
- probe_in78,
- probe_in79,
- probe_in80,
- probe_in81,
- probe_in82,
- probe_in83,
- probe_in84,
- probe_in85,
- probe_in86,
- probe_in87,
- probe_in88,
- probe_in89,
- probe_in90,
- probe_in91,
- probe_in92,
- probe_in93,
- probe_in94,
- probe_in95,
- probe_in96,
- probe_in97,
- probe_in98,
- probe_in99,
- probe_in100,
- probe_in101,
- probe_in102,
- probe_in103,
- probe_in104,
- probe_in105,
- probe_in106,
- probe_in107,
- probe_in108,
- probe_in109,
- probe_in110,
- probe_in111,
- probe_in112,
- probe_in113,
- probe_in114,
- probe_in115,
- probe_in116,
- probe_in117,
- probe_in118,
- probe_in119,
- probe_in120,
- probe_in121,
- probe_in122,
- probe_in123,
- probe_in124,
- probe_in125,
- probe_in126,
- probe_in127,
- probe_in128,
- probe_in129,
- probe_in130,
- probe_in131,
- probe_in132,
- probe_in133,
- probe_in134,
- probe_in135,
- probe_in136,
- probe_in137,
- probe_in138,
- probe_in139,
- probe_in140,
- probe_in141,
- probe_in142,
- probe_in143,
- probe_in144,
- probe_in145,
- probe_in146,
- probe_in147,
- probe_in148,
- probe_in149,
- probe_in150,
- probe_in151,
- probe_in152,
- probe_in153,
- probe_in154,
- probe_in155,
- probe_in156,
- probe_in157,
- probe_in158,
- probe_in159,
- probe_in160,
- probe_in161,
- probe_in162,
- probe_in163,
- probe_in164,
- probe_in165,
- probe_in166,
- probe_in167,
- probe_in168,
- probe_in169,
- probe_in170,
- probe_in171,
- probe_in172,
- probe_in173,
- probe_in174,
- probe_in175,
- probe_in176,
- probe_in177,
- probe_in178,
- probe_in179,
- probe_in180,
- probe_in181,
- probe_in182,
- probe_in183,
- probe_in184,
- probe_in185,
- probe_in186,
- probe_in187,
- probe_in188,
- probe_in189,
- probe_in190,
- probe_in191,
- probe_in192,
- probe_in193,
- probe_in194,
- probe_in195,
- probe_in196,
- probe_in197,
- probe_in198,
- probe_in199,
- probe_in200,
- probe_in201,
- probe_in202,
- probe_in203,
- probe_in204,
- probe_in205,
- probe_in206,
- probe_in207,
- probe_in208,
- probe_in209,
- probe_in210,
- probe_in211,
- probe_in212,
- probe_in213,
- probe_in214,
- probe_in215,
- probe_in216,
- probe_in217,
- probe_in218,
- probe_in219,
- probe_in220,
- probe_in221,
- probe_in222,
- probe_in223,
- probe_in224,
- probe_in225,
- probe_in226,
- probe_in227,
- probe_in228,
- probe_in229,
- probe_in230,
- probe_in231,
- probe_in232,
- probe_in233,
- probe_in234,
- probe_in235,
- probe_in236,
- probe_in237,
- probe_in238,
- probe_in239,
- probe_in240,
- probe_in241,
- probe_in242,
- probe_in243,
- probe_in244,
- probe_in245,
- probe_in246,
- probe_in247,
- probe_in248,
- probe_in249,
- probe_in250,
- probe_in251,
- probe_in252,
- probe_in253,
- probe_in254,
- probe_in255,
- sl_iport0,
- sl_oport0,
- probe_out0,
- probe_out1,
- probe_out2,
- probe_out3,
- probe_out4,
- probe_out5,
- probe_out6,
- probe_out7,
- probe_out8,
- probe_out9,
- probe_out10,
- probe_out11,
- probe_out12,
- probe_out13,
- probe_out14,
- probe_out15,
- probe_out16,
- probe_out17,
- probe_out18,
- probe_out19,
- probe_out20,
- probe_out21,
- probe_out22,
- probe_out23,
- probe_out24,
- probe_out25,
- probe_out26,
- probe_out27,
- probe_out28,
- probe_out29,
- probe_out30,
- probe_out31,
- probe_out32,
- probe_out33,
- probe_out34,
- probe_out35,
- probe_out36,
- probe_out37,
- probe_out38,
- probe_out39,
- probe_out40,
- probe_out41,
- probe_out42,
- probe_out43,
- probe_out44,
- probe_out45,
- probe_out46,
- probe_out47,
- probe_out48,
- probe_out49,
- probe_out50,
- probe_out51,
- probe_out52,
- probe_out53,
- probe_out54,
- probe_out55,
- probe_out56,
- probe_out57,
- probe_out58,
- probe_out59,
- probe_out60,
- probe_out61,
- probe_out62,
- probe_out63,
- probe_out64,
- probe_out65,
- probe_out66,
- probe_out67,
- probe_out68,
- probe_out69,
- probe_out70,
- probe_out71,
- probe_out72,
- probe_out73,
- probe_out74,
- probe_out75,
- probe_out76,
- probe_out77,
- probe_out78,
- probe_out79,
- probe_out80,
- probe_out81,
- probe_out82,
- probe_out83,
- probe_out84,
- probe_out85,
- probe_out86,
- probe_out87,
- probe_out88,
- probe_out89,
- probe_out90,
- probe_out91,
- probe_out92,
- probe_out93,
- probe_out94,
- probe_out95,
- probe_out96,
- probe_out97,
- probe_out98,
- probe_out99,
- probe_out100,
- probe_out101,
- probe_out102,
- probe_out103,
- probe_out104,
- probe_out105,
- probe_out106,
- probe_out107,
- probe_out108,
- probe_out109,
- probe_out110,
- probe_out111,
- probe_out112,
- probe_out113,
- probe_out114,
- probe_out115,
- probe_out116,
- probe_out117,
- probe_out118,
- probe_out119,
- probe_out120,
- probe_out121,
- probe_out122,
- probe_out123,
- probe_out124,
- probe_out125,
- probe_out126,
- probe_out127,
- probe_out128,
- probe_out129,
- probe_out130,
- probe_out131,
- probe_out132,
- probe_out133,
- probe_out134,
- probe_out135,
- probe_out136,
- probe_out137,
- probe_out138,
- probe_out139,
- probe_out140,
- probe_out141,
- probe_out142,
- probe_out143,
- probe_out144,
- probe_out145,
- probe_out146,
- probe_out147,
- probe_out148,
- probe_out149,
- probe_out150,
- probe_out151,
- probe_out152,
- probe_out153,
- probe_out154,
- probe_out155,
- probe_out156,
- probe_out157,
- probe_out158,
- probe_out159,
- probe_out160,
- probe_out161,
- probe_out162,
- probe_out163,
- probe_out164,
- probe_out165,
- probe_out166,
- probe_out167,
- probe_out168,
- probe_out169,
- probe_out170,
- probe_out171,
- probe_out172,
- probe_out173,
- probe_out174,
- probe_out175,
- probe_out176,
- probe_out177,
- probe_out178,
- probe_out179,
- probe_out180,
- probe_out181,
- probe_out182,
- probe_out183,
- probe_out184,
- probe_out185,
- probe_out186,
- probe_out187,
- probe_out188,
- probe_out189,
- probe_out190,
- probe_out191,
- probe_out192,
- probe_out193,
- probe_out194,
- probe_out195,
- probe_out196,
- probe_out197,
- probe_out198,
- probe_out199,
- probe_out200,
- probe_out201,
- probe_out202,
- probe_out203,
- probe_out204,
- probe_out205,
- probe_out206,
- probe_out207,
- probe_out208,
- probe_out209,
- probe_out210,
- probe_out211,
- probe_out212,
- probe_out213,
- probe_out214,
- probe_out215,
- probe_out216,
- probe_out217,
- probe_out218,
- probe_out219,
- probe_out220,
- probe_out221,
- probe_out222,
- probe_out223,
- probe_out224,
- probe_out225,
- probe_out226,
- probe_out227,
- probe_out228,
- probe_out229,
- probe_out230,
- probe_out231,
- probe_out232,
- probe_out233,
- probe_out234,
- probe_out235,
- probe_out236,
- probe_out237,
- probe_out238,
- probe_out239,
- probe_out240,
- probe_out241,
- probe_out242,
- probe_out243,
- probe_out244,
- probe_out245,
- probe_out246,
- probe_out247,
- probe_out248,
- probe_out249,
- probe_out250,
- probe_out251,
- probe_out252,
- probe_out253,
- probe_out254,
- probe_out255);
- input clk;
- input [0:0]probe_in0;
- input [0:0]probe_in1;
- input [0:0]probe_in2;
- input [0:0]probe_in3;
- input [0:0]probe_in4;
- input [0:0]probe_in5;
- input [0:0]probe_in6;
- input [0:0]probe_in7;
- input [0:0]probe_in8;
- input [0:0]probe_in9;
- input [0:0]probe_in10;
- input [0:0]probe_in11;
- input [0:0]probe_in12;
- input [0:0]probe_in13;
- input [0:0]probe_in14;
- input [0:0]probe_in15;
- input [0:0]probe_in16;
- input [0:0]probe_in17;
- input [0:0]probe_in18;
- input [0:0]probe_in19;
- input [0:0]probe_in20;
- input [0:0]probe_in21;
- input [0:0]probe_in22;
- input [0:0]probe_in23;
- input [0:0]probe_in24;
- input [0:0]probe_in25;
- input [0:0]probe_in26;
- input [0:0]probe_in27;
- input [0:0]probe_in28;
- input [0:0]probe_in29;
- input [0:0]probe_in30;
- input [0:0]probe_in31;
- input [0:0]probe_in32;
- input [0:0]probe_in33;
- input [0:0]probe_in34;
- input [0:0]probe_in35;
- input [0:0]probe_in36;
- input [0:0]probe_in37;
- input [0:0]probe_in38;
- input [0:0]probe_in39;
- input [0:0]probe_in40;
- input [0:0]probe_in41;
- input [0:0]probe_in42;
- input [0:0]probe_in43;
- input [0:0]probe_in44;
- input [0:0]probe_in45;
- input [0:0]probe_in46;
- input [0:0]probe_in47;
- input [0:0]probe_in48;
- input [0:0]probe_in49;
- input [0:0]probe_in50;
- input [0:0]probe_in51;
- input [0:0]probe_in52;
- input [0:0]probe_in53;
- input [0:0]probe_in54;
- input [0:0]probe_in55;
- input [0:0]probe_in56;
- input [0:0]probe_in57;
- input [0:0]probe_in58;
- input [0:0]probe_in59;
- input [0:0]probe_in60;
- input [0:0]probe_in61;
- input [0:0]probe_in62;
- input [0:0]probe_in63;
- input [0:0]probe_in64;
- input [0:0]probe_in65;
- input [0:0]probe_in66;
- input [0:0]probe_in67;
- input [0:0]probe_in68;
- input [0:0]probe_in69;
- input [0:0]probe_in70;
- input [0:0]probe_in71;
- input [0:0]probe_in72;
- input [0:0]probe_in73;
- input [0:0]probe_in74;
- input [0:0]probe_in75;
- input [0:0]probe_in76;
- input [0:0]probe_in77;
- input [0:0]probe_in78;
- input [0:0]probe_in79;
- input [0:0]probe_in80;
- input [0:0]probe_in81;
- input [0:0]probe_in82;
- input [0:0]probe_in83;
- input [0:0]probe_in84;
- input [0:0]probe_in85;
- input [0:0]probe_in86;
- input [0:0]probe_in87;
- input [0:0]probe_in88;
- input [0:0]probe_in89;
- input [0:0]probe_in90;
- input [0:0]probe_in91;
- input [0:0]probe_in92;
- input [0:0]probe_in93;
- input [0:0]probe_in94;
- input [0:0]probe_in95;
- input [0:0]probe_in96;
- input [0:0]probe_in97;
- input [0:0]probe_in98;
- input [0:0]probe_in99;
- input [0:0]probe_in100;
- input [0:0]probe_in101;
- input [0:0]probe_in102;
- input [0:0]probe_in103;
- input [0:0]probe_in104;
- input [0:0]probe_in105;
- input [0:0]probe_in106;
- input [0:0]probe_in107;
- input [0:0]probe_in108;
- input [0:0]probe_in109;
- input [0:0]probe_in110;
- input [0:0]probe_in111;
- input [0:0]probe_in112;
- input [0:0]probe_in113;
- input [0:0]probe_in114;
- input [0:0]probe_in115;
- input [0:0]probe_in116;
- input [0:0]probe_in117;
- input [0:0]probe_in118;
- input [0:0]probe_in119;
- input [0:0]probe_in120;
- input [0:0]probe_in121;
- input [0:0]probe_in122;
- input [0:0]probe_in123;
- input [0:0]probe_in124;
- input [0:0]probe_in125;
- input [0:0]probe_in126;
- input [0:0]probe_in127;
- input [0:0]probe_in128;
- input [0:0]probe_in129;
- input [0:0]probe_in130;
- input [0:0]probe_in131;
- input [0:0]probe_in132;
- input [0:0]probe_in133;
- input [0:0]probe_in134;
- input [0:0]probe_in135;
- input [0:0]probe_in136;
- input [0:0]probe_in137;
- input [0:0]probe_in138;
- input [0:0]probe_in139;
- input [0:0]probe_in140;
- input [0:0]probe_in141;
- input [0:0]probe_in142;
- input [0:0]probe_in143;
- input [0:0]probe_in144;
- input [0:0]probe_in145;
- input [0:0]probe_in146;
- input [0:0]probe_in147;
- input [0:0]probe_in148;
- input [0:0]probe_in149;
- input [0:0]probe_in150;
- input [0:0]probe_in151;
- input [0:0]probe_in152;
- input [0:0]probe_in153;
- input [0:0]probe_in154;
- input [0:0]probe_in155;
- input [0:0]probe_in156;
- input [0:0]probe_in157;
- input [0:0]probe_in158;
- input [0:0]probe_in159;
- input [0:0]probe_in160;
- input [0:0]probe_in161;
- input [0:0]probe_in162;
- input [0:0]probe_in163;
- input [0:0]probe_in164;
- input [0:0]probe_in165;
- input [0:0]probe_in166;
- input [0:0]probe_in167;
- input [0:0]probe_in168;
- input [0:0]probe_in169;
- input [0:0]probe_in170;
- input [0:0]probe_in171;
- input [0:0]probe_in172;
- input [0:0]probe_in173;
- input [0:0]probe_in174;
- input [0:0]probe_in175;
- input [0:0]probe_in176;
- input [0:0]probe_in177;
- input [0:0]probe_in178;
- input [0:0]probe_in179;
- input [0:0]probe_in180;
- input [0:0]probe_in181;
- input [0:0]probe_in182;
- input [0:0]probe_in183;
- input [0:0]probe_in184;
- input [0:0]probe_in185;
- input [0:0]probe_in186;
- input [0:0]probe_in187;
- input [0:0]probe_in188;
- input [0:0]probe_in189;
- input [0:0]probe_in190;
- input [0:0]probe_in191;
- input [0:0]probe_in192;
- input [0:0]probe_in193;
- input [0:0]probe_in194;
- input [0:0]probe_in195;
- input [0:0]probe_in196;
- input [0:0]probe_in197;
- input [0:0]probe_in198;
- input [0:0]probe_in199;
- input [0:0]probe_in200;
- input [0:0]probe_in201;
- input [0:0]probe_in202;
- input [0:0]probe_in203;
- input [0:0]probe_in204;
- input [0:0]probe_in205;
- input [0:0]probe_in206;
- input [0:0]probe_in207;
- input [0:0]probe_in208;
- input [0:0]probe_in209;
- input [0:0]probe_in210;
- input [0:0]probe_in211;
- input [0:0]probe_in212;
- input [0:0]probe_in213;
- input [0:0]probe_in214;
- input [0:0]probe_in215;
- input [0:0]probe_in216;
- input [0:0]probe_in217;
- input [0:0]probe_in218;
- input [0:0]probe_in219;
- input [0:0]probe_in220;
- input [0:0]probe_in221;
- input [0:0]probe_in222;
- input [0:0]probe_in223;
- input [0:0]probe_in224;
- input [0:0]probe_in225;
- input [0:0]probe_in226;
- input [0:0]probe_in227;
- input [0:0]probe_in228;
- input [0:0]probe_in229;
- input [0:0]probe_in230;
- input [0:0]probe_in231;
- input [0:0]probe_in232;
- input [0:0]probe_in233;
- input [0:0]probe_in234;
- input [0:0]probe_in235;
- input [0:0]probe_in236;
- input [0:0]probe_in237;
- input [0:0]probe_in238;
- input [0:0]probe_in239;
- input [0:0]probe_in240;
- input [0:0]probe_in241;
- input [0:0]probe_in242;
- input [0:0]probe_in243;
- input [0:0]probe_in244;
- input [0:0]probe_in245;
- input [0:0]probe_in246;
- input [0:0]probe_in247;
- input [0:0]probe_in248;
- input [0:0]probe_in249;
- input [0:0]probe_in250;
- input [0:0]probe_in251;
- input [0:0]probe_in252;
- input [0:0]probe_in253;
- input [0:0]probe_in254;
- input [0:0]probe_in255;
- (* dont_touch = "true" *) input [36:0]sl_iport0;
- (* dont_touch = "true" *) output [16:0]sl_oport0;
- output [0:0]probe_out0;
- output [0:0]probe_out1;
- output [0:0]probe_out2;
- output [0:0]probe_out3;
- output [0:0]probe_out4;
- output [0:0]probe_out5;
- output [0:0]probe_out6;
- output [0:0]probe_out7;
- output [0:0]probe_out8;
- output [0:0]probe_out9;
- output [0:0]probe_out10;
- output [0:0]probe_out11;
- output [0:0]probe_out12;
- output [0:0]probe_out13;
- output [0:0]probe_out14;
- output [0:0]probe_out15;
- output [0:0]probe_out16;
- output [0:0]probe_out17;
- output [0:0]probe_out18;
- output [0:0]probe_out19;
- output [0:0]probe_out20;
- output [0:0]probe_out21;
- output [0:0]probe_out22;
- output [0:0]probe_out23;
- output [0:0]probe_out24;
- output [0:0]probe_out25;
- output [0:0]probe_out26;
- output [0:0]probe_out27;
- output [0:0]probe_out28;
- output [0:0]probe_out29;
- output [0:0]probe_out30;
- output [0:0]probe_out31;
- output [0:0]probe_out32;
- output [0:0]probe_out33;
- output [0:0]probe_out34;
- output [0:0]probe_out35;
- output [0:0]probe_out36;
- output [0:0]probe_out37;
- output [0:0]probe_out38;
- output [0:0]probe_out39;
- output [0:0]probe_out40;
- output [0:0]probe_out41;
- output [0:0]probe_out42;
- output [0:0]probe_out43;
- output [0:0]probe_out44;
- output [0:0]probe_out45;
- output [0:0]probe_out46;
- output [0:0]probe_out47;
- output [0:0]probe_out48;
- output [0:0]probe_out49;
- output [0:0]probe_out50;
- output [0:0]probe_out51;
- output [0:0]probe_out52;
- output [0:0]probe_out53;
- output [0:0]probe_out54;
- output [0:0]probe_out55;
- output [0:0]probe_out56;
- output [0:0]probe_out57;
- output [0:0]probe_out58;
- output [0:0]probe_out59;
- output [0:0]probe_out60;
- output [0:0]probe_out61;
- output [0:0]probe_out62;
- output [0:0]probe_out63;
- output [0:0]probe_out64;
- output [0:0]probe_out65;
- output [0:0]probe_out66;
- output [0:0]probe_out67;
- output [0:0]probe_out68;
- output [0:0]probe_out69;
- output [0:0]probe_out70;
- output [0:0]probe_out71;
- output [0:0]probe_out72;
- output [0:0]probe_out73;
- output [0:0]probe_out74;
- output [0:0]probe_out75;
- output [0:0]probe_out76;
- output [0:0]probe_out77;
- output [0:0]probe_out78;
- output [0:0]probe_out79;
- output [0:0]probe_out80;
- output [0:0]probe_out81;
- output [0:0]probe_out82;
- output [0:0]probe_out83;
- output [0:0]probe_out84;
- output [0:0]probe_out85;
- output [0:0]probe_out86;
- output [0:0]probe_out87;
- output [0:0]probe_out88;
- output [0:0]probe_out89;
- output [0:0]probe_out90;
- output [0:0]probe_out91;
- output [0:0]probe_out92;
- output [0:0]probe_out93;
- output [0:0]probe_out94;
- output [0:0]probe_out95;
- output [0:0]probe_out96;
- output [0:0]probe_out97;
- output [0:0]probe_out98;
- output [0:0]probe_out99;
- output [0:0]probe_out100;
- output [0:0]probe_out101;
- output [0:0]probe_out102;
- output [0:0]probe_out103;
- output [0:0]probe_out104;
- output [0:0]probe_out105;
- output [0:0]probe_out106;
- output [0:0]probe_out107;
- output [0:0]probe_out108;
- output [0:0]probe_out109;
- output [0:0]probe_out110;
- output [0:0]probe_out111;
- output [0:0]probe_out112;
- output [0:0]probe_out113;
- output [0:0]probe_out114;
- output [0:0]probe_out115;
- output [0:0]probe_out116;
- output [0:0]probe_out117;
- output [0:0]probe_out118;
- output [0:0]probe_out119;
- output [0:0]probe_out120;
- output [0:0]probe_out121;
- output [0:0]probe_out122;
- output [0:0]probe_out123;
- output [0:0]probe_out124;
- output [0:0]probe_out125;
- output [0:0]probe_out126;
- output [0:0]probe_out127;
- output [0:0]probe_out128;
- output [0:0]probe_out129;
- output [0:0]probe_out130;
- output [0:0]probe_out131;
- output [0:0]probe_out132;
- output [0:0]probe_out133;
- output [0:0]probe_out134;
- output [0:0]probe_out135;
- output [0:0]probe_out136;
- output [0:0]probe_out137;
- output [0:0]probe_out138;
- output [0:0]probe_out139;
- output [0:0]probe_out140;
- output [0:0]probe_out141;
- output [0:0]probe_out142;
- output [0:0]probe_out143;
- output [0:0]probe_out144;
- output [0:0]probe_out145;
- output [0:0]probe_out146;
- output [0:0]probe_out147;
- output [0:0]probe_out148;
- output [0:0]probe_out149;
- output [0:0]probe_out150;
- output [0:0]probe_out151;
- output [0:0]probe_out152;
- output [0:0]probe_out153;
- output [0:0]probe_out154;
- output [0:0]probe_out155;
- output [0:0]probe_out156;
- output [0:0]probe_out157;
- output [0:0]probe_out158;
- output [0:0]probe_out159;
- output [0:0]probe_out160;
- output [0:0]probe_out161;
- output [0:0]probe_out162;
- output [0:0]probe_out163;
- output [0:0]probe_out164;
- output [0:0]probe_out165;
- output [0:0]probe_out166;
- output [0:0]probe_out167;
- output [0:0]probe_out168;
- output [0:0]probe_out169;
- output [0:0]probe_out170;
- output [0:0]probe_out171;
- output [0:0]probe_out172;
- output [0:0]probe_out173;
- output [0:0]probe_out174;
- output [0:0]probe_out175;
- output [0:0]probe_out176;
- output [0:0]probe_out177;
- output [0:0]probe_out178;
- output [0:0]probe_out179;
- output [0:0]probe_out180;
- output [0:0]probe_out181;
- output [0:0]probe_out182;
- output [0:0]probe_out183;
- output [0:0]probe_out184;
- output [0:0]probe_out185;
- output [0:0]probe_out186;
- output [0:0]probe_out187;
- output [0:0]probe_out188;
- output [0:0]probe_out189;
- output [0:0]probe_out190;
- output [0:0]probe_out191;
- output [0:0]probe_out192;
- output [0:0]probe_out193;
- output [0:0]probe_out194;
- output [0:0]probe_out195;
- output [0:0]probe_out196;
- output [0:0]probe_out197;
- output [0:0]probe_out198;
- output [0:0]probe_out199;
- output [0:0]probe_out200;
- output [0:0]probe_out201;
- output [0:0]probe_out202;
- output [0:0]probe_out203;
- output [0:0]probe_out204;
- output [0:0]probe_out205;
- output [0:0]probe_out206;
- output [0:0]probe_out207;
- output [0:0]probe_out208;
- output [0:0]probe_out209;
- output [0:0]probe_out210;
- output [0:0]probe_out211;
- output [0:0]probe_out212;
- output [0:0]probe_out213;
- output [0:0]probe_out214;
- output [0:0]probe_out215;
- output [0:0]probe_out216;
- output [0:0]probe_out217;
- output [0:0]probe_out218;
- output [0:0]probe_out219;
- output [0:0]probe_out220;
- output [0:0]probe_out221;
- output [0:0]probe_out222;
- output [0:0]probe_out223;
- output [0:0]probe_out224;
- output [0:0]probe_out225;
- output [0:0]probe_out226;
- output [0:0]probe_out227;
- output [0:0]probe_out228;
- output [0:0]probe_out229;
- output [0:0]probe_out230;
- output [0:0]probe_out231;
- output [0:0]probe_out232;
- output [0:0]probe_out233;
- output [0:0]probe_out234;
- output [0:0]probe_out235;
- output [0:0]probe_out236;
- output [0:0]probe_out237;
- output [0:0]probe_out238;
- output [0:0]probe_out239;
- output [0:0]probe_out240;
- output [0:0]probe_out241;
- output [0:0]probe_out242;
- output [0:0]probe_out243;
- output [0:0]probe_out244;
- output [0:0]probe_out245;
- output [0:0]probe_out246;
- output [0:0]probe_out247;
- output [0:0]probe_out248;
- output [0:0]probe_out249;
- output [0:0]probe_out250;
- output [0:0]probe_out251;
- output [0:0]probe_out252;
- output [0:0]probe_out253;
- output [0:0]probe_out254;
- output [0:0]probe_out255;
-
- wire \<const0> ;
- wire DECODER_INST_n_4;
- wire DECODER_INST_n_5;
- wire [0:0]Probe_out_reg;
- wire [16:0]bus_addr;
- (* DONT_TOUCH *) wire bus_clk;
- wire \bus_data_int_reg_n_0_[10] ;
- wire \bus_data_int_reg_n_0_[11] ;
- wire \bus_data_int_reg_n_0_[12] ;
- wire \bus_data_int_reg_n_0_[13] ;
- wire \bus_data_int_reg_n_0_[14] ;
- wire \bus_data_int_reg_n_0_[15] ;
- wire \bus_data_int_reg_n_0_[2] ;
- wire \bus_data_int_reg_n_0_[3] ;
- wire \bus_data_int_reg_n_0_[4] ;
- wire \bus_data_int_reg_n_0_[5] ;
- wire \bus_data_int_reg_n_0_[6] ;
- wire \bus_data_int_reg_n_0_[7] ;
- wire \bus_data_int_reg_n_0_[8] ;
- wire \bus_data_int_reg_n_0_[9] ;
- wire bus_den;
- wire [15:0]bus_di;
- wire [15:0]bus_do;
- wire bus_drdy;
- wire bus_dwe;
- wire bus_rst;
- wire clear;
- wire clk;
- wire committ;
- wire p_0_in;
- wire p_2_in;
- wire [0:0]probe_out0;
- (* DONT_TOUCH *) wire [36:0]sl_iport0;
- (* DONT_TOUCH *) wire [16:0]sl_oport0;
- wire xsdb_wr__0;
-
- assign probe_out1[0] = \<const0> ;
- assign probe_out10[0] = \<const0> ;
- assign probe_out100[0] = \<const0> ;
- assign probe_out101[0] = \<const0> ;
- assign probe_out102[0] = \<const0> ;
- assign probe_out103[0] = \<const0> ;
- assign probe_out104[0] = \<const0> ;
- assign probe_out105[0] = \<const0> ;
- assign probe_out106[0] = \<const0> ;
- assign probe_out107[0] = \<const0> ;
- assign probe_out108[0] = \<const0> ;
- assign probe_out109[0] = \<const0> ;
- assign probe_out11[0] = \<const0> ;
- assign probe_out110[0] = \<const0> ;
- assign probe_out111[0] = \<const0> ;
- assign probe_out112[0] = \<const0> ;
- assign probe_out113[0] = \<const0> ;
- assign probe_out114[0] = \<const0> ;
- assign probe_out115[0] = \<const0> ;
- assign probe_out116[0] = \<const0> ;
- assign probe_out117[0] = \<const0> ;
- assign probe_out118[0] = \<const0> ;
- assign probe_out119[0] = \<const0> ;
- assign probe_out12[0] = \<const0> ;
- assign probe_out120[0] = \<const0> ;
- assign probe_out121[0] = \<const0> ;
- assign probe_out122[0] = \<const0> ;
- assign probe_out123[0] = \<const0> ;
- assign probe_out124[0] = \<const0> ;
- assign probe_out125[0] = \<const0> ;
- assign probe_out126[0] = \<const0> ;
- assign probe_out127[0] = \<const0> ;
- assign probe_out128[0] = \<const0> ;
- assign probe_out129[0] = \<const0> ;
- assign probe_out13[0] = \<const0> ;
- assign probe_out130[0] = \<const0> ;
- assign probe_out131[0] = \<const0> ;
- assign probe_out132[0] = \<const0> ;
- assign probe_out133[0] = \<const0> ;
- assign probe_out134[0] = \<const0> ;
- assign probe_out135[0] = \<const0> ;
- assign probe_out136[0] = \<const0> ;
- assign probe_out137[0] = \<const0> ;
- assign probe_out138[0] = \<const0> ;
- assign probe_out139[0] = \<const0> ;
- assign probe_out14[0] = \<const0> ;
- assign probe_out140[0] = \<const0> ;
- assign probe_out141[0] = \<const0> ;
- assign probe_out142[0] = \<const0> ;
- assign probe_out143[0] = \<const0> ;
- assign probe_out144[0] = \<const0> ;
- assign probe_out145[0] = \<const0> ;
- assign probe_out146[0] = \<const0> ;
- assign probe_out147[0] = \<const0> ;
- assign probe_out148[0] = \<const0> ;
- assign probe_out149[0] = \<const0> ;
- assign probe_out15[0] = \<const0> ;
- assign probe_out150[0] = \<const0> ;
- assign probe_out151[0] = \<const0> ;
- assign probe_out152[0] = \<const0> ;
- assign probe_out153[0] = \<const0> ;
- assign probe_out154[0] = \<const0> ;
- assign probe_out155[0] = \<const0> ;
- assign probe_out156[0] = \<const0> ;
- assign probe_out157[0] = \<const0> ;
- assign probe_out158[0] = \<const0> ;
- assign probe_out159[0] = \<const0> ;
- assign probe_out16[0] = \<const0> ;
- assign probe_out160[0] = \<const0> ;
- assign probe_out161[0] = \<const0> ;
- assign probe_out162[0] = \<const0> ;
- assign probe_out163[0] = \<const0> ;
- assign probe_out164[0] = \<const0> ;
- assign probe_out165[0] = \<const0> ;
- assign probe_out166[0] = \<const0> ;
- assign probe_out167[0] = \<const0> ;
- assign probe_out168[0] = \<const0> ;
- assign probe_out169[0] = \<const0> ;
- assign probe_out17[0] = \<const0> ;
- assign probe_out170[0] = \<const0> ;
- assign probe_out171[0] = \<const0> ;
- assign probe_out172[0] = \<const0> ;
- assign probe_out173[0] = \<const0> ;
- assign probe_out174[0] = \<const0> ;
- assign probe_out175[0] = \<const0> ;
- assign probe_out176[0] = \<const0> ;
- assign probe_out177[0] = \<const0> ;
- assign probe_out178[0] = \<const0> ;
- assign probe_out179[0] = \<const0> ;
- assign probe_out18[0] = \<const0> ;
- assign probe_out180[0] = \<const0> ;
- assign probe_out181[0] = \<const0> ;
- assign probe_out182[0] = \<const0> ;
- assign probe_out183[0] = \<const0> ;
- assign probe_out184[0] = \<const0> ;
- assign probe_out185[0] = \<const0> ;
- assign probe_out186[0] = \<const0> ;
- assign probe_out187[0] = \<const0> ;
- assign probe_out188[0] = \<const0> ;
- assign probe_out189[0] = \<const0> ;
- assign probe_out19[0] = \<const0> ;
- assign probe_out190[0] = \<const0> ;
- assign probe_out191[0] = \<const0> ;
- assign probe_out192[0] = \<const0> ;
- assign probe_out193[0] = \<const0> ;
- assign probe_out194[0] = \<const0> ;
- assign probe_out195[0] = \<const0> ;
- assign probe_out196[0] = \<const0> ;
- assign probe_out197[0] = \<const0> ;
- assign probe_out198[0] = \<const0> ;
- assign probe_out199[0] = \<const0> ;
- assign probe_out2[0] = \<const0> ;
- assign probe_out20[0] = \<const0> ;
- assign probe_out200[0] = \<const0> ;
- assign probe_out201[0] = \<const0> ;
- assign probe_out202[0] = \<const0> ;
- assign probe_out203[0] = \<const0> ;
- assign probe_out204[0] = \<const0> ;
- assign probe_out205[0] = \<const0> ;
- assign probe_out206[0] = \<const0> ;
- assign probe_out207[0] = \<const0> ;
- assign probe_out208[0] = \<const0> ;
- assign probe_out209[0] = \<const0> ;
- assign probe_out21[0] = \<const0> ;
- assign probe_out210[0] = \<const0> ;
- assign probe_out211[0] = \<const0> ;
- assign probe_out212[0] = \<const0> ;
- assign probe_out213[0] = \<const0> ;
- assign probe_out214[0] = \<const0> ;
- assign probe_out215[0] = \<const0> ;
- assign probe_out216[0] = \<const0> ;
- assign probe_out217[0] = \<const0> ;
- assign probe_out218[0] = \<const0> ;
- assign probe_out219[0] = \<const0> ;
- assign probe_out22[0] = \<const0> ;
- assign probe_out220[0] = \<const0> ;
- assign probe_out221[0] = \<const0> ;
- assign probe_out222[0] = \<const0> ;
- assign probe_out223[0] = \<const0> ;
- assign probe_out224[0] = \<const0> ;
- assign probe_out225[0] = \<const0> ;
- assign probe_out226[0] = \<const0> ;
- assign probe_out227[0] = \<const0> ;
- assign probe_out228[0] = \<const0> ;
- assign probe_out229[0] = \<const0> ;
- assign probe_out23[0] = \<const0> ;
- assign probe_out230[0] = \<const0> ;
- assign probe_out231[0] = \<const0> ;
- assign probe_out232[0] = \<const0> ;
- assign probe_out233[0] = \<const0> ;
- assign probe_out234[0] = \<const0> ;
- assign probe_out235[0] = \<const0> ;
- assign probe_out236[0] = \<const0> ;
- assign probe_out237[0] = \<const0> ;
- assign probe_out238[0] = \<const0> ;
- assign probe_out239[0] = \<const0> ;
- assign probe_out24[0] = \<const0> ;
- assign probe_out240[0] = \<const0> ;
- assign probe_out241[0] = \<const0> ;
- assign probe_out242[0] = \<const0> ;
- assign probe_out243[0] = \<const0> ;
- assign probe_out244[0] = \<const0> ;
- assign probe_out245[0] = \<const0> ;
- assign probe_out246[0] = \<const0> ;
- assign probe_out247[0] = \<const0> ;
- assign probe_out248[0] = \<const0> ;
- assign probe_out249[0] = \<const0> ;
- assign probe_out25[0] = \<const0> ;
- assign probe_out250[0] = \<const0> ;
- assign probe_out251[0] = \<const0> ;
- assign probe_out252[0] = \<const0> ;
- assign probe_out253[0] = \<const0> ;
- assign probe_out254[0] = \<const0> ;
- assign probe_out255[0] = \<const0> ;
- assign probe_out26[0] = \<const0> ;
- assign probe_out27[0] = \<const0> ;
- assign probe_out28[0] = \<const0> ;
- assign probe_out29[0] = \<const0> ;
- assign probe_out3[0] = \<const0> ;
- assign probe_out30[0] = \<const0> ;
- assign probe_out31[0] = \<const0> ;
- assign probe_out32[0] = \<const0> ;
- assign probe_out33[0] = \<const0> ;
- assign probe_out34[0] = \<const0> ;
- assign probe_out35[0] = \<const0> ;
- assign probe_out36[0] = \<const0> ;
- assign probe_out37[0] = \<const0> ;
- assign probe_out38[0] = \<const0> ;
- assign probe_out39[0] = \<const0> ;
- assign probe_out4[0] = \<const0> ;
- assign probe_out40[0] = \<const0> ;
- assign probe_out41[0] = \<const0> ;
- assign probe_out42[0] = \<const0> ;
- assign probe_out43[0] = \<const0> ;
- assign probe_out44[0] = \<const0> ;
- assign probe_out45[0] = \<const0> ;
- assign probe_out46[0] = \<const0> ;
- assign probe_out47[0] = \<const0> ;
- assign probe_out48[0] = \<const0> ;
- assign probe_out49[0] = \<const0> ;
- assign probe_out5[0] = \<const0> ;
- assign probe_out50[0] = \<const0> ;
- assign probe_out51[0] = \<const0> ;
- assign probe_out52[0] = \<const0> ;
- assign probe_out53[0] = \<const0> ;
- assign probe_out54[0] = \<const0> ;
- assign probe_out55[0] = \<const0> ;
- assign probe_out56[0] = \<const0> ;
- assign probe_out57[0] = \<const0> ;
- assign probe_out58[0] = \<const0> ;
- assign probe_out59[0] = \<const0> ;
- assign probe_out6[0] = \<const0> ;
- assign probe_out60[0] = \<const0> ;
- assign probe_out61[0] = \<const0> ;
- assign probe_out62[0] = \<const0> ;
- assign probe_out63[0] = \<const0> ;
- assign probe_out64[0] = \<const0> ;
- assign probe_out65[0] = \<const0> ;
- assign probe_out66[0] = \<const0> ;
- assign probe_out67[0] = \<const0> ;
- assign probe_out68[0] = \<const0> ;
- assign probe_out69[0] = \<const0> ;
- assign probe_out7[0] = \<const0> ;
- assign probe_out70[0] = \<const0> ;
- assign probe_out71[0] = \<const0> ;
- assign probe_out72[0] = \<const0> ;
- assign probe_out73[0] = \<const0> ;
- assign probe_out74[0] = \<const0> ;
- assign probe_out75[0] = \<const0> ;
- assign probe_out76[0] = \<const0> ;
- assign probe_out77[0] = \<const0> ;
- assign probe_out78[0] = \<const0> ;
- assign probe_out79[0] = \<const0> ;
- assign probe_out8[0] = \<const0> ;
- assign probe_out80[0] = \<const0> ;
- assign probe_out81[0] = \<const0> ;
- assign probe_out82[0] = \<const0> ;
- assign probe_out83[0] = \<const0> ;
- assign probe_out84[0] = \<const0> ;
- assign probe_out85[0] = \<const0> ;
- assign probe_out86[0] = \<const0> ;
- assign probe_out87[0] = \<const0> ;
- assign probe_out88[0] = \<const0> ;
- assign probe_out89[0] = \<const0> ;
- assign probe_out9[0] = \<const0> ;
- assign probe_out90[0] = \<const0> ;
- assign probe_out91[0] = \<const0> ;
- assign probe_out92[0] = \<const0> ;
- assign probe_out93[0] = \<const0> ;
- assign probe_out94[0] = \<const0> ;
- assign probe_out95[0] = \<const0> ;
- assign probe_out96[0] = \<const0> ;
- assign probe_out97[0] = \<const0> ;
- assign probe_out98[0] = \<const0> ;
- assign probe_out99[0] = \<const0> ;
- scalp_zynqps_vio_0_0_vio_v3_0_19_decoder DECODER_INST
- (.\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 (DECODER_INST_n_4),
- .\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 (DECODER_INST_n_5),
- .Probe_out_reg(Probe_out_reg),
- .Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,p_2_in}),
- .SR(clear),
- .in0(committ),
- .out(bus_clk),
- .s_daddr_o(bus_addr),
- .s_den_o(bus_den),
- .s_do_i(bus_do),
- .s_drdy_i(bus_drdy),
- .s_dwe_o(bus_dwe),
- .s_rst_o(bus_rst),
- .xsdb_wr__0(xsdb_wr__0));
- GND GND
- (.G(\<const0> ));
- scalp_zynqps_vio_0_0_vio_v3_0_19_probe_out_all PROBE_OUT_ALL_INST
- (.\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 (DECODER_INST_n_4),
- .\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 (DECODER_INST_n_5),
- .Probe_out_reg(Probe_out_reg),
- .Q(p_2_in),
- .SR(clear),
- .clk(clk),
- .in0(committ),
- .out(bus_clk),
- .probe_out0(probe_out0),
- .s_daddr_o({bus_addr[16],bus_addr[11:8],bus_addr[3:0]}),
- .xsdb_wr__0(xsdb_wr__0));
- (* C_BUILD_REVISION = "0" *)
- (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_MAJOR_VER = "2" *)
- (* C_CORE_MINOR_VER = "0" *)
- (* C_CORE_TYPE = "2" *)
- (* C_CSE_DRV_VER = "1" *)
- (* C_MAJOR_VERSION = "2013" *)
- (* C_MINOR_VERSION = "1" *)
- (* C_NEXT_SLAVE = "0" *)
- (* C_PIPE_IFACE = "0" *)
- (* C_USE_TEST_REG = "1" *)
- (* C_XDEVICEFAMILY = "zynq" *)
- (* C_XSDB_SLAVE_TYPE = "33" *)
- (* DONT_TOUCH *)
- scalp_zynqps_vio_0_0_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
- (.s_daddr_o(bus_addr),
- .s_dclk_o(bus_clk),
- .s_den_o(bus_den),
- .s_di_o(bus_di),
- .s_do_i(bus_do),
- .s_drdy_i(bus_drdy),
- .s_dwe_o(bus_dwe),
- .s_rst_o(bus_rst),
- .sl_iport_i(sl_iport0),
- .sl_oport_o(sl_oport0));
- FDRE \bus_data_int_reg[0]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[0]),
- .Q(p_2_in),
- .R(1'b0));
- FDRE \bus_data_int_reg[10]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[10]),
- .Q(\bus_data_int_reg_n_0_[10] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[11]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[11]),
- .Q(\bus_data_int_reg_n_0_[11] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[12]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[12]),
- .Q(\bus_data_int_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[13]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[13]),
- .Q(\bus_data_int_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[14]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[14]),
- .Q(\bus_data_int_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[15]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[15]),
- .Q(\bus_data_int_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[1]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[1]),
- .Q(p_0_in),
- .R(1'b0));
- FDRE \bus_data_int_reg[2]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[2]),
- .Q(\bus_data_int_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[3]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[3]),
- .Q(\bus_data_int_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[4]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[4]),
- .Q(\bus_data_int_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[5]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[5]),
- .Q(\bus_data_int_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[6]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[6]),
- .Q(\bus_data_int_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[7]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[7]),
- .Q(\bus_data_int_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[8]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[8]),
- .Q(\bus_data_int_reg_n_0_[8] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[9]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[9]),
- .Q(\bus_data_int_reg_n_0_[9] ),
- .R(1'b0));
-endmodule
-
-(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
-(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
-(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *)
-(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *)
-(* C_XDEVICEFAMILY = "zynq" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* ORIG_REF_NAME = "xsdbs_v1_0_2_xsdbs" *)
-(* dont_touch = "true" *)
-module scalp_zynqps_vio_0_0_xsdbs_v1_0_2_xsdbs
- (s_rst_o,
- s_dclk_o,
- s_den_o,
- s_dwe_o,
- s_daddr_o,
- s_di_o,
- sl_oport_o,
- s_do_i,
- sl_iport_i,
- s_drdy_i);
- output s_rst_o;
- output s_dclk_o;
- output s_den_o;
- output s_dwe_o;
- output [16:0]s_daddr_o;
- output [15:0]s_di_o;
- output [16:0]sl_oport_o;
- input [15:0]s_do_i;
- input [36:0]sl_iport_i;
- input s_drdy_i;
-
- wire [15:0]reg_do;
- wire \reg_do[0]_i_2_n_0 ;
- wire \reg_do[0]_i_3_n_0 ;
- wire \reg_do[0]_i_4_n_0 ;
- wire \reg_do[10]_i_2_n_0 ;
- wire \reg_do[10]_i_3_n_0 ;
- wire \reg_do[10]_i_4_n_0 ;
- wire \reg_do[10]_i_5_n_0 ;
- wire \reg_do[11]_i_2_n_0 ;
- wire \reg_do[11]_i_3_n_0 ;
- wire \reg_do[12]_i_2_n_0 ;
- wire \reg_do[12]_i_3_n_0 ;
- wire \reg_do[13]_i_2_n_0 ;
- wire \reg_do[13]_i_3_n_0 ;
- wire \reg_do[14]_i_2_n_0 ;
- wire \reg_do[14]_i_3_n_0 ;
- wire \reg_do[15]_i_2_n_0 ;
- wire \reg_do[15]_i_3_n_0 ;
- wire \reg_do[15]_i_4_n_0 ;
- wire \reg_do[15]_i_5_n_0 ;
- wire \reg_do[15]_i_6_n_0 ;
- wire \reg_do[1]_i_2_n_0 ;
- wire \reg_do[1]_i_3_n_0 ;
- wire \reg_do[1]_i_4_n_0 ;
- wire \reg_do[2]_i_2_n_0 ;
- wire \reg_do[2]_i_3_n_0 ;
- wire \reg_do[2]_i_4_n_0 ;
- wire \reg_do[3]_i_2_n_0 ;
- wire \reg_do[3]_i_3_n_0 ;
- wire \reg_do[3]_i_4_n_0 ;
- wire \reg_do[4]_i_2_n_0 ;
- wire \reg_do[4]_i_3_n_0 ;
- wire \reg_do[4]_i_4_n_0 ;
- wire \reg_do[5]_i_2_n_0 ;
- wire \reg_do[5]_i_3_n_0 ;
- wire \reg_do[5]_i_4_n_0 ;
- wire \reg_do[5]_i_5_n_0 ;
- wire \reg_do[6]_i_2_n_0 ;
- wire \reg_do[6]_i_3_n_0 ;
- wire \reg_do[6]_i_4_n_0 ;
- wire \reg_do[7]_i_2_n_0 ;
- wire \reg_do[7]_i_3_n_0 ;
- wire \reg_do[7]_i_4_n_0 ;
- wire \reg_do[8]_i_2_n_0 ;
- wire \reg_do[8]_i_3_n_0 ;
- wire \reg_do[8]_i_4_n_0 ;
- wire \reg_do[9]_i_2_n_0 ;
- wire \reg_do[9]_i_3_n_0 ;
- wire \reg_do[9]_i_4_n_0 ;
- wire \reg_do[9]_i_5_n_0 ;
- wire \reg_do[9]_i_6_n_0 ;
- wire \reg_do_reg_n_0_[0] ;
- wire \reg_do_reg_n_0_[10] ;
- wire \reg_do_reg_n_0_[11] ;
- wire \reg_do_reg_n_0_[12] ;
- wire \reg_do_reg_n_0_[13] ;
- wire \reg_do_reg_n_0_[14] ;
- wire \reg_do_reg_n_0_[15] ;
- wire \reg_do_reg_n_0_[1] ;
- wire \reg_do_reg_n_0_[2] ;
- wire \reg_do_reg_n_0_[3] ;
- wire \reg_do_reg_n_0_[4] ;
- wire \reg_do_reg_n_0_[5] ;
- wire \reg_do_reg_n_0_[6] ;
- wire \reg_do_reg_n_0_[7] ;
- wire \reg_do_reg_n_0_[8] ;
- wire \reg_do_reg_n_0_[9] ;
- wire reg_drdy;
- wire reg_drdy_i_1_n_0;
- wire [15:0]reg_test;
- wire reg_test0;
- wire s_den_o;
- wire s_den_o_INST_0_i_1_n_0;
- wire [15:0]s_do_i;
- wire s_drdy_i;
- wire [36:0]sl_iport_i;
- wire [16:0]sl_oport_o;
- (* DONT_TOUCH *) (* UUID = "1" *) wire [127:0]uuid_stamp;
-
- assign s_daddr_o[16:0] = sl_iport_i[20:4];
- assign s_dclk_o = sl_iport_i[1];
- assign s_di_o[15:0] = sl_iport_i[36:21];
- assign s_dwe_o = sl_iport_i[3];
- assign s_rst_o = sl_iport_i[0];
- LUT6 #(
- .INIT(64'hAAAAAAAA0020AAAA))
- \reg_do[0]_i_1
- (.I0(\reg_do[0]_i_2_n_0 ),
- .I1(\reg_do[9]_i_3_n_0 ),
- .I2(reg_test[0]),
- .I3(sl_iport_i[4]),
- .I4(sl_iport_i[5]),
- .I5(\reg_do[9]_i_2_n_0 ),
- .O(reg_do[0]));
- LUT6 #(
- .INIT(64'hABABABAAAAAAABAA))
- \reg_do[0]_i_2
- (.I0(\reg_do[5]_i_3_n_0 ),
- .I1(sl_iport_i[8]),
- .I2(sl_iport_i[7]),
- .I3(\reg_do[0]_i_3_n_0 ),
- .I4(sl_iport_i[6]),
- .I5(\reg_do[0]_i_4_n_0 ),
- .O(\reg_do[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[0]_i_3
- (.I0(uuid_stamp[48]),
- .I1(uuid_stamp[32]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[16]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[0]),
- .O(\reg_do[0]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[0]_i_4
- (.I0(uuid_stamp[112]),
- .I1(uuid_stamp[96]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[80]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[64]),
- .O(\reg_do[0]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2808))
- \reg_do[10]_i_1
- (.I0(\reg_do[10]_i_2_n_0 ),
- .I1(sl_iport_i[4]),
- .I2(sl_iport_i[5]),
- .I3(reg_test[10]),
- .I4(\reg_do[10]_i_3_n_0 ),
- .O(reg_do[10]));
- LUT6 #(
- .INIT(64'h0800000000000000))
- \reg_do[10]_i_2
- (.I0(sl_iport_i[6]),
- .I1(sl_iport_i[9]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(sl_iport_i[11]),
- .I5(sl_iport_i[10]),
- .O(\reg_do[10]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[10]_i_3
- (.I0(\reg_do[10]_i_4_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[10]_i_5_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[10]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[10]_i_4
- (.I0(uuid_stamp[122]),
- .I1(uuid_stamp[106]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[90]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[74]),
- .O(\reg_do[10]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[10]_i_5
- (.I0(uuid_stamp[58]),
- .I1(uuid_stamp[42]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[26]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[10]),
- .O(\reg_do[10]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h4540FFFF45404540))
- \reg_do[11]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[11]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[11]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[11]),
- .O(reg_do[11]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[11]_i_2
- (.I0(uuid_stamp[59]),
- .I1(uuid_stamp[43]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[27]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[11]),
- .O(\reg_do[11]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[11]_i_3
- (.I0(uuid_stamp[123]),
- .I1(uuid_stamp[107]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[91]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[75]),
- .O(\reg_do[11]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h5404FFFF54045404))
- \reg_do[12]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[12]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[12]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[12]),
- .O(reg_do[12]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[12]_i_2
- (.I0(uuid_stamp[124]),
- .I1(uuid_stamp[108]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[92]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[76]),
- .O(\reg_do[12]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[12]_i_3
- (.I0(uuid_stamp[60]),
- .I1(uuid_stamp[44]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[28]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[12]),
- .O(\reg_do[12]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h4540FFFF45404540))
- \reg_do[13]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[13]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[13]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[13]),
- .O(reg_do[13]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[13]_i_2
- (.I0(uuid_stamp[61]),
- .I1(uuid_stamp[45]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[29]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[13]),
- .O(\reg_do[13]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[13]_i_3
- (.I0(uuid_stamp[125]),
- .I1(uuid_stamp[109]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[93]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[77]),
- .O(\reg_do[13]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h4540FFFF45404540))
- \reg_do[14]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[14]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[14]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[14]),
- .O(reg_do[14]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[14]_i_2
- (.I0(uuid_stamp[62]),
- .I1(uuid_stamp[46]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[30]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[14]),
- .O(\reg_do[14]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[14]_i_3
- (.I0(uuid_stamp[126]),
- .I1(uuid_stamp[110]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[94]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[78]),
- .O(\reg_do[14]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0B01FFFF0B010B01))
- \reg_do[15]_i_1
- (.I0(\reg_do[15]_i_2_n_0 ),
- .I1(\reg_do[15]_i_3_n_0 ),
- .I2(\reg_do[15]_i_4_n_0 ),
- .I3(\reg_do[15]_i_5_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[15]),
- .O(reg_do[15]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT3 #(
- .INIT(8'h45))
- \reg_do[15]_i_2
- (.I0(sl_iport_i[8]),
- .I1(sl_iport_i[7]),
- .I2(sl_iport_i[6]),
- .O(\reg_do[15]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h505F3030505F3F3F))
- \reg_do[15]_i_3
- (.I0(uuid_stamp[127]),
- .I1(uuid_stamp[111]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[95]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[79]),
- .O(\reg_do[15]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \reg_do[15]_i_4
- (.I0(sl_iport_i[7]),
- .I1(sl_iport_i[8]),
- .I2(sl_iport_i[9]),
- .I3(sl_iport_i[11]),
- .I4(sl_iport_i[10]),
- .O(\reg_do[15]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[15]_i_5
- (.I0(uuid_stamp[63]),
- .I1(uuid_stamp[47]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[31]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[15]),
- .O(\reg_do[15]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFD0FFFFFFFF))
- \reg_do[15]_i_6
- (.I0(sl_iport_i[6]),
- .I1(sl_iport_i[7]),
- .I2(sl_iport_i[8]),
- .I3(\reg_do[9]_i_2_n_0 ),
- .I4(sl_iport_i[4]),
- .I5(sl_iport_i[5]),
- .O(\reg_do[15]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAAAAAAAAAFEAA))
- \reg_do[1]_i_1
- (.I0(\reg_do[1]_i_2_n_0 ),
- .I1(reg_test[1]),
- .I2(\reg_do[9]_i_3_n_0 ),
- .I3(sl_iport_i[5]),
- .I4(sl_iport_i[4]),
- .I5(\reg_do[9]_i_2_n_0 ),
- .O(reg_do[1]));
- LUT6 #(
- .INIT(64'h00000000FFAE00A2))
- \reg_do[1]_i_2
- (.I0(\reg_do[1]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[1]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[1]_i_3
- (.I0(uuid_stamp[49]),
- .I1(uuid_stamp[33]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[17]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[1]),
- .O(\reg_do[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[1]_i_4
- (.I0(uuid_stamp[113]),
- .I1(uuid_stamp[97]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[81]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[65]),
- .O(\reg_do[1]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[2]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[2]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[2]_i_2_n_0 ),
- .O(reg_do[2]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[2]_i_2
- (.I0(\reg_do[2]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[2]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[2]_i_3
- (.I0(uuid_stamp[114]),
- .I1(uuid_stamp[98]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[82]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[66]),
- .O(\reg_do[2]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[2]_i_4
- (.I0(uuid_stamp[50]),
- .I1(uuid_stamp[34]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[18]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[2]),
- .O(\reg_do[2]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[3]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[3]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[3]_i_2_n_0 ),
- .O(reg_do[3]));
- LUT6 #(
- .INIT(64'h000000003333AA3A))
- \reg_do[3]_i_2
- (.I0(\reg_do[3]_i_3_n_0 ),
- .I1(\reg_do[3]_i_4_n_0 ),
- .I2(sl_iport_i[6]),
- .I3(sl_iport_i[7]),
- .I4(sl_iport_i[8]),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[3]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[3]_i_3
- (.I0(uuid_stamp[51]),
- .I1(uuid_stamp[35]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[19]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[3]),
- .O(\reg_do[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h05F5030305F5F3F3))
- \reg_do[3]_i_4
- (.I0(uuid_stamp[83]),
- .I1(uuid_stamp[67]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[115]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[99]),
- .O(\reg_do[3]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[4]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[4]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[4]_i_2_n_0 ),
- .O(reg_do[4]));
- LUT6 #(
- .INIT(64'h00000000FFAE00A2))
- \reg_do[4]_i_2
- (.I0(\reg_do[4]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[4]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[4]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[4]_i_3
- (.I0(uuid_stamp[52]),
- .I1(uuid_stamp[36]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[20]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[4]),
- .O(\reg_do[4]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[4]_i_4
- (.I0(uuid_stamp[116]),
- .I1(uuid_stamp[100]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[84]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[68]),
- .O(\reg_do[4]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h888888888A88A8A8))
- \reg_do[5]_i_1
- (.I0(\reg_do[5]_i_2_n_0 ),
- .I1(\reg_do[9]_i_2_n_0 ),
- .I2(\reg_do[9]_i_3_n_0 ),
- .I3(reg_test[5]),
- .I4(sl_iport_i[5]),
- .I5(sl_iport_i[4]),
- .O(reg_do[5]));
- LUT6 #(
- .INIT(64'hABABABAAAAAAABAA))
- \reg_do[5]_i_2
- (.I0(\reg_do[5]_i_3_n_0 ),
- .I1(sl_iport_i[8]),
- .I2(sl_iport_i[7]),
- .I3(\reg_do[5]_i_4_n_0 ),
- .I4(sl_iport_i[6]),
- .I5(\reg_do[5]_i_5_n_0 ),
- .O(\reg_do[5]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \reg_do[5]_i_3
- (.I0(sl_iport_i[10]),
- .I1(sl_iport_i[11]),
- .I2(sl_iport_i[9]),
- .I3(sl_iport_i[8]),
- .O(\reg_do[5]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[5]_i_4
- (.I0(uuid_stamp[53]),
- .I1(uuid_stamp[37]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[21]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[5]),
- .O(\reg_do[5]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[5]_i_5
- (.I0(uuid_stamp[117]),
- .I1(uuid_stamp[101]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[85]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[69]),
- .O(\reg_do[5]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[6]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[6]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[6]_i_2_n_0 ),
- .O(reg_do[6]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[6]_i_2
- (.I0(\reg_do[6]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[6]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[6]_i_3
- (.I0(uuid_stamp[118]),
- .I1(uuid_stamp[102]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[86]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[70]),
- .O(\reg_do[6]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[6]_i_4
- (.I0(uuid_stamp[54]),
- .I1(uuid_stamp[38]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[22]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[6]),
- .O(\reg_do[6]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[7]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[7]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[7]_i_2_n_0 ),
- .O(reg_do[7]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[7]_i_2
- (.I0(\reg_do[7]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[7]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[7]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[7]_i_3
- (.I0(uuid_stamp[119]),
- .I1(uuid_stamp[103]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[87]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[71]),
- .O(\reg_do[7]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[7]_i_4
- (.I0(uuid_stamp[55]),
- .I1(uuid_stamp[39]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[23]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[7]),
- .O(\reg_do[7]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF7500))
- \reg_do[8]_i_1
- (.I0(sl_iport_i[5]),
- .I1(sl_iport_i[4]),
- .I2(reg_test[8]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[8]_i_2_n_0 ),
- .O(reg_do[8]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[8]_i_2
- (.I0(\reg_do[8]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[8]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[8]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[8]_i_3
- (.I0(uuid_stamp[120]),
- .I1(uuid_stamp[104]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[88]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[72]),
- .O(\reg_do[8]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[8]_i_4
- (.I0(uuid_stamp[56]),
- .I1(uuid_stamp[40]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[24]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[8]),
- .O(\reg_do[8]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF40144010))
- \reg_do[9]_i_1
- (.I0(\reg_do[9]_i_2_n_0 ),
- .I1(sl_iport_i[5]),
- .I2(sl_iport_i[4]),
- .I3(\reg_do[9]_i_3_n_0 ),
- .I4(reg_test[9]),
- .I5(\reg_do[9]_i_4_n_0 ),
- .O(reg_do[9]));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFF7FFFFF))
- \reg_do[9]_i_2
- (.I0(sl_iport_i[10]),
- .I1(sl_iport_i[11]),
- .I2(sl_iport_i[8]),
- .I3(sl_iport_i[7]),
- .I4(sl_iport_i[9]),
- .O(\reg_do[9]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT3 #(
- .INIT(8'h8A))
- \reg_do[9]_i_3
- (.I0(sl_iport_i[8]),
- .I1(sl_iport_i[7]),
- .I2(sl_iport_i[6]),
- .O(\reg_do[9]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[9]_i_4
- (.I0(\reg_do[9]_i_5_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[9]_i_6_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[9]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[9]_i_5
- (.I0(uuid_stamp[121]),
- .I1(uuid_stamp[105]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[89]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[73]),
- .O(\reg_do[9]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[9]_i_6
- (.I0(uuid_stamp[57]),
- .I1(uuid_stamp[41]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[25]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[9]),
- .O(\reg_do[9]_i_6_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[0]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[0]),
- .Q(\reg_do_reg_n_0_[0] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[10]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[10]),
- .Q(\reg_do_reg_n_0_[10] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[11]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[11]),
- .Q(\reg_do_reg_n_0_[11] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[12]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[12]),
- .Q(\reg_do_reg_n_0_[12] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[13]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[13]),
- .Q(\reg_do_reg_n_0_[13] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[14]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[14]),
- .Q(\reg_do_reg_n_0_[14] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[15]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[15]),
- .Q(\reg_do_reg_n_0_[15] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[1]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[1]),
- .Q(\reg_do_reg_n_0_[1] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[2]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[2]),
- .Q(\reg_do_reg_n_0_[2] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[3]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[3]),
- .Q(\reg_do_reg_n_0_[3] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[4]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[4]),
- .Q(\reg_do_reg_n_0_[4] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[5]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[5]),
- .Q(\reg_do_reg_n_0_[5] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[6]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[6]),
- .Q(\reg_do_reg_n_0_[6] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[7]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[7]),
- .Q(\reg_do_reg_n_0_[7] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[8]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[8]),
- .Q(\reg_do_reg_n_0_[8] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[9]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[9]),
- .Q(\reg_do_reg_n_0_[9] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0000800000000000))
- reg_drdy_i_1
- (.I0(s_den_o_INST_0_i_1_n_0),
- .I1(sl_iport_i[12]),
- .I2(sl_iport_i[13]),
- .I3(sl_iport_i[14]),
- .I4(sl_iport_i[0]),
- .I5(sl_iport_i[2]),
- .O(reg_drdy_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- reg_drdy_reg
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_drdy_i_1_n_0),
- .Q(reg_drdy),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \reg_test[15]_i_1
- (.I0(s_den_o_INST_0_i_1_n_0),
- .I1(sl_iport_i[12]),
- .I2(sl_iport_i[13]),
- .I3(sl_iport_i[14]),
- .I4(sl_iport_i[3]),
- .I5(sl_iport_i[2]),
- .O(reg_test0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[0]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[21]),
- .Q(reg_test[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[10]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[31]),
- .Q(reg_test[10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[11]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[32]),
- .Q(reg_test[11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[12]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[33]),
- .Q(reg_test[12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[13]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[34]),
- .Q(reg_test[13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[14]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[35]),
- .Q(reg_test[14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[15]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[36]),
- .Q(reg_test[15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[1]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[22]),
- .Q(reg_test[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[2]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[23]),
- .Q(reg_test[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[3]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[24]),
- .Q(reg_test[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[4]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[25]),
- .Q(reg_test[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[5]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[26]),
- .Q(reg_test[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[6]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[27]),
- .Q(reg_test[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[7]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[28]),
- .Q(reg_test[7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[8]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[29]),
- .Q(reg_test[8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[9]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[30]),
- .Q(reg_test[9]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'h7FFF0000))
- s_den_o_INST_0
- (.I0(s_den_o_INST_0_i_1_n_0),
- .I1(sl_iport_i[12]),
- .I2(sl_iport_i[13]),
- .I3(sl_iport_i[14]),
- .I4(sl_iport_i[2]),
- .O(s_den_o));
- LUT6 #(
- .INIT(64'h8000000000000000))
- s_den_o_INST_0_i_1
- (.I0(sl_iport_i[15]),
- .I1(sl_iport_i[16]),
- .I2(sl_iport_i[17]),
- .I3(sl_iport_i[18]),
- .I4(sl_iport_i[20]),
- .I5(sl_iport_i[19]),
- .O(s_den_o_INST_0_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT2 #(
- .INIT(4'hE))
- \sl_oport_o[0]_INST_0
- (.I0(reg_drdy),
- .I1(s_drdy_i),
- .O(sl_oport_o[0]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[10]_INST_0
- (.I0(\reg_do_reg_n_0_[9] ),
- .I1(reg_drdy),
- .I2(s_do_i[9]),
- .O(sl_oport_o[10]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[11]_INST_0
- (.I0(\reg_do_reg_n_0_[10] ),
- .I1(reg_drdy),
- .I2(s_do_i[10]),
- .O(sl_oport_o[11]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[12]_INST_0
- (.I0(\reg_do_reg_n_0_[11] ),
- .I1(reg_drdy),
- .I2(s_do_i[11]),
- .O(sl_oport_o[12]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[13]_INST_0
- (.I0(\reg_do_reg_n_0_[12] ),
- .I1(reg_drdy),
- .I2(s_do_i[12]),
- .O(sl_oport_o[13]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[14]_INST_0
- (.I0(\reg_do_reg_n_0_[13] ),
- .I1(reg_drdy),
- .I2(s_do_i[13]),
- .O(sl_oport_o[14]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[15]_INST_0
- (.I0(\reg_do_reg_n_0_[14] ),
- .I1(reg_drdy),
- .I2(s_do_i[14]),
- .O(sl_oport_o[15]));
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[16]_INST_0
- (.I0(\reg_do_reg_n_0_[15] ),
- .I1(reg_drdy),
- .I2(s_do_i[15]),
- .O(sl_oport_o[16]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[1]_INST_0
- (.I0(\reg_do_reg_n_0_[0] ),
- .I1(reg_drdy),
- .I2(s_do_i[0]),
- .O(sl_oport_o[1]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[2]_INST_0
- (.I0(\reg_do_reg_n_0_[1] ),
- .I1(reg_drdy),
- .I2(s_do_i[1]),
- .O(sl_oport_o[2]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[3]_INST_0
- (.I0(\reg_do_reg_n_0_[2] ),
- .I1(reg_drdy),
- .I2(s_do_i[2]),
- .O(sl_oport_o[3]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[4]_INST_0
- (.I0(\reg_do_reg_n_0_[3] ),
- .I1(reg_drdy),
- .I2(s_do_i[3]),
- .O(sl_oport_o[4]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[5]_INST_0
- (.I0(\reg_do_reg_n_0_[4] ),
- .I1(reg_drdy),
- .I2(s_do_i[4]),
- .O(sl_oport_o[5]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[6]_INST_0
- (.I0(\reg_do_reg_n_0_[5] ),
- .I1(reg_drdy),
- .I2(s_do_i[5]),
- .O(sl_oport_o[6]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[7]_INST_0
- (.I0(\reg_do_reg_n_0_[6] ),
- .I1(reg_drdy),
- .I2(s_do_i[6]),
- .O(sl_oport_o[7]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[8]_INST_0
- (.I0(\reg_do_reg_n_0_[7] ),
- .I1(reg_drdy),
- .I2(s_do_i[7]),
- .O(sl_oport_o[8]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[9]_INST_0
- (.I0(\reg_do_reg_n_0_[8] ),
- .I1(reg_drdy),
- .I2(s_do_i[8]),
- .O(sl_oport_o[9]));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[0]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[0]),
- .Q(uuid_stamp[0]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[100]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[100]),
- .Q(uuid_stamp[100]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[101]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[101]),
- .Q(uuid_stamp[101]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[102]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[102]),
- .Q(uuid_stamp[102]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[103]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[103]),
- .Q(uuid_stamp[103]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[104]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[104]),
- .Q(uuid_stamp[104]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[105]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[105]),
- .Q(uuid_stamp[105]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[106]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[106]),
- .Q(uuid_stamp[106]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[107]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[107]),
- .Q(uuid_stamp[107]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[108]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[108]),
- .Q(uuid_stamp[108]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[109]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[109]),
- .Q(uuid_stamp[109]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[10]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[10]),
- .Q(uuid_stamp[10]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[110]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[110]),
- .Q(uuid_stamp[110]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[111]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[111]),
- .Q(uuid_stamp[111]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[112]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[112]),
- .Q(uuid_stamp[112]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[113]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[113]),
- .Q(uuid_stamp[113]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[114]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[114]),
- .Q(uuid_stamp[114]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[115]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[115]),
- .Q(uuid_stamp[115]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[116]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[116]),
- .Q(uuid_stamp[116]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[117]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[117]),
- .Q(uuid_stamp[117]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[118]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[118]),
- .Q(uuid_stamp[118]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[119]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[119]),
- .Q(uuid_stamp[119]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[11]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[11]),
- .Q(uuid_stamp[11]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[120]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[120]),
- .Q(uuid_stamp[120]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[121]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[121]),
- .Q(uuid_stamp[121]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[122]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[122]),
- .Q(uuid_stamp[122]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[123]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[123]),
- .Q(uuid_stamp[123]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[124]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[124]),
- .Q(uuid_stamp[124]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[125]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[125]),
- .Q(uuid_stamp[125]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[126]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[126]),
- .Q(uuid_stamp[126]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[127]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[127]),
- .Q(uuid_stamp[127]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[12]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[12]),
- .Q(uuid_stamp[12]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[13]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[13]),
- .Q(uuid_stamp[13]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[14]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[14]),
- .Q(uuid_stamp[14]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[15]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[15]),
- .Q(uuid_stamp[15]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[16]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[16]),
- .Q(uuid_stamp[16]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[17]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[17]),
- .Q(uuid_stamp[17]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[18]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[18]),
- .Q(uuid_stamp[18]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[19]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[19]),
- .Q(uuid_stamp[19]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[1]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[1]),
- .Q(uuid_stamp[1]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[20]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[20]),
- .Q(uuid_stamp[20]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[21]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[21]),
- .Q(uuid_stamp[21]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[22]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[22]),
- .Q(uuid_stamp[22]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[23]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[23]),
- .Q(uuid_stamp[23]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[24]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[24]),
- .Q(uuid_stamp[24]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[25]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[25]),
- .Q(uuid_stamp[25]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[26]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[26]),
- .Q(uuid_stamp[26]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[27]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[27]),
- .Q(uuid_stamp[27]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[28]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[28]),
- .Q(uuid_stamp[28]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[29]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[29]),
- .Q(uuid_stamp[29]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[2]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[2]),
- .Q(uuid_stamp[2]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[30]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[30]),
- .Q(uuid_stamp[30]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[31]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[31]),
- .Q(uuid_stamp[31]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[32]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[32]),
- .Q(uuid_stamp[32]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[33]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[33]),
- .Q(uuid_stamp[33]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[34]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[34]),
- .Q(uuid_stamp[34]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[35]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[35]),
- .Q(uuid_stamp[35]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[36]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[36]),
- .Q(uuid_stamp[36]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[37]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[37]),
- .Q(uuid_stamp[37]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[38]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[38]),
- .Q(uuid_stamp[38]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[39]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[39]),
- .Q(uuid_stamp[39]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[3]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[3]),
- .Q(uuid_stamp[3]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[40]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[40]),
- .Q(uuid_stamp[40]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[41]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[41]),
- .Q(uuid_stamp[41]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[42]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[42]),
- .Q(uuid_stamp[42]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[43]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[43]),
- .Q(uuid_stamp[43]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[44]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[44]),
- .Q(uuid_stamp[44]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[45]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[45]),
- .Q(uuid_stamp[45]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[46]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[46]),
- .Q(uuid_stamp[46]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[47]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[47]),
- .Q(uuid_stamp[47]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[48]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[48]),
- .Q(uuid_stamp[48]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[49]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[49]),
- .Q(uuid_stamp[49]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[4]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[4]),
- .Q(uuid_stamp[4]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[50]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[50]),
- .Q(uuid_stamp[50]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[51]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[51]),
- .Q(uuid_stamp[51]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[52]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[52]),
- .Q(uuid_stamp[52]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[53]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[53]),
- .Q(uuid_stamp[53]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[54]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[54]),
- .Q(uuid_stamp[54]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[55]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[55]),
- .Q(uuid_stamp[55]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[56]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[56]),
- .Q(uuid_stamp[56]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[57]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[57]),
- .Q(uuid_stamp[57]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[58]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[58]),
- .Q(uuid_stamp[58]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[59]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[59]),
- .Q(uuid_stamp[59]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[5]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[5]),
- .Q(uuid_stamp[5]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[60]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[60]),
- .Q(uuid_stamp[60]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[61]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[61]),
- .Q(uuid_stamp[61]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[62]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[62]),
- .Q(uuid_stamp[62]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[63]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[63]),
- .Q(uuid_stamp[63]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[64]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[64]),
- .Q(uuid_stamp[64]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[65]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[65]),
- .Q(uuid_stamp[65]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[66]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[66]),
- .Q(uuid_stamp[66]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[67]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[67]),
- .Q(uuid_stamp[67]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[68]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[68]),
- .Q(uuid_stamp[68]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[69]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[69]),
- .Q(uuid_stamp[69]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[6]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[6]),
- .Q(uuid_stamp[6]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[70]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[70]),
- .Q(uuid_stamp[70]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[71]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[71]),
- .Q(uuid_stamp[71]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[72]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[72]),
- .Q(uuid_stamp[72]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[73]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[73]),
- .Q(uuid_stamp[73]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[74]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[74]),
- .Q(uuid_stamp[74]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[75]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[75]),
- .Q(uuid_stamp[75]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[76]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[76]),
- .Q(uuid_stamp[76]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[77]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[77]),
- .Q(uuid_stamp[77]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[78]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[78]),
- .Q(uuid_stamp[78]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[79]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[79]),
- .Q(uuid_stamp[79]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[7]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[7]),
- .Q(uuid_stamp[7]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[80]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[80]),
- .Q(uuid_stamp[80]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[81]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[81]),
- .Q(uuid_stamp[81]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[82]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[82]),
- .Q(uuid_stamp[82]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[83]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[83]),
- .Q(uuid_stamp[83]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[84]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[84]),
- .Q(uuid_stamp[84]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[85]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[85]),
- .Q(uuid_stamp[85]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[86]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[86]),
- .Q(uuid_stamp[86]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[87]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[87]),
- .Q(uuid_stamp[87]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[88]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[88]),
- .Q(uuid_stamp[88]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[89]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[89]),
- .Q(uuid_stamp[89]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[8]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[8]),
- .Q(uuid_stamp[8]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[90]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[90]),
- .Q(uuid_stamp[90]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[91]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[91]),
- .Q(uuid_stamp[91]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[92]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[92]),
- .Q(uuid_stamp[92]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[93]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[93]),
- .Q(uuid_stamp[93]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[94]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[94]),
- .Q(uuid_stamp[94]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[95]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[95]),
- .Q(uuid_stamp[95]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[96]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[96]),
- .Q(uuid_stamp[96]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[97]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[97]),
- .Q(uuid_stamp[97]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[98]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[98]),
- .Q(uuid_stamp[98]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[99]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[99]),
- .Q(uuid_stamp[99]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[9]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[9]),
- .Q(uuid_stamp[9]),
- .R(1'b0));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.v
deleted file mode 100644
index 93800814b131eddd61fde3ce84d7ce2532f7c00c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.v
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:36 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub
-// /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.v
-// Design : scalp_zynqps_vio_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "vio,Vivado 2019.2" *)
-module scalp_zynqps_vio_0_0(clk, probe_out0)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0]" */;
- input clk;
- output [0:0]probe_out0;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd
deleted file mode 100644
index e32bf2606b62245018c2e55c73ab80a27d49fdcd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
--- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY scalp_zynqps_vio_0_0 IS
-PORT (
-CLK : IN STD_LOGIC;
-
-probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) := "0"
-);
-END scalp_zynqps_vio_0_0;
-ARCHITECTURE scalp_zynqps_vio_0_0_arch OF scalp_zynqps_vio_0_0 IS
-BEGIN
-END scalp_zynqps_vio_0_0_arch;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/synth/scalp_zynqps_vio_0_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/synth/scalp_zynqps_vio_0_0.v
deleted file mode 100644
index 494512c223fd89e4a9b8a8c02f683cda7cedf2a1..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/synth/scalp_zynqps_vio_0_0.v
+++ /dev/null
@@ -1,1378 +0,0 @@
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-(* X_CORE_INFO = "vio,Vivado 2019.2" *)
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_vio_0_0,vio,{}" *)
-(* CORE_GENERATION_INFO = "scalp_zynqps_vio_0_0,vio,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=vio,x_ipVersion=3.0,x_ipLanguage=VHDL,C_XLNX_HW_PROBE_INFO=DEFAULT,C_XDEVICEFAMILY=zynq,C_CORE_TYPE=2,C_CORE_INFO1=0,C_CORE_INFO2=0,C_NUM_PROBE_IN=0,C_NUM_PROBE_OUT=1,C_EN_PROBE_IN_ACTIVITY=0,C_MAJOR_VERSION=2013,C_MINOR_VERSION=1,C_BUILD_REVISION=0,C_CORE_MAJOR_VER=2,C_CORE_MINOR_VER=0,C_CORE_MINOR_ALPHA_VER=97,C_XSDB_SLAVE_TYPE=33,C_NEXT_SLAVE=0,C_CSE_DRV_VER=1,C_USE_TEST_REG=1,C_PIPE_IFACE=0,C_PROBE_IN0_WIDTH=1,C_PROBE_IN1_WIDTH=1,C_PROBE_IN2_WIDTH=1,C_PROBE_IN3_WIDTH=1,C_PROBE_IN4_WIDTH=1,C_PROBE_IN5_WIDTH=1,C_PROBE_IN6_WIDTH=1,C_PROBE_IN7_WIDTH=1,C_PROBE_IN8_WIDTH=1,C_PROBE_IN9_WIDTH=1,C_PROBE_IN10_WIDTH=1,C_PROBE_IN11_WIDTH=1,C_PROBE_IN12_WIDTH=1,C_PROBE_IN13_WIDTH=1,C_PROBE_IN14_WIDTH=1,C_PROBE_IN15_WIDTH=1,C_PROBE_IN16_WIDTH=1,C_PROBE_IN17_WIDTH=1,C_PROBE_IN18_WIDTH=1,C_PROBE_IN19_WIDTH=1,C_PROBE_IN20_WIDTH=1,C_PROBE_IN21_WIDTH=1,C_PROBE_IN22_WIDTH=1,C_PROBE_IN23_WIDTH=1,C_PROBE_IN24_WIDTH=1,C_PROBE_IN25_WIDTH=1,C_PROBE_IN26_WIDTH=1,C_PROBE_IN27_WIDTH=1,C_PROBE_IN28_WIDTH=1,C_PROBE_IN29_WIDTH=1,C_PROBE_IN30_WIDTH=1,C_PROBE_IN31_WIDTH=1,C_PROBE_IN32_WIDTH=1,C_PROBE_IN33_WIDTH=1,C_PROBE_IN34_WIDTH=1,C_PROBE_IN35_WIDTH=1,C_PROBE_IN36_WIDTH=1,C_PROBE_IN37_WIDTH=1,C_PROBE_IN38_WIDTH=1,C_PROBE_IN39_WIDTH=1,C_PROBE_IN40_WIDTH=1,C_PROBE_IN41_WIDTH=1,C_PROBE_IN42_WIDTH=1,C_PROBE_IN43_WIDTH=1,C_PROBE_IN44_WIDTH=1,C_PROBE_IN45_WIDTH=1,C_PROBE_IN46_WIDTH=1,C_PROBE_IN47_WIDTH=1,C_PROBE_IN48_WIDTH=1,C_PROBE_IN49_WIDTH=1,C_PROBE_IN50_WIDTH=1,C_PROBE_IN51_WIDTH=1,C_PROBE_IN52_WIDTH=1,C_PROBE_IN53_WIDTH=1,C_PROBE_IN54_WIDTH=1,C_PROBE_IN55_WIDTH=1,C_PROBE_IN56_WIDTH=1,C_PROBE_IN57_WIDTH=1,C_PROBE_IN58_WIDTH=1,C_PROBE_IN59_WIDTH=1,C_PROBE_IN60_WIDTH=1,C_PROBE_IN61_WIDTH=1,C_PROBE_IN62_WIDTH=1,C_PROBE_IN63_WIDTH=1,C_PROBE_IN64_WIDTH=1,C_PROBE_IN65_WIDTH=1,C_PROBE_IN66_WIDTH=1,C_PROBE_IN67_WIDTH=1,C_PROBE_IN68_WIDTH=1,C_PROBE_IN69_WIDTH=1,C_PROBE_IN70_WIDTH=1,C_PROBE_IN71_WIDTH=1,C_PROBE_IN72_WIDTH=1,\
-C_PROBE_IN73_WIDTH=1,C_PROBE_IN74_WIDTH=1,C_PROBE_IN75_WIDTH=1,C_PROBE_IN76_WIDTH=1,C_PROBE_IN77_WIDTH=1,C_PROBE_IN78_WIDTH=1,C_PROBE_IN79_WIDTH=1,C_PROBE_IN80_WIDTH=1,C_PROBE_IN81_WIDTH=1,C_PROBE_IN82_WIDTH=1,C_PROBE_IN83_WIDTH=1,C_PROBE_IN84_WIDTH=1,C_PROBE_IN85_WIDTH=1,C_PROBE_IN86_WIDTH=1,C_PROBE_IN87_WIDTH=1,C_PROBE_IN88_WIDTH=1,C_PROBE_IN89_WIDTH=1,C_PROBE_IN90_WIDTH=1,C_PROBE_IN91_WIDTH=1,C_PROBE_IN92_WIDTH=1,C_PROBE_IN93_WIDTH=1,C_PROBE_IN94_WIDTH=1,C_PROBE_IN95_WIDTH=1,C_PROBE_IN96_WIDTH=1,C_PROBE_IN97_WIDTH=1,C_PROBE_IN98_WIDTH=1,C_PROBE_IN99_WIDTH=1,C_PROBE_IN100_WIDTH=1,C_PROBE_IN101_WIDTH=1,C_PROBE_IN102_WIDTH=1,C_PROBE_IN103_WIDTH=1,C_PROBE_IN104_WIDTH=1,C_PROBE_IN105_WIDTH=1,C_PROBE_IN106_WIDTH=1,C_PROBE_IN107_WIDTH=1,C_PROBE_IN108_WIDTH=1,C_PROBE_IN109_WIDTH=1,C_PROBE_IN110_WIDTH=1,C_PROBE_IN111_WIDTH=1,C_PROBE_IN112_WIDTH=1,C_PROBE_IN113_WIDTH=1,C_PROBE_IN114_WIDTH=1,C_PROBE_IN115_WIDTH=1,C_PROBE_IN116_WIDTH=1,C_PROBE_IN117_WIDTH=1,C_PROBE_IN118_WIDTH=1,C_PROBE_IN119_WIDTH=1,C_PROBE_IN120_WIDTH=1,C_PROBE_IN121_WIDTH=1,C_PROBE_IN122_WIDTH=1,C_PROBE_IN123_WIDTH=1,C_PROBE_IN124_WIDTH=1,C_PROBE_IN125_WIDTH=1,C_PROBE_IN126_WIDTH=1,C_PROBE_IN127_WIDTH=1,C_PROBE_IN128_WIDTH=1,C_PROBE_IN129_WIDTH=1,C_PROBE_IN130_WIDTH=1,C_PROBE_IN131_WIDTH=1,C_PROBE_IN132_WIDTH=1,C_PROBE_IN133_WIDTH=1,C_PROBE_IN134_WIDTH=1,C_PROBE_IN135_WIDTH=1,C_PROBE_IN136_WIDTH=1,C_PROBE_IN137_WIDTH=1,C_PROBE_IN138_WIDTH=1,C_PROBE_IN139_WIDTH=1,C_PROBE_IN140_WIDTH=1,C_PROBE_IN141_WIDTH=1,C_PROBE_IN142_WIDTH=1,C_PROBE_IN143_WIDTH=1,C_PROBE_IN144_WIDTH=1,C_PROBE_IN145_WIDTH=1,C_PROBE_IN146_WIDTH=1,C_PROBE_IN147_WIDTH=1,C_PROBE_IN148_WIDTH=1,C_PROBE_IN149_WIDTH=1,C_PROBE_IN150_WIDTH=1,C_PROBE_IN151_WIDTH=1,C_PROBE_IN152_WIDTH=1,C_PROBE_IN153_WIDTH=1,C_PROBE_IN154_WIDTH=1,C_PROBE_IN155_WIDTH=1,C_PROBE_IN156_WIDTH=1,C_PROBE_IN157_WIDTH=1,C_PROBE_IN158_WIDTH=1,C_PROBE_IN159_WIDTH=1,C_PROBE_IN160_WIDTH=1,C_PROBE_IN161_WIDTH=1,C_PROBE_IN162_WIDTH=1,C_PROBE_IN163_WIDTH=1,C_PROBE_IN164_WIDTH=1,C_PROBE_IN165_WIDTH=1,C_PROBE_IN166_WIDTH=1,C_PROBE_IN167_WIDTH=1,C_PROBE_IN168_WIDTH=1,C_PROBE_IN169_WIDTH=1,C_PROBE_IN170_WIDTH=1,C_PROBE_IN171_WIDTH=1,C_PROBE_IN172_WIDTH=1,\
-C_PROBE_IN173_WIDTH=1,C_PROBE_IN174_WIDTH=1,C_PROBE_IN175_WIDTH=1,C_PROBE_IN176_WIDTH=1,C_PROBE_IN177_WIDTH=1,C_PROBE_IN178_WIDTH=1,C_PROBE_IN179_WIDTH=1,C_PROBE_IN180_WIDTH=1,C_PROBE_IN181_WIDTH=1,C_PROBE_IN182_WIDTH=1,C_PROBE_IN183_WIDTH=1,C_PROBE_IN184_WIDTH=1,C_PROBE_IN185_WIDTH=1,C_PROBE_IN186_WIDTH=1,C_PROBE_IN187_WIDTH=1,C_PROBE_IN188_WIDTH=1,C_PROBE_IN189_WIDTH=1,C_PROBE_IN190_WIDTH=1,C_PROBE_IN191_WIDTH=1,C_PROBE_IN192_WIDTH=1,C_PROBE_IN193_WIDTH=1,C_PROBE_IN194_WIDTH=1,C_PROBE_IN195_WIDTH=1,C_PROBE_IN196_WIDTH=1,C_PROBE_IN197_WIDTH=1,C_PROBE_IN198_WIDTH=1,C_PROBE_IN199_WIDTH=1,C_PROBE_IN200_WIDTH=1,C_PROBE_IN201_WIDTH=1,C_PROBE_IN202_WIDTH=1,C_PROBE_IN203_WIDTH=1,C_PROBE_IN204_WIDTH=1,C_PROBE_IN205_WIDTH=1,C_PROBE_IN206_WIDTH=1,C_PROBE_IN207_WIDTH=1,C_PROBE_IN208_WIDTH=1,C_PROBE_IN209_WIDTH=1,C_PROBE_IN210_WIDTH=1,C_PROBE_IN211_WIDTH=1,C_PROBE_IN212_WIDTH=1,C_PROBE_IN213_WIDTH=1,C_PROBE_IN214_WIDTH=1,C_PROBE_IN215_WIDTH=1,C_PROBE_IN216_WIDTH=1,C_PROBE_IN217_WIDTH=1,C_PROBE_IN218_WIDTH=1,C_PROBE_IN219_WIDTH=1,C_PROBE_IN220_WIDTH=1,C_PROBE_IN221_WIDTH=1,C_PROBE_IN222_WIDTH=1,C_PROBE_IN223_WIDTH=1,C_PROBE_IN224_WIDTH=1,C_PROBE_IN225_WIDTH=1,C_PROBE_IN226_WIDTH=1,C_PROBE_IN227_WIDTH=1,C_PROBE_IN228_WIDTH=1,C_PROBE_IN229_WIDTH=1,C_PROBE_IN230_WIDTH=1,C_PROBE_IN231_WIDTH=1,C_PROBE_IN232_WIDTH=1,C_PROBE_IN233_WIDTH=1,C_PROBE_IN234_WIDTH=1,C_PROBE_IN235_WIDTH=1,C_PROBE_IN236_WIDTH=1,C_PROBE_IN237_WIDTH=1,C_PROBE_IN238_WIDTH=1,C_PROBE_IN239_WIDTH=1,C_PROBE_IN240_WIDTH=1,C_PROBE_IN241_WIDTH=1,C_PROBE_IN242_WIDTH=1,C_PROBE_IN243_WIDTH=1,C_PROBE_IN244_WIDTH=1,C_PROBE_IN245_WIDTH=1,C_PROBE_IN246_WIDTH=1,C_PROBE_IN247_WIDTH=1,C_PROBE_IN248_WIDTH=1,C_PROBE_IN249_WIDTH=1,C_PROBE_IN250_WIDTH=1,C_PROBE_IN251_WIDTH=1,C_PROBE_IN252_WIDTH=1,C_PROBE_IN253_WIDTH=1,C_PROBE_IN254_WIDTH=1,C_PROBE_IN255_WIDTH=1,C_PROBE_OUT0_WIDTH=1,C_PROBE_OUT1_WIDTH=1,C_PROBE_OUT2_WIDTH=1,C_PROBE_OUT3_WIDTH=1,C_PROBE_OUT4_WIDTH=1,C_PROBE_OUT5_WIDTH=1,C_PROBE_OUT6_WIDTH=1,C_PROBE_OUT7_WIDTH=1,C_PROBE_OUT8_WIDTH=1,C_PROBE_OUT9_WIDTH=1,C_PROBE_OUT10_WIDTH=1,C_PROBE_OUT11_WIDTH=1,C_PROBE_OUT12_WIDTH=1,C_PROBE_OUT13_WIDTH=1,C_PROBE_OUT14_WIDTH=1,C_PROBE_OUT15_WIDTH=1,C_PROBE_OUT16_WIDTH=1,\
-C_PROBE_OUT17_WIDTH=1,C_PROBE_OUT18_WIDTH=1,C_PROBE_OUT19_WIDTH=1,C_PROBE_OUT20_WIDTH=1,C_PROBE_OUT21_WIDTH=1,C_PROBE_OUT22_WIDTH=1,C_PROBE_OUT23_WIDTH=1,C_PROBE_OUT24_WIDTH=1,C_PROBE_OUT25_WIDTH=1,C_PROBE_OUT26_WIDTH=1,C_PROBE_OUT27_WIDTH=1,C_PROBE_OUT28_WIDTH=1,C_PROBE_OUT29_WIDTH=1,C_PROBE_OUT30_WIDTH=1,C_PROBE_OUT31_WIDTH=1,C_PROBE_OUT32_WIDTH=1,C_PROBE_OUT33_WIDTH=1,C_PROBE_OUT34_WIDTH=1,C_PROBE_OUT35_WIDTH=1,C_PROBE_OUT36_WIDTH=1,C_PROBE_OUT37_WIDTH=1,C_PROBE_OUT38_WIDTH=1,C_PROBE_OUT39_WIDTH=1,C_PROBE_OUT40_WIDTH=1,C_PROBE_OUT41_WIDTH=1,C_PROBE_OUT42_WIDTH=1,C_PROBE_OUT43_WIDTH=1,C_PROBE_OUT44_WIDTH=1,C_PROBE_OUT45_WIDTH=1,C_PROBE_OUT46_WIDTH=1,C_PROBE_OUT47_WIDTH=1,C_PROBE_OUT48_WIDTH=1,C_PROBE_OUT49_WIDTH=1,C_PROBE_OUT50_WIDTH=1,C_PROBE_OUT51_WIDTH=1,C_PROBE_OUT52_WIDTH=1,C_PROBE_OUT53_WIDTH=1,C_PROBE_OUT54_WIDTH=1,C_PROBE_OUT55_WIDTH=1,C_PROBE_OUT56_WIDTH=1,C_PROBE_OUT57_WIDTH=1,C_PROBE_OUT58_WIDTH=1,C_PROBE_OUT59_WIDTH=1,C_PROBE_OUT60_WIDTH=1,C_PROBE_OUT61_WIDTH=1,C_PROBE_OUT62_WIDTH=1,C_PROBE_OUT63_WIDTH=1,C_PROBE_OUT64_WIDTH=1,C_PROBE_OUT65_WIDTH=1,C_PROBE_OUT66_WIDTH=1,C_PROBE_OUT67_WIDTH=1,C_PROBE_OUT68_WIDTH=1,C_PROBE_OUT69_WIDTH=1,C_PROBE_OUT70_WIDTH=1,C_PROBE_OUT71_WIDTH=1,C_PROBE_OUT72_WIDTH=1,C_PROBE_OUT73_WIDTH=1,C_PROBE_OUT74_WIDTH=1,C_PROBE_OUT75_WIDTH=1,C_PROBE_OUT76_WIDTH=1,C_PROBE_OUT77_WIDTH=1,C_PROBE_OUT78_WIDTH=1,C_PROBE_OUT79_WIDTH=1,C_PROBE_OUT80_WIDTH=1,C_PROBE_OUT81_WIDTH=1,C_PROBE_OUT82_WIDTH=1,C_PROBE_OUT83_WIDTH=1,C_PROBE_OUT84_WIDTH=1,C_PROBE_OUT85_WIDTH=1,C_PROBE_OUT86_WIDTH=1,C_PROBE_OUT87_WIDTH=1,C_PROBE_OUT88_WIDTH=1,C_PROBE_OUT89_WIDTH=1,C_PROBE_OUT90_WIDTH=1,C_PROBE_OUT91_WIDTH=1,C_PROBE_OUT92_WIDTH=1,C_PROBE_OUT93_WIDTH=1,C_PROBE_OUT94_WIDTH=1,C_PROBE_OUT95_WIDTH=1,C_PROBE_OUT96_WIDTH=1,C_PROBE_OUT97_WIDTH=1,C_PROBE_OUT98_WIDTH=1,C_PROBE_OUT99_WIDTH=1,C_PROBE_OUT100_WIDTH=1,C_PROBE_OUT101_WIDTH=1,C_PROBE_OUT102_WIDTH=1,C_PROBE_OUT103_WIDTH=1,C_PROBE_OUT104_WIDTH=1,C_PROBE_OUT105_WIDTH=1,C_PROBE_OUT106_WIDTH=1,C_PROBE_OUT107_WIDTH=1,C_PROBE_OUT108_WIDTH=1,C_PROBE_OUT109_WIDTH=1,C_PROBE_OUT110_WIDTH=1,C_PROBE_OUT111_WIDTH=1,C_PROBE_OUT112_WIDTH=1,C_PROBE_OUT113_WIDTH=1,C_PROBE_OUT114_WIDTH=1,C_PROBE_OUT115_WIDTH=1,C_PROBE_OUT116_WIDTH=1,\
-C_PROBE_OUT117_WIDTH=1,C_PROBE_OUT118_WIDTH=1,C_PROBE_OUT119_WIDTH=1,C_PROBE_OUT120_WIDTH=1,C_PROBE_OUT121_WIDTH=1,C_PROBE_OUT122_WIDTH=1,C_PROBE_OUT123_WIDTH=1,C_PROBE_OUT124_WIDTH=1,C_PROBE_OUT125_WIDTH=1,C_PROBE_OUT126_WIDTH=1,C_PROBE_OUT127_WIDTH=1,C_PROBE_OUT128_WIDTH=1,C_PROBE_OUT129_WIDTH=1,C_PROBE_OUT130_WIDTH=1,C_PROBE_OUT131_WIDTH=1,C_PROBE_OUT132_WIDTH=1,C_PROBE_OUT133_WIDTH=1,C_PROBE_OUT134_WIDTH=1,C_PROBE_OUT135_WIDTH=1,C_PROBE_OUT136_WIDTH=1,C_PROBE_OUT137_WIDTH=1,C_PROBE_OUT138_WIDTH=1,C_PROBE_OUT139_WIDTH=1,C_PROBE_OUT140_WIDTH=1,C_PROBE_OUT141_WIDTH=1,C_PROBE_OUT142_WIDTH=1,C_PROBE_OUT143_WIDTH=1,C_PROBE_OUT144_WIDTH=1,C_PROBE_OUT145_WIDTH=1,C_PROBE_OUT146_WIDTH=1,C_PROBE_OUT147_WIDTH=1,C_PROBE_OUT148_WIDTH=1,C_PROBE_OUT149_WIDTH=1,C_PROBE_OUT150_WIDTH=1,C_PROBE_OUT151_WIDTH=1,C_PROBE_OUT152_WIDTH=1,C_PROBE_OUT153_WIDTH=1,C_PROBE_OUT154_WIDTH=1,C_PROBE_OUT155_WIDTH=1,C_PROBE_OUT156_WIDTH=1,C_PROBE_OUT157_WIDTH=1,C_PROBE_OUT158_WIDTH=1,C_PROBE_OUT159_WIDTH=1,C_PROBE_OUT160_WIDTH=1,C_PROBE_OUT161_WIDTH=1,C_PROBE_OUT162_WIDTH=1,C_PROBE_OUT163_WIDTH=1,C_PROBE_OUT164_WIDTH=1,C_PROBE_OUT165_WIDTH=1,C_PROBE_OUT166_WIDTH=1,C_PROBE_OUT167_WIDTH=1,C_PROBE_OUT168_WIDTH=1,C_PROBE_OUT169_WIDTH=1,C_PROBE_OUT170_WIDTH=1,C_PROBE_OUT171_WIDTH=1,C_PROBE_OUT172_WIDTH=1,C_PROBE_OUT173_WIDTH=1,C_PROBE_OUT174_WIDTH=1,C_PROBE_OUT175_WIDTH=1,C_PROBE_OUT176_WIDTH=1,C_PROBE_OUT177_WIDTH=1,C_PROBE_OUT178_WIDTH=1,C_PROBE_OUT179_WIDTH=1,C_PROBE_OUT180_WIDTH=1,C_PROBE_OUT181_WIDTH=1,C_PROBE_OUT182_WIDTH=1,C_PROBE_OUT183_WIDTH=1,C_PROBE_OUT184_WIDTH=1,C_PROBE_OUT185_WIDTH=1,C_PROBE_OUT186_WIDTH=1,C_PROBE_OUT187_WIDTH=1,C_PROBE_OUT188_WIDTH=1,C_PROBE_OUT189_WIDTH=1,C_PROBE_OUT190_WIDTH=1,C_PROBE_OUT191_WIDTH=1,C_PROBE_OUT192_WIDTH=1,C_PROBE_OUT193_WIDTH=1,C_PROBE_OUT194_WIDTH=1,C_PROBE_OUT195_WIDTH=1,C_PROBE_OUT196_WIDTH=1,C_PROBE_OUT197_WIDTH=1,C_PROBE_OUT198_WIDTH=1,C_PROBE_OUT199_WIDTH=1,C_PROBE_OUT200_WIDTH=1,C_PROBE_OUT201_WIDTH=1,C_PROBE_OUT202_WIDTH=1,C_PROBE_OUT203_WIDTH=1,C_PROBE_OUT204_WIDTH=1,C_PROBE_OUT205_WIDTH=1,C_PROBE_OUT206_WIDTH=1,C_PROBE_OUT207_WIDTH=1,C_PROBE_OUT208_WIDTH=1,C_PROBE_OUT209_WIDTH=1,C_PROBE_OUT210_WIDTH=1,C_PROBE_OUT211_WIDTH=1,C_PROBE_OUT212_WIDTH=1,C_PROBE_OUT213_WIDTH=1,C_PROBE_OUT214_WIDTH=1,C_PROBE_OUT215_WIDTH=1,C_PROBE_OUT216_WIDTH=1,\
-C_PROBE_OUT217_WIDTH=1,C_PROBE_OUT218_WIDTH=1,C_PROBE_OUT219_WIDTH=1,C_PROBE_OUT220_WIDTH=1,C_PROBE_OUT221_WIDTH=1,C_PROBE_OUT222_WIDTH=1,C_PROBE_OUT223_WIDTH=1,C_PROBE_OUT224_WIDTH=1,C_PROBE_OUT225_WIDTH=1,C_PROBE_OUT226_WIDTH=1,C_PROBE_OUT227_WIDTH=1,C_PROBE_OUT228_WIDTH=1,C_PROBE_OUT229_WIDTH=1,C_PROBE_OUT230_WIDTH=1,C_PROBE_OUT231_WIDTH=1,C_PROBE_OUT232_WIDTH=1,C_PROBE_OUT233_WIDTH=1,C_PROBE_OUT234_WIDTH=1,C_PROBE_OUT235_WIDTH=1,C_PROBE_OUT236_WIDTH=1,C_PROBE_OUT237_WIDTH=1,C_PROBE_OUT238_WIDTH=1,C_PROBE_OUT239_WIDTH=1,C_PROBE_OUT240_WIDTH=1,C_PROBE_OUT241_WIDTH=1,C_PROBE_OUT242_WIDTH=1,C_PROBE_OUT243_WIDTH=1,C_PROBE_OUT244_WIDTH=1,C_PROBE_OUT245_WIDTH=1,C_PROBE_OUT246_WIDTH=1,C_PROBE_OUT247_WIDTH=1,C_PROBE_OUT248_WIDTH=1,C_PROBE_OUT249_WIDTH=1,C_PROBE_OUT250_WIDTH=1,C_PROBE_OUT251_WIDTH=1,C_PROBE_OUT252_WIDTH=1,C_PROBE_OUT253_WIDTH=1,C_PROBE_OUT254_WIDTH=1,C_PROBE_OUT255_WIDTH=1,C_PROBE_OUT0_INIT_VAL=0x0,C_PROBE_OUT1_INIT_VAL=0,C_PROBE_OUT2_INIT_VAL=0,C_PROBE_OUT3_INIT_VAL=0,C_PROBE_OUT4_INIT_VAL=0,C_PROBE_OUT5_INIT_VAL=0,C_PROBE_OUT6_INIT_VAL=0,C_PROBE_OUT7_INIT_VAL=0,C_PROBE_OUT8_INIT_VAL=0,C_PROBE_OUT9_INIT_VAL=0,C_PROBE_OUT10_INIT_VAL=0,C_PROBE_OUT11_INIT_VAL=0,C_PROBE_OUT12_INIT_VAL=0,C_PROBE_OUT13_INIT_VAL=0,C_PROBE_OUT14_INIT_VAL=0,C_PROBE_OUT15_INIT_VAL=0,C_PROBE_OUT16_INIT_VAL=0,C_PROBE_OUT17_INIT_VAL=0,C_PROBE_OUT18_INIT_VAL=0,C_PROBE_OUT19_INIT_VAL=0,C_PROBE_OUT20_INIT_VAL=0,C_PROBE_OUT21_INIT_VAL=0,C_PROBE_OUT22_INIT_VAL=0,C_PROBE_OUT23_INIT_VAL=0,C_PROBE_OUT24_INIT_VAL=0,C_PROBE_OUT25_INIT_VAL=0,C_PROBE_OUT26_INIT_VAL=0,C_PROBE_OUT27_INIT_VAL=0,C_PROBE_OUT28_INIT_VAL=0,C_PROBE_OUT29_INIT_VAL=0,C_PROBE_OUT30_INIT_VAL=0,C_PROBE_OUT31_INIT_VAL=0,C_PROBE_OUT32_INIT_VAL=0,C_PROBE_OUT33_INIT_VAL=0,C_PROBE_OUT34_INIT_VAL=0,C_PROBE_OUT35_INIT_VAL=0,C_PROBE_OUT36_INIT_VAL=0,C_PROBE_OUT37_INIT_VAL=0,C_PROBE_OUT38_INIT_VAL=0,C_PROBE_OUT39_INIT_VAL=0,C_PROBE_OUT40_INIT_VAL=0,C_PROBE_OUT41_INIT_VAL=0,C_PROBE_OUT42_INIT_VAL=0,C_PROBE_OUT43_INIT_VAL=0,C_PROBE_OUT44_INIT_VAL=0,C_PROBE_OUT45_INIT_VAL=0,C_PROBE_OUT46_INIT_VAL=0,C_PROBE_OUT47_INIT_VAL=0,C_PROBE_OUT48_INIT_VAL=0,C_PROBE_OUT49_INIT_VAL=0,C_PROBE_OUT50_INIT_VAL=0,C_PROBE_OUT51_INIT_VAL=0,C_PROBE_OUT52_INIT_VAL=0,C_PROBE_OUT53_INIT_VAL=0,C_PROBE_OUT54_INIT_VAL=0,C_PROBE_OUT55_INIT_VAL=0,C_PROBE_OUT56_INIT_VAL=0,C_PROBE_OUT57_INIT_VAL=0,C_PROBE_OUT58_INIT_VAL=0,C_PROBE_OUT59_INIT_VAL=0,C_PROBE_OUT60_INIT_VAL=0,\
-C_PROBE_OUT61_INIT_VAL=0,C_PROBE_OUT62_INIT_VAL=0,C_PROBE_OUT63_INIT_VAL=0,C_PROBE_OUT64_INIT_VAL=0,C_PROBE_OUT65_INIT_VAL=0,C_PROBE_OUT66_INIT_VAL=0,C_PROBE_OUT67_INIT_VAL=0,C_PROBE_OUT68_INIT_VAL=0,C_PROBE_OUT69_INIT_VAL=0,C_PROBE_OUT70_INIT_VAL=0,C_PROBE_OUT71_INIT_VAL=0,C_PROBE_OUT72_INIT_VAL=0,C_PROBE_OUT73_INIT_VAL=0,C_PROBE_OUT74_INIT_VAL=0,C_PROBE_OUT75_INIT_VAL=0,C_PROBE_OUT76_INIT_VAL=0,C_PROBE_OUT77_INIT_VAL=0,C_PROBE_OUT78_INIT_VAL=0,C_PROBE_OUT79_INIT_VAL=0,C_PROBE_OUT80_INIT_VAL=0,C_PROBE_OUT81_INIT_VAL=0,C_PROBE_OUT82_INIT_VAL=0,C_PROBE_OUT83_INIT_VAL=0,C_PROBE_OUT84_INIT_VAL=0,C_PROBE_OUT85_INIT_VAL=0,C_PROBE_OUT86_INIT_VAL=0,C_PROBE_OUT87_INIT_VAL=0,C_PROBE_OUT88_INIT_VAL=0,C_PROBE_OUT89_INIT_VAL=0,C_PROBE_OUT90_INIT_VAL=0,C_PROBE_OUT91_INIT_VAL=0,C_PROBE_OUT92_INIT_VAL=0,C_PROBE_OUT93_INIT_VAL=0,C_PROBE_OUT94_INIT_VAL=0,C_PROBE_OUT95_INIT_VAL=0,C_PROBE_OUT96_INIT_VAL=0,C_PROBE_OUT97_INIT_VAL=0,C_PROBE_OUT98_INIT_VAL=0,C_PROBE_OUT99_INIT_VAL=0,C_PROBE_OUT100_INIT_VAL=0,C_PROBE_OUT101_INIT_VAL=0,C_PROBE_OUT102_INIT_VAL=0,C_PROBE_OUT103_INIT_VAL=0,C_PROBE_OUT104_INIT_VAL=0,C_PROBE_OUT105_INIT_VAL=0,C_PROBE_OUT106_INIT_VAL=0,C_PROBE_OUT107_INIT_VAL=0,C_PROBE_OUT108_INIT_VAL=0,C_PROBE_OUT109_INIT_VAL=0,C_PROBE_OUT110_INIT_VAL=0,C_PROBE_OUT111_INIT_VAL=0,C_PROBE_OUT112_INIT_VAL=0,C_PROBE_OUT113_INIT_VAL=0,C_PROBE_OUT114_INIT_VAL=0,C_PROBE_OUT115_INIT_VAL=0,C_PROBE_OUT116_INIT_VAL=0,C_PROBE_OUT117_INIT_VAL=0,C_PROBE_OUT118_INIT_VAL=0,C_PROBE_OUT119_INIT_VAL=0,C_PROBE_OUT120_INIT_VAL=0,C_PROBE_OUT121_INIT_VAL=0,C_PROBE_OUT122_INIT_VAL=0,C_PROBE_OUT123_INIT_VAL=0,C_PROBE_OUT124_INIT_VAL=0,C_PROBE_OUT125_INIT_VAL=0,C_PROBE_OUT126_INIT_VAL=0,C_PROBE_OUT127_INIT_VAL=0,C_PROBE_OUT128_INIT_VAL=0,C_PROBE_OUT129_INIT_VAL=0,C_PROBE_OUT130_INIT_VAL=0,C_PROBE_OUT131_INIT_VAL=0,C_PROBE_OUT132_INIT_VAL=0,C_PROBE_OUT133_INIT_VAL=0,C_PROBE_OUT134_INIT_VAL=0,C_PROBE_OUT135_INIT_VAL=0,C_PROBE_OUT136_INIT_VAL=0,C_PROBE_OUT137_INIT_VAL=0,C_PROBE_OUT138_INIT_VAL=0,C_PROBE_OUT139_INIT_VAL=0,C_PROBE_OUT140_INIT_VAL=0,C_PROBE_OUT141_INIT_VAL=0,C_PROBE_OUT142_INIT_VAL=0,C_PROBE_OUT143_INIT_VAL=0,C_PROBE_OUT144_INIT_VAL=0,C_PROBE_OUT145_INIT_VAL=0,C_PROBE_OUT146_INIT_VAL=0,C_PROBE_OUT147_INIT_VAL=0,C_PROBE_OUT148_INIT_VAL=0,C_PROBE_OUT149_INIT_VAL=0,C_PROBE_OUT150_INIT_VAL=0,C_PROBE_OUT151_INIT_VAL=0,C_PROBE_OUT152_INIT_VAL=0,C_PROBE_OUT153_INIT_VAL=0,C_PROBE_OUT154_INIT_VAL=0,C_PROBE_OUT155_INIT_VAL=0,C_PROBE_OUT156_INIT_VAL=0,C_PROBE_OUT157_INIT_VAL=0,C_PROBE_OUT158_INIT_VAL=0,C_PROBE_OUT159_INIT_VAL=0,C_PROBE_OUT160_INIT_VAL=0,\
-C_PROBE_OUT161_INIT_VAL=0,C_PROBE_OUT162_INIT_VAL=0,C_PROBE_OUT163_INIT_VAL=0,C_PROBE_OUT164_INIT_VAL=0,C_PROBE_OUT165_INIT_VAL=0,C_PROBE_OUT166_INIT_VAL=0,C_PROBE_OUT167_INIT_VAL=0,C_PROBE_OUT168_INIT_VAL=0,C_PROBE_OUT169_INIT_VAL=0,C_PROBE_OUT170_INIT_VAL=0,C_PROBE_OUT171_INIT_VAL=0,C_PROBE_OUT172_INIT_VAL=0,C_PROBE_OUT173_INIT_VAL=0,C_PROBE_OUT174_INIT_VAL=0,C_PROBE_OUT175_INIT_VAL=0,C_PROBE_OUT176_INIT_VAL=0,C_PROBE_OUT177_INIT_VAL=0,C_PROBE_OUT178_INIT_VAL=0,C_PROBE_OUT179_INIT_VAL=0,C_PROBE_OUT180_INIT_VAL=0,C_PROBE_OUT181_INIT_VAL=0,C_PROBE_OUT182_INIT_VAL=0,C_PROBE_OUT183_INIT_VAL=0,C_PROBE_OUT184_INIT_VAL=0,C_PROBE_OUT185_INIT_VAL=0,C_PROBE_OUT186_INIT_VAL=0,C_PROBE_OUT187_INIT_VAL=0,C_PROBE_OUT188_INIT_VAL=0,C_PROBE_OUT189_INIT_VAL=0,C_PROBE_OUT190_INIT_VAL=0,C_PROBE_OUT191_INIT_VAL=0,C_PROBE_OUT192_INIT_VAL=0,C_PROBE_OUT193_INIT_VAL=0,C_PROBE_OUT194_INIT_VAL=0,C_PROBE_OUT195_INIT_VAL=0,C_PROBE_OUT196_INIT_VAL=0,C_PROBE_OUT197_INIT_VAL=0,C_PROBE_OUT198_INIT_VAL=0,C_PROBE_OUT199_INIT_VAL=0,C_PROBE_OUT200_INIT_VAL=0,C_PROBE_OUT201_INIT_VAL=0,C_PROBE_OUT202_INIT_VAL=0,C_PROBE_OUT203_INIT_VAL=0,C_PROBE_OUT204_INIT_VAL=0,C_PROBE_OUT205_INIT_VAL=0,C_PROBE_OUT206_INIT_VAL=0,C_PROBE_OUT207_INIT_VAL=0,C_PROBE_OUT208_INIT_VAL=0,C_PROBE_OUT209_INIT_VAL=0,C_PROBE_OUT210_INIT_VAL=0,C_PROBE_OUT211_INIT_VAL=0,C_PROBE_OUT212_INIT_VAL=0,C_PROBE_OUT213_INIT_VAL=0,C_PROBE_OUT214_INIT_VAL=0,C_PROBE_OUT215_INIT_VAL=0,C_PROBE_OUT216_INIT_VAL=0,C_PROBE_OUT217_INIT_VAL=0,C_PROBE_OUT218_INIT_VAL=0,C_PROBE_OUT219_INIT_VAL=0,C_PROBE_OUT220_INIT_VAL=0,C_PROBE_OUT221_INIT_VAL=0,C_PROBE_OUT222_INIT_VAL=0,C_PROBE_OUT223_INIT_VAL=0,C_PROBE_OUT224_INIT_VAL=0,C_PROBE_OUT225_INIT_VAL=0,C_PROBE_OUT226_INIT_VAL=0,C_PROBE_OUT227_INIT_VAL=0,C_PROBE_OUT228_INIT_VAL=0,C_PROBE_OUT229_INIT_VAL=0,C_PROBE_OUT230_INIT_VAL=0,C_PROBE_OUT231_INIT_VAL=0,C_PROBE_OUT232_INIT_VAL=0,C_PROBE_OUT233_INIT_VAL=0,C_PROBE_OUT234_INIT_VAL=0,C_PROBE_OUT235_INIT_VAL=0,C_PROBE_OUT236_INIT_VAL=0,C_PROBE_OUT237_INIT_VAL=0,C_PROBE_OUT238_INIT_VAL=0,C_PROBE_OUT239_INIT_VAL=0,C_PROBE_OUT240_INIT_VAL=0,C_PROBE_OUT241_INIT_VAL=0,C_PROBE_OUT242_INIT_VAL=0,C_PROBE_OUT243_INIT_VAL=0,C_PROBE_OUT244_INIT_VAL=0,C_PROBE_OUT245_INIT_VAL=0,C_PROBE_OUT246_INIT_VAL=0,C_PROBE_OUT247_INIT_VAL=0,C_PROBE_OUT248_INIT_VAL=0,C_PROBE_OUT249_INIT_VAL=0,C_PROBE_OUT250_INIT_VAL=0,C_PROBE_OUT251_INIT_VAL=0,C_PROBE_OUT252_INIT_VAL=0,C_PROBE_OUT253_INIT_VAL=0,C_PROBE_OUT254_INIT_VAL=0,C_PROBE_OUT255_INIT_VAL=0}" *)
-module scalp_zynqps_vio_0_0 (
-clk,
-
-probe_out0
-);
-
-input clk;
-
-output [0 : 0] probe_out0;
-
-
-wire [16:0] sl_oport0;
-wire [36:0] sl_iport0;
-
-vio_v3_0_19_vio #(
-.C_XLNX_HW_PROBE_INFO("DEFAULT"),
-.C_XDEVICEFAMILY("zynq"),
-.C_CORE_TYPE(2),
-.C_CORE_INFO1(0),
-.C_CORE_INFO2(0),
-.C_NUM_PROBE_IN(0),
-.C_EN_PROBE_IN_ACTIVITY(0),
-.C_NUM_PROBE_OUT(1),
-.C_MAJOR_VERSION(2013),
-.C_MINOR_VERSION(1),
-.C_BUILD_REVISION(0),
-.C_CORE_MAJOR_VER(2),
-.C_CORE_MINOR_VER(0),
-.C_CORE_MINOR_ALPHA_VER(97),
-.C_XSDB_SLAVE_TYPE(33),
-.C_NEXT_SLAVE(0),
-.C_CSE_DRV_VER(1),
-.C_USE_TEST_REG(1),
-.C_PIPE_IFACE(0),
-.C_PROBE_IN0_WIDTH(1),
-.C_PROBE_IN1_WIDTH(1),
-.C_PROBE_IN2_WIDTH(1),
-.C_PROBE_IN3_WIDTH(1),
-.C_PROBE_IN4_WIDTH(1),
-.C_PROBE_IN5_WIDTH(1),
-.C_PROBE_IN6_WIDTH(1),
-.C_PROBE_IN7_WIDTH(1),
-.C_PROBE_IN8_WIDTH(1),
-.C_PROBE_IN9_WIDTH(1),
-.C_PROBE_IN10_WIDTH(1),
-.C_PROBE_IN11_WIDTH(1),
-.C_PROBE_IN12_WIDTH(1),
-.C_PROBE_IN13_WIDTH(1),
-.C_PROBE_IN14_WIDTH(1),
-.C_PROBE_IN15_WIDTH(1),
-.C_PROBE_IN16_WIDTH(1),
-.C_PROBE_IN17_WIDTH(1),
-.C_PROBE_IN18_WIDTH(1),
-.C_PROBE_IN19_WIDTH(1),
-.C_PROBE_IN20_WIDTH(1),
-.C_PROBE_IN21_WIDTH(1),
-.C_PROBE_IN22_WIDTH(1),
-.C_PROBE_IN23_WIDTH(1),
-.C_PROBE_IN24_WIDTH(1),
-.C_PROBE_IN25_WIDTH(1),
-.C_PROBE_IN26_WIDTH(1),
-.C_PROBE_IN27_WIDTH(1),
-.C_PROBE_IN28_WIDTH(1),
-.C_PROBE_IN29_WIDTH(1),
-.C_PROBE_IN30_WIDTH(1),
-.C_PROBE_IN31_WIDTH(1),
-.C_PROBE_IN32_WIDTH(1),
-.C_PROBE_IN33_WIDTH(1),
-.C_PROBE_IN34_WIDTH(1),
-.C_PROBE_IN35_WIDTH(1),
-.C_PROBE_IN36_WIDTH(1),
-.C_PROBE_IN37_WIDTH(1),
-.C_PROBE_IN38_WIDTH(1),
-.C_PROBE_IN39_WIDTH(1),
-.C_PROBE_IN40_WIDTH(1),
-.C_PROBE_IN41_WIDTH(1),
-.C_PROBE_IN42_WIDTH(1),
-.C_PROBE_IN43_WIDTH(1),
-.C_PROBE_IN44_WIDTH(1),
-.C_PROBE_IN45_WIDTH(1),
-.C_PROBE_IN46_WIDTH(1),
-.C_PROBE_IN47_WIDTH(1),
-.C_PROBE_IN48_WIDTH(1),
-.C_PROBE_IN49_WIDTH(1),
-.C_PROBE_IN50_WIDTH(1),
-.C_PROBE_IN51_WIDTH(1),
-.C_PROBE_IN52_WIDTH(1),
-.C_PROBE_IN53_WIDTH(1),
-.C_PROBE_IN54_WIDTH(1),
-.C_PROBE_IN55_WIDTH(1),
-.C_PROBE_IN56_WIDTH(1),
-.C_PROBE_IN57_WIDTH(1),
-.C_PROBE_IN58_WIDTH(1),
-.C_PROBE_IN59_WIDTH(1),
-.C_PROBE_IN60_WIDTH(1),
-.C_PROBE_IN61_WIDTH(1),
-.C_PROBE_IN62_WIDTH(1),
-.C_PROBE_IN63_WIDTH(1),
-.C_PROBE_IN64_WIDTH(1),
-.C_PROBE_IN65_WIDTH(1),
-.C_PROBE_IN66_WIDTH(1),
-.C_PROBE_IN67_WIDTH(1),
-.C_PROBE_IN68_WIDTH(1),
-.C_PROBE_IN69_WIDTH(1),
-.C_PROBE_IN70_WIDTH(1),
-.C_PROBE_IN71_WIDTH(1),
-.C_PROBE_IN72_WIDTH(1),
-.C_PROBE_IN73_WIDTH(1),
-.C_PROBE_IN74_WIDTH(1),
-.C_PROBE_IN75_WIDTH(1),
-.C_PROBE_IN76_WIDTH(1),
-.C_PROBE_IN77_WIDTH(1),
-.C_PROBE_IN78_WIDTH(1),
-.C_PROBE_IN79_WIDTH(1),
-.C_PROBE_IN80_WIDTH(1),
-.C_PROBE_IN81_WIDTH(1),
-.C_PROBE_IN82_WIDTH(1),
-.C_PROBE_IN83_WIDTH(1),
-.C_PROBE_IN84_WIDTH(1),
-.C_PROBE_IN85_WIDTH(1),
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-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/122e/hdl/xsdbs_v1_0_vl_rfs.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/122e/hdl/xsdbs_v1_0_vl_rfs.v
deleted file mode 100755
index 7a52987bb7301bf598f0a1c4b8582fbf8aea8feb..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/122e/hdl/xsdbs_v1_0_vl_rfs.v
+++ /dev/null
@@ -1,520 +0,0 @@
-`pragma protect begin_protected
-`pragma protect version = 1
-`pragma protect encrypt_agent = "XILINX"
-`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
-`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
-`pragma protect key_block
-MXx6522AObP5IFTlcIuVM7G10F3elAm2A9QyBFfQrckMYdW7hITs7EoK45w7tw8ydIgMKTNM3VDh
-HMs+Frb7/w==
-
-`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
-IjtXJiULbpa4PJS66fGgQJdnq9Y0Akm7HynNL6VoqZokVHBLnHwCrOpYBv7bgFeWiLxzZb4u9MJX
-abgPdfEsnKt6xr/fn1X32aoiN7t8YwUq3V19+tFlnPO1LwwDx32Uj5NvsZ+RGag7N/mAgcoGj4+W
-d0/yikxyJH/TLTO0JGA=
-
-`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-awSFbPsaEkuNTPX3e3XmHIHkUHd5qkZSzlbsJw==
-
-`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-T02edPx2z4XpOPNEXEARABxwiA+7eOB9vCm9vQ==
-
-`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-8Cx5DZn7Y0gv5YCHf45pM/tr5jed7+NkcBD1uw==
-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-LnbGMzcWnzKUb/GwyrY=
-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-PFKnWHNOJJk4xK0C8EO/P0oodmosD1wA3+b1yg==
-
-`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-SqJzQEzaRwqFbzhIrGQW8S0/DZM6dXunKcChTg==
-
-`pragma protect data_method = "AES128-CBC"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 25472)
-`pragma protect data_block
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-6oRfg+nkEHAqyrpSjp8Dfz2XmzV/f6I9u8XDqDWlqWx0dpeLgtGwGBIFeQe6J9CQEqg=
-`pragma protect end_protected
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/1b7e/hdl/ltlib_v1_0_vl_rfs.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/1b7e/hdl/ltlib_v1_0_vl_rfs.v
deleted file mode 100755
index 9e91dcafbd35dc4b8186c677c2b475e371ea0d0e..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/1b7e/hdl/ltlib_v1_0_vl_rfs.v
+++ /dev/null
@@ -1,1209 +0,0 @@
-`pragma protect begin_protected
-`pragma protect version = 1
-`pragma protect encrypt_agent = "XILINX"
-`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
-`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
-`pragma protect key_block
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-zWeLHFkLlw==
-
-`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-llGPC/3pse6qVTL916Zj/z2XgpkgyjUidf943g==
-
-`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect data_method = "AES128-CBC"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64736)
-`pragma protect data_block
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-`pragma protect end_protected
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v
deleted file mode 100755
index 9c42c12bd6b553f503271146e7daf3b4de52df64..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v
+++ /dev/null
@@ -1,80 +0,0 @@
-`timescale 1ns / 1ps
-/*
--------------------------------------------------------------------------------
--- $Id: util_vector_logic.v 2.0 2017/01/01
--------------------------------------------------------------------------------
---
--- ***************************************************************************
--- ** Copyright(C) 2017 by Xilinx, Inc. All rights reserved. **
--- ** **
--- ** This text contains proprietary, confidential **
--- ** information of Xilinx, Inc. , is distributed by **
--- ** under license from Xilinx, Inc., and may be used, **
--- ** copied and/or disclosed only pursuant to the terms **
--- ** of a valid license agreement with Xilinx, Inc. **
--- ** **
--- ** Unmodified source code is guaranteed to place and route, **
--- ** function and run at speed according to the datasheet **
--- ** specification. Source code is provided "as-is", with no **
--- ** obligation on the part of Xilinx to provide support. **
--- ** **
--- ** Xilinx Hotline support of source code IP shall only include **
--- ** standard level Xilinx Hotline support, and will only address **
--- ** issues and questions related to the standard released Netlist **
--- ** version of the core (and thus indirectly, the original core source). **
--- ** **
--- ** The Xilinx Support Hotline does not have access to source **
--- ** code and therefore cannot answer specific questions related **
--- ** to source HDL. The Xilinx Support Hotline will only be able **
--- ** to confirm the problem in the Netlist version of the core. **
--- ** **
--- ** This copyright and support notice must be retained as part **
--- ** of this text at all times. **
--- ***************************************************************************
---
--------------------------------------------------------------------------------
--- Filename: util_vector_logic.v
---
--- Description:
---
--- Verilog-Standard:
--------------------------------------------------------------------------------
-*/
-
-
-module util_vector_logic_v2_0_1_util_vector_logic ( Op1, Op2, Res);
-
-parameter C_OPERATION = "and";
-parameter integer C_SIZE = 8;
-
-input [C_SIZE - 1:0] Op1;
-input [C_SIZE - 1:0] Op2;
-output [C_SIZE - 1:0] Res;
-
-//wire [C_SIZE - 1:0] Res;
-//parameter C_Oper = C_OPERATION;
-
-generate if (C_OPERATION == "and") begin: GEN_AND_OP
- assign Res = Op1 & Op2;
-end
-endgenerate
-
-generate if (C_OPERATION == "or") begin: GEN_OR_OP
- assign Res = Op1 | Op2;
-end
-endgenerate
-
-generate if (C_OPERATION == "xor") begin: GEN_XOR_OP
- assign Res = Op1 ^ Op2;
-end
-endgenerate
-
-generate if (C_OPERATION == "not") begin: GEN_NOT_OP
- assign Res = ~Op1;
-end
-endgenerate
-
-endmodule // module util_vector_logic
-
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_apis.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_apis.v
deleted file mode 100755
index 6cc9738a850ee340fc4f6f92680fea5b8665478b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_apis.v
+++ /dev/null
@@ -1,842 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_apis.v
- *
- * Date : 2012-11
- *
- * Description : Set of Zynq VIP APIs that are used for writing tests.
- *
- *****************************************************************************/
-
- /* API for setting the STOP_ON_ERROR*/
- task automatic set_stop_on_error;
- input LEVEL;
- begin
- $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
- STOP_ON_ERROR = LEVEL;
-// M_AXI_GP0.master.set_stop_on_error(LEVEL);
-// M_AXI_GP1.master.set_stop_on_error(LEVEL);
-// S_AXI_GP0.slave.set_stop_on_error(LEVEL);
-// S_AXI_GP1.slave.set_stop_on_error(LEVEL);
-// S_AXI_HP0.slave.set_stop_on_error(LEVEL);
-// S_AXI_HP1.slave.set_stop_on_error(LEVEL);
-// S_AXI_HP2.slave.set_stop_on_error(LEVEL);
-// S_AXI_HP3.slave.set_stop_on_error(LEVEL);
-// S_AXI_ACP.slave.set_stop_on_error(LEVEL);
- M_AXI_GP0.STOP_ON_ERROR = LEVEL;
- M_AXI_GP1.STOP_ON_ERROR = LEVEL;
- S_AXI_GP0.STOP_ON_ERROR = LEVEL;
- S_AXI_GP1.STOP_ON_ERROR = LEVEL;
- S_AXI_HP0.STOP_ON_ERROR = LEVEL;
- S_AXI_HP1.STOP_ON_ERROR = LEVEL;
- S_AXI_HP2.STOP_ON_ERROR = LEVEL;
- S_AXI_HP3.STOP_ON_ERROR = LEVEL;
- S_AXI_ACP.STOP_ON_ERROR = LEVEL;
-
- end
- endtask
-
- /* API for setting the verbosity for channel level info*/
- task automatic set_channel_level_info;
- input [1023:0] name;
- input LEVEL;
- begin
- $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL);
- case(name)
-// "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
-// "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
-// "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
-// "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
-// "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
-// "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
-// "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
-// "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
-// "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
- "ALL" : begin
-// M_AXI_GP0.master.set_channel_level_info(LEVEL);
-// M_AXI_GP1.master.set_channel_level_info(LEVEL);
-// S_AXI_GP0.slave.set_channel_level_info(LEVEL);
-// S_AXI_GP1.slave.set_channel_level_info(LEVEL);
-// S_AXI_HP0.slave.set_channel_level_info(LEVEL);
-// S_AXI_HP1.slave.set_channel_level_info(LEVEL);
-// S_AXI_HP2.slave.set_channel_level_info(LEVEL);
-// S_AXI_HP3.slave.set_channel_level_info(LEVEL);
-// S_AXI_ACP.slave.set_channel_level_info(LEVEL);
- end
- default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
- endcase
- end
- endtask
-
- /* API for setting the verbosity for function level info*/
- task automatic set_function_level_info;
- input [1023:0] name;
- input LEVEL;
- begin
- $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL);
- case(name)
-// "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
-// "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
-// "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
-// "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
-// "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
-// "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
-// "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
-// "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
-// "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
- "ALL" : begin
-// M_AXI_GP0.master.set_function_level_info(LEVEL);
-// M_AXI_GP1.master.set_function_level_info(LEVEL);
-// S_AXI_GP0.slave.set_function_level_info(LEVEL);
-// S_AXI_GP1.slave.set_function_level_info(LEVEL);
-// S_AXI_HP0.slave.set_function_level_info(LEVEL);
-// S_AXI_HP1.slave.set_function_level_info(LEVEL);
-// S_AXI_HP2.slave.set_function_level_info(LEVEL);
-// S_AXI_HP3.slave.set_function_level_info(LEVEL);
-// S_AXI_ACP.slave.set_function_level_info(LEVEL);
- end
- default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
- endcase
- end
- endtask
-
- /* API for setting the Message verbosity */
- task automatic set_debug_level_info;
- input LEVEL;
- begin
- $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL);
- DEBUG_INFO = LEVEL;
- M_AXI_GP0.DEBUG_INFO = LEVEL;
- M_AXI_GP1.DEBUG_INFO = LEVEL;
- S_AXI_GP0.DEBUG_INFO = LEVEL;
- S_AXI_GP1.DEBUG_INFO = LEVEL;
- S_AXI_HP0.DEBUG_INFO = LEVEL;
- S_AXI_HP1.DEBUG_INFO = LEVEL;
- S_AXI_HP2.DEBUG_INFO = LEVEL;
- S_AXI_HP3.DEBUG_INFO = LEVEL;
- S_AXI_ACP.DEBUG_INFO = LEVEL;
- end
- endtask
-
- /* API for setting ARQos Values */
- task automatic set_arqos;
- input [1023:0] name;
- input [axi_qos_width-1:0] value;
- begin
- $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value);
- case(name)
- "S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
- "S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
- "S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
- "S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
- "S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
- "S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
- "S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
- default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
- endcase
- end
- endtask
-
- /* API for setting AWQos Values */
- task automatic set_awqos;
- input [1023:0] name;
- input [axi_qos_width-1:0] value;
- begin
- $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value);
- case(name)
- "S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
- "S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
- "S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
- "S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
- "S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
- "S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
- "S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
- default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
- endcase
- end
- endtask
-
- /* API for soft reset control */
- task automatic fpga_soft_reset;
- input[data_width-1:0] reset_ctrl;
- begin
- if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl);
- gen_rst.fpga_soft_reset(reset_ctrl);
- end
- endtask
-
- /* API for por and strb reset control */
-// task automatic por_srstb_reset;
-// input por_reset_ctrl;
-// begin
-// if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO, por_reset_ctrl);
-// // gen_rst.por_srstb_reset(por_reset_ctrl);
-// gen_rst.por_srstb_reset(por_reset_ctrl);
-//
-// end
-// endtask
-
- /* API for pre-loading memories from (DDR/OCM model) */
- task automatic pre_load_mem_from_file;
- input [(max_chars*8)-1:0] file_name;
- input [addr_width-1:0] start_addr;
- input [int_width-1:0] no_of_bytes;
- reg [1:0] mem_type;
- integer succ;
- begin
- mem_type = decode_address(start_addr);
- succ = $fopen(file_name,"r");
- if(succ == 0) begin
- $display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name);
- if(STOP_ON_ERROR) $stop;
- end
- else if(check_addr_aligned(start_addr)) begin
- case(mem_type)
- OCM_MEM : begin
- if (!C_HIGH_OCM_EN)
- ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
- else
- ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
- end
- DDR_MEM : begin
- ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
- end
- default : begin
- $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- endcase
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR)
- $stop;
- end
- end
- endtask
-
- /* API for pre-loading memories (DDR/OCM) */
- task automatic pre_load_mem;
- input [1:0] data_type;
- input [addr_width-1:0] start_addr;
- input [int_width-1:0] no_of_bytes;
- reg [1:0] mem_type;
- begin
- mem_type = decode_address(start_addr);
- if(check_addr_aligned(start_addr)) begin
- case(mem_type)
- OCM_MEM : begin
- if (!C_HIGH_OCM_EN)
- ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes);
- else
- ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
- end
- DDR_MEM : begin
- ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
- end
- default : begin
- $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- endcase
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- end
- endtask
-
- /* API for backdoor write to memories (DDR/OCM) */
- task automatic write_mem;
- input [max_burst_bits-1 :0] data;
- input [addr_width-1:0] start_addr;
- input [max_burst_bytes_width:0] no_of_bytes;
- reg [1:0] mem_type;
- integer succ;
- begin
- mem_type = decode_address(start_addr);
- if(check_addr_aligned(start_addr)) begin
- case(mem_type)
- OCM_MEM : begin
- if (!C_HIGH_OCM_EN)
- ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
- else
- ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes);
- end
- DDR_MEM : begin
- ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
- end
- default : begin
- $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- endcase
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR)
- $stop;
- end
- end
- endtask
-
- /* read_memory */
- task automatic read_mem;
- input [addr_width-1:0] start_addr;
- input [max_burst_bytes_width :0] no_of_bytes;
- output[max_burst_bits-1 :0] data;
- reg [1:0] mem_type;
- integer succ;
- begin
- mem_type = decode_address(start_addr);
- if(check_addr_aligned(start_addr)) begin
- case(mem_type)
- OCM_MEM : begin
- if (!C_HIGH_OCM_EN)
- ocmc.ocm.read_mem(data,start_addr,no_of_bytes);
- else
- ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes);
- end
- DDR_MEM : begin
- ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
- end
- default : begin
- $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- endcase
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR)
- $stop;
- end
- end
- endtask
-
- /* API for backdoor read to memories (DDR/OCM) */
- task automatic peek_mem_to_file;
- input [(max_chars*8)-1:0] file_name;
- input [addr_width-1:0] start_addr;
- input [int_width-1:0] no_of_bytes;
- reg [1:0] mem_type;
- integer succ;
- begin
- mem_type = decode_address(start_addr);
- if(check_addr_aligned(start_addr)) begin
- case(mem_type)
- OCM_MEM : begin
- if (!C_HIGH_OCM_EN)
- ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes);
- else
- ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
- end
- DDR_MEM : begin
- ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
- if(DEBUG_INFO)
- $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
- end
- default : begin
- $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- endcase
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR)
- $stop;
- end
- end
- endtask
-
- /* API to read interrupt status */
- task automatic read_interrupt;
- output[irq_width-1:0] irq_status;
- begin
- irq_status = IRQ_F2P;
- if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status);
- end
- endtask
-
- /* API to wait on interrup */
- task automatic wait_interrupt;
- input [3:0] irq;
- output[irq_width-1:0] irq_status;
- begin
- if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq);
-
- case(irq)
- 0 : wait(IRQ_F2P[0] === 1'b1);
- 1 : wait(IRQ_F2P[1] === 1'b1);
- 2 : wait(IRQ_F2P[2] === 1'b1);
- 3 : wait(IRQ_F2P[3] === 1'b1);
- 4 : wait(IRQ_F2P[4] === 1'b1);
- 5 : wait(IRQ_F2P[5] === 1'b1);
- 6 : wait(IRQ_F2P[6] === 1'b1);
- 7 : wait(IRQ_F2P[7] === 1'b1);
- 8 : wait(IRQ_F2P[8] === 1'b1);
- 9 : wait(IRQ_F2P[9] === 1'b1);
- 10: wait(IRQ_F2P[10] === 1'b1);
- 11: wait(IRQ_F2P[11] === 1'b1);
- 12: wait(IRQ_F2P[12] === 1'b1);
- 13: wait(IRQ_F2P[13] === 1'b1);
- 14: wait(IRQ_F2P[14] === 1'b1);
- 15: wait(IRQ_F2P[15] === 1'b1);
- default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
- endcase
- if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq);
- irq_status = IRQ_F2P;
- end
- endtask
-
- /* API to wait for a certain match pattern*/
- task automatic wait_mem_update;
- input[addr_width-1:0] address;
- input[data_width-1:0] data_in;
- output[data_width-1:0] data_out;
- reg[data_width-1:0] datao;
- begin
- if(mem_update_key) begin
- mem_update_key = 0;
- if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in);
- if(check_addr_aligned(address)) begin
- ddrc.ddr.wait_mem_update(address, datao);
- if(datao != data_in)begin
- $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
- $stop;
- end else
- $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in);
- data_out = datao;
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address);
- if(STOP_ON_ERROR) $stop;
- end
- mem_update_key = 1;
- end else
- $display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
- end
- endtask
-
-
- /* API to initiate a WRITE transaction on one of the AXI-Master ports*/
- task automatic write_from_file;
- input [(max_chars*8)-1:0] file_name;
- input [addr_width-1:0] start_addr;
- input [int_width-1:0] wr_size;
- output [axi_rsp_width-1:0] response;
- integer succ;
- begin
- succ = $fopen(file_name,"r");
- if(succ == 0) begin
- $display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name);
- if(STOP_ON_ERROR) $stop;
- end
- else if(!check_master_address(start_addr)) begin
- $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(check_addr_aligned(start_addr)) begin
- $fclose(succ);
- // case(start_addr[31:30])
- if (start_addr[31:30] === 2'b01) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
- M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
- end else if(start_addr[31:30] === 2'b10) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
- M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
- end else begin
- $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
- end
- // endcase
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- end
- endtask
-
- /* API to initiate a READ transaction on one of the AXI-Master ports*/
- task automatic read_to_file;
- input [(max_chars*8)-1:0] file_name;
- input [addr_width-1:0] start_addr;
- input [int_width-1:0] rd_size;
- output [axi_rsp_width-1:0] response;
- begin
- if(!check_master_address(start_addr)) begin
- $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(check_addr_aligned(start_addr)) begin
- // case(start_addr[31:30])
- if (start_addr[31:30] === 2'b01) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
- M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
- end else if(start_addr[31:30] === 2'b10) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
- M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
- // end
- // default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
- // endcase
- end else begin
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end
- end
- end
- endtask
-
- /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/
- task automatic write_data;
- input [addr_width-1:0] start_addr;
- input [max_transfer_bytes_width:0] wr_size;
- input [(max_transfer_bytes*8)-1:0] w_data;
- output [axi_rsp_width-1:0] response;
- reg[511:0] rsp;
- begin
- if(!check_master_address(start_addr)) begin
- $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(wr_size > max_transfer_bytes) begin
- $display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(start_addr[31:30] === GP_M0) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
- M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else if(start_addr[31:30] === GP_M1) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
- M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else
- $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
- end
- endtask
-
- /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/
- task automatic read_data;
- input [addr_width-1:0] start_addr;
- input [max_transfer_bytes_width:0] rd_size;
- output[(max_transfer_bytes*8)-1:0] rd_data;
- output [axi_rsp_width-1:0] response;
- reg[511:0] rsp;
- begin
- if(!check_master_address(start_addr)) begin
- $display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(rd_size > max_transfer_bytes) begin
- $display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(start_addr[31:30] === GP_M0) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
- M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else if(start_addr[31:30] === GP_M1) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
- M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else
- $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
- end
- endtask
-
-/* Hooks to call to VIP APIs */
- task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
- reg[511:0] rsp;
- begin
- if(!check_master_address(start_addr)) begin
- $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(start_addr[31:30] === 2'b01) begin
- // end else if(start_addr[31:30] === GP_M0) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
- M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else if(start_addr[31:30] === 2'b10) begin
- // end else if(start_addr[31:30] === GP_M1) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
- M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else
- $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr);
- end
- endtask
-
- task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
- reg[511:0] rsp; /// string for response
- begin
- if(!check_master_address(start_addr)) begin
- $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(start_addr[31:30] === 2'b01) begin
- // end else if(start_addr[31:30] === GP_M0) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
- M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else if(start_addr[31:30] === 2'b10) begin
- // end else if(start_addr[31:30] === GP_M1) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
- M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else
- $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr);
- end
- endtask
-
- task automatic read_burst;
- input [addr_width-1:0] start_addr;
- input [axi_len_width-1:0] len;
- input [axi_size_width-1:0] siz;
- input [axi_brst_type_width-1:0] burst;
- input [axi_lock_width-1:0] lck;
- input [axi_cache_width-1:0] cache;
- input [axi_prot_width-1:0] prot;
- output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
- output [(axi_rsp_width*axi_burst_len)-1:0] response;
- reg[511:0] rsp;
- begin
- if(!check_master_address(start_addr)) begin
- $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr);
- if(STOP_ON_ERROR) $stop;
- end else if(start_addr[31:30] === 2'b01) begin
- // end else if(start_addr[31:30] === GP_M0) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
- M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else if(start_addr[31:30] === 2'b10) begin
- // end else if(start_addr[31:30] === GP_M1) begin
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
- M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
- rsp = get_resp(response);
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
- end else
- $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr);
- end
- endtask
-
- task automatic wait_reg_update;
- input [addr_width-1:0] addr;
- input [data_width-1:0] data_i;
- input [data_width-1:0] mask_i;
- input [int_width-1:0] time_interval;
- input [int_width-1:0] time_out;
- output [data_width-1:0] data_o;
-
- reg upd_done0;
- reg upd_done1;
- begin
- if(!check_master_address(addr)) begin
- $display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr);
- if(STOP_ON_ERROR) $stop;
- end else if(addr[31:30] === 2'b01) begin
- // end else if(addr[31:30] === GP_M0) begin
- if(reg_update_key_0) begin
- reg_update_key_0 = 0;
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
- M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
- if(DEBUG_INFO && upd_done0)
- $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
- reg_update_key_0 = 1;
- end else
- $display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
- end else if(addr[31:30] === 2'b10) begin
- // end else if(addr[31:30] === GP_M1) begin
- if(reg_update_key_1) begin
- reg_update_key_1 = 0;
- if(DEBUG_INFO)
- $display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
- M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
- if(DEBUG_INFO && upd_done1)
- $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
- reg_update_key_1 = 1;
- end else
- $display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
- end else
- $display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr);
- end
- endtask
-
-/* API to read register map */
- task read_register_map;
- input [addr_width-1:0] start_addr;
- input [max_regs_width:0] no_of_registers;
- output[max_burst_bits-1 :0] data;
- reg [max_regs_width:0] no_of_regs;
- begin
- no_of_regs = no_of_registers;
- if(no_of_registers > 32) begin
- $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
- no_of_regs = 32;
- end
- if(check_addr_aligned(start_addr)) begin
- if(decode_address(start_addr) == REG_MEM) begin
- if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs );
- regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
- if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data );
- end else begin
- $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
- end
- end else begin
- data = 0;
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
- end
- end
- endtask
-
-/* API to read single register */
- task read_register;
- input [addr_width-1:0] addr;
- output[data_width-1:0] data;
- begin
- if(check_addr_aligned(addr)) begin
- if(decode_address(addr) == REG_MEM) begin
- if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr );
- regc.regm.get_data(addr >> 2, data);
- if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data );
- end else begin
- $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
- end
- end else begin
- data = 0;
- $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
- end
-
- end
- endtask
-
- /* API to set the AXI-Slave profile*/
- task automatic set_slave_profile;
- input[1023:0] name;
- input[1:0] latency ;
- begin
- if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name);
- case(name)
- "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
- "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
- "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
- "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
- "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
- "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
- "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
- "ALL" : begin
- S_AXI_GP0.set_latency_type(latency);
- S_AXI_GP1.set_latency_type(latency);
- S_AXI_HP0.set_latency_type(latency);
- S_AXI_HP1.set_latency_type(latency);
- S_AXI_HP2.set_latency_type(latency);
- S_AXI_HP3.set_latency_type(latency);
- S_AXI_ACP.set_latency_type(latency);
- end
- endcase
- end
- endtask
-
-
-/*------------------------------ LOCAL APIs ------------------------------------------------ */
-
- /* local API for address decoding*/
- function automatic [1:0] decode_address;
- input [addr_width-1:0] address;
- begin
- if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr ))
- decode_address = OCM_MEM; /// OCM
- else if(address >= ddr_start_addr && address <= ddr_end_addr)
- decode_address = DDR_MEM; /// DDR
- else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
- decode_address = OCM_MEM; /// OCM
- else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
- decode_address = REG_MEM; /// Register Map
- else
- decode_address = INVALID_MEM_TYPE; /// ERROR in Address
- end
- endfunction
-
- /* local API for checking address is 32-bit (4-byte) aligned */
- function automatic check_addr_aligned;
- input [addr_width-1:0] address;
- begin
- if((address%4) !=0 ) begin //
- check_addr_aligned = 0; ///not_aligned
- end else
- check_addr_aligned = 1;
- end
- endfunction
-
- /* local API to check address for GP Masters */
- function check_master_address;
- input [addr_width-1:0] address;
- begin
- if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr)
- check_master_address = 1'b1;
- else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr)
- check_master_address = 1'b1;
- else
- check_master_address = 1'b0; /// ERROR in Address
- end
- endfunction
-
- /* Response decode */
- function automatic [511:0] get_resp;
- input[axi_rsp_width-1:0] response;
- begin
- case(response)
- 2'b00 : get_resp = "OKAY";
- 2'b01 : get_resp = "EXOKAY";
- 2'b10 : get_resp = "SLVERR";
- 2'b11 : get_resp = "DECERR";
- endcase
- end
- endfunction
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_acp.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_acp.v
deleted file mode 100755
index 6672bf0ed8a959700e29826ec3d2d59f5346e190..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_acp.v
+++ /dev/null
@@ -1,94 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_axi_acp.v
- *
- * Date : 2012-11
- *
- * Description : Connections for ACP port
- *
- *****************************************************************************/
-
-/* AXI Slave ACP */
- processing_system7_vip_v1_0_8_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
- axi_acp_name, // name
- axi_acp_data_width, // data width
- addr_width, /// address width
- axi_acp_id_width, // ID width
- C_S_AXI_ACP_BASEADDR, // slave base address
- C_S_AXI_ACP_HIGHADDR,// slave size
- axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes
- axi_slv_excl_support, // Exclusive access support
- axi_acp_wr_outstanding,
- axi_acp_rd_outstanding)
- S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
- .S_ACLK (S_AXI_ACP_ACLK),
- // Write Address Channel
- .S_AWID (S_AXI_ACP_AWID),
- .S_AWADDR (S_AXI_ACP_AWADDR),
- .S_AWLEN (S_AXI_ACP_AWLEN),
- .S_AWSIZE (S_AXI_ACP_AWSIZE),
- .S_AWBURST (S_AXI_ACP_AWBURST),
- .S_AWLOCK (S_AXI_ACP_AWLOCK),
- .S_AWCACHE (S_AXI_ACP_AWCACHE),
- .S_AWPROT (S_AXI_ACP_AWPROT),
- .S_AWVALID (S_AXI_ACP_AWVALID),
- .S_AWREADY (S_AXI_ACP_AWREADY),
- // Write Data Channel Signals.
- .S_WID (S_AXI_ACP_WID),
- .S_WDATA (S_AXI_ACP_WDATA),
- .S_WSTRB (S_AXI_ACP_WSTRB),
- .S_WLAST (S_AXI_ACP_WLAST),
- .S_WVALID (S_AXI_ACP_WVALID),
- .S_WREADY (S_AXI_ACP_WREADY),
- // Write Response Channel Signals.
- .S_BID (S_AXI_ACP_BID),
- .S_BRESP (S_AXI_ACP_BRESP),
- .S_BVALID (S_AXI_ACP_BVALID),
- .S_BREADY (S_AXI_ACP_BREADY),
- // Read Address Channel Signals.
- .S_ARID (S_AXI_ACP_ARID),
- .S_ARADDR (S_AXI_ACP_ARADDR),
- .S_ARLEN (S_AXI_ACP_ARLEN),
- .S_ARSIZE (S_AXI_ACP_ARSIZE),
- .S_ARBURST (S_AXI_ACP_ARBURST),
- .S_ARLOCK (S_AXI_ACP_ARLOCK),
- .S_ARCACHE (S_AXI_ACP_ARCACHE),
- .S_ARPROT (S_AXI_ACP_ARPROT),
- .S_ARVALID (S_AXI_ACP_ARVALID),
- .S_ARREADY (S_AXI_ACP_ARREADY),
- // Read Data Channel Signals.
- .S_RID (S_AXI_ACP_RID),
- .S_RDATA (S_AXI_ACP_RDATA),
- .S_RRESP (S_AXI_ACP_RRESP),
- .S_RLAST (S_AXI_ACP_RLAST),
- .S_RVALID (S_AXI_ACP_RVALID),
- .S_RREADY (S_AXI_ACP_RREADY),
- // Side band signals
- .S_AWQOS (S_AXI_ACP_AWQOS),
- .S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals
-
- .SW_CLK (net_sw_clk),
-/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
- .WR_DATA_ACK_DDR (ddr_wr_ack_port0),
- .WR_DATA_ACK_OCM (ocm_wr_ack_port0),
- .WR_DATA (net_wr_data_acp),
- .WR_DATA_STRB (net_wr_strb_acp),
- .WR_ADDR (net_wr_addr_acp),
- .WR_BYTES (net_wr_bytes_acp),
- .WR_DATA_VALID_DDR (ddr_wr_dv_port0),
- .WR_DATA_VALID_OCM (ocm_wr_dv_port0),
- .WR_QOS (net_wr_qos_acp),
-
- .RD_REQ_DDR (ddr_rd_req_port0),
- .RD_REQ_OCM (ocm_rd_req_port0),
- .RD_REQ_REG (reg_rd_req_port0),
- .RD_ADDR (net_rd_addr_acp),
- .RD_DATA_DDR (ddr_rd_data_port0),
- .RD_DATA_OCM (ocm_rd_data_port0),
- .RD_DATA_REG (reg_rd_data_port0),
- .RD_BYTES (net_rd_bytes_acp),
- .RD_DATA_VALID_DDR (ddr_rd_dv_port0),
- .RD_DATA_VALID_OCM (ocm_rd_dv_port0),
- .RD_DATA_VALID_REG (reg_rd_dv_port0),
- .RD_QOS (net_rd_qos_acp)
-
-);
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_gp.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_gp.v
deleted file mode 100755
index 4fedf803673b42cbfed65c2a7c8afe3c6601f792..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_gp.v
+++ /dev/null
@@ -1,311 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_axi_gp.v
- *
- * Date : 2012-11
- *
- * Description : Connections for AXI GP ports
- *
- *****************************************************************************/
-
- /* IDs for Masters
- // l2m1 (CPU000)
- 12'b11_000_000_00_00
- 12'b11_010_000_00_00
- 12'b11_011_000_00_00
- 12'b11_100_000_00_00
- 12'b11_101_000_00_00
- 12'b11_110_000_00_00
- 12'b11_111_000_00_00
- // l2m1 (CPU001)
- 12'b11_000_001_00_00
- 12'b11_010_001_00_00
- 12'b11_011_001_00_00
- 12'b11_100_001_00_00
- 12'b11_101_001_00_00
- 12'b11_110_001_00_00
- 12'b11_111_001_00_00
- */
-
-/* AXI -Master GP0 */
- processing_system7_vip_v1_0_8_axi_master #(C_USE_M_AXI_GP0, // enable
- axi_mgp0_name,// name
- axi_mgp_data_width, /// Data Width
- addr_width, /// Address width
- axi_mgp_id_width, //// ID Width
- axi_mgp_outstanding, //// Outstanding transactions
- axi_mst_excl_support, // EXCL Access Support
- axi_mgp_wr_id, //WR_ID
- axi_mgp_rd_id) //RD_ID
- M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
- .M_ACLK (M_AXI_GP0_ACLK),
- // Write Address Channel
- .M_AWID (M_AXI_GP0_AWID_FULL),
- .M_AWADDR (M_AXI_GP0_AWADDR),
- .M_AWLEN (M_AXI_GP0_AWLEN),
- .M_AWSIZE (M_AXI_GP0_AWSIZE),
- .M_AWBURST (M_AXI_GP0_AWBURST),
- .M_AWLOCK (M_AXI_GP0_AWLOCK),
- .M_AWCACHE (M_AXI_GP0_AWCACHE),
- .M_AWPROT (M_AXI_GP0_AWPROT),
- .M_AWVALID (M_AXI_GP0_AWVALID),
- .M_AWREADY (M_AXI_GP0_AWREADY),
- // Write Data Channel Signals.
- .M_WID (M_AXI_GP0_WID_FULL),
- .M_WDATA (M_AXI_GP0_WDATA),
- .M_WSTRB (M_AXI_GP0_WSTRB),
- .M_WLAST (M_AXI_GP0_WLAST),
- .M_WVALID (M_AXI_GP0_WVALID),
- .M_WREADY (M_AXI_GP0_WREADY),
- // Write Response Channel Signals.
- .M_BID (M_AXI_GP0_BID_FULL),
- .M_BRESP (M_AXI_GP0_BRESP),
- .M_BVALID (M_AXI_GP0_BVALID),
- .M_BREADY (M_AXI_GP0_BREADY),
- // Read Address Channel Signals.
- .M_ARID (M_AXI_GP0_ARID_FULL),
- .M_ARADDR (M_AXI_GP0_ARADDR),
- .M_ARLEN (M_AXI_GP0_ARLEN),
- .M_ARSIZE (M_AXI_GP0_ARSIZE),
- .M_ARBURST (M_AXI_GP0_ARBURST),
- .M_ARLOCK (M_AXI_GP0_ARLOCK),
- .M_ARCACHE (M_AXI_GP0_ARCACHE),
- .M_ARPROT (M_AXI_GP0_ARPROT),
- .M_ARVALID (M_AXI_GP0_ARVALID),
- .M_ARREADY (M_AXI_GP0_ARREADY),
- // Read Data Channel Signals.
- .M_RID (M_AXI_GP0_RID_FULL),
- .M_RDATA (M_AXI_GP0_RDATA),
- .M_RRESP (M_AXI_GP0_RRESP),
- .M_RLAST (M_AXI_GP0_RLAST),
- .M_RVALID (M_AXI_GP0_RVALID),
- .M_RREADY (M_AXI_GP0_RREADY),
- // Side band signals
- .M_AWQOS (M_AXI_GP0_AWQOS),
- .M_ARQOS (M_AXI_GP0_ARQOS)
- );
-
- /* AXI Master GP1 */
- processing_system7_vip_v1_0_8_axi_master #(C_USE_M_AXI_GP1, // enable
- axi_mgp1_name,// name
- axi_mgp_data_width, /// Data Width
- addr_width, /// Address width
- axi_mgp_id_width, //// ID Width
- axi_mgp_outstanding, //// Outstanding transactions
- axi_mst_excl_support, // EXCL Access Support
- axi_mgp_wr_id, //WR_ID
- axi_mgp_rd_id) //RD_ID
- M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
- .M_ACLK (M_AXI_GP1_ACLK),
- // Write Address Channel
- .M_AWID (M_AXI_GP1_AWID_FULL),
- .M_AWADDR (M_AXI_GP1_AWADDR),
- .M_AWLEN (M_AXI_GP1_AWLEN),
- .M_AWSIZE (M_AXI_GP1_AWSIZE),
- .M_AWBURST (M_AXI_GP1_AWBURST),
- .M_AWLOCK (M_AXI_GP1_AWLOCK),
- .M_AWCACHE (M_AXI_GP1_AWCACHE),
- .M_AWPROT (M_AXI_GP1_AWPROT),
- .M_AWVALID (M_AXI_GP1_AWVALID),
- .M_AWREADY (M_AXI_GP1_AWREADY),
- // Write Data Channel Signals.
- .M_WID (M_AXI_GP1_WID_FULL),
- .M_WDATA (M_AXI_GP1_WDATA),
- .M_WSTRB (M_AXI_GP1_WSTRB),
- .M_WLAST (M_AXI_GP1_WLAST),
- .M_WVALID (M_AXI_GP1_WVALID),
- .M_WREADY (M_AXI_GP1_WREADY),
- // Write Response Channel Signals.
- .M_BID (M_AXI_GP1_BID_FULL),
- .M_BRESP (M_AXI_GP1_BRESP),
- .M_BVALID (M_AXI_GP1_BVALID),
- .M_BREADY (M_AXI_GP1_BREADY),
- // Read Address Channel Signals.
- .M_ARID (M_AXI_GP1_ARID_FULL),
- .M_ARADDR (M_AXI_GP1_ARADDR),
- .M_ARLEN (M_AXI_GP1_ARLEN),
- .M_ARSIZE (M_AXI_GP1_ARSIZE),
- .M_ARBURST (M_AXI_GP1_ARBURST),
- .M_ARLOCK (M_AXI_GP1_ARLOCK),
- .M_ARCACHE (M_AXI_GP1_ARCACHE),
- .M_ARPROT (M_AXI_GP1_ARPROT),
- .M_ARVALID (M_AXI_GP1_ARVALID),
- .M_ARREADY (M_AXI_GP1_ARREADY),
- // Read Data Channel Signals.
- .M_RID (M_AXI_GP1_RID_FULL),
- .M_RDATA (M_AXI_GP1_RDATA),
- .M_RRESP (M_AXI_GP1_RRESP),
- .M_RLAST (M_AXI_GP1_RLAST),
- .M_RVALID (M_AXI_GP1_RVALID),
- .M_RREADY (M_AXI_GP1_RREADY),
- // Side band signals
- .M_AWQOS (M_AXI_GP1_AWQOS),
- .M_ARQOS (M_AXI_GP1_ARQOS)
- );
-
-/* AXI Slave GP0 */
- processing_system7_vip_v1_0_8_axi_slave #(C_USE_S_AXI_GP0, /// enable
- axi_sgp0_name, //name
- axi_sgp_data_width, /// data width
- addr_width, /// address width
- axi_sgp_id_width, /// ID width
- C_S_AXI_GP0_BASEADDR,//// base address
- C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr)
- axi_sgp_outstanding, // outstanding transactions
- axi_slv_excl_support, // exclusive access not supported
- axi_sgp_wr_outstanding,
- axi_sgp_rd_outstanding)
- S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
- .S_ACLK (S_AXI_GP0_ACLK),
- // Write Address Channel
- .S_AWID (S_AXI_GP0_AWID),
- .S_AWADDR (S_AXI_GP0_AWADDR),
- .S_AWLEN (S_AXI_GP0_AWLEN),
- .S_AWSIZE (S_AXI_GP0_AWSIZE),
- .S_AWBURST (S_AXI_GP0_AWBURST),
- .S_AWLOCK (S_AXI_GP0_AWLOCK),
- .S_AWCACHE (S_AXI_GP0_AWCACHE),
- .S_AWPROT (S_AXI_GP0_AWPROT),
- .S_AWVALID (S_AXI_GP0_AWVALID),
- .S_AWREADY (S_AXI_GP0_AWREADY),
- // Write Data Channel Signals.
- .S_WID (S_AXI_GP0_WID),
- .S_WDATA (S_AXI_GP0_WDATA),
- .S_WSTRB (S_AXI_GP0_WSTRB),
- .S_WLAST (S_AXI_GP0_WLAST),
- .S_WVALID (S_AXI_GP0_WVALID),
- .S_WREADY (S_AXI_GP0_WREADY),
- // Write Response Channel Signals.
- .S_BID (S_AXI_GP0_BID),
- .S_BRESP (S_AXI_GP0_BRESP),
- .S_BVALID (S_AXI_GP0_BVALID),
- .S_BREADY (S_AXI_GP0_BREADY),
- // Read Address Channel Signals.
- .S_ARID (S_AXI_GP0_ARID),
- .S_ARADDR (S_AXI_GP0_ARADDR),
- .S_ARLEN (S_AXI_GP0_ARLEN),
- .S_ARSIZE (S_AXI_GP0_ARSIZE),
- .S_ARBURST (S_AXI_GP0_ARBURST),
- .S_ARLOCK (S_AXI_GP0_ARLOCK),
- .S_ARCACHE (S_AXI_GP0_ARCACHE),
- .S_ARPROT (S_AXI_GP0_ARPROT),
- .S_ARVALID (S_AXI_GP0_ARVALID),
- .S_ARREADY (S_AXI_GP0_ARREADY),
- // Read Data Channel Signals.
- .S_RID (S_AXI_GP0_RID),
- .S_RDATA (S_AXI_GP0_RDATA),
- .S_RRESP (S_AXI_GP0_RRESP),
- .S_RLAST (S_AXI_GP0_RLAST),
- .S_RVALID (S_AXI_GP0_RVALID),
- .S_RREADY (S_AXI_GP0_RREADY),
- // Side band signals
- .S_AWQOS (S_AXI_GP0_AWQOS),
- .S_ARQOS (S_AXI_GP0_ARQOS),
-
- .SW_CLK (net_sw_clk),
- .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
- .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
- .WR_DATA (net_wr_data_gp0),
- .WR_DATA_STRB (net_wr_strb_gp0),
- .WR_ADDR (net_wr_addr_gp0),
- .WR_BYTES (net_wr_bytes_gp0),
- .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0),
- .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0),
- .WR_QOS (net_wr_qos_gp0),
- .RD_REQ_DDR (net_rd_req_ddr_gp0),
- .RD_REQ_OCM (net_rd_req_ocm_gp0),
- .RD_REQ_REG (net_rd_req_reg_gp0),
- .RD_ADDR (net_rd_addr_gp0),
- .RD_DATA_DDR (net_rd_data_ddr_gp0),
- .RD_DATA_OCM (net_rd_data_ocm_gp0),
- .RD_DATA_REG (net_rd_data_reg_gp0),
- .RD_BYTES (net_rd_bytes_gp0),
- .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
- .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
- .RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
- .RD_QOS (net_rd_qos_gp0)
-
-);
-
-/* AXI Slave GP1 */
- processing_system7_vip_v1_0_8_axi_slave #(C_USE_S_AXI_GP1, /// enable
- axi_sgp1_name, //name
- axi_sgp_data_width, /// data width
- addr_width, /// address width
- axi_sgp_id_width, /// ID width
- C_S_AXI_GP1_BASEADDR,//// base address
- C_S_AXI_GP1_HIGHADDR,/// HIGh_addr
- axi_sgp_outstanding, // outstanding transactions
- axi_slv_excl_support, // exclusive access
- axi_sgp_wr_outstanding,
- axi_sgp_rd_outstanding)
- S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn),
- .S_ACLK (S_AXI_GP1_ACLK),
- // Write Address Channel
- .S_AWID (S_AXI_GP1_AWID),
- .S_AWADDR (S_AXI_GP1_AWADDR),
- .S_AWLEN (S_AXI_GP1_AWLEN),
- .S_AWSIZE (S_AXI_GP1_AWSIZE),
- .S_AWBURST (S_AXI_GP1_AWBURST),
- .S_AWLOCK (S_AXI_GP1_AWLOCK),
- .S_AWCACHE (S_AXI_GP1_AWCACHE),
- .S_AWPROT (S_AXI_GP1_AWPROT),
- .S_AWVALID (S_AXI_GP1_AWVALID),
- .S_AWREADY (S_AXI_GP1_AWREADY),
- // Write Data Channel Signals.
- .S_WID (S_AXI_GP1_WID),
- .S_WDATA (S_AXI_GP1_WDATA),
- .S_WSTRB (S_AXI_GP1_WSTRB),
- .S_WLAST (S_AXI_GP1_WLAST),
- .S_WVALID (S_AXI_GP1_WVALID),
- .S_WREADY (S_AXI_GP1_WREADY),
- // Write Response Channel Signals.
- .S_BID (S_AXI_GP1_BID),
- .S_BRESP (S_AXI_GP1_BRESP),
- .S_BVALID (S_AXI_GP1_BVALID),
- .S_BREADY (S_AXI_GP1_BREADY),
- // Read Address Channel Signals.
- .S_ARID (S_AXI_GP1_ARID),
- .S_ARADDR (S_AXI_GP1_ARADDR),
- .S_ARLEN (S_AXI_GP1_ARLEN),
- .S_ARSIZE (S_AXI_GP1_ARSIZE),
- .S_ARBURST (S_AXI_GP1_ARBURST),
- .S_ARLOCK (S_AXI_GP1_ARLOCK),
- .S_ARCACHE (S_AXI_GP1_ARCACHE),
- .S_ARPROT (S_AXI_GP1_ARPROT),
- .S_ARVALID (S_AXI_GP1_ARVALID),
- .S_ARREADY (S_AXI_GP1_ARREADY),
- // Read Data Channel Signals.
- .S_RID (S_AXI_GP1_RID),
- .S_RDATA (S_AXI_GP1_RDATA),
- .S_RRESP (S_AXI_GP1_RRESP),
- .S_RLAST (S_AXI_GP1_RLAST),
- .S_RVALID (S_AXI_GP1_RVALID),
- .S_RREADY (S_AXI_GP1_RREADY),
- // Side band signals
- .S_AWQOS (S_AXI_GP1_AWQOS),
- .S_ARQOS (S_AXI_GP1_ARQOS),
-
- .SW_CLK (net_sw_clk),
- .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
- .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
- .WR_DATA (net_wr_data_gp1),
- .WR_DATA_STRB (net_wr_strb_gp1),
- .WR_ADDR (net_wr_addr_gp1),
- .WR_BYTES (net_wr_bytes_gp1),
- .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1),
- .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1),
- .WR_QOS (net_wr_qos_gp1),
- .RD_REQ_OCM (net_rd_req_ocm_gp1),
- .RD_REQ_DDR (net_rd_req_ddr_gp1),
- .RD_REQ_REG (net_rd_req_reg_gp1),
- .RD_ADDR (net_rd_addr_gp1),
- .RD_DATA_DDR (net_rd_data_ddr_gp1),
- .RD_DATA_OCM (net_rd_data_ocm_gp1),
- .RD_DATA_REG (net_rd_data_reg_gp1),
- .RD_BYTES (net_rd_bytes_gp1),
- .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
- .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
- .RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
- .RD_QOS (net_rd_qos_gp1)
-
-);
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_hp.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_hp.v
deleted file mode 100755
index a96d4d7646413a646aac757c1bcdc6f8fa542556..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_axi_hp.v
+++ /dev/null
@@ -1,350 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_axi_hp.v
- *
- * Date : 2012-11
- *
- * Description : Connections for AXI HP ports
- *
- *****************************************************************************/
-
-/* AXI Slave HP0 */
- processing_system7_vip_v1_0_8_afi_slave #( C_USE_S_AXI_HP0, // enable
- axi_hp0_name, // name
- C_S_AXI_HP0_DATA_WIDTH, // data width
- addr_width, /// address width
- axi_hp_id_width, // ID width
- C_S_AXI_HP0_BASEADDR, // slave base address
- C_S_AXI_HP0_HIGHADDR, // slave size
- axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
- axi_slv_excl_support) // Exclusive access support
- S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
- .S_ACLK (S_AXI_HP0_ACLK),
- // Write Address channel
- .S_AWID (S_AXI_HP0_AWID),
- .S_AWADDR (S_AXI_HP0_AWADDR),
- .S_AWLEN (S_AXI_HP0_AWLEN),
- .S_AWSIZE (S_AXI_HP0_AWSIZE),
- .S_AWBURST (S_AXI_HP0_AWBURST),
- .S_AWLOCK (S_AXI_HP0_AWLOCK),
- .S_AWCACHE (S_AXI_HP0_AWCACHE),
- .S_AWPROT (S_AXI_HP0_AWPROT),
- .S_AWVALID (S_AXI_HP0_AWVALID),
- .S_AWREADY (S_AXI_HP0_AWREADY),
- // Write Data channel signals.
- .S_WID (S_AXI_HP0_WID),
- .S_WDATA (S_AXI_HP0_WDATA),
- .S_WSTRB (S_AXI_HP0_WSTRB),
- .S_WLAST (S_AXI_HP0_WLAST),
- .S_WVALID (S_AXI_HP0_WVALID),
- .S_WREADY (S_AXI_HP0_WREADY),
- // Write Response channel signals.
- .S_BID (S_AXI_HP0_BID),
- .S_BRESP (S_AXI_HP0_BRESP),
- .S_BVALID (S_AXI_HP0_BVALID),
- .S_BREADY (S_AXI_HP0_BREADY),
- // Read Address channel signals.
- .S_ARID (S_AXI_HP0_ARID),
- .S_ARADDR (S_AXI_HP0_ARADDR),
- .S_ARLEN (S_AXI_HP0_ARLEN),
- .S_ARSIZE (S_AXI_HP0_ARSIZE),
- .S_ARBURST (S_AXI_HP0_ARBURST),
- .S_ARLOCK (S_AXI_HP0_ARLOCK),
- .S_ARCACHE (S_AXI_HP0_ARCACHE),
- .S_ARPROT (S_AXI_HP0_ARPROT),
- .S_ARVALID (S_AXI_HP0_ARVALID),
- .S_ARREADY (S_AXI_HP0_ARREADY),
- // Read Data channel signals.
- .S_RID (S_AXI_HP0_RID),
- .S_RDATA (S_AXI_HP0_RDATA),
- .S_RRESP (S_AXI_HP0_RRESP),
- .S_RLAST (S_AXI_HP0_RLAST),
- .S_RVALID (S_AXI_HP0_RVALID),
- .S_RREADY (S_AXI_HP0_RREADY),
- // Side band signals
- .S_AWQOS (S_AXI_HP0_AWQOS),
- .S_ARQOS (S_AXI_HP0_ARQOS),
- // these are needed only for HP ports
- .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
- .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
- .S_RCOUNT (S_AXI_HP0_RCOUNT),
- .S_WCOUNT (S_AXI_HP0_WCOUNT),
- .S_RACOUNT (S_AXI_HP0_RACOUNT),
- .S_WACOUNT (S_AXI_HP0_WACOUNT),
-
- .SW_CLK (net_sw_clk),
- .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
- .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
- .WR_DATA (net_wr_data_hp0),
- .WR_DATA_STRB (net_wr_strb_hp0),
- .WR_ADDR (net_wr_addr_hp0),
- .WR_BYTES (net_wr_bytes_hp0),
- .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0),
- .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0),
- .WR_QOS (net_wr_qos_hp0),
- .RD_REQ_DDR (net_rd_req_ddr_hp0),
- .RD_REQ_OCM (net_rd_req_ocm_hp0),
- .RD_ADDR (net_rd_addr_hp0),
- .RD_DATA_DDR (net_rd_data_ddr_hp0),
- .RD_DATA_OCM (net_rd_data_ocm_hp0),
- .RD_BYTES (net_rd_bytes_hp0),
- .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
- .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
- .RD_QOS (net_rd_qos_hp0)
- );
-
-/* AXI Slave HP1 */
- processing_system7_vip_v1_0_8_afi_slave #( C_USE_S_AXI_HP1, // enable
- axi_hp1_name, // name
- C_S_AXI_HP1_DATA_WIDTH, // data width
- addr_width, /// address width
- axi_hp_id_width, // ID width
- C_S_AXI_HP1_BASEADDR, // slave base address
- C_S_AXI_HP1_HIGHADDR, // Slave size
- axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
- axi_slv_excl_support) // Exclusive access support
- S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
- .S_ACLK (S_AXI_HP1_ACLK),
- // Write Address channel
- .S_AWID (S_AXI_HP1_AWID),
- .S_AWADDR (S_AXI_HP1_AWADDR),
- .S_AWLEN (S_AXI_HP1_AWLEN),
- .S_AWSIZE (S_AXI_HP1_AWSIZE),
- .S_AWBURST (S_AXI_HP1_AWBURST),
- .S_AWLOCK (S_AXI_HP1_AWLOCK),
- .S_AWCACHE (S_AXI_HP1_AWCACHE),
- .S_AWPROT (S_AXI_HP1_AWPROT),
- .S_AWVALID (S_AXI_HP1_AWVALID),
- .S_AWREADY (S_AXI_HP1_AWREADY),
- // Write Data channel signals.
- .S_WID (S_AXI_HP1_WID),
- .S_WDATA (S_AXI_HP1_WDATA),
- .S_WSTRB (S_AXI_HP1_WSTRB),
- .S_WLAST (S_AXI_HP1_WLAST),
- .S_WVALID (S_AXI_HP1_WVALID),
- .S_WREADY (S_AXI_HP1_WREADY),
- // Write Response channel signals.
- .S_BID (S_AXI_HP1_BID),
- .S_BRESP (S_AXI_HP1_BRESP),
- .S_BVALID (S_AXI_HP1_BVALID),
- .S_BREADY (S_AXI_HP1_BREADY),
- // Read Address channel signals.
- .S_ARID (S_AXI_HP1_ARID),
- .S_ARADDR (S_AXI_HP1_ARADDR),
- .S_ARLEN (S_AXI_HP1_ARLEN),
- .S_ARSIZE (S_AXI_HP1_ARSIZE),
- .S_ARBURST (S_AXI_HP1_ARBURST),
- .S_ARLOCK (S_AXI_HP1_ARLOCK),
- .S_ARCACHE (S_AXI_HP1_ARCACHE),
- .S_ARPROT (S_AXI_HP1_ARPROT),
- .S_ARVALID (S_AXI_HP1_ARVALID),
- .S_ARREADY (S_AXI_HP1_ARREADY),
- // Read Data channel signals.
- .S_RID (S_AXI_HP1_RID),
- .S_RDATA (S_AXI_HP1_RDATA),
- .S_RRESP (S_AXI_HP1_RRESP),
- .S_RLAST (S_AXI_HP1_RLAST),
- .S_RVALID (S_AXI_HP1_RVALID),
- .S_RREADY (S_AXI_HP1_RREADY),
- // Side band signals
- .S_AWQOS (S_AXI_HP1_AWQOS),
- .S_ARQOS (S_AXI_HP1_ARQOS),
- // these are needed only for HP ports
- .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
- .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
- .S_RCOUNT (S_AXI_HP1_RCOUNT),
- .S_WCOUNT (S_AXI_HP1_WCOUNT),
- .S_RACOUNT (S_AXI_HP1_RACOUNT),
- .S_WACOUNT (S_AXI_HP1_WACOUNT),
-
- .SW_CLK (net_sw_clk),
- .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
- .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
- .WR_DATA (net_wr_data_hp1),
- .WR_DATA_STRB (net_wr_strb_hp1),
- .WR_ADDR (net_wr_addr_hp1),
- .WR_BYTES (net_wr_bytes_hp1),
- .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1),
- .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1),
- .WR_QOS (net_wr_qos_hp1),
- .RD_REQ_DDR (net_rd_req_ddr_hp1),
- .RD_REQ_OCM (net_rd_req_ocm_hp1),
- .RD_ADDR (net_rd_addr_hp1),
- .RD_DATA_DDR (net_rd_data_ddr_hp1),
- .RD_DATA_OCM (net_rd_data_ocm_hp1),
- .RD_BYTES (net_rd_bytes_hp1),
- .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
- .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
- .RD_QOS (net_rd_qos_hp1)
-
- );
-
-/* AXI Slave HP2 */
- processing_system7_vip_v1_0_8_afi_slave #( C_USE_S_AXI_HP2, // enable
- axi_hp2_name, // name
- C_S_AXI_HP2_DATA_WIDTH, // data width
- addr_width, /// address width
- axi_hp_id_width, // ID width
- C_S_AXI_HP2_BASEADDR, // slave base address
- C_S_AXI_HP2_HIGHADDR, // SLave size
- axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
- axi_slv_excl_support) // Exclusive access support
- S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
- .S_ACLK (S_AXI_HP2_ACLK),
- // Write Address channel
- .S_AWID (S_AXI_HP2_AWID),
- .S_AWADDR (S_AXI_HP2_AWADDR),
- .S_AWLEN (S_AXI_HP2_AWLEN),
- .S_AWSIZE (S_AXI_HP2_AWSIZE),
- .S_AWBURST (S_AXI_HP2_AWBURST),
- .S_AWLOCK (S_AXI_HP2_AWLOCK),
- .S_AWCACHE (S_AXI_HP2_AWCACHE),
- .S_AWPROT (S_AXI_HP2_AWPROT),
- .S_AWVALID (S_AXI_HP2_AWVALID),
- .S_AWREADY (S_AXI_HP2_AWREADY),
- // Write Data channel signals.
- .S_WID (S_AXI_HP2_WID),
- .S_WDATA (S_AXI_HP2_WDATA),
- .S_WSTRB (S_AXI_HP2_WSTRB),
- .S_WLAST (S_AXI_HP2_WLAST),
- .S_WVALID (S_AXI_HP2_WVALID),
- .S_WREADY (S_AXI_HP2_WREADY),
- // Write Response channel signals.
- .S_BID (S_AXI_HP2_BID),
- .S_BRESP (S_AXI_HP2_BRESP),
- .S_BVALID (S_AXI_HP2_BVALID),
- .S_BREADY (S_AXI_HP2_BREADY),
- // Read Address channel signals.
- .S_ARID (S_AXI_HP2_ARID),
- .S_ARADDR (S_AXI_HP2_ARADDR),
- .S_ARLEN (S_AXI_HP2_ARLEN),
- .S_ARSIZE (S_AXI_HP2_ARSIZE),
- .S_ARBURST (S_AXI_HP2_ARBURST),
- .S_ARLOCK (S_AXI_HP2_ARLOCK),
- .S_ARCACHE (S_AXI_HP2_ARCACHE),
- .S_ARPROT (S_AXI_HP2_ARPROT),
- .S_ARVALID (S_AXI_HP2_ARVALID),
- .S_ARREADY (S_AXI_HP2_ARREADY),
- // Read Data channel signals.
- .S_RID (S_AXI_HP2_RID),
- .S_RDATA (S_AXI_HP2_RDATA),
- .S_RRESP (S_AXI_HP2_RRESP),
- .S_RLAST (S_AXI_HP2_RLAST),
- .S_RVALID (S_AXI_HP2_RVALID),
- .S_RREADY (S_AXI_HP2_RREADY),
- // Side band signals
- .S_AWQOS (S_AXI_HP2_AWQOS),
- .S_ARQOS (S_AXI_HP2_ARQOS),
- // these are needed only for HP ports
- .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
- .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
- .S_RCOUNT (S_AXI_HP2_RCOUNT),
- .S_WCOUNT (S_AXI_HP2_WCOUNT),
- .S_RACOUNT (S_AXI_HP2_RACOUNT),
- .S_WACOUNT (S_AXI_HP2_WACOUNT),
-
- .SW_CLK (net_sw_clk),
- .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
- .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
- .WR_DATA (net_wr_data_hp2),
- .WR_DATA_STRB (net_wr_strb_hp2),
- .WR_ADDR (net_wr_addr_hp2),
- .WR_BYTES (net_wr_bytes_hp2),
- .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2),
- .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2),
- .WR_QOS (net_wr_qos_hp2),
- .RD_REQ_DDR (net_rd_req_ddr_hp2),
- .RD_REQ_OCM (net_rd_req_ocm_hp2),
- .RD_ADDR (net_rd_addr_hp2),
- .RD_DATA_DDR (net_rd_data_ddr_hp2),
- .RD_DATA_OCM (net_rd_data_ocm_hp2),
- .RD_BYTES (net_rd_bytes_hp2),
- .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
- .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
- .RD_QOS (net_rd_qos_hp2)
-
- );
-
-/* AXI Slave HP3 */
- processing_system7_vip_v1_0_8_afi_slave #( C_USE_S_AXI_HP3, // enable
- axi_hp3_name, // name
- C_S_AXI_HP3_DATA_WIDTH, // data width
- addr_width, /// address width
- axi_hp_id_width, // ID width
- C_S_AXI_HP3_BASEADDR, // slave base address
- C_S_AXI_HP3_HIGHADDR, // SLave size
- axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
- axi_slv_excl_support) // Exclusive access support
- S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
- .S_ACLK (S_AXI_HP3_ACLK),
- // Write ADDRESS CHANNEL
- .S_AWID (S_AXI_HP3_AWID),
- .S_AWADDR (S_AXI_HP3_AWADDR),
- .S_AWLEN (S_AXI_HP3_AWLEN),
- .S_AWSIZE (S_AXI_HP3_AWSIZE),
- .S_AWBURST (S_AXI_HP3_AWBURST),
- .S_AWLOCK (S_AXI_HP3_AWLOCK),
- .S_AWCACHE (S_AXI_HP3_AWCACHE),
- .S_AWPROT (S_AXI_HP3_AWPROT),
- .S_AWVALID (S_AXI_HP3_AWVALID),
- .S_AWREADY (S_AXI_HP3_AWREADY),
- // Write Data channel signals.
- .S_WID (S_AXI_HP3_WID),
- .S_WDATA (S_AXI_HP3_WDATA),
- .S_WSTRB (S_AXI_HP3_WSTRB),
- .S_WLAST (S_AXI_HP3_WLAST),
- .S_WVALID (S_AXI_HP3_WVALID),
- .S_WREADY (S_AXI_HP3_WREADY),
- // Write Response channel signals.
- .S_BID (S_AXI_HP3_BID),
- .S_BRESP (S_AXI_HP3_BRESP),
- .S_BVALID (S_AXI_HP3_BVALID),
- .S_BREADY (S_AXI_HP3_BREADY),
- // Read Address channel signals.
- .S_ARID (S_AXI_HP3_ARID),
- .S_ARADDR (S_AXI_HP3_ARADDR),
- .S_ARLEN (S_AXI_HP3_ARLEN),
- .S_ARSIZE (S_AXI_HP3_ARSIZE),
- .S_ARBURST (S_AXI_HP3_ARBURST),
- .S_ARLOCK (S_AXI_HP3_ARLOCK),
- .S_ARCACHE (S_AXI_HP3_ARCACHE),
- .S_ARPROT (S_AXI_HP3_ARPROT),
- .S_ARVALID (S_AXI_HP3_ARVALID),
- .S_ARREADY (S_AXI_HP3_ARREADY),
- // Read Data channel signals.
- .S_RID (S_AXI_HP3_RID),
- .S_RDATA (S_AXI_HP3_RDATA),
- .S_RRESP (S_AXI_HP3_RRESP),
- .S_RLAST (S_AXI_HP3_RLAST),
- .S_RVALID (S_AXI_HP3_RVALID),
- .S_RREADY (S_AXI_HP3_RREADY),
- // Side band signals
- .S_AWQOS (S_AXI_HP3_AWQOS),
- .S_ARQOS (S_AXI_HP3_ARQOS),
- // these are needed only for HP ports
- .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
- .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
- .S_RCOUNT (S_AXI_HP3_RCOUNT),
- .S_WCOUNT (S_AXI_HP3_WCOUNT),
- .S_RACOUNT (S_AXI_HP3_RACOUNT),
- .S_WACOUNT (S_AXI_HP3_WACOUNT),
-
- .SW_CLK (net_sw_clk),
- .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
- .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
- .WR_DATA (net_wr_data_hp3),
- .WR_DATA_STRB (net_wr_strb_hp3),
- .WR_ADDR (net_wr_addr_hp3),
- .WR_BYTES (net_wr_bytes_hp3),
- .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3),
- .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3),
- .WR_QOS (net_wr_qos_hp3),
- .RD_REQ_DDR (net_rd_req_ddr_hp3),
- .RD_REQ_OCM (net_rd_req_ocm_hp3),
- .RD_ADDR (net_rd_addr_hp3),
- .RD_DATA_DDR (net_rd_data_ddr_hp3),
- .RD_DATA_OCM (net_rd_data_ocm_hp3),
- .RD_BYTES (net_rd_bytes_hp3),
- .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
- .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
- .RD_QOS (net_rd_qos_hp3)
- );
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_local_params.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_local_params.v
deleted file mode 100755
index 3635125dd0d98cef80a7deab7f2522a54cf99fea..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_local_params.v
+++ /dev/null
@@ -1,244 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_local_params.v
- *
- * Date : 2012-11
- *
- * Description : Parameters used in Zynq VIP
- *
- *****************************************************************************/
-
-
-/* local */
-parameter m_axi_gp0_baseaddr = 32'h4000_0000;
-parameter m_axi_gp1_baseaddr = 32'h8000_0000;
-parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
-parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
-
-parameter addr_width = 32; // maximum address width
-parameter data_width = 32; // maximum data width.
-parameter max_chars = 128; // max characters for file name
-parameter mem_width = data_width/8; /// memory width in bytes
-parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
-parameter int_width = 32; //integre width
-
-/* for internal read/write APIs used for data transfers */
-parameter max_burst_len = 16; /// maximum brst length on axi
-parameter max_data_width = 64; // maximum data width for internal AXI bursts
-parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts
-parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer
-parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts
-
-parameter max_registers = 32;
-parameter max_regs_width = clogb2(max_registers);
-
-parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11;
-
-/* Interrupt bits supported */
-parameter irq_width = 16;
-
-/* GP Master0 & Master1 address decode */
-parameter GP_M0 = 2'b01;
-parameter GP_M1 = 2'b10;
-
-parameter ALL_RANDOM= 2'b00;
-parameter ALL_ZEROS = 2'b01;
-parameter ALL_ONES = 2'b10;
-
-parameter ddr_start_addr = 32'h0008_0000;
-parameter ddr_end_addr = 32'h7FFF_FFFF;
-
-parameter ocm_start_addr = 32'h0000_0000;
-parameter ocm_end_addr = 32'h0003_FFFF;
-parameter high_ocm_start_addr = 32'hFFFC_0000;
-parameter high_ocm_end_addr = 32'hFFFF_FFFF;
-parameter ocm_low_addr = 32'hFFFF_0000;
-
-parameter reg_start_addr = 32'hE000_0000;
-parameter reg_end_addr = 32'hF8F0_2F80;
-
-
-/* for Master port APIs and AXI protocol related signal widths*/
-parameter axi_burst_len = 16;
-parameter axi_len_width = clogb2(axi_burst_len);
-parameter axi_size_width = 3;
-parameter axi_brst_type_width = 2;
-parameter axi_lock_width = 2;
-parameter axi_cache_width = 4;
-parameter axi_prot_width = 3;
-parameter axi_rsp_width = 2;
-parameter axi_mgp_data_width = 32;
-parameter axi_mgp_id_width = 12;
-parameter axi_mgp_outstanding = 8;
-parameter axi_mgp_wr_id = 12'hC00;
-parameter axi_mgp_rd_id = 12'hC0C;
-parameter axi_mgp0_name = "M_AXI_GP0";
-parameter axi_mgp1_name = "M_AXI_GP1";
-parameter axi_qos_width = 4;
-parameter max_transfer_bytes = 256; // For Master APIs.
-parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
-
-
-/* for GP slave ports*/
-parameter axi_sgp_data_width = 32;
-parameter axi_sgp_id_width = 6;
-parameter axi_sgp_rd_outstanding = 8;
-parameter axi_sgp_wr_outstanding = 8;
-parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
-parameter axi_sgp0_name = "S_AXI_GP0";
-parameter axi_sgp1_name = "S_AXI_GP1";
-
-/* for ACP slave ports*/
-parameter axi_acp_data_width = 64;
-parameter axi_acp_id_width = 3;
-parameter axi_acp_rd_outstanding = 7;
-parameter axi_acp_wr_outstanding = 3;
-parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
-parameter axi_acp_name = "S_AXI_ACP";
-
-/* for HP slave ports*/
-parameter axi_hp_id_width = 6;
-parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
-parameter axi_hp0_name = "S_AXI_HP0";
-parameter axi_hp1_name = "S_AXI_HP1";
-parameter axi_hp2_name = "S_AXI_HP2";
-parameter axi_hp3_name = "S_AXI_HP3";
-
-
-parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported
-parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
-
-/* AXI transfer types */
-parameter AXI_FIXED = 2'b00;
-parameter AXI_INCR = 2'b01;
-parameter AXI_WRAP = 2'b10;
-
-/* Exclusive Access */
-parameter AXI_NRML = 2'b00;
-parameter AXI_EXCL = 2'b01;
-parameter AXI_LOCK = 2'b10;
-
-/* AXI Response types */
-parameter AXI_OK = 2'b00;
-parameter AXI_EXCL_OK = 2'b01;
-parameter AXI_SLV_ERR = 2'b10;
-parameter AXI_DEC_ERR = 2'b11;
-
-function automatic integer clogb2;
- input [31:0] value;
- begin
- value = value - 1;
- for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
- value = value >> 1;
- end
- end
-endfunction
-
-/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
- /* WR FIFO data */
- // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
- // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
- // parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
- // parameter wr_bytes_lsb = 0;
- // parameter wr_bytes_msb = max_burst_bytes_width;
- // parameter wr_addr_lsb = wr_bytes_msb + 1;
- // parameter wr_addr_msb = wr_addr_lsb + addr_width-1;
- // parameter wr_data_lsb = wr_addr_msb + 1;
- // parameter wr_data_msb = wr_data_lsb + max_burst_bits-1;
- // parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
- // parameter wr_qos_lsb = wr_data_msb + 1;
- // `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1;
-
- /* WR AFI FIFO data */
- /* ID - 1071:1066
- Resp - 1065:1064
- data - 1063:40
- address - 39:8
- valid_bytes - 7:0
- */
- // parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
- // parameter wr_afi_bytes_lsb = 0;
- // parameter wr_afi_bytes_msb = max_burst_bytes_width;
- // parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1;
- // parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1;
- // parameter wr_afi_data_lsb = wr_afi_addr_msb + 1;
- // parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1;
- // parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1;
- // parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1;
- // parameter wr_afi_ln_lsb = wr_afi_id_msb + 1;
- // parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1;
- // parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1;
- // parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1;
-
-
- parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes
- parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
- parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
-
-/* for interconnect fifo models */
- parameter intr_max_outstanding = 8;
- parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
- parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
- parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
-
- //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
- parameter rd_afi_bytes_lsb = 0;
- parameter rd_afi_bytes_msb = max_burst_bytes_width;
- parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1;
- parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1;
- parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1;
- parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1;
- parameter rd_afi_ln_lsb = rd_afi_id_msb + 1;
- parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1;
- parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1;
- parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1;
- parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1;
- parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1;
- parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1;
- parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1;
- parameter rd_afi_data_lsb = rd_afi_addr_msb + 1;
- parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1;
-
-
-/* Latency types */
- parameter BEST_CASE = 0;
- parameter AVG_CASE = 1;
- parameter WORST_CASE = 2;
- parameter RANDOM_CASE = 3;
-
-/* Latency Parameters ACP */
- parameter acp_wr_min = 21;
- parameter acp_wr_avg = 16;
- parameter acp_wr_max = 27;
- parameter acp_rd_min = 34;
- parameter acp_rd_avg = 125;
- parameter acp_rd_max = 130;
-
-/* Latency Parameters GP */
- parameter gp_wr_min = 21;
- parameter gp_wr_avg = 16;
- parameter gp_wr_max = 46;
- parameter gp_rd_min = 38;
- parameter gp_rd_avg = 125;
- parameter gp_rd_max = 130;
-
-/* Latency Parameters HP */
- parameter afi_wr_min = 37;
- parameter afi_wr_avg = 41;
- parameter afi_wr_max = 42;
- parameter afi_rd_min = 41;
- parameter afi_rd_avg = 221;
- parameter afi_rd_max = 229;
-
-/* ID VALID and INVALID */
- parameter secure_access_enabled = 0;
- parameter id_invalid = 0;
- parameter id_valid = 1;
-
-/* Display */
- parameter DISP_INFO = "*ZYNQ_VIP_INFO";
- parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
- parameter DISP_ERR = "*ZYNQ_VIP_ERROR";
- parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
-
- parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_reg_init.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_reg_init.v
deleted file mode 100755
index 72b4ff0c5d4cbb150c7d1b76259665fdc6b6e884..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_reg_init.v
+++ /dev/null
@@ -1,2924 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_reg_init.v
- *
- * Date : 2012-11
- *
- * Description : Initialize register default values.
- *
- *****************************************************************************/
-
-// Register default value info for chip pele_ps
-// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012
-// 54 modules, 2532 registers.
-
-
-// ************************************************************
-// Module afi0 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL);
-set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP);
-set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS);
-set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL);
-set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG);
-set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL);
-set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP);
-set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS);
-set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL);
-set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG);
-
-// ************************************************************
-// Module afi1 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL);
-set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP);
-set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS);
-set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL);
-set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG);
-set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL);
-set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP);
-set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS);
-set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL);
-set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG);
-
-// ************************************************************
-// Module afi2 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL);
-set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP);
-set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS);
-set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL);
-set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG);
-set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL);
-set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP);
-set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS);
-set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL);
-set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG);
-
-// ************************************************************
-// Module afi3 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL);
-set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP);
-set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS);
-set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL);
-set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG);
-set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL);
-set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP);
-set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS);
-set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL);
-set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG);
-
-// ************************************************************
-// Module can0 can
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( can0__SRR, val_can0__SRR);
-set_reset_data( can0__MSR, val_can0__MSR);
-set_reset_data( can0__BRPR, val_can0__BRPR);
-set_reset_data( can0__BTR, val_can0__BTR);
-set_reset_data( can0__ECR, val_can0__ECR);
-set_reset_data( can0__ESR, val_can0__ESR);
-set_reset_data( can0__SR, val_can0__SR);
-set_reset_data( can0__ISR, val_can0__ISR);
-set_reset_data( can0__IER, val_can0__IER);
-set_reset_data( can0__ICR, val_can0__ICR);
-set_reset_data( can0__TCR, val_can0__TCR);
-set_reset_data( can0__WIR, val_can0__WIR);
-set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID);
-set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC);
-set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1);
-set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2);
-set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID);
-set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC);
-set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1);
-set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2);
-set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID);
-set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC);
-set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1);
-set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2);
-set_reset_data( can0__AFR, val_can0__AFR);
-set_reset_data( can0__AFMR1, val_can0__AFMR1);
-set_reset_data( can0__AFIR1, val_can0__AFIR1);
-set_reset_data( can0__AFMR2, val_can0__AFMR2);
-set_reset_data( can0__AFIR2, val_can0__AFIR2);
-set_reset_data( can0__AFMR3, val_can0__AFMR3);
-set_reset_data( can0__AFIR3, val_can0__AFIR3);
-set_reset_data( can0__AFMR4, val_can0__AFMR4);
-set_reset_data( can0__AFIR4, val_can0__AFIR4);
-
-// ************************************************************
-// Module can1 can
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( can1__SRR, val_can1__SRR);
-set_reset_data( can1__MSR, val_can1__MSR);
-set_reset_data( can1__BRPR, val_can1__BRPR);
-set_reset_data( can1__BTR, val_can1__BTR);
-set_reset_data( can1__ECR, val_can1__ECR);
-set_reset_data( can1__ESR, val_can1__ESR);
-set_reset_data( can1__SR, val_can1__SR);
-set_reset_data( can1__ISR, val_can1__ISR);
-set_reset_data( can1__IER, val_can1__IER);
-set_reset_data( can1__ICR, val_can1__ICR);
-set_reset_data( can1__TCR, val_can1__TCR);
-set_reset_data( can1__WIR, val_can1__WIR);
-set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID);
-set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC);
-set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1);
-set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2);
-set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID);
-set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC);
-set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1);
-set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2);
-set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID);
-set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC);
-set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1);
-set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2);
-set_reset_data( can1__AFR, val_can1__AFR);
-set_reset_data( can1__AFMR1, val_can1__AFMR1);
-set_reset_data( can1__AFIR1, val_can1__AFIR1);
-set_reset_data( can1__AFMR2, val_can1__AFMR2);
-set_reset_data( can1__AFIR2, val_can1__AFIR2);
-set_reset_data( can1__AFMR3, val_can1__AFMR3);
-set_reset_data( can1__AFIR3, val_can1__AFIR3);
-set_reset_data( can1__AFMR4, val_can1__AFMR4);
-set_reset_data( can1__AFIR4, val_can1__AFIR4);
-
-// ************************************************************
-// Module ddrc ddrc
-// doc version: 1.25
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl);
-set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg);
-set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg);
-set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg);
-set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg);
-set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0);
-set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1);
-set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2);
-set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3);
-set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4);
-set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param);
-set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg);
-set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg);
-set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr);
-set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ);
-set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank);
-set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col);
-set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row);
-set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg);
-set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg);
-set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt);
-set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg);
-set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib);
-set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold);
-set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1);
-set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2);
-set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3);
-set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4);
-set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5);
-set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6);
-set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01);
-set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ);
-set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg);
-set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg);
-set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c);
-set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d);
-set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing);
-set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2);
-set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing);
-set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET);
-set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET);
-set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET);
-set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET);
-set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET);
-set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET);
-set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET);
-set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET);
-set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET);
-set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET);
-set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET);
-set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET);
-set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub);
-set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET);
-set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET);
-set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable);
-set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0);
-set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1);
-set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2);
-set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3);
-set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0);
-set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1);
-set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2);
-set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3);
-set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0);
-set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1);
-set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2);
-set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3);
-set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0);
-set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1);
-set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2);
-set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3);
-set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0);
-set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1);
-set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2);
-set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3);
-set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0);
-set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1);
-set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2);
-set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3);
-set_reset_data( ddrc__reg_64, val_ddrc__reg_64);
-set_reset_data( ddrc__reg_65, val_ddrc__reg_65);
-set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0);
-set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1);
-set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2);
-set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3);
-set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710);
-set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711);
-set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712);
-set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713);
-set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0);
-set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1);
-set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2);
-set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3);
-set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts);
-set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts);
-set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2);
-set_reset_data( ddrc__axi_id, val_ddrc__axi_id);
-set_reset_data( ddrc__page_mask, val_ddrc__page_mask);
-set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0);
-set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1);
-set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2);
-set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3);
-set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0);
-set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1);
-set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2);
-set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3);
-set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0);
-set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1);
-set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2);
-set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3);
-set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0);
-set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1);
-set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2);
-set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3);
-set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20);
-set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21);
-set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22);
-set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23);
-set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30);
-set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31);
-set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32);
-set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33);
-set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg);
-set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0);
-set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1);
-set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2);
-set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3);
-set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read);
-set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0);
-set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1);
-set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2);
-set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3);
-set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm);
-set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm);
-set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm);
-
-// ************************************************************
-// Module debug_axim axim
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL);
-set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS);
-set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL);
-set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL);
-set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS);
-set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL);
-set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL);
-set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH);
-set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT);
-set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER);
-set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT);
-set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD);
-set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT);
-set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK);
-set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER);
-set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER);
-set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC);
-set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK);
-set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER);
-set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER);
-set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC);
-set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK);
-set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER);
-set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER);
-set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC);
-set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK);
-set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER);
-set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER);
-set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC);
-set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK);
-set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER);
-set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER);
-set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC);
-set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK);
-set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER);
-set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER);
-set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC);
-set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK);
-set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER);
-set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER);
-set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC);
-set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK);
-set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER);
-set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER);
-set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC);
-set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL);
-set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT);
-set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK);
-set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN);
-set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK);
-set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA);
-set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS);
-set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1);
-set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0);
-set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL);
-set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET);
-set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR);
-set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS);
-set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS);
-set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS);
-set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID);
-set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE);
-set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4);
-set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5);
-set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6);
-set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7);
-set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0);
-set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1);
-set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2);
-set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3);
-set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0);
-set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1);
-set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2);
-set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3);
-
-// ************************************************************
-// Module debug_cpu_cti0 cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL);
-set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK);
-set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET);
-set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR);
-set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE);
-set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0);
-set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1);
-set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2);
-set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3);
-set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4);
-set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5);
-set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6);
-set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7);
-set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0);
-set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1);
-set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2);
-set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3);
-set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4);
-set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5);
-set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6);
-set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7);
-set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS);
-set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS);
-set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS);
-set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS);
-set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE);
-set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL);
-set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK);
-set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK);
-set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT);
-set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT);
-set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK);
-set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK);
-set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN);
-set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN);
-set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL);
-set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR);
-set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR);
-set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR);
-set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR);
-set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR);
-set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID);
-set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR);
-set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4);
-set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5);
-set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6);
-set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7);
-set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0);
-set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1);
-set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2);
-set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3);
-set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0);
-set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1);
-set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2);
-set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3);
-
-// ************************************************************
-// Module debug_cpu_cti1 cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL);
-set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK);
-set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET);
-set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR);
-set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE);
-set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0);
-set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1);
-set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2);
-set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3);
-set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4);
-set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5);
-set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6);
-set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7);
-set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0);
-set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1);
-set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2);
-set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3);
-set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4);
-set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5);
-set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6);
-set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7);
-set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS);
-set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS);
-set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS);
-set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS);
-set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE);
-set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL);
-set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK);
-set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK);
-set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT);
-set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT);
-set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK);
-set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK);
-set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN);
-set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN);
-set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL);
-set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR);
-set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR);
-set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR);
-set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR);
-set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR);
-set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID);
-set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR);
-set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4);
-set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5);
-set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6);
-set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7);
-set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0);
-set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1);
-set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2);
-set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3);
-set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0);
-set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1);
-set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2);
-set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3);
-
-// ************************************************************
-// Module debug_cpu_pmu0 cortexa9_pmu
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0);
-set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1);
-set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2);
-set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3);
-set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4);
-set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5);
-set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR);
-set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0);
-set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1);
-set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2);
-set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3);
-set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4);
-set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5);
-set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET);
-set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR);
-set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET);
-set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR);
-set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR);
-set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC);
-set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR);
-set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR);
-
-// ************************************************************
-// Module debug_cpu_pmu1 cortexa9_pmu
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0);
-set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1);
-set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2);
-set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3);
-set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4);
-set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5);
-set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR);
-set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0);
-set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1);
-set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2);
-set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3);
-set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4);
-set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5);
-set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET);
-set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR);
-set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET);
-set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR);
-set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR);
-set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC);
-set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR);
-set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR);
-
-// ************************************************************
-// Module debug_cpu_ptm0 ptm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR);
-set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR);
-set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER);
-set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR);
-set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR);
-set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR);
-set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1);
-set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1);
-set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2);
-set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3);
-set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4);
-set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5);
-set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6);
-set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7);
-set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8);
-set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1);
-set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2);
-set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3);
-set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4);
-set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5);
-set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6);
-set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7);
-set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8);
-set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1);
-set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2);
-set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1);
-set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2);
-set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1);
-set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2);
-set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1);
-set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2);
-set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR);
-set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR);
-set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR);
-set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR);
-set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR);
-set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR);
-set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR);
-set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1);
-set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2);
-set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1);
-set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR);
-set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR);
-set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR);
-set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER);
-set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR);
-set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR);
-set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR);
-set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR);
-set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR);
-set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT);
-set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN);
-set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER);
-set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0);
-set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2);
-set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID);
-set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0);
-set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL);
-set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR);
-set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR);
-set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR);
-set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR);
-set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR);
-set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID);
-set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR);
-set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4);
-set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5);
-set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6);
-set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7);
-set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0);
-set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1);
-set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2);
-set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3);
-set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0);
-set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1);
-set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2);
-set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3);
-
-// ************************************************************
-// Module debug_cpu_ptm1 ptm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR);
-set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR);
-set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER);
-set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR);
-set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR);
-set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR);
-set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1);
-set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1);
-set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2);
-set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3);
-set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4);
-set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5);
-set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6);
-set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7);
-set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8);
-set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1);
-set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2);
-set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3);
-set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4);
-set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5);
-set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6);
-set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7);
-set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8);
-set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1);
-set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2);
-set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1);
-set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2);
-set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1);
-set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2);
-set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1);
-set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2);
-set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR);
-set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR);
-set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR);
-set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR);
-set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR);
-set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR);
-set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR);
-set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1);
-set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2);
-set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1);
-set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR);
-set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR);
-set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR);
-set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER);
-set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR);
-set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR);
-set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR);
-set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR);
-set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR);
-set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT);
-set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN);
-set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER);
-set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0);
-set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2);
-set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID);
-set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0);
-set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL);
-set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR);
-set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR);
-set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR);
-set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR);
-set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR);
-set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID);
-set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR);
-set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4);
-set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5);
-set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6);
-set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7);
-set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0);
-set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1);
-set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2);
-set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3);
-set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0);
-set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1);
-set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2);
-set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3);
-
-// ************************************************************
-// Module debug_cti_axim cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL);
-set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK);
-set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET);
-set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR);
-set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE);
-set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0);
-set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1);
-set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2);
-set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3);
-set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4);
-set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5);
-set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6);
-set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7);
-set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0);
-set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1);
-set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2);
-set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3);
-set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4);
-set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5);
-set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6);
-set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7);
-set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS);
-set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS);
-set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS);
-set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS);
-set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE);
-set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL);
-set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK);
-set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK);
-set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT);
-set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT);
-set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK);
-set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK);
-set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN);
-set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN);
-set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL);
-set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR);
-set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR);
-set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR);
-set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR);
-set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR);
-set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID);
-set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR);
-set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4);
-set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5);
-set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6);
-set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7);
-set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0);
-set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1);
-set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2);
-set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3);
-set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0);
-set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1);
-set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2);
-set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3);
-
-// ************************************************************
-// Module debug_cti_etb_tpiu cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL);
-set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK);
-set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET);
-set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR);
-set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6);
-set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6);
-set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7);
-set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS);
-set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS);
-set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS);
-set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS);
-set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE);
-set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL);
-set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK);
-set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK);
-set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT);
-set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT);
-set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK);
-set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK);
-set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN);
-set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN);
-set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL);
-set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR);
-set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR);
-set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR);
-set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR);
-set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR);
-set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID);
-set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2);
-set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3);
-set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0);
-set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1);
-set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2);
-set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3);
-
-// ************************************************************
-// Module debug_cti_ftm cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL);
-set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK);
-set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET);
-set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR);
-set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE);
-set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0);
-set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1);
-set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2);
-set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3);
-set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4);
-set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5);
-set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6);
-set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7);
-set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0);
-set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1);
-set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2);
-set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3);
-set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4);
-set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5);
-set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6);
-set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7);
-set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS);
-set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS);
-set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS);
-set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS);
-set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE);
-set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL);
-set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK);
-set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK);
-set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT);
-set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT);
-set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK);
-set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK);
-set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN);
-set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN);
-set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL);
-set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR);
-set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR);
-set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR);
-set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR);
-set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR);
-set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID);
-set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR);
-set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4);
-set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5);
-set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6);
-set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7);
-set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0);
-set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1);
-set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2);
-set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3);
-set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0);
-set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1);
-set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2);
-set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3);
-
-// ************************************************************
-// Module debug_dap_rom dap
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00);
-set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01);
-set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02);
-set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03);
-set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04);
-set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05);
-set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06);
-set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07);
-set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08);
-set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09);
-set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10);
-set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11);
-set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12);
-set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13);
-set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14);
-set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15);
-set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4);
-set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5);
-set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6);
-set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7);
-set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0);
-set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1);
-set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2);
-set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3);
-set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0);
-set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1);
-set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2);
-set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3);
-
-// ************************************************************
-// Module debug_etb etb
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_etb__RDP, val_debug_etb__RDP);
-set_reset_data( debug_etb__STS, val_debug_etb__STS);
-set_reset_data( debug_etb__RRD, val_debug_etb__RRD);
-set_reset_data( debug_etb__RRP, val_debug_etb__RRP);
-set_reset_data( debug_etb__RWP, val_debug_etb__RWP);
-set_reset_data( debug_etb__TRG, val_debug_etb__TRG);
-set_reset_data( debug_etb__CTL, val_debug_etb__CTL);
-set_reset_data( debug_etb__RWD, val_debug_etb__RWD);
-set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR);
-set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR);
-set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0);
-set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK);
-set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN);
-set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0);
-set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2);
-set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1);
-set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0);
-set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR);
-set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR);
-set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR);
-set_reset_data( debug_etb__LAR, val_debug_etb__LAR);
-set_reset_data( debug_etb__LSR, val_debug_etb__LSR);
-set_reset_data( debug_etb__ASR, val_debug_etb__ASR);
-set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID);
-set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR);
-set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4);
-set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5);
-set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6);
-set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7);
-set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0);
-set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1);
-set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2);
-set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3);
-set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0);
-set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1);
-set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2);
-set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3);
-
-// ************************************************************
-// Module debug_ftm ftm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL);
-set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS);
-set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL);
-set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0);
-set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1);
-set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2);
-set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3);
-set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0);
-set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1);
-set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2);
-set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3);
-set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE);
-set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD);
-set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT);
-set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID);
-set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK);
-set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER);
-set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS);
-set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT);
-set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0);
-set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2);
-set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1);
-set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0);
-set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR);
-set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET);
-set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR);
-set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS);
-set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS);
-set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS);
-set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID);
-set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE);
-set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4);
-set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5);
-set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6);
-set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7);
-set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0);
-set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1);
-set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2);
-set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3);
-set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0);
-set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1);
-set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2);
-set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3);
-
-// ************************************************************
-// Module debug_funnel funnel
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_funnel__Control, val_debug_funnel__Control);
-set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl);
-set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0);
-set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2);
-set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1);
-set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0);
-set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR);
-set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR);
-set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR);
-set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR);
-set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR);
-set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR);
-set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID);
-set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR);
-set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4);
-set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5);
-set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6);
-set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7);
-set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0);
-set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1);
-set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2);
-set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3);
-set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0);
-set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1);
-set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2);
-set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3);
-
-// ************************************************************
-// Module debug_itm itm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00);
-set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01);
-set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02);
-set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03);
-set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04);
-set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05);
-set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06);
-set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07);
-set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08);
-set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09);
-set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10);
-set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11);
-set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12);
-set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13);
-set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14);
-set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15);
-set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16);
-set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17);
-set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18);
-set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19);
-set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20);
-set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21);
-set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22);
-set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23);
-set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24);
-set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25);
-set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26);
-set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27);
-set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28);
-set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29);
-set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30);
-set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31);
-set_reset_data( debug_itm__TER, val_debug_itm__TER);
-set_reset_data( debug_itm__TTR, val_debug_itm__TTR);
-set_reset_data( debug_itm__CR, val_debug_itm__CR);
-set_reset_data( debug_itm__SCR, val_debug_itm__SCR);
-set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK);
-set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT);
-set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0);
-set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2);
-set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1);
-set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0);
-set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR);
-set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR);
-set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR);
-set_reset_data( debug_itm__LAR, val_debug_itm__LAR);
-set_reset_data( debug_itm__LSR, val_debug_itm__LSR);
-set_reset_data( debug_itm__ASR, val_debug_itm__ASR);
-set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID);
-set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR);
-set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4);
-set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5);
-set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6);
-set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7);
-set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0);
-set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1);
-set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2);
-set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3);
-set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0);
-set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1);
-set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2);
-set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3);
-
-// ************************************************************
-// Module debug_tpiu tpiu
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize);
-set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize);
-set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode);
-set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount);
-set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult);
-set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest);
-set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest);
-set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount);
-set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR);
-set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR);
-set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount);
-set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn);
-set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut);
-set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK);
-set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN);
-set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0);
-set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2);
-set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1);
-set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0);
-set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR);
-set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR);
-set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR);
-set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR);
-set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR);
-set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR);
-set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID);
-set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR);
-set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4);
-set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5);
-set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6);
-set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7);
-set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0);
-set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1);
-set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2);
-set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3);
-set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0);
-set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1);
-set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2);
-set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3);
-
-// ************************************************************
-// Module devcfg devcfg
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( devcfg__CTRL, val_devcfg__CTRL);
-set_reset_data( devcfg__LOCK, val_devcfg__LOCK);
-set_reset_data( devcfg__CFG, val_devcfg__CFG);
-set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS);
-set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK);
-set_reset_data( devcfg__STATUS, val_devcfg__STATUS);
-set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR);
-set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR);
-set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN);
-set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN);
-set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW);
-set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR);
-set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID);
-set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK);
-set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL);
-set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG);
-set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS);
-set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK);
-set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS);
-set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO);
-set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO);
-set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL);
-
-// ************************************************************
-// Module dmac0_ns dmac
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR);
-set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC);
-set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN);
-set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS);
-set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS);
-set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR);
-set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD);
-set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__FSRC);
-set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD);
-set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0);
-set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1);
-set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2);
-set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3);
-set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4);
-set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5);
-set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6);
-set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7);
-set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0);
-set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0);
-set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1);
-set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1);
-set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2);
-set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2);
-set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3);
-set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3);
-set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4);
-set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4);
-set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5);
-set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5);
-set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6);
-set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6);
-set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7);
-set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7);
-set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0);
-set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0);
-set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0);
-set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0);
-set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0);
-set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1);
-set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1);
-set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1);
-set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1);
-set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1);
-set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2);
-set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2);
-set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2);
-set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2);
-set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2);
-set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3);
-set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3);
-set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3);
-set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3);
-set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3);
-set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4);
-set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4);
-set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4);
-set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4);
-set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4);
-set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5);
-set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5);
-set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5);
-set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5);
-set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5);
-set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6);
-set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6);
-set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6);
-set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6);
-set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6);
-set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7);
-set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7);
-set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7);
-set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7);
-set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7);
-set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS);
-set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD);
-set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0);
-set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1);
-set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0);
-set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1);
-set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2);
-set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3);
-set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4);
-set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD);
-set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD);
-set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0);
-set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1);
-set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2);
-set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3);
-set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0);
-set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1);
-set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2);
-set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3);
-
-// ************************************************************
-// Module dmac0_s dmac
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR);
-set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC);
-set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN);
-set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS);
-set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS);
-set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR);
-set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD);
-set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC);
-set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD);
-set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0);
-set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1);
-set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2);
-set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3);
-set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4);
-set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5);
-set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6);
-set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7);
-set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0);
-set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0);
-set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1);
-set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1);
-set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2);
-set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2);
-set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3);
-set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3);
-set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4);
-set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4);
-set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5);
-set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5);
-set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6);
-set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6);
-set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7);
-set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7);
-set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0);
-set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0);
-set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0);
-set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0);
-set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0);
-set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1);
-set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1);
-set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1);
-set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1);
-set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1);
-set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2);
-set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2);
-set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2);
-set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2);
-set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2);
-set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3);
-set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3);
-set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3);
-set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3);
-set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3);
-set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4);
-set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4);
-set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4);
-set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4);
-set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4);
-set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5);
-set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5);
-set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5);
-set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5);
-set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5);
-set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6);
-set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6);
-set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6);
-set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6);
-set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6);
-set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7);
-set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7);
-set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7);
-set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7);
-set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7);
-set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS);
-set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD);
-set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0);
-set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1);
-set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0);
-set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1);
-set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2);
-set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3);
-set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4);
-set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD);
-set_reset_data( dmac0_s__WD, val_dmac0_s__WD);
-set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0);
-set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1);
-set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2);
-set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3);
-set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0);
-set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1);
-set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2);
-set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3);
-
-// ************************************************************
-// Module efuse_ctrl efuse_ctrl
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK);
-set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK);
-set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA);
-set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG);
-set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS);
-set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL);
-set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW);
-set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW);
-
-// ************************************************************
-// Module gem0 GEM
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl);
-set_reset_data( gem0__net_cfg, val_gem0__net_cfg);
-set_reset_data( gem0__net_status, val_gem0__net_status);
-set_reset_data( gem0__user_io, val_gem0__user_io);
-set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg);
-set_reset_data( gem0__tx_status, val_gem0__tx_status);
-set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar);
-set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar);
-set_reset_data( gem0__rx_status, val_gem0__rx_status);
-set_reset_data( gem0__intr_status, val_gem0__intr_status);
-set_reset_data( gem0__intr_en, val_gem0__intr_en);
-set_reset_data( gem0__intr_dis, val_gem0__intr_dis);
-set_reset_data( gem0__intr_mask, val_gem0__intr_mask);
-set_reset_data( gem0__phy_maint, val_gem0__phy_maint);
-set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq);
-set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq);
-set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd);
-set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd);
-set_reset_data( gem0__hash_bot, val_gem0__hash_bot);
-set_reset_data( gem0__hash_top, val_gem0__hash_top);
-set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot);
-set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top);
-set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot);
-set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top);
-set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot);
-set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top);
-set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot);
-set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top);
-set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1);
-set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2);
-set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3);
-set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4);
-set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan);
-set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch);
-set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan);
-set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause);
-set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot);
-set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top);
-set_reset_data( gem0__module_id, val_gem0__module_id);
-set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot);
-set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top);
-set_reset_data( gem0__frames_tx, val_gem0__frames_tx);
-set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx);
-set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx);
-set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx);
-set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx);
-set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx);
-set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx);
-set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx);
-set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx);
-set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx);
-set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx);
-set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs);
-set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames);
-set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames);
-set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns);
-set_reset_data( gem0__late_collisns, val_gem0__late_collisns);
-set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames);
-set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs);
-set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot);
-set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top);
-set_reset_data( gem0__frames_rx, val_gem0__frames_rx);
-set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx);
-set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx);
-set_reset_data( gem0__pause_rx, val_gem0__pause_rx);
-set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx);
-set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx);
-set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx);
-set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx);
-set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx);
-set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx);
-set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx);
-set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx);
-set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx);
-set_reset_data( gem0__jab_rx, val_gem0__jab_rx);
-set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors);
-set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors);
-set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors);
-set_reset_data( gem0__align_errors, val_gem0__align_errors);
-set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors);
-set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors);
-set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors);
-set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors);
-set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors);
-set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s);
-set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns);
-set_reset_data( gem0__timer_s, val_gem0__timer_s);
-set_reset_data( gem0__timer_ns, val_gem0__timer_ns);
-set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust);
-set_reset_data( gem0__timer_incr, val_gem0__timer_incr);
-set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s);
-set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns);
-set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s);
-set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns);
-set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s);
-set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns);
-set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s);
-set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns);
-set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl);
-set_reset_data( gem0__pcs_status, val_gem0__pcs_status);
-set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id);
-set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id);
-set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad);
-set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability);
-set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp);
-set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg);
-set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg);
-set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status);
-set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1);
-set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2);
-set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3);
-set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4);
-set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5);
-set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6);
-set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7);
-set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1);
-set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2);
-set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3);
-set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4);
-set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5);
-set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6);
-set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7);
-set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1);
-set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2);
-set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3);
-set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4);
-set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5);
-set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6);
-set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7);
-set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1);
-set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2);
-set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3);
-set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4);
-set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5);
-set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6);
-set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7);
-set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1);
-set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2);
-set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3);
-set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4);
-set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5);
-set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6);
-set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7);
-set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0);
-set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1);
-set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2);
-set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3);
-set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4);
-set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5);
-set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6);
-set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7);
-set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8);
-set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9);
-set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10);
-set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11);
-set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12);
-set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13);
-set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14);
-set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15);
-set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0);
-set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1);
-set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2);
-set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3);
-set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4);
-set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5);
-set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6);
-set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7);
-set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8);
-set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9);
-set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10);
-set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11);
-set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12);
-set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13);
-set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14);
-set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15);
-set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1);
-set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2);
-set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3);
-set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4);
-set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5);
-set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6);
-set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7);
-set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1);
-set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2);
-set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3);
-set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4);
-set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5);
-set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6);
-set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7);
-set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1);
-set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2);
-set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3);
-set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4);
-set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5);
-set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6);
-set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7);
-
-// ************************************************************
-// Module gem1 GEM
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl);
-set_reset_data( gem1__net_cfg, val_gem1__net_cfg);
-set_reset_data( gem1__net_status, val_gem1__net_status);
-set_reset_data( gem1__user_io, val_gem1__user_io);
-set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg);
-set_reset_data( gem1__tx_status, val_gem1__tx_status);
-set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar);
-set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar);
-set_reset_data( gem1__rx_status, val_gem1__rx_status);
-set_reset_data( gem1__intr_status, val_gem1__intr_status);
-set_reset_data( gem1__intr_en, val_gem1__intr_en);
-set_reset_data( gem1__intr_dis, val_gem1__intr_dis);
-set_reset_data( gem1__intr_mask, val_gem1__intr_mask);
-set_reset_data( gem1__phy_maint, val_gem1__phy_maint);
-set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq);
-set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq);
-set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd);
-set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd);
-set_reset_data( gem1__hash_bot, val_gem1__hash_bot);
-set_reset_data( gem1__hash_top, val_gem1__hash_top);
-set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot);
-set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top);
-set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot);
-set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top);
-set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot);
-set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top);
-set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot);
-set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top);
-set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1);
-set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2);
-set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3);
-set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4);
-set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan);
-set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch);
-set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan);
-set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause);
-set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot);
-set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top);
-set_reset_data( gem1__module_id, val_gem1__module_id);
-set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot);
-set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top);
-set_reset_data( gem1__frames_tx, val_gem1__frames_tx);
-set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx);
-set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx);
-set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx);
-set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx);
-set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx);
-set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx);
-set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx);
-set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx);
-set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx);
-set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx);
-set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs);
-set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames);
-set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames);
-set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns);
-set_reset_data( gem1__late_collisns, val_gem1__late_collisns);
-set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames);
-set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs);
-set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot);
-set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top);
-set_reset_data( gem1__frames_rx, val_gem1__frames_rx);
-set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx);
-set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx);
-set_reset_data( gem1__pause_rx, val_gem1__pause_rx);
-set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx);
-set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx);
-set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx);
-set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx);
-set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx);
-set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx);
-set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx);
-set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx);
-set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx);
-set_reset_data( gem1__jab_rx, val_gem1__jab_rx);
-set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors);
-set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors);
-set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors);
-set_reset_data( gem1__align_errors, val_gem1__align_errors);
-set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors);
-set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors);
-set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors);
-set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors);
-set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors);
-set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s);
-set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns);
-set_reset_data( gem1__timer_s, val_gem1__timer_s);
-set_reset_data( gem1__timer_ns, val_gem1__timer_ns);
-set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust);
-set_reset_data( gem1__timer_incr, val_gem1__timer_incr);
-set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s);
-set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns);
-set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s);
-set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns);
-set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s);
-set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns);
-set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s);
-set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns);
-set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl);
-set_reset_data( gem1__pcs_status, val_gem1__pcs_status);
-set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id);
-set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id);
-set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad);
-set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability);
-set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp);
-set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg);
-set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg);
-set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status);
-set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1);
-set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2);
-set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3);
-set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4);
-set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5);
-set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6);
-set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7);
-set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1);
-set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2);
-set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3);
-set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4);
-set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5);
-set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6);
-set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7);
-set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1);
-set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2);
-set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3);
-set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4);
-set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5);
-set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6);
-set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7);
-set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1);
-set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2);
-set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3);
-set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4);
-set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5);
-set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6);
-set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7);
-set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1);
-set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2);
-set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3);
-set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4);
-set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5);
-set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6);
-set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7);
-set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0);
-set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1);
-set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2);
-set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3);
-set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4);
-set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5);
-set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6);
-set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7);
-set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8);
-set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9);
-set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10);
-set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11);
-set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12);
-set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13);
-set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14);
-set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15);
-set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0);
-set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1);
-set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2);
-set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3);
-set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4);
-set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5);
-set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6);
-set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7);
-set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8);
-set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9);
-set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10);
-set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11);
-set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12);
-set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13);
-set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14);
-set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15);
-set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1);
-set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2);
-set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3);
-set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4);
-set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5);
-set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6);
-set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7);
-set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1);
-set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2);
-set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3);
-set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4);
-set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5);
-set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6);
-set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7);
-set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1);
-set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2);
-set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3);
-set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4);
-set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5);
-set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6);
-set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7);
-
-// ************************************************************
-// Module gpio gpio
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW);
-set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW);
-set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW);
-set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW);
-set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW);
-set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW);
-set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW);
-set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW);
-set_reset_data( gpio__DATA_0, val_gpio__DATA_0);
-set_reset_data( gpio__DATA_1, val_gpio__DATA_1);
-set_reset_data( gpio__DATA_2, val_gpio__DATA_2);
-set_reset_data( gpio__DATA_3, val_gpio__DATA_3);
-set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO);
-set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO);
-set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO);
-set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO);
-set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0);
-set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0);
-set_reset_data( gpio__OEN_0, val_gpio__OEN_0);
-set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0);
-set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0);
-set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0);
-set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0);
-set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0);
-set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0);
-set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0);
-set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1);
-set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1);
-set_reset_data( gpio__OEN_1, val_gpio__OEN_1);
-set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1);
-set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1);
-set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1);
-set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1);
-set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1);
-set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1);
-set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1);
-set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2);
-set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2);
-set_reset_data( gpio__OEN_2, val_gpio__OEN_2);
-set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2);
-set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2);
-set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2);
-set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2);
-set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2);
-set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2);
-set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2);
-set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3);
-set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3);
-set_reset_data( gpio__OEN_3, val_gpio__OEN_3);
-set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3);
-set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3);
-set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3);
-set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3);
-set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3);
-set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3);
-set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3);
-
-// ************************************************************
-// Module gpv_iou_switch gpv_iou_switch
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap);
-set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0);
-set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1);
-set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi);
-set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou);
-set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves);
-set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc);
-set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4);
-set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5);
-set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6);
-set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7);
-set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0);
-set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1);
-set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2);
-set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3);
-set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0);
-set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1);
-set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2);
-set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3);
-set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0);
-set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0);
-set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1);
-set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1);
-set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi);
-set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou);
-set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc);
-set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0);
-set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0);
-set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0);
-set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0);
-set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1);
-set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1);
-set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1);
-set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1);
-set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0);
-set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0);
-set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0);
-set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0);
-set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1);
-set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1);
-set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1);
-set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1);
-set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0);
-set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0);
-set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0);
-set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0);
-set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1);
-set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1);
-set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1);
-set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1);
-set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou);
-
-// ************************************************************
-// Module gpv_qos301_cpu qos301
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl);
-set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot);
-set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot);
-set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p);
-set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b);
-set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r);
-set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p);
-set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b);
-set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r);
-
-// ************************************************************
-// Module gpv_qos301_dmac qos301
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl);
-set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot);
-set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot);
-set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p);
-set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b);
-set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r);
-set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p);
-set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b);
-set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r);
-
-// ************************************************************
-// Module gpv_qos301_iou qos301
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl);
-set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot);
-set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot);
-set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p);
-set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b);
-set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r);
-set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p);
-set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b);
-set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r);
-
-// ************************************************************
-// Module gpv_trustzone nic301_addr_region_ctrl_registers
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap);
-set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0);
-set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1);
-set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb);
-
-// ************************************************************
-// Module i2c0 IIC
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0);
-set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0);
-set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0);
-set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0);
-set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0);
-set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0);
-set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0);
-set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0);
-set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0);
-set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0);
-set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0);
-
-// ************************************************************
-// Module i2c1 IIC
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0);
-set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0);
-set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0);
-set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0);
-set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0);
-set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0);
-set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0);
-set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0);
-set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0);
-set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0);
-set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0);
-
-// ************************************************************
-// Module l2cache L2Cpl310
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id);
-set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type);
-set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control);
-set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control);
-set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control);
-set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control);
-set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl);
-set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg);
-set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg);
-set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1);
-set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0);
-set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask);
-set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status);
-set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status);
-set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear);
-set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync);
-set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa);
-set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way);
-set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa);
-set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index);
-set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way);
-set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa);
-set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index);
-set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way);
-set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0);
-set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0);
-set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1);
-set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1);
-set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2);
-set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2);
-set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3);
-set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3);
-set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4);
-set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4);
-set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5);
-set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5);
-set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6);
-set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6);
-set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7);
-set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7);
-set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en);
-set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way);
-set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start);
-set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end);
-set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl);
-set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl);
-set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl);
-
-// ************************************************************
-// Module mpcore mpcore
-// doc version: 1.3
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER);
-set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER);
-set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register);
-set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State);
-set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register);
-set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register);
-set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC);
-set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register);
-set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR);
-set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR);
-set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR);
-set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR);
-set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR);
-set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR);
-set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR);
-set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR);
-set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR);
-set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0);
-set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1);
-set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register);
-set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register);
-set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0);
-set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1);
-set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register);
-set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register);
-set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register);
-set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register);
-set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register);
-set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register);
-set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register);
-set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register);
-set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register);
-set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register);
-set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register);
-set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR);
-set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR);
-set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR);
-set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0);
-set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1);
-set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2);
-set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0);
-set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1);
-set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2);
-set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0);
-set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1);
-set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2);
-set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0);
-set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1);
-set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2);
-set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0);
-set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1);
-set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2);
-set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0);
-set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1);
-set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2);
-set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0);
-set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1);
-set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2);
-set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3);
-set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4);
-set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5);
-set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6);
-set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7);
-set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8);
-set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9);
-set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10);
-set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11);
-set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12);
-set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13);
-set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14);
-set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15);
-set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16);
-set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17);
-set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18);
-set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19);
-set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20);
-set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21);
-set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22);
-set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23);
-set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0);
-set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1);
-set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2);
-set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3);
-set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4);
-set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5);
-set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6);
-set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7);
-set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8);
-set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9);
-set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10);
-set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11);
-set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12);
-set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13);
-set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14);
-set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15);
-set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16);
-set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17);
-set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18);
-set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19);
-set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20);
-set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21);
-set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22);
-set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23);
-set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0);
-set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1);
-set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2);
-set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3);
-set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4);
-set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5);
-set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status);
-set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0);
-set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1);
-set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR);
-set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4);
-set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5);
-set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6);
-set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7);
-set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0);
-set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1);
-set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2);
-set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3);
-set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0);
-set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1);
-set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2);
-set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3);
-
-// ************************************************************
-// Module ocm ocm
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL);
-set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS);
-set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS);
-set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL);
-
-// ************************************************************
-// Module qspi qspi
-// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller
-/// Design Specification document
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( qspi__Config_reg, val_qspi__Config_reg);
-set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG);
-set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG);
-set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG);
-set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG);
-set_reset_data( qspi__En_REG, val_qspi__En_REG);
-set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG);
-set_reset_data( qspi__TXD0, val_qspi__TXD0);
-set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG);
-set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG);
-set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG);
-set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG);
-set_reset_data( qspi__GPIO, val_qspi__GPIO);
-set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ);
-set_reset_data( qspi__TXD1, val_qspi__TXD1);
-set_reset_data( qspi__TXD2, val_qspi__TXD2);
-set_reset_data( qspi__TXD3, val_qspi__TXD3);
-set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG);
-set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS);
-set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID);
-
-// ************************************************************
-// Module sd0 sdio
-// doc version: 4.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register);
-set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count);
-set_reset_data( sd0__Argument, val_sd0__Argument);
-set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command);
-set_reset_data( sd0__Response0, val_sd0__Response0);
-set_reset_data( sd0__Response1, val_sd0__Response1);
-set_reset_data( sd0__Response2, val_sd0__Response2);
-set_reset_data( sd0__Response3, val_sd0__Response3);
-set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port);
-set_reset_data( sd0__Present_State, val_sd0__Present_State);
-set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
-set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset);
-set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status);
-set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable);
-set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
-set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status);
-set_reset_data( sd0__Capabilities, val_sd0__Capabilities);
-set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities);
-set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
-set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status);
-set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address);
-set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control);
-set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection);
-set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support);
-set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version);
-
-// ************************************************************
-// Module sd1 sdio
-// doc version: 4.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register);
-set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count);
-set_reset_data( sd1__Argument, val_sd1__Argument);
-set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command);
-set_reset_data( sd1__Response0, val_sd1__Response0);
-set_reset_data( sd1__Response1, val_sd1__Response1);
-set_reset_data( sd1__Response2, val_sd1__Response2);
-set_reset_data( sd1__Response3, val_sd1__Response3);
-set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port);
-set_reset_data( sd1__Present_State, val_sd1__Present_State);
-set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control);
-set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset);
-set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status);
-set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable);
-set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable);
-set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status);
-set_reset_data( sd1__Capabilities, val_sd1__Capabilities);
-set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities);
-set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status);
-set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status);
-set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address);
-set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control);
-set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection);
-set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support);
-set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version);
-
-// ************************************************************
-// Module slcr slcr
-// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( slcr__SCL, val_slcr__SCL);
-set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK);
-set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK);
-set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA);
-set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL);
-set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL);
-set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL);
-set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS);
-set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG);
-set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG);
-set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG);
-set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL);
-set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL);
-set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL);
-set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL);
-set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL);
-set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL);
-set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL);
-set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL);
-set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL);
-set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL);
-set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL);
-set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL);
-set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL);
-set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL);
-set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL);
-set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL);
-set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL);
-set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL);
-set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL);
-set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL);
-set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL);
-set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL);
-set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL);
-set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT);
-set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA);
-set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL);
-set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL);
-set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT);
-set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA);
-set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL);
-set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL);
-set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT);
-set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA);
-set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL);
-set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL);
-set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT);
-set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA);
-set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL);
-set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM);
-set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST);
-set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR);
-set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE);
-set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG);
-set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT);
-set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT);
-set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL);
-set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL);
-set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL);
-set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL);
-set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL);
-set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL);
-set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL);
-set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL);
-set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL);
-set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL);
-set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL);
-set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL);
-set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL);
-set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL);
-set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL);
-set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL);
-set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL);
-set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL);
-set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL);
-set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON);
-set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR);
-set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS);
-set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE);
-set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL);
-set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL);
-set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0);
-set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1);
-set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM);
-set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM);
-set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS);
-set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS);
-set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS);
-set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM);
-set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO);
-set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB);
-set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M);
-set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI);
-set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL);
-set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE);
-set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT);
-set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START);
-set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START);
-set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA);
-set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL);
-set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS);
-set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00);
-set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01);
-set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02);
-set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03);
-set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04);
-set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05);
-set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06);
-set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07);
-set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08);
-set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09);
-set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10);
-set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11);
-set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12);
-set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13);
-set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14);
-set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15);
-set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16);
-set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17);
-set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18);
-set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19);
-set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20);
-set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21);
-set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22);
-set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23);
-set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24);
-set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25);
-set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26);
-set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27);
-set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28);
-set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29);
-set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30);
-set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31);
-set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32);
-set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33);
-set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34);
-set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35);
-set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36);
-set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37);
-set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38);
-set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39);
-set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40);
-set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41);
-set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42);
-set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43);
-set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44);
-set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45);
-set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46);
-set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47);
-set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48);
-set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49);
-set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50);
-set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51);
-set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52);
-set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53);
-set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL);
-set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK);
-set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0);
-set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1);
-set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL);
-set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL);
-set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN);
-set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG);
-set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0);
-set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1);
-set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2);
-set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0);
-set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1);
-set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2);
-set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM);
-set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM);
-set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01);
-set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01);
-set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0);
-set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1);
-set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0);
-set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1);
-set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI);
-set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM);
-set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0);
-set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1);
-set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2);
-set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0);
-set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1);
-set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2);
-set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0);
-set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1);
-set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2);
-set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0);
-set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1);
-set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2);
-set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM);
-set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0);
-set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1);
-set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM);
-set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM);
-set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL);
-set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18);
-set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25);
-set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33);
-set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL);
-set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL);
-set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL);
-set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0);
-set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1);
-set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0);
-set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1);
-set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0);
-set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1);
-set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK);
-set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR);
-set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA);
-set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF);
-set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK);
-set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL);
-set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL);
-set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS);
-
-// ************************************************************
-// Module smcc pl353
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( smcc__memc_status, val_smcc__memc_status);
-set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg);
-set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set);
-set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr);
-set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd);
-set_reset_data( smcc__set_cycles, val_smcc__set_cycles);
-set_reset_data( smcc__set_opmode, val_smcc__set_opmode);
-set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0);
-set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1);
-set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0);
-set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0);
-set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1);
-set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1);
-set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0);
-set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0);
-set_reset_data( smcc__user_status, val_smcc__user_status);
-set_reset_data( smcc__user_config, val_smcc__user_config);
-set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0);
-set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0);
-set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0);
-set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0);
-set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0);
-set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0);
-set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0);
-set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0);
-set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0);
-set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0);
-set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1);
-set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1);
-set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1);
-set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1);
-set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1);
-set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1);
-set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1);
-set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1);
-set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1);
-set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1);
-set_reset_data( smcc__integration_test, val_smcc__integration_test);
-set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0);
-set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1);
-set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2);
-set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3);
-set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0);
-set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1);
-set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2);
-set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3);
-
-// ************************************************************
-// Module spi0 SPI
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0);
-set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0);
-set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0);
-set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0);
-set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0);
-set_reset_data( spi0__En_reg0, val_spi0__En_reg0);
-set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0);
-set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0);
-set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0);
-set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0);
-set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0);
-set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0);
-set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0);
-
-// ************************************************************
-// Module spi1 SPI
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0);
-set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0);
-set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0);
-set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0);
-set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0);
-set_reset_data( spi1__En_reg0, val_spi1__En_reg0);
-set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0);
-set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0);
-set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0);
-set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0);
-set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0);
-set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0);
-set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0);
-
-// ************************************************************
-// Module swdt swdt
-// doc version: 2.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( swdt__MODE, val_swdt__MODE);
-set_reset_data( swdt__CONTROL, val_swdt__CONTROL);
-set_reset_data( swdt__RESTART, val_swdt__RESTART);
-set_reset_data( swdt__STATUS, val_swdt__STATUS);
-
-// ************************************************************
-// Module ttc0 ttc
-// doc version: 2.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1);
-set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2);
-set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3);
-set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1);
-set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2);
-set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3);
-set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1);
-set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2);
-set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3);
-set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1);
-set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2);
-set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3);
-set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1);
-set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2);
-set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3);
-set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1);
-set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2);
-set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3);
-set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1);
-set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2);
-set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3);
-set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1);
-set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2);
-set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3);
-set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1);
-set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2);
-set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3);
-set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1);
-set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2);
-set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3);
-set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1);
-set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2);
-set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3);
-
-// ************************************************************
-// Module ttc1 ttc
-// doc version: 2.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1);
-set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2);
-set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3);
-set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1);
-set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2);
-set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3);
-set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1);
-set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2);
-set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3);
-set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1);
-set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2);
-set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3);
-set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1);
-set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2);
-set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3);
-set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1);
-set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2);
-set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3);
-set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1);
-set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2);
-set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3);
-set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1);
-set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2);
-set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3);
-set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1);
-set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2);
-set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3);
-set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1);
-set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2);
-set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3);
-set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1);
-set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2);
-set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3);
-
-// ************************************************************
-// Module uart0 UART
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0);
-set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0);
-set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0);
-set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0);
-set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0);
-set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0);
-set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0);
-set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0);
-set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0);
-set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0);
-set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0);
-set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0);
-set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0);
-set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0);
-set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0);
-set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0);
-set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0);
-set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0);
-
-// ************************************************************
-// Module uart1 UART
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0);
-set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0);
-set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0);
-set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0);
-set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0);
-set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0);
-set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0);
-set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0);
-set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0);
-set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0);
-set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0);
-set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0);
-set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0);
-set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0);
-set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0);
-set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0);
-set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0);
-set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0);
-
-// ************************************************************
-// Module usb0 usb
-// doc version: 1.3
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( usb0__ID, val_usb0__ID);
-set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL);
-set_reset_data( usb0__HWHOST, val_usb0__HWHOST);
-set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE);
-set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF);
-set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF);
-set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD);
-set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL);
-set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD);
-set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL);
-set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG);
-set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION);
-set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS);
-set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS);
-set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION);
-set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS);
-set_reset_data( usb0__USBCMD, val_usb0__USBCMD);
-set_reset_data( usb0__USBSTS, val_usb0__USBSTS);
-set_reset_data( usb0__USBINTR, val_usb0__USBINTR);
-set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX);
-set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR);
-set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR);
-set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL);
-set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE);
-set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING);
-set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING);
-set_reset_data( usb0__IC_USB, val_usb0__IC_USB);
-set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT);
-set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK);
-set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN);
-set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG);
-set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1);
-set_reset_data( usb0__OTGSC, val_usb0__OTGSC);
-set_reset_data( usb0__USBMODE, val_usb0__USBMODE);
-set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT);
-set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME);
-set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH);
-set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT);
-set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE);
-set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0);
-set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1);
-set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2);
-set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3);
-set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4);
-set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5);
-set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6);
-set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7);
-set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8);
-set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9);
-set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10);
-set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11);
-set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12);
-
-// ************************************************************
-// Module usb1 usb
-// doc version: 1.3
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-set_reset_data( usb1__ID, val_usb1__ID);
-set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL);
-set_reset_data( usb1__HWHOST, val_usb1__HWHOST);
-set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE);
-set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF);
-set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF);
-set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD);
-set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL);
-set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD);
-set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL);
-set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG);
-set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION);
-set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS);
-set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS);
-set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION);
-set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS);
-set_reset_data( usb1__USBCMD, val_usb1__USBCMD);
-set_reset_data( usb1__USBSTS, val_usb1__USBSTS);
-set_reset_data( usb1__USBINTR, val_usb1__USBINTR);
-set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX);
-set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR);
-set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR);
-set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL);
-set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE);
-set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING);
-set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING);
-set_reset_data( usb1__IC_USB, val_usb1__IC_USB);
-set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT);
-set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK);
-set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN);
-set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG);
-set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1);
-set_reset_data( usb1__OTGSC, val_usb1__OTGSC);
-set_reset_data( usb1__USBMODE, val_usb1__USBMODE);
-set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT);
-set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME);
-set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH);
-set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT);
-set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE);
-set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0);
-set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1);
-set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2);
-set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3);
-set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4);
-set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5);
-set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6);
-set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7);
-set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8);
-set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9);
-set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10);
-set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11);
-set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12);
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_reg_params.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_reg_params.v
deleted file mode 100755
index 22bf4b8faeeaf7bb05906fe2eca561f1e030c9e6..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_reg_params.v
+++ /dev/null
@@ -1,10519 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_reg_params.v
- *
- * Date : 2012-11
- *
- * Description : Parameters for Register Address and Default values.
- *
- *****************************************************************************/
-
-// Register default value info for chip pele_ps
-// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012
-// 54 modules, 2532 registers.
-
-
-// ************************************************************
-// Module afi0 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000;
-parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000;
-parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004;
-parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi0__AFI_RDQOS = 32'hF8008008;
-parameter val_afi0__AFI_RDQOS = 32'h00000000;
-parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF;
-
-parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C;
-parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi0__AFI_RDDEBUG = 32'hF8008010;
-parameter val_afi0__AFI_RDDEBUG = 32'h00000000;
-parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF;
-
-parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014;
-parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00;
-parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018;
-parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi0__AFI_WRQOS = 32'hF800801C;
-parameter val_afi0__AFI_WRQOS = 32'h00000000;
-parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF;
-
-parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020;
-parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi0__AFI_WRDEBUG = 32'hF8008024;
-parameter val_afi0__AFI_WRDEBUG = 32'h00000000;
-parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module afi1 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000;
-parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000;
-parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004;
-parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi1__AFI_RDQOS = 32'hF8009008;
-parameter val_afi1__AFI_RDQOS = 32'h00000000;
-parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF;
-
-parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C;
-parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi1__AFI_RDDEBUG = 32'hF8009010;
-parameter val_afi1__AFI_RDDEBUG = 32'h00000000;
-parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF;
-
-parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014;
-parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00;
-parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018;
-parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi1__AFI_WRQOS = 32'hF800901C;
-parameter val_afi1__AFI_WRQOS = 32'h00000000;
-parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF;
-
-parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020;
-parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi1__AFI_WRDEBUG = 32'hF8009024;
-parameter val_afi1__AFI_WRDEBUG = 32'h00000000;
-parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module afi2 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000;
-parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000;
-parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004;
-parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi2__AFI_RDQOS = 32'hF800A008;
-parameter val_afi2__AFI_RDQOS = 32'h00000000;
-parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF;
-
-parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C;
-parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi2__AFI_RDDEBUG = 32'hF800A010;
-parameter val_afi2__AFI_RDDEBUG = 32'h00000000;
-parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF;
-
-parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014;
-parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00;
-parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018;
-parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi2__AFI_WRQOS = 32'hF800A01C;
-parameter val_afi2__AFI_WRQOS = 32'h00000000;
-parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF;
-
-parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020;
-parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi2__AFI_WRDEBUG = 32'hF800A024;
-parameter val_afi2__AFI_WRDEBUG = 32'h00000000;
-parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module afi3 AFI
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000;
-parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000;
-parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004;
-parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi3__AFI_RDQOS = 32'hF800B008;
-parameter val_afi3__AFI_RDQOS = 32'h00000000;
-parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF;
-
-parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C;
-parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi3__AFI_RDDEBUG = 32'hF800B010;
-parameter val_afi3__AFI_RDDEBUG = 32'h00000000;
-parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF;
-
-parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014;
-parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00;
-parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF;
-
-parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018;
-parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007;
-parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF;
-
-parameter afi3__AFI_WRQOS = 32'hF800B01C;
-parameter val_afi3__AFI_WRQOS = 32'h00000000;
-parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF;
-
-parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020;
-parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000;
-parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF;
-
-parameter afi3__AFI_WRDEBUG = 32'hF800B024;
-parameter val_afi3__AFI_WRDEBUG = 32'h00000000;
-parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module can0 can
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter can0__SRR = 32'hE0008000;
-parameter val_can0__SRR = 32'h00000000;
-parameter mask_can0__SRR = 32'hFFFFFFFF;
-
-parameter can0__MSR = 32'hE0008004;
-parameter val_can0__MSR = 32'h00000000;
-parameter mask_can0__MSR = 32'hFFFFFFFF;
-
-parameter can0__BRPR = 32'hE0008008;
-parameter val_can0__BRPR = 32'h00000000;
-parameter mask_can0__BRPR = 32'hFFFFFFFF;
-
-parameter can0__BTR = 32'hE000800C;
-parameter val_can0__BTR = 32'h00000000;
-parameter mask_can0__BTR = 32'hFFFFFFFF;
-
-parameter can0__ECR = 32'hE0008010;
-parameter val_can0__ECR = 32'h00000000;
-parameter mask_can0__ECR = 32'hFFFFFFFF;
-
-parameter can0__ESR = 32'hE0008014;
-parameter val_can0__ESR = 32'h00000000;
-parameter mask_can0__ESR = 32'hFFFFFFFF;
-
-parameter can0__SR = 32'hE0008018;
-parameter val_can0__SR = 32'h00000001;
-parameter mask_can0__SR = 32'hFFFFFFFF;
-
-parameter can0__ISR = 32'hE000801C;
-parameter val_can0__ISR = 32'h00006000;
-parameter mask_can0__ISR = 32'hFFFFFFFF;
-
-parameter can0__IER = 32'hE0008020;
-parameter val_can0__IER = 32'h00000000;
-parameter mask_can0__IER = 32'hFFFFFFFF;
-
-parameter can0__ICR = 32'hE0008024;
-parameter val_can0__ICR = 32'h00000000;
-parameter mask_can0__ICR = 32'hFFFFFFFF;
-
-parameter can0__TCR = 32'hE0008028;
-parameter val_can0__TCR = 32'h00000000;
-parameter mask_can0__TCR = 32'hFFFFFFFF;
-
-parameter can0__WIR = 32'hE000802C;
-parameter val_can0__WIR = 32'h00003F3F;
-parameter mask_can0__WIR = 32'hFFFFFFFF;
-
-parameter can0__TXFIFO_ID = 32'hE0008030;
-parameter val_can0__TXFIFO_ID = 32'h00000000;
-parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF;
-
-parameter can0__TXFIFO_DLC = 32'hE0008034;
-parameter val_can0__TXFIFO_DLC = 32'h00000000;
-parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF;
-
-parameter can0__TXFIFO_DATA1 = 32'hE0008038;
-parameter val_can0__TXFIFO_DATA1 = 32'h00000000;
-parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF;
-
-parameter can0__TXFIFO_DATA2 = 32'hE000803C;
-parameter val_can0__TXFIFO_DATA2 = 32'h00000000;
-parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF;
-
-parameter can0__TXHPB_ID = 32'hE0008040;
-parameter val_can0__TXHPB_ID = 32'h00000000;
-parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF;
-
-parameter can0__TXHPB_DLC = 32'hE0008044;
-parameter val_can0__TXHPB_DLC = 32'h00000000;
-parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF;
-
-parameter can0__TXHPB_DATA1 = 32'hE0008048;
-parameter val_can0__TXHPB_DATA1 = 32'h00000000;
-parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF;
-
-parameter can0__TXHPB_DATA2 = 32'hE000804C;
-parameter val_can0__TXHPB_DATA2 = 32'h00000000;
-parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF;
-
-parameter can0__RXFIFO_ID = 32'hE0008050;
-parameter val_can0__RXFIFO_ID = 32'h00000000;
-parameter mask_can0__RXFIFO_ID = 32'h00000000;
-
-parameter can0__RXFIFO_DLC = 32'hE0008054;
-parameter val_can0__RXFIFO_DLC = 32'h00000000;
-parameter mask_can0__RXFIFO_DLC = 32'h00000000;
-
-parameter can0__RXFIFO_DATA1 = 32'hE0008058;
-parameter val_can0__RXFIFO_DATA1 = 32'h00000000;
-parameter mask_can0__RXFIFO_DATA1 = 32'h00000000;
-
-parameter can0__RXFIFO_DATA2 = 32'hE000805C;
-parameter val_can0__RXFIFO_DATA2 = 32'h00000000;
-parameter mask_can0__RXFIFO_DATA2 = 32'h00000000;
-
-parameter can0__AFR = 32'hE0008060;
-parameter val_can0__AFR = 32'h00000000;
-parameter mask_can0__AFR = 32'hFFFFFFFF;
-
-parameter can0__AFMR1 = 32'hE0008064;
-parameter val_can0__AFMR1 = 32'h00000000;
-parameter mask_can0__AFMR1 = 32'h00000000;
-
-parameter can0__AFIR1 = 32'hE0008068;
-parameter val_can0__AFIR1 = 32'h00000000;
-parameter mask_can0__AFIR1 = 32'h00000000;
-
-parameter can0__AFMR2 = 32'hE000806C;
-parameter val_can0__AFMR2 = 32'h00000000;
-parameter mask_can0__AFMR2 = 32'h00000000;
-
-parameter can0__AFIR2 = 32'hE0008070;
-parameter val_can0__AFIR2 = 32'h00000000;
-parameter mask_can0__AFIR2 = 32'h00000000;
-
-parameter can0__AFMR3 = 32'hE0008074;
-parameter val_can0__AFMR3 = 32'h00000000;
-parameter mask_can0__AFMR3 = 32'h00000000;
-
-parameter can0__AFIR3 = 32'hE0008078;
-parameter val_can0__AFIR3 = 32'h00000000;
-parameter mask_can0__AFIR3 = 32'h00000000;
-
-parameter can0__AFMR4 = 32'hE000807C;
-parameter val_can0__AFMR4 = 32'h00000000;
-parameter mask_can0__AFMR4 = 32'h00000000;
-
-parameter can0__AFIR4 = 32'hE0008080;
-parameter val_can0__AFIR4 = 32'h00000000;
-parameter mask_can0__AFIR4 = 32'h00000000;
-
-
-// ************************************************************
-// Module can1 can
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter can1__SRR = 32'hE0009000;
-parameter val_can1__SRR = 32'h00000000;
-parameter mask_can1__SRR = 32'hFFFFFFFF;
-
-parameter can1__MSR = 32'hE0009004;
-parameter val_can1__MSR = 32'h00000000;
-parameter mask_can1__MSR = 32'hFFFFFFFF;
-
-parameter can1__BRPR = 32'hE0009008;
-parameter val_can1__BRPR = 32'h00000000;
-parameter mask_can1__BRPR = 32'hFFFFFFFF;
-
-parameter can1__BTR = 32'hE000900C;
-parameter val_can1__BTR = 32'h00000000;
-parameter mask_can1__BTR = 32'hFFFFFFFF;
-
-parameter can1__ECR = 32'hE0009010;
-parameter val_can1__ECR = 32'h00000000;
-parameter mask_can1__ECR = 32'hFFFFFFFF;
-
-parameter can1__ESR = 32'hE0009014;
-parameter val_can1__ESR = 32'h00000000;
-parameter mask_can1__ESR = 32'hFFFFFFFF;
-
-parameter can1__SR = 32'hE0009018;
-parameter val_can1__SR = 32'h00000001;
-parameter mask_can1__SR = 32'hFFFFFFFF;
-
-parameter can1__ISR = 32'hE000901C;
-parameter val_can1__ISR = 32'h00006000;
-parameter mask_can1__ISR = 32'hFFFFFFFF;
-
-parameter can1__IER = 32'hE0009020;
-parameter val_can1__IER = 32'h00000000;
-parameter mask_can1__IER = 32'hFFFFFFFF;
-
-parameter can1__ICR = 32'hE0009024;
-parameter val_can1__ICR = 32'h00000000;
-parameter mask_can1__ICR = 32'hFFFFFFFF;
-
-parameter can1__TCR = 32'hE0009028;
-parameter val_can1__TCR = 32'h00000000;
-parameter mask_can1__TCR = 32'hFFFFFFFF;
-
-parameter can1__WIR = 32'hE000902C;
-parameter val_can1__WIR = 32'h00003F3F;
-parameter mask_can1__WIR = 32'hFFFFFFFF;
-
-parameter can1__TXFIFO_ID = 32'hE0009030;
-parameter val_can1__TXFIFO_ID = 32'h00000000;
-parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF;
-
-parameter can1__TXFIFO_DLC = 32'hE0009034;
-parameter val_can1__TXFIFO_DLC = 32'h00000000;
-parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF;
-
-parameter can1__TXFIFO_DATA1 = 32'hE0009038;
-parameter val_can1__TXFIFO_DATA1 = 32'h00000000;
-parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF;
-
-parameter can1__TXFIFO_DATA2 = 32'hE000903C;
-parameter val_can1__TXFIFO_DATA2 = 32'h00000000;
-parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF;
-
-parameter can1__TXHPB_ID = 32'hE0009040;
-parameter val_can1__TXHPB_ID = 32'h00000000;
-parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF;
-
-parameter can1__TXHPB_DLC = 32'hE0009044;
-parameter val_can1__TXHPB_DLC = 32'h00000000;
-parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF;
-
-parameter can1__TXHPB_DATA1 = 32'hE0009048;
-parameter val_can1__TXHPB_DATA1 = 32'h00000000;
-parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF;
-
-parameter can1__TXHPB_DATA2 = 32'hE000904C;
-parameter val_can1__TXHPB_DATA2 = 32'h00000000;
-parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF;
-
-parameter can1__RXFIFO_ID = 32'hE0009050;
-parameter val_can1__RXFIFO_ID = 32'h00000000;
-parameter mask_can1__RXFIFO_ID = 32'h00000000;
-
-parameter can1__RXFIFO_DLC = 32'hE0009054;
-parameter val_can1__RXFIFO_DLC = 32'h00000000;
-parameter mask_can1__RXFIFO_DLC = 32'h00000000;
-
-parameter can1__RXFIFO_DATA1 = 32'hE0009058;
-parameter val_can1__RXFIFO_DATA1 = 32'h00000000;
-parameter mask_can1__RXFIFO_DATA1 = 32'h00000000;
-
-parameter can1__RXFIFO_DATA2 = 32'hE000905C;
-parameter val_can1__RXFIFO_DATA2 = 32'h00000000;
-parameter mask_can1__RXFIFO_DATA2 = 32'h00000000;
-
-parameter can1__AFR = 32'hE0009060;
-parameter val_can1__AFR = 32'h00000000;
-parameter mask_can1__AFR = 32'hFFFFFFFF;
-
-parameter can1__AFMR1 = 32'hE0009064;
-parameter val_can1__AFMR1 = 32'h00000000;
-parameter mask_can1__AFMR1 = 32'h00000000;
-
-parameter can1__AFIR1 = 32'hE0009068;
-parameter val_can1__AFIR1 = 32'h00000000;
-parameter mask_can1__AFIR1 = 32'h00000000;
-
-parameter can1__AFMR2 = 32'hE000906C;
-parameter val_can1__AFMR2 = 32'h00000000;
-parameter mask_can1__AFMR2 = 32'h00000000;
-
-parameter can1__AFIR2 = 32'hE0009070;
-parameter val_can1__AFIR2 = 32'h00000000;
-parameter mask_can1__AFIR2 = 32'h00000000;
-
-parameter can1__AFMR3 = 32'hE0009074;
-parameter val_can1__AFMR3 = 32'h00000000;
-parameter mask_can1__AFMR3 = 32'h00000000;
-
-parameter can1__AFIR3 = 32'hE0009078;
-parameter val_can1__AFIR3 = 32'h00000000;
-parameter mask_can1__AFIR3 = 32'h00000000;
-
-parameter can1__AFMR4 = 32'hE000907C;
-parameter val_can1__AFMR4 = 32'h00000000;
-parameter mask_can1__AFMR4 = 32'h00000000;
-
-parameter can1__AFIR4 = 32'hE0009080;
-parameter val_can1__AFIR4 = 32'h00000000;
-parameter mask_can1__AFIR4 = 32'h00000000;
-
-
-// ************************************************************
-// Module ddrc ddrc
-// doc version: 1.25
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter ddrc__ddrc_ctrl = 32'hF8006000;
-parameter val_ddrc__ddrc_ctrl = 32'h00000200;
-parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF;
-
-parameter ddrc__Two_rank_cfg = 32'hF8006004;
-parameter val_ddrc__Two_rank_cfg = 32'h000C1076;
-parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF;
-
-parameter ddrc__HPR_reg = 32'hF8006008;
-parameter val_ddrc__HPR_reg = 32'h03C0780F;
-parameter mask_ddrc__HPR_reg = 32'h03FFFFFF;
-
-parameter ddrc__LPR_reg = 32'hF800600C;
-parameter val_ddrc__LPR_reg = 32'h03C0780F;
-parameter mask_ddrc__LPR_reg = 32'h03FFFFFF;
-
-parameter ddrc__WR_reg = 32'hF8006010;
-parameter val_ddrc__WR_reg = 32'h0007F80F;
-parameter mask_ddrc__WR_reg = 32'h03FFFFFF;
-
-parameter ddrc__DRAM_param_reg0 = 32'hF8006014;
-parameter val_ddrc__DRAM_param_reg0 = 32'h00041016;
-parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF;
-
-parameter ddrc__DRAM_param_reg1 = 32'hF8006018;
-parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9;
-parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF;
-
-parameter ddrc__DRAM_param_reg2 = 32'hF800601C;
-parameter val_ddrc__DRAM_param_reg2 = 32'h83015904;
-parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF;
-
-parameter ddrc__DRAM_param_reg3 = 32'hF8006020;
-parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0;
-parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF;
-
-parameter ddrc__DRAM_param_reg4 = 32'hF8006024;
-parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C;
-parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF;
-
-parameter ddrc__DRAM_init_param = 32'hF8006028;
-parameter val_ddrc__DRAM_init_param = 32'h00002007;
-parameter mask_ddrc__DRAM_init_param = 32'h00003FFF;
-
-parameter ddrc__DRAM_EMR_reg = 32'hF800602C;
-parameter val_ddrc__DRAM_EMR_reg = 32'h00000008;
-parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF;
-
-parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030;
-parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940;
-parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF;
-
-parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034;
-parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034;
-parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF;
-
-parameter ddrc__DRAM_disable_DQ = 32'hF8006038;
-parameter val_ddrc__DRAM_disable_DQ = 32'h00000000;
-parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF;
-
-parameter ddrc__DRAM_addr_map_bank = 32'hF800603C;
-parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77;
-parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF;
-
-parameter ddrc__DRAM_addr_map_col = 32'hF8006040;
-parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000;
-parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF;
-
-parameter ddrc__DRAM_addr_map_row = 32'hF8006044;
-parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555;
-parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF;
-
-parameter ddrc__DRAM_ODT_reg = 32'hF8006048;
-parameter val_ddrc__DRAM_ODT_reg = 32'h00000249;
-parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF;
-
-parameter ddrc__phy_dbg_reg = 32'hF800604C;
-parameter val_ddrc__phy_dbg_reg = 32'h00000000;
-parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF;
-
-parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050;
-parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200;
-parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF;
-
-parameter ddrc__mode_sts_reg = 32'hF8006054;
-parameter val_ddrc__mode_sts_reg = 32'h00000000;
-parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF;
-
-parameter ddrc__DLL_calib = 32'hF8006058;
-parameter val_ddrc__DLL_calib = 32'h00000101;
-parameter mask_ddrc__DLL_calib = 32'h0001FFFF;
-
-parameter ddrc__ODT_delay_hold = 32'hF800605C;
-parameter val_ddrc__ODT_delay_hold = 32'h00000023;
-parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF;
-
-parameter ddrc__ctrl_reg1 = 32'hF8006060;
-parameter val_ddrc__ctrl_reg1 = 32'h0000003E;
-parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF;
-
-parameter ddrc__ctrl_reg2 = 32'hF8006064;
-parameter val_ddrc__ctrl_reg2 = 32'h00020000;
-parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF;
-
-parameter ddrc__ctrl_reg3 = 32'hF8006068;
-parameter val_ddrc__ctrl_reg3 = 32'h00284027;
-parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF;
-
-parameter ddrc__ctrl_reg4 = 32'hF800606C;
-parameter val_ddrc__ctrl_reg4 = 32'h00001610;
-parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF;
-
-parameter ddrc__ctrl_reg5 = 32'hF8006078;
-parameter val_ddrc__ctrl_reg5 = 32'h00455111;
-parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF;
-
-parameter ddrc__ctrl_reg6 = 32'hF800607C;
-parameter val_ddrc__ctrl_reg6 = 32'h00032222;
-parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF;
-
-parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0;
-parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000;
-parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF;
-
-parameter ddrc__CHE_T_ZQ = 32'hF80060A4;
-parameter val_ddrc__CHE_T_ZQ = 32'h10300802;
-parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF;
-
-parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8;
-parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A;
-parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF;
-
-parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC;
-parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000;
-parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF;
-
-parameter ddrc__reg_2c = 32'hF80060B0;
-parameter val_ddrc__reg_2c = 32'h00000000;
-parameter mask_ddrc__reg_2c = 32'h1FFFFFFF;
-
-parameter ddrc__reg_2d = 32'hF80060B4;
-parameter val_ddrc__reg_2d = 32'h00000200;
-parameter mask_ddrc__reg_2d = 32'h000007FF;
-
-parameter ddrc__dfi_timing = 32'hF80060B8;
-parameter val_ddrc__dfi_timing = 32'h00200067;
-parameter mask_ddrc__dfi_timing = 32'h01FFFFFF;
-
-parameter ddrc__refresh_timer_2 = 32'hF80060BC;
-parameter val_ddrc__refresh_timer_2 = 32'h00000000;
-parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF;
-
-parameter ddrc__nc_timing = 32'hF80060C0;
-parameter val_ddrc__nc_timing = 32'h00000000;
-parameter mask_ddrc__nc_timing = 32'h003FFFFF;
-
-parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4;
-parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003;
-
-parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8;
-parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF;
-
-parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC;
-parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF;
-
-parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0;
-parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF;
-
-parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4;
-parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF;
-
-parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8;
-parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF;
-
-parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC;
-parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001;
-
-parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0;
-parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF;
-
-parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4;
-parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF;
-
-parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8;
-parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF;
-
-parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC;
-parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF;
-
-parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0;
-parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF;
-
-parameter ddrc__ECC_scrub = 32'hF80060F4;
-parameter val_ddrc__ECC_scrub = 32'h00000008;
-parameter mask_ddrc__ECC_scrub = 32'h0000000F;
-
-parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8;
-parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF;
-
-parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC;
-parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000;
-parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF;
-
-parameter ddrc__phy_rcvr_enable = 32'hF8006114;
-parameter val_ddrc__phy_rcvr_enable = 32'h00000000;
-parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF;
-
-parameter ddrc__PHY_Config0 = 32'hF8006118;
-parameter val_ddrc__PHY_Config0 = 32'h40000001;
-parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF;
-
-parameter ddrc__PHY_Config1 = 32'hF800611C;
-parameter val_ddrc__PHY_Config1 = 32'h40000001;
-parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF;
-
-parameter ddrc__PHY_Config2 = 32'hF8006120;
-parameter val_ddrc__PHY_Config2 = 32'h40000001;
-parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF;
-
-parameter ddrc__PHY_Config3 = 32'hF8006124;
-parameter val_ddrc__PHY_Config3 = 32'h40000001;
-parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF;
-
-parameter ddrc__phy_init_ratio0 = 32'hF800612C;
-parameter val_ddrc__phy_init_ratio0 = 32'h00000000;
-parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF;
-
-parameter ddrc__phy_init_ratio1 = 32'hF8006130;
-parameter val_ddrc__phy_init_ratio1 = 32'h00000000;
-parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF;
-
-parameter ddrc__phy_init_ratio2 = 32'hF8006134;
-parameter val_ddrc__phy_init_ratio2 = 32'h00000000;
-parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF;
-
-parameter ddrc__phy_init_ratio3 = 32'hF8006138;
-parameter val_ddrc__phy_init_ratio3 = 32'h00000000;
-parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF;
-
-parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140;
-parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040;
-parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF;
-
-parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144;
-parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040;
-parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF;
-
-parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148;
-parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040;
-parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF;
-
-parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C;
-parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040;
-parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF;
-
-parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154;
-parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000;
-parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF;
-
-parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158;
-parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000;
-parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF;
-
-parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C;
-parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000;
-parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF;
-
-parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160;
-parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000;
-parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF;
-
-parameter ddrc__phy_we_cfg0 = 32'hF8006168;
-parameter val_ddrc__phy_we_cfg0 = 32'h00000040;
-parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF;
-
-parameter ddrc__phy_we_cfg1 = 32'hF800616C;
-parameter val_ddrc__phy_we_cfg1 = 32'h00000040;
-parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF;
-
-parameter ddrc__phy_we_cfg2 = 32'hF8006170;
-parameter val_ddrc__phy_we_cfg2 = 32'h00000040;
-parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF;
-
-parameter ddrc__phy_we_cfg3 = 32'hF8006174;
-parameter val_ddrc__phy_we_cfg3 = 32'h00000040;
-parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF;
-
-parameter ddrc__wr_data_slv0 = 32'hF800617C;
-parameter val_ddrc__wr_data_slv0 = 32'h00000080;
-parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF;
-
-parameter ddrc__wr_data_slv1 = 32'hF8006180;
-parameter val_ddrc__wr_data_slv1 = 32'h00000080;
-parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF;
-
-parameter ddrc__wr_data_slv2 = 32'hF8006184;
-parameter val_ddrc__wr_data_slv2 = 32'h00000080;
-parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF;
-
-parameter ddrc__wr_data_slv3 = 32'hF8006188;
-parameter val_ddrc__wr_data_slv3 = 32'h00000080;
-parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF;
-
-parameter ddrc__reg_64 = 32'hF8006190;
-parameter val_ddrc__reg_64 = 32'h10020000;
-parameter mask_ddrc__reg_64 = 32'hFFFFFFFF;
-
-parameter ddrc__reg_65 = 32'hF8006194;
-parameter val_ddrc__reg_65 = 32'h00000000;
-parameter mask_ddrc__reg_65 = 32'h000FFFFF;
-
-parameter ddrc__reg69_6a0 = 32'hF80061A4;
-parameter val_ddrc__reg69_6a0 = 32'h000F0000;
-parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF;
-
-parameter ddrc__reg69_6a1 = 32'hF80061A8;
-parameter val_ddrc__reg69_6a1 = 32'h000F0000;
-parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF;
-
-parameter ddrc__reg6c_6d2 = 32'hF80061B0;
-parameter val_ddrc__reg6c_6d2 = 32'h000F0000;
-parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF;
-
-parameter ddrc__reg6c_6d3 = 32'hF80061B4;
-parameter val_ddrc__reg6c_6d3 = 32'h000F0000;
-parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF;
-
-parameter ddrc__reg6e_710 = 32'hF80061B8;
-parameter val_ddrc__reg6e_710 = 32'h00000000;
-parameter mask_ddrc__reg6e_710 = 32'h00000000;
-
-parameter ddrc__reg6e_711 = 32'hF80061BC;
-parameter val_ddrc__reg6e_711 = 32'h00000000;
-parameter mask_ddrc__reg6e_711 = 32'h00000000;
-
-parameter ddrc__reg6e_712 = 32'hF80061C0;
-parameter val_ddrc__reg6e_712 = 32'h00000000;
-parameter mask_ddrc__reg6e_712 = 32'h00000000;
-
-parameter ddrc__reg6e_713 = 32'hF80061C4;
-parameter val_ddrc__reg6e_713 = 32'h00000000;
-parameter mask_ddrc__reg6e_713 = 32'h00000000;
-
-parameter ddrc__phy_dll_sts0 = 32'hF80061CC;
-parameter val_ddrc__phy_dll_sts0 = 32'h00000000;
-parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF;
-
-parameter ddrc__phy_dll_sts1 = 32'hF80061D0;
-parameter val_ddrc__phy_dll_sts1 = 32'h00000000;
-parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF;
-
-parameter ddrc__phy_dll_sts2 = 32'hF80061D4;
-parameter val_ddrc__phy_dll_sts2 = 32'h00000000;
-parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF;
-
-parameter ddrc__phy_dll_sts3 = 32'hF80061D8;
-parameter val_ddrc__phy_dll_sts3 = 32'h00000000;
-parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF;
-
-parameter ddrc__dll_lock_sts = 32'hF80061E0;
-parameter val_ddrc__dll_lock_sts = 32'h00000000;
-parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF;
-
-parameter ddrc__phy_ctrl_sts = 32'hF80061E4;
-parameter val_ddrc__phy_ctrl_sts = 32'h00000000;
-parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000;
-
-parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8;
-parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000;
-parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF;
-
-parameter ddrc__axi_id = 32'hF8006200;
-parameter val_ddrc__axi_id = 32'h00153042;
-parameter mask_ddrc__axi_id = 32'h03FFFFFF;
-
-parameter ddrc__page_mask = 32'hF8006204;
-parameter val_ddrc__page_mask = 32'h00000000;
-parameter mask_ddrc__page_mask = 32'hFFFFFFFF;
-
-parameter ddrc__axi_priority_wr_port0 = 32'hF8006208;
-parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF;
-parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF;
-
-parameter ddrc__axi_priority_wr_port1 = 32'hF800620C;
-parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF;
-parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF;
-
-parameter ddrc__axi_priority_wr_port2 = 32'hF8006210;
-parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF;
-parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF;
-
-parameter ddrc__axi_priority_wr_port3 = 32'hF8006214;
-parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF;
-parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF;
-
-parameter ddrc__axi_priority_rd_port0 = 32'hF8006218;
-parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF;
-parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF;
-
-parameter ddrc__axi_priority_rd_port1 = 32'hF800621C;
-parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF;
-parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF;
-
-parameter ddrc__axi_priority_rd_port2 = 32'hF8006220;
-parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF;
-parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF;
-
-parameter ddrc__axi_priority_rd_port3 = 32'hF8006224;
-parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF;
-parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF;
-
-parameter ddrc__AHB_priority_cfg0 = 32'hF8006248;
-parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF;
-parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF;
-
-parameter ddrc__AHB_priority_cfg1 = 32'hF800624C;
-parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF;
-parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF;
-
-parameter ddrc__AHB_priority_cfg2 = 32'hF8006250;
-parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF;
-parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF;
-
-parameter ddrc__AHB_priority_cfg3 = 32'hF8006254;
-parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF;
-parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF;
-
-parameter ddrc__perf_mon0 = 32'hF8006260;
-parameter val_ddrc__perf_mon0 = 32'h00000000;
-parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF;
-
-parameter ddrc__perf_mon1 = 32'hF8006264;
-parameter val_ddrc__perf_mon1 = 32'h00000000;
-parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF;
-
-parameter ddrc__perf_mon2 = 32'hF8006268;
-parameter val_ddrc__perf_mon2 = 32'h00000000;
-parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF;
-
-parameter ddrc__perf_mon3 = 32'hF800626C;
-parameter val_ddrc__perf_mon3 = 32'h00000000;
-parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF;
-
-parameter ddrc__perf_mon20 = 32'hF8006270;
-parameter val_ddrc__perf_mon20 = 32'h00000000;
-parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF;
-
-parameter ddrc__perf_mon21 = 32'hF8006274;
-parameter val_ddrc__perf_mon21 = 32'h00000000;
-parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF;
-
-parameter ddrc__perf_mon22 = 32'hF8006278;
-parameter val_ddrc__perf_mon22 = 32'h00000000;
-parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF;
-
-parameter ddrc__perf_mon23 = 32'hF800627C;
-parameter val_ddrc__perf_mon23 = 32'h00000000;
-parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF;
-
-parameter ddrc__perf_mon30 = 32'hF8006280;
-parameter val_ddrc__perf_mon30 = 32'h00000000;
-parameter mask_ddrc__perf_mon30 = 32'h0000FFFF;
-
-parameter ddrc__perf_mon31 = 32'hF8006284;
-parameter val_ddrc__perf_mon31 = 32'h00000000;
-parameter mask_ddrc__perf_mon31 = 32'h0000FFFF;
-
-parameter ddrc__perf_mon32 = 32'hF8006288;
-parameter val_ddrc__perf_mon32 = 32'h00000000;
-parameter mask_ddrc__perf_mon32 = 32'h0000FFFF;
-
-parameter ddrc__perf_mon33 = 32'hF800628C;
-parameter val_ddrc__perf_mon33 = 32'h00000000;
-parameter mask_ddrc__perf_mon33 = 32'h0000FFFF;
-
-parameter ddrc__trusted_mem_cfg = 32'hF8006290;
-parameter val_ddrc__trusted_mem_cfg = 32'h00000000;
-parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF;
-
-parameter ddrc__excl_access_cfg0 = 32'hF8006294;
-parameter val_ddrc__excl_access_cfg0 = 32'h00000000;
-parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF;
-
-parameter ddrc__excl_access_cfg1 = 32'hF8006298;
-parameter val_ddrc__excl_access_cfg1 = 32'h00000000;
-parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF;
-
-parameter ddrc__excl_access_cfg2 = 32'hF800629C;
-parameter val_ddrc__excl_access_cfg2 = 32'h00000000;
-parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF;
-
-parameter ddrc__excl_access_cfg3 = 32'hF80062A0;
-parameter val_ddrc__excl_access_cfg3 = 32'h00000000;
-parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF;
-
-parameter ddrc__mode_reg_read = 32'hF80062A4;
-parameter val_ddrc__mode_reg_read = 32'h00000000;
-parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF;
-
-parameter ddrc__lpddr_ctrl0 = 32'hF80062A8;
-parameter val_ddrc__lpddr_ctrl0 = 32'h00000000;
-parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF;
-
-parameter ddrc__lpddr_ctrl1 = 32'hF80062AC;
-parameter val_ddrc__lpddr_ctrl1 = 32'h00000000;
-parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF;
-
-parameter ddrc__lpddr_ctrl2 = 32'hF80062B0;
-parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015;
-parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF;
-
-parameter ddrc__lpddr_ctrl3 = 32'hF80062B4;
-parameter val_ddrc__lpddr_ctrl3 = 32'h00000601;
-parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF;
-
-parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8;
-parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444;
-parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF;
-
-parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC;
-parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888;
-parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF;
-
-parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0;
-parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444;
-parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF;
-
-
-// ************************************************************
-// Module debug_axim axim
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_axim__GLOBAL_CTRL = 32'hF880C000;
-parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002;
-parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003;
-
-parameter debug_axim__GLOBAL_STATUS = 32'hF880C004;
-parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000;
-parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3;
-
-parameter debug_axim__FILTER_CTRL = 32'hF880C010;
-parameter val_debug_axim__FILTER_CTRL = 32'h00000000;
-parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F;
-
-parameter debug_axim__TRIGGER_CTRL = 32'hF880C020;
-parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000;
-parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF;
-
-parameter debug_axim__TRIGGER_STATUS = 32'hF880C024;
-parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000;
-parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003;
-
-parameter debug_axim__PACKET_CTRL = 32'hF880C030;
-parameter val_debug_axim__PACKET_CTRL = 32'h00070000;
-parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF;
-
-parameter debug_axim__TOUT_CTRL = 32'hF880C040;
-parameter val_debug_axim__TOUT_CTRL = 32'h00000000;
-parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F;
-
-parameter debug_axim__TOUT_THRESH = 32'hF880C044;
-parameter val_debug_axim__TOUT_THRESH = 32'h00008000;
-parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF;
-
-parameter debug_axim__FIFO_CURRENT = 32'hF880C050;
-parameter val_debug_axim__FIFO_CURRENT = 32'h80000000;
-parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF;
-
-parameter debug_axim__FIFO_HYSTER = 32'hF880C054;
-parameter val_debug_axim__FIFO_HYSTER = 32'h00000100;
-parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF;
-
-parameter debug_axim__SYNC_CURRENT = 32'hF880C060;
-parameter val_debug_axim__SYNC_CURRENT = 32'h00000000;
-parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF;
-
-parameter debug_axim__SYNC_RELOAD = 32'hF880C064;
-parameter val_debug_axim__SYNC_RELOAD = 32'h00000800;
-parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF;
-
-parameter debug_axim__TSTMP_CURRENT = 32'hF880C070;
-parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000;
-parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000;
-
-parameter debug_axim__ADDR0_MASK = 32'hF880C200;
-parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR0_LOWER = 32'hF880C204;
-parameter val_debug_axim__ADDR0_LOWER = 32'h00000000;
-parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR0_UPPER = 32'hF880C208;
-parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR0_MISC = 32'hF880C20C;
-parameter val_debug_axim__ADDR0_MISC = 32'h00000000;
-parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF;
-
-parameter debug_axim__ADDR1_MASK = 32'hF880C210;
-parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR1_LOWER = 32'hF880C214;
-parameter val_debug_axim__ADDR1_LOWER = 32'h00000000;
-parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR1_UPPER = 32'hF880C218;
-parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR1_MISC = 32'hF880C21C;
-parameter val_debug_axim__ADDR1_MISC = 32'h00000000;
-parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF;
-
-parameter debug_axim__ADDR2_MASK = 32'hF880C220;
-parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR2_LOWER = 32'hF880C224;
-parameter val_debug_axim__ADDR2_LOWER = 32'h00000000;
-parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR2_UPPER = 32'hF880C228;
-parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR2_MISC = 32'hF880C22C;
-parameter val_debug_axim__ADDR2_MISC = 32'h00000000;
-parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF;
-
-parameter debug_axim__ADDR3_MASK = 32'hF880C230;
-parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR3_LOWER = 32'hF880C234;
-parameter val_debug_axim__ADDR3_LOWER = 32'h00000000;
-parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR3_UPPER = 32'hF880C238;
-parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC;
-parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF;
-
-parameter debug_axim__ADDR3_MISC = 32'hF880C23C;
-parameter val_debug_axim__ADDR3_MISC = 32'h00000000;
-parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF;
-
-parameter debug_axim__ID0_MASK = 32'hF880C300;
-parameter val_debug_axim__ID0_MASK = 32'h000003FF;
-parameter mask_debug_axim__ID0_MASK = 32'h000003FF;
-
-parameter debug_axim__ID0_LOWER = 32'hF880C304;
-parameter val_debug_axim__ID0_LOWER = 32'h00000000;
-parameter mask_debug_axim__ID0_LOWER = 32'h000003FF;
-
-parameter debug_axim__ID0_UPPER = 32'hF880C308;
-parameter val_debug_axim__ID0_UPPER = 32'h000003FF;
-parameter mask_debug_axim__ID0_UPPER = 32'h000003FF;
-
-parameter debug_axim__ID0_MISC = 32'hF880C30C;
-parameter val_debug_axim__ID0_MISC = 32'h00000000;
-parameter mask_debug_axim__ID0_MISC = 32'h00003FFF;
-
-parameter debug_axim__ID1_MASK = 32'hF880C310;
-parameter val_debug_axim__ID1_MASK = 32'h000003FF;
-parameter mask_debug_axim__ID1_MASK = 32'h000003FF;
-
-parameter debug_axim__ID1_LOWER = 32'hF880C314;
-parameter val_debug_axim__ID1_LOWER = 32'h00000000;
-parameter mask_debug_axim__ID1_LOWER = 32'h000003FF;
-
-parameter debug_axim__ID1_UPPER = 32'hF880C318;
-parameter val_debug_axim__ID1_UPPER = 32'h000003FF;
-parameter mask_debug_axim__ID1_UPPER = 32'h000003FF;
-
-parameter debug_axim__ID1_MISC = 32'hF880C31C;
-parameter val_debug_axim__ID1_MISC = 32'h00000000;
-parameter mask_debug_axim__ID1_MISC = 32'h00003FFF;
-
-parameter debug_axim__ID2_MASK = 32'hF880C320;
-parameter val_debug_axim__ID2_MASK = 32'h000003FF;
-parameter mask_debug_axim__ID2_MASK = 32'h000003FF;
-
-parameter debug_axim__ID2_LOWER = 32'hF880C324;
-parameter val_debug_axim__ID2_LOWER = 32'h00000000;
-parameter mask_debug_axim__ID2_LOWER = 32'h000003FF;
-
-parameter debug_axim__ID2_UPPER = 32'hF880C328;
-parameter val_debug_axim__ID2_UPPER = 32'h000003FF;
-parameter mask_debug_axim__ID2_UPPER = 32'h000003FF;
-
-parameter debug_axim__ID2_MISC = 32'hF880C32C;
-parameter val_debug_axim__ID2_MISC = 32'h00000000;
-parameter mask_debug_axim__ID2_MISC = 32'h00003FFF;
-
-parameter debug_axim__ID3_MASK = 32'hF880C330;
-parameter val_debug_axim__ID3_MASK = 32'h000003FF;
-parameter mask_debug_axim__ID3_MASK = 32'h000003FF;
-
-parameter debug_axim__ID3_LOWER = 32'hF880C334;
-parameter val_debug_axim__ID3_LOWER = 32'h00000000;
-parameter mask_debug_axim__ID3_LOWER = 32'h000003FF;
-
-parameter debug_axim__ID3_UPPER = 32'hF880C338;
-parameter val_debug_axim__ID3_UPPER = 32'h000003FF;
-parameter mask_debug_axim__ID3_UPPER = 32'h000003FF;
-
-parameter debug_axim__ID3_MISC = 32'hF880C33C;
-parameter val_debug_axim__ID3_MISC = 32'h00000000;
-parameter mask_debug_axim__ID3_MISC = 32'h00003FFF;
-
-parameter debug_axim__AXI_SEL = 32'hF880C800;
-parameter val_debug_axim__AXI_SEL = 32'h00000000;
-parameter mask_debug_axim__AXI_SEL = 32'h00000007;
-
-parameter debug_axim__IT_TRIGOUT = 32'hF880CED0;
-parameter val_debug_axim__IT_TRIGOUT = 32'h00000000;
-parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001;
-
-parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4;
-parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000;
-parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000;
-
-parameter debug_axim__IT_TRIGIN = 32'hF880CED8;
-parameter val_debug_axim__IT_TRIGIN = 32'h00000000;
-parameter mask_debug_axim__IT_TRIGIN = 32'h00000000;
-
-parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC;
-parameter val_debug_axim__IT_TRIGINACK = 32'h00000000;
-parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001;
-
-parameter debug_axim__IT_ATBDATA = 32'hF880CEEC;
-parameter val_debug_axim__IT_ATBDATA = 32'h00000000;
-parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F;
-
-parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0;
-parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000;
-parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000;
-
-parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4;
-parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000;
-parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F;
-
-parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8;
-parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000;
-parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF;
-
-parameter debug_axim__IT_CTRL = 32'hF880CF00;
-parameter val_debug_axim__IT_CTRL = 32'h00000000;
-parameter mask_debug_axim__IT_CTRL = 32'h00000001;
-
-parameter debug_axim__CLAIM_SET = 32'hF880CFA0;
-parameter val_debug_axim__CLAIM_SET = 32'h00000001;
-parameter mask_debug_axim__CLAIM_SET = 32'h0000000F;
-
-parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4;
-parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000;
-parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F;
-
-parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0;
-parameter val_debug_axim__LOCK_ACCESS = 32'h00000000;
-parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF;
-
-parameter debug_axim__LOCK_STATUS = 32'hF880CFB4;
-parameter val_debug_axim__LOCK_STATUS = 32'h00000003;
-parameter mask_debug_axim__LOCK_STATUS = 32'h00000007;
-
-parameter debug_axim__AUTH_STATUS = 32'hF880CFB8;
-parameter val_debug_axim__AUTH_STATUS = 32'h00000000;
-parameter mask_debug_axim__AUTH_STATUS = 32'h00000033;
-
-parameter debug_axim__DEV_ID = 32'hF880CFC8;
-parameter val_debug_axim__DEV_ID = 32'h00000000;
-parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF;
-
-parameter debug_axim__DEV_TYPE = 32'hF880CFCC;
-parameter val_debug_axim__DEV_TYPE = 32'h00000043;
-parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID4 = 32'hF880CFD0;
-parameter val_debug_axim__PERIPHID4 = 32'h00000003;
-parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID5 = 32'hF880CFD4;
-parameter val_debug_axim__PERIPHID5 = 32'h00000000;
-parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID6 = 32'hF880CFD8;
-parameter val_debug_axim__PERIPHID6 = 32'h00000000;
-parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID7 = 32'hF880CFDC;
-parameter val_debug_axim__PERIPHID7 = 32'h00000000;
-parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID0 = 32'hF880CFE0;
-parameter val_debug_axim__PERIPHID0 = 32'h000000B2;
-parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID1 = 32'hF880CFE4;
-parameter val_debug_axim__PERIPHID1 = 32'h00000093;
-parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID2 = 32'hF880CFE8;
-parameter val_debug_axim__PERIPHID2 = 32'h00000008;
-parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF;
-
-parameter debug_axim__PERIPHID3 = 32'hF880CFEC;
-parameter val_debug_axim__PERIPHID3 = 32'h00000002;
-parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF;
-
-parameter debug_axim__COMPID0 = 32'hF880CFF0;
-parameter val_debug_axim__COMPID0 = 32'h0000000D;
-parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF;
-
-parameter debug_axim__COMPID1 = 32'hF880CFF4;
-parameter val_debug_axim__COMPID1 = 32'h00000090;
-parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF;
-
-parameter debug_axim__COMPID2 = 32'hF880CFF8;
-parameter val_debug_axim__COMPID2 = 32'h00000005;
-parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF;
-
-parameter debug_axim__COMPID3 = 32'hF880CFFC;
-parameter val_debug_axim__COMPID3 = 32'h000000B1;
-parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module debug_cpu_cti0 cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000;
-parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001;
-
-parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010;
-parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF;
-
-parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014;
-parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018;
-parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C;
-parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020;
-parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024;
-parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028;
-parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C;
-parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030;
-parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034;
-parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038;
-parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C;
-parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0;
-parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4;
-parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8;
-parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC;
-parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0;
-parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4;
-parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8;
-parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC;
-parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130;
-parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000;
-
-parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134;
-parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF;
-
-parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138;
-parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000;
-
-parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C;
-parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTIGATE = 32'hF8898140;
-parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F;
-parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F;
-
-parameter debug_cpu_cti0__ASICCTL = 32'hF8898144;
-parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000;
-parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF;
-
-parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC;
-parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F;
-
-parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0;
-parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF;
-
-parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4;
-parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F;
-
-parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8;
-parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF;
-
-parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC;
-parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F;
-
-parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0;
-parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF;
-
-parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4;
-parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F;
-
-parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8;
-parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF;
-
-parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00;
-parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000;
-parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001;
-
-parameter debug_cpu_cti0__CTSR = 32'hF8898FA0;
-parameter val_debug_cpu_cti0__CTSR = 32'h0000000F;
-parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F;
-
-parameter debug_cpu_cti0__CTCR = 32'hF8898FA4;
-parameter val_debug_cpu_cti0__CTCR = 32'h00000000;
-parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F;
-
-parameter debug_cpu_cti0__LAR = 32'hF8898FB0;
-parameter val_debug_cpu_cti0__LAR = 32'h00000000;
-parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF;
-
-parameter debug_cpu_cti0__LSR = 32'hF8898FB4;
-parameter val_debug_cpu_cti0__LSR = 32'h00000003;
-parameter mask_debug_cpu_cti0__LSR = 32'h00000007;
-
-parameter debug_cpu_cti0__ASR = 32'hF8898FB8;
-parameter val_debug_cpu_cti0__ASR = 32'h00000005;
-parameter mask_debug_cpu_cti0__ASR = 32'h00000005;
-
-parameter debug_cpu_cti0__DEVID = 32'hF8898FC8;
-parameter val_debug_cpu_cti0__DEVID = 32'h00040800;
-parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF;
-
-parameter debug_cpu_cti0__DTIR = 32'hF8898FCC;
-parameter val_debug_cpu_cti0__DTIR = 32'h00000014;
-parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0;
-parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004;
-parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4;
-parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000;
-parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8;
-parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000;
-parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC;
-parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000;
-parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0;
-parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006;
-parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4;
-parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8;
-parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B;
-parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF;
-
-parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC;
-parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000;
-parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF;
-
-parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0;
-parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D;
-parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF;
-
-parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4;
-parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090;
-parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF;
-
-parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8;
-parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005;
-parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF;
-
-parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC;
-parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1;
-parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_cpu_cti1 cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000;
-parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001;
-
-parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010;
-parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF;
-
-parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014;
-parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018;
-parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C;
-parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020;
-parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024;
-parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028;
-parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C;
-parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030;
-parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034;
-parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038;
-parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C;
-parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0;
-parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4;
-parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8;
-parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC;
-parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0;
-parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4;
-parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8;
-parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC;
-parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130;
-parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000;
-
-parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134;
-parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF;
-
-parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138;
-parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000;
-
-parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C;
-parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTIGATE = 32'hF8899140;
-parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F;
-parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F;
-
-parameter debug_cpu_cti1__ASICCTL = 32'hF8899144;
-parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000;
-parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF;
-
-parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC;
-parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F;
-
-parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0;
-parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF;
-
-parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4;
-parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F;
-
-parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8;
-parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF;
-
-parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC;
-parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F;
-
-parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0;
-parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF;
-
-parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4;
-parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F;
-
-parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8;
-parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF;
-
-parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00;
-parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000;
-parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001;
-
-parameter debug_cpu_cti1__CTSR = 32'hF8899FA0;
-parameter val_debug_cpu_cti1__CTSR = 32'h0000000F;
-parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F;
-
-parameter debug_cpu_cti1__CTCR = 32'hF8899FA4;
-parameter val_debug_cpu_cti1__CTCR = 32'h00000000;
-parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F;
-
-parameter debug_cpu_cti1__LAR = 32'hF8899FB0;
-parameter val_debug_cpu_cti1__LAR = 32'h00000000;
-parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF;
-
-parameter debug_cpu_cti1__LSR = 32'hF8899FB4;
-parameter val_debug_cpu_cti1__LSR = 32'h00000003;
-parameter mask_debug_cpu_cti1__LSR = 32'h00000007;
-
-parameter debug_cpu_cti1__ASR = 32'hF8899FB8;
-parameter val_debug_cpu_cti1__ASR = 32'h00000005;
-parameter mask_debug_cpu_cti1__ASR = 32'h00000005;
-
-parameter debug_cpu_cti1__DEVID = 32'hF8899FC8;
-parameter val_debug_cpu_cti1__DEVID = 32'h00040800;
-parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF;
-
-parameter debug_cpu_cti1__DTIR = 32'hF8899FCC;
-parameter val_debug_cpu_cti1__DTIR = 32'h00000014;
-parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0;
-parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004;
-parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4;
-parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000;
-parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8;
-parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000;
-parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC;
-parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000;
-parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0;
-parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006;
-parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4;
-parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8;
-parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B;
-parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF;
-
-parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC;
-parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000;
-parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF;
-
-parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0;
-parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D;
-parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF;
-
-parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4;
-parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090;
-parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF;
-
-parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8;
-parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005;
-parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF;
-
-parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC;
-parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1;
-parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_cpu_pmu0 cortexa9_pmu
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000;
-parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004;
-parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008;
-parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C;
-parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010;
-parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014;
-parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C;
-parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400;
-parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404;
-parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408;
-parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C;
-parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410;
-parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414;
-parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00;
-parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20;
-parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40;
-parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60;
-parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80;
-parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0;
-parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000;
-
-parameter debug_cpu_pmu0__PMCR = 32'hF8891E04;
-parameter val_debug_cpu_pmu0__PMCR = 32'h41093000;
-parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08;
-parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000;
-parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module debug_cpu_pmu1 cortexa9_pmu
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000;
-parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004;
-parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008;
-parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C;
-parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010;
-parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014;
-parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C;
-parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400;
-parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404;
-parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408;
-parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C;
-parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410;
-parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414;
-parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00;
-parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20;
-parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40;
-parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60;
-parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80;
-parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0;
-parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000;
-
-parameter debug_cpu_pmu1__PMCR = 32'hF8893E04;
-parameter val_debug_cpu_pmu1__PMCR = 32'h41093000;
-parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF;
-
-parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08;
-parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000;
-parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module debug_cpu_ptm0 ptm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cpu_ptm0__ETMCR = 32'hF889C000;
-parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400;
-parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF;
-
-parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004;
-parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004;
-parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008;
-parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMSR = 32'hF889C010;
-parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F;
-
-parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014;
-parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF;
-
-parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018;
-parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF;
-
-parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024;
-parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040;
-parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044;
-parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048;
-parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C;
-parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050;
-parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054;
-parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058;
-parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C;
-parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080;
-parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084;
-parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088;
-parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C;
-parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090;
-parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094;
-parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098;
-parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C;
-parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140;
-parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144;
-parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150;
-parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000;
-parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF;
-
-parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154;
-parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000;
-parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF;
-
-parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160;
-parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164;
-parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170;
-parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174;
-parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180;
-parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184;
-parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188;
-parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C;
-parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190;
-parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194;
-parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C;
-parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003;
-
-parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0;
-parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4;
-parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0;
-parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCIDCVR1 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC;
-parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0;
-parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400;
-parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF;
-
-parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4;
-parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300;
-parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8;
-parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2;
-parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF;
-
-parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC;
-parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF;
-
-parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC;
-parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F;
-
-parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200;
-parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F;
-
-parameter debug_cpu_ptm0__OSLSR = 32'hF889C304;
-parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314;
-parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001;
-parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC;
-parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF;
-
-parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0;
-parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020;
-
-parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8;
-parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001;
-
-parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC;
-parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F;
-
-parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0;
-parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000;
-
-parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4;
-parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F;
-
-parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8;
-parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF;
-
-parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00;
-parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001;
-
-parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0;
-parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF;
-parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF;
-
-parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4;
-parameter val_debug_cpu_ptm0__CTCR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF;
-
-parameter debug_cpu_ptm0__LAR = 32'hF889CFB0;
-parameter val_debug_cpu_ptm0__LAR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__LSR = 32'hF889CFB4;
-parameter val_debug_cpu_ptm0__LSR = 32'h00000003;
-parameter mask_debug_cpu_ptm0__LSR = 32'h00000007;
-
-parameter debug_cpu_ptm0__ASR = 32'hF889CFB8;
-parameter val_debug_cpu_ptm0__ASR = 32'h00000000;
-parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3;
-
-parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8;
-parameter val_debug_cpu_ptm0__DEVID = 32'h00000000;
-parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC;
-parameter val_debug_cpu_ptm0__DTIR = 32'h00000013;
-parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0;
-parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004;
-parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4;
-parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8;
-parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC;
-parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0;
-parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050;
-parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4;
-parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8;
-parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B;
-parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC;
-parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000;
-parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0;
-parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D;
-parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4;
-parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090;
-parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8;
-parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005;
-parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF;
-
-parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC;
-parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1;
-parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_cpu_ptm1 ptm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cpu_ptm1__ETMCR = 32'hF889D000;
-parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400;
-parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF;
-
-parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004;
-parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004;
-parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008;
-parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMSR = 32'hF889D010;
-parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F;
-
-parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014;
-parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF;
-
-parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018;
-parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF;
-
-parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024;
-parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040;
-parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044;
-parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048;
-parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C;
-parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050;
-parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054;
-parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058;
-parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C;
-parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080;
-parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084;
-parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088;
-parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C;
-parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090;
-parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094;
-parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098;
-parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C;
-parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140;
-parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144;
-parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150;
-parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000;
-parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF;
-
-parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154;
-parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000;
-parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF;
-
-parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160;
-parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164;
-parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170;
-parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174;
-parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF;
-
-parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180;
-parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184;
-parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188;
-parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C;
-parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190;
-parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194;
-parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C;
-parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003;
-
-parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0;
-parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4;
-parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF;
-
-parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0;
-parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC;
-parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0;
-parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400;
-parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF;
-
-parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4;
-parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300;
-parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8;
-parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2;
-parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF;
-
-parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC;
-parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF;
-
-parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC;
-parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F;
-
-parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200;
-parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F;
-
-parameter debug_cpu_ptm1__OSLSR = 32'hF889D304;
-parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314;
-parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001;
-parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC;
-parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF;
-
-parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0;
-parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020;
-
-parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8;
-parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001;
-
-parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC;
-parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F;
-
-parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0;
-parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000;
-
-parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4;
-parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F;
-
-parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8;
-parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF;
-
-parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00;
-parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001;
-
-parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0;
-parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF;
-parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF;
-
-parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4;
-parameter val_debug_cpu_ptm1__CTCR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF;
-
-parameter debug_cpu_ptm1__LAR = 32'hF889DFB0;
-parameter val_debug_cpu_ptm1__LAR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__LSR = 32'hF889DFB4;
-parameter val_debug_cpu_ptm1__LSR = 32'h00000003;
-parameter mask_debug_cpu_ptm1__LSR = 32'h00000007;
-
-parameter debug_cpu_ptm1__ASR = 32'hF889DFB8;
-parameter val_debug_cpu_ptm1__ASR = 32'h00000000;
-parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3;
-
-parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8;
-parameter val_debug_cpu_ptm1__DEVID = 32'h00000000;
-parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF;
-
-parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC;
-parameter val_debug_cpu_ptm1__DTIR = 32'h00000013;
-parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0;
-parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004;
-parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4;
-parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8;
-parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC;
-parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0;
-parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050;
-parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4;
-parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8;
-parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B;
-parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC;
-parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000;
-parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0;
-parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D;
-parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4;
-parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090;
-parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8;
-parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005;
-parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF;
-
-parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC;
-parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1;
-parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_cti_axim cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cti_axim__CTICONTROL = 32'hF880A000;
-parameter val_debug_cti_axim__CTICONTROL = 32'h00000000;
-parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001;
-
-parameter debug_cti_axim__CTIINTACK = 32'hF880A010;
-parameter val_debug_cti_axim__CTIINTACK = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF;
-
-parameter debug_cti_axim__CTIAPPSET = 32'hF880A014;
-parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000;
-parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F;
-
-parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018;
-parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000;
-parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F;
-
-parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C;
-parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000;
-parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN0 = 32'hF880A020;
-parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN1 = 32'hF880A024;
-parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN2 = 32'hF880A028;
-parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C;
-parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN4 = 32'hF880A030;
-parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN5 = 32'hF880A034;
-parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN6 = 32'hF880A038;
-parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C;
-parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0;
-parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4;
-parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8;
-parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC;
-parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0;
-parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4;
-parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8;
-parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F;
-
-parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC;
-parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000;
-parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F;
-
-parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130;
-parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000;
-parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000;
-
-parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134;
-parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000;
-parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF;
-
-parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138;
-parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000;
-parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000;
-
-parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C;
-parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000;
-parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F;
-
-parameter debug_cti_axim__CTIGATE = 32'hF880A140;
-parameter val_debug_cti_axim__CTIGATE = 32'h0000000F;
-parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F;
-
-parameter debug_cti_axim__ASICCTL = 32'hF880A144;
-parameter val_debug_cti_axim__ASICCTL = 32'h00000000;
-parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF;
-
-parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC;
-parameter val_debug_cti_axim__ITCHINACK = 32'h00000000;
-parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F;
-
-parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0;
-parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000;
-parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF;
-
-parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4;
-parameter val_debug_cti_axim__ITCHOUT = 32'h00000000;
-parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F;
-
-parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8;
-parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000;
-parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF;
-
-parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC;
-parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000;
-parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F;
-
-parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0;
-parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000;
-parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF;
-
-parameter debug_cti_axim__ITCHIN = 32'hF880AEF4;
-parameter val_debug_cti_axim__ITCHIN = 32'h00000000;
-parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F;
-
-parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8;
-parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000;
-parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF;
-
-parameter debug_cti_axim__ITCTRL = 32'hF880AF00;
-parameter val_debug_cti_axim__ITCTRL = 32'h00000000;
-parameter mask_debug_cti_axim__ITCTRL = 32'h00000001;
-
-parameter debug_cti_axim__CTSR = 32'hF880AFA0;
-parameter val_debug_cti_axim__CTSR = 32'h0000000F;
-parameter mask_debug_cti_axim__CTSR = 32'h0000000F;
-
-parameter debug_cti_axim__CTCR = 32'hF880AFA4;
-parameter val_debug_cti_axim__CTCR = 32'h00000000;
-parameter mask_debug_cti_axim__CTCR = 32'h0000000F;
-
-parameter debug_cti_axim__LAR = 32'hF880AFB0;
-parameter val_debug_cti_axim__LAR = 32'h00000000;
-parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF;
-
-parameter debug_cti_axim__LSR = 32'hF880AFB4;
-parameter val_debug_cti_axim__LSR = 32'h00000003;
-parameter mask_debug_cti_axim__LSR = 32'h00000007;
-
-parameter debug_cti_axim__ASR = 32'hF880AFB8;
-parameter val_debug_cti_axim__ASR = 32'h00000005;
-parameter mask_debug_cti_axim__ASR = 32'h00000005;
-
-parameter debug_cti_axim__DEVID = 32'hF880AFC8;
-parameter val_debug_cti_axim__DEVID = 32'h00040800;
-parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF;
-
-parameter debug_cti_axim__DTIR = 32'hF880AFCC;
-parameter val_debug_cti_axim__DTIR = 32'h00000014;
-parameter mask_debug_cti_axim__DTIR = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0;
-parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004;
-parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4;
-parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000;
-parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8;
-parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000;
-parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC;
-parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000;
-parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0;
-parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006;
-parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4;
-parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8;
-parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B;
-parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF;
-
-parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC;
-parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000;
-parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF;
-
-parameter debug_cti_axim__COMPID0 = 32'hF880AFF0;
-parameter val_debug_cti_axim__COMPID0 = 32'h0000000D;
-parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF;
-
-parameter debug_cti_axim__COMPID1 = 32'hF880AFF4;
-parameter val_debug_cti_axim__COMPID1 = 32'h00000090;
-parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF;
-
-parameter debug_cti_axim__COMPID2 = 32'hF880AFF8;
-parameter val_debug_cti_axim__COMPID2 = 32'h00000005;
-parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF;
-
-parameter debug_cti_axim__COMPID3 = 32'hF880AFFC;
-parameter val_debug_cti_axim__COMPID3 = 32'h000000B1;
-parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_cti_etb_tpiu cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000;
-parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001;
-
-parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010;
-parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014;
-parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018;
-parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C;
-parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020;
-parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024;
-parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028;
-parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C;
-parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030;
-parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034;
-parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038;
-parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C;
-parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC;
-parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130;
-parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000;
-
-parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134;
-parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138;
-parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000;
-
-parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C;
-parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140;
-parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F;
-parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144;
-parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC;
-parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0;
-parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4;
-parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8;
-parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC;
-parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0;
-parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4;
-parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8;
-parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00;
-parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001;
-
-parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0;
-parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F;
-parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4;
-parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F;
-
-parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0;
-parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF;
-
-parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4;
-parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003;
-parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007;
-
-parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8;
-parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005;
-parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005;
-
-parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8;
-parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800;
-parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF;
-
-parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC;
-parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014;
-parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0;
-parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004;
-parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4;
-parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8;
-parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC;
-parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0;
-parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006;
-parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4;
-parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8;
-parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B;
-parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC;
-parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000;
-parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0;
-parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D;
-parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4;
-parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090;
-parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8;
-parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005;
-parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF;
-
-parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC;
-parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1;
-parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_cti_ftm cti
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_cti_ftm__CTICONTROL = 32'hF8809000;
-parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000;
-parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001;
-
-parameter debug_cti_ftm__CTIINTACK = 32'hF8809010;
-parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF;
-
-parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014;
-parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018;
-parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C;
-parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020;
-parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024;
-parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028;
-parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C;
-parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030;
-parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034;
-parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038;
-parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C;
-parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0;
-parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4;
-parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8;
-parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC;
-parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0;
-parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4;
-parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8;
-parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC;
-parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000;
-parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F;
-
-parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130;
-parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000;
-parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000;
-
-parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134;
-parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000;
-parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF;
-
-parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138;
-parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000;
-parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000;
-
-parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C;
-parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000;
-parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F;
-
-parameter debug_cti_ftm__CTIGATE = 32'hF8809140;
-parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F;
-parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F;
-
-parameter debug_cti_ftm__ASICCTL = 32'hF8809144;
-parameter val_debug_cti_ftm__ASICCTL = 32'h00000000;
-parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF;
-
-parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC;
-parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000;
-parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F;
-
-parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0;
-parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000;
-parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF;
-
-parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4;
-parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000;
-parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F;
-
-parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8;
-parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000;
-parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF;
-
-parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC;
-parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000;
-parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F;
-
-parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0;
-parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000;
-parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF;
-
-parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4;
-parameter val_debug_cti_ftm__ITCHIN = 32'h00000000;
-parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F;
-
-parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8;
-parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000;
-parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF;
-
-parameter debug_cti_ftm__ITCTRL = 32'hF8809F00;
-parameter val_debug_cti_ftm__ITCTRL = 32'h00000000;
-parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001;
-
-parameter debug_cti_ftm__CTSR = 32'hF8809FA0;
-parameter val_debug_cti_ftm__CTSR = 32'h0000000F;
-parameter mask_debug_cti_ftm__CTSR = 32'h0000000F;
-
-parameter debug_cti_ftm__CTCR = 32'hF8809FA4;
-parameter val_debug_cti_ftm__CTCR = 32'h00000000;
-parameter mask_debug_cti_ftm__CTCR = 32'h0000000F;
-
-parameter debug_cti_ftm__LAR = 32'hF8809FB0;
-parameter val_debug_cti_ftm__LAR = 32'h00000000;
-parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF;
-
-parameter debug_cti_ftm__LSR = 32'hF8809FB4;
-parameter val_debug_cti_ftm__LSR = 32'h00000003;
-parameter mask_debug_cti_ftm__LSR = 32'h00000007;
-
-parameter debug_cti_ftm__ASR = 32'hF8809FB8;
-parameter val_debug_cti_ftm__ASR = 32'h00000005;
-parameter mask_debug_cti_ftm__ASR = 32'h00000005;
-
-parameter debug_cti_ftm__DEVID = 32'hF8809FC8;
-parameter val_debug_cti_ftm__DEVID = 32'h00040800;
-parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF;
-
-parameter debug_cti_ftm__DTIR = 32'hF8809FCC;
-parameter val_debug_cti_ftm__DTIR = 32'h00000014;
-parameter mask_debug_cti_ftm__DTIR = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0;
-parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004;
-parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4;
-parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000;
-parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8;
-parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000;
-parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC;
-parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000;
-parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0;
-parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006;
-parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4;
-parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8;
-parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B;
-parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF;
-
-parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC;
-parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000;
-parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF;
-
-parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0;
-parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D;
-parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF;
-
-parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4;
-parameter val_debug_cti_ftm__COMPID1 = 32'h00000090;
-parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF;
-
-parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8;
-parameter val_debug_cti_ftm__COMPID2 = 32'h00000005;
-parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF;
-
-parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC;
-parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1;
-parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_dap_rom dap
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000;
-parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003;
-parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004;
-parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003;
-parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008;
-parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003;
-parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C;
-parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003;
-parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010;
-parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003;
-parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014;
-parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003;
-parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018;
-parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003;
-parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C;
-parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003;
-parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020;
-parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003;
-parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024;
-parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003;
-parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028;
-parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000;
-parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C;
-parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000;
-parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030;
-parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000;
-parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034;
-parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000;
-parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038;
-parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000;
-parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C;
-parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000;
-parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF;
-
-parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0;
-parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003;
-parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF;
-
-parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4;
-parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000;
-parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF;
-
-parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8;
-parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000;
-parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF;
-
-parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC;
-parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000;
-parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF;
-
-parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0;
-parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2;
-parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF;
-
-parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4;
-parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093;
-parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF;
-
-parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8;
-parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008;
-parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF;
-
-parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC;
-parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000;
-parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF;
-
-parameter debug_dap_rom__COMPID0 = 32'hF8800FF0;
-parameter val_debug_dap_rom__COMPID0 = 32'h0000000D;
-parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF;
-
-parameter debug_dap_rom__COMPID1 = 32'hF8800FF4;
-parameter val_debug_dap_rom__COMPID1 = 32'h00000010;
-parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF;
-
-parameter debug_dap_rom__COMPID2 = 32'hF8800FF8;
-parameter val_debug_dap_rom__COMPID2 = 32'h00000005;
-parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF;
-
-parameter debug_dap_rom__COMPID3 = 32'hF8800FFC;
-parameter val_debug_dap_rom__COMPID3 = 32'h000000B1;
-parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_etb etb
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_etb__RDP = 32'hF8801004;
-parameter val_debug_etb__RDP = 32'h00000400;
-parameter mask_debug_etb__RDP = 32'hFFFFFFFF;
-
-parameter debug_etb__STS = 32'hF880100C;
-parameter val_debug_etb__STS = 32'h00000000;
-parameter mask_debug_etb__STS = 32'h0000000F;
-
-parameter debug_etb__RRD = 32'hF8801010;
-parameter val_debug_etb__RRD = 32'h00000000;
-parameter mask_debug_etb__RRD = 32'hFFFFFFFF;
-
-parameter debug_etb__RRP = 32'hF8801014;
-parameter val_debug_etb__RRP = 32'h00000000;
-parameter mask_debug_etb__RRP = 32'h000003FF;
-
-parameter debug_etb__RWP = 32'hF8801018;
-parameter val_debug_etb__RWP = 32'h00000000;
-parameter mask_debug_etb__RWP = 32'h000003FF;
-
-parameter debug_etb__TRG = 32'hF880101C;
-parameter val_debug_etb__TRG = 32'h00000000;
-parameter mask_debug_etb__TRG = 32'h000003FF;
-
-parameter debug_etb__CTL = 32'hF8801020;
-parameter val_debug_etb__CTL = 32'h00000000;
-parameter mask_debug_etb__CTL = 32'h00000001;
-
-parameter debug_etb__RWD = 32'hF8801024;
-parameter val_debug_etb__RWD = 32'h00000000;
-parameter mask_debug_etb__RWD = 32'hFFFFFFFF;
-
-parameter debug_etb__FFSR = 32'hF8801300;
-parameter val_debug_etb__FFSR = 32'h00000000;
-parameter mask_debug_etb__FFSR = 32'h00000003;
-
-parameter debug_etb__FFCR = 32'hF8801304;
-parameter val_debug_etb__FFCR = 32'h00000200;
-parameter mask_debug_etb__FFCR = 32'h00003FFF;
-
-parameter debug_etb__ITMISCOP0 = 32'hF8801EE0;
-parameter val_debug_etb__ITMISCOP0 = 32'h00000000;
-parameter mask_debug_etb__ITMISCOP0 = 32'h00000003;
-
-parameter debug_etb__ITTRFLINACK = 32'hF8801EE4;
-parameter val_debug_etb__ITTRFLINACK = 32'h00000000;
-parameter mask_debug_etb__ITTRFLINACK = 32'h00000003;
-
-parameter debug_etb__ITTRFLIN = 32'hF8801EE8;
-parameter val_debug_etb__ITTRFLIN = 32'h00000000;
-parameter mask_debug_etb__ITTRFLIN = 32'h00000003;
-
-parameter debug_etb__ITATBDATA0 = 32'hF8801EEC;
-parameter val_debug_etb__ITATBDATA0 = 32'h00000000;
-parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F;
-
-parameter debug_etb__ITATBCTR2 = 32'hF8801EF0;
-parameter val_debug_etb__ITATBCTR2 = 32'h00000000;
-parameter mask_debug_etb__ITATBCTR2 = 32'h00000003;
-
-parameter debug_etb__ITATBCTR1 = 32'hF8801EF4;
-parameter val_debug_etb__ITATBCTR1 = 32'h00000000;
-parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F;
-
-parameter debug_etb__ITATBCTR0 = 32'hF8801EF8;
-parameter val_debug_etb__ITATBCTR0 = 32'h00000000;
-parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF;
-
-parameter debug_etb__IMCR = 32'hF8801F00;
-parameter val_debug_etb__IMCR = 32'h00000000;
-parameter mask_debug_etb__IMCR = 32'h00000001;
-
-parameter debug_etb__CTSR = 32'hF8801FA0;
-parameter val_debug_etb__CTSR = 32'h0000000F;
-parameter mask_debug_etb__CTSR = 32'h0000000F;
-
-parameter debug_etb__CTCR = 32'hF8801FA4;
-parameter val_debug_etb__CTCR = 32'h00000000;
-parameter mask_debug_etb__CTCR = 32'h0000000F;
-
-parameter debug_etb__LAR = 32'hF8801FB0;
-parameter val_debug_etb__LAR = 32'h00000000;
-parameter mask_debug_etb__LAR = 32'hFFFFFFFF;
-
-parameter debug_etb__LSR = 32'hF8801FB4;
-parameter val_debug_etb__LSR = 32'h00000003;
-parameter mask_debug_etb__LSR = 32'h00000007;
-
-parameter debug_etb__ASR = 32'hF8801FB8;
-parameter val_debug_etb__ASR = 32'h00000000;
-parameter mask_debug_etb__ASR = 32'h000000FF;
-
-parameter debug_etb__DEVID = 32'hF8801FC8;
-parameter val_debug_etb__DEVID = 32'h00000000;
-parameter mask_debug_etb__DEVID = 32'h0000003F;
-
-parameter debug_etb__DTIR = 32'hF8801FCC;
-parameter val_debug_etb__DTIR = 32'h00000021;
-parameter mask_debug_etb__DTIR = 32'h000000FF;
-
-parameter debug_etb__PERIPHID4 = 32'hF8801FD0;
-parameter val_debug_etb__PERIPHID4 = 32'h00000004;
-parameter mask_debug_etb__PERIPHID4 = 32'h000000FF;
-
-parameter debug_etb__PERIPHID5 = 32'hF8801FD4;
-parameter val_debug_etb__PERIPHID5 = 32'h00000000;
-parameter mask_debug_etb__PERIPHID5 = 32'h000000FF;
-
-parameter debug_etb__PERIPHID6 = 32'hF8801FD8;
-parameter val_debug_etb__PERIPHID6 = 32'h00000000;
-parameter mask_debug_etb__PERIPHID6 = 32'h000000FF;
-
-parameter debug_etb__PERIPHID7 = 32'hF8801FDC;
-parameter val_debug_etb__PERIPHID7 = 32'h00000000;
-parameter mask_debug_etb__PERIPHID7 = 32'h000000FF;
-
-parameter debug_etb__PERIPHID0 = 32'hF8801FE0;
-parameter val_debug_etb__PERIPHID0 = 32'h00000007;
-parameter mask_debug_etb__PERIPHID0 = 32'h000000FF;
-
-parameter debug_etb__PERIPHID1 = 32'hF8801FE4;
-parameter val_debug_etb__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_etb__PERIPHID1 = 32'h000000FF;
-
-parameter debug_etb__PERIPHID2 = 32'hF8801FE8;
-parameter val_debug_etb__PERIPHID2 = 32'h0000002B;
-parameter mask_debug_etb__PERIPHID2 = 32'h000000FF;
-
-parameter debug_etb__PERIPHID3 = 32'hF8801FEC;
-parameter val_debug_etb__PERIPHID3 = 32'h00000000;
-parameter mask_debug_etb__PERIPHID3 = 32'h000000FF;
-
-parameter debug_etb__COMPID0 = 32'hF8801FF0;
-parameter val_debug_etb__COMPID0 = 32'h0000000D;
-parameter mask_debug_etb__COMPID0 = 32'h000000FF;
-
-parameter debug_etb__COMPID1 = 32'hF8801FF4;
-parameter val_debug_etb__COMPID1 = 32'h00000090;
-parameter mask_debug_etb__COMPID1 = 32'h000000FF;
-
-parameter debug_etb__COMPID2 = 32'hF8801FF8;
-parameter val_debug_etb__COMPID2 = 32'h00000005;
-parameter mask_debug_etb__COMPID2 = 32'h000000FF;
-
-parameter debug_etb__COMPID3 = 32'hF8801FFC;
-parameter val_debug_etb__COMPID3 = 32'h000000B1;
-parameter mask_debug_etb__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_ftm ftm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_ftm__FTMGLBCTRL = 32'hF880B000;
-parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000;
-parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001;
-
-parameter debug_ftm__FTMSTATUS = 32'hF880B004;
-parameter val_debug_ftm__FTMSTATUS = 32'h00000082;
-parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF;
-
-parameter debug_ftm__FTMCONTROL = 32'hF880B008;
-parameter val_debug_ftm__FTMCONTROL = 32'h00000000;
-parameter mask_debug_ftm__FTMCONTROL = 32'h00000007;
-
-parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C;
-parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000;
-parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF;
-
-parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010;
-parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000;
-parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF;
-
-parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014;
-parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000;
-parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF;
-
-parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018;
-parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000;
-parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF;
-
-parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C;
-parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000;
-parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF;
-
-parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020;
-parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000;
-parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF;
-
-parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024;
-parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000;
-parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF;
-
-parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028;
-parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000;
-parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF;
-
-parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C;
-parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000;
-parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F;
-
-parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030;
-parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000;
-parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF;
-
-parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034;
-parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000;
-parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF;
-
-parameter debug_ftm__FTMATID = 32'hF880B400;
-parameter val_debug_ftm__FTMATID = 32'h00000000;
-parameter mask_debug_ftm__FTMATID = 32'h0000007F;
-
-parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0;
-parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000;
-parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F;
-
-parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4;
-parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000;
-parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F;
-
-parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8;
-parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000;
-parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001;
-
-parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC;
-parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001;
-parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF;
-
-parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC;
-parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000;
-parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F;
-
-parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0;
-parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001;
-parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003;
-
-parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4;
-parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000;
-parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F;
-
-parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8;
-parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000;
-parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF;
-
-parameter debug_ftm__FTMITCR = 32'hF880BF00;
-parameter val_debug_ftm__FTMITCR = 32'h00000000;
-parameter mask_debug_ftm__FTMITCR = 32'h00000001;
-
-parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0;
-parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF;
-parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF;
-
-parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4;
-parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF;
-parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF;
-
-parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0;
-parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000;
-parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF;
-
-parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4;
-parameter val_debug_ftm__LOCK_STATUS = 32'h00000003;
-parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007;
-
-parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8;
-parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088;
-parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF;
-
-parameter debug_ftm__FTMDEVID = 32'hF880BFC8;
-parameter val_debug_ftm__FTMDEVID = 32'h00000000;
-parameter mask_debug_ftm__FTMDEVID = 32'h00000001;
-
-parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC;
-parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033;
-parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0;
-parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000;
-parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4;
-parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000;
-parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8;
-parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000;
-parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC;
-parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000;
-parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0;
-parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001;
-parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4;
-parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090;
-parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8;
-parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C;
-parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF;
-
-parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC;
-parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000;
-parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF;
-
-parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0;
-parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D;
-parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF;
-
-parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4;
-parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090;
-parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF;
-
-parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8;
-parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005;
-parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF;
-
-parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC;
-parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1;
-parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_funnel funnel
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_funnel__Control = 32'hF8804000;
-parameter val_debug_funnel__Control = 32'h00000300;
-parameter mask_debug_funnel__Control = 32'h00000FFF;
-
-parameter debug_funnel__PriControl = 32'hF8804004;
-parameter val_debug_funnel__PriControl = 32'h00FAC688;
-parameter mask_debug_funnel__PriControl = 32'h00FFFFFF;
-
-parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC;
-parameter val_debug_funnel__ITATBDATA0 = 32'h00000000;
-parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F;
-
-parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0;
-parameter val_debug_funnel__ITATBCTR2 = 32'h00000000;
-parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003;
-
-parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4;
-parameter val_debug_funnel__ITATBCTR1 = 32'h00000000;
-parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F;
-
-parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8;
-parameter val_debug_funnel__ITATBCTR0 = 32'h00000000;
-parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF;
-
-parameter debug_funnel__IMCR = 32'hF8804F00;
-parameter val_debug_funnel__IMCR = 32'h00000000;
-parameter mask_debug_funnel__IMCR = 32'h00000001;
-
-parameter debug_funnel__CTSR = 32'hF8804FA0;
-parameter val_debug_funnel__CTSR = 32'h0000000F;
-parameter mask_debug_funnel__CTSR = 32'h0000000F;
-
-parameter debug_funnel__CTCR = 32'hF8804FA4;
-parameter val_debug_funnel__CTCR = 32'h00000000;
-parameter mask_debug_funnel__CTCR = 32'h0000000F;
-
-parameter debug_funnel__LAR = 32'hF8804FB0;
-parameter val_debug_funnel__LAR = 32'h00000000;
-parameter mask_debug_funnel__LAR = 32'hFFFFFFFF;
-
-parameter debug_funnel__LSR = 32'hF8804FB4;
-parameter val_debug_funnel__LSR = 32'h00000003;
-parameter mask_debug_funnel__LSR = 32'h00000007;
-
-parameter debug_funnel__ASR = 32'hF8804FB8;
-parameter val_debug_funnel__ASR = 32'h00000000;
-parameter mask_debug_funnel__ASR = 32'h000000FF;
-
-parameter debug_funnel__DEVID = 32'hF8804FC8;
-parameter val_debug_funnel__DEVID = 32'h00000028;
-parameter mask_debug_funnel__DEVID = 32'h000000FF;
-
-parameter debug_funnel__DTIR = 32'hF8804FCC;
-parameter val_debug_funnel__DTIR = 32'h00000012;
-parameter mask_debug_funnel__DTIR = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID4 = 32'hF8804FD0;
-parameter val_debug_funnel__PERIPHID4 = 32'h00000004;
-parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID5 = 32'hF8804FD4;
-parameter val_debug_funnel__PERIPHID5 = 32'h00000000;
-parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID6 = 32'hF8804FD8;
-parameter val_debug_funnel__PERIPHID6 = 32'h00000000;
-parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID7 = 32'hF8804FDC;
-parameter val_debug_funnel__PERIPHID7 = 32'h00000000;
-parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID0 = 32'hF8804FE0;
-parameter val_debug_funnel__PERIPHID0 = 32'h00000008;
-parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID1 = 32'hF8804FE4;
-parameter val_debug_funnel__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID2 = 32'hF8804FE8;
-parameter val_debug_funnel__PERIPHID2 = 32'h0000001B;
-parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF;
-
-parameter debug_funnel__PERIPHID3 = 32'hF8804FEC;
-parameter val_debug_funnel__PERIPHID3 = 32'h00000000;
-parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF;
-
-parameter debug_funnel__COMPID0 = 32'hF8804FF0;
-parameter val_debug_funnel__COMPID0 = 32'h0000000D;
-parameter mask_debug_funnel__COMPID0 = 32'h000000FF;
-
-parameter debug_funnel__COMPID1 = 32'hF8804FF4;
-parameter val_debug_funnel__COMPID1 = 32'h00000090;
-parameter mask_debug_funnel__COMPID1 = 32'h000000FF;
-
-parameter debug_funnel__COMPID2 = 32'hF8804FF8;
-parameter val_debug_funnel__COMPID2 = 32'h00000005;
-parameter mask_debug_funnel__COMPID2 = 32'h000000FF;
-
-parameter debug_funnel__COMPID3 = 32'hF8804FFC;
-parameter val_debug_funnel__COMPID3 = 32'h000000B1;
-parameter mask_debug_funnel__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_itm itm
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_itm__StimPort00 = 32'hF8805000;
-parameter val_debug_itm__StimPort00 = 32'h00000000;
-parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort01 = 32'hF8805004;
-parameter val_debug_itm__StimPort01 = 32'h00000000;
-parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort02 = 32'hF8805008;
-parameter val_debug_itm__StimPort02 = 32'h00000000;
-parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort03 = 32'hF880500C;
-parameter val_debug_itm__StimPort03 = 32'h00000000;
-parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort04 = 32'hF8805010;
-parameter val_debug_itm__StimPort04 = 32'h00000000;
-parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort05 = 32'hF8805014;
-parameter val_debug_itm__StimPort05 = 32'h00000000;
-parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort06 = 32'hF8805018;
-parameter val_debug_itm__StimPort06 = 32'h00000000;
-parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort07 = 32'hF880501C;
-parameter val_debug_itm__StimPort07 = 32'h00000000;
-parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort08 = 32'hF8805020;
-parameter val_debug_itm__StimPort08 = 32'h00000000;
-parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort09 = 32'hF8805024;
-parameter val_debug_itm__StimPort09 = 32'h00000000;
-parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort10 = 32'hF8805028;
-parameter val_debug_itm__StimPort10 = 32'h00000000;
-parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort11 = 32'hF880502C;
-parameter val_debug_itm__StimPort11 = 32'h00000000;
-parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort12 = 32'hF8805030;
-parameter val_debug_itm__StimPort12 = 32'h00000000;
-parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort13 = 32'hF8805034;
-parameter val_debug_itm__StimPort13 = 32'h00000000;
-parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort14 = 32'hF8805038;
-parameter val_debug_itm__StimPort14 = 32'h00000000;
-parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort15 = 32'hF880503C;
-parameter val_debug_itm__StimPort15 = 32'h00000000;
-parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort16 = 32'hF8805040;
-parameter val_debug_itm__StimPort16 = 32'h00000000;
-parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort17 = 32'hF8805044;
-parameter val_debug_itm__StimPort17 = 32'h00000000;
-parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort18 = 32'hF8805048;
-parameter val_debug_itm__StimPort18 = 32'h00000000;
-parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort19 = 32'hF880504C;
-parameter val_debug_itm__StimPort19 = 32'h00000000;
-parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort20 = 32'hF8805050;
-parameter val_debug_itm__StimPort20 = 32'h00000000;
-parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort21 = 32'hF8805054;
-parameter val_debug_itm__StimPort21 = 32'h00000000;
-parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort22 = 32'hF8805058;
-parameter val_debug_itm__StimPort22 = 32'h00000000;
-parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort23 = 32'hF880505C;
-parameter val_debug_itm__StimPort23 = 32'h00000000;
-parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort24 = 32'hF8805060;
-parameter val_debug_itm__StimPort24 = 32'h00000000;
-parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort25 = 32'hF8805064;
-parameter val_debug_itm__StimPort25 = 32'h00000000;
-parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort26 = 32'hF8805068;
-parameter val_debug_itm__StimPort26 = 32'h00000000;
-parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort27 = 32'hF880506C;
-parameter val_debug_itm__StimPort27 = 32'h00000000;
-parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort28 = 32'hF8805070;
-parameter val_debug_itm__StimPort28 = 32'h00000000;
-parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort29 = 32'hF8805074;
-parameter val_debug_itm__StimPort29 = 32'h00000000;
-parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort30 = 32'hF8805078;
-parameter val_debug_itm__StimPort30 = 32'h00000000;
-parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF;
-
-parameter debug_itm__StimPort31 = 32'hF880507C;
-parameter val_debug_itm__StimPort31 = 32'h00000000;
-parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF;
-
-parameter debug_itm__TER = 32'hF8805E00;
-parameter val_debug_itm__TER = 32'h00000000;
-parameter mask_debug_itm__TER = 32'hFFFFFFFF;
-
-parameter debug_itm__TTR = 32'hF8805E20;
-parameter val_debug_itm__TTR = 32'h00000000;
-parameter mask_debug_itm__TTR = 32'hFFFFFFFF;
-
-parameter debug_itm__CR = 32'hF8805E80;
-parameter val_debug_itm__CR = 32'h00000004;
-parameter mask_debug_itm__CR = 32'h00FFFFFF;
-
-parameter debug_itm__SCR = 32'hF8805E90;
-parameter val_debug_itm__SCR = 32'h00000400;
-parameter mask_debug_itm__SCR = 32'h00000FFF;
-
-parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4;
-parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000;
-parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001;
-
-parameter debug_itm__ITTRIGOUT = 32'hF8805EE8;
-parameter val_debug_itm__ITTRIGOUT = 32'h00000000;
-parameter mask_debug_itm__ITTRIGOUT = 32'h00000001;
-
-parameter debug_itm__ITATBDATA0 = 32'hF8805EEC;
-parameter val_debug_itm__ITATBDATA0 = 32'h00000000;
-parameter mask_debug_itm__ITATBDATA0 = 32'h00000003;
-
-parameter debug_itm__ITATBCTR2 = 32'hF8805EF0;
-parameter val_debug_itm__ITATBCTR2 = 32'h00000001;
-parameter mask_debug_itm__ITATBCTR2 = 32'h00000001;
-
-parameter debug_itm__ITATABCTR1 = 32'hF8805EF4;
-parameter val_debug_itm__ITATABCTR1 = 32'h00000000;
-parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F;
-
-parameter debug_itm__ITATBCTR0 = 32'hF8805EF8;
-parameter val_debug_itm__ITATBCTR0 = 32'h00000000;
-parameter mask_debug_itm__ITATBCTR0 = 32'h00000003;
-
-parameter debug_itm__IMCR = 32'hF8805F00;
-parameter val_debug_itm__IMCR = 32'h00000000;
-parameter mask_debug_itm__IMCR = 32'h00000001;
-
-parameter debug_itm__CTSR = 32'hF8805FA0;
-parameter val_debug_itm__CTSR = 32'h000000FF;
-parameter mask_debug_itm__CTSR = 32'h000000FF;
-
-parameter debug_itm__CTCR = 32'hF8805FA4;
-parameter val_debug_itm__CTCR = 32'h00000000;
-parameter mask_debug_itm__CTCR = 32'h000000FF;
-
-parameter debug_itm__LAR = 32'hF8805FB0;
-parameter val_debug_itm__LAR = 32'h00000000;
-parameter mask_debug_itm__LAR = 32'hFFFFFFFF;
-
-parameter debug_itm__LSR = 32'hF8805FB4;
-parameter val_debug_itm__LSR = 32'h00000003;
-parameter mask_debug_itm__LSR = 32'h00000007;
-
-parameter debug_itm__ASR = 32'hF8805FB8;
-parameter val_debug_itm__ASR = 32'h00000088;
-parameter mask_debug_itm__ASR = 32'h000000FF;
-
-parameter debug_itm__DEVID = 32'hF8805FC8;
-parameter val_debug_itm__DEVID = 32'h00000020;
-parameter mask_debug_itm__DEVID = 32'h00001FFF;
-
-parameter debug_itm__DTIR = 32'hF8805FCC;
-parameter val_debug_itm__DTIR = 32'h00000043;
-parameter mask_debug_itm__DTIR = 32'h000000FF;
-
-parameter debug_itm__PERIPHID4 = 32'hF8805FD0;
-parameter val_debug_itm__PERIPHID4 = 32'h00000004;
-parameter mask_debug_itm__PERIPHID4 = 32'h000000FF;
-
-parameter debug_itm__PERIPHID5 = 32'hF8805FD4;
-parameter val_debug_itm__PERIPHID5 = 32'h00000000;
-parameter mask_debug_itm__PERIPHID5 = 32'h000000FF;
-
-parameter debug_itm__PERIPHID6 = 32'hF8805FD8;
-parameter val_debug_itm__PERIPHID6 = 32'h00000000;
-parameter mask_debug_itm__PERIPHID6 = 32'h000000FF;
-
-parameter debug_itm__PERIPHID7 = 32'hF8805FDC;
-parameter val_debug_itm__PERIPHID7 = 32'h00000000;
-parameter mask_debug_itm__PERIPHID7 = 32'h000000FF;
-
-parameter debug_itm__PERIPHID0 = 32'hF8805FE0;
-parameter val_debug_itm__PERIPHID0 = 32'h00000013;
-parameter mask_debug_itm__PERIPHID0 = 32'h000000FF;
-
-parameter debug_itm__PERIPHID1 = 32'hF8805FE4;
-parameter val_debug_itm__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_itm__PERIPHID1 = 32'h000000FF;
-
-parameter debug_itm__PERIPHID2 = 32'hF8805FE8;
-parameter val_debug_itm__PERIPHID2 = 32'h0000002B;
-parameter mask_debug_itm__PERIPHID2 = 32'h000000FF;
-
-parameter debug_itm__PERIPHID3 = 32'hF8805FEC;
-parameter val_debug_itm__PERIPHID3 = 32'h00000000;
-parameter mask_debug_itm__PERIPHID3 = 32'h000000FF;
-
-parameter debug_itm__COMPID0 = 32'hF8805FF0;
-parameter val_debug_itm__COMPID0 = 32'h0000000D;
-parameter mask_debug_itm__COMPID0 = 32'h000000FF;
-
-parameter debug_itm__COMPID1 = 32'hF8805FF4;
-parameter val_debug_itm__COMPID1 = 32'h00000090;
-parameter mask_debug_itm__COMPID1 = 32'h000000FF;
-
-parameter debug_itm__COMPID2 = 32'hF8805FF8;
-parameter val_debug_itm__COMPID2 = 32'h00000005;
-parameter mask_debug_itm__COMPID2 = 32'h000000FF;
-
-parameter debug_itm__COMPID3 = 32'hF8805FFC;
-parameter val_debug_itm__COMPID3 = 32'h000000B1;
-parameter mask_debug_itm__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module debug_tpiu tpiu
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter debug_tpiu__SuppSize = 32'hF8803000;
-parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF;
-parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF;
-
-parameter debug_tpiu__CurrentSize = 32'hF8803004;
-parameter val_debug_tpiu__CurrentSize = 32'h00000001;
-parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF;
-
-parameter debug_tpiu__SuppTrigMode = 32'hF8803100;
-parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F;
-parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF;
-
-parameter debug_tpiu__TrigCount = 32'hF8803104;
-parameter val_debug_tpiu__TrigCount = 32'h00000000;
-parameter mask_debug_tpiu__TrigCount = 32'h000000FF;
-
-parameter debug_tpiu__TrigMult = 32'hF8803108;
-parameter val_debug_tpiu__TrigMult = 32'h00000000;
-parameter mask_debug_tpiu__TrigMult = 32'h0000001F;
-
-parameter debug_tpiu__SuppTest = 32'hF8803200;
-parameter val_debug_tpiu__SuppTest = 32'h0003000F;
-parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF;
-
-parameter debug_tpiu__CurrentTest = 32'hF8803204;
-parameter val_debug_tpiu__CurrentTest = 32'h00000000;
-parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF;
-
-parameter debug_tpiu__TestRepeatCount = 32'hF8803208;
-parameter val_debug_tpiu__TestRepeatCount = 32'h00000000;
-parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF;
-
-parameter debug_tpiu__FFSR = 32'hF8803300;
-parameter val_debug_tpiu__FFSR = 32'h00000006;
-parameter mask_debug_tpiu__FFSR = 32'h00000007;
-
-parameter debug_tpiu__FFCR = 32'hF8803304;
-parameter val_debug_tpiu__FFCR = 32'h00000000;
-parameter mask_debug_tpiu__FFCR = 32'h00003FFF;
-
-parameter debug_tpiu__FormatSyncCount = 32'hF8803308;
-parameter val_debug_tpiu__FormatSyncCount = 32'h00000040;
-parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF;
-
-parameter debug_tpiu__EXTCTLIn = 32'hF8803400;
-parameter val_debug_tpiu__EXTCTLIn = 32'h00000000;
-parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF;
-
-parameter debug_tpiu__EXTCTLOut = 32'hF8803404;
-parameter val_debug_tpiu__EXTCTLOut = 32'h00000000;
-parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF;
-
-parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4;
-parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000;
-parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003;
-
-parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8;
-parameter val_debug_tpiu__ITTRFLIN = 32'h00000000;
-parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000;
-
-parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC;
-parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000;
-parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000;
-
-parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0;
-parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000;
-parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003;
-
-parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4;
-parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000;
-parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000;
-
-parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8;
-parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000;
-parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000;
-
-parameter debug_tpiu__IMCR = 32'hF8803F00;
-parameter val_debug_tpiu__IMCR = 32'h00000000;
-parameter mask_debug_tpiu__IMCR = 32'h00000001;
-
-parameter debug_tpiu__CTSR = 32'hF8803FA0;
-parameter val_debug_tpiu__CTSR = 32'h0000000F;
-parameter mask_debug_tpiu__CTSR = 32'h0000000F;
-
-parameter debug_tpiu__CTCR = 32'hF8803FA4;
-parameter val_debug_tpiu__CTCR = 32'h00000000;
-parameter mask_debug_tpiu__CTCR = 32'h0000000F;
-
-parameter debug_tpiu__LAR = 32'hF8803FB0;
-parameter val_debug_tpiu__LAR = 32'h00000000;
-parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF;
-
-parameter debug_tpiu__LSR = 32'hF8803FB4;
-parameter val_debug_tpiu__LSR = 32'h00000003;
-parameter mask_debug_tpiu__LSR = 32'h00000007;
-
-parameter debug_tpiu__ASR = 32'hF8803FB8;
-parameter val_debug_tpiu__ASR = 32'h00000000;
-parameter mask_debug_tpiu__ASR = 32'h000000FF;
-
-parameter debug_tpiu__DEVID = 32'hF8803FC8;
-parameter val_debug_tpiu__DEVID = 32'h000000A0;
-parameter mask_debug_tpiu__DEVID = 32'h00000FFF;
-
-parameter debug_tpiu__DTIR = 32'hF8803FCC;
-parameter val_debug_tpiu__DTIR = 32'h00000011;
-parameter mask_debug_tpiu__DTIR = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0;
-parameter val_debug_tpiu__PERIPHID4 = 32'h00000004;
-parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4;
-parameter val_debug_tpiu__PERIPHID5 = 32'h00000000;
-parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8;
-parameter val_debug_tpiu__PERIPHID6 = 32'h00000000;
-parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC;
-parameter val_debug_tpiu__PERIPHID7 = 32'h00000000;
-parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0;
-parameter val_debug_tpiu__PERIPHID0 = 32'h00000012;
-parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4;
-parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9;
-parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8;
-parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B;
-parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF;
-
-parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC;
-parameter val_debug_tpiu__PERIPHID3 = 32'h00000000;
-parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF;
-
-parameter debug_tpiu__COMPID0 = 32'hF8803FF0;
-parameter val_debug_tpiu__COMPID0 = 32'h0000000D;
-parameter mask_debug_tpiu__COMPID0 = 32'h000000FF;
-
-parameter debug_tpiu__COMPID1 = 32'hF8803FF4;
-parameter val_debug_tpiu__COMPID1 = 32'h00000090;
-parameter mask_debug_tpiu__COMPID1 = 32'h000000FF;
-
-parameter debug_tpiu__COMPID2 = 32'hF8803FF8;
-parameter val_debug_tpiu__COMPID2 = 32'h00000005;
-parameter mask_debug_tpiu__COMPID2 = 32'h000000FF;
-
-parameter debug_tpiu__COMPID3 = 32'hF8803FFC;
-parameter val_debug_tpiu__COMPID3 = 32'h000000B1;
-parameter mask_debug_tpiu__COMPID3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module devcfg devcfg
-// doc version: 1.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter devcfg__CTRL = 32'hF8007000;
-parameter val_devcfg__CTRL = 32'h0C000000;
-parameter mask_devcfg__CTRL = 32'hFFFFFFFF;
-
-parameter devcfg__LOCK = 32'hF8007004;
-parameter val_devcfg__LOCK = 32'h00000000;
-parameter mask_devcfg__LOCK = 32'hFFFFFFFF;
-
-parameter devcfg__CFG = 32'hF8007008;
-parameter val_devcfg__CFG = 32'h0000050B;
-parameter mask_devcfg__CFG = 32'hFFFFFFFF;
-
-parameter devcfg__INT_STS = 32'hF800700C;
-parameter val_devcfg__INT_STS = 32'h00000000;
-parameter mask_devcfg__INT_STS = 32'hFFFFFFFF;
-
-parameter devcfg__INT_MASK = 32'hF8007010;
-parameter val_devcfg__INT_MASK = 32'hFFFFFFFF;
-parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF;
-
-parameter devcfg__STATUS = 32'hF8007014;
-parameter val_devcfg__STATUS = 32'h40000820;
-parameter mask_devcfg__STATUS = 32'hFFFFFFFF;
-
-parameter devcfg__DMA_SRC_ADDR = 32'hF8007018;
-parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000;
-parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF;
-
-parameter devcfg__DMA_DST_ADDR = 32'hF800701C;
-parameter val_devcfg__DMA_DST_ADDR = 32'h00000000;
-parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF;
-
-parameter devcfg__DMA_SRC_LEN = 32'hF8007020;
-parameter val_devcfg__DMA_SRC_LEN = 32'h00000000;
-parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF;
-
-parameter devcfg__DMA_DEST_LEN = 32'hF8007024;
-parameter val_devcfg__DMA_DEST_LEN = 32'h00000000;
-parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF;
-
-parameter devcfg__ROM_SHADOW = 32'hF8007028;
-parameter val_devcfg__ROM_SHADOW = 32'h00000000;
-parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF;
-
-parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C;
-parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000;
-parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF;
-
-parameter devcfg__SW_ID = 32'hF8007030;
-parameter val_devcfg__SW_ID = 32'h00000000;
-parameter mask_devcfg__SW_ID = 32'hFFFFFFFF;
-
-parameter devcfg__UNLOCK = 32'hF8007034;
-parameter val_devcfg__UNLOCK = 32'h00000000;
-parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF;
-
-parameter devcfg__MCTRL = 32'hF8007080;
-parameter val_devcfg__MCTRL = 32'h00800000;
-parameter mask_devcfg__MCTRL = 32'h0FFFFFFF;
-
-parameter devcfg__XADCIF_CFG = 32'hF8007100;
-parameter val_devcfg__XADCIF_CFG = 32'h00001114;
-parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF;
-
-parameter devcfg__XADCIF_INT_STS = 32'hF8007104;
-parameter val_devcfg__XADCIF_INT_STS = 32'h00000200;
-parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF;
-
-parameter devcfg__XADCIF_INT_MASK = 32'hF8007108;
-parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF;
-parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF;
-
-parameter devcfg__XADCIF_MSTS = 32'hF800710C;
-parameter val_devcfg__XADCIF_MSTS = 32'h00000500;
-parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF;
-
-parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110;
-parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000;
-parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF;
-
-parameter devcfg__XADCIF_RDFIFO = 32'hF8007114;
-parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000;
-parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF;
-
-parameter devcfg__XADCIF_MCTL = 32'hF8007118;
-parameter val_devcfg__XADCIF_MCTL = 32'h00000010;
-parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module dmac0_ns dmac
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter dmac0_ns__DSR = 32'hF8004000;
-parameter val_dmac0_ns__DSR = 32'h00000000;
-parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DPC = 32'hF8004004;
-parameter val_dmac0_ns__DPC = 32'h00000000;
-parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF;
-
-parameter dmac0_ns__INTEN = 32'hF8004020;
-parameter val_dmac0_ns__INTEN = 32'h00000000;
-parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF;
-
-parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024;
-parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000;
-parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF;
-
-parameter dmac0_ns__INTMIS = 32'hF8004028;
-parameter val_dmac0_ns__INTMIS = 32'h00000000;
-parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF;
-
-parameter dmac0_ns__INTCLR = 32'hF800402C;
-parameter val_dmac0_ns__INTCLR = 32'h00000000;
-parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FSRD = 32'hF8004030;
-parameter val_dmac0_ns__FSRD = 32'h00000000;
-parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FSRC = 32'hF8004034;
-parameter val_dmac0_ns__FSRC = 32'h00000000;
-parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTRD = 32'hF8004038;
-parameter val_dmac0_ns__FTRD = 32'h00000000;
-parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR0 = 32'hF8004040;
-parameter val_dmac0_ns__FTR0 = 32'h00000000;
-parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR1 = 32'hF8004044;
-parameter val_dmac0_ns__FTR1 = 32'h00000000;
-parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR2 = 32'hF8004048;
-parameter val_dmac0_ns__FTR2 = 32'h00000000;
-parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR3 = 32'hF800404C;
-parameter val_dmac0_ns__FTR3 = 32'h00000000;
-parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR4 = 32'hF8004050;
-parameter val_dmac0_ns__FTR4 = 32'h00000000;
-parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR5 = 32'hF8004054;
-parameter val_dmac0_ns__FTR5 = 32'h00000000;
-parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR6 = 32'hF8004058;
-parameter val_dmac0_ns__FTR6 = 32'h00000000;
-parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__FTR7 = 32'hF800405C;
-parameter val_dmac0_ns__FTR7 = 32'h00000000;
-parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR0 = 32'hF8004100;
-parameter val_dmac0_ns__CSR0 = 32'h00000000;
-parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC0 = 32'hF8004104;
-parameter val_dmac0_ns__CPC0 = 32'h00000000;
-parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR1 = 32'hF8004108;
-parameter val_dmac0_ns__CSR1 = 32'h00000000;
-parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC1 = 32'hF800410C;
-parameter val_dmac0_ns__CPC1 = 32'h00000000;
-parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR2 = 32'hF8004110;
-parameter val_dmac0_ns__CSR2 = 32'h00000000;
-parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC2 = 32'hF8004114;
-parameter val_dmac0_ns__CPC2 = 32'h00000000;
-parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR3 = 32'hF8004118;
-parameter val_dmac0_ns__CSR3 = 32'h00000000;
-parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC3 = 32'hF800411C;
-parameter val_dmac0_ns__CPC3 = 32'h00000000;
-parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR4 = 32'hF8004120;
-parameter val_dmac0_ns__CSR4 = 32'h00000000;
-parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC4 = 32'hF8004124;
-parameter val_dmac0_ns__CPC4 = 32'h00000000;
-parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR5 = 32'hF8004128;
-parameter val_dmac0_ns__CSR5 = 32'h00000000;
-parameter mask_dmac0_ns__CSR5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC5 = 32'hF800412C;
-parameter val_dmac0_ns__CPC5 = 32'h00000000;
-parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR6 = 32'hF8004130;
-parameter val_dmac0_ns__CSR6 = 32'h00000000;
-parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC6 = 32'hF8004134;
-parameter val_dmac0_ns__CPC6 = 32'h00000000;
-parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CSR7 = 32'hF8004138;
-parameter val_dmac0_ns__CSR7 = 32'h00000000;
-parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CPC7 = 32'hF800413C;
-parameter val_dmac0_ns__CPC7 = 32'h00000000;
-parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR0 = 32'hF8004400;
-parameter val_dmac0_ns__SAR0 = 32'h00000000;
-parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR0 = 32'hF8004404;
-parameter val_dmac0_ns__DAR0 = 32'h00000000;
-parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR0 = 32'hF8004408;
-parameter val_dmac0_ns__CCR0 = 32'h00000000;
-parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_0 = 32'hF800440C;
-parameter val_dmac0_ns__LC0_0 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_0 = 32'hF8004410;
-parameter val_dmac0_ns__LC1_0 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR1 = 32'hF8004420;
-parameter val_dmac0_ns__SAR1 = 32'h00000000;
-parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR1 = 32'hF8004424;
-parameter val_dmac0_ns__DAR1 = 32'h00000000;
-parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR1 = 32'hF8004428;
-parameter val_dmac0_ns__CCR1 = 32'h00000000;
-parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_1 = 32'hF800442C;
-parameter val_dmac0_ns__LC0_1 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_1 = 32'hF8004430;
-parameter val_dmac0_ns__LC1_1 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR2 = 32'hF8004440;
-parameter val_dmac0_ns__SAR2 = 32'h00000000;
-parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR2 = 32'hF8004444;
-parameter val_dmac0_ns__DAR2 = 32'h00000000;
-parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR2 = 32'hF8004448;
-parameter val_dmac0_ns__CCR2 = 32'h00000000;
-parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_2 = 32'hF800444C;
-parameter val_dmac0_ns__LC0_2 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_2 = 32'hF8004450;
-parameter val_dmac0_ns__LC1_2 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR3 = 32'hF8004460;
-parameter val_dmac0_ns__SAR3 = 32'h00000000;
-parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR3 = 32'hF8004464;
-parameter val_dmac0_ns__DAR3 = 32'h00000000;
-parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR3 = 32'hF8004468;
-parameter val_dmac0_ns__CCR3 = 32'h00000000;
-parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_3 = 32'hF800446C;
-parameter val_dmac0_ns__LC0_3 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_3 = 32'hF8004470;
-parameter val_dmac0_ns__LC1_3 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR4 = 32'hF8004480;
-parameter val_dmac0_ns__SAR4 = 32'h00000000;
-parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR4 = 32'hF8004484;
-parameter val_dmac0_ns__DAR4 = 32'h00000000;
-parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR4 = 32'hF8004488;
-parameter val_dmac0_ns__CCR4 = 32'h00000000;
-parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_4 = 32'hF800448C;
-parameter val_dmac0_ns__LC0_4 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_4 = 32'hF8004490;
-parameter val_dmac0_ns__LC1_4 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR5 = 32'hF80044A0;
-parameter val_dmac0_ns__SAR5 = 32'h00000000;
-parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR5 = 32'hF80044A4;
-parameter val_dmac0_ns__DAR5 = 32'h00000000;
-parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR5 = 32'hF80044A8;
-parameter val_dmac0_ns__CCR5 = 32'h00000000;
-parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_5 = 32'hF80044AC;
-parameter val_dmac0_ns__LC0_5 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_5 = 32'hF80044B0;
-parameter val_dmac0_ns__LC1_5 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR6 = 32'hF80044C0;
-parameter val_dmac0_ns__SAR6 = 32'h00000000;
-parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR6 = 32'hF80044C4;
-parameter val_dmac0_ns__DAR6 = 32'h00000000;
-parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR6 = 32'hF80044C8;
-parameter val_dmac0_ns__CCR6 = 32'h00000000;
-parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_6 = 32'hF80044CC;
-parameter val_dmac0_ns__LC0_6 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_6 = 32'hF80044D0;
-parameter val_dmac0_ns__LC1_6 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__SAR7 = 32'hF80044E0;
-parameter val_dmac0_ns__SAR7 = 32'h00000000;
-parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DAR7 = 32'hF80044E4;
-parameter val_dmac0_ns__DAR7 = 32'h00000000;
-parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CCR7 = 32'hF80044E8;
-parameter val_dmac0_ns__CCR7 = 32'h00000000;
-parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC0_7 = 32'hF80044EC;
-parameter val_dmac0_ns__LC0_7 = 32'h00000000;
-parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__LC1_7 = 32'hF80044F0;
-parameter val_dmac0_ns__LC1_7 = 32'h00000000;
-parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DBGSTATUS = 32'hF8004D00;
-parameter val_dmac0_ns__DBGSTATUS = 32'h00000000;
-parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DBGCMD = 32'hF8004D04;
-parameter val_dmac0_ns__DBGCMD = 32'h00000000;
-parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DBGINST0 = 32'hF8004D08;
-parameter val_dmac0_ns__DBGINST0 = 32'h00000000;
-parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__DBGINST1 = 32'hF8004D0C;
-parameter val_dmac0_ns__DBGINST1 = 32'h00000000;
-parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CR0 = 32'hF8004E00;
-parameter val_dmac0_ns__CR0 = 32'h00000000;
-parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CR1 = 32'hF8004E04;
-parameter val_dmac0_ns__CR1 = 32'h00000000;
-parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CR2 = 32'hF8004E08;
-parameter val_dmac0_ns__CR2 = 32'h00000000;
-parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CR3 = 32'hF8004E0C;
-parameter val_dmac0_ns__CR3 = 32'h00000000;
-parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CR4 = 32'hF8004E10;
-parameter val_dmac0_ns__CR4 = 32'h00000000;
-parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__CRD = 32'hF8004E14;
-parameter val_dmac0_ns__CRD = 32'h00000000;
-parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF;
-
-parameter dmac0_ns__WD = 32'hF8004E80;
-parameter val_dmac0_ns__WD = 32'h00000000;
-parameter mask_dmac0_ns__WD = 32'hFFFFFFFF;
-
-parameter dmac0_ns__periph_id_0 = 32'hF8004FE0;
-parameter val_dmac0_ns__periph_id_0 = 32'h00000000;
-parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__periph_id_1 = 32'hF8004FE4;
-parameter val_dmac0_ns__periph_id_1 = 32'h00000000;
-parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__periph_id_2 = 32'hF8004FE8;
-parameter val_dmac0_ns__periph_id_2 = 32'h00000000;
-parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__periph_id_3 = 32'hF8004FEC;
-parameter val_dmac0_ns__periph_id_3 = 32'h00000000;
-parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0;
-parameter val_dmac0_ns__pcell_id_0 = 32'h00000000;
-parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4;
-parameter val_dmac0_ns__pcell_id_1 = 32'h00000000;
-parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8;
-parameter val_dmac0_ns__pcell_id_2 = 32'h00000000;
-parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF;
-
-parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC;
-parameter val_dmac0_ns__pcell_id_3 = 32'h00000000;
-parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module dmac0_s dmac
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter dmac0_s__DSR = 32'hF8003000;
-parameter val_dmac0_s__DSR = 32'h00000000;
-parameter mask_dmac0_s__DSR = 32'hFFFFFFFF;
-
-parameter dmac0_s__DPC = 32'hF8003004;
-parameter val_dmac0_s__DPC = 32'h00000000;
-parameter mask_dmac0_s__DPC = 32'hFFFFFFFF;
-
-parameter dmac0_s__INTEN = 32'hF8003020;
-parameter val_dmac0_s__INTEN = 32'h00000000;
-parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF;
-
-parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024;
-parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000;
-parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF;
-
-parameter dmac0_s__INTMIS = 32'hF8003028;
-parameter val_dmac0_s__INTMIS = 32'h00000000;
-parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF;
-
-parameter dmac0_s__INTCLR = 32'hF800302C;
-parameter val_dmac0_s__INTCLR = 32'h00000000;
-parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF;
-
-parameter dmac0_s__FSRD = 32'hF8003030;
-parameter val_dmac0_s__FSRD = 32'h00000000;
-parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF;
-
-parameter dmac0_s__FSRC = 32'hF8003034;
-parameter val_dmac0_s__FSRC = 32'h00000000;
-parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTRD = 32'hF8003038;
-parameter val_dmac0_s__FTRD = 32'h00000000;
-parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR0 = 32'hF8003040;
-parameter val_dmac0_s__FTR0 = 32'h00000000;
-parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR1 = 32'hF8003044;
-parameter val_dmac0_s__FTR1 = 32'h00000000;
-parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR2 = 32'hF8003048;
-parameter val_dmac0_s__FTR2 = 32'h00000000;
-parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR3 = 32'hF800304C;
-parameter val_dmac0_s__FTR3 = 32'h00000000;
-parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR4 = 32'hF8003050;
-parameter val_dmac0_s__FTR4 = 32'h00000000;
-parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR5 = 32'hF8003054;
-parameter val_dmac0_s__FTR5 = 32'h00000000;
-parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR6 = 32'hF8003058;
-parameter val_dmac0_s__FTR6 = 32'h00000000;
-parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__FTR7 = 32'hF800305C;
-parameter val_dmac0_s__FTR7 = 32'h00000000;
-parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR0 = 32'hF8003100;
-parameter val_dmac0_s__CSR0 = 32'h00000000;
-parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC0 = 32'hF8003104;
-parameter val_dmac0_s__CPC0 = 32'h00000000;
-parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR1 = 32'hF8003108;
-parameter val_dmac0_s__CSR1 = 32'h00000000;
-parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC1 = 32'hF800310C;
-parameter val_dmac0_s__CPC1 = 32'h00000000;
-parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR2 = 32'hF8003110;
-parameter val_dmac0_s__CSR2 = 32'h00000000;
-parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC2 = 32'hF8003114;
-parameter val_dmac0_s__CPC2 = 32'h00000000;
-parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR3 = 32'hF8003118;
-parameter val_dmac0_s__CSR3 = 32'h00000000;
-parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC3 = 32'hF800311C;
-parameter val_dmac0_s__CPC3 = 32'h00000000;
-parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR4 = 32'hF8003120;
-parameter val_dmac0_s__CSR4 = 32'h00000000;
-parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC4 = 32'hF8003124;
-parameter val_dmac0_s__CPC4 = 32'h00000000;
-parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR5 = 32'hF8003128;
-parameter val_dmac0_s__CSR5 = 32'h00000000;
-parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC5 = 32'hF800312C;
-parameter val_dmac0_s__CPC5 = 32'h00000000;
-parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR6 = 32'hF8003130;
-parameter val_dmac0_s__CSR6 = 32'h00000000;
-parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC6 = 32'hF8003134;
-parameter val_dmac0_s__CPC6 = 32'h00000000;
-parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CSR7 = 32'hF8003138;
-parameter val_dmac0_s__CSR7 = 32'h00000000;
-parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CPC7 = 32'hF800313C;
-parameter val_dmac0_s__CPC7 = 32'h00000000;
-parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR0 = 32'hF8003400;
-parameter val_dmac0_s__SAR0 = 32'h00000000;
-parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR0 = 32'hF8003404;
-parameter val_dmac0_s__DAR0 = 32'h00000000;
-parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR0 = 32'hF8003408;
-parameter val_dmac0_s__CCR0 = 32'h00800200;
-parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_0 = 32'hF800340C;
-parameter val_dmac0_s__LC0_0 = 32'h00000000;
-parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_0 = 32'hF8003410;
-parameter val_dmac0_s__LC1_0 = 32'h00000000;
-parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR1 = 32'hF8003420;
-parameter val_dmac0_s__SAR1 = 32'h00000000;
-parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR1 = 32'hF8003424;
-parameter val_dmac0_s__DAR1 = 32'h00000000;
-parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR1 = 32'hF8003428;
-parameter val_dmac0_s__CCR1 = 32'h00800200;
-parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_1 = 32'hF800342C;
-parameter val_dmac0_s__LC0_1 = 32'h00000000;
-parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_1 = 32'hF8003430;
-parameter val_dmac0_s__LC1_1 = 32'h00000000;
-parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR2 = 32'hF8003440;
-parameter val_dmac0_s__SAR2 = 32'h00000000;
-parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR2 = 32'hF8003444;
-parameter val_dmac0_s__DAR2 = 32'h00000000;
-parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR2 = 32'hF8003448;
-parameter val_dmac0_s__CCR2 = 32'h00800200;
-parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_2 = 32'hF800344C;
-parameter val_dmac0_s__LC0_2 = 32'h00000000;
-parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_2 = 32'hF8003450;
-parameter val_dmac0_s__LC1_2 = 32'h00000000;
-parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR3 = 32'hF8003460;
-parameter val_dmac0_s__SAR3 = 32'h00000000;
-parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR3 = 32'hF8003464;
-parameter val_dmac0_s__DAR3 = 32'h00000000;
-parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR3 = 32'hF8003468;
-parameter val_dmac0_s__CCR3 = 32'h00800200;
-parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_3 = 32'hF800346C;
-parameter val_dmac0_s__LC0_3 = 32'h00000000;
-parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_3 = 32'hF8003470;
-parameter val_dmac0_s__LC1_3 = 32'h00000000;
-parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR4 = 32'hF8003480;
-parameter val_dmac0_s__SAR4 = 32'h00000000;
-parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR4 = 32'hF8003484;
-parameter val_dmac0_s__DAR4 = 32'h00000000;
-parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR4 = 32'hF8003488;
-parameter val_dmac0_s__CCR4 = 32'h00800200;
-parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_4 = 32'hF800348C;
-parameter val_dmac0_s__LC0_4 = 32'h00000000;
-parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_4 = 32'hF8003490;
-parameter val_dmac0_s__LC1_4 = 32'h00000000;
-parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR5 = 32'hF80034A0;
-parameter val_dmac0_s__SAR5 = 32'h00000000;
-parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR5 = 32'hF80034A4;
-parameter val_dmac0_s__DAR5 = 32'h00000000;
-parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR5 = 32'hF80034A8;
-parameter val_dmac0_s__CCR5 = 32'h00800200;
-parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_5 = 32'hF80034AC;
-parameter val_dmac0_s__LC0_5 = 32'h00000000;
-parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_5 = 32'hF80034B0;
-parameter val_dmac0_s__LC1_5 = 32'h00000000;
-parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR6 = 32'hF80034C0;
-parameter val_dmac0_s__SAR6 = 32'h00000000;
-parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR6 = 32'hF80034C4;
-parameter val_dmac0_s__DAR6 = 32'h00000000;
-parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR6 = 32'hF80034C8;
-parameter val_dmac0_s__CCR6 = 32'h00800200;
-parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_6 = 32'hF80034CC;
-parameter val_dmac0_s__LC0_6 = 32'h00000000;
-parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_6 = 32'hF80034D0;
-parameter val_dmac0_s__LC1_6 = 32'h00000000;
-parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF;
-
-parameter dmac0_s__SAR7 = 32'hF80034E0;
-parameter val_dmac0_s__SAR7 = 32'h00000000;
-parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DAR7 = 32'hF80034E4;
-parameter val_dmac0_s__DAR7 = 32'h00000000;
-parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CCR7 = 32'hF80034E8;
-parameter val_dmac0_s__CCR7 = 32'h00800200;
-parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC0_7 = 32'hF80034EC;
-parameter val_dmac0_s__LC0_7 = 32'h00000000;
-parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__LC1_7 = 32'hF80034F0;
-parameter val_dmac0_s__LC1_7 = 32'h00000000;
-parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DBGSTATUS = 32'hF8003D00;
-parameter val_dmac0_s__DBGSTATUS = 32'h00000000;
-parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF;
-
-parameter dmac0_s__DBGCMD = 32'hF8003D04;
-parameter val_dmac0_s__DBGCMD = 32'h00000000;
-parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF;
-
-parameter dmac0_s__DBGINST0 = 32'hF8003D08;
-parameter val_dmac0_s__DBGINST0 = 32'h00000000;
-parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__DBGINST1 = 32'hF8003D0C;
-parameter val_dmac0_s__DBGINST1 = 32'h00000000;
-parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CR0 = 32'hF8003E00;
-parameter val_dmac0_s__CR0 = 32'h001E3071;
-parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CR1 = 32'hF8003E04;
-parameter val_dmac0_s__CR1 = 32'h00000074;
-parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CR2 = 32'hF8003E08;
-parameter val_dmac0_s__CR2 = 32'h00000000;
-parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CR3 = 32'hF8003E0C;
-parameter val_dmac0_s__CR3 = 32'h00000000;
-parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CR4 = 32'hF8003E10;
-parameter val_dmac0_s__CR4 = 32'h00000000;
-parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF;
-
-parameter dmac0_s__CRD = 32'hF8003E14;
-parameter val_dmac0_s__CRD = 32'h07FF7F73;
-parameter mask_dmac0_s__CRD = 32'hFFFFFFFF;
-
-parameter dmac0_s__WD = 32'hF8003E80;
-parameter val_dmac0_s__WD = 32'h00000000;
-parameter mask_dmac0_s__WD = 32'hFFFFFFFF;
-
-parameter dmac0_s__periph_id_0 = 32'hF8003FE0;
-parameter val_dmac0_s__periph_id_0 = 32'h00000030;
-parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__periph_id_1 = 32'hF8003FE4;
-parameter val_dmac0_s__periph_id_1 = 32'h00000013;
-parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__periph_id_2 = 32'hF8003FE8;
-parameter val_dmac0_s__periph_id_2 = 32'h00000024;
-parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__periph_id_3 = 32'hF8003FEC;
-parameter val_dmac0_s__periph_id_3 = 32'h00000000;
-parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF;
-
-parameter dmac0_s__pcell_id_0 = 32'hF8003FF0;
-parameter val_dmac0_s__pcell_id_0 = 32'h0000000D;
-parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF;
-
-parameter dmac0_s__pcell_id_1 = 32'hF8003FF4;
-parameter val_dmac0_s__pcell_id_1 = 32'h000000F0;
-parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF;
-
-parameter dmac0_s__pcell_id_2 = 32'hF8003FF8;
-parameter val_dmac0_s__pcell_id_2 = 32'h00000005;
-parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF;
-
-parameter dmac0_s__pcell_id_3 = 32'hF8003FFC;
-parameter val_dmac0_s__pcell_id_3 = 32'h000000B1;
-parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module efuse_ctrl efuse_ctrl
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter efuse_ctrl__WR_LOCK = 32'hF800D000;
-parameter val_efuse_ctrl__WR_LOCK = 32'h00000000;
-parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF;
-
-parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004;
-parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000;
-parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF;
-
-parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008;
-parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001;
-parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF;
-
-parameter efuse_ctrl__CFG = 32'hF800D00C;
-parameter val_efuse_ctrl__CFG = 32'h00010F00;
-parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF;
-
-parameter efuse_ctrl__STATUS = 32'hF800D010;
-parameter val_efuse_ctrl__STATUS = 32'h00100000;
-parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF;
-
-parameter efuse_ctrl__CONTROL = 32'hF800D014;
-parameter val_efuse_ctrl__CONTROL = 32'h00000003;
-parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF;
-
-parameter efuse_ctrl__PGM_STBW = 32'hF800D018;
-parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0;
-parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF;
-
-parameter efuse_ctrl__RD_STBW = 32'hF800D01C;
-parameter val_efuse_ctrl__RD_STBW = 32'h0000000B;
-parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module gem0 GEM
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gem0__net_ctrl = 32'hE000B000;
-parameter val_gem0__net_ctrl = 32'h00000000;
-parameter mask_gem0__net_ctrl = 32'hFFFFFFFF;
-
-parameter gem0__net_cfg = 32'hE000B004;
-parameter val_gem0__net_cfg = 32'h00080000;
-parameter mask_gem0__net_cfg = 32'hFFFFFFFF;
-
-parameter gem0__net_status = 32'hE000B008;
-parameter val_gem0__net_status = 32'h00000004;
-parameter mask_gem0__net_status = 32'hFFFFFFFD;
-
-parameter gem0__user_io = 32'hE000B00C;
-parameter val_gem0__user_io = 32'h00000000;
-parameter mask_gem0__user_io = 32'h0000FFFF;
-
-parameter gem0__dma_cfg = 32'hE000B010;
-parameter val_gem0__dma_cfg = 32'h00020784;
-parameter mask_gem0__dma_cfg = 32'hFFFFFFFF;
-
-parameter gem0__tx_status = 32'hE000B014;
-parameter val_gem0__tx_status = 32'h00000000;
-parameter mask_gem0__tx_status = 32'hFFFFFFFF;
-
-parameter gem0__rx_qbar = 32'hE000B018;
-parameter val_gem0__rx_qbar = 32'h00000000;
-parameter mask_gem0__rx_qbar = 32'hFFFFFFFF;
-
-parameter gem0__tx_qbar = 32'hE000B01C;
-parameter val_gem0__tx_qbar = 32'h00000000;
-parameter mask_gem0__tx_qbar = 32'hFFFFFFFF;
-
-parameter gem0__rx_status = 32'hE000B020;
-parameter val_gem0__rx_status = 32'h00000000;
-parameter mask_gem0__rx_status = 32'hFFFFFFFF;
-
-parameter gem0__intr_status = 32'hE000B024;
-parameter val_gem0__intr_status = 32'h00000000;
-parameter mask_gem0__intr_status = 32'hFFFFFFFF;
-
-parameter gem0__intr_en = 32'hE000B028;
-parameter val_gem0__intr_en = 32'h00000000;
-parameter mask_gem0__intr_en = 32'h00000000;
-
-parameter gem0__intr_dis = 32'hE000B02C;
-parameter val_gem0__intr_dis = 32'h00000000;
-parameter mask_gem0__intr_dis = 32'h00000000;
-
-parameter gem0__intr_mask = 32'hE000B030;
-parameter val_gem0__intr_mask = 32'h0001FFFF;
-parameter mask_gem0__intr_mask = 32'hFC01FFFF;
-
-parameter gem0__phy_maint = 32'hE000B034;
-parameter val_gem0__phy_maint = 32'h00000000;
-parameter mask_gem0__phy_maint = 32'hFFFFFFFF;
-
-parameter gem0__rx_pauseq = 32'hE000B038;
-parameter val_gem0__rx_pauseq = 32'h00000000;
-parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF;
-
-parameter gem0__tx_pauseq = 32'hE000B03C;
-parameter val_gem0__tx_pauseq = 32'h0000FFFF;
-parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF;
-
-parameter gem0__tx_partial_st_fwd = 32'hE000B040;
-parameter val_gem0__tx_partial_st_fwd = 32'h000003FF;
-parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF;
-
-parameter gem0__rx_partial_st_fwd = 32'hE000B044;
-parameter val_gem0__rx_partial_st_fwd = 32'h000003FF;
-parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF;
-
-parameter gem0__hash_bot = 32'hE000B080;
-parameter val_gem0__hash_bot = 32'h00000000;
-parameter mask_gem0__hash_bot = 32'hFFFFFFFF;
-
-parameter gem0__hash_top = 32'hE000B084;
-parameter val_gem0__hash_top = 32'h00000000;
-parameter mask_gem0__hash_top = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr1_bot = 32'hE000B088;
-parameter val_gem0__spec_addr1_bot = 32'h00000000;
-parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr1_top = 32'hE000B08C;
-parameter val_gem0__spec_addr1_top = 32'h00000000;
-parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr2_bot = 32'hE000B090;
-parameter val_gem0__spec_addr2_bot = 32'h00000000;
-parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr2_top = 32'hE000B094;
-parameter val_gem0__spec_addr2_top = 32'h00000000;
-parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr3_bot = 32'hE000B098;
-parameter val_gem0__spec_addr3_bot = 32'h00000000;
-parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr3_top = 32'hE000B09C;
-parameter val_gem0__spec_addr3_top = 32'h00000000;
-parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr4_bot = 32'hE000B0A0;
-parameter val_gem0__spec_addr4_bot = 32'h00000000;
-parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr4_top = 32'hE000B0A4;
-parameter val_gem0__spec_addr4_top = 32'h00000000;
-parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF;
-
-parameter gem0__type_id_match1 = 32'hE000B0A8;
-parameter val_gem0__type_id_match1 = 32'h00000000;
-parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF;
-
-parameter gem0__type_id_match2 = 32'hE000B0AC;
-parameter val_gem0__type_id_match2 = 32'h00000000;
-parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF;
-
-parameter gem0__type_id_match3 = 32'hE000B0B0;
-parameter val_gem0__type_id_match3 = 32'h00000000;
-parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF;
-
-parameter gem0__type_id_match4 = 32'hE000B0B4;
-parameter val_gem0__type_id_match4 = 32'h00000000;
-parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF;
-
-parameter gem0__wake_on_lan = 32'hE000B0B8;
-parameter val_gem0__wake_on_lan = 32'h00000000;
-parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF;
-
-parameter gem0__ipg_stretch = 32'hE000B0BC;
-parameter val_gem0__ipg_stretch = 32'h00000000;
-parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF;
-
-parameter gem0__stacked_vlan = 32'hE000B0C0;
-parameter val_gem0__stacked_vlan = 32'h00000000;
-parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF;
-
-parameter gem0__tx_pfc_pause = 32'hE000B0C4;
-parameter val_gem0__tx_pfc_pause = 32'h00000000;
-parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8;
-parameter val_gem0__spec_addr1_mask_bot = 32'h00000000;
-parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF;
-
-parameter gem0__spec_addr1_mask_top = 32'hE000B0CC;
-parameter val_gem0__spec_addr1_mask_top = 32'h00000000;
-parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF;
-
-parameter gem0__module_id = 32'hE000B0FC;
-parameter val_gem0__module_id = 32'h00020118;
-parameter mask_gem0__module_id = 32'hFFFFFFFF;
-
-parameter gem0__octets_tx_bot = 32'hE000B100;
-parameter val_gem0__octets_tx_bot = 32'h00000000;
-parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF;
-
-parameter gem0__octets_tx_top = 32'hE000B104;
-parameter val_gem0__octets_tx_top = 32'h00000000;
-parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF;
-
-parameter gem0__frames_tx = 32'hE000B108;
-parameter val_gem0__frames_tx = 32'h00000000;
-parameter mask_gem0__frames_tx = 32'hFFFFFFFF;
-
-parameter gem0__broadcast_frames_tx = 32'hE000B10C;
-parameter val_gem0__broadcast_frames_tx = 32'h00000000;
-parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF;
-
-parameter gem0__multi_frames_tx = 32'hE000B110;
-parameter val_gem0__multi_frames_tx = 32'h00000000;
-parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF;
-
-parameter gem0__pause_frames_tx = 32'hE000B114;
-parameter val_gem0__pause_frames_tx = 32'h00000000;
-parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF;
-
-parameter gem0__frames_64b_tx = 32'hE000B118;
-parameter val_gem0__frames_64b_tx = 32'h00000000;
-parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF;
-
-parameter gem0__frames_65to127b_tx = 32'hE000B11C;
-parameter val_gem0__frames_65to127b_tx = 32'h00000000;
-parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF;
-
-parameter gem0__frames_128to255b_tx = 32'hE000B120;
-parameter val_gem0__frames_128to255b_tx = 32'h00000000;
-parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF;
-
-parameter gem0__frames_256to511b_tx = 32'hE000B124;
-parameter val_gem0__frames_256to511b_tx = 32'h00000000;
-parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF;
-
-parameter gem0__frames_512to1023b_tx = 32'hE000B128;
-parameter val_gem0__frames_512to1023b_tx = 32'h00000000;
-parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF;
-
-parameter gem0__frames_1024to1518b_tx = 32'hE000B12C;
-parameter val_gem0__frames_1024to1518b_tx = 32'h00000000;
-parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF;
-
-parameter gem0__frames_gt1518b_tx = 32'hE000B130;
-parameter val_gem0__frames_gt1518b_tx = 32'h00000000;
-parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF;
-
-parameter gem0__tx_under_runs = 32'hE000B134;
-parameter val_gem0__tx_under_runs = 32'h00000000;
-parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF;
-
-parameter gem0__single_collisn_frames = 32'hE000B138;
-parameter val_gem0__single_collisn_frames = 32'h00000000;
-parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF;
-
-parameter gem0__multi_collisn_frames = 32'hE000B13C;
-parameter val_gem0__multi_collisn_frames = 32'h00000000;
-parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF;
-
-parameter gem0__excessive_collisns = 32'hE000B140;
-parameter val_gem0__excessive_collisns = 32'h00000000;
-parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF;
-
-parameter gem0__late_collisns = 32'hE000B144;
-parameter val_gem0__late_collisns = 32'h00000000;
-parameter mask_gem0__late_collisns = 32'hFFFFFFFF;
-
-parameter gem0__deferred_tx_frames = 32'hE000B148;
-parameter val_gem0__deferred_tx_frames = 32'h00000000;
-parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF;
-
-parameter gem0__carrier_sense_errs = 32'hE000B14C;
-parameter val_gem0__carrier_sense_errs = 32'h00000000;
-parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF;
-
-parameter gem0__octets_rx_bot = 32'hE000B150;
-parameter val_gem0__octets_rx_bot = 32'h00000000;
-parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF;
-
-parameter gem0__octets_rx_top = 32'hE000B154;
-parameter val_gem0__octets_rx_top = 32'h00000000;
-parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF;
-
-parameter gem0__frames_rx = 32'hE000B158;
-parameter val_gem0__frames_rx = 32'h00000000;
-parameter mask_gem0__frames_rx = 32'hFFFFFFFF;
-
-parameter gem0__bdcast_fames_rx = 32'hE000B15C;
-parameter val_gem0__bdcast_fames_rx = 32'h00000000;
-parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF;
-
-parameter gem0__multi_frames_rx = 32'hE000B160;
-parameter val_gem0__multi_frames_rx = 32'h00000000;
-parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF;
-
-parameter gem0__pause_rx = 32'hE000B164;
-parameter val_gem0__pause_rx = 32'h00000000;
-parameter mask_gem0__pause_rx = 32'hFFFFFFFF;
-
-parameter gem0__frames_64b_rx = 32'hE000B168;
-parameter val_gem0__frames_64b_rx = 32'h00000000;
-parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF;
-
-parameter gem0__frames_65to127b_rx = 32'hE000B16C;
-parameter val_gem0__frames_65to127b_rx = 32'h00000000;
-parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF;
-
-parameter gem0__frames_128to255b_rx = 32'hE000B170;
-parameter val_gem0__frames_128to255b_rx = 32'h00000000;
-parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF;
-
-parameter gem0__frames_256to511b_rx = 32'hE000B174;
-parameter val_gem0__frames_256to511b_rx = 32'h00000000;
-parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF;
-
-parameter gem0__frames_512to1023b_rx = 32'hE000B178;
-parameter val_gem0__frames_512to1023b_rx = 32'h00000000;
-parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF;
-
-parameter gem0__frames_1024to1518b_rx = 32'hE000B17C;
-parameter val_gem0__frames_1024to1518b_rx = 32'h00000000;
-parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF;
-
-parameter gem0__frames_gt1518b_rx = 32'hE000B180;
-parameter val_gem0__frames_gt1518b_rx = 32'h00000000;
-parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF;
-
-parameter gem0__undersz_rx = 32'hE000B184;
-parameter val_gem0__undersz_rx = 32'h00000000;
-parameter mask_gem0__undersz_rx = 32'hFFFFFFFF;
-
-parameter gem0__oversz_rx = 32'hE000B188;
-parameter val_gem0__oversz_rx = 32'h00000000;
-parameter mask_gem0__oversz_rx = 32'hFFFFFFFF;
-
-parameter gem0__jab_rx = 32'hE000B18C;
-parameter val_gem0__jab_rx = 32'h00000000;
-parameter mask_gem0__jab_rx = 32'hFFFFFFFF;
-
-parameter gem0__fcs_errors = 32'hE000B190;
-parameter val_gem0__fcs_errors = 32'h00000000;
-parameter mask_gem0__fcs_errors = 32'hFFFFFFFF;
-
-parameter gem0__length_field_errors = 32'hE000B194;
-parameter val_gem0__length_field_errors = 32'h00000000;
-parameter mask_gem0__length_field_errors = 32'hFFFFFFFF;
-
-parameter gem0__rx_symbol_errors = 32'hE000B198;
-parameter val_gem0__rx_symbol_errors = 32'h00000000;
-parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF;
-
-parameter gem0__align_errors = 32'hE000B19C;
-parameter val_gem0__align_errors = 32'h00000000;
-parameter mask_gem0__align_errors = 32'hFFFFFFFF;
-
-parameter gem0__rx_resource_errors = 32'hE000B1A0;
-parameter val_gem0__rx_resource_errors = 32'h00000000;
-parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF;
-
-parameter gem0__rx_overrun_errors = 32'hE000B1A4;
-parameter val_gem0__rx_overrun_errors = 32'h00000000;
-parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF;
-
-parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8;
-parameter val_gem0__ip_hdr_csum_errors = 32'h00000000;
-parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF;
-
-parameter gem0__tcp_csum_errors = 32'hE000B1AC;
-parameter val_gem0__tcp_csum_errors = 32'h00000000;
-parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF;
-
-parameter gem0__udp_csum_errors = 32'hE000B1B0;
-parameter val_gem0__udp_csum_errors = 32'h00000000;
-parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF;
-
-parameter gem0__timer_strobe_s = 32'hE000B1C8;
-parameter val_gem0__timer_strobe_s = 32'h00000000;
-parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF;
-
-parameter gem0__timer_strobe_ns = 32'hE000B1CC;
-parameter val_gem0__timer_strobe_ns = 32'h00000000;
-parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF;
-
-parameter gem0__timer_s = 32'hE000B1D0;
-parameter val_gem0__timer_s = 32'h00000000;
-parameter mask_gem0__timer_s = 32'hFFFFFFFF;
-
-parameter gem0__timer_ns = 32'hE000B1D4;
-parameter val_gem0__timer_ns = 32'h00000000;
-parameter mask_gem0__timer_ns = 32'hFFFFFFFF;
-
-parameter gem0__timer_adjust = 32'hE000B1D8;
-parameter val_gem0__timer_adjust = 32'h00000000;
-parameter mask_gem0__timer_adjust = 32'hFFFFFFFF;
-
-parameter gem0__timer_incr = 32'hE000B1DC;
-parameter val_gem0__timer_incr = 32'h00000000;
-parameter mask_gem0__timer_incr = 32'hFFFFFFFF;
-
-parameter gem0__ptp_tx_s = 32'hE000B1E0;
-parameter val_gem0__ptp_tx_s = 32'h00000000;
-parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF;
-
-parameter gem0__ptp_tx_ns = 32'hE000B1E4;
-parameter val_gem0__ptp_tx_ns = 32'h00000000;
-parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF;
-
-parameter gem0__ptp_rx_s = 32'hE000B1E8;
-parameter val_gem0__ptp_rx_s = 32'h00000000;
-parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF;
-
-parameter gem0__ptp_rx_ns = 32'hE000B1EC;
-parameter val_gem0__ptp_rx_ns = 32'h00000000;
-parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF;
-
-parameter gem0__ptp_peer_tx_s = 32'hE000B1F0;
-parameter val_gem0__ptp_peer_tx_s = 32'h00000000;
-parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF;
-
-parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4;
-parameter val_gem0__ptp_peer_tx_ns = 32'h00000000;
-parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF;
-
-parameter gem0__ptp_peer_rx_s = 32'hE000B1F8;
-parameter val_gem0__ptp_peer_rx_s = 32'h00000000;
-parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF;
-
-parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC;
-parameter val_gem0__ptp_peer_rx_ns = 32'h00000000;
-parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF;
-
-parameter gem0__pcs_ctrl = 32'hE000B200;
-parameter val_gem0__pcs_ctrl = 32'h00000000;
-parameter mask_gem0__pcs_ctrl = 32'h00000000;
-
-parameter gem0__pcs_status = 32'hE000B204;
-parameter val_gem0__pcs_status = 32'h00000000;
-parameter mask_gem0__pcs_status = 32'h00000000;
-
-parameter gem0__pcs_upper_phy_id = 32'hE000B208;
-parameter val_gem0__pcs_upper_phy_id = 32'h00000000;
-parameter mask_gem0__pcs_upper_phy_id = 32'h00000000;
-
-parameter gem0__pcs_lower_phy_id = 32'hE000B20C;
-parameter val_gem0__pcs_lower_phy_id = 32'h00000000;
-parameter mask_gem0__pcs_lower_phy_id = 32'h00000000;
-
-parameter gem0__pcs_autoneg_ad = 32'hE000B210;
-parameter val_gem0__pcs_autoneg_ad = 32'h00000000;
-parameter mask_gem0__pcs_autoneg_ad = 32'h00000000;
-
-parameter gem0__pcs_autoneg_ability = 32'hE000B214;
-parameter val_gem0__pcs_autoneg_ability = 32'h00000000;
-parameter mask_gem0__pcs_autoneg_ability = 32'h00000000;
-
-parameter gem0__pcs_autonec_exp = 32'hE000B218;
-parameter val_gem0__pcs_autonec_exp = 32'h00000000;
-parameter mask_gem0__pcs_autonec_exp = 32'h00000000;
-
-parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C;
-parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000;
-parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000;
-
-parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220;
-parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000;
-parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000;
-
-parameter gem0__pcs_extended_status = 32'hE000B23C;
-parameter val_gem0__pcs_extended_status = 32'h00000000;
-parameter mask_gem0__pcs_extended_status = 32'h00000000;
-
-parameter gem0__design_cfg1 = 32'hE000B280;
-parameter val_gem0__design_cfg1 = 32'h02000000;
-parameter mask_gem0__design_cfg1 = 32'h0E000000;
-
-parameter gem0__design_cfg2 = 32'hE000B284;
-parameter val_gem0__design_cfg2 = 32'h2A813FFF;
-parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF;
-
-parameter gem0__design_cfg3 = 32'hE000B288;
-parameter val_gem0__design_cfg3 = 32'h00000000;
-parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF;
-
-parameter gem0__design_cfg4 = 32'hE000B28C;
-parameter val_gem0__design_cfg4 = 32'h00000000;
-parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF;
-
-parameter gem0__design_cfg5 = 32'hE000B290;
-parameter val_gem0__design_cfg5 = 32'h002F2045;
-parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF;
-
-parameter gem0__design_cfg6 = 32'hE000B294;
-parameter val_gem0__design_cfg6 = 32'h00000000;
-parameter mask_gem0__design_cfg6 = 32'h00000000;
-
-parameter gem0__design_cfg7 = 32'hE000B298;
-parameter val_gem0__design_cfg7 = 32'h00000000;
-parameter mask_gem0__design_cfg7 = 32'h00000000;
-
-parameter gem0__isr_pq1 = 32'hE000B400;
-parameter val_gem0__isr_pq1 = 32'h00000000;
-parameter mask_gem0__isr_pq1 = 32'h00000000;
-
-parameter gem0__isr_pq2 = 32'hE000B404;
-parameter val_gem0__isr_pq2 = 32'h00000000;
-parameter mask_gem0__isr_pq2 = 32'h00000000;
-
-parameter gem0__isr_pq3 = 32'hE000B408;
-parameter val_gem0__isr_pq3 = 32'h00000000;
-parameter mask_gem0__isr_pq3 = 32'h00000000;
-
-parameter gem0__isr_pq4 = 32'hE000B40C;
-parameter val_gem0__isr_pq4 = 32'h00000000;
-parameter mask_gem0__isr_pq4 = 32'h00000000;
-
-parameter gem0__isr_pq5 = 32'hE000B410;
-parameter val_gem0__isr_pq5 = 32'h00000000;
-parameter mask_gem0__isr_pq5 = 32'h00000000;
-
-parameter gem0__isr_pq6 = 32'hE000B414;
-parameter val_gem0__isr_pq6 = 32'h00000000;
-parameter mask_gem0__isr_pq6 = 32'h00000000;
-
-parameter gem0__isr_pq7 = 32'hE000B418;
-parameter val_gem0__isr_pq7 = 32'h00000000;
-parameter mask_gem0__isr_pq7 = 32'h00000000;
-
-parameter gem0__tx_qbar_q1 = 32'hE000B440;
-parameter val_gem0__tx_qbar_q1 = 32'h00000000;
-parameter mask_gem0__tx_qbar_q1 = 32'h00000000;
-
-parameter gem0__tx_qbar_q2 = 32'hE000B444;
-parameter val_gem0__tx_qbar_q2 = 32'h00000000;
-parameter mask_gem0__tx_qbar_q2 = 32'h00000000;
-
-parameter gem0__tx_qbar_q3 = 32'hE000B448;
-parameter val_gem0__tx_qbar_q3 = 32'h00000000;
-parameter mask_gem0__tx_qbar_q3 = 32'h00000000;
-
-parameter gem0__tx_qbar_q4 = 32'hE000B44C;
-parameter val_gem0__tx_qbar_q4 = 32'h00000000;
-parameter mask_gem0__tx_qbar_q4 = 32'h00000000;
-
-parameter gem0__tx_qbar_q5 = 32'hE000B450;
-parameter val_gem0__tx_qbar_q5 = 32'h00000000;
-parameter mask_gem0__tx_qbar_q5 = 32'h00000000;
-
-parameter gem0__tx_qbar_q6 = 32'hE000B454;
-parameter val_gem0__tx_qbar_q6 = 32'h00000000;
-parameter mask_gem0__tx_qbar_q6 = 32'h00000000;
-
-parameter gem0__tx_qbar_q7 = 32'hE000B458;
-parameter val_gem0__tx_qbar_q7 = 32'h00000000;
-parameter mask_gem0__tx_qbar_q7 = 32'h00000000;
-
-parameter gem0__rx_qbar_q1 = 32'hE000B480;
-parameter val_gem0__rx_qbar_q1 = 32'h00000000;
-parameter mask_gem0__rx_qbar_q1 = 32'h00000000;
-
-parameter gem0__rx_qbar_q2 = 32'hE000B484;
-parameter val_gem0__rx_qbar_q2 = 32'h00000000;
-parameter mask_gem0__rx_qbar_q2 = 32'h00000000;
-
-parameter gem0__rx_qbar_q3 = 32'hE000B488;
-parameter val_gem0__rx_qbar_q3 = 32'h00000000;
-parameter mask_gem0__rx_qbar_q3 = 32'h00000000;
-
-parameter gem0__rx_qbar_q4 = 32'hE000B48C;
-parameter val_gem0__rx_qbar_q4 = 32'h00000000;
-parameter mask_gem0__rx_qbar_q4 = 32'h00000000;
-
-parameter gem0__rx_qbar_q5 = 32'hE000B490;
-parameter val_gem0__rx_qbar_q5 = 32'h00000000;
-parameter mask_gem0__rx_qbar_q5 = 32'h00000000;
-
-parameter gem0__rx_qbar_q6 = 32'hE000B494;
-parameter val_gem0__rx_qbar_q6 = 32'h00000000;
-parameter mask_gem0__rx_qbar_q6 = 32'h00000000;
-
-parameter gem0__rx_qbar_q7 = 32'hE000B498;
-parameter val_gem0__rx_qbar_q7 = 32'h00000000;
-parameter mask_gem0__rx_qbar_q7 = 32'h00000000;
-
-parameter gem0__rx_bufsz_q1 = 32'hE000B4A0;
-parameter val_gem0__rx_bufsz_q1 = 32'h00000000;
-parameter mask_gem0__rx_bufsz_q1 = 32'h00000000;
-
-parameter gem0__rx_bufsz_q2 = 32'hE000B4A4;
-parameter val_gem0__rx_bufsz_q2 = 32'h00000000;
-parameter mask_gem0__rx_bufsz_q2 = 32'h00000000;
-
-parameter gem0__rx_bufsz_q3 = 32'hE000B4A8;
-parameter val_gem0__rx_bufsz_q3 = 32'h00000000;
-parameter mask_gem0__rx_bufsz_q3 = 32'h00000000;
-
-parameter gem0__rx_bufsz_q4 = 32'hE000B4AC;
-parameter val_gem0__rx_bufsz_q4 = 32'h00000000;
-parameter mask_gem0__rx_bufsz_q4 = 32'h00000000;
-
-parameter gem0__rx_bufsz_q5 = 32'hE000B4B0;
-parameter val_gem0__rx_bufsz_q5 = 32'h00000000;
-parameter mask_gem0__rx_bufsz_q5 = 32'h00000000;
-
-parameter gem0__rx_bufsz_q6 = 32'hE000B4B4;
-parameter val_gem0__rx_bufsz_q6 = 32'h00000000;
-parameter mask_gem0__rx_bufsz_q6 = 32'h00000000;
-
-parameter gem0__rx_bufsz_q7 = 32'hE000B4B8;
-parameter val_gem0__rx_bufsz_q7 = 32'h00000000;
-parameter mask_gem0__rx_bufsz_q7 = 32'h00000000;
-
-parameter gem0__screen_t1_r0 = 32'hE000B500;
-parameter val_gem0__screen_t1_r0 = 32'h00000000;
-parameter mask_gem0__screen_t1_r0 = 32'h00000000;
-
-parameter gem0__screen_t1_r1 = 32'hE000B504;
-parameter val_gem0__screen_t1_r1 = 32'h00000000;
-parameter mask_gem0__screen_t1_r1 = 32'h00000000;
-
-parameter gem0__screen_t1_r2 = 32'hE000B508;
-parameter val_gem0__screen_t1_r2 = 32'h00000000;
-parameter mask_gem0__screen_t1_r2 = 32'h00000000;
-
-parameter gem0__screen_t1_r3 = 32'hE000B50C;
-parameter val_gem0__screen_t1_r3 = 32'h00000000;
-parameter mask_gem0__screen_t1_r3 = 32'h00000000;
-
-parameter gem0__screen_t1_r4 = 32'hE000B510;
-parameter val_gem0__screen_t1_r4 = 32'h00000000;
-parameter mask_gem0__screen_t1_r4 = 32'h00000000;
-
-parameter gem0__screen_t1_r5 = 32'hE000B514;
-parameter val_gem0__screen_t1_r5 = 32'h00000000;
-parameter mask_gem0__screen_t1_r5 = 32'h00000000;
-
-parameter gem0__screen_t1_r6 = 32'hE000B518;
-parameter val_gem0__screen_t1_r6 = 32'h00000000;
-parameter mask_gem0__screen_t1_r6 = 32'h00000000;
-
-parameter gem0__screen_t1_r7 = 32'hE000B51C;
-parameter val_gem0__screen_t1_r7 = 32'h00000000;
-parameter mask_gem0__screen_t1_r7 = 32'h00000000;
-
-parameter gem0__screen_t1_r8 = 32'hE000B520;
-parameter val_gem0__screen_t1_r8 = 32'h00000000;
-parameter mask_gem0__screen_t1_r8 = 32'h00000000;
-
-parameter gem0__screen_t1_r9 = 32'hE000B524;
-parameter val_gem0__screen_t1_r9 = 32'h00000000;
-parameter mask_gem0__screen_t1_r9 = 32'h00000000;
-
-parameter gem0__screen_t1_r10 = 32'hE000B528;
-parameter val_gem0__screen_t1_r10 = 32'h00000000;
-parameter mask_gem0__screen_t1_r10 = 32'h00000000;
-
-parameter gem0__screen_t1_r11 = 32'hE000B52C;
-parameter val_gem0__screen_t1_r11 = 32'h00000000;
-parameter mask_gem0__screen_t1_r11 = 32'h00000000;
-
-parameter gem0__screen_t1_r12 = 32'hE000B530;
-parameter val_gem0__screen_t1_r12 = 32'h00000000;
-parameter mask_gem0__screen_t1_r12 = 32'h00000000;
-
-parameter gem0__screen_t1_r13 = 32'hE000B534;
-parameter val_gem0__screen_t1_r13 = 32'h00000000;
-parameter mask_gem0__screen_t1_r13 = 32'h00000000;
-
-parameter gem0__screen_t1_r14 = 32'hE000B538;
-parameter val_gem0__screen_t1_r14 = 32'h00000000;
-parameter mask_gem0__screen_t1_r14 = 32'h00000000;
-
-parameter gem0__screen_t1_r15 = 32'hE000B53C;
-parameter val_gem0__screen_t1_r15 = 32'h00000000;
-parameter mask_gem0__screen_t1_r15 = 32'h00000000;
-
-parameter gem0__screen_t2_r0 = 32'hE000B540;
-parameter val_gem0__screen_t2_r0 = 32'h00000000;
-parameter mask_gem0__screen_t2_r0 = 32'h00000000;
-
-parameter gem0__screen_t2_r1 = 32'hE000B544;
-parameter val_gem0__screen_t2_r1 = 32'h00000000;
-parameter mask_gem0__screen_t2_r1 = 32'h00000000;
-
-parameter gem0__screen_t2_r2 = 32'hE000B548;
-parameter val_gem0__screen_t2_r2 = 32'h00000000;
-parameter mask_gem0__screen_t2_r2 = 32'h00000000;
-
-parameter gem0__screen_t2_r3 = 32'hE000B54C;
-parameter val_gem0__screen_t2_r3 = 32'h00000000;
-parameter mask_gem0__screen_t2_r3 = 32'h00000000;
-
-parameter gem0__screen_t2_r4 = 32'hE000B550;
-parameter val_gem0__screen_t2_r4 = 32'h00000000;
-parameter mask_gem0__screen_t2_r4 = 32'h00000000;
-
-parameter gem0__screen_t2_r5 = 32'hE000B554;
-parameter val_gem0__screen_t2_r5 = 32'h00000000;
-parameter mask_gem0__screen_t2_r5 = 32'h00000000;
-
-parameter gem0__screen_t2_r6 = 32'hE000B558;
-parameter val_gem0__screen_t2_r6 = 32'h00000000;
-parameter mask_gem0__screen_t2_r6 = 32'h00000000;
-
-parameter gem0__screen_t2_r7 = 32'hE000B55C;
-parameter val_gem0__screen_t2_r7 = 32'h00000000;
-parameter mask_gem0__screen_t2_r7 = 32'h00000000;
-
-parameter gem0__screen_t2_r8 = 32'hE000B560;
-parameter val_gem0__screen_t2_r8 = 32'h00000000;
-parameter mask_gem0__screen_t2_r8 = 32'h00000000;
-
-parameter gem0__screen_t2_r9 = 32'hE000B564;
-parameter val_gem0__screen_t2_r9 = 32'h00000000;
-parameter mask_gem0__screen_t2_r9 = 32'h00000000;
-
-parameter gem0__screen_t2_r10 = 32'hE000B568;
-parameter val_gem0__screen_t2_r10 = 32'h00000000;
-parameter mask_gem0__screen_t2_r10 = 32'h00000000;
-
-parameter gem0__screen_t2_r11 = 32'hE000B56C;
-parameter val_gem0__screen_t2_r11 = 32'h00000000;
-parameter mask_gem0__screen_t2_r11 = 32'h00000000;
-
-parameter gem0__screen_t2_r12 = 32'hE000B570;
-parameter val_gem0__screen_t2_r12 = 32'h00000000;
-parameter mask_gem0__screen_t2_r12 = 32'h00000000;
-
-parameter gem0__screen_t2_r13 = 32'hE000B574;
-parameter val_gem0__screen_t2_r13 = 32'h00000000;
-parameter mask_gem0__screen_t2_r13 = 32'h00000000;
-
-parameter gem0__screen_t2_r14 = 32'hE000B578;
-parameter val_gem0__screen_t2_r14 = 32'h00000000;
-parameter mask_gem0__screen_t2_r14 = 32'h00000000;
-
-parameter gem0__screen_t2_r15 = 32'hE000B57C;
-parameter val_gem0__screen_t2_r15 = 32'h00000000;
-parameter mask_gem0__screen_t2_r15 = 32'h00000000;
-
-parameter gem0__intr_en_pq1 = 32'hE000B600;
-parameter val_gem0__intr_en_pq1 = 32'h00000000;
-parameter mask_gem0__intr_en_pq1 = 32'h00000000;
-
-parameter gem0__intr_en_pq2 = 32'hE000B604;
-parameter val_gem0__intr_en_pq2 = 32'h00000000;
-parameter mask_gem0__intr_en_pq2 = 32'h00000000;
-
-parameter gem0__intr_en_pq3 = 32'hE000B608;
-parameter val_gem0__intr_en_pq3 = 32'h00000000;
-parameter mask_gem0__intr_en_pq3 = 32'h00000000;
-
-parameter gem0__intr_en_pq4 = 32'hE000B60C;
-parameter val_gem0__intr_en_pq4 = 32'h00000000;
-parameter mask_gem0__intr_en_pq4 = 32'h00000000;
-
-parameter gem0__intr_en_pq5 = 32'hE000B610;
-parameter val_gem0__intr_en_pq5 = 32'h00000000;
-parameter mask_gem0__intr_en_pq5 = 32'h00000000;
-
-parameter gem0__intr_en_pq6 = 32'hE000B614;
-parameter val_gem0__intr_en_pq6 = 32'h00000000;
-parameter mask_gem0__intr_en_pq6 = 32'h00000000;
-
-parameter gem0__intr_en_pq7 = 32'hE000B618;
-parameter val_gem0__intr_en_pq7 = 32'h00000000;
-parameter mask_gem0__intr_en_pq7 = 32'h00000000;
-
-parameter gem0__intr_dis_pq1 = 32'hE000B620;
-parameter val_gem0__intr_dis_pq1 = 32'h00000000;
-parameter mask_gem0__intr_dis_pq1 = 32'h00000000;
-
-parameter gem0__intr_dis_pq2 = 32'hE000B624;
-parameter val_gem0__intr_dis_pq2 = 32'h00000000;
-parameter mask_gem0__intr_dis_pq2 = 32'h00000000;
-
-parameter gem0__intr_dis_pq3 = 32'hE000B628;
-parameter val_gem0__intr_dis_pq3 = 32'h00000000;
-parameter mask_gem0__intr_dis_pq3 = 32'h00000000;
-
-parameter gem0__intr_dis_pq4 = 32'hE000B62C;
-parameter val_gem0__intr_dis_pq4 = 32'h00000000;
-parameter mask_gem0__intr_dis_pq4 = 32'h00000000;
-
-parameter gem0__intr_dis_pq5 = 32'hE000B630;
-parameter val_gem0__intr_dis_pq5 = 32'h00000000;
-parameter mask_gem0__intr_dis_pq5 = 32'h00000000;
-
-parameter gem0__intr_dis_pq6 = 32'hE000B634;
-parameter val_gem0__intr_dis_pq6 = 32'h00000000;
-parameter mask_gem0__intr_dis_pq6 = 32'h00000000;
-
-parameter gem0__intr_dis_pq7 = 32'hE000B638;
-parameter val_gem0__intr_dis_pq7 = 32'h00000000;
-parameter mask_gem0__intr_dis_pq7 = 32'h00000000;
-
-parameter gem0__intr_mask_pq1 = 32'hE000B640;
-parameter val_gem0__intr_mask_pq1 = 32'h00000000;
-parameter mask_gem0__intr_mask_pq1 = 32'h00000000;
-
-parameter gem0__intr_mask_pq2 = 32'hE000B644;
-parameter val_gem0__intr_mask_pq2 = 32'h00000000;
-parameter mask_gem0__intr_mask_pq2 = 32'h00000000;
-
-parameter gem0__intr_mask_pq3 = 32'hE000B648;
-parameter val_gem0__intr_mask_pq3 = 32'h00000000;
-parameter mask_gem0__intr_mask_pq3 = 32'h00000000;
-
-parameter gem0__intr_mask_pq4 = 32'hE000B64C;
-parameter val_gem0__intr_mask_pq4 = 32'h00000000;
-parameter mask_gem0__intr_mask_pq4 = 32'h00000000;
-
-parameter gem0__intr_mask_pq5 = 32'hE000B650;
-parameter val_gem0__intr_mask_pq5 = 32'h00000000;
-parameter mask_gem0__intr_mask_pq5 = 32'h00000000;
-
-parameter gem0__intr_mask_pq6 = 32'hE000B654;
-parameter val_gem0__intr_mask_pq6 = 32'h00000000;
-parameter mask_gem0__intr_mask_pq6 = 32'h00000000;
-
-parameter gem0__intr_mask_pq7 = 32'hE000B658;
-parameter val_gem0__intr_mask_pq7 = 32'h00000000;
-parameter mask_gem0__intr_mask_pq7 = 32'h00000000;
-
-
-// ************************************************************
-// Module gem1 GEM
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gem1__net_ctrl = 32'hE000C000;
-parameter val_gem1__net_ctrl = 32'h00000000;
-parameter mask_gem1__net_ctrl = 32'hFFFFFFFF;
-
-parameter gem1__net_cfg = 32'hE000C004;
-parameter val_gem1__net_cfg = 32'h00080000;
-parameter mask_gem1__net_cfg = 32'hFFFFFFFF;
-
-parameter gem1__net_status = 32'hE000C008;
-parameter val_gem1__net_status = 32'h00000004;
-parameter mask_gem1__net_status = 32'hFFFFFFFD;
-
-parameter gem1__user_io = 32'hE000C00C;
-parameter val_gem1__user_io = 32'h00000000;
-parameter mask_gem1__user_io = 32'h0000FFFF;
-
-parameter gem1__dma_cfg = 32'hE000C010;
-parameter val_gem1__dma_cfg = 32'h00020784;
-parameter mask_gem1__dma_cfg = 32'hFFFFFFFF;
-
-parameter gem1__tx_status = 32'hE000C014;
-parameter val_gem1__tx_status = 32'h00000000;
-parameter mask_gem1__tx_status = 32'hFFFFFFFF;
-
-parameter gem1__rx_qbar = 32'hE000C018;
-parameter val_gem1__rx_qbar = 32'h00000000;
-parameter mask_gem1__rx_qbar = 32'hFFFFFFFF;
-
-parameter gem1__tx_qbar = 32'hE000C01C;
-parameter val_gem1__tx_qbar = 32'h00000000;
-parameter mask_gem1__tx_qbar = 32'hFFFFFFFF;
-
-parameter gem1__rx_status = 32'hE000C020;
-parameter val_gem1__rx_status = 32'h00000000;
-parameter mask_gem1__rx_status = 32'hFFFFFFFF;
-
-parameter gem1__intr_status = 32'hE000C024;
-parameter val_gem1__intr_status = 32'h00000000;
-parameter mask_gem1__intr_status = 32'hFFFFFFFF;
-
-parameter gem1__intr_en = 32'hE000C028;
-parameter val_gem1__intr_en = 32'h00000000;
-parameter mask_gem1__intr_en = 32'h00000000;
-
-parameter gem1__intr_dis = 32'hE000C02C;
-parameter val_gem1__intr_dis = 32'h00000000;
-parameter mask_gem1__intr_dis = 32'h00000000;
-
-parameter gem1__intr_mask = 32'hE000C030;
-parameter val_gem1__intr_mask = 32'h0001FFFF;
-parameter mask_gem1__intr_mask = 32'hFC01FFFF;
-
-parameter gem1__phy_maint = 32'hE000C034;
-parameter val_gem1__phy_maint = 32'h00000000;
-parameter mask_gem1__phy_maint = 32'hFFFFFFFF;
-
-parameter gem1__rx_pauseq = 32'hE000C038;
-parameter val_gem1__rx_pauseq = 32'h00000000;
-parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF;
-
-parameter gem1__tx_pauseq = 32'hE000C03C;
-parameter val_gem1__tx_pauseq = 32'h0000FFFF;
-parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF;
-
-parameter gem1__tx_partial_st_fwd = 32'hE000C040;
-parameter val_gem1__tx_partial_st_fwd = 32'h000003FF;
-parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF;
-
-parameter gem1__rx_partial_st_fwd = 32'hE000C044;
-parameter val_gem1__rx_partial_st_fwd = 32'h000003FF;
-parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF;
-
-parameter gem1__hash_bot = 32'hE000C080;
-parameter val_gem1__hash_bot = 32'h00000000;
-parameter mask_gem1__hash_bot = 32'hFFFFFFFF;
-
-parameter gem1__hash_top = 32'hE000C084;
-parameter val_gem1__hash_top = 32'h00000000;
-parameter mask_gem1__hash_top = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr1_bot = 32'hE000C088;
-parameter val_gem1__spec_addr1_bot = 32'h00000000;
-parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr1_top = 32'hE000C08C;
-parameter val_gem1__spec_addr1_top = 32'h00000000;
-parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr2_bot = 32'hE000C090;
-parameter val_gem1__spec_addr2_bot = 32'h00000000;
-parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr2_top = 32'hE000C094;
-parameter val_gem1__spec_addr2_top = 32'h00000000;
-parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr3_bot = 32'hE000C098;
-parameter val_gem1__spec_addr3_bot = 32'h00000000;
-parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr3_top = 32'hE000C09C;
-parameter val_gem1__spec_addr3_top = 32'h00000000;
-parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr4_bot = 32'hE000C0A0;
-parameter val_gem1__spec_addr4_bot = 32'h00000000;
-parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr4_top = 32'hE000C0A4;
-parameter val_gem1__spec_addr4_top = 32'h00000000;
-parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF;
-
-parameter gem1__type_id_match1 = 32'hE000C0A8;
-parameter val_gem1__type_id_match1 = 32'h00000000;
-parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF;
-
-parameter gem1__type_id_match2 = 32'hE000C0AC;
-parameter val_gem1__type_id_match2 = 32'h00000000;
-parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF;
-
-parameter gem1__type_id_match3 = 32'hE000C0B0;
-parameter val_gem1__type_id_match3 = 32'h00000000;
-parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF;
-
-parameter gem1__type_id_match4 = 32'hE000C0B4;
-parameter val_gem1__type_id_match4 = 32'h00000000;
-parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF;
-
-parameter gem1__wake_on_lan = 32'hE000C0B8;
-parameter val_gem1__wake_on_lan = 32'h00000000;
-parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF;
-
-parameter gem1__ipg_stretch = 32'hE000C0BC;
-parameter val_gem1__ipg_stretch = 32'h00000000;
-parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF;
-
-parameter gem1__stacked_vlan = 32'hE000C0C0;
-parameter val_gem1__stacked_vlan = 32'h00000000;
-parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF;
-
-parameter gem1__tx_pfc_pause = 32'hE000C0C4;
-parameter val_gem1__tx_pfc_pause = 32'h00000000;
-parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8;
-parameter val_gem1__spec_addr1_mask_bot = 32'h00000000;
-parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF;
-
-parameter gem1__spec_addr1_mask_top = 32'hE000C0CC;
-parameter val_gem1__spec_addr1_mask_top = 32'h00000000;
-parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF;
-
-parameter gem1__module_id = 32'hE000C0FC;
-parameter val_gem1__module_id = 32'h00020118;
-parameter mask_gem1__module_id = 32'hFFFFFFFF;
-
-parameter gem1__octets_tx_bot = 32'hE000C100;
-parameter val_gem1__octets_tx_bot = 32'h00000000;
-parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF;
-
-parameter gem1__octets_tx_top = 32'hE000C104;
-parameter val_gem1__octets_tx_top = 32'h00000000;
-parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF;
-
-parameter gem1__frames_tx = 32'hE000C108;
-parameter val_gem1__frames_tx = 32'h00000000;
-parameter mask_gem1__frames_tx = 32'hFFFFFFFF;
-
-parameter gem1__broadcast_frames_tx = 32'hE000C10C;
-parameter val_gem1__broadcast_frames_tx = 32'h00000000;
-parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF;
-
-parameter gem1__multi_frames_tx = 32'hE000C110;
-parameter val_gem1__multi_frames_tx = 32'h00000000;
-parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF;
-
-parameter gem1__pause_frames_tx = 32'hE000C114;
-parameter val_gem1__pause_frames_tx = 32'h00000000;
-parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF;
-
-parameter gem1__frames_64b_tx = 32'hE000C118;
-parameter val_gem1__frames_64b_tx = 32'h00000000;
-parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF;
-
-parameter gem1__frames_65to127b_tx = 32'hE000C11C;
-parameter val_gem1__frames_65to127b_tx = 32'h00000000;
-parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF;
-
-parameter gem1__frames_128to255b_tx = 32'hE000C120;
-parameter val_gem1__frames_128to255b_tx = 32'h00000000;
-parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF;
-
-parameter gem1__frames_256to511b_tx = 32'hE000C124;
-parameter val_gem1__frames_256to511b_tx = 32'h00000000;
-parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF;
-
-parameter gem1__frames_512to1023b_tx = 32'hE000C128;
-parameter val_gem1__frames_512to1023b_tx = 32'h00000000;
-parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF;
-
-parameter gem1__frames_1024to1518b_tx = 32'hE000C12C;
-parameter val_gem1__frames_1024to1518b_tx = 32'h00000000;
-parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF;
-
-parameter gem1__frames_gt1518b_tx = 32'hE000C130;
-parameter val_gem1__frames_gt1518b_tx = 32'h00000000;
-parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF;
-
-parameter gem1__tx_under_runs = 32'hE000C134;
-parameter val_gem1__tx_under_runs = 32'h00000000;
-parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF;
-
-parameter gem1__single_collisn_frames = 32'hE000C138;
-parameter val_gem1__single_collisn_frames = 32'h00000000;
-parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF;
-
-parameter gem1__multi_collisn_frames = 32'hE000C13C;
-parameter val_gem1__multi_collisn_frames = 32'h00000000;
-parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF;
-
-parameter gem1__excessive_collisns = 32'hE000C140;
-parameter val_gem1__excessive_collisns = 32'h00000000;
-parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF;
-
-parameter gem1__late_collisns = 32'hE000C144;
-parameter val_gem1__late_collisns = 32'h00000000;
-parameter mask_gem1__late_collisns = 32'hFFFFFFFF;
-
-parameter gem1__deferred_tx_frames = 32'hE000C148;
-parameter val_gem1__deferred_tx_frames = 32'h00000000;
-parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF;
-
-parameter gem1__carrier_sense_errs = 32'hE000C14C;
-parameter val_gem1__carrier_sense_errs = 32'h00000000;
-parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF;
-
-parameter gem1__octets_rx_bot = 32'hE000C150;
-parameter val_gem1__octets_rx_bot = 32'h00000000;
-parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF;
-
-parameter gem1__octets_rx_top = 32'hE000C154;
-parameter val_gem1__octets_rx_top = 32'h00000000;
-parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF;
-
-parameter gem1__frames_rx = 32'hE000C158;
-parameter val_gem1__frames_rx = 32'h00000000;
-parameter mask_gem1__frames_rx = 32'hFFFFFFFF;
-
-parameter gem1__bdcast_fames_rx = 32'hE000C15C;
-parameter val_gem1__bdcast_fames_rx = 32'h00000000;
-parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF;
-
-parameter gem1__multi_frames_rx = 32'hE000C160;
-parameter val_gem1__multi_frames_rx = 32'h00000000;
-parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF;
-
-parameter gem1__pause_rx = 32'hE000C164;
-parameter val_gem1__pause_rx = 32'h00000000;
-parameter mask_gem1__pause_rx = 32'hFFFFFFFF;
-
-parameter gem1__frames_64b_rx = 32'hE000C168;
-parameter val_gem1__frames_64b_rx = 32'h00000000;
-parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF;
-
-parameter gem1__frames_65to127b_rx = 32'hE000C16C;
-parameter val_gem1__frames_65to127b_rx = 32'h00000000;
-parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF;
-
-parameter gem1__frames_128to255b_rx = 32'hE000C170;
-parameter val_gem1__frames_128to255b_rx = 32'h00000000;
-parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF;
-
-parameter gem1__frames_256to511b_rx = 32'hE000C174;
-parameter val_gem1__frames_256to511b_rx = 32'h00000000;
-parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF;
-
-parameter gem1__frames_512to1023b_rx = 32'hE000C178;
-parameter val_gem1__frames_512to1023b_rx = 32'h00000000;
-parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF;
-
-parameter gem1__frames_1024to1518b_rx = 32'hE000C17C;
-parameter val_gem1__frames_1024to1518b_rx = 32'h00000000;
-parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF;
-
-parameter gem1__frames_gt1518b_rx = 32'hE000C180;
-parameter val_gem1__frames_gt1518b_rx = 32'h00000000;
-parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF;
-
-parameter gem1__undersz_rx = 32'hE000C184;
-parameter val_gem1__undersz_rx = 32'h00000000;
-parameter mask_gem1__undersz_rx = 32'hFFFFFFFF;
-
-parameter gem1__oversz_rx = 32'hE000C188;
-parameter val_gem1__oversz_rx = 32'h00000000;
-parameter mask_gem1__oversz_rx = 32'hFFFFFFFF;
-
-parameter gem1__jab_rx = 32'hE000C18C;
-parameter val_gem1__jab_rx = 32'h00000000;
-parameter mask_gem1__jab_rx = 32'hFFFFFFFF;
-
-parameter gem1__fcs_errors = 32'hE000C190;
-parameter val_gem1__fcs_errors = 32'h00000000;
-parameter mask_gem1__fcs_errors = 32'hFFFFFFFF;
-
-parameter gem1__length_field_errors = 32'hE000C194;
-parameter val_gem1__length_field_errors = 32'h00000000;
-parameter mask_gem1__length_field_errors = 32'hFFFFFFFF;
-
-parameter gem1__rx_symbol_errors = 32'hE000C198;
-parameter val_gem1__rx_symbol_errors = 32'h00000000;
-parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF;
-
-parameter gem1__align_errors = 32'hE000C19C;
-parameter val_gem1__align_errors = 32'h00000000;
-parameter mask_gem1__align_errors = 32'hFFFFFFFF;
-
-parameter gem1__rx_resource_errors = 32'hE000C1A0;
-parameter val_gem1__rx_resource_errors = 32'h00000000;
-parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF;
-
-parameter gem1__rx_overrun_errors = 32'hE000C1A4;
-parameter val_gem1__rx_overrun_errors = 32'h00000000;
-parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF;
-
-parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8;
-parameter val_gem1__ip_hdr_csum_errors = 32'h00000000;
-parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF;
-
-parameter gem1__tcp_csum_errors = 32'hE000C1AC;
-parameter val_gem1__tcp_csum_errors = 32'h00000000;
-parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF;
-
-parameter gem1__udp_csum_errors = 32'hE000C1B0;
-parameter val_gem1__udp_csum_errors = 32'h00000000;
-parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF;
-
-parameter gem1__timer_strobe_s = 32'hE000C1C8;
-parameter val_gem1__timer_strobe_s = 32'h00000000;
-parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF;
-
-parameter gem1__timer_strobe_ns = 32'hE000C1CC;
-parameter val_gem1__timer_strobe_ns = 32'h00000000;
-parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF;
-
-parameter gem1__timer_s = 32'hE000C1D0;
-parameter val_gem1__timer_s = 32'h00000000;
-parameter mask_gem1__timer_s = 32'hFFFFFFFF;
-
-parameter gem1__timer_ns = 32'hE000C1D4;
-parameter val_gem1__timer_ns = 32'h00000000;
-parameter mask_gem1__timer_ns = 32'hFFFFFFFF;
-
-parameter gem1__timer_adjust = 32'hE000C1D8;
-parameter val_gem1__timer_adjust = 32'h00000000;
-parameter mask_gem1__timer_adjust = 32'hFFFFFFFF;
-
-parameter gem1__timer_incr = 32'hE000C1DC;
-parameter val_gem1__timer_incr = 32'h00000000;
-parameter mask_gem1__timer_incr = 32'hFFFFFFFF;
-
-parameter gem1__ptp_tx_s = 32'hE000C1E0;
-parameter val_gem1__ptp_tx_s = 32'h00000000;
-parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF;
-
-parameter gem1__ptp_tx_ns = 32'hE000C1E4;
-parameter val_gem1__ptp_tx_ns = 32'h00000000;
-parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF;
-
-parameter gem1__ptp_rx_s = 32'hE000C1E8;
-parameter val_gem1__ptp_rx_s = 32'h00000000;
-parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF;
-
-parameter gem1__ptp_rx_ns = 32'hE000C1EC;
-parameter val_gem1__ptp_rx_ns = 32'h00000000;
-parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF;
-
-parameter gem1__ptp_peer_tx_s = 32'hE000C1F0;
-parameter val_gem1__ptp_peer_tx_s = 32'h00000000;
-parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF;
-
-parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4;
-parameter val_gem1__ptp_peer_tx_ns = 32'h00000000;
-parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF;
-
-parameter gem1__ptp_peer_rx_s = 32'hE000C1F8;
-parameter val_gem1__ptp_peer_rx_s = 32'h00000000;
-parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF;
-
-parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC;
-parameter val_gem1__ptp_peer_rx_ns = 32'h00000000;
-parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF;
-
-parameter gem1__pcs_ctrl = 32'hE000C200;
-parameter val_gem1__pcs_ctrl = 32'h00000000;
-parameter mask_gem1__pcs_ctrl = 32'h00000000;
-
-parameter gem1__pcs_status = 32'hE000C204;
-parameter val_gem1__pcs_status = 32'h00000000;
-parameter mask_gem1__pcs_status = 32'h00000000;
-
-parameter gem1__pcs_upper_phy_id = 32'hE000C208;
-parameter val_gem1__pcs_upper_phy_id = 32'h00000000;
-parameter mask_gem1__pcs_upper_phy_id = 32'h00000000;
-
-parameter gem1__pcs_lower_phy_id = 32'hE000C20C;
-parameter val_gem1__pcs_lower_phy_id = 32'h00000000;
-parameter mask_gem1__pcs_lower_phy_id = 32'h00000000;
-
-parameter gem1__pcs_autoneg_ad = 32'hE000C210;
-parameter val_gem1__pcs_autoneg_ad = 32'h00000000;
-parameter mask_gem1__pcs_autoneg_ad = 32'h00000000;
-
-parameter gem1__pcs_autoneg_ability = 32'hE000C214;
-parameter val_gem1__pcs_autoneg_ability = 32'h00000000;
-parameter mask_gem1__pcs_autoneg_ability = 32'h00000000;
-
-parameter gem1__pcs_autonec_exp = 32'hE000C218;
-parameter val_gem1__pcs_autonec_exp = 32'h00000000;
-parameter mask_gem1__pcs_autonec_exp = 32'h00000000;
-
-parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C;
-parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000;
-parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000;
-
-parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220;
-parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000;
-parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000;
-
-parameter gem1__pcs_extended_status = 32'hE000C23C;
-parameter val_gem1__pcs_extended_status = 32'h00000000;
-parameter mask_gem1__pcs_extended_status = 32'h00000000;
-
-parameter gem1__design_cfg1 = 32'hE000C280;
-parameter val_gem1__design_cfg1 = 32'h02000000;
-parameter mask_gem1__design_cfg1 = 32'h0E000000;
-
-parameter gem1__design_cfg2 = 32'hE000C284;
-parameter val_gem1__design_cfg2 = 32'h2A813FFF;
-parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF;
-
-parameter gem1__design_cfg3 = 32'hE000C288;
-parameter val_gem1__design_cfg3 = 32'h00000000;
-parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF;
-
-parameter gem1__design_cfg4 = 32'hE000C28C;
-parameter val_gem1__design_cfg4 = 32'h00000000;
-parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF;
-
-parameter gem1__design_cfg5 = 32'hE000C290;
-parameter val_gem1__design_cfg5 = 32'h002F2045;
-parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF;
-
-parameter gem1__design_cfg6 = 32'hE000C294;
-parameter val_gem1__design_cfg6 = 32'h00000000;
-parameter mask_gem1__design_cfg6 = 32'h00000000;
-
-parameter gem1__design_cfg7 = 32'hE000C298;
-parameter val_gem1__design_cfg7 = 32'h00000000;
-parameter mask_gem1__design_cfg7 = 32'h00000000;
-
-parameter gem1__isr_pq1 = 32'hE000C400;
-parameter val_gem1__isr_pq1 = 32'h00000000;
-parameter mask_gem1__isr_pq1 = 32'h00000000;
-
-parameter gem1__isr_pq2 = 32'hE000C404;
-parameter val_gem1__isr_pq2 = 32'h00000000;
-parameter mask_gem1__isr_pq2 = 32'h00000000;
-
-parameter gem1__isr_pq3 = 32'hE000C408;
-parameter val_gem1__isr_pq3 = 32'h00000000;
-parameter mask_gem1__isr_pq3 = 32'h00000000;
-
-parameter gem1__isr_pq4 = 32'hE000C40C;
-parameter val_gem1__isr_pq4 = 32'h00000000;
-parameter mask_gem1__isr_pq4 = 32'h00000000;
-
-parameter gem1__isr_pq5 = 32'hE000C410;
-parameter val_gem1__isr_pq5 = 32'h00000000;
-parameter mask_gem1__isr_pq5 = 32'h00000000;
-
-parameter gem1__isr_pq6 = 32'hE000C414;
-parameter val_gem1__isr_pq6 = 32'h00000000;
-parameter mask_gem1__isr_pq6 = 32'h00000000;
-
-parameter gem1__isr_pq7 = 32'hE000C418;
-parameter val_gem1__isr_pq7 = 32'h00000000;
-parameter mask_gem1__isr_pq7 = 32'h00000000;
-
-parameter gem1__tx_qbar_q1 = 32'hE000C440;
-parameter val_gem1__tx_qbar_q1 = 32'h00000000;
-parameter mask_gem1__tx_qbar_q1 = 32'h00000000;
-
-parameter gem1__tx_qbar_q2 = 32'hE000C444;
-parameter val_gem1__tx_qbar_q2 = 32'h00000000;
-parameter mask_gem1__tx_qbar_q2 = 32'h00000000;
-
-parameter gem1__tx_qbar_q3 = 32'hE000C448;
-parameter val_gem1__tx_qbar_q3 = 32'h00000000;
-parameter mask_gem1__tx_qbar_q3 = 32'h00000000;
-
-parameter gem1__tx_qbar_q4 = 32'hE000C44C;
-parameter val_gem1__tx_qbar_q4 = 32'h00000000;
-parameter mask_gem1__tx_qbar_q4 = 32'h00000000;
-
-parameter gem1__tx_qbar_q5 = 32'hE000C450;
-parameter val_gem1__tx_qbar_q5 = 32'h00000000;
-parameter mask_gem1__tx_qbar_q5 = 32'h00000000;
-
-parameter gem1__tx_qbar_q6 = 32'hE000C454;
-parameter val_gem1__tx_qbar_q6 = 32'h00000000;
-parameter mask_gem1__tx_qbar_q6 = 32'h00000000;
-
-parameter gem1__tx_qbar_q7 = 32'hE000C458;
-parameter val_gem1__tx_qbar_q7 = 32'h00000000;
-parameter mask_gem1__tx_qbar_q7 = 32'h00000000;
-
-parameter gem1__rx_qbar_q1 = 32'hE000C480;
-parameter val_gem1__rx_qbar_q1 = 32'h00000000;
-parameter mask_gem1__rx_qbar_q1 = 32'h00000000;
-
-parameter gem1__rx_qbar_q2 = 32'hE000C484;
-parameter val_gem1__rx_qbar_q2 = 32'h00000000;
-parameter mask_gem1__rx_qbar_q2 = 32'h00000000;
-
-parameter gem1__rx_qbar_q3 = 32'hE000C488;
-parameter val_gem1__rx_qbar_q3 = 32'h00000000;
-parameter mask_gem1__rx_qbar_q3 = 32'h00000000;
-
-parameter gem1__rx_qbar_q4 = 32'hE000C48C;
-parameter val_gem1__rx_qbar_q4 = 32'h00000000;
-parameter mask_gem1__rx_qbar_q4 = 32'h00000000;
-
-parameter gem1__rx_qbar_q5 = 32'hE000C490;
-parameter val_gem1__rx_qbar_q5 = 32'h00000000;
-parameter mask_gem1__rx_qbar_q5 = 32'h00000000;
-
-parameter gem1__rx_qbar_q6 = 32'hE000C494;
-parameter val_gem1__rx_qbar_q6 = 32'h00000000;
-parameter mask_gem1__rx_qbar_q6 = 32'h00000000;
-
-parameter gem1__rx_qbar_q7 = 32'hE000C498;
-parameter val_gem1__rx_qbar_q7 = 32'h00000000;
-parameter mask_gem1__rx_qbar_q7 = 32'h00000000;
-
-parameter gem1__rx_bufsz_q1 = 32'hE000C4A0;
-parameter val_gem1__rx_bufsz_q1 = 32'h00000000;
-parameter mask_gem1__rx_bufsz_q1 = 32'h00000000;
-
-parameter gem1__rx_bufsz_q2 = 32'hE000C4A4;
-parameter val_gem1__rx_bufsz_q2 = 32'h00000000;
-parameter mask_gem1__rx_bufsz_q2 = 32'h00000000;
-
-parameter gem1__rx_bufsz_q3 = 32'hE000C4A8;
-parameter val_gem1__rx_bufsz_q3 = 32'h00000000;
-parameter mask_gem1__rx_bufsz_q3 = 32'h00000000;
-
-parameter gem1__rx_bufsz_q4 = 32'hE000C4AC;
-parameter val_gem1__rx_bufsz_q4 = 32'h00000000;
-parameter mask_gem1__rx_bufsz_q4 = 32'h00000000;
-
-parameter gem1__rx_bufsz_q5 = 32'hE000C4B0;
-parameter val_gem1__rx_bufsz_q5 = 32'h00000000;
-parameter mask_gem1__rx_bufsz_q5 = 32'h00000000;
-
-parameter gem1__rx_bufsz_q6 = 32'hE000C4B4;
-parameter val_gem1__rx_bufsz_q6 = 32'h00000000;
-parameter mask_gem1__rx_bufsz_q6 = 32'h00000000;
-
-parameter gem1__rx_bufsz_q7 = 32'hE000C4B8;
-parameter val_gem1__rx_bufsz_q7 = 32'h00000000;
-parameter mask_gem1__rx_bufsz_q7 = 32'h00000000;
-
-parameter gem1__screen_t1_r0 = 32'hE000C500;
-parameter val_gem1__screen_t1_r0 = 32'h00000000;
-parameter mask_gem1__screen_t1_r0 = 32'h00000000;
-
-parameter gem1__screen_t1_r1 = 32'hE000C504;
-parameter val_gem1__screen_t1_r1 = 32'h00000000;
-parameter mask_gem1__screen_t1_r1 = 32'h00000000;
-
-parameter gem1__screen_t1_r2 = 32'hE000C508;
-parameter val_gem1__screen_t1_r2 = 32'h00000000;
-parameter mask_gem1__screen_t1_r2 = 32'h00000000;
-
-parameter gem1__screen_t1_r3 = 32'hE000C50C;
-parameter val_gem1__screen_t1_r3 = 32'h00000000;
-parameter mask_gem1__screen_t1_r3 = 32'h00000000;
-
-parameter gem1__screen_t1_r4 = 32'hE000C510;
-parameter val_gem1__screen_t1_r4 = 32'h00000000;
-parameter mask_gem1__screen_t1_r4 = 32'h00000000;
-
-parameter gem1__screen_t1_r5 = 32'hE000C514;
-parameter val_gem1__screen_t1_r5 = 32'h00000000;
-parameter mask_gem1__screen_t1_r5 = 32'h00000000;
-
-parameter gem1__screen_t1_r6 = 32'hE000C518;
-parameter val_gem1__screen_t1_r6 = 32'h00000000;
-parameter mask_gem1__screen_t1_r6 = 32'h00000000;
-
-parameter gem1__screen_t1_r7 = 32'hE000C51C;
-parameter val_gem1__screen_t1_r7 = 32'h00000000;
-parameter mask_gem1__screen_t1_r7 = 32'h00000000;
-
-parameter gem1__screen_t1_r8 = 32'hE000C520;
-parameter val_gem1__screen_t1_r8 = 32'h00000000;
-parameter mask_gem1__screen_t1_r8 = 32'h00000000;
-
-parameter gem1__screen_t1_r9 = 32'hE000C524;
-parameter val_gem1__screen_t1_r9 = 32'h00000000;
-parameter mask_gem1__screen_t1_r9 = 32'h00000000;
-
-parameter gem1__screen_t1_r10 = 32'hE000C528;
-parameter val_gem1__screen_t1_r10 = 32'h00000000;
-parameter mask_gem1__screen_t1_r10 = 32'h00000000;
-
-parameter gem1__screen_t1_r11 = 32'hE000C52C;
-parameter val_gem1__screen_t1_r11 = 32'h00000000;
-parameter mask_gem1__screen_t1_r11 = 32'h00000000;
-
-parameter gem1__screen_t1_r12 = 32'hE000C530;
-parameter val_gem1__screen_t1_r12 = 32'h00000000;
-parameter mask_gem1__screen_t1_r12 = 32'h00000000;
-
-parameter gem1__screen_t1_r13 = 32'hE000C534;
-parameter val_gem1__screen_t1_r13 = 32'h00000000;
-parameter mask_gem1__screen_t1_r13 = 32'h00000000;
-
-parameter gem1__screen_t1_r14 = 32'hE000C538;
-parameter val_gem1__screen_t1_r14 = 32'h00000000;
-parameter mask_gem1__screen_t1_r14 = 32'h00000000;
-
-parameter gem1__screen_t1_r15 = 32'hE000C53C;
-parameter val_gem1__screen_t1_r15 = 32'h00000000;
-parameter mask_gem1__screen_t1_r15 = 32'h00000000;
-
-parameter gem1__screen_t2_r0 = 32'hE000C540;
-parameter val_gem1__screen_t2_r0 = 32'h00000000;
-parameter mask_gem1__screen_t2_r0 = 32'h00000000;
-
-parameter gem1__screen_t2_r1 = 32'hE000C544;
-parameter val_gem1__screen_t2_r1 = 32'h00000000;
-parameter mask_gem1__screen_t2_r1 = 32'h00000000;
-
-parameter gem1__screen_t2_r2 = 32'hE000C548;
-parameter val_gem1__screen_t2_r2 = 32'h00000000;
-parameter mask_gem1__screen_t2_r2 = 32'h00000000;
-
-parameter gem1__screen_t2_r3 = 32'hE000C54C;
-parameter val_gem1__screen_t2_r3 = 32'h00000000;
-parameter mask_gem1__screen_t2_r3 = 32'h00000000;
-
-parameter gem1__screen_t2_r4 = 32'hE000C550;
-parameter val_gem1__screen_t2_r4 = 32'h00000000;
-parameter mask_gem1__screen_t2_r4 = 32'h00000000;
-
-parameter gem1__screen_t2_r5 = 32'hE000C554;
-parameter val_gem1__screen_t2_r5 = 32'h00000000;
-parameter mask_gem1__screen_t2_r5 = 32'h00000000;
-
-parameter gem1__screen_t2_r6 = 32'hE000C558;
-parameter val_gem1__screen_t2_r6 = 32'h00000000;
-parameter mask_gem1__screen_t2_r6 = 32'h00000000;
-
-parameter gem1__screen_t2_r7 = 32'hE000C55C;
-parameter val_gem1__screen_t2_r7 = 32'h00000000;
-parameter mask_gem1__screen_t2_r7 = 32'h00000000;
-
-parameter gem1__screen_t2_r8 = 32'hE000C560;
-parameter val_gem1__screen_t2_r8 = 32'h00000000;
-parameter mask_gem1__screen_t2_r8 = 32'h00000000;
-
-parameter gem1__screen_t2_r9 = 32'hE000C564;
-parameter val_gem1__screen_t2_r9 = 32'h00000000;
-parameter mask_gem1__screen_t2_r9 = 32'h00000000;
-
-parameter gem1__screen_t2_r10 = 32'hE000C568;
-parameter val_gem1__screen_t2_r10 = 32'h00000000;
-parameter mask_gem1__screen_t2_r10 = 32'h00000000;
-
-parameter gem1__screen_t2_r11 = 32'hE000C56C;
-parameter val_gem1__screen_t2_r11 = 32'h00000000;
-parameter mask_gem1__screen_t2_r11 = 32'h00000000;
-
-parameter gem1__screen_t2_r12 = 32'hE000C570;
-parameter val_gem1__screen_t2_r12 = 32'h00000000;
-parameter mask_gem1__screen_t2_r12 = 32'h00000000;
-
-parameter gem1__screen_t2_r13 = 32'hE000C574;
-parameter val_gem1__screen_t2_r13 = 32'h00000000;
-parameter mask_gem1__screen_t2_r13 = 32'h00000000;
-
-parameter gem1__screen_t2_r14 = 32'hE000C578;
-parameter val_gem1__screen_t2_r14 = 32'h00000000;
-parameter mask_gem1__screen_t2_r14 = 32'h00000000;
-
-parameter gem1__screen_t2_r15 = 32'hE000C57C;
-parameter val_gem1__screen_t2_r15 = 32'h00000000;
-parameter mask_gem1__screen_t2_r15 = 32'h00000000;
-
-parameter gem1__intr_en_pq1 = 32'hE000C600;
-parameter val_gem1__intr_en_pq1 = 32'h00000000;
-parameter mask_gem1__intr_en_pq1 = 32'h00000000;
-
-parameter gem1__intr_en_pq2 = 32'hE000C604;
-parameter val_gem1__intr_en_pq2 = 32'h00000000;
-parameter mask_gem1__intr_en_pq2 = 32'h00000000;
-
-parameter gem1__intr_en_pq3 = 32'hE000C608;
-parameter val_gem1__intr_en_pq3 = 32'h00000000;
-parameter mask_gem1__intr_en_pq3 = 32'h00000000;
-
-parameter gem1__intr_en_pq4 = 32'hE000C60C;
-parameter val_gem1__intr_en_pq4 = 32'h00000000;
-parameter mask_gem1__intr_en_pq4 = 32'h00000000;
-
-parameter gem1__intr_en_pq5 = 32'hE000C610;
-parameter val_gem1__intr_en_pq5 = 32'h00000000;
-parameter mask_gem1__intr_en_pq5 = 32'h00000000;
-
-parameter gem1__intr_en_pq6 = 32'hE000C614;
-parameter val_gem1__intr_en_pq6 = 32'h00000000;
-parameter mask_gem1__intr_en_pq6 = 32'h00000000;
-
-parameter gem1__intr_en_pq7 = 32'hE000C618;
-parameter val_gem1__intr_en_pq7 = 32'h00000000;
-parameter mask_gem1__intr_en_pq7 = 32'h00000000;
-
-parameter gem1__intr_dis_pq1 = 32'hE000C620;
-parameter val_gem1__intr_dis_pq1 = 32'h00000000;
-parameter mask_gem1__intr_dis_pq1 = 32'h00000000;
-
-parameter gem1__intr_dis_pq2 = 32'hE000C624;
-parameter val_gem1__intr_dis_pq2 = 32'h00000000;
-parameter mask_gem1__intr_dis_pq2 = 32'h00000000;
-
-parameter gem1__intr_dis_pq3 = 32'hE000C628;
-parameter val_gem1__intr_dis_pq3 = 32'h00000000;
-parameter mask_gem1__intr_dis_pq3 = 32'h00000000;
-
-parameter gem1__intr_dis_pq4 = 32'hE000C62C;
-parameter val_gem1__intr_dis_pq4 = 32'h00000000;
-parameter mask_gem1__intr_dis_pq4 = 32'h00000000;
-
-parameter gem1__intr_dis_pq5 = 32'hE000C630;
-parameter val_gem1__intr_dis_pq5 = 32'h00000000;
-parameter mask_gem1__intr_dis_pq5 = 32'h00000000;
-
-parameter gem1__intr_dis_pq6 = 32'hE000C634;
-parameter val_gem1__intr_dis_pq6 = 32'h00000000;
-parameter mask_gem1__intr_dis_pq6 = 32'h00000000;
-
-parameter gem1__intr_dis_pq7 = 32'hE000C638;
-parameter val_gem1__intr_dis_pq7 = 32'h00000000;
-parameter mask_gem1__intr_dis_pq7 = 32'h00000000;
-
-parameter gem1__intr_mask_pq1 = 32'hE000C640;
-parameter val_gem1__intr_mask_pq1 = 32'h00000000;
-parameter mask_gem1__intr_mask_pq1 = 32'h00000000;
-
-parameter gem1__intr_mask_pq2 = 32'hE000C644;
-parameter val_gem1__intr_mask_pq2 = 32'h00000000;
-parameter mask_gem1__intr_mask_pq2 = 32'h00000000;
-
-parameter gem1__intr_mask_pq3 = 32'hE000C648;
-parameter val_gem1__intr_mask_pq3 = 32'h00000000;
-parameter mask_gem1__intr_mask_pq3 = 32'h00000000;
-
-parameter gem1__intr_mask_pq4 = 32'hE000C64C;
-parameter val_gem1__intr_mask_pq4 = 32'h00000000;
-parameter mask_gem1__intr_mask_pq4 = 32'h00000000;
-
-parameter gem1__intr_mask_pq5 = 32'hE000C650;
-parameter val_gem1__intr_mask_pq5 = 32'h00000000;
-parameter mask_gem1__intr_mask_pq5 = 32'h00000000;
-
-parameter gem1__intr_mask_pq6 = 32'hE000C654;
-parameter val_gem1__intr_mask_pq6 = 32'h00000000;
-parameter mask_gem1__intr_mask_pq6 = 32'h00000000;
-
-parameter gem1__intr_mask_pq7 = 32'hE000C658;
-parameter val_gem1__intr_mask_pq7 = 32'h00000000;
-parameter mask_gem1__intr_mask_pq7 = 32'h00000000;
-
-
-// ************************************************************
-// Module gpio gpio
-// doc version:
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gpio__MASK_DATA_0_LSW = 32'hE000A000;
-parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000;
-
-parameter gpio__MASK_DATA_0_MSW = 32'hE000A004;
-parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000;
-
-parameter gpio__MASK_DATA_1_LSW = 32'hE000A008;
-parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000;
-
-parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C;
-parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0;
-
-parameter gpio__MASK_DATA_2_LSW = 32'hE000A010;
-parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF;
-
-parameter gpio__MASK_DATA_2_MSW = 32'hE000A014;
-parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF;
-
-parameter gpio__MASK_DATA_3_LSW = 32'hE000A018;
-parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF;
-
-parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C;
-parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000;
-parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF;
-
-parameter gpio__DATA_0 = 32'hE000A040;
-parameter val_gpio__DATA_0 = 32'h00000000;
-parameter mask_gpio__DATA_0 = 32'h00000000;
-
-parameter gpio__DATA_1 = 32'hE000A044;
-parameter val_gpio__DATA_1 = 32'h00000000;
-parameter mask_gpio__DATA_1 = 32'h00000000;
-
-parameter gpio__DATA_2 = 32'hE000A048;
-parameter val_gpio__DATA_2 = 32'h00000000;
-parameter mask_gpio__DATA_2 = 32'hFFFFFFFF;
-
-parameter gpio__DATA_3 = 32'hE000A04C;
-parameter val_gpio__DATA_3 = 32'h00000000;
-parameter mask_gpio__DATA_3 = 32'hFFFFFFFF;
-
-parameter gpio__DATA_0_RO = 32'hE000A060;
-parameter val_gpio__DATA_0_RO = 32'h00000000;
-parameter mask_gpio__DATA_0_RO = 32'h00000000;
-
-parameter gpio__DATA_1_RO = 32'hE000A064;
-parameter val_gpio__DATA_1_RO = 32'h00000000;
-parameter mask_gpio__DATA_1_RO = 32'h00000000;
-
-parameter gpio__DATA_2_RO = 32'hE000A068;
-parameter val_gpio__DATA_2_RO = 32'h00000000;
-parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF;
-
-parameter gpio__DATA_3_RO = 32'hE000A06C;
-parameter val_gpio__DATA_3_RO = 32'h00000000;
-parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF;
-
-parameter gpio__BYPM_0 = 32'hE000A200;
-parameter val_gpio__BYPM_0 = 32'h00000000;
-parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF;
-
-parameter gpio__DIRM_0 = 32'hE000A204;
-parameter val_gpio__DIRM_0 = 32'h00000000;
-parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF;
-
-parameter gpio__OEN_0 = 32'hE000A208;
-parameter val_gpio__OEN_0 = 32'h00000000;
-parameter mask_gpio__OEN_0 = 32'hFFFFFFFF;
-
-parameter gpio__INT_MASK_0 = 32'hE000A20C;
-parameter val_gpio__INT_MASK_0 = 32'h00000000;
-parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF;
-
-parameter gpio__INT_EN_0 = 32'hE000A210;
-parameter val_gpio__INT_EN_0 = 32'h00000000;
-parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF;
-
-parameter gpio__INT_DIS_0 = 32'hE000A214;
-parameter val_gpio__INT_DIS_0 = 32'h00000000;
-parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF;
-
-parameter gpio__INT_STAT_0 = 32'hE000A218;
-parameter val_gpio__INT_STAT_0 = 32'h00000000;
-parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF;
-
-parameter gpio__INT_TYPE_0 = 32'hE000A21C;
-parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF;
-parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF;
-
-parameter gpio__INT_POLARITY_0 = 32'hE000A220;
-parameter val_gpio__INT_POLARITY_0 = 32'h00000000;
-parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF;
-
-parameter gpio__INT_ANY_0 = 32'hE000A224;
-parameter val_gpio__INT_ANY_0 = 32'h00000000;
-parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF;
-
-parameter gpio__BYPM_1 = 32'hE000A240;
-parameter val_gpio__BYPM_1 = 32'h00000000;
-parameter mask_gpio__BYPM_1 = 32'h003FFFFF;
-
-parameter gpio__DIRM_1 = 32'hE000A244;
-parameter val_gpio__DIRM_1 = 32'h00000000;
-parameter mask_gpio__DIRM_1 = 32'h003FFFFF;
-
-parameter gpio__OEN_1 = 32'hE000A248;
-parameter val_gpio__OEN_1 = 32'h00000000;
-parameter mask_gpio__OEN_1 = 32'h003FFFFF;
-
-parameter gpio__INT_MASK_1 = 32'hE000A24C;
-parameter val_gpio__INT_MASK_1 = 32'h00000000;
-parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF;
-
-parameter gpio__INT_EN_1 = 32'hE000A250;
-parameter val_gpio__INT_EN_1 = 32'h00000000;
-parameter mask_gpio__INT_EN_1 = 32'h003FFFFF;
-
-parameter gpio__INT_DIS_1 = 32'hE000A254;
-parameter val_gpio__INT_DIS_1 = 32'h00000000;
-parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF;
-
-parameter gpio__INT_STAT_1 = 32'hE000A258;
-parameter val_gpio__INT_STAT_1 = 32'h00000000;
-parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF;
-
-parameter gpio__INT_TYPE_1 = 32'hE000A25C;
-parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF;
-parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF;
-
-parameter gpio__INT_POLARITY_1 = 32'hE000A260;
-parameter val_gpio__INT_POLARITY_1 = 32'h00000000;
-parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF;
-
-parameter gpio__INT_ANY_1 = 32'hE000A264;
-parameter val_gpio__INT_ANY_1 = 32'h00000000;
-parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF;
-
-parameter gpio__BYPM_2 = 32'hE000A280;
-parameter val_gpio__BYPM_2 = 32'h00000000;
-parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF;
-
-parameter gpio__DIRM_2 = 32'hE000A284;
-parameter val_gpio__DIRM_2 = 32'h00000000;
-parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF;
-
-parameter gpio__OEN_2 = 32'hE000A288;
-parameter val_gpio__OEN_2 = 32'h00000000;
-parameter mask_gpio__OEN_2 = 32'hFFFFFFFF;
-
-parameter gpio__INT_MASK_2 = 32'hE000A28C;
-parameter val_gpio__INT_MASK_2 = 32'h00000000;
-parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF;
-
-parameter gpio__INT_EN_2 = 32'hE000A290;
-parameter val_gpio__INT_EN_2 = 32'h00000000;
-parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF;
-
-parameter gpio__INT_DIS_2 = 32'hE000A294;
-parameter val_gpio__INT_DIS_2 = 32'h00000000;
-parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF;
-
-parameter gpio__INT_STAT_2 = 32'hE000A298;
-parameter val_gpio__INT_STAT_2 = 32'h00000000;
-parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF;
-
-parameter gpio__INT_TYPE_2 = 32'hE000A29C;
-parameter val_gpio__INT_TYPE_2 = 32'hFFFFFFFF;
-parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF;
-
-parameter gpio__INT_POLARITY_2 = 32'hE000A2A0;
-parameter val_gpio__INT_POLARITY_2 = 32'h00000000;
-parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF;
-
-parameter gpio__INT_ANY_2 = 32'hE000A2A4;
-parameter val_gpio__INT_ANY_2 = 32'h00000000;
-parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF;
-
-parameter gpio__BYPM_3 = 32'hE000A2C0;
-parameter val_gpio__BYPM_3 = 32'h00000000;
-parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF;
-
-parameter gpio__DIRM_3 = 32'hE000A2C4;
-parameter val_gpio__DIRM_3 = 32'h00000000;
-parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF;
-
-parameter gpio__OEN_3 = 32'hE000A2C8;
-parameter val_gpio__OEN_3 = 32'h00000000;
-parameter mask_gpio__OEN_3 = 32'hFFFFFFFF;
-
-parameter gpio__INT_MASK_3 = 32'hE000A2CC;
-parameter val_gpio__INT_MASK_3 = 32'h00000000;
-parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF;
-
-parameter gpio__INT_EN_3 = 32'hE000A2D0;
-parameter val_gpio__INT_EN_3 = 32'h00000000;
-parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF;
-
-parameter gpio__INT_DIS_3 = 32'hE000A2D4;
-parameter val_gpio__INT_DIS_3 = 32'h00000000;
-parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF;
-
-parameter gpio__INT_STAT_3 = 32'hE000A2D8;
-parameter val_gpio__INT_STAT_3 = 32'h00000000;
-parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF;
-
-parameter gpio__INT_TYPE_3 = 32'hE000A2DC;
-parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF;
-parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF;
-
-parameter gpio__INT_POLARITY_3 = 32'hE000A2E0;
-parameter val_gpio__INT_POLARITY_3 = 32'h00000000;
-parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF;
-
-parameter gpio__INT_ANY_3 = 32'hE000A2E4;
-parameter val_gpio__INT_ANY_3 = 32'h00000000;
-parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module gpv_iou_switch gpv_iou_switch
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gpv_iou_switch__Remap = 32'hE0200000;
-parameter val_gpv_iou_switch__Remap = 32'h00000000;
-parameter mask_gpv_iou_switch__Remap = 32'h000000FF;
-
-parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008;
-parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000;
-parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001;
-
-parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C;
-parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000;
-parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001;
-
-parameter gpv_iou_switch__security4_qspi = 32'hE0200010;
-parameter val_gpv_iou_switch__security4_qspi = 32'h00000000;
-parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001;
-
-parameter gpv_iou_switch__security5_miou = 32'hE0200014;
-parameter val_gpv_iou_switch__security5_miou = 32'h00000000;
-parameter mask_gpv_iou_switch__security5_miou = 32'h00000001;
-
-parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018;
-parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000;
-parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF;
-
-parameter gpv_iou_switch__security7_smc = 32'hE020001C;
-parameter val_gpv_iou_switch__security7_smc = 32'h00000000;
-parameter mask_gpv_iou_switch__security7_smc = 32'h00000001;
-
-parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0;
-parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004;
-parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF;
-
-parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4;
-parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000;
-parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF;
-
-parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8;
-parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000;
-parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF;
-
-parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC;
-parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000;
-parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF;
-
-parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0;
-parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001;
-parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF;
-
-parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4;
-parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3;
-parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF;
-
-parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8;
-parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B;
-parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF;
-
-parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC;
-parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000;
-parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF;
-
-parameter gpv_iou_switch__component_id0 = 32'hE0201FF0;
-parameter val_gpv_iou_switch__component_id0 = 32'h0000000D;
-parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF;
-
-parameter gpv_iou_switch__component_id1 = 32'hE0201FF4;
-parameter val_gpv_iou_switch__component_id1 = 32'h000000F0;
-parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF;
-
-parameter gpv_iou_switch__component_id2 = 32'hE0201FF8;
-parameter val_gpv_iou_switch__component_id2 = 32'h00000005;
-parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF;
-
-parameter gpv_iou_switch__component_id3 = 32'hE0201FFC;
-parameter val_gpv_iou_switch__component_id3 = 32'h000000B1;
-parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF;
-
-parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008;
-parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003;
-
-parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044;
-parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000;
-parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000;
-
-parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008;
-parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003;
-
-parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044;
-parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000;
-parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000;
-
-parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008;
-parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008;
-parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008;
-parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028;
-parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007;
-
-parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100;
-parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000;
-parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F;
-
-parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104;
-parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000;
-parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F;
-
-parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108;
-parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028;
-parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007;
-
-parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100;
-parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000;
-parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F;
-
-parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104;
-parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000;
-parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F;
-
-parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108;
-parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028;
-parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007;
-
-parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100;
-parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000;
-parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F;
-
-parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104;
-parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000;
-parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F;
-
-parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108;
-parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028;
-parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007;
-
-parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100;
-parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000;
-parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F;
-
-parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104;
-parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000;
-parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F;
-
-parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108;
-parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028;
-parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007;
-
-parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100;
-parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000;
-parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F;
-
-parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104;
-parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000;
-parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F;
-
-parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108;
-parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028;
-parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007;
-
-parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100;
-parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000;
-parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F;
-
-parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104;
-parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000;
-parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F;
-
-parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108;
-parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003;
-
-parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108;
-parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000;
-parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003;
-
-
-// ************************************************************
-// Module gpv_qos301_cpu qos301
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C;
-parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000;
-parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF;
-
-parameter gpv_qos301_cpu__max_ot = 32'hF8946110;
-parameter val_gpv_qos301_cpu__max_ot = 32'h00000000;
-parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF;
-
-parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114;
-parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000;
-parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF;
-
-parameter gpv_qos301_cpu__aw_p = 32'hF8946118;
-parameter val_gpv_qos301_cpu__aw_p = 32'h00000000;
-parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000;
-
-parameter gpv_qos301_cpu__aw_b = 32'hF894611C;
-parameter val_gpv_qos301_cpu__aw_b = 32'h00000000;
-parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF;
-
-parameter gpv_qos301_cpu__aw_r = 32'hF8946120;
-parameter val_gpv_qos301_cpu__aw_r = 32'h00000000;
-parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000;
-
-parameter gpv_qos301_cpu__ar_p = 32'hF8946124;
-parameter val_gpv_qos301_cpu__ar_p = 32'h00000000;
-parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000;
-
-parameter gpv_qos301_cpu__ar_b = 32'hF8946128;
-parameter val_gpv_qos301_cpu__ar_b = 32'h00000000;
-parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF;
-
-parameter gpv_qos301_cpu__ar_r = 32'hF894612C;
-parameter val_gpv_qos301_cpu__ar_r = 32'h00000000;
-parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000;
-
-
-// ************************************************************
-// Module gpv_qos301_dmac qos301
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C;
-parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000;
-parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF;
-
-parameter gpv_qos301_dmac__max_ot = 32'hF8947110;
-parameter val_gpv_qos301_dmac__max_ot = 32'h00000000;
-parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF;
-
-parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114;
-parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000;
-parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF;
-
-parameter gpv_qos301_dmac__aw_p = 32'hF8947118;
-parameter val_gpv_qos301_dmac__aw_p = 32'h00000000;
-parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000;
-
-parameter gpv_qos301_dmac__aw_b = 32'hF894711C;
-parameter val_gpv_qos301_dmac__aw_b = 32'h00000000;
-parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF;
-
-parameter gpv_qos301_dmac__aw_r = 32'hF8947120;
-parameter val_gpv_qos301_dmac__aw_r = 32'h00000000;
-parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000;
-
-parameter gpv_qos301_dmac__ar_p = 32'hF8947124;
-parameter val_gpv_qos301_dmac__ar_p = 32'h00000000;
-parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000;
-
-parameter gpv_qos301_dmac__ar_b = 32'hF8947128;
-parameter val_gpv_qos301_dmac__ar_b = 32'h00000000;
-parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF;
-
-parameter gpv_qos301_dmac__ar_r = 32'hF894712C;
-parameter val_gpv_qos301_dmac__ar_r = 32'h00000000;
-parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000;
-
-
-// ************************************************************
-// Module gpv_qos301_iou qos301
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gpv_qos301_iou__qos_cntl = 32'hF894810C;
-parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000;
-parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF;
-
-parameter gpv_qos301_iou__max_ot = 32'hF8948110;
-parameter val_gpv_qos301_iou__max_ot = 32'h00000000;
-parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF;
-
-parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114;
-parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000;
-parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF;
-
-parameter gpv_qos301_iou__aw_p = 32'hF8948118;
-parameter val_gpv_qos301_iou__aw_p = 32'h00000000;
-parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000;
-
-parameter gpv_qos301_iou__aw_b = 32'hF894811C;
-parameter val_gpv_qos301_iou__aw_b = 32'h00000000;
-parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF;
-
-parameter gpv_qos301_iou__aw_r = 32'hF8948120;
-parameter val_gpv_qos301_iou__aw_r = 32'h00000000;
-parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000;
-
-parameter gpv_qos301_iou__ar_p = 32'hF8948124;
-parameter val_gpv_qos301_iou__ar_p = 32'h00000000;
-parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000;
-
-parameter gpv_qos301_iou__ar_b = 32'hF8948128;
-parameter val_gpv_qos301_iou__ar_b = 32'h00000000;
-parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF;
-
-parameter gpv_qos301_iou__ar_r = 32'hF894812C;
-parameter val_gpv_qos301_iou__ar_r = 32'h00000000;
-parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000;
-
-
-// ************************************************************
-// Module gpv_trustzone nic301_addr_region_ctrl_registers
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter gpv_trustzone__Remap = 32'hF8900000;
-parameter val_gpv_trustzone__Remap = 32'h00000000;
-parameter mask_gpv_trustzone__Remap = 32'h000000C0;
-
-parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C;
-parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000;
-parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001;
-
-parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020;
-parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000;
-parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001;
-
-parameter gpv_trustzone__security_apb = 32'hF8900028;
-parameter val_gpv_trustzone__security_apb = 32'h00000000;
-parameter mask_gpv_trustzone__security_apb = 32'h0000003F;
-
-
-// ************************************************************
-// Module i2c0 IIC
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter i2c0__Control_reg0 = 32'hE0004000;
-parameter val_i2c0__Control_reg0 = 32'h00000000;
-parameter mask_i2c0__Control_reg0 = 32'h0000FFFF;
-
-parameter i2c0__Status_reg0 = 32'hE0004004;
-parameter val_i2c0__Status_reg0 = 32'h00000000;
-parameter mask_i2c0__Status_reg0 = 32'h0000FFFF;
-
-parameter i2c0__I2C_address_reg0 = 32'hE0004008;
-parameter val_i2c0__I2C_address_reg0 = 32'h00000000;
-parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF;
-
-parameter i2c0__I2C_data_reg0 = 32'hE000400C;
-parameter val_i2c0__I2C_data_reg0 = 32'h00000000;
-parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF;
-
-parameter i2c0__Interrupt_status_reg0 = 32'hE0004010;
-parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000;
-parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF;
-
-parameter i2c0__Transfer_size_reg0 = 32'hE0004014;
-parameter val_i2c0__Transfer_size_reg0 = 32'h00000000;
-parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF;
-
-parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018;
-parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000;
-parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF;
-
-parameter i2c0__Time_out_reg0 = 32'hE000401C;
-parameter val_i2c0__Time_out_reg0 = 32'h0000001F;
-parameter mask_i2c0__Time_out_reg0 = 32'h000000FF;
-
-parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020;
-parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF;
-parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF;
-
-parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024;
-parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000;
-parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF;
-
-parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028;
-parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000;
-parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF;
-
-
-// ************************************************************
-// Module i2c1 IIC
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter i2c1__Control_reg0 = 32'hE0005000;
-parameter val_i2c1__Control_reg0 = 32'h00000000;
-parameter mask_i2c1__Control_reg0 = 32'h0000FFFF;
-
-parameter i2c1__Status_reg0 = 32'hE0005004;
-parameter val_i2c1__Status_reg0 = 32'h00000000;
-parameter mask_i2c1__Status_reg0 = 32'h0000FFFF;
-
-parameter i2c1__I2C_address_reg0 = 32'hE0005008;
-parameter val_i2c1__I2C_address_reg0 = 32'h00000000;
-parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF;
-
-parameter i2c1__I2C_data_reg0 = 32'hE000500C;
-parameter val_i2c1__I2C_data_reg0 = 32'h00000000;
-parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF;
-
-parameter i2c1__Interrupt_status_reg0 = 32'hE0005010;
-parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000;
-parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF;
-
-parameter i2c1__Transfer_size_reg0 = 32'hE0005014;
-parameter val_i2c1__Transfer_size_reg0 = 32'h00000000;
-parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF;
-
-parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018;
-parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000;
-parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF;
-
-parameter i2c1__Time_out_reg0 = 32'hE000501C;
-parameter val_i2c1__Time_out_reg0 = 32'h0000001F;
-parameter mask_i2c1__Time_out_reg0 = 32'h000000FF;
-
-parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020;
-parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF;
-parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF;
-
-parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024;
-parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000;
-parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF;
-
-parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028;
-parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000;
-parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF;
-
-
-// ************************************************************
-// Module l2cache L2Cpl310
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter l2cache__reg0_cache_id = 32'hF8F02000;
-parameter val_l2cache__reg0_cache_id = 32'h410000C8;
-parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF;
-
-parameter l2cache__reg0_cache_type = 32'hF8F02004;
-parameter val_l2cache__reg0_cache_type = 32'h9E300300;
-parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF;
-
-parameter l2cache__reg1_control = 32'hF8F02100;
-parameter val_l2cache__reg1_control = 32'h00000000;
-parameter mask_l2cache__reg1_control = 32'h7FFFFFFF;
-
-parameter l2cache__reg1_aux_control = 32'hF8F02104;
-parameter val_l2cache__reg1_aux_control = 32'h02050000;
-parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF;
-
-parameter l2cache__reg1_tag_ram_control = 32'hF8F02108;
-parameter val_l2cache__reg1_tag_ram_control = 32'h00000777;
-parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF;
-
-parameter l2cache__reg1_data_ram_control = 32'hF8F0210C;
-parameter val_l2cache__reg1_data_ram_control = 32'h00000777;
-parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200;
-parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000;
-parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204;
-parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000;
-parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208;
-parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000;
-parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C;
-parameter val_l2cache__reg2_ev_counter1 = 32'h00000000;
-parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_ev_counter0 = 32'hF8F02210;
-parameter val_l2cache__reg2_ev_counter0 = 32'h00000000;
-parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_int_mask = 32'hF8F02214;
-parameter val_l2cache__reg2_int_mask = 32'h00000000;
-parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_int_mask_status = 32'hF8F02218;
-parameter val_l2cache__reg2_int_mask_status = 32'h00000000;
-parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_int_raw_status = 32'hF8F0221C;
-parameter val_l2cache__reg2_int_raw_status = 32'h00000000;
-parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF;
-
-parameter l2cache__reg2_int_clear = 32'hF8F02220;
-parameter val_l2cache__reg2_int_clear = 32'h00000000;
-parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_cache_sync = 32'hF8F02730;
-parameter val_l2cache__reg7_cache_sync = 32'h00000000;
-parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_inv_pa = 32'hF8F02770;
-parameter val_l2cache__reg7_inv_pa = 32'h00000000;
-parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_inv_way = 32'hF8F0277C;
-parameter val_l2cache__reg7_inv_way = 32'h00000000;
-parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_clean_pa = 32'hF8F027B0;
-parameter val_l2cache__reg7_clean_pa = 32'h00000000;
-parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_clean_index = 32'hF8F027B8;
-parameter val_l2cache__reg7_clean_index = 32'h00000000;
-parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_clean_way = 32'hF8F027BC;
-parameter val_l2cache__reg7_clean_way = 32'h00000000;
-parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0;
-parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000;
-parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8;
-parameter val_l2cache__reg7_clean_inv_index = 32'h00000000;
-parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF;
-
-parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC;
-parameter val_l2cache__reg7_clean_inv_way = 32'h00000000;
-parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900;
-parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904;
-parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908;
-parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C;
-parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910;
-parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914;
-parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918;
-parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C;
-parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920;
-parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924;
-parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928;
-parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C;
-parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930;
-parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934;
-parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938;
-parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000;
-parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C;
-parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000;
-parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_lock_line_en = 32'hF8F02950;
-parameter val_l2cache__reg9_lock_line_en = 32'h00000000;
-parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF;
-
-parameter l2cache__reg9_unlock_way = 32'hF8F02954;
-parameter val_l2cache__reg9_unlock_way = 32'h00000000;
-parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF;
-
-parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00;
-parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001;
-parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF;
-
-parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04;
-parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000;
-parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF;
-
-parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40;
-parameter val_l2cache__reg15_debug_ctrl = 32'h00000000;
-parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF;
-
-parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60;
-parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000;
-parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF;
-
-parameter l2cache__reg15_power_ctrl = 32'hF8F02F80;
-parameter val_l2cache__reg15_power_ctrl = 32'h00000000;
-parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module mpcore mpcore
-// doc version: 1.3
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000;
-parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002;
-parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF;
-
-parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004;
-parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501;
-parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF;
-
-parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008;
-parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000;
-parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF;
-
-parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C;
-parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000;
-parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF;
-
-parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040;
-parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000;
-parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044;
-parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000;
-parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF;
-
-parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050;
-parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F;
-parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF;
-
-parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054;
-parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000;
-parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF;
-
-parameter mpcore__ICCICR = 32'hF8F00100;
-parameter val_mpcore__ICCICR = 32'h00000000;
-parameter mask_mpcore__ICCICR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCPMR = 32'hF8F00104;
-parameter val_mpcore__ICCPMR = 32'h00000000;
-parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCBPR = 32'hF8F00108;
-parameter val_mpcore__ICCBPR = 32'h00000002;
-parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCIAR = 32'hF8F0010C;
-parameter val_mpcore__ICCIAR = 32'h000003FF;
-parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCEOIR = 32'hF8F00110;
-parameter val_mpcore__ICCEOIR = 32'h00000000;
-parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCRPR = 32'hF8F00114;
-parameter val_mpcore__ICCRPR = 32'h000000FF;
-parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCHPIR = 32'hF8F00118;
-parameter val_mpcore__ICCHPIR = 32'h000003FF;
-parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCABPR = 32'hF8F0011C;
-parameter val_mpcore__ICCABPR = 32'h00000003;
-parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF;
-
-parameter mpcore__ICCIDR = 32'hF8F001FC;
-parameter val_mpcore__ICCIDR = 32'h3901243B;
-parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF;
-
-parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200;
-parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000;
-parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF;
-
-parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204;
-parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000;
-parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF;
-
-parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208;
-parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000;
-parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C;
-parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000;
-parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210;
-parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000;
-parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF;
-
-parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214;
-parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000;
-parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF;
-
-parameter mpcore__Auto_increment_Register = 32'hF8F00218;
-parameter val_mpcore__Auto_increment_Register = 32'h00000000;
-parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600;
-parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000;
-parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604;
-parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000;
-parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608;
-parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000;
-parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C;
-parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000;
-parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Watchdog_Load_Register = 32'hF8F00620;
-parameter val_mpcore__Watchdog_Load_Register = 32'h00000000;
-parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624;
-parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000;
-parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Watchdog_Control_Register = 32'hF8F00628;
-parameter val_mpcore__Watchdog_Control_Register = 32'h00000000;
-parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C;
-parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000;
-parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630;
-parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000;
-parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF;
-
-parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634;
-parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000;
-parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF;
-
-parameter mpcore__ICDDCR = 32'hF8F01000;
-parameter val_mpcore__ICDDCR = 32'h00000000;
-parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICTR = 32'hF8F01004;
-parameter val_mpcore__ICDICTR = 32'h00000C22;
-parameter mask_mpcore__ICDICTR = 32'hE000FFFF;
-
-parameter mpcore__ICDIIDR = 32'hF8F01008;
-parameter val_mpcore__ICDIIDR = 32'h0102043B;
-parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISR0 = 32'hF8F01080;
-parameter val_mpcore__ICDISR0 = 32'h00000000;
-parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISR1 = 32'hF8F01084;
-parameter val_mpcore__ICDISR1 = 32'h00000000;
-parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISR2 = 32'hF8F01088;
-parameter val_mpcore__ICDISR2 = 32'h00000000;
-parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISER0 = 32'hF8F01100;
-parameter val_mpcore__ICDISER0 = 32'h0000FFFF;
-parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISER1 = 32'hF8F01104;
-parameter val_mpcore__ICDISER1 = 32'h00000000;
-parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISER2 = 32'hF8F01108;
-parameter val_mpcore__ICDISER2 = 32'h00000000;
-parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICER0 = 32'hF8F01180;
-parameter val_mpcore__ICDICER0 = 32'h0000FFFF;
-parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICER1 = 32'hF8F01184;
-parameter val_mpcore__ICDICER1 = 32'h00000000;
-parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICER2 = 32'hF8F01188;
-parameter val_mpcore__ICDICER2 = 32'h00000000;
-parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISPR0 = 32'hF8F01200;
-parameter val_mpcore__ICDISPR0 = 32'h00000000;
-parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISPR1 = 32'hF8F01204;
-parameter val_mpcore__ICDISPR1 = 32'h00000000;
-parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDISPR2 = 32'hF8F01208;
-parameter val_mpcore__ICDISPR2 = 32'h00000000;
-parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICPR0 = 32'hF8F01280;
-parameter val_mpcore__ICDICPR0 = 32'h00000000;
-parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICPR1 = 32'hF8F01284;
-parameter val_mpcore__ICDICPR1 = 32'h00000000;
-parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICPR2 = 32'hF8F01288;
-parameter val_mpcore__ICDICPR2 = 32'h00000000;
-parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDABR0 = 32'hF8F01300;
-parameter val_mpcore__ICDABR0 = 32'h00000000;
-parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDABR1 = 32'hF8F01304;
-parameter val_mpcore__ICDABR1 = 32'h00000000;
-parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDABR2 = 32'hF8F01308;
-parameter val_mpcore__ICDABR2 = 32'h00000000;
-parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR0 = 32'hF8F01400;
-parameter val_mpcore__ICDIPR0 = 32'h00000000;
-parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR1 = 32'hF8F01404;
-parameter val_mpcore__ICDIPR1 = 32'h00000000;
-parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR2 = 32'hF8F01408;
-parameter val_mpcore__ICDIPR2 = 32'h00000000;
-parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR3 = 32'hF8F0140C;
-parameter val_mpcore__ICDIPR3 = 32'h00000000;
-parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR4 = 32'hF8F01410;
-parameter val_mpcore__ICDIPR4 = 32'h00000000;
-parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR5 = 32'hF8F01414;
-parameter val_mpcore__ICDIPR5 = 32'h00000000;
-parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR6 = 32'hF8F01418;
-parameter val_mpcore__ICDIPR6 = 32'h00000000;
-parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR7 = 32'hF8F0141C;
-parameter val_mpcore__ICDIPR7 = 32'h00000000;
-parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR8 = 32'hF8F01420;
-parameter val_mpcore__ICDIPR8 = 32'h00000000;
-parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR9 = 32'hF8F01424;
-parameter val_mpcore__ICDIPR9 = 32'h00000000;
-parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR10 = 32'hF8F01428;
-parameter val_mpcore__ICDIPR10 = 32'h00000000;
-parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR11 = 32'hF8F0142C;
-parameter val_mpcore__ICDIPR11 = 32'h00000000;
-parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR12 = 32'hF8F01430;
-parameter val_mpcore__ICDIPR12 = 32'h00000000;
-parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR13 = 32'hF8F01434;
-parameter val_mpcore__ICDIPR13 = 32'h00000000;
-parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR14 = 32'hF8F01438;
-parameter val_mpcore__ICDIPR14 = 32'h00000000;
-parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR15 = 32'hF8F0143C;
-parameter val_mpcore__ICDIPR15 = 32'h00000000;
-parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR16 = 32'hF8F01440;
-parameter val_mpcore__ICDIPR16 = 32'h00000000;
-parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR17 = 32'hF8F01444;
-parameter val_mpcore__ICDIPR17 = 32'h00000000;
-parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR18 = 32'hF8F01448;
-parameter val_mpcore__ICDIPR18 = 32'h00000000;
-parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR19 = 32'hF8F0144C;
-parameter val_mpcore__ICDIPR19 = 32'h00000000;
-parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR20 = 32'hF8F01450;
-parameter val_mpcore__ICDIPR20 = 32'h00000000;
-parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR21 = 32'hF8F01454;
-parameter val_mpcore__ICDIPR21 = 32'h00000000;
-parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR22 = 32'hF8F01458;
-parameter val_mpcore__ICDIPR22 = 32'h00000000;
-parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPR23 = 32'hF8F0145C;
-parameter val_mpcore__ICDIPR23 = 32'h00000000;
-parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR0 = 32'hF8F01800;
-parameter val_mpcore__ICDIPTR0 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR1 = 32'hF8F01804;
-parameter val_mpcore__ICDIPTR1 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR2 = 32'hF8F01808;
-parameter val_mpcore__ICDIPTR2 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR3 = 32'hF8F0180C;
-parameter val_mpcore__ICDIPTR3 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR4 = 32'hF8F01810;
-parameter val_mpcore__ICDIPTR4 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR5 = 32'hF8F01814;
-parameter val_mpcore__ICDIPTR5 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR6 = 32'hF8F01818;
-parameter val_mpcore__ICDIPTR6 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR7 = 32'hF8F0181C;
-parameter val_mpcore__ICDIPTR7 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR8 = 32'hF8F01820;
-parameter val_mpcore__ICDIPTR8 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR9 = 32'hF8F01824;
-parameter val_mpcore__ICDIPTR9 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR10 = 32'hF8F01828;
-parameter val_mpcore__ICDIPTR10 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR11 = 32'hF8F0182C;
-parameter val_mpcore__ICDIPTR11 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR12 = 32'hF8F01830;
-parameter val_mpcore__ICDIPTR12 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR13 = 32'hF8F01834;
-parameter val_mpcore__ICDIPTR13 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR14 = 32'hF8F01838;
-parameter val_mpcore__ICDIPTR14 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR15 = 32'hF8F0183C;
-parameter val_mpcore__ICDIPTR15 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR16 = 32'hF8F01840;
-parameter val_mpcore__ICDIPTR16 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR17 = 32'hF8F01844;
-parameter val_mpcore__ICDIPTR17 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR18 = 32'hF8F01848;
-parameter val_mpcore__ICDIPTR18 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR19 = 32'hF8F0184C;
-parameter val_mpcore__ICDIPTR19 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR20 = 32'hF8F01850;
-parameter val_mpcore__ICDIPTR20 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR21 = 32'hF8F01854;
-parameter val_mpcore__ICDIPTR21 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR22 = 32'hF8F01858;
-parameter val_mpcore__ICDIPTR22 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDIPTR23 = 32'hF8F0185C;
-parameter val_mpcore__ICDIPTR23 = 32'h01010101;
-parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICFR0 = 32'hF8F01C00;
-parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA;
-parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICFR1 = 32'hF8F01C04;
-parameter val_mpcore__ICDICFR1 = 32'h7DC00000;
-parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICFR2 = 32'hF8F01C08;
-parameter val_mpcore__ICDICFR2 = 32'h55555555;
-parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICFR3 = 32'hF8F01C0C;
-parameter val_mpcore__ICDICFR3 = 32'h55555555;
-parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICFR4 = 32'hF8F01C10;
-parameter val_mpcore__ICDICFR4 = 32'h55555555;
-parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDICFR5 = 32'hF8F01C14;
-parameter val_mpcore__ICDICFR5 = 32'h55555555;
-parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF;
-
-parameter mpcore__ppi_status = 32'hF8F01D00;
-parameter val_mpcore__ppi_status = 32'h00000000;
-parameter mask_mpcore__ppi_status = 32'hFFFFFFFF;
-
-parameter mpcore__spi_status_0 = 32'hF8F01D04;
-parameter val_mpcore__spi_status_0 = 32'h00000000;
-parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF;
-
-parameter mpcore__spi_status_1 = 32'hF8F01D08;
-parameter val_mpcore__spi_status_1 = 32'h00000000;
-parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICDSGIR = 32'hF8F01F00;
-parameter val_mpcore__ICDSGIR = 32'h00000000;
-parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR4 = 32'hF8F01FD0;
-parameter val_mpcore__ICPIDR4 = 32'h00000004;
-parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR5 = 32'hF8F01FD4;
-parameter val_mpcore__ICPIDR5 = 32'h00000000;
-parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR6 = 32'hF8F01FD8;
-parameter val_mpcore__ICPIDR6 = 32'h00000000;
-parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR7 = 32'hF8F01FDC;
-parameter val_mpcore__ICPIDR7 = 32'h00000000;
-parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR0 = 32'hF8F01FE0;
-parameter val_mpcore__ICPIDR0 = 32'h00000090;
-parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR1 = 32'hF8F01FE4;
-parameter val_mpcore__ICPIDR1 = 32'h000000B3;
-parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR2 = 32'hF8F01FE8;
-parameter val_mpcore__ICPIDR2 = 32'h0000001B;
-parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICPIDR3 = 32'hF8F01FEC;
-parameter val_mpcore__ICPIDR3 = 32'h00000000;
-parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF;
-
-parameter mpcore__ICCIDR0 = 32'hF8F01FF0;
-parameter val_mpcore__ICCIDR0 = 32'h0000000D;
-parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF;
-
-parameter mpcore__ICCIDR1 = 32'hF8F01FF4;
-parameter val_mpcore__ICCIDR1 = 32'h000000F0;
-parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF;
-
-parameter mpcore__ICCIDR2 = 32'hF8F01FF8;
-parameter val_mpcore__ICCIDR2 = 32'h00000005;
-parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF;
-
-parameter mpcore__ICCIDR3 = 32'hF8F01FFC;
-parameter val_mpcore__ICCIDR3 = 32'h000000B1;
-parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module ocm ocm
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter ocm__OCM_PARITY_CTRL = 32'hF800C000;
-parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000;
-parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF;
-
-parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004;
-parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000;
-parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF;
-
-parameter ocm__OCM_IRQ_STS = 32'hF800C008;
-parameter val_ocm__OCM_IRQ_STS = 32'h00000000;
-parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF;
-
-parameter ocm__OCM_CONTROL = 32'hF800C00C;
-parameter val_ocm__OCM_CONTROL = 32'h00000000;
-parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module qspi qspi
-// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller
-// Design Specification document
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter qspi__Config_reg = 32'hE000D000;
-parameter val_qspi__Config_reg = 32'h80000000;
-parameter mask_qspi__Config_reg = 32'hFFFDFFFF;
-
-parameter qspi__Intr_status_REG = 32'hE000D004;
-parameter val_qspi__Intr_status_REG = 32'h00000004;
-parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF;
-
-parameter qspi__Intrpt_en_REG = 32'hE000D008;
-parameter val_qspi__Intrpt_en_REG = 32'h00000000;
-parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF;
-
-parameter qspi__Intrpt_dis_REG = 32'hE000D00C;
-parameter val_qspi__Intrpt_dis_REG = 32'h00000000;
-parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF;
-
-parameter qspi__Intrpt_mask_REG = 32'hE000D010;
-parameter val_qspi__Intrpt_mask_REG = 32'h00000000;
-parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF;
-
-parameter qspi__En_REG = 32'hE000D014;
-parameter val_qspi__En_REG = 32'h00000000;
-parameter mask_qspi__En_REG = 32'hFFFFFFFF;
-
-parameter qspi__Delay_REG = 32'hE000D018;
-parameter val_qspi__Delay_REG = 32'h00000000;
-parameter mask_qspi__Delay_REG = 32'hFFFFFFFF;
-
-parameter qspi__TXD0 = 32'hE000D01C;
-parameter val_qspi__TXD0 = 32'h00000000;
-parameter mask_qspi__TXD0 = 32'hFFFFFFFF;
-
-parameter qspi__Rx_data_REG = 32'hE000D020;
-parameter val_qspi__Rx_data_REG = 32'h00000000;
-parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF;
-
-parameter qspi__Slave_Idle_count_REG = 32'hE000D024;
-parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF;
-parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF;
-
-parameter qspi__TX_thres_REG = 32'hE000D028;
-parameter val_qspi__TX_thres_REG = 32'h00000001;
-parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF;
-
-parameter qspi__RX_thres_REG = 32'hE000D02C;
-parameter val_qspi__RX_thres_REG = 32'h00000001;
-parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF;
-
-parameter qspi__GPIO = 32'hE000D030;
-parameter val_qspi__GPIO = 32'h00000001;
-parameter mask_qspi__GPIO = 32'hFFFFFFFF;
-
-parameter qspi__LPBK_DLY_ADJ = 32'hE000D038;
-parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033;
-parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF;
-
-parameter qspi__TXD1 = 32'hE000D080;
-parameter val_qspi__TXD1 = 32'h00000000;
-parameter mask_qspi__TXD1 = 32'hFFFFFFFF;
-
-parameter qspi__TXD2 = 32'hE000D084;
-parameter val_qspi__TXD2 = 32'h00000000;
-parameter mask_qspi__TXD2 = 32'hFFFFFFFF;
-
-parameter qspi__TXD3 = 32'hE000D088;
-parameter val_qspi__TXD3 = 32'h00000000;
-parameter mask_qspi__TXD3 = 32'hFFFFFFFF;
-
-parameter qspi__LQSPI_CFG = 32'hE000D0A0;
-parameter val_qspi__LQSPI_CFG = 32'h03A002EB;
-parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF;
-
-parameter qspi__LQSPI_STS = 32'hE000D0A4;
-parameter val_qspi__LQSPI_STS = 32'h00000000;
-parameter mask_qspi__LQSPI_STS = 32'h000001FF;
-
-parameter qspi__MOD_ID = 32'hE000D0FC;
-parameter val_qspi__MOD_ID = 32'h01090101;
-parameter mask_qspi__MOD_ID = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module sd0 sdio
-// doc version: 4.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter sd0__SDMA_system_address_register = 32'hE0100000;
-parameter val_sd0__SDMA_system_address_register = 32'h00000000;
-parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF;
-
-parameter sd0__Block_Size_Block_Count = 32'hE0100004;
-parameter val_sd0__Block_Size_Block_Count = 32'h00000000;
-parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF;
-
-parameter sd0__Argument = 32'hE0100008;
-parameter val_sd0__Argument = 32'h00000000;
-parameter mask_sd0__Argument = 32'hFFFFFFFF;
-
-parameter sd0__Transfer_Mode_Command = 32'hE010000C;
-parameter val_sd0__Transfer_Mode_Command = 32'h00000000;
-parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF;
-
-parameter sd0__Response0 = 32'hE0100010;
-parameter val_sd0__Response0 = 32'h00000000;
-parameter mask_sd0__Response0 = 32'hFFFFFFFF;
-
-parameter sd0__Response1 = 32'hE0100014;
-parameter val_sd0__Response1 = 32'h00000000;
-parameter mask_sd0__Response1 = 32'hFFFFFFFF;
-
-parameter sd0__Response2 = 32'hE0100018;
-parameter val_sd0__Response2 = 32'h00000000;
-parameter mask_sd0__Response2 = 32'hFFFFFFFF;
-
-parameter sd0__Response3 = 32'hE010001C;
-parameter val_sd0__Response3 = 32'h00000000;
-parameter mask_sd0__Response3 = 32'hFFFFFFFF;
-
-parameter sd0__Buffer_Data_Port = 32'hE0100020;
-parameter val_sd0__Buffer_Data_Port = 32'h00000000;
-parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF;
-
-parameter sd0__Present_State = 32'hE0100024;
-parameter val_sd0__Present_State = 32'h01F20000;
-parameter mask_sd0__Present_State = 32'h01FFFFFF;
-
-parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028;
-parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000;
-parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF;
-
-parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C;
-parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000;
-parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF;
-
-parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030;
-parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000;
-parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF;
-
-parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034;
-parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000;
-parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF;
-
-parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038;
-parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000;
-parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF;
-
-parameter sd0__Auto_CMD12_error_status = 32'hE010003C;
-parameter val_sd0__Auto_CMD12_error_status = 32'h00000000;
-parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF;
-
-parameter sd0__Capabilities = 32'hE0100040;
-parameter val_sd0__Capabilities = 32'h69EC0080;
-parameter mask_sd0__Capabilities = 32'h7FFFFFFF;
-
-parameter sd0__Maximum_current_capabilities = 32'hE0100048;
-parameter val_sd0__Maximum_current_capabilities = 32'h00000001;
-parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF;
-
-parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050;
-parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000;
-parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF;
-
-parameter sd0__ADMA_error_status = 32'hE0100054;
-parameter val_sd0__ADMA_error_status = 32'h00000000;
-parameter mask_sd0__ADMA_error_status = 32'h00000007;
-
-parameter sd0__ADMA_system_address = 32'hE0100058;
-parameter val_sd0__ADMA_system_address = 32'h00000000;
-parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF;
-
-parameter sd0__Boot_Timeout_control = 32'hE0100060;
-parameter val_sd0__Boot_Timeout_control = 32'h00000000;
-parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF;
-
-parameter sd0__Debug_Selection = 32'hE0100064;
-parameter val_sd0__Debug_Selection = 32'h00000000;
-parameter mask_sd0__Debug_Selection = 32'h00000001;
-
-parameter sd0__SPI_interrupt_support = 32'hE01000F0;
-parameter val_sd0__SPI_interrupt_support = 32'h00000000;
-parameter mask_sd0__SPI_interrupt_support = 32'h000000FF;
-
-parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC;
-parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000;
-parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module sd1 sdio
-// doc version: 4.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter sd1__SDMA_system_address_register = 32'hE0101000;
-parameter val_sd1__SDMA_system_address_register = 32'h00000000;
-parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF;
-
-parameter sd1__Block_Size_Block_Count = 32'hE0101004;
-parameter val_sd1__Block_Size_Block_Count = 32'h00000000;
-parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF;
-
-parameter sd1__Argument = 32'hE0101008;
-parameter val_sd1__Argument = 32'h00000000;
-parameter mask_sd1__Argument = 32'hFFFFFFFF;
-
-parameter sd1__Transfer_Mode_Command = 32'hE010100C;
-parameter val_sd1__Transfer_Mode_Command = 32'h00000000;
-parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF;
-
-parameter sd1__Response0 = 32'hE0101010;
-parameter val_sd1__Response0 = 32'h00000000;
-parameter mask_sd1__Response0 = 32'hFFFFFFFF;
-
-parameter sd1__Response1 = 32'hE0101014;
-parameter val_sd1__Response1 = 32'h00000000;
-parameter mask_sd1__Response1 = 32'hFFFFFFFF;
-
-parameter sd1__Response2 = 32'hE0101018;
-parameter val_sd1__Response2 = 32'h00000000;
-parameter mask_sd1__Response2 = 32'hFFFFFFFF;
-
-parameter sd1__Response3 = 32'hE010101C;
-parameter val_sd1__Response3 = 32'h00000000;
-parameter mask_sd1__Response3 = 32'hFFFFFFFF;
-
-parameter sd1__Buffer_Data_Port = 32'hE0101020;
-parameter val_sd1__Buffer_Data_Port = 32'h00000000;
-parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF;
-
-parameter sd1__Present_State = 32'hE0101024;
-parameter val_sd1__Present_State = 32'h01F20000;
-parameter mask_sd1__Present_State = 32'h01FFFFFF;
-
-parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028;
-parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000;
-parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF;
-
-parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C;
-parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000;
-parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF;
-
-parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030;
-parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000;
-parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF;
-
-parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034;
-parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000;
-parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF;
-
-parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038;
-parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000;
-parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF;
-
-parameter sd1__Auto_CMD12_error_status = 32'hE010103C;
-parameter val_sd1__Auto_CMD12_error_status = 32'h00000000;
-parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF;
-
-parameter sd1__Capabilities = 32'hE0101040;
-parameter val_sd1__Capabilities = 32'h69EC0080;
-parameter mask_sd1__Capabilities = 32'h7FFFFFFF;
-
-parameter sd1__Maximum_current_capabilities = 32'hE0101048;
-parameter val_sd1__Maximum_current_capabilities = 32'h00000001;
-parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF;
-
-parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050;
-parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000;
-parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF;
-
-parameter sd1__ADMA_error_status = 32'hE0101054;
-parameter val_sd1__ADMA_error_status = 32'h00000000;
-parameter mask_sd1__ADMA_error_status = 32'h00000007;
-
-parameter sd1__ADMA_system_address = 32'hE0101058;
-parameter val_sd1__ADMA_system_address = 32'h00000000;
-parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF;
-
-parameter sd1__Boot_Timeout_control = 32'hE0101060;
-parameter val_sd1__Boot_Timeout_control = 32'h00000000;
-parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF;
-
-parameter sd1__Debug_Selection = 32'hE0101064;
-parameter val_sd1__Debug_Selection = 32'h00000000;
-parameter mask_sd1__Debug_Selection = 32'h00000001;
-
-parameter sd1__SPI_interrupt_support = 32'hE01010F0;
-parameter val_sd1__SPI_interrupt_support = 32'h00000000;
-parameter mask_sd1__SPI_interrupt_support = 32'h000000FF;
-
-parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC;
-parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000;
-parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module slcr slcr
-// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter slcr__SCL = 32'hF8000000;
-parameter val_slcr__SCL = 32'h00000000;
-parameter mask_slcr__SCL = 32'hFFFFFFFF;
-
-parameter slcr__SLCR_LOCK = 32'hF8000004;
-parameter val_slcr__SLCR_LOCK = 32'h00000000;
-parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF;
-
-parameter slcr__SLCR_UNLOCK = 32'hF8000008;
-parameter val_slcr__SLCR_UNLOCK = 32'h00000000;
-parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF;
-
-parameter slcr__SLCR_LOCKSTA = 32'hF800000C;
-parameter val_slcr__SLCR_LOCKSTA = 32'h00000001;
-parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF;
-
-parameter slcr__ARM_PLL_CTRL = 32'hF8000100;
-parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008;
-parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DDR_PLL_CTRL = 32'hF8000104;
-parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008;
-parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__IO_PLL_CTRL = 32'hF8000108;
-parameter val_slcr__IO_PLL_CTRL = 32'h0001A008;
-parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__PLL_STATUS = 32'hF800010C;
-parameter val_slcr__PLL_STATUS = 32'h0000003F;
-parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF;
-
-parameter slcr__ARM_PLL_CFG = 32'hF8000110;
-parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0;
-parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF;
-
-parameter slcr__DDR_PLL_CFG = 32'hF8000114;
-parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0;
-parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF;
-
-parameter slcr__IO_PLL_CFG = 32'hF8000118;
-parameter val_slcr__IO_PLL_CFG = 32'h00177EA0;
-parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF;
-
-parameter slcr__PLL_BG_CTRL = 32'hF800011C;
-parameter val_slcr__PLL_BG_CTRL = 32'h00000000;
-parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__ARM_CLK_CTRL = 32'hF8000120;
-parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400;
-parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DDR_CLK_CTRL = 32'hF8000124;
-parameter val_slcr__DDR_CLK_CTRL = 32'h18400003;
-parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DCI_CLK_CTRL = 32'hF8000128;
-parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201;
-parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__APER_CLK_CTRL = 32'hF800012C;
-parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD;
-parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__USB0_CLK_CTRL = 32'hF8000130;
-parameter val_slcr__USB0_CLK_CTRL = 32'h00101941;
-parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__USB1_CLK_CTRL = 32'hF8000134;
-parameter val_slcr__USB1_CLK_CTRL = 32'h00101941;
-parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138;
-parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001;
-parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C;
-parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001;
-parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__GEM0_CLK_CTRL = 32'hF8000140;
-parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01;
-parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__GEM1_CLK_CTRL = 32'hF8000144;
-parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01;
-parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__SMC_CLK_CTRL = 32'hF8000148;
-parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21;
-parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C;
-parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821;
-parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__SDIO_CLK_CTRL = 32'hF8000150;
-parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03;
-parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__UART_CLK_CTRL = 32'hF8000154;
-parameter val_slcr__UART_CLK_CTRL = 32'h00003F03;
-parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__SPI_CLK_CTRL = 32'hF8000158;
-parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03;
-parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__CAN_CLK_CTRL = 32'hF800015C;
-parameter val_slcr__CAN_CLK_CTRL = 32'h00501903;
-parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160;
-parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000;
-parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DBG_CLK_CTRL = 32'hF8000164;
-parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03;
-parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__PCAP_CLK_CTRL = 32'hF8000168;
-parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01;
-parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C;
-parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000;
-parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170;
-parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800;
-parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA0_THR_CTRL = 32'hF8000174;
-parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000;
-parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA0_THR_CNT = 32'hF8000178;
-parameter val_slcr__FPGA0_THR_CNT = 32'h00000000;
-parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF;
-
-parameter slcr__FPGA0_THR_STA = 32'hF800017C;
-parameter val_slcr__FPGA0_THR_STA = 32'h00010000;
-parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF;
-
-parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180;
-parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800;
-parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA1_THR_CTRL = 32'hF8000184;
-parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000;
-parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA1_THR_CNT = 32'hF8000188;
-parameter val_slcr__FPGA1_THR_CNT = 32'h00000000;
-parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF;
-
-parameter slcr__FPGA1_THR_STA = 32'hF800018C;
-parameter val_slcr__FPGA1_THR_STA = 32'h00010000;
-parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF;
-
-parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190;
-parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800;
-parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA2_THR_CTRL = 32'hF8000194;
-parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000;
-parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA2_THR_CNT = 32'hF8000198;
-parameter val_slcr__FPGA2_THR_CNT = 32'h00000000;
-parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF;
-
-parameter slcr__FPGA2_THR_STA = 32'hF800019C;
-parameter val_slcr__FPGA2_THR_STA = 32'h00010000;
-parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF;
-
-parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0;
-parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800;
-parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4;
-parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000;
-parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA3_THR_CNT = 32'hF80001A8;
-parameter val_slcr__FPGA3_THR_CNT = 32'h00000000;
-parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF;
-
-parameter slcr__FPGA3_THR_STA = 32'hF80001AC;
-parameter val_slcr__FPGA3_THR_STA = 32'h00010000;
-parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF;
-
-parameter slcr__SRST_UART_CTRL = 32'hF80001B0;
-parameter val_slcr__SRST_UART_CTRL = 32'h00000000;
-parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__BANDGAP_TRIM = 32'hF80001B8;
-parameter val_slcr__BANDGAP_TRIM = 32'h0000001F;
-parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF;
-
-parameter slcr__CC_TEST = 32'hF80001BC;
-parameter val_slcr__CC_TEST = 32'h00000000;
-parameter mask_slcr__CC_TEST = 32'hFFFFFFFF;
-
-parameter slcr__PLL_PREDIVISOR = 32'hF80001C0;
-parameter val_slcr__PLL_PREDIVISOR = 32'h00000001;
-parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF;
-
-parameter slcr__CLK_621_TRUE = 32'hF80001C4;
-parameter val_slcr__CLK_621_TRUE = 32'h00000001;
-parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1;
-
-parameter slcr__PICTURE_DBG = 32'hF80001D0;
-parameter val_slcr__PICTURE_DBG = 32'h00000000;
-parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF;
-
-parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4;
-parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000;
-parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF;
-
-parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8;
-parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000;
-parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF;
-
-parameter slcr__PSS_RST_CTRL = 32'hF8000200;
-parameter val_slcr__PSS_RST_CTRL = 32'h00000000;
-parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DDR_RST_CTRL = 32'hF8000204;
-parameter val_slcr__DDR_RST_CTRL = 32'h00000000;
-parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__TOPSW_RST_CTRL = 32'hF8000208;
-parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000;
-parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DMAC_RST_CTRL = 32'hF800020C;
-parameter val_slcr__DMAC_RST_CTRL = 32'h00000000;
-parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__USB_RST_CTRL = 32'hF8000210;
-parameter val_slcr__USB_RST_CTRL = 32'h00000000;
-parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__GEM_RST_CTRL = 32'hF8000214;
-parameter val_slcr__GEM_RST_CTRL = 32'h00000000;
-parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__SDIO_RST_CTRL = 32'hF8000218;
-parameter val_slcr__SDIO_RST_CTRL = 32'h00000000;
-parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__SPI_RST_CTRL = 32'hF800021C;
-parameter val_slcr__SPI_RST_CTRL = 32'h00000000;
-parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__CAN_RST_CTRL = 32'hF8000220;
-parameter val_slcr__CAN_RST_CTRL = 32'h00000000;
-parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__I2C_RST_CTRL = 32'hF8000224;
-parameter val_slcr__I2C_RST_CTRL = 32'h00000000;
-parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__UART_RST_CTRL = 32'hF8000228;
-parameter val_slcr__UART_RST_CTRL = 32'h00000000;
-parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__GPIO_RST_CTRL = 32'hF800022C;
-parameter val_slcr__GPIO_RST_CTRL = 32'h00000000;
-parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__LQSPI_RST_CTRL = 32'hF8000230;
-parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000;
-parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__SMC_RST_CTRL = 32'hF8000234;
-parameter val_slcr__SMC_RST_CTRL = 32'h00000000;
-parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__OCM_RST_CTRL = 32'hF8000238;
-parameter val_slcr__OCM_RST_CTRL = 32'h00000000;
-parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DEVCI_RST_CTRL = 32'hF800023C;
-parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000;
-parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__FPGA_RST_CTRL = 32'hF8000240;
-parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F;
-parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244;
-parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000;
-parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__RS_AWDT_CTRL = 32'hF800024C;
-parameter val_slcr__RS_AWDT_CTRL = 32'h00000000;
-parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__RST_REASON = 32'hF8000250;
-parameter val_slcr__RST_REASON = 32'h00000040;
-parameter mask_slcr__RST_REASON = 32'hFFFFFFFF;
-
-parameter slcr__RST_REASON_CLR = 32'hF8000254;
-parameter val_slcr__RST_REASON_CLR = 32'h00000000;
-parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF;
-
-parameter slcr__REBOOT_STATUS = 32'hF8000258;
-parameter val_slcr__REBOOT_STATUS = 32'h00400000;
-parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF;
-
-parameter slcr__BOOT_MODE = 32'hF800025C;
-parameter val_slcr__BOOT_MODE = 32'h00000000;
-parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0;
-
-parameter slcr__APU_CTRL = 32'hF8000300;
-parameter val_slcr__APU_CTRL = 32'h00000000;
-parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__WDT_CLK_SEL = 32'hF8000304;
-parameter val_slcr__WDT_CLK_SEL = 32'h00000000;
-parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF;
-
-parameter slcr__TZ_OCM_RAM0 = 32'hF8000400;
-parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000;
-parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF;
-
-parameter slcr__TZ_OCM_RAM1 = 32'hF8000404;
-parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000;
-parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF;
-
-parameter slcr__TZ_OCM_ROM = 32'hF8000408;
-parameter val_slcr__TZ_OCM_ROM = 32'h00000000;
-parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF;
-
-parameter slcr__TZ_DDR_RAM = 32'hF8000430;
-parameter val_slcr__TZ_DDR_RAM = 32'h00000000;
-parameter mask_slcr__TZ_DDR_RAM = 32'h00000001;
-
-parameter slcr__TZ_DMA_NS = 32'hF8000440;
-parameter val_slcr__TZ_DMA_NS = 32'h00000000;
-parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF;
-
-parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444;
-parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000;
-parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF;
-
-parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448;
-parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000;
-parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF;
-
-parameter slcr__TZ_GEM = 32'hF8000450;
-parameter val_slcr__TZ_GEM = 32'h00000000;
-parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF;
-
-parameter slcr__TZ_SDIO = 32'hF8000454;
-parameter val_slcr__TZ_SDIO = 32'h00000000;
-parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF;
-
-parameter slcr__TZ_USB = 32'hF8000458;
-parameter val_slcr__TZ_USB = 32'h00000000;
-parameter mask_slcr__TZ_USB = 32'hFFFFFFFF;
-
-parameter slcr__TZ_FPGA_M = 32'hF8000484;
-parameter val_slcr__TZ_FPGA_M = 32'h00000000;
-parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF;
-
-parameter slcr__TZ_FPGA_AFI = 32'hF8000488;
-parameter val_slcr__TZ_FPGA_AFI = 32'h00000000;
-parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF;
-
-parameter slcr__DBG_CTRL = 32'hF8000500;
-parameter val_slcr__DBG_CTRL = 32'h00000000;
-parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__PSS_IDCODE = 32'hF8000530;
-parameter val_slcr__PSS_IDCODE = 32'h03720093;
-parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF;
-
-parameter slcr__DDR_URGENT = 32'hF8000600;
-parameter val_slcr__DDR_URGENT = 32'h00000000;
-parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF;
-
-parameter slcr__DDR_CAL_START = 32'hF800060C;
-parameter val_slcr__DDR_CAL_START = 32'h00000000;
-parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF;
-
-parameter slcr__DDR_REF_START = 32'hF8000614;
-parameter val_slcr__DDR_REF_START = 32'h00000000;
-parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF;
-
-parameter slcr__DDR_CMD_STA = 32'hF8000618;
-parameter val_slcr__DDR_CMD_STA = 32'h00000000;
-parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF;
-
-parameter slcr__DDR_URGENT_SEL = 32'hF800061C;
-parameter val_slcr__DDR_URGENT_SEL = 32'h00000000;
-parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF;
-
-parameter slcr__DDR_DFI_STATUS = 32'hF8000620;
-parameter val_slcr__DDR_DFI_STATUS = 32'h00000000;
-parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_00 = 32'hF8000700;
-parameter val_slcr__MIO_PIN_00 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_01 = 32'hF8000704;
-parameter val_slcr__MIO_PIN_01 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_02 = 32'hF8000708;
-parameter val_slcr__MIO_PIN_02 = 32'h00000601;
-parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_03 = 32'hF800070C;
-parameter val_slcr__MIO_PIN_03 = 32'h00000601;
-parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_04 = 32'hF8000710;
-parameter val_slcr__MIO_PIN_04 = 32'h00000601;
-parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_05 = 32'hF8000714;
-parameter val_slcr__MIO_PIN_05 = 32'h00000601;
-parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_06 = 32'hF8000718;
-parameter val_slcr__MIO_PIN_06 = 32'h00000601;
-parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_07 = 32'hF800071C;
-parameter val_slcr__MIO_PIN_07 = 32'h00000601;
-parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_08 = 32'hF8000720;
-parameter val_slcr__MIO_PIN_08 = 32'h00000601;
-parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_09 = 32'hF8000724;
-parameter val_slcr__MIO_PIN_09 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_10 = 32'hF8000728;
-parameter val_slcr__MIO_PIN_10 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_11 = 32'hF800072C;
-parameter val_slcr__MIO_PIN_11 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_12 = 32'hF8000730;
-parameter val_slcr__MIO_PIN_12 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_13 = 32'hF8000734;
-parameter val_slcr__MIO_PIN_13 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_14 = 32'hF8000738;
-parameter val_slcr__MIO_PIN_14 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_15 = 32'hF800073C;
-parameter val_slcr__MIO_PIN_15 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_16 = 32'hF8000740;
-parameter val_slcr__MIO_PIN_16 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_17 = 32'hF8000744;
-parameter val_slcr__MIO_PIN_17 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_18 = 32'hF8000748;
-parameter val_slcr__MIO_PIN_18 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_19 = 32'hF800074C;
-parameter val_slcr__MIO_PIN_19 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_20 = 32'hF8000750;
-parameter val_slcr__MIO_PIN_20 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_21 = 32'hF8000754;
-parameter val_slcr__MIO_PIN_21 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_22 = 32'hF8000758;
-parameter val_slcr__MIO_PIN_22 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_23 = 32'hF800075C;
-parameter val_slcr__MIO_PIN_23 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_24 = 32'hF8000760;
-parameter val_slcr__MIO_PIN_24 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_25 = 32'hF8000764;
-parameter val_slcr__MIO_PIN_25 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_26 = 32'hF8000768;
-parameter val_slcr__MIO_PIN_26 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_27 = 32'hF800076C;
-parameter val_slcr__MIO_PIN_27 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_28 = 32'hF8000770;
-parameter val_slcr__MIO_PIN_28 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_29 = 32'hF8000774;
-parameter val_slcr__MIO_PIN_29 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_30 = 32'hF8000778;
-parameter val_slcr__MIO_PIN_30 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_31 = 32'hF800077C;
-parameter val_slcr__MIO_PIN_31 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_32 = 32'hF8000780;
-parameter val_slcr__MIO_PIN_32 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_33 = 32'hF8000784;
-parameter val_slcr__MIO_PIN_33 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_34 = 32'hF8000788;
-parameter val_slcr__MIO_PIN_34 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_35 = 32'hF800078C;
-parameter val_slcr__MIO_PIN_35 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_36 = 32'hF8000790;
-parameter val_slcr__MIO_PIN_36 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_37 = 32'hF8000794;
-parameter val_slcr__MIO_PIN_37 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_38 = 32'hF8000798;
-parameter val_slcr__MIO_PIN_38 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_39 = 32'hF800079C;
-parameter val_slcr__MIO_PIN_39 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_40 = 32'hF80007A0;
-parameter val_slcr__MIO_PIN_40 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_41 = 32'hF80007A4;
-parameter val_slcr__MIO_PIN_41 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_42 = 32'hF80007A8;
-parameter val_slcr__MIO_PIN_42 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_43 = 32'hF80007AC;
-parameter val_slcr__MIO_PIN_43 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_44 = 32'hF80007B0;
-parameter val_slcr__MIO_PIN_44 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_45 = 32'hF80007B4;
-parameter val_slcr__MIO_PIN_45 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_46 = 32'hF80007B8;
-parameter val_slcr__MIO_PIN_46 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_47 = 32'hF80007BC;
-parameter val_slcr__MIO_PIN_47 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_48 = 32'hF80007C0;
-parameter val_slcr__MIO_PIN_48 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_49 = 32'hF80007C4;
-parameter val_slcr__MIO_PIN_49 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_50 = 32'hF80007C8;
-parameter val_slcr__MIO_PIN_50 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_51 = 32'hF80007CC;
-parameter val_slcr__MIO_PIN_51 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_52 = 32'hF80007D0;
-parameter val_slcr__MIO_PIN_52 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_PIN_53 = 32'hF80007D4;
-parameter val_slcr__MIO_PIN_53 = 32'h00001601;
-parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800;
-parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000;
-parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF;
-
-parameter slcr__MIO_LOOPBACK = 32'hF8000804;
-parameter val_slcr__MIO_LOOPBACK = 32'h00000000;
-parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF;
-
-parameter slcr__MIO_MST_TRI0 = 32'hF800080C;
-parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF;
-parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF;
-
-parameter slcr__MIO_MST_TRI1 = 32'hF8000810;
-parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF;
-parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF;
-
-parameter slcr__SD0_WP_CD_SEL = 32'hF8000830;
-parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000;
-parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF;
-
-parameter slcr__SD1_WP_CD_SEL = 32'hF8000834;
-parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000;
-parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF;
-
-parameter slcr__LVL_SHFTR_EN = 32'hF8000900;
-parameter val_slcr__LVL_SHFTR_EN = 32'h00000000;
-parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF;
-
-parameter slcr__OCM_CFG = 32'hF8000910;
-parameter val_slcr__OCM_CFG = 32'h00000000;
-parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF;
-
-parameter slcr__CPU0_RAM0 = 32'hF8000A00;
-parameter val_slcr__CPU0_RAM0 = 32'h00020202;
-parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF;
-
-parameter slcr__CPU0_RAM1 = 32'hF8000A04;
-parameter val_slcr__CPU0_RAM1 = 32'h00020202;
-parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF;
-
-parameter slcr__CPU0_RAM2 = 32'hF8000A08;
-parameter val_slcr__CPU0_RAM2 = 32'h02020202;
-parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF;
-
-parameter slcr__CPU1_RAM0 = 32'hF8000A0C;
-parameter val_slcr__CPU1_RAM0 = 32'h00020202;
-parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF;
-
-parameter slcr__CPU1_RAM1 = 32'hF8000A10;
-parameter val_slcr__CPU1_RAM1 = 32'h00020202;
-parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF;
-
-parameter slcr__CPU1_RAM2 = 32'hF8000A14;
-parameter val_slcr__CPU1_RAM2 = 32'h02020202;
-parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF;
-
-parameter slcr__SCU_RAM = 32'hF8000A18;
-parameter val_slcr__SCU_RAM = 32'h00000002;
-parameter mask_slcr__SCU_RAM = 32'h000000FF;
-
-parameter slcr__L2C_RAM = 32'hF8000A1C;
-parameter val_slcr__L2C_RAM = 32'h00020202;
-parameter mask_slcr__L2C_RAM = 32'h00FFFFFF;
-
-parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30;
-parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909;
-parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF;
-
-parameter slcr__IOU_RAM_USB01 = 32'hF8000A34;
-parameter val_slcr__IOU_RAM_USB01 = 32'h09090909;
-parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF;
-
-parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38;
-parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909;
-parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF;
-
-parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C;
-parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909;
-parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF;
-
-parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40;
-parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909;
-parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF;
-
-parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44;
-parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909;
-parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF;
-
-parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48;
-parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909;
-parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF;
-
-parameter slcr__DMAC_RAM = 32'hF8000A50;
-parameter val_slcr__DMAC_RAM = 32'h00000009;
-parameter mask_slcr__DMAC_RAM = 32'h000000FF;
-
-parameter slcr__AFI0_RAM0 = 32'hF8000A60;
-parameter val_slcr__AFI0_RAM0 = 32'h09090909;
-parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF;
-
-parameter slcr__AFI0_RAM1 = 32'hF8000A64;
-parameter val_slcr__AFI0_RAM1 = 32'h09090909;
-parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF;
-
-parameter slcr__AFI0_RAM2 = 32'hF8000A68;
-parameter val_slcr__AFI0_RAM2 = 32'h00000909;
-parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF;
-
-parameter slcr__AFI1_RAM0 = 32'hF8000A6C;
-parameter val_slcr__AFI1_RAM0 = 32'h09090909;
-parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF;
-
-parameter slcr__AFI1_RAM1 = 32'hF8000A70;
-parameter val_slcr__AFI1_RAM1 = 32'h09090909;
-parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF;
-
-parameter slcr__AFI1_RAM2 = 32'hF8000A74;
-parameter val_slcr__AFI1_RAM2 = 32'h00000909;
-parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF;
-
-parameter slcr__AFI2_RAM0 = 32'hF8000A78;
-parameter val_slcr__AFI2_RAM0 = 32'h09090909;
-parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF;
-
-parameter slcr__AFI2_RAM1 = 32'hF8000A7C;
-parameter val_slcr__AFI2_RAM1 = 32'h09090909;
-parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF;
-
-parameter slcr__AFI2_RAM2 = 32'hF8000A80;
-parameter val_slcr__AFI2_RAM2 = 32'h00000909;
-parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF;
-
-parameter slcr__AFI3_RAM0 = 32'hF8000A84;
-parameter val_slcr__AFI3_RAM0 = 32'h09090909;
-parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF;
-
-parameter slcr__AFI3_RAM1 = 32'hF8000A88;
-parameter val_slcr__AFI3_RAM1 = 32'h09090909;
-parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF;
-
-parameter slcr__AFI3_RAM2 = 32'hF8000A8C;
-parameter val_slcr__AFI3_RAM2 = 32'h00000909;
-parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF;
-
-parameter slcr__OCM_RAM = 32'hF8000A90;
-parameter val_slcr__OCM_RAM = 32'h01010101;
-parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF;
-
-parameter slcr__OCM_ROM0 = 32'hF8000A94;
-parameter val_slcr__OCM_ROM0 = 32'h09090909;
-parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF;
-
-parameter slcr__OCM_ROM1 = 32'hF8000A98;
-parameter val_slcr__OCM_ROM1 = 32'h09090909;
-parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF;
-
-parameter slcr__DEVCI_RAM = 32'hF8000AA0;
-parameter val_slcr__DEVCI_RAM = 32'h00000909;
-parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF;
-
-parameter slcr__CSG_RAM = 32'hF8000AB0;
-parameter val_slcr__CSG_RAM = 32'h00000001;
-parameter mask_slcr__CSG_RAM = 32'h000000FF;
-
-parameter slcr__GPIOB_CTRL = 32'hF8000B00;
-parameter val_slcr__GPIOB_CTRL = 32'h00000000;
-parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04;
-parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000;
-parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF;
-
-parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08;
-parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000;
-parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF;
-
-parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C;
-parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000;
-parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF;
-
-parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10;
-parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000;
-parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF;
-
-parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14;
-parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000;
-parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF;
-
-parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18;
-parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000;
-parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40;
-parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800;
-parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44;
-parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800;
-parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DATA0 = 32'hF8000B48;
-parameter val_slcr__DDRIOB_DATA0 = 32'h00000800;
-parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C;
-parameter val_slcr__DDRIOB_DATA1 = 32'h00000800;
-parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50;
-parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800;
-parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54;
-parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800;
-parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_CLOCK = 32'hF8000B58;
-parameter val_slcr__DDRIOB_CLOCK = 32'h00000800;
-parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C;
-parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000;
-parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60;
-parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000;
-parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64;
-parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000;
-parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68;
-parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000;
-parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C;
-parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000;
-parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70;
-parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020;
-parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF;
-
-parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74;
-parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000;
-parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module smcc pl353
-// doc version: 1.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter smcc__memc_status = 32'hE000E000;
-parameter val_smcc__memc_status = 32'h00000000;
-parameter mask_smcc__memc_status = 32'h00001FFF;
-
-parameter smcc__memif_cfg = 32'hE000E004;
-parameter val_smcc__memif_cfg = 32'h00011205;
-parameter mask_smcc__memif_cfg = 32'h0003FFFF;
-
-parameter smcc__memc_cfg_set = 32'hE000E008;
-parameter val_smcc__memc_cfg_set = 32'h00000000;
-parameter mask_smcc__memc_cfg_set = 32'h00000000;
-
-parameter smcc__memc_cfg_clr = 32'hE000E00C;
-parameter val_smcc__memc_cfg_clr = 32'h00000000;
-parameter mask_smcc__memc_cfg_clr = 32'h00000000;
-
-parameter smcc__direct_cmd = 32'hE000E010;
-parameter val_smcc__direct_cmd = 32'h00000000;
-parameter mask_smcc__direct_cmd = 32'h00000000;
-
-parameter smcc__set_cycles = 32'hE000E014;
-parameter val_smcc__set_cycles = 32'h00000000;
-parameter mask_smcc__set_cycles = 32'h00000000;
-
-parameter smcc__set_opmode = 32'hE000E018;
-parameter val_smcc__set_opmode = 32'h00000000;
-parameter mask_smcc__set_opmode = 32'h00000000;
-
-parameter smcc__refresh_period_0 = 32'hE000E020;
-parameter val_smcc__refresh_period_0 = 32'h00000000;
-parameter mask_smcc__refresh_period_0 = 32'h0000000F;
-
-parameter smcc__refresh_period_1 = 32'hE000E024;
-parameter val_smcc__refresh_period_1 = 32'h00000000;
-parameter mask_smcc__refresh_period_1 = 32'h0000000F;
-
-parameter smcc__sram_cycles0_0 = 32'hE000E100;
-parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC;
-parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF;
-
-parameter smcc__opmode0_0 = 32'hE000E104;
-parameter val_smcc__opmode0_0 = 32'hE2FE0800;
-parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF;
-
-parameter smcc__sram_cycles0_1 = 32'hE000E120;
-parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC;
-parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF;
-
-parameter smcc__opmode0_1 = 32'hE000E124;
-parameter val_smcc__opmode0_1 = 32'hE4FE0800;
-parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF;
-
-parameter smcc__nand_cycles1_0 = 32'hE000E180;
-parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC;
-parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF;
-
-parameter smcc__opmode1_0 = 32'hE000E184;
-parameter val_smcc__opmode1_0 = 32'hE1FF0001;
-parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF;
-
-parameter smcc__user_status = 32'hE000E200;
-parameter val_smcc__user_status = 32'h00000000;
-parameter mask_smcc__user_status = 32'h000000FF;
-
-parameter smcc__user_config = 32'hE000E204;
-parameter val_smcc__user_config = 32'h00000000;
-parameter mask_smcc__user_config = 32'h00000000;
-
-parameter smcc__ecc_status_0 = 32'hE000E300;
-parameter val_smcc__ecc_status_0 = 32'h00000000;
-parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF;
-
-parameter smcc__ecc_memcfg_0 = 32'hE000E304;
-parameter val_smcc__ecc_memcfg_0 = 32'h00000000;
-parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF;
-
-parameter smcc__ecc_memcommand1_0 = 32'hE000E308;
-parameter val_smcc__ecc_memcommand1_0 = 32'h00000000;
-parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF;
-
-parameter smcc__ecc_memcommand2_0 = 32'hE000E30C;
-parameter val_smcc__ecc_memcommand2_0 = 32'h00000000;
-parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF;
-
-parameter smcc__ecc_addr0_0 = 32'hE000E310;
-parameter val_smcc__ecc_addr0_0 = 32'h00000000;
-parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_addr1_0 = 32'hE000E314;
-parameter val_smcc__ecc_addr1_0 = 32'h00000000;
-parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF;
-
-parameter smcc__ecc_value0_0 = 32'hE000E318;
-parameter val_smcc__ecc_value0_0 = 32'h00000000;
-parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_value1_0 = 32'hE000E31C;
-parameter val_smcc__ecc_value1_0 = 32'h00000000;
-parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_value2_0 = 32'hE000E320;
-parameter val_smcc__ecc_value2_0 = 32'h00000000;
-parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_value3_0 = 32'hE000E324;
-parameter val_smcc__ecc_value3_0 = 32'h00000000;
-parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_status_1 = 32'hE000E400;
-parameter val_smcc__ecc_status_1 = 32'h00000000;
-parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF;
-
-parameter smcc__ecc_memcfg_1 = 32'hE000E404;
-parameter val_smcc__ecc_memcfg_1 = 32'h00000043;
-parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF;
-
-parameter smcc__ecc_memcommand1_1 = 32'hE000E408;
-parameter val_smcc__ecc_memcommand1_1 = 32'h01300080;
-parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF;
-
-parameter smcc__ecc_memcommand2_1 = 32'hE000E40C;
-parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585;
-parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF;
-
-parameter smcc__ecc_addr0_1 = 32'hE000E410;
-parameter val_smcc__ecc_addr0_1 = 32'h00000000;
-parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_addr1_1 = 32'hE000E414;
-parameter val_smcc__ecc_addr1_1 = 32'h00000000;
-parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF;
-
-parameter smcc__ecc_value0_1 = 32'hE000E418;
-parameter val_smcc__ecc_value0_1 = 32'h00000000;
-parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_value1_1 = 32'hE000E41C;
-parameter val_smcc__ecc_value1_1 = 32'h00000000;
-parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_value2_1 = 32'hE000E420;
-parameter val_smcc__ecc_value2_1 = 32'h00000000;
-parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF;
-
-parameter smcc__ecc_value3_1 = 32'hE000E424;
-parameter val_smcc__ecc_value3_1 = 32'h00000000;
-parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF;
-
-parameter smcc__integration_test = 32'hE000EE00;
-parameter val_smcc__integration_test = 32'h00000000;
-parameter mask_smcc__integration_test = 32'hFFFFFFFF;
-
-parameter smcc__periph_id_0 = 32'hE000EFE0;
-parameter val_smcc__periph_id_0 = 32'h00000053;
-parameter mask_smcc__periph_id_0 = 32'h000000FF;
-
-parameter smcc__periph_id_1 = 32'hE000EFE4;
-parameter val_smcc__periph_id_1 = 32'h00000013;
-parameter mask_smcc__periph_id_1 = 32'h000000FF;
-
-parameter smcc__periph_id_2 = 32'hE000EFE8;
-parameter val_smcc__periph_id_2 = 32'h00000054;
-parameter mask_smcc__periph_id_2 = 32'h000000FF;
-
-parameter smcc__periph_id_3 = 32'hE000EFEC;
-parameter val_smcc__periph_id_3 = 32'h00000000;
-parameter mask_smcc__periph_id_3 = 32'h00000001;
-
-parameter smcc__pcell_id_0 = 32'hE000EFF0;
-parameter val_smcc__pcell_id_0 = 32'h0000000D;
-parameter mask_smcc__pcell_id_0 = 32'h000000FF;
-
-parameter smcc__pcell_id_1 = 32'hE000EFF4;
-parameter val_smcc__pcell_id_1 = 32'h000000F0;
-parameter mask_smcc__pcell_id_1 = 32'h000000FF;
-
-parameter smcc__pcell_id_2 = 32'hE000EFF8;
-parameter val_smcc__pcell_id_2 = 32'h00000005;
-parameter mask_smcc__pcell_id_2 = 32'h000000FF;
-
-parameter smcc__pcell_id_3 = 32'hE000EFFC;
-parameter val_smcc__pcell_id_3 = 32'h000000B1;
-parameter mask_smcc__pcell_id_3 = 32'h000000FF;
-
-
-// ************************************************************
-// Module spi0 SPI
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter spi0__Config_reg0 = 32'hE0006000;
-parameter val_spi0__Config_reg0 = 32'h00020000;
-parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Intr_status_reg0 = 32'hE0006004;
-parameter val_spi0__Intr_status_reg0 = 32'h00000004;
-parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Intrpt_en_reg0 = 32'hE0006008;
-parameter val_spi0__Intrpt_en_reg0 = 32'h00000000;
-parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Intrpt_dis_reg0 = 32'hE000600C;
-parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000;
-parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Intrpt_mask_reg0 = 32'hE0006010;
-parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000;
-parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__En_reg0 = 32'hE0006014;
-parameter val_spi0__En_reg0 = 32'h00000000;
-parameter mask_spi0__En_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Delay_reg0 = 32'hE0006018;
-parameter val_spi0__Delay_reg0 = 32'h00000000;
-parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Tx_data_reg0 = 32'hE000601C;
-parameter val_spi0__Tx_data_reg0 = 32'h00000000;
-parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Rx_data_reg0 = 32'hE0006020;
-parameter val_spi0__Rx_data_reg0 = 32'h00000000;
-parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024;
-parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF;
-parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__TX_thres_reg0 = 32'hE0006028;
-parameter val_spi0__TX_thres_reg0 = 32'h00000001;
-parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__RX_thres_reg0 = 32'hE000602C;
-parameter val_spi0__RX_thres_reg0 = 32'h00000001;
-parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF;
-
-parameter spi0__Mod_id_reg0 = 32'hE00060FC;
-parameter val_spi0__Mod_id_reg0 = 32'h00090106;
-parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module spi1 SPI
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter spi1__Config_reg0 = 32'hE0007000;
-parameter val_spi1__Config_reg0 = 32'h00020000;
-parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Intr_status_reg0 = 32'hE0007004;
-parameter val_spi1__Intr_status_reg0 = 32'h00000004;
-parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Intrpt_en_reg0 = 32'hE0007008;
-parameter val_spi1__Intrpt_en_reg0 = 32'h00000000;
-parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Intrpt_dis_reg0 = 32'hE000700C;
-parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000;
-parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Intrpt_mask_reg0 = 32'hE0007010;
-parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000;
-parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__En_reg0 = 32'hE0007014;
-parameter val_spi1__En_reg0 = 32'h00000000;
-parameter mask_spi1__En_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Delay_reg0 = 32'hE0007018;
-parameter val_spi1__Delay_reg0 = 32'h00000000;
-parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Tx_data_reg0 = 32'hE000701C;
-parameter val_spi1__Tx_data_reg0 = 32'h00000000;
-parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Rx_data_reg0 = 32'hE0007020;
-parameter val_spi1__Rx_data_reg0 = 32'h00000000;
-parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024;
-parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF;
-parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__TX_thres_reg0 = 32'hE0007028;
-parameter val_spi1__TX_thres_reg0 = 32'h00000001;
-parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__RX_thres_reg0 = 32'hE000702C;
-parameter val_spi1__RX_thres_reg0 = 32'h00000001;
-parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF;
-
-parameter spi1__Mod_id_reg0 = 32'hE00070FC;
-parameter val_spi1__Mod_id_reg0 = 32'h00090106;
-parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module swdt swdt
-// doc version: 2.1
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter swdt__MODE = 32'hF8005000;
-parameter val_swdt__MODE = 32'h000001C2;
-parameter mask_swdt__MODE = 32'h00FFFFFF;
-
-parameter swdt__CONTROL = 32'hF8005004;
-parameter val_swdt__CONTROL = 32'h03FFC3FC;
-parameter mask_swdt__CONTROL = 32'h03FFFFFF;
-
-parameter swdt__RESTART = 32'hF8005008;
-parameter val_swdt__RESTART = 32'h00000000;
-parameter mask_swdt__RESTART = 32'h0000FFFF;
-
-parameter swdt__STATUS = 32'hF800500C;
-parameter val_swdt__STATUS = 32'h00000000;
-parameter mask_swdt__STATUS = 32'h00000001;
-
-
-// ************************************************************
-// Module ttc0 ttc
-// doc version: 2.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter ttc0__Clock_Control_1 = 32'hF8001000;
-parameter val_ttc0__Clock_Control_1 = 32'h00000000;
-parameter mask_ttc0__Clock_Control_1 = 32'h0000007F;
-
-parameter ttc0__Clock_Control_2 = 32'hF8001004;
-parameter val_ttc0__Clock_Control_2 = 32'h00000000;
-parameter mask_ttc0__Clock_Control_2 = 32'h0000007F;
-
-parameter ttc0__Clock_Control_3 = 32'hF8001008;
-parameter val_ttc0__Clock_Control_3 = 32'h00000000;
-parameter mask_ttc0__Clock_Control_3 = 32'h0000007F;
-
-parameter ttc0__Counter_Control_1 = 32'hF800100C;
-parameter val_ttc0__Counter_Control_1 = 32'h00000021;
-parameter mask_ttc0__Counter_Control_1 = 32'h0000007F;
-
-parameter ttc0__Counter_Control_2 = 32'hF8001010;
-parameter val_ttc0__Counter_Control_2 = 32'h00000021;
-parameter mask_ttc0__Counter_Control_2 = 32'h0000007F;
-
-parameter ttc0__Counter_Control_3 = 32'hF8001014;
-parameter val_ttc0__Counter_Control_3 = 32'h00000021;
-parameter mask_ttc0__Counter_Control_3 = 32'h0000007F;
-
-parameter ttc0__Counter_Value_1 = 32'hF8001018;
-parameter val_ttc0__Counter_Value_1 = 32'h00000000;
-parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF;
-
-parameter ttc0__Counter_Value_2 = 32'hF800101C;
-parameter val_ttc0__Counter_Value_2 = 32'h00000000;
-parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF;
-
-parameter ttc0__Counter_Value_3 = 32'hF8001020;
-parameter val_ttc0__Counter_Value_3 = 32'h00000000;
-parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF;
-
-parameter ttc0__Interval_Counter_1 = 32'hF8001024;
-parameter val_ttc0__Interval_Counter_1 = 32'h00000000;
-parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF;
-
-parameter ttc0__Interval_Counter_2 = 32'hF8001028;
-parameter val_ttc0__Interval_Counter_2 = 32'h00000000;
-parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF;
-
-parameter ttc0__Interval_Counter_3 = 32'hF800102C;
-parameter val_ttc0__Interval_Counter_3 = 32'h00000000;
-parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF;
-
-parameter ttc0__Match_1_Counter_1 = 32'hF8001030;
-parameter val_ttc0__Match_1_Counter_1 = 32'h00000000;
-parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF;
-
-parameter ttc0__Match_1_Counter_2 = 32'hF8001034;
-parameter val_ttc0__Match_1_Counter_2 = 32'h00000000;
-parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF;
-
-parameter ttc0__Match_1_Counter_3 = 32'hF8001038;
-parameter val_ttc0__Match_1_Counter_3 = 32'h00000000;
-parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF;
-
-parameter ttc0__Match_2_Counter_1 = 32'hF800103C;
-parameter val_ttc0__Match_2_Counter_1 = 32'h00000000;
-parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF;
-
-parameter ttc0__Match_2_Counter_2 = 32'hF8001040;
-parameter val_ttc0__Match_2_Counter_2 = 32'h00000000;
-parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF;
-
-parameter ttc0__Match_2_Counter_3 = 32'hF8001044;
-parameter val_ttc0__Match_2_Counter_3 = 32'h00000000;
-parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF;
-
-parameter ttc0__Match_3_Counter_1 = 32'hF8001048;
-parameter val_ttc0__Match_3_Counter_1 = 32'h00000000;
-parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF;
-
-parameter ttc0__Match_3_Counter_2 = 32'hF800104C;
-parameter val_ttc0__Match_3_Counter_2 = 32'h00000000;
-parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF;
-
-parameter ttc0__Match_3_Counter_3 = 32'hF8001050;
-parameter val_ttc0__Match_3_Counter_3 = 32'h00000000;
-parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF;
-
-parameter ttc0__Interrupt_Register_1 = 32'hF8001054;
-parameter val_ttc0__Interrupt_Register_1 = 32'h00000000;
-parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F;
-
-parameter ttc0__Interrupt_Register_2 = 32'hF8001058;
-parameter val_ttc0__Interrupt_Register_2 = 32'h00000000;
-parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F;
-
-parameter ttc0__Interrupt_Register_3 = 32'hF800105C;
-parameter val_ttc0__Interrupt_Register_3 = 32'h00000000;
-parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F;
-
-parameter ttc0__Interrupt_Enable_1 = 32'hF8001060;
-parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000;
-parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F;
-
-parameter ttc0__Interrupt_Enable_2 = 32'hF8001064;
-parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000;
-parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F;
-
-parameter ttc0__Interrupt_Enable_3 = 32'hF8001068;
-parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000;
-parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F;
-
-parameter ttc0__Event_Control_Timer_1 = 32'hF800106C;
-parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000;
-parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007;
-
-parameter ttc0__Event_Control_Timer_2 = 32'hF8001070;
-parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000;
-parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007;
-
-parameter ttc0__Event_Control_Timer_3 = 32'hF8001074;
-parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000;
-parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007;
-
-parameter ttc0__Event_Register_1 = 32'hF8001078;
-parameter val_ttc0__Event_Register_1 = 32'h00000000;
-parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF;
-
-parameter ttc0__Event_Register_2 = 32'hF800107C;
-parameter val_ttc0__Event_Register_2 = 32'h00000000;
-parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF;
-
-parameter ttc0__Event_Register_3 = 32'hF8001080;
-parameter val_ttc0__Event_Register_3 = 32'h00000000;
-parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF;
-
-
-// ************************************************************
-// Module ttc1 ttc
-// doc version: 2.0
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter ttc1__Clock_Control_1 = 32'hF8002000;
-parameter val_ttc1__Clock_Control_1 = 32'h00000000;
-parameter mask_ttc1__Clock_Control_1 = 32'h0000007F;
-
-parameter ttc1__Clock_Control_2 = 32'hF8002004;
-parameter val_ttc1__Clock_Control_2 = 32'h00000000;
-parameter mask_ttc1__Clock_Control_2 = 32'h0000007F;
-
-parameter ttc1__Clock_Control_3 = 32'hF8002008;
-parameter val_ttc1__Clock_Control_3 = 32'h00000000;
-parameter mask_ttc1__Clock_Control_3 = 32'h0000007F;
-
-parameter ttc1__Counter_Control_1 = 32'hF800200C;
-parameter val_ttc1__Counter_Control_1 = 32'h00000021;
-parameter mask_ttc1__Counter_Control_1 = 32'h0000007F;
-
-parameter ttc1__Counter_Control_2 = 32'hF8002010;
-parameter val_ttc1__Counter_Control_2 = 32'h00000021;
-parameter mask_ttc1__Counter_Control_2 = 32'h0000007F;
-
-parameter ttc1__Counter_Control_3 = 32'hF8002014;
-parameter val_ttc1__Counter_Control_3 = 32'h00000021;
-parameter mask_ttc1__Counter_Control_3 = 32'h0000007F;
-
-parameter ttc1__Counter_Value_1 = 32'hF8002018;
-parameter val_ttc1__Counter_Value_1 = 32'h00000000;
-parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF;
-
-parameter ttc1__Counter_Value_2 = 32'hF800201C;
-parameter val_ttc1__Counter_Value_2 = 32'h00000000;
-parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF;
-
-parameter ttc1__Counter_Value_3 = 32'hF8002020;
-parameter val_ttc1__Counter_Value_3 = 32'h00000000;
-parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF;
-
-parameter ttc1__Interval_Counter_1 = 32'hF8002024;
-parameter val_ttc1__Interval_Counter_1 = 32'h00000000;
-parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF;
-
-parameter ttc1__Interval_Counter_2 = 32'hF8002028;
-parameter val_ttc1__Interval_Counter_2 = 32'h00000000;
-parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF;
-
-parameter ttc1__Interval_Counter_3 = 32'hF800202C;
-parameter val_ttc1__Interval_Counter_3 = 32'h00000000;
-parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF;
-
-parameter ttc1__Match_1_Counter_1 = 32'hF8002030;
-parameter val_ttc1__Match_1_Counter_1 = 32'h00000000;
-parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF;
-
-parameter ttc1__Match_1_Counter_2 = 32'hF8002034;
-parameter val_ttc1__Match_1_Counter_2 = 32'h00000000;
-parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF;
-
-parameter ttc1__Match_1_Counter_3 = 32'hF8002038;
-parameter val_ttc1__Match_1_Counter_3 = 32'h00000000;
-parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF;
-
-parameter ttc1__Match_2_Counter_1 = 32'hF800203C;
-parameter val_ttc1__Match_2_Counter_1 = 32'h00000000;
-parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF;
-
-parameter ttc1__Match_2_Counter_2 = 32'hF8002040;
-parameter val_ttc1__Match_2_Counter_2 = 32'h00000000;
-parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF;
-
-parameter ttc1__Match_2_Counter_3 = 32'hF8002044;
-parameter val_ttc1__Match_2_Counter_3 = 32'h00000000;
-parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF;
-
-parameter ttc1__Match_3_Counter_1 = 32'hF8002048;
-parameter val_ttc1__Match_3_Counter_1 = 32'h00000000;
-parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF;
-
-parameter ttc1__Match_3_Counter_2 = 32'hF800204C;
-parameter val_ttc1__Match_3_Counter_2 = 32'h00000000;
-parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF;
-
-parameter ttc1__Match_3_Counter_3 = 32'hF8002050;
-parameter val_ttc1__Match_3_Counter_3 = 32'h00000000;
-parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF;
-
-parameter ttc1__Interrupt_Register_1 = 32'hF8002054;
-parameter val_ttc1__Interrupt_Register_1 = 32'h00000000;
-parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F;
-
-parameter ttc1__Interrupt_Register_2 = 32'hF8002058;
-parameter val_ttc1__Interrupt_Register_2 = 32'h00000000;
-parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F;
-
-parameter ttc1__Interrupt_Register_3 = 32'hF800205C;
-parameter val_ttc1__Interrupt_Register_3 = 32'h00000000;
-parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F;
-
-parameter ttc1__Interrupt_Enable_1 = 32'hF8002060;
-parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000;
-parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F;
-
-parameter ttc1__Interrupt_Enable_2 = 32'hF8002064;
-parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000;
-parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F;
-
-parameter ttc1__Interrupt_Enable_3 = 32'hF8002068;
-parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000;
-parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F;
-
-parameter ttc1__Event_Control_Timer_1 = 32'hF800206C;
-parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000;
-parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007;
-
-parameter ttc1__Event_Control_Timer_2 = 32'hF8002070;
-parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000;
-parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007;
-
-parameter ttc1__Event_Control_Timer_3 = 32'hF8002074;
-parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000;
-parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007;
-
-parameter ttc1__Event_Register_1 = 32'hF8002078;
-parameter val_ttc1__Event_Register_1 = 32'h00000000;
-parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF;
-
-parameter ttc1__Event_Register_2 = 32'hF800207C;
-parameter val_ttc1__Event_Register_2 = 32'h00000000;
-parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF;
-
-parameter ttc1__Event_Register_3 = 32'hF8002080;
-parameter val_ttc1__Event_Register_3 = 32'h00000000;
-parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF;
-
-
-// ************************************************************
-// Module uart0 UART
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter uart0__Control_reg0 = 32'hE0000000;
-parameter val_uart0__Control_reg0 = 32'h00000128;
-parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__mode_reg0 = 32'hE0000004;
-parameter val_uart0__mode_reg0 = 32'h00000000;
-parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Intrpt_en_reg0 = 32'hE0000008;
-parameter val_uart0__Intrpt_en_reg0 = 32'h00000000;
-parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Intrpt_dis_reg0 = 32'hE000000C;
-parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000;
-parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Intrpt_mask_reg0 = 32'hE0000010;
-parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000;
-parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014;
-parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200;
-parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018;
-parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B;
-parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C;
-parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000;
-parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020;
-parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020;
-parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF;
-
-parameter uart0__Modem_ctrl_reg0 = 32'hE0000024;
-parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000;
-parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Modem_sts_reg0 = 32'hE0000028;
-parameter val_uart0__Modem_sts_reg0 = 32'h00000000;
-parameter mask_uart0__Modem_sts_reg0 = 32'h00000000;
-
-parameter uart0__Channel_sts_reg0 = 32'hE000002C;
-parameter val_uart0__Channel_sts_reg0 = 32'h00000000;
-parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__TX_RX_FIFO0 = 32'hE0000030;
-parameter val_uart0__TX_RX_FIFO0 = 32'h00000000;
-parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF;
-
-parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034;
-parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F;
-parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__Flow_delay_reg0 = 32'hE0000038;
-parameter val_uart0__Flow_delay_reg0 = 32'h00000000;
-parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF;
-
-parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C;
-parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000;
-parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF;
-
-parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040;
-parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000;
-parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF;
-
-parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044;
-parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020;
-parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module uart1 UART
-// doc version: 1.2
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter uart1__Control_reg0 = 32'hE0001000;
-parameter val_uart1__Control_reg0 = 32'h00000128;
-parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__mode_reg0 = 32'hE0001004;
-parameter val_uart1__mode_reg0 = 32'h00000000;
-parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Intrpt_en_reg0 = 32'hE0001008;
-parameter val_uart1__Intrpt_en_reg0 = 32'h00000000;
-parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Intrpt_dis_reg0 = 32'hE000100C;
-parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000;
-parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Intrpt_mask_reg0 = 32'hE0001010;
-parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000;
-parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014;
-parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200;
-parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018;
-parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B;
-parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C;
-parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000;
-parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020;
-parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020;
-parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF;
-
-parameter uart1__Modem_ctrl_reg0 = 32'hE0001024;
-parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000;
-parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Modem_sts_reg0 = 32'hE0001028;
-parameter val_uart1__Modem_sts_reg0 = 32'h00000000;
-parameter mask_uart1__Modem_sts_reg0 = 32'h00000000;
-
-parameter uart1__Channel_sts_reg0 = 32'hE000102C;
-parameter val_uart1__Channel_sts_reg0 = 32'h00000000;
-parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__TX_RX_FIFO0 = 32'hE0001030;
-parameter val_uart1__TX_RX_FIFO0 = 32'h00000000;
-parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF;
-
-parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034;
-parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F;
-parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__Flow_delay_reg0 = 32'hE0001038;
-parameter val_uart1__Flow_delay_reg0 = 32'h00000000;
-parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF;
-
-parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C;
-parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000;
-parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF;
-
-parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040;
-parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000;
-parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF;
-
-parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044;
-parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020;
-parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF;
-
-
-// ************************************************************
-// Module usb0 usb
-// doc version: 1.3
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter usb0__ID = 32'hE0002000;
-parameter val_usb0__ID = 32'hE441FA05;
-parameter mask_usb0__ID = 32'hFFFFFFFF;
-
-parameter usb0__HWGENERAL = 32'hE0002004;
-parameter val_usb0__HWGENERAL = 32'h00000083;
-parameter mask_usb0__HWGENERAL = 32'h00000FFF;
-
-parameter usb0__HWHOST = 32'hE0002008;
-parameter val_usb0__HWHOST = 32'h10020001;
-parameter mask_usb0__HWHOST = 32'hFFFFFFFF;
-
-parameter usb0__HWDEVICE = 32'hE000200C;
-parameter val_usb0__HWDEVICE = 32'h00000019;
-parameter mask_usb0__HWDEVICE = 32'h0000003F;
-
-parameter usb0__HWTXBUF = 32'hE0002010;
-parameter val_usb0__HWTXBUF = 32'h80060A10;
-parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF;
-
-parameter usb0__HWRXBUF = 32'hE0002014;
-parameter val_usb0__HWRXBUF = 32'h00000A10;
-parameter mask_usb0__HWRXBUF = 32'hFF00FFFF;
-
-parameter usb0__GPTIMER0LD = 32'hE0002080;
-parameter val_usb0__GPTIMER0LD = 32'h00000000;
-parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF;
-
-parameter usb0__GPTIMER0CTRL = 32'hE0002084;
-parameter val_usb0__GPTIMER0CTRL = 32'h00000000;
-parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF;
-
-parameter usb0__GPTIMER1LD = 32'hE0002088;
-parameter val_usb0__GPTIMER1LD = 32'h00000000;
-parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF;
-
-parameter usb0__GPTIMER1CTRL = 32'hE000208C;
-parameter val_usb0__GPTIMER1CTRL = 32'h00000000;
-parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF;
-
-parameter usb0__SBUSCFG = 32'hE0002090;
-parameter val_usb0__SBUSCFG = 32'h00000003;
-parameter mask_usb0__SBUSCFG = 32'h00000007;
-
-parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100;
-parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040;
-parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF;
-
-parameter usb0__HCSPARAMS = 32'hE0002104;
-parameter val_usb0__HCSPARAMS = 32'h00010011;
-parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF;
-
-parameter usb0__HCCPARAMS = 32'hE0002108;
-parameter val_usb0__HCCPARAMS = 32'h00000006;
-parameter mask_usb0__HCCPARAMS = 32'h0000FFFF;
-
-parameter usb0__DCIVERSION = 32'hE0002120;
-parameter val_usb0__DCIVERSION = 32'h00000001;
-parameter mask_usb0__DCIVERSION = 32'h0000FFFF;
-
-parameter usb0__DCCPARAMS = 32'hE0002124;
-parameter val_usb0__DCCPARAMS = 32'h0000018C;
-parameter mask_usb0__DCCPARAMS = 32'h000001FF;
-
-parameter usb0__USBCMD = 32'hE0002140;
-parameter val_usb0__USBCMD = 32'h00000B00;
-parameter mask_usb0__USBCMD = 32'h00FFFFFF;
-
-parameter usb0__USBSTS = 32'hE0002144;
-parameter val_usb0__USBSTS = 32'h00000000;
-parameter mask_usb0__USBSTS = 32'h03FFFFFF;
-
-parameter usb0__USBINTR = 32'hE0002148;
-parameter val_usb0__USBINTR = 32'h00000000;
-parameter mask_usb0__USBINTR = 32'h03FF0FFF;
-
-parameter usb0__FRINDEX = 32'hE000214C;
-parameter val_usb0__FRINDEX = 32'h00000000;
-parameter mask_usb0__FRINDEX = 32'h00003FFF;
-
-parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154;
-parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000;
-parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF;
-
-parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158;
-parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000;
-parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF;
-
-parameter usb0__TTCTRL = 32'hE000215C;
-parameter val_usb0__TTCTRL = 32'h00000000;
-parameter mask_usb0__TTCTRL = 32'hFFFFFFFF;
-
-parameter usb0__BURSTSIZE = 32'hE0002160;
-parameter val_usb0__BURSTSIZE = 32'h00001010;
-parameter mask_usb0__BURSTSIZE = 32'h0001FFFF;
-
-parameter usb0__TXFILLTUNING = 32'hE0002164;
-parameter val_usb0__TXFILLTUNING = 32'h00020000;
-parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF;
-
-parameter usb0__TXTTFILLTUNING = 32'hE0002168;
-parameter val_usb0__TXTTFILLTUNING = 32'h00000000;
-parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF;
-
-parameter usb0__IC_USB = 32'hE000216C;
-parameter val_usb0__IC_USB = 32'h00000000;
-parameter mask_usb0__IC_USB = 32'hFFFFFFFF;
-
-parameter usb0__ULPI_VIEWPORT = 32'hE0002170;
-parameter val_usb0__ULPI_VIEWPORT = 32'h00000000;
-parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF;
-
-parameter usb0__ENDPTNAK = 32'hE0002178;
-parameter val_usb0__ENDPTNAK = 32'h00000000;
-parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF;
-
-parameter usb0__ENDPTNAKEN = 32'hE000217C;
-parameter val_usb0__ENDPTNAKEN = 32'h00000000;
-parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF;
-
-parameter usb0__CONFIGFLAG = 32'hE0002180;
-parameter val_usb0__CONFIGFLAG = 32'h00000001;
-parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF;
-
-parameter usb0__PORTSC1 = 32'hE0002184;
-parameter val_usb0__PORTSC1 = 32'h00000000;
-parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF;
-
-parameter usb0__OTGSC = 32'hE00021A4;
-parameter val_usb0__OTGSC = 32'h00000020;
-parameter mask_usb0__OTGSC = 32'hFFFFFFFF;
-
-parameter usb0__USBMODE = 32'hE00021A8;
-parameter val_usb0__USBMODE = 32'h00000000;
-parameter mask_usb0__USBMODE = 32'h0000FFFF;
-
-parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC;
-parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000;
-parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF;
-
-parameter usb0__ENDPTPRIME = 32'hE00021B0;
-parameter val_usb0__ENDPTPRIME = 32'h00000000;
-parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF;
-
-parameter usb0__ENDPTFLUSH = 32'hE00021B4;
-parameter val_usb0__ENDPTFLUSH = 32'h00000000;
-parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF;
-
-parameter usb0__ENDPTSTAT = 32'hE00021B8;
-parameter val_usb0__ENDPTSTAT = 32'h00000000;
-parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF;
-
-parameter usb0__ENDPTCOMPLETE = 32'hE00021BC;
-parameter val_usb0__ENDPTCOMPLETE = 32'h00000000;
-parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF;
-
-parameter usb0__ENDPTCTRL0 = 32'hE00021C0;
-parameter val_usb0__ENDPTCTRL0 = 32'h00800080;
-parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL1 = 32'hE00021C4;
-parameter val_usb0__ENDPTCTRL1 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL2 = 32'hE00021C8;
-parameter val_usb0__ENDPTCTRL2 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL3 = 32'hE00021CC;
-parameter val_usb0__ENDPTCTRL3 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL4 = 32'hE00021D0;
-parameter val_usb0__ENDPTCTRL4 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL5 = 32'hE00021D4;
-parameter val_usb0__ENDPTCTRL5 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL6 = 32'hE00021D8;
-parameter val_usb0__ENDPTCTRL6 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL7 = 32'hE00021DC;
-parameter val_usb0__ENDPTCTRL7 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL8 = 32'hE00021E0;
-parameter val_usb0__ENDPTCTRL8 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL9 = 32'hE00021E4;
-parameter val_usb0__ENDPTCTRL9 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL10 = 32'hE00021E8;
-parameter val_usb0__ENDPTCTRL10 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL11 = 32'hE00021EC;
-parameter val_usb0__ENDPTCTRL11 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF;
-
-parameter usb0__ENDPTCTRL12 = 32'hE00021F0;
-parameter val_usb0__ENDPTCTRL12 = 32'h00000000;
-parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF;
-
-
-// ************************************************************
-// Module usb1 usb
-// doc version: 1.3
-// ************************************************************
-
-// ADDRESS DEVFALUE MASK NAME
-parameter usb1__ID = 32'hE0003000;
-parameter val_usb1__ID = 32'hE441FA05;
-parameter mask_usb1__ID = 32'hFFFFFFFF;
-
-parameter usb1__HWGENERAL = 32'hE0003004;
-parameter val_usb1__HWGENERAL = 32'h00000083;
-parameter mask_usb1__HWGENERAL = 32'h00000FFF;
-
-parameter usb1__HWHOST = 32'hE0003008;
-parameter val_usb1__HWHOST = 32'h10020001;
-parameter mask_usb1__HWHOST = 32'hFFFFFFFF;
-
-parameter usb1__HWDEVICE = 32'hE000300C;
-parameter val_usb1__HWDEVICE = 32'h00000019;
-parameter mask_usb1__HWDEVICE = 32'h0000003F;
-
-parameter usb1__HWTXBUF = 32'hE0003010;
-parameter val_usb1__HWTXBUF = 32'h80060A10;
-parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF;
-
-parameter usb1__HWRXBUF = 32'hE0003014;
-parameter val_usb1__HWRXBUF = 32'h00000A10;
-parameter mask_usb1__HWRXBUF = 32'hFF00FFFF;
-
-parameter usb1__GPTIMER0LD = 32'hE0003080;
-parameter val_usb1__GPTIMER0LD = 32'h00000000;
-parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF;
-
-parameter usb1__GPTIMER0CTRL = 32'hE0003084;
-parameter val_usb1__GPTIMER0CTRL = 32'h00000000;
-parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF;
-
-parameter usb1__GPTIMER1LD = 32'hE0003088;
-parameter val_usb1__GPTIMER1LD = 32'h00000000;
-parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF;
-
-parameter usb1__GPTIMER1CTRL = 32'hE000308C;
-parameter val_usb1__GPTIMER1CTRL = 32'h00000000;
-parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF;
-
-parameter usb1__SBUSCFG = 32'hE0003090;
-parameter val_usb1__SBUSCFG = 32'h00000003;
-parameter mask_usb1__SBUSCFG = 32'h00000007;
-
-parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100;
-parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040;
-parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF;
-
-parameter usb1__HCSPARAMS = 32'hE0003104;
-parameter val_usb1__HCSPARAMS = 32'h00010011;
-parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF;
-
-parameter usb1__HCCPARAMS = 32'hE0003108;
-parameter val_usb1__HCCPARAMS = 32'h00000006;
-parameter mask_usb1__HCCPARAMS = 32'h0000FFFF;
-
-parameter usb1__DCIVERSION = 32'hE0003120;
-parameter val_usb1__DCIVERSION = 32'h00000001;
-parameter mask_usb1__DCIVERSION = 32'h0000FFFF;
-
-parameter usb1__DCCPARAMS = 32'hE0003124;
-parameter val_usb1__DCCPARAMS = 32'h0000018C;
-parameter mask_usb1__DCCPARAMS = 32'h000001FF;
-
-parameter usb1__USBCMD = 32'hE0003140;
-parameter val_usb1__USBCMD = 32'h00000B00;
-parameter mask_usb1__USBCMD = 32'h00FFFFFF;
-
-parameter usb1__USBSTS = 32'hE0003144;
-parameter val_usb1__USBSTS = 32'h00000000;
-parameter mask_usb1__USBSTS = 32'h03FFFFFF;
-
-parameter usb1__USBINTR = 32'hE0003148;
-parameter val_usb1__USBINTR = 32'h00000000;
-parameter mask_usb1__USBINTR = 32'h03FF0FFF;
-
-parameter usb1__FRINDEX = 32'hE000314C;
-parameter val_usb1__FRINDEX = 32'h00000000;
-parameter mask_usb1__FRINDEX = 32'h00003FFF;
-
-parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154;
-parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000;
-parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF;
-
-parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158;
-parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000;
-parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF;
-
-parameter usb1__TTCTRL = 32'hE000315C;
-parameter val_usb1__TTCTRL = 32'h00000000;
-parameter mask_usb1__TTCTRL = 32'hFFFFFFFF;
-
-parameter usb1__BURSTSIZE = 32'hE0003160;
-parameter val_usb1__BURSTSIZE = 32'h00001010;
-parameter mask_usb1__BURSTSIZE = 32'h0001FFFF;
-
-parameter usb1__TXFILLTUNING = 32'hE0003164;
-parameter val_usb1__TXFILLTUNING = 32'h00020000;
-parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF;
-
-parameter usb1__TXTTFILLTUNING = 32'hE0003168;
-parameter val_usb1__TXTTFILLTUNING = 32'h00000000;
-parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF;
-
-parameter usb1__IC_USB = 32'hE000316C;
-parameter val_usb1__IC_USB = 32'h00000000;
-parameter mask_usb1__IC_USB = 32'hFFFFFFFF;
-
-parameter usb1__ULPI_VIEWPORT = 32'hE0003170;
-parameter val_usb1__ULPI_VIEWPORT = 32'h00000000;
-parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF;
-
-parameter usb1__ENDPTNAK = 32'hE0003178;
-parameter val_usb1__ENDPTNAK = 32'h00000000;
-parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF;
-
-parameter usb1__ENDPTNAKEN = 32'hE000317C;
-parameter val_usb1__ENDPTNAKEN = 32'h00000000;
-parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF;
-
-parameter usb1__CONFIGFLAG = 32'hE0003180;
-parameter val_usb1__CONFIGFLAG = 32'h00000001;
-parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF;
-
-parameter usb1__PORTSC1 = 32'hE0003184;
-parameter val_usb1__PORTSC1 = 32'h00000000;
-parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF;
-
-parameter usb1__OTGSC = 32'hE00031A4;
-parameter val_usb1__OTGSC = 32'h00000020;
-parameter mask_usb1__OTGSC = 32'hFFFFFFFF;
-
-parameter usb1__USBMODE = 32'hE00031A8;
-parameter val_usb1__USBMODE = 32'h00000000;
-parameter mask_usb1__USBMODE = 32'h0000FFFF;
-
-parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC;
-parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000;
-parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF;
-
-parameter usb1__ENDPTPRIME = 32'hE00031B0;
-parameter val_usb1__ENDPTPRIME = 32'h00000000;
-parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF;
-
-parameter usb1__ENDPTFLUSH = 32'hE00031B4;
-parameter val_usb1__ENDPTFLUSH = 32'h00000000;
-parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF;
-
-parameter usb1__ENDPTSTAT = 32'hE00031B8;
-parameter val_usb1__ENDPTSTAT = 32'h00000000;
-parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF;
-
-parameter usb1__ENDPTCOMPLETE = 32'hE00031BC;
-parameter val_usb1__ENDPTCOMPLETE = 32'h00000000;
-parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF;
-
-parameter usb1__ENDPTCTRL0 = 32'hE00031C0;
-parameter val_usb1__ENDPTCTRL0 = 32'h00800080;
-parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL1 = 32'hE00031C4;
-parameter val_usb1__ENDPTCTRL1 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL2 = 32'hE00031C8;
-parameter val_usb1__ENDPTCTRL2 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL3 = 32'hE00031CC;
-parameter val_usb1__ENDPTCTRL3 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL4 = 32'hE00031D0;
-parameter val_usb1__ENDPTCTRL4 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL5 = 32'hE00031D4;
-parameter val_usb1__ENDPTCTRL5 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL6 = 32'hE00031D8;
-parameter val_usb1__ENDPTCTRL6 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL7 = 32'hE00031DC;
-parameter val_usb1__ENDPTCTRL7 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL8 = 32'hE00031E0;
-parameter val_usb1__ENDPTCTRL8 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL9 = 32'hE00031E4;
-parameter val_usb1__ENDPTCTRL9 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL10 = 32'hE00031E8;
-parameter val_usb1__ENDPTCTRL10 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL11 = 32'hE00031EC;
-parameter val_usb1__ENDPTCTRL11 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF;
-
-parameter usb1__ENDPTCTRL12 = 32'hE00031F0;
-parameter val_usb1__ENDPTCTRL12 = 32'h00000000;
-parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_unused_ports.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_unused_ports.v
deleted file mode 100755
index 770ceb47536c6cc6354834e2879d89f6fe4e68dc..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_8_unused_ports.v
+++ /dev/null
@@ -1,433 +0,0 @@
-/*****************************************************************************
- * File : processing_system7_vip_v1_0_8_unused_ports.v
- *
- * Date : 2012-11
- *
- * Description : Semantic checks for unused ports.
- *
- *****************************************************************************/
-
-/* CAN */
-assign CAN0_PHY_TX = 0;
-assign CAN1_PHY_TX = 0;
-always @(CAN0_PHY_RX or CAN1_PHY_RX)
-begin
- if(CAN0_PHY_RX | CAN1_PHY_RX)
- $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* ETHERNET */
-/* ------------------------------------------- */
-
-assign ENET0_GMII_TX_EN = 0;
-assign ENET0_GMII_TX_ER = 0;
-assign ENET0_MDIO_MDC = 0;
-assign ENET0_MDIO_O = 0; /// confirm
-assign ENET0_MDIO_T = 0;
-assign ENET0_PTP_DELAY_REQ_RX = 0;
-assign ENET0_PTP_DELAY_REQ_TX = 0;
-assign ENET0_PTP_PDELAY_REQ_RX = 0;
-assign ENET0_PTP_PDELAY_REQ_TX = 0;
-assign ENET0_PTP_PDELAY_RESP_RX = 0;
-assign ENET0_PTP_PDELAY_RESP_TX = 0;
-assign ENET0_PTP_SYNC_FRAME_RX = 0;
-assign ENET0_PTP_SYNC_FRAME_TX = 0;
-assign ENET0_SOF_RX = 0;
-assign ENET0_SOF_TX = 0;
-assign ENET0_GMII_TXD = 0;
-always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
- ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
- ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
-begin
- if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
- ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
- ENET0_GMII_TX_CLK | ENET0_MDIO_I )
- $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
-end
-
-assign ENET1_GMII_TX_EN = 0;
-assign ENET1_GMII_TX_ER = 0;
-assign ENET1_MDIO_MDC = 0;
-assign ENET1_MDIO_O = 0;/// confirm
-assign ENET1_MDIO_T = 0;
-assign ENET1_PTP_DELAY_REQ_RX = 0;
-assign ENET1_PTP_DELAY_REQ_TX = 0;
-assign ENET1_PTP_PDELAY_REQ_RX = 0;
-assign ENET1_PTP_PDELAY_REQ_TX = 0;
-assign ENET1_PTP_PDELAY_RESP_RX = 0;
-assign ENET1_PTP_PDELAY_RESP_TX = 0;
-assign ENET1_PTP_SYNC_FRAME_RX = 0;
-assign ENET1_PTP_SYNC_FRAME_TX = 0;
-assign ENET1_SOF_RX = 0;
-assign ENET1_SOF_TX = 0;
-assign ENET1_GMII_TXD = 0;
-always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
- ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
- ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
-begin
- if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
- ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
- ENET1_GMII_TX_CLK | ENET1_MDIO_I )
- $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* GPIO */
-/* ------------------------------------------- */
-
-assign GPIO_O = 0;
-assign GPIO_T = 0;
-always@(GPIO_I)
-begin
-// if(GPIO_I !== 0)
-// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* I2C */
-/* ------------------------------------------- */
-
-assign I2C0_SDA_O = 0;
-assign I2C0_SDA_T = 0;
-assign I2C0_SCL_O = 0;
-assign I2C0_SCL_T = 0;
-assign I2C1_SDA_O = 0;
-assign I2C1_SDA_T = 0;
-assign I2C1_SCL_O = 0;
-assign I2C1_SCL_T = 0;
-always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
-begin
- if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
- $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* JTAG */
-/* ------------------------------------------- */
-
-assign PJTAG_TD_T = 0;
-assign PJTAG_TD_O = 0;
-always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
-begin
- if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
- $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* SDIO */
-/* ------------------------------------------- */
-
-assign SDIO0_CLK = 0;
-assign SDIO0_CMD_O = 0;
-assign SDIO0_CMD_T = 0;
-assign SDIO0_DATA_O = 0;
-assign SDIO0_DATA_T = 0;
-assign SDIO0_LED = 0;
-assign SDIO0_BUSPOW = 0;
-assign SDIO0_BUSVOLT = 0;
-always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
-begin
- if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
- $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
-end
-
-assign SDIO1_CLK = 0;
-assign SDIO1_CMD_O = 0;
-assign SDIO1_CMD_T = 0;
-assign SDIO1_DATA_O = 0;
-assign SDIO1_DATA_T = 0;
-assign SDIO1_LED = 0;
-assign SDIO1_BUSPOW = 0;
-assign SDIO1_BUSVOLT = 0;
-always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
-begin
- if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
- $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* SPI */
-/* ------------------------------------------- */
-
-assign SPI0_SCLK_O = 0;
-assign SPI0_SCLK_T = 0;
-assign SPI0_MOSI_O = 0;
-assign SPI0_MOSI_T = 0;
-assign SPI0_MISO_O = 0;
-assign SPI0_MISO_T = 0;
-assign SPI0_SS_O = 0; /// confirm
-assign SPI0_SS1_O = 0;/// confirm
-assign SPI0_SS2_O = 0;/// confirm
-assign SPI0_SS_T = 0;
-always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
-begin
- if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
- $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
-end
-
-assign SPI1_SCLK_O = 0;
-assign SPI1_SCLK_T = 0;
-assign SPI1_MOSI_O = 0;
-assign SPI1_MOSI_T = 0;
-assign SPI1_MISO_O = 0;
-assign SPI1_MISO_T = 0;
-assign SPI1_SS_O = 0;
-assign SPI1_SS1_O = 0;
-assign SPI1_SS2_O = 0;
-assign SPI1_SS_T = 0;
-always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
-begin
- if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
- $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* UART */
-/* ------------------------------------------- */
-/// confirm
-assign UART0_DTRN = 0;
-assign UART0_RTSN = 0;
-assign UART0_TX = 0;
-always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
-begin
- if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
- $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
-end
-
-assign UART1_DTRN = 0;
-assign UART1_RTSN = 0;
-assign UART1_TX = 0;
-always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
-begin
- if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
- $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* TTC */
-/* ------------------------------------------- */
-
-assign TTC0_WAVE0_OUT = 0;
-assign TTC0_WAVE1_OUT = 0;
-assign TTC0_WAVE2_OUT = 0;
-always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
-begin
- if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
- $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
-end
-
-assign TTC1_WAVE0_OUT = 0;
-assign TTC1_WAVE1_OUT = 0;
-assign TTC1_WAVE2_OUT = 0;
-always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
-begin
- if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
- $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* WDT */
-/* ------------------------------------------- */
-
-assign WDT_RST_OUT = 0;
-always@(WDT_CLK_IN)
-begin
- if(WDT_CLK_IN)
- $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* TRACE */
-/* ------------------------------------------- */
-
-assign TRACE_CTL = 0;
-assign TRACE_DATA = 0;
-always@(TRACE_CLK)
-begin
- if(TRACE_CLK)
- $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* USB */
-/* ------------------------------------------- */
-assign USB0_PORT_INDCTL = 0;
-assign USB0_VBUS_PWRSELECT = 0;
-always@(USB0_VBUS_PWRFAULT)
-begin
- if(USB0_VBUS_PWRFAULT)
- $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
-end
-
-assign USB1_PORT_INDCTL = 0;
-assign USB1_VBUS_PWRSELECT = 0;
-always@(USB1_VBUS_PWRFAULT)
-begin
- if(USB1_VBUS_PWRFAULT)
- $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
-end
-
-always@(SRAM_INTIN)
-begin
- if(SRAM_INTIN)
- $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* DMA */
-/* ------------------------------------------- */
-
-assign DMA0_DATYPE = 0;
-assign DMA0_DAVALID = 0;
-assign DMA0_DRREADY = 0;
-assign DMA0_RSTN = 0;
-always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
-begin
- if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
- $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
-end
-
-assign DMA1_DATYPE = 0;
-assign DMA1_DAVALID = 0;
-assign DMA1_DRREADY = 0;
-assign DMA1_RSTN = 0;
-always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
-begin
- if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
- $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
-end
-
-assign DMA2_DATYPE = 0;
-assign DMA2_DAVALID = 0;
-assign DMA2_DRREADY = 0;
-assign DMA2_RSTN = 0;
-always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
-begin
- if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
- $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
-end
-
-assign DMA3_DATYPE = 0;
-assign DMA3_DAVALID = 0;
-assign DMA3_DRREADY = 0;
-assign DMA3_RSTN = 0;
-always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
-begin
- if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
- $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* FTM */
-/* ------------------------------------------- */
-
-assign FTMT_F2P_TRIGACK = 0;
-assign FTMT_P2F_TRIG = 0;
-assign FTMT_P2F_DEBUG = 0;
-always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
- FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
-begin
- if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
- $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* EVENT */
-/* ------------------------------------------- */
-
-assign EVENT_EVENTO = 0;
-assign EVENT_STANDBYWFE = 0;
-assign EVENT_STANDBYWFI = 0;
-always@(EVENT_EVENTI)
-begin
- if(EVENT_EVENTI)
- $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* MIO */
-/* ------------------------------------------- */
-
-always@(MIO)
-begin
-// if(MIO !== 0)
-// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* FCLK_TRIG */
-/* ------------------------------------------- */
-
-always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
-begin
- if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
- $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* MISC */
-/* ------------------------------------------- */
-
-always@(FPGA_IDLE_N)
-begin
- if(FPGA_IDLE_N)
- $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
-end
-
-always@(DDR_ARB)
-begin
-// if(DDR_ARB !== 0)
-// $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
-end
-
-always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
-begin
- if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
- $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* DDR */
-/* ------------------------------------------- */
-
-assign DDR_WEB = 0;
-always@(DDR_Clk or DDR_CS_n)
-begin
-if(!DDR_CS_n)
- $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
-end
-
-/* ------------------------------------------- */
-/* IRQ_P2F */
-/* ------------------------------------------- */
-
-assign IRQ_P2F_DMAC_ABORT = 0;
-assign IRQ_P2F_DMAC0 = 0;
-assign IRQ_P2F_DMAC1 = 0;
-assign IRQ_P2F_DMAC2 = 0;
-assign IRQ_P2F_DMAC3 = 0;
-assign IRQ_P2F_DMAC4 = 0;
-assign IRQ_P2F_DMAC5 = 0;
-assign IRQ_P2F_DMAC6 = 0;
-assign IRQ_P2F_DMAC7 = 0;
-assign IRQ_P2F_SMC = 0;
-assign IRQ_P2F_QSPI = 0;
-assign IRQ_P2F_CTI = 0;
-assign IRQ_P2F_GPIO = 0;
-assign IRQ_P2F_USB0 = 0;
-assign IRQ_P2F_ENET0 = 0;
-assign IRQ_P2F_ENET_WAKE0 = 0;
-assign IRQ_P2F_SDIO0 = 0;
-assign IRQ_P2F_I2C0 = 0;
-assign IRQ_P2F_SPI0 = 0;
-assign IRQ_P2F_UART0 = 0;
-assign IRQ_P2F_CAN0 = 0;
-assign IRQ_P2F_USB1 = 0;
-assign IRQ_P2F_ENET1 = 0;
-assign IRQ_P2F_ENET_WAKE1 = 0;
-assign IRQ_P2F_SDIO1 = 0;
-assign IRQ_P2F_I2C1 = 0;
-assign IRQ_P2F_SPI1 = 0;
-assign IRQ_P2F_UART1 = 0;
-assign IRQ_P2F_CAN1 = 0;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v
deleted file mode 100755
index 90a0bf53300e0a648c3fa110ca4a1eb2166e7b53..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v
+++ /dev/null
@@ -1,31 +0,0 @@
-//------------------------------------------------------------------------
-//--
-//-- Filename : xlconstant.v
-//--
-//-- Date : 06/05/12
-//--
-//-- Description : VERILOG description of a constant block. This
-//-- block does not use a core.
-//--
-//------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------
-//--
-//-- Module : xlconstant
-//--
-//-- Architecture : behavior
-//--
-//-- Description : Top level VERILOG description of constant block
-//--
-//------------------------------------------------------------------------
-`timescale 1ps/1ps
-module xlconstant_v1_1_6_xlconstant (dout);
- parameter CONST_VAL = 1;
- parameter CONST_WIDTH = 1;
- output [CONST_WIDTH-1:0] dout;
-
- assign dout = CONST_VAL;
-endmodule
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/46fd/hdl/vio_v3_0_19_vio_include.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/46fd/hdl/vio_v3_0_19_vio_include.v
deleted file mode 100755
index 9b2ac768b2a01377eb04be1b23d19aa81008bfbf..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/46fd/hdl/vio_v3_0_19_vio_include.v
+++ /dev/null
@@ -1,292 +0,0 @@
-`pragma protect begin_protected
-`pragma protect version = 1
-`pragma protect encrypt_agent = "XILINX"
-`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
-`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
-`pragma protect key_block
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-hUEBDwnMWQ==
-
-`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-vrI4r+MC+eI2DfesoN4=
-
-`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect data_method = "AES128-CBC"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
-`pragma protect data_block
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/46fd/hdl/vio_v3_0_syn_rfs.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/46fd/hdl/vio_v3_0_syn_rfs.v
deleted file mode 100755
index 968c65a1fc501acaa81fe6a3fb51a4a2b7a10b09..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/46fd/hdl/vio_v3_0_syn_rfs.v
+++ /dev/null
@@ -1,5008 +0,0 @@
-`pragma protect begin_protected
-`pragma protect version = 1
-`pragma protect encrypt_agent = "XILINX"
-`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
-`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect data_method = "AES128-CBC"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 281264)
-`pragma protect data_block
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v
deleted file mode 100755
index 98caca1518a127a10d77c7ca3ce50e0566177530..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v
+++ /dev/null
@@ -1,409 +0,0 @@
-//-----------------------------------------------------------------------------
-//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
-//--
-//-- This file contains confidential and proprietary information
-//-- of Xilinx, Inc. and is protected under U.S. and
-//-- international copyright and other intellectual property
-//-- laws.
-//--
-//-- DISCLAIMER
-//-- This disclaimer is not a license and does not grant any
-//-- rights to the materials distributed herewith. Except as
-//-- otherwise provided in a valid license issued to you by
-//-- Xilinx, and to the maximum extent permitted by applicable
-//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-//-- (2) Xilinx shall not be liable (whether in contract or tort,
-//-- including negligence, or under any other theory of
-//-- liability) for any loss or damage of any kind or nature
-//-- related to, arising under or in connection with these
-//-- materials, including for any direct, or any indirect,
-//-- special, incidental, or consequential loss or damage
-//-- (including loss of data, profits, goodwill, or any type of
-//-- loss or damage suffered as a result of any action brought
-//-- by a third party) even if such damage or loss was
-//-- reasonably foreseeable or Xilinx had been advised of the
-//-- possibility of the same.
-//--
-//-- CRITICAL APPLICATIONS
-//-- Xilinx products are not designed or intended to be fail-
-//-- safe, or for use in any application requiring fail-safe
-//-- performance, such as life-support or safety devices or
-//-- systems, Class III medical devices, nuclear facilities,
-//-- applications related to the deployment of airbags, or any
-//-- other applications that could lead to death, personal
-//-- injury, or severe property or environmental damage
-//-- (individually and collectively, "Critical
-//-- Applications"). Customer assumes the sole risk and
-//-- liability of any use of Xilinx products in Critical
-//-- Applications, subject only to applicable laws and
-//-- regulations governing limitations on product liability.
-//--
-//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-//-- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: ACP Transaction Checker
-//
-// Check for optimized ACP transactions and flag if they are broken.
-//
-//
-//
-// Verilog-standard: Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-// atc
-// aw_atc
-// w_atc
-// b_atc
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-`default_nettype none
-
-module processing_system7_v5_5_atc #
- (
- parameter C_FAMILY = "rtl",
- // FPGA Family. Current version: virtex6, spartan6 or later.
- parameter integer C_AXI_ID_WIDTH = 4,
- // Width of all ID signals on SI and MI side of checker.
- // Range: >= 1.
- parameter integer C_AXI_ADDR_WIDTH = 32,
- // Width of all ADDR signals on SI and MI side of checker.
- // Range: 32.
- parameter integer C_AXI_DATA_WIDTH = 64,
- // Width of all DATA signals on SI and MI side of checker.
- // Range: 64.
- parameter integer C_AXI_AWUSER_WIDTH = 1,
- // Width of AWUSER signals.
- // Range: >= 1.
- parameter integer C_AXI_ARUSER_WIDTH = 1,
- // Width of ARUSER signals.
- // Range: >= 1.
- parameter integer C_AXI_WUSER_WIDTH = 1,
- // Width of WUSER signals.
- // Range: >= 1.
- parameter integer C_AXI_RUSER_WIDTH = 1,
- // Width of RUSER signals.
- // Range: >= 1.
- parameter integer C_AXI_BUSER_WIDTH = 1
- // Width of BUSER signals.
- // Range: >= 1.
- )
- (
- // Global Signals
- input wire ACLK,
- input wire ARESETN,
-
- // Slave Interface Write Address Ports
- input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
- input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
- input wire [4-1:0] S_AXI_AWLEN,
- input wire [3-1:0] S_AXI_AWSIZE,
- input wire [2-1:0] S_AXI_AWBURST,
- input wire [2-1:0] S_AXI_AWLOCK,
- input wire [4-1:0] S_AXI_AWCACHE,
- input wire [3-1:0] S_AXI_AWPROT,
- input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
- input wire S_AXI_AWVALID,
- output wire S_AXI_AWREADY,
- // Slave Interface Write Data Ports
- input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
- input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
- input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
- input wire S_AXI_WLAST,
- input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
- input wire S_AXI_WVALID,
- output wire S_AXI_WREADY,
- // Slave Interface Write Response Ports
- output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
- output wire [2-1:0] S_AXI_BRESP,
- output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
- output wire S_AXI_BVALID,
- input wire S_AXI_BREADY,
- // Slave Interface Read Address Ports
- input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
- input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
- input wire [4-1:0] S_AXI_ARLEN,
- input wire [3-1:0] S_AXI_ARSIZE,
- input wire [2-1:0] S_AXI_ARBURST,
- input wire [2-1:0] S_AXI_ARLOCK,
- input wire [4-1:0] S_AXI_ARCACHE,
- input wire [3-1:0] S_AXI_ARPROT,
- input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
- input wire S_AXI_ARVALID,
- output wire S_AXI_ARREADY,
- // Slave Interface Read Data Ports
- output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
- output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
- output wire [2-1:0] S_AXI_RRESP,
- output wire S_AXI_RLAST,
- output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
- output wire S_AXI_RVALID,
- input wire S_AXI_RREADY,
-
- // Master Interface Write Address Port
- output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
- output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
- output wire [4-1:0] M_AXI_AWLEN,
- output wire [3-1:0] M_AXI_AWSIZE,
- output wire [2-1:0] M_AXI_AWBURST,
- output wire [2-1:0] M_AXI_AWLOCK,
- output wire [4-1:0] M_AXI_AWCACHE,
- output wire [3-1:0] M_AXI_AWPROT,
- output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
- output wire M_AXI_AWVALID,
- input wire M_AXI_AWREADY,
- // Master Interface Write Data Ports
- output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
- output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
- output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
- output wire M_AXI_WLAST,
- output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
- output wire M_AXI_WVALID,
- input wire M_AXI_WREADY,
- // Master Interface Write Response Ports
- input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
- input wire [2-1:0] M_AXI_BRESP,
- input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
- input wire M_AXI_BVALID,
- output wire M_AXI_BREADY,
- // Master Interface Read Address Port
- output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
- output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
- output wire [4-1:0] M_AXI_ARLEN,
- output wire [3-1:0] M_AXI_ARSIZE,
- output wire [2-1:0] M_AXI_ARBURST,
- output wire [2-1:0] M_AXI_ARLOCK,
- output wire [4-1:0] M_AXI_ARCACHE,
- output wire [3-1:0] M_AXI_ARPROT,
- output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
- output wire M_AXI_ARVALID,
- input wire M_AXI_ARREADY,
- // Master Interface Read Data Ports
- input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
- input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
- input wire [2-1:0] M_AXI_RRESP,
- input wire M_AXI_RLAST,
- input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
- input wire M_AXI_RVALID,
- output wire M_AXI_RREADY,
-
- output wire ERROR_TRIGGER,
- output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
- );
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Functions
- /////////////////////////////////////////////////////////////////////////////
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Local params
- /////////////////////////////////////////////////////////////////////////////
-
- localparam C_FIFO_DEPTH_LOG = 4;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Internal signals
- /////////////////////////////////////////////////////////////////////////////
-
- // Internal reset.
- reg ARESET;
-
- // AW->W command queue signals.
- wire cmd_w_valid;
- wire cmd_w_check;
- wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
- wire cmd_w_ready;
-
- // W->B command queue signals.
- wire cmd_b_push;
- wire cmd_b_error;
- wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
- wire cmd_b_full;
- wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
- wire cmd_b_ready;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Handle Internal Reset
- /////////////////////////////////////////////////////////////////////////////
- always @ (posedge ACLK) begin
- ARESET <= !ARESETN;
- end
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Handle Write Channels (AW/W/B)
- /////////////////////////////////////////////////////////////////////////////
-
- // Write Address Channel.
- processing_system7_v5_5_aw_atc #
- (
- .C_FAMILY (C_FAMILY),
- .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
- .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
- .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
- .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
- ) write_addr_inst
- (
- // Global Signals
- .ARESET (ARESET),
- .ACLK (ACLK),
-
- // Command Interface (Out)
- .cmd_w_valid (cmd_w_valid),
- .cmd_w_check (cmd_w_check),
- .cmd_w_id (cmd_w_id),
- .cmd_w_ready (cmd_w_ready),
- .cmd_b_addr (cmd_b_addr),
- .cmd_b_ready (cmd_b_ready),
-
- // Slave Interface Write Address Ports
- .S_AXI_AWID (S_AXI_AWID),
- .S_AXI_AWADDR (S_AXI_AWADDR),
- .S_AXI_AWLEN (S_AXI_AWLEN),
- .S_AXI_AWSIZE (S_AXI_AWSIZE),
- .S_AXI_AWBURST (S_AXI_AWBURST),
- .S_AXI_AWLOCK (S_AXI_AWLOCK),
- .S_AXI_AWCACHE (S_AXI_AWCACHE),
- .S_AXI_AWPROT (S_AXI_AWPROT),
- .S_AXI_AWUSER (S_AXI_AWUSER),
- .S_AXI_AWVALID (S_AXI_AWVALID),
- .S_AXI_AWREADY (S_AXI_AWREADY),
-
- // Master Interface Write Address Port
- .M_AXI_AWID (M_AXI_AWID),
- .M_AXI_AWADDR (M_AXI_AWADDR),
- .M_AXI_AWLEN (M_AXI_AWLEN),
- .M_AXI_AWSIZE (M_AXI_AWSIZE),
- .M_AXI_AWBURST (M_AXI_AWBURST),
- .M_AXI_AWLOCK (M_AXI_AWLOCK),
- .M_AXI_AWCACHE (M_AXI_AWCACHE),
- .M_AXI_AWPROT (M_AXI_AWPROT),
- .M_AXI_AWUSER (M_AXI_AWUSER),
- .M_AXI_AWVALID (M_AXI_AWVALID),
- .M_AXI_AWREADY (M_AXI_AWREADY)
- );
-
- // Write Data channel.
- processing_system7_v5_5_w_atc #
- (
- .C_FAMILY (C_FAMILY),
- .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
- .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
- .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
- ) write_data_inst
- (
- // Global Signals
- .ARESET (ARESET),
- .ACLK (ACLK),
-
- // Command Interface (In)
- .cmd_w_valid (cmd_w_valid),
- .cmd_w_check (cmd_w_check),
- .cmd_w_id (cmd_w_id),
- .cmd_w_ready (cmd_w_ready),
-
- // Command Interface (Out)
- .cmd_b_push (cmd_b_push),
- .cmd_b_error (cmd_b_error),
- .cmd_b_id (cmd_b_id),
- .cmd_b_full (cmd_b_full),
-
- // Slave Interface Write Data Ports
- .S_AXI_WID (S_AXI_WID),
- .S_AXI_WDATA (S_AXI_WDATA),
- .S_AXI_WSTRB (S_AXI_WSTRB),
- .S_AXI_WLAST (S_AXI_WLAST),
- .S_AXI_WUSER (S_AXI_WUSER),
- .S_AXI_WVALID (S_AXI_WVALID),
- .S_AXI_WREADY (S_AXI_WREADY),
-
- // Master Interface Write Data Ports
- .M_AXI_WID (M_AXI_WID),
- .M_AXI_WDATA (M_AXI_WDATA),
- .M_AXI_WSTRB (M_AXI_WSTRB),
- .M_AXI_WLAST (M_AXI_WLAST),
- .M_AXI_WUSER (M_AXI_WUSER),
- .M_AXI_WVALID (M_AXI_WVALID),
- .M_AXI_WREADY (M_AXI_WREADY)
- );
-
- // Write Response channel.
- processing_system7_v5_5_b_atc #
- (
- .C_FAMILY (C_FAMILY),
- .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
- .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
- .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
- ) write_response_inst
- (
- // Global Signals
- .ARESET (ARESET),
- .ACLK (ACLK),
-
- // Command Interface (In)
- .cmd_b_push (cmd_b_push),
- .cmd_b_error (cmd_b_error),
- .cmd_b_id (cmd_b_id),
- .cmd_b_full (cmd_b_full),
- .cmd_b_addr (cmd_b_addr),
- .cmd_b_ready (cmd_b_ready),
-
- // Slave Interface Write Response Ports
- .S_AXI_BID (S_AXI_BID),
- .S_AXI_BRESP (S_AXI_BRESP),
- .S_AXI_BUSER (S_AXI_BUSER),
- .S_AXI_BVALID (S_AXI_BVALID),
- .S_AXI_BREADY (S_AXI_BREADY),
-
- // Master Interface Write Response Ports
- .M_AXI_BID (M_AXI_BID),
- .M_AXI_BRESP (M_AXI_BRESP),
- .M_AXI_BUSER (M_AXI_BUSER),
- .M_AXI_BVALID (M_AXI_BVALID),
- .M_AXI_BREADY (M_AXI_BREADY),
-
- // Trigger detection
- .ERROR_TRIGGER (ERROR_TRIGGER),
- .ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
- );
-
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Handle Read Channels (AR/R)
- /////////////////////////////////////////////////////////////////////////////
- // Read Address Port
- assign M_AXI_ARID = S_AXI_ARID;
- assign M_AXI_ARADDR = S_AXI_ARADDR;
- assign M_AXI_ARLEN = S_AXI_ARLEN;
- assign M_AXI_ARSIZE = S_AXI_ARSIZE;
- assign M_AXI_ARBURST = S_AXI_ARBURST;
- assign M_AXI_ARLOCK = S_AXI_ARLOCK;
- assign M_AXI_ARCACHE = S_AXI_ARCACHE;
- assign M_AXI_ARPROT = S_AXI_ARPROT;
- assign M_AXI_ARUSER = S_AXI_ARUSER;
- assign M_AXI_ARVALID = S_AXI_ARVALID;
- assign S_AXI_ARREADY = M_AXI_ARREADY;
-
- // Read Data Port
- assign S_AXI_RID = M_AXI_RID;
- assign S_AXI_RDATA = M_AXI_RDATA;
- assign S_AXI_RRESP = M_AXI_RRESP;
- assign S_AXI_RLAST = M_AXI_RLAST;
- assign S_AXI_RUSER = M_AXI_RUSER;
- assign S_AXI_RVALID = M_AXI_RVALID;
- assign M_AXI_RREADY = S_AXI_RREADY;
-
-
-endmodule
-`default_nettype wire
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v
deleted file mode 100755
index 25bbc9d246998cfdadc812f96f05cff1963028b6..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v
+++ /dev/null
@@ -1,298 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: Address Write Channel for ATC
-//
-//
-// Verilog-standard: Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-// aw_atc
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-
-module processing_system7_v5_5_aw_atc #
- (
- parameter C_FAMILY = "rtl",
- // FPGA Family. Current version: virtex6, spartan6 or later.
- parameter integer C_AXI_ID_WIDTH = 4,
- // Width of all ID signals on SI and MI side of checker.
- // Range: >= 1.
- parameter integer C_AXI_ADDR_WIDTH = 32,
- // Width of all ADDR signals on SI and MI side of checker.
- // Range: 32.
- parameter integer C_AXI_AWUSER_WIDTH = 1,
- // Width of AWUSER signals.
- // Range: >= 1.
- parameter integer C_FIFO_DEPTH_LOG = 4
- )
- (
- // Global Signals
- input wire ARESET,
- input wire ACLK,
-
- // Command Interface
- output reg cmd_w_valid,
- output wire cmd_w_check,
- output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
- input wire cmd_w_ready,
- input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
- input wire cmd_b_ready,
-
- // Slave Interface Write Address Port
- input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
- input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
- input wire [4-1:0] S_AXI_AWLEN,
- input wire [3-1:0] S_AXI_AWSIZE,
- input wire [2-1:0] S_AXI_AWBURST,
- input wire [2-1:0] S_AXI_AWLOCK,
- input wire [4-1:0] S_AXI_AWCACHE,
- input wire [3-1:0] S_AXI_AWPROT,
- input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
- input wire S_AXI_AWVALID,
- output wire S_AXI_AWREADY,
-
- // Master Interface Write Address Port
- output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
- output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
- output wire [4-1:0] M_AXI_AWLEN,
- output wire [3-1:0] M_AXI_AWSIZE,
- output wire [2-1:0] M_AXI_AWBURST,
- output wire [2-1:0] M_AXI_AWLOCK,
- output wire [4-1:0] M_AXI_AWCACHE,
- output wire [3-1:0] M_AXI_AWPROT,
- output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
- output wire M_AXI_AWVALID,
- input wire M_AXI_AWREADY
- );
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Local params
- /////////////////////////////////////////////////////////////////////////////
-
- // Constants for burst types.
- localparam [2-1:0] C_FIX_BURST = 2'b00;
- localparam [2-1:0] C_INCR_BURST = 2'b01;
- localparam [2-1:0] C_WRAP_BURST = 2'b10;
-
- // Constants for size.
- localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011;
-
- // Constants for length.
- localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011;
-
- // Constants for cacheline address.
- localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0;
-
- // Command FIFO settings
- localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
- localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Variables for generating parameter controlled instances.
- /////////////////////////////////////////////////////////////////////////////
-
- integer index;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Functions
- /////////////////////////////////////////////////////////////////////////////
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Internal signals
- /////////////////////////////////////////////////////////////////////////////
-
- // Transaction properties.
- wire access_is_incr;
- wire access_is_wrap;
- wire access_is_coherent;
- wire access_optimized_size;
- wire incr_addr_boundary;
- wire incr_is_optimized;
- wire wrap_is_optimized;
- wire access_is_optimized;
-
- // Command FIFO.
- wire cmd_w_push;
- reg cmd_full;
- reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
- wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr;
- reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Transaction Decode:
- //
- // Detect if transaction is of correct typ, size and length to qualify as
- // an optimized transaction that has to be checked for errors.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Transaction burst type.
- assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST );
- assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST );
-
- // Transaction has to be Coherent.
- assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) &
- ( S_AXI_AWCACHE[1] == 1'b1 );
-
- // Transaction cacheline boundary address.
- assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
-
- // Transaction length & size.
- assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) &
- ( S_AXI_AWLEN == C_OPTIMIZED_LEN );
-
- // Transaction is optimized.
- assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
- assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size;
- assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized );
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Command FIFO:
- //
- // Since supported write interleaving is only 1, it is safe to use only a
- // simple SRL based FIFO as a command queue.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Determine when transaction infromation is pushed to the FIFO.
- assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
-
- // SRL FIFO Pointer.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
- end else begin
- if ( cmd_w_push & ~cmd_w_ready ) begin
- addr_ptr <= addr_ptr + 1;
- end else if ( ~cmd_w_push & cmd_w_ready ) begin
- addr_ptr <= addr_ptr - 1;
- end
- end
- end
-
- // Total number of buffered commands.
- assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
-
- // FIFO Flags.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- cmd_full <= 1'b0;
- cmd_w_valid <= 1'b0;
- end else begin
- if ( cmd_w_push & ~cmd_w_ready ) begin
- cmd_w_valid <= 1'b1;
- end else if ( ~cmd_w_push & cmd_w_ready ) begin
- cmd_w_valid <= ( addr_ptr != 0 );
- end
- if ( cmd_w_push & ~cmd_b_ready ) begin
- // Going to full.
- cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
- end else if ( ~cmd_w_push & cmd_b_ready ) begin
- // Pop in middle of queue doesn't affect full status.
- cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
- end
- end
- end
-
- // Infere SRL for storage.
- always @ (posedge ACLK) begin
- if ( cmd_w_push ) begin
- for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
- data_srl[index+1] <= data_srl[index];
- end
- data_srl[0] <= {access_is_optimized, S_AXI_AWID};
- end
- end
-
- // Get current transaction info.
- assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Transaction Throttling:
- //
- // Stall commands if FIFO is full.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Propagate masked valid.
- assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full;
-
- // Return ready with push back.
- assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Address Write propagation:
- //
- // All information is simply forwarded on from the SI- to MI-Side untouched.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // 1:1 mapping.
- assign M_AXI_AWID = S_AXI_AWID;
- assign M_AXI_AWADDR = S_AXI_AWADDR;
- assign M_AXI_AWLEN = S_AXI_AWLEN;
- assign M_AXI_AWSIZE = S_AXI_AWSIZE;
- assign M_AXI_AWBURST = S_AXI_AWBURST;
- assign M_AXI_AWLOCK = S_AXI_AWLOCK;
- assign M_AXI_AWCACHE = S_AXI_AWCACHE;
- assign M_AXI_AWPROT = S_AXI_AWPROT;
- assign M_AXI_AWUSER = S_AXI_AWUSER;
-
-
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v
deleted file mode 100755
index 36f280fcacd1e765b68d7f861e34fc3bac74e256..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v
+++ /dev/null
@@ -1,413 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: Write Response Channel for ATC
-//
-//
-// Verilog-standard: Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-// b_atc
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-
-module processing_system7_v5_5_b_atc #
- (
- parameter C_FAMILY = "rtl",
- // FPGA Family. Current version: virtex6, spartan6 or later.
- parameter integer C_AXI_ID_WIDTH = 4,
- // Width of all ID signals on SI and MI side of checker.
- // Range: >= 1.
- parameter integer C_AXI_BUSER_WIDTH = 1,
- // Width of AWUSER signals.
- // Range: >= 1.
- parameter integer C_FIFO_DEPTH_LOG = 4
- )
- (
- // Global Signals
- input wire ARESET,
- input wire ACLK,
-
- // Command Interface
- input wire cmd_b_push,
- input wire cmd_b_error,
- input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
- output wire cmd_b_ready,
- output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
- output reg cmd_b_full,
-
- // Slave Interface Write Response Ports
- output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
- output reg [2-1:0] S_AXI_BRESP,
- output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
- output wire S_AXI_BVALID,
- input wire S_AXI_BREADY,
-
- // Master Interface Write Response Ports
- input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
- input wire [2-1:0] M_AXI_BRESP,
- input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
- input wire M_AXI_BVALID,
- output wire M_AXI_BREADY,
-
- // Trigger detection
- output reg ERROR_TRIGGER,
- output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
- );
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Local params
- /////////////////////////////////////////////////////////////////////////////
-
- // Constants for packing levels.
- localparam [2-1:0] C_RESP_OKAY = 2'b00;
- localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
- localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
- localparam [2-1:0] C_RESP_DECERR = 2'b11;
-
- // Command FIFO settings
- localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
- localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Variables for generating parameter controlled instances.
- /////////////////////////////////////////////////////////////////////////////
-
- integer index;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Functions
- /////////////////////////////////////////////////////////////////////////////
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Internal signals
- /////////////////////////////////////////////////////////////////////////////
-
- // Command Queue.
- reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
- reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
- reg cmd_b_valid;
- wire cmd_b_ready_i;
- wire inject_error;
- wire [C_AXI_ID_WIDTH-1:0] current_id;
-
- // Search command.
- wire found_match;
- wire use_match;
- wire matching_id;
-
- // Manage valid command.
- wire write_valid_cmd;
- reg [C_FIFO_DEPTH-2:0] valid_cmd;
- reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
- reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
- reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
- reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
-
- // Pipelined data
- reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
- reg [2-1:0] M_AXI_BRESP_I;
- reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
- reg M_AXI_BVALID_I;
- wire M_AXI_BREADY_I;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Command Queue:
- //
- // Keep track of depth of Queue to generate full flag.
- //
- // Also generate valid to mark pressence of commands in Queue.
- //
- // Maintain Queue and extract data from currently searched entry.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // SRL FIFO Pointer.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
- end else begin
- if ( cmd_b_push & ~cmd_b_ready_i ) begin
- // Pushing data increase length/addr.
- addr_ptr <= addr_ptr + 1;
- end else if ( cmd_b_ready_i ) begin
- // Collapse addr when data is popped.
- addr_ptr <= collapsed_addr_ptr;
- end
- end
- end
-
- // FIFO Flags.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- cmd_b_full <= 1'b0;
- cmd_b_valid <= 1'b0;
- end else begin
- if ( cmd_b_push & ~cmd_b_ready_i ) begin
- cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
- cmd_b_valid <= 1'b1;
- end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
- cmd_b_full <= 1'b0;
- cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
- end
- end
- end
-
- // Infere SRL for storage.
- always @ (posedge ACLK) begin
- if ( cmd_b_push ) begin
- for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
- data_srl[index+1] <= data_srl[index];
- end
- data_srl[0] <= {cmd_b_error, cmd_b_id};
- end
- end
-
- // Get current transaction info.
- assign {inject_error, current_id} = data_srl[search_addr_ptr];
-
- // Assign outputs.
- assign cmd_b_addr = collapsed_addr_ptr;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Search Command Queue:
- //
- // Search for matching valid command in queue.
- //
- // A command is found when an valid entry with correct ID is found. The queue
- // is search from the oldest entry, i.e. from a high value.
- // When new commands are pushed the search address has to be updated to always
- // start the search from the oldest available.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Handle search addr.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
- end else begin
- if ( cmd_b_ready_i ) begin
- // Collapse addr when data is popped.
- search_addr_ptr <= collapsed_addr_ptr;
-
- end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
- // Skip non valid command.
- search_addr_ptr <= search_addr_ptr - 1;
-
- end else if ( cmd_b_push ) begin
- search_addr_ptr <= search_addr_ptr + 1;
-
- end
- end
- end
-
- // Check if searched command is valid and match ID (for existing response on MI side).
- assign matching_id = ( M_AXI_BID_I == current_id );
- assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
- assign use_match = found_match & S_AXI_BREADY;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Track Used Commands:
- //
- // Actions that affect Valid Command:
- // * When a new command is pushed
- // => Shift valid vector one step
- // * When a command is used
- // => Clear corresponding valid bit
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Valid command status is updated when a command is used or a new one is pushed.
- assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
-
- // Update the used command valid bit.
- always @ *
- begin
- updated_valid_cmd = valid_cmd;
- updated_valid_cmd[search_addr_ptr] = ~use_match;
- end
-
- // Shift valid vector when command is pushed.
- always @ *
- begin
- if ( cmd_b_push ) begin
- next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
- end else begin
- next_valid_cmd = updated_valid_cmd;
- end
- end
-
- // Valid signals for next cycle.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- valid_cmd <= {C_FIFO_WIDTH{1'b0}};
- end else if ( write_valid_cmd ) begin
- valid_cmd <= next_valid_cmd;
- end
- end
-
- // Detect oldest available command in Queue.
- always @ *
- begin
- // Default to empty.
- collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
-
- for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
- if ( next_valid_cmd[index] ) begin
- collapsed_addr_ptr = index;
- end
- end
- end
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Pipe incoming data:
- //
- // The B channel is piped to improve timing and avoid impact in search
- // mechanism due to late arriving signals.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Clock data.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
- M_AXI_BRESP_I <= 2'b00;
- M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
- M_AXI_BVALID_I <= 1'b0;
- end else begin
- if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
- M_AXI_BVALID_I <= 1'b0;
- end
- if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
- M_AXI_BID_I <= M_AXI_BID;
- M_AXI_BRESP_I <= M_AXI_BRESP;
- M_AXI_BUSER_I <= M_AXI_BUSER;
- M_AXI_BVALID_I <= 1'b1;
- end
- end
- end
-
- // Generate ready to get new transaction.
- assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Inject Error:
- //
- // BRESP is modified according to command information.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Inject error in response.
- always @ *
- begin
- if ( inject_error ) begin
- S_AXI_BRESP = C_RESP_SLVERROR;
- end else begin
- S_AXI_BRESP = M_AXI_BRESP_I;
- end
- end
-
- // Handle interrupt generation.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- ERROR_TRIGGER <= 1'b0;
- ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
- end else begin
- if ( inject_error & cmd_b_ready_i ) begin
- ERROR_TRIGGER <= 1'b1;
- ERROR_TRANSACTION_ID <= M_AXI_BID_I;
- end else begin
- ERROR_TRIGGER <= 1'b0;
- end
- end
- end
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Transaction Throttling:
- //
- // Response is passed forward when a matching entry has been found in queue.
- // Both ready and valid are set when the command is completed.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Propagate masked valid.
- assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
-
- // Return ready with push back.
- assign M_AXI_BREADY_I = cmd_b_valid & use_match;
-
- // Command has been handled.
- assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
- assign cmd_b_ready = cmd_b_ready_i;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Write Response Propagation:
- //
- // All information is simply forwarded on from MI- to SI-Side untouched.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // 1:1 mapping.
- assign S_AXI_BID = M_AXI_BID_I;
- assign S_AXI_BUSER = M_AXI_BUSER_I;
-
-
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v
deleted file mode 100755
index 0c776b3cbc41b98abf2525efcb9be28948753321..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v
+++ /dev/null
@@ -1,310 +0,0 @@
-// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-// Filename: trace_buffer.v
-// Description: Trace port buffer
-//-----------------------------------------------------------------------------
-// Structure: This section shows the hierarchical structure of
-// pss_wrapper.
-//
-// --processing_system7
-// |
-// --trace_buffer
-//-----------------------------------------------------------------------------
-
-
-module processing_system7_v5_5_trace_buffer #
- (
- parameter integer FIFO_SIZE = 128,
- parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
- parameter integer C_DELAY_CLKS = 12
- )
- (
- input wire TRACE_CLK,
- input wire RST,
- input wire TRACE_VALID_IN,
- input wire [3:0] TRACE_ATID_IN,
- input wire [31:0] TRACE_DATA_IN,
- output wire TRACE_VALID_OUT,
- output wire [3:0] TRACE_ATID_OUT,
- output wire [31:0] TRACE_DATA_OUT
- );
-
-//------------------------------------------------------------
-// Architecture section
-//------------------------------------------------------------
-
-// function called clogb2 that returns an integer which has the
-// value of the ceiling of the log base 2.
-
-function integer clogb2 (input integer bit_depth);
- integer i;
- integer temp_log;
- begin
- temp_log = 0;
- for(i=bit_depth; i > 0; i = i>>1)
- clogb2 = temp_log;
- temp_log=temp_log+1;
- end
-endfunction
-
-localparam DEPTH = clogb2(FIFO_SIZE-1);
-
-wire [31:0] reset_zeros;
-reg [31:0] trace_pedge; // write enable for FIFO
-reg [31:0] ti;
-reg [31:0] tom;
-
-reg [3:0] atid;
-
-reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
-
-reg [4:0] dly_ctr;
-reg [DEPTH-1:0] fifo_wp;
-reg [DEPTH-1:0] fifo_rp;
-
-reg fifo_re;
-wire fifo_empty;
-wire fifo_full;
-reg fifo_full_reg;
-
-assign reset_zeros = 32'h0;
-
-
-// Pipeline Stage for Traceport ATID ports
- always @(posedge TRACE_CLK) begin
- // process pedge_ti
- // rising clock edge
- if((RST == 1'b1)) begin
- atid <= reset_zeros;
- end
- else begin
- atid <= TRACE_ATID_IN;
- end
- end
-
- assign TRACE_ATID_OUT = atid;
-
- /////////////////////////////////////////////
- // Generate FIFO data based on TRACE_VALID_IN
- /////////////////////////////////////////////
- generate
- if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
- /////////////////////////////////////////////
-
- // memory update process
- // Update memory when positive edge detected and FIFO not full
- always @(posedge TRACE_CLK) begin
- if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
- trace_fifo[fifo_wp] <= TRACE_DATA_IN;
- end
- end
-
- // fifo write pointer
- always @(posedge TRACE_CLK) begin
- // process
- if(RST == 1'b1) begin
- fifo_wp <= {DEPTH{1'b0}};
- end
- else if(TRACE_VALID_IN ) begin
- if(fifo_wp == (FIFO_SIZE - 1)) begin
- if (fifo_empty) begin
- fifo_wp <= {DEPTH{1'b0}};
- end
- end
- else begin
- fifo_wp <= fifo_wp + 1;
- end
- end
- end
-
-
- /////////////////////////////////////////////
- // Generate FIFO data based on data edge
- /////////////////////////////////////////////
- end else begin : gen_data_edge_detector
- /////////////////////////////////////////////
-
-
- // purpose: check for pos edge on any trace input
- always @(posedge TRACE_CLK) begin
- // process pedge_ti
- // rising clock edge
- if((RST == 1'b1)) begin
- ti <= reset_zeros;
- trace_pedge <= reset_zeros;
- end
- else begin
- ti <= TRACE_DATA_IN;
- trace_pedge <= (~ti & TRACE_DATA_IN);
- //trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
- // posedge only
- end
- end
-
- // memory update process
- // Update memory when positive edge detected and FIFO not full
- always @(posedge TRACE_CLK) begin
- if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
- trace_fifo[fifo_wp] <= trace_pedge;
- end
- end
-
- // fifo write pointer
- always @(posedge TRACE_CLK) begin
- // process
- if(RST == 1'b1) begin
- fifo_wp <= {DEPTH{1'b0}};
- end
- else if(|(trace_pedge) == 1'b1) begin
- if(fifo_wp == (FIFO_SIZE - 1)) begin
- if (fifo_empty) begin
- fifo_wp <= {DEPTH{1'b0}};
- end
- end
- else begin
- fifo_wp <= fifo_wp + 1;
- end
- end
- end
-
-
- end
- endgenerate
-
-
- always @(posedge TRACE_CLK) begin
- tom <= trace_fifo[fifo_rp] ;
- end
-
-
-// // fifo write pointer
-// always @(posedge TRACE_CLK) begin
-// // process
-// if(RST == 1'b1) begin
-// fifo_wp <= {DEPTH{1'b0}};
-// end
-// else if(|(trace_pedge) == 1'b1) begin
-// if(fifo_wp == (FIFO_SIZE - 1)) begin
-// fifo_wp <= {DEPTH{1'b0}};
-// end
-// else begin
-// fifo_wp <= fifo_wp + 1;
-// end
-// end
-// end
-
-
- // fifo read pointer update
- always @(posedge TRACE_CLK) begin
- if(RST == 1'b1) begin
- fifo_rp <= {DEPTH{1'b0}};
- fifo_re <= 1'b0;
- end
- else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
- fifo_re <= 1'b1;
- if(fifo_rp == (FIFO_SIZE - 1)) begin
- fifo_rp <= {DEPTH{1'b0}};
- end
- else begin
- fifo_rp <= fifo_rp + 1;
- end
- end
- else begin
- fifo_re <= 1'b0;
- end
- end
-
- // delay counter update
- always @(posedge TRACE_CLK) begin
- if(RST == 1'b1) begin
- dly_ctr <= 5'h0;
- end
- else if (fifo_re == 1'b1) begin
- dly_ctr <= C_DELAY_CLKS-1;
- end
- else if(dly_ctr != 5'h0) begin
- dly_ctr <= dly_ctr - 1;
- end
- end
-
- // fifo empty update
- assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
-
- // fifo full update
- assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
-
- always @(posedge TRACE_CLK) begin
- if(RST == 1'b1) begin
- fifo_full_reg <= 1'b0;
- end
- else if (fifo_empty) begin
- fifo_full_reg <= 1'b0;
- end else begin
- fifo_full_reg <= fifo_full;
- end
- end
-
-// always @(posedge TRACE_CLK) begin
-// if(RST == 1'b1) begin
-// fifo_full_reg <= 1'b0;
-// end
-// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
-// fifo_full_reg <= 1'b1;
-// end
-// else begin
-// fifo_full_reg <= 1'b0;
-// end
-// end
-//
- assign TRACE_DATA_OUT = tom;
-
- assign TRACE_VALID_OUT = fifo_re;
-
-
-
-
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v
deleted file mode 100755
index 8b19a70a2f770ab92d4f4074c8d76057f2510597..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v
+++ /dev/null
@@ -1,244 +0,0 @@
-// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
-// --
-// -- This file contains confidential and proprietary information
-// -- of Xilinx, Inc. and is protected under U.S. and
-// -- international copyright and other intellectual property
-// -- laws.
-// --
-// -- DISCLAIMER
-// -- This disclaimer is not a license and does not grant any
-// -- rights to the materials distributed herewith. Except as
-// -- otherwise provided in a valid license issued to you by
-// -- Xilinx, and to the maximum extent permitted by applicable
-// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// -- (2) Xilinx shall not be liable (whether in contract or tort,
-// -- including negligence, or under any other theory of
-// -- liability) for any loss or damage of any kind or nature
-// -- related to, arising under or in connection with these
-// -- materials, including for any direct, or any indirect,
-// -- special, incidental, or consequential loss or damage
-// -- (including loss of data, profits, goodwill, or any type of
-// -- loss or damage suffered as a result of any action brought
-// -- by a third party) even if such damage or loss was
-// -- reasonably foreseeable or Xilinx had been advised of the
-// -- possibility of the same.
-// --
-// -- CRITICAL APPLICATIONS
-// -- Xilinx products are not designed or intended to be fail-
-// -- safe, or for use in any application requiring fail-safe
-// -- performance, such as life-support or safety devices or
-// -- systems, Class III medical devices, nuclear facilities,
-// -- applications related to the deployment of airbags, or any
-// -- other applications that could lead to death, personal
-// -- injury, or severe property or environmental damage
-// -- (individually and collectively, "Critical
-// -- Applications"). Customer assumes the sole risk and
-// -- liability of any use of Xilinx products in Critical
-// -- Applications, subject only to applicable laws and
-// -- regulations governing limitations on product liability.
-// --
-// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// -- PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// Description: Write Channel for ATC
-//
-//
-// Verilog-standard: Verilog 2001
-//--------------------------------------------------------------------------
-//
-// Structure:
-// w_atc
-//
-//--------------------------------------------------------------------------
-`timescale 1ps/1ps
-
-
-module processing_system7_v5_5_w_atc #
- (
- parameter C_FAMILY = "rtl",
- // FPGA Family. Current version: virtex6, spartan6 or later.
- parameter integer C_AXI_ID_WIDTH = 4,
- // Width of all ID signals on SI and MI side of checker.
- // Range: >= 1.
- parameter integer C_AXI_DATA_WIDTH = 64,
- // Width of all DATA signals on SI and MI side of checker.
- // Range: 64.
- parameter integer C_AXI_WUSER_WIDTH = 1
- // Width of AWUSER signals.
- // Range: >= 1.
- )
- (
- // Global Signals
- input wire ARESET,
- input wire ACLK,
-
- // Command Interface (In)
- input wire cmd_w_valid,
- input wire cmd_w_check,
- input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
- output wire cmd_w_ready,
-
- // Command Interface (Out)
- output wire cmd_b_push,
- output wire cmd_b_error,
- output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
- input wire cmd_b_full,
-
- // Slave Interface Write Port
- input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
- input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
- input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
- input wire S_AXI_WLAST,
- input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
- input wire S_AXI_WVALID,
- output wire S_AXI_WREADY,
-
- // Master Interface Write Address Port
- output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
- output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
- output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
- output wire M_AXI_WLAST,
- output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
- output wire M_AXI_WVALID,
- input wire M_AXI_WREADY
- );
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Local params
- /////////////////////////////////////////////////////////////////////////////
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Variables for generating parameter controlled instances.
- /////////////////////////////////////////////////////////////////////////////
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Functions
- /////////////////////////////////////////////////////////////////////////////
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Internal signals
- /////////////////////////////////////////////////////////////////////////////
-
- // Detecttion.
- wire any_strb_deasserted;
- wire incoming_strb_issue;
- reg first_word;
- reg strb_issue;
-
- // Data flow.
- wire data_pop;
- wire cmd_b_push_blocked;
- reg cmd_b_push_i;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Detect error:
- //
- // Detect and accumulate error when a transaction shall be scanned for
- // potential issues.
- // Accumulation of error is restarted for each ne transaction.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Check stobe information
- assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
- assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
-
- // Keep track of first word in a transaction.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- first_word <= 1'b1;
- end else if ( data_pop ) begin
- first_word <= S_AXI_WLAST;
- end
- end
-
- // Keep track of error status.
- always @ (posedge ACLK) begin
- if (ARESET) begin
- strb_issue <= 1'b0;
- cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
- end else if ( data_pop ) begin
- if ( first_word ) begin
- strb_issue <= incoming_strb_issue;
- end else begin
- strb_issue <= incoming_strb_issue | strb_issue;
- end
- cmd_b_id <= cmd_w_id;
- end
- end
-
- assign cmd_b_error = strb_issue;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Control command queue to B:
- //
- // Push command to B queue when all data for the transaction has flowed
- // through.
- // Delay pipelined command until there is room in the Queue.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Detect when data is popped.
- assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
-
- // Push command when last word in transfered (pipelined).
- always @ (posedge ACLK) begin
- if (ARESET) begin
- cmd_b_push_i <= 1'b0;
- end else begin
- cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
- end
- end
-
- // Detect if pipelined push is blocked.
- assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
-
- // Assign output.
- assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Transaction Throttling:
- //
- // Stall commands if FIFO is full or there is no valid command information
- // from AW.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // Propagate masked valid.
- assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
-
- // Return ready with push back.
- assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
-
- // End of burst.
- assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
-
-
- /////////////////////////////////////////////////////////////////////////////
- // Write propagation:
- //
- // All information is simply forwarded on from the SI- to MI-Side untouched.
- //
- /////////////////////////////////////////////////////////////////////////////
-
- // 1:1 mapping.
- assign M_AXI_WID = S_AXI_WID;
- assign M_AXI_WDATA = S_AXI_WDATA;
- assign M_AXI_WSTRB = S_AXI_WSTRB;
- assign M_AXI_WLAST = S_AXI_WLAST;
- assign M_AXI_WUSER = S_AXI_WUSER;
-
-
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v
deleted file mode 100755
index d6ec7f81931163faff16cfc77a52809fd75115e6..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v
+++ /dev/null
@@ -1,670 +0,0 @@
-// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// axis to vector
-// A generic module to merge all axi signals into one signal called payload.
-// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
-//
-// Verilog-standard: Verilog 2001
-//--------------------------------------------------------------------------
-//
-
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *)
-module axi_infrastructure_v1_1_0_axi2vector #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
- parameter integer C_AXI_PROTOCOL = 0,
- parameter integer C_AXI_ID_WIDTH = 4,
- parameter integer C_AXI_ADDR_WIDTH = 32,
- parameter integer C_AXI_DATA_WIDTH = 32,
- parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
- parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
- parameter integer C_AXI_AWUSER_WIDTH = 1,
- parameter integer C_AXI_WUSER_WIDTH = 1,
- parameter integer C_AXI_BUSER_WIDTH = 1,
- parameter integer C_AXI_ARUSER_WIDTH = 1,
- parameter integer C_AXI_RUSER_WIDTH = 1,
- parameter integer C_AWPAYLOAD_WIDTH = 61,
- parameter integer C_WPAYLOAD_WIDTH = 73,
- parameter integer C_BPAYLOAD_WIDTH = 6,
- parameter integer C_ARPAYLOAD_WIDTH = 61,
- parameter integer C_RPAYLOAD_WIDTH = 69
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
- // Slave Interface Write Address Ports
- input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
- input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
- input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
- input wire [3-1:0] s_axi_awsize,
- input wire [2-1:0] s_axi_awburst,
- input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
- input wire [4-1:0] s_axi_awcache,
- input wire [3-1:0] s_axi_awprot,
- input wire [4-1:0] s_axi_awregion,
- input wire [4-1:0] s_axi_awqos,
- input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
-
- // Slave Interface Write Data Ports
- input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
- input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
- input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
- input wire s_axi_wlast,
- input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
-
- // Slave Interface Write Response Ports
- output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
- output wire [2-1:0] s_axi_bresp,
- output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
-
- // Slave Interface Read Address Ports
- input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
- input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
- input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
- input wire [3-1:0] s_axi_arsize,
- input wire [2-1:0] s_axi_arburst,
- input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
- input wire [4-1:0] s_axi_arcache,
- input wire [3-1:0] s_axi_arprot,
- input wire [4-1:0] s_axi_arregion,
- input wire [4-1:0] s_axi_arqos,
- input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
-
- // Slave Interface Read Data Ports
- output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
- output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
- output wire [2-1:0] s_axi_rresp,
- output wire s_axi_rlast,
- output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
-
- // payloads
- output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
- output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
- input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
- output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
- input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Functions
-////////////////////////////////////////////////////////////////////////////////
-`include "axi_infrastructure_v1_1_0.vh"
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-// AXI4, AXI4LITE, AXI3 packing
-assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
-assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
-
-assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
-assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
-
-assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
-
-assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
-assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
-
-assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
-assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
-
-generate
- if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
- assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
- assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
- assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
- assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
- assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
- assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
- assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
-
- assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
- if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
- assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
- end
- else begin : gen_no_axi3_wid_packing
- end
-
- assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
-
- assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
- assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
- assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
- assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
- assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
- assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
- assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
-
- assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
- assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
-
- if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
- assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
- assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
- end
- else begin : gen_no_region_signals
- end
- if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
- assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
- assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
- assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
- assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
- assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
- end
- else begin : gen_no_user_signals
- assign s_axi_buser = 'b0;
- assign s_axi_ruser = 'b0;
- end
- end
- else begin : gen_axi4lite_packing
- assign s_axi_bid = 'b0;
- assign s_axi_buser = 'b0;
-
- assign s_axi_rlast = 1'b1;
- assign s_axi_rid = 'b0;
- assign s_axi_ruser = 'b0;
- end
-endgenerate
-endmodule
-
-`default_nettype wire
-
-
-// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-// Description: SRL based FIFO for AXIS/AXI Channels.
-//--------------------------------------------------------------------------
-
-
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *)
-module axi_infrastructure_v1_1_0_axic_srl_fifo #(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
- parameter C_FAMILY = "virtex7",
- parameter integer C_PAYLOAD_WIDTH = 1,
- parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
- input wire aclk, // Clock
- input wire aresetn, // Reset
- input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
- input wire s_valid, // Input data valid
- output reg s_ready, // Input data ready
- output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
- output reg m_valid, // Output data valid
- input wire m_ready // Output data ready
-);
-////////////////////////////////////////////////////////////////////////////////
-// Functions
-////////////////////////////////////////////////////////////////////////////////
-// ceiling logb2
-function integer f_clogb2 (input integer size);
- integer s;
- begin
- s = size;
- s = s - 1;
- for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
- s = s >> 1;
- end
-endfunction // clogb2
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
-wire [4-1:0] fifo_addr;
-wire push;
-wire pop ;
-reg areset_r1;
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-always @(posedge aclk) begin
- areset_r1 <= ~aresetn;
-end
-
-always @(posedge aclk) begin
- if (~aresetn) begin
- fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
- end
- else begin
- fifo_index <= push & ~pop ? fifo_index + 1'b1 :
- ~push & pop ? fifo_index - 1'b1 :
- fifo_index;
- end
-end
-
-assign push = s_valid & s_ready;
-
-always @(posedge aclk) begin
- if (~aresetn) begin
- s_ready <= 1'b0;
- end
- else begin
- s_ready <= areset_r1 ? 1'b1 :
- push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
- ~push & pop ? 1'b1 :
- s_ready;
- end
-end
-
-assign pop = m_valid & m_ready;
-
-always @(posedge aclk) begin
- if (~aresetn) begin
- m_valid <= 1'b0;
- end
- else begin
- m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
- push & ~pop ? 1'b1 :
- m_valid;
- end
-end
-
-generate
- if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
- assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
- assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
- end
- else begin : gen_fifo_addr
- assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
- end
-endgenerate
-
-
-generate
- genvar i;
- for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
- SRL16E
- u_srl_fifo(
- .Q ( m_payload[i] ) ,
- .A0 ( fifo_addr[0] ) ,
- .A1 ( fifo_addr[1] ) ,
- .A2 ( fifo_addr[2] ) ,
- .A3 ( fifo_addr[3] ) ,
- .CE ( push ) ,
- .CLK ( aclk ) ,
- .D ( s_payload[i] )
- );
- end
-endgenerate
-
-endmodule
-
-`default_nettype wire
-
-
-// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//-----------------------------------------------------------------------------
-//
-// axi to vector
-// A generic module to merge all axi signals into one signal called payload.
-// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
-//
-// Verilog-standard: Verilog 2001
-//--------------------------------------------------------------------------
-//
-
-`timescale 1ps/1ps
-`default_nettype none
-
-(* DowngradeIPIdentifiedWarnings="yes" *)
-module axi_infrastructure_v1_1_0_vector2axi #
-(
-///////////////////////////////////////////////////////////////////////////////
-// Parameter Definitions
-///////////////////////////////////////////////////////////////////////////////
- parameter integer C_AXI_PROTOCOL = 0,
- parameter integer C_AXI_ID_WIDTH = 4,
- parameter integer C_AXI_ADDR_WIDTH = 32,
- parameter integer C_AXI_DATA_WIDTH = 32,
- parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
- parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
- parameter integer C_AXI_AWUSER_WIDTH = 1,
- parameter integer C_AXI_WUSER_WIDTH = 1,
- parameter integer C_AXI_BUSER_WIDTH = 1,
- parameter integer C_AXI_ARUSER_WIDTH = 1,
- parameter integer C_AXI_RUSER_WIDTH = 1,
- parameter integer C_AWPAYLOAD_WIDTH = 61,
- parameter integer C_WPAYLOAD_WIDTH = 73,
- parameter integer C_BPAYLOAD_WIDTH = 6,
- parameter integer C_ARPAYLOAD_WIDTH = 61,
- parameter integer C_RPAYLOAD_WIDTH = 69
-)
-(
-///////////////////////////////////////////////////////////////////////////////
-// Port Declarations
-///////////////////////////////////////////////////////////////////////////////
- // Slave Interface Write Address Ports
- output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
- output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
- output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
- output wire [3-1:0] m_axi_awsize,
- output wire [2-1:0] m_axi_awburst,
- output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
- output wire [4-1:0] m_axi_awcache,
- output wire [3-1:0] m_axi_awprot,
- output wire [4-1:0] m_axi_awregion,
- output wire [4-1:0] m_axi_awqos,
- output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
-
- // Slave Interface Write Data Ports
- output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
- output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
- output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
- output wire m_axi_wlast,
- output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
-
- // Slave Interface Write Response Ports
- input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
- input wire [2-1:0] m_axi_bresp,
- input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
-
- // Slave Interface Read Address Ports
- output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
- output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
- output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
- output wire [3-1:0] m_axi_arsize,
- output wire [2-1:0] m_axi_arburst,
- output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
- output wire [4-1:0] m_axi_arcache,
- output wire [3-1:0] m_axi_arprot,
- output wire [4-1:0] m_axi_arregion,
- output wire [4-1:0] m_axi_arqos,
- output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
-
- // Slave Interface Read Data Ports
- input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
- input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
- input wire [2-1:0] m_axi_rresp,
- input wire m_axi_rlast,
- input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
-
- // payloads
- input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
- input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
- output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
- input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
- output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
-);
-
-////////////////////////////////////////////////////////////////////////////////
-// Functions
-////////////////////////////////////////////////////////////////////////////////
-`include "axi_infrastructure_v1_1_0.vh"
-
-////////////////////////////////////////////////////////////////////////////////
-// Local parameters
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-// Wires/Reg declarations
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-// BEGIN RTL
-////////////////////////////////////////////////////////////////////////////////
-
-// AXI4, AXI4LITE, AXI3 packing
-assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
-assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
-
-assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
-assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
-
-assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
-
-assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
-assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
-
-assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
-assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
-
-generate
- if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
- assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
- assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
- assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
- assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
- assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
- assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
- assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
-
- assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
- if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
- assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
- end
- else begin : gen_no_axi3_wid_packing
- assign m_axi_wid = 1'b0;
- end
-
- assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
-
- assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
- assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
- assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
- assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
- assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
- assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
- assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
-
- assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
- assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
-
- if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
- assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
- assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
- end
- else begin : gen_no_region_signals
- assign m_axi_awregion = 'b0;
- assign m_axi_arregion = 'b0;
- end
- if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
- assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
- assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
- assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
- assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
- assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
- end
- else begin : gen_no_user_signals
- assign m_axi_awuser = 'b0;
- assign m_axi_wuser = 'b0;
- assign m_axi_aruser = 'b0;
- end
- end
- else begin : gen_axi4lite_packing
- assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
- assign m_axi_awburst = 'b0;
- assign m_axi_awcache = 'b0;
- assign m_axi_awlen = 'b0;
- assign m_axi_awlock = 'b0;
- assign m_axi_awid = 'b0;
- assign m_axi_awqos = 'b0;
-
- assign m_axi_wlast = 1'b1;
- assign m_axi_wid = 'b0;
-
-
- assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
- assign m_axi_arburst = 'b0;
- assign m_axi_arcache = 'b0;
- assign m_axi_arlen = 'b0;
- assign m_axi_arlock = 'b0;
- assign m_axi_arid = 'b0;
- assign m_axi_arqos = 'b0;
-
- assign m_axi_awregion = 'b0;
- assign m_axi_arregion = 'b0;
-
- assign m_axi_awuser = 'b0;
- assign m_axi_wuser = 'b0;
- assign m_axi_aruser = 'b0;
- end
-endgenerate
-endmodule
-
-`default_nettype wire
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
deleted file mode 100644
index bfaf20bedd4a7b48d3cb5c3eb436c07f4a58e10a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
+++ /dev/null
@@ -1,1097 +0,0 @@
-{
- "design": {
- "design_info": {
- "boundary_crc": "0x9BACF2E346C3B3B5",
- "device": "xc7z015clg485-2",
- "name": "scalp_zynqps",
- "synth_flow_mode": "Hierarchical",
- "tool_version": "2019.2",
- "validated": "true"
- },
- "design_tree": {
- "gnd_constant": "",
- "processing_system7_0": "",
- "util_vector_logic_0": "",
- "util_vector_logic_1": "",
- "vio_0": ""
- },
- "interface_ports": {
- "DDR": {
- "mode": "Master",
- "vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
- "parameters": {
- "CAN_DEBUG": {
- "value": "false",
- "value_src": "default"
- },
- "TIMEPERIOD_PS": {
- "value": "1250",
- "value_src": "default"
- },
- "MEMORY_TYPE": {
- "value": "COMPONENTS",
- "value_src": "default"
- },
- "DATA_WIDTH": {
- "value": "8",
- "value_src": "default"
- },
- "CS_ENABLED": {
- "value": "true",
- "value_src": "default"
- },
- "DATA_MASK_ENABLED": {
- "value": "true",
- "value_src": "default"
- },
- "SLOT": {
- "value": "Single",
- "value_src": "default"
- },
- "MEM_ADDR_MAP": {
- "value": "ROW_COLUMN_BANK",
- "value_src": "default"
- },
- "BURST_LENGTH": {
- "value": "8",
- "value_src": "default"
- },
- "AXI_ARBITRATION_SCHEME": {
- "value": "TDM",
- "value_src": "default"
- },
- "CAS_LATENCY": {
- "value": "11",
- "value_src": "default"
- },
- "CAS_WRITE_LATENCY": {
- "value": "11",
- "value_src": "default"
- }
- }
- },
- "FIXED_IO": {
- "mode": "Master",
- "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
- "parameters": {
- "CAN_DEBUG": {
- "value": "false",
- "value_src": "default"
- }
- }
- }
- },
- "ports": {
- "FclkClk0xCO": {
- "type": "clk",
- "direction": "O",
- "parameters": {
- "CLK_DOMAIN": {
- "value": "scalp_zynqps_processing_system7_0_0_FCLK_CLK0",
- "value_src": "default_prop"
- },
- "FREQ_HZ": {
- "value": "125000000"
- },
- "INSERT_VIP": {
- "value": "0",
- "value_src": "default"
- },
- "PHASE": {
- "value": "0.000",
- "value_src": "default"
- }
- }
- },
- "FclkReset0xRO": {
- "direction": "O",
- "left": "0",
- "right": "0"
- },
- "Spi1MOSIxSO": {
- "direction": "O"
- },
- "Spi1SSxSO": {
- "direction": "O"
- },
- "Spi1SclkxCO": {
- "direction": "O"
- },
- "Usb0VBusPwrFaultxSI": {
- "direction": "I"
- }
- },
- "components": {
- "gnd_constant": {
- "vlnv": "xilinx.com:ip:xlconstant:1.1",
- "xci_name": "scalp_zynqps_gnd_constant_0",
- "parameters": {
- "CONST_VAL": {
- "value": "0"
- }
- }
- },
- "processing_system7_0": {
- "vlnv": "xilinx.com:ip:processing_system7:5.5",
- "xci_name": "scalp_zynqps_processing_system7_0_0",
- "parameters": {
- "PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
- "value": "750.000000"
- },
- "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
- "value": "97.222221"
- },
- "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
- "value": "10.204082"
- },
- "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
- "value": "10.000000"
- },
- "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
- "value": "10.000000"
- },
- "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
- "value": "10.000000"
- },
- "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
- "value": "10.000000"
- },
- "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
- "value": "194.444443"
- },
- "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
- "value": "134.615387"
- },
- "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
- "value": "97.222221"
- },
- "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
- "value": "10.000000"
- },
- "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
- "value": "159.090912"
- },
- "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
- "value": "200.000000"
- },
- "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
- "value": "97.222221"
- },
- "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_APU_PERIPHERAL_FREQMHZ": {
- "value": "750"
- },
- "PCW_CAN1_CAN1_IO": {
- "value": "MIO 52 .. 53"
- },
- "PCW_CAN1_GRP_CLK_ENABLE": {
- "value": "0"
- },
- "PCW_CAN1_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_CAN_PERIPHERAL_FREQMHZ": {
- "value": "100"
- },
- "PCW_CAN_PERIPHERAL_VALID": {
- "value": "1"
- },
- "PCW_CLK0_FREQ": {
- "value": "125000000"
- },
- "PCW_CLK1_FREQ": {
- "value": "10000000"
- },
- "PCW_CLK2_FREQ": {
- "value": "10000000"
- },
- "PCW_CLK3_FREQ": {
- "value": "10000000"
- },
- "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": {
- "value": "50"
- },
- "PCW_DDR_RAM_HIGHADDR": {
- "value": "0x0FFFFFFF"
- },
- "PCW_ENET0_ENET0_IO": {
- "value": "MIO 16 .. 27"
- },
- "PCW_ENET0_GRP_MDIO_ENABLE": {
- "value": "0"
- },
- "PCW_ENET0_PERIPHERAL_CLKSRC": {
- "value": "IO PLL"
- },
- "PCW_ENET0_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_ENET0_PERIPHERAL_FREQMHZ": {
- "value": "1000 Mbps"
- },
- "PCW_ENET0_RESET_ENABLE": {
- "value": "0"
- },
- "PCW_ENET_RESET_ENABLE": {
- "value": "1"
- },
- "PCW_ENET_RESET_SELECT": {
- "value": "Share reset pin"
- },
- "PCW_EN_CAN1": {
- "value": "1"
- },
- "PCW_EN_EMIO_CAN1": {
- "value": "0"
- },
- "PCW_EN_EMIO_CD_SDIO1": {
- "value": "0"
- },
- "PCW_EN_EMIO_ENET0": {
- "value": "0"
- },
- "PCW_EN_EMIO_I2C0": {
- "value": "0"
- },
- "PCW_EN_EMIO_SDIO1": {
- "value": "0"
- },
- "PCW_EN_EMIO_SPI0": {
- "value": "0"
- },
- "PCW_EN_EMIO_SPI1": {
- "value": "1"
- },
- "PCW_EN_EMIO_UART0": {
- "value": "0"
- },
- "PCW_EN_EMIO_WP_SDIO1": {
- "value": "0"
- },
- "PCW_EN_ENET0": {
- "value": "1"
- },
- "PCW_EN_GPIO": {
- "value": "1"
- },
- "PCW_EN_I2C0": {
- "value": "1"
- },
- "PCW_EN_QSPI": {
- "value": "1"
- },
- "PCW_EN_SDIO1": {
- "value": "1"
- },
- "PCW_EN_SPI0": {
- "value": "1"
- },
- "PCW_EN_SPI1": {
- "value": "1"
- },
- "PCW_EN_UART0": {
- "value": "1"
- },
- "PCW_EN_UART1": {
- "value": "1"
- },
- "PCW_EN_USB0": {
- "value": "1"
- },
- "PCW_FPGA0_PERIPHERAL_FREQMHZ": {
- "value": "125"
- },
- "PCW_FPGA_FCLK0_ENABLE": {
- "value": "1"
- },
- "PCW_GPIO_MIO_GPIO_ENABLE": {
- "value": "1"
- },
- "PCW_GPIO_MIO_GPIO_IO": {
- "value": "MIO"
- },
- "PCW_I2C0_GRP_INT_ENABLE": {
- "value": "0"
- },
- "PCW_I2C0_I2C0_IO": {
- "value": "MIO 50 .. 51"
- },
- "PCW_I2C0_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_I2C0_RESET_ENABLE": {
- "value": "0"
- },
- "PCW_I2C_PERIPHERAL_FREQMHZ": {
- "value": "125.000000"
- },
- "PCW_I2C_RESET_ENABLE": {
- "value": "1"
- },
- "PCW_I2C_RESET_SELECT": {
- "value": "Share reset pin"
- },
- "PCW_MIO_0_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_0_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_0_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_10_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_10_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_10_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_11_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_11_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_11_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_12_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_12_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_12_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_13_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_13_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_13_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_14_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_14_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_14_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_15_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_15_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_15_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_16_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_16_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_16_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_17_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_17_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_17_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_18_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_18_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_18_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_19_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_19_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_19_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_1_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_1_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_1_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_20_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_20_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_20_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_21_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_21_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_21_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_22_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_22_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_22_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_23_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_23_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_23_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_24_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_24_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_24_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_25_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_25_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_25_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_26_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_26_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_26_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_27_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_27_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_27_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_28_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_28_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_28_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_29_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_29_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_29_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_2_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_2_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_30_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_30_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_30_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_31_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_31_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_31_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_32_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_32_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_32_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_33_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_33_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_33_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_34_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_34_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_34_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_35_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_35_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_35_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_36_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_36_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_36_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_37_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_37_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_37_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_38_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_38_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_38_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_39_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_39_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_39_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_3_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_3_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_40_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_40_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_40_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_41_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_41_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_41_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_42_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_42_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_42_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_43_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_43_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_43_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_44_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_44_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_44_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_45_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_45_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_45_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_46_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_46_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_46_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_47_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_47_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_47_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_48_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_48_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_48_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_49_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_49_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_49_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_4_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_4_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_50_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_50_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_50_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_51_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_51_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_51_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_52_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_52_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_52_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_53_IOTYPE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_MIO_53_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_53_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_5_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_5_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_6_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_6_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_7_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_7_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_8_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_8_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_9_IOTYPE": {
- "value": "LVCMOS 3.3V"
- },
- "PCW_MIO_9_PULLUP": {
- "value": "enabled"
- },
- "PCW_MIO_9_SLEW": {
- "value": "slow"
- },
- "PCW_MIO_TREE_PERIPHERALS": {
- "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#SPI 0#UART 0#UART 0#UART 1#UART 1#I2C 0#I2C 0#CAN 1#CAN 1"
- },
- "PCW_MIO_TREE_SIGNALS": {
- "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx"
- },
- "PCW_PRESET_BANK1_VOLTAGE": {
- "value": "LVCMOS 2.5V"
- },
- "PCW_QSPI_GRP_FBCLK_ENABLE": {
- "value": "0"
- },
- "PCW_QSPI_GRP_IO1_ENABLE": {
- "value": "0"
- },
- "PCW_QSPI_GRP_SINGLE_SS_ENABLE": {
- "value": "1"
- },
- "PCW_QSPI_GRP_SINGLE_SS_IO": {
- "value": "MIO 1 .. 6"
- },
- "PCW_QSPI_GRP_SS1_ENABLE": {
- "value": "0"
- },
- "PCW_QSPI_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_QSPI_PERIPHERAL_FREQMHZ": {
- "value": "133"
- },
- "PCW_QSPI_QSPI_IO": {
- "value": "MIO 1 .. 6"
- },
- "PCW_SD1_GRP_CD_ENABLE": {
- "value": "1"
- },
- "PCW_SD1_GRP_CD_IO": {
- "value": "MIO 9"
- },
- "PCW_SD1_GRP_POW_ENABLE": {
- "value": "0"
- },
- "PCW_SD1_GRP_WP_ENABLE": {
- "value": "0"
- },
- "PCW_SD1_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_SD1_SD1_IO": {
- "value": "MIO 10 .. 15"
- },
- "PCW_SDIO_PERIPHERAL_FREQMHZ": {
- "value": "100"
- },
- "PCW_SDIO_PERIPHERAL_VALID": {
- "value": "1"
- },
- "PCW_SINGLE_QSPI_DATA_MODE": {
- "value": "x4"
- },
- "PCW_SPI0_GRP_SS1_ENABLE": {
- "value": "0"
- },
- "PCW_SPI0_GRP_SS2_ENABLE": {
- "value": "0"
- },
- "PCW_SPI0_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_SPI0_SPI0_IO": {
- "value": "MIO 40 .. 45"
- },
- "PCW_SPI1_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_SPI1_SPI1_IO": {
- "value": "EMIO"
- },
- "PCW_SPI_PERIPHERAL_FREQMHZ": {
- "value": "166.666666"
- },
- "PCW_SPI_PERIPHERAL_VALID": {
- "value": "1"
- },
- "PCW_UART0_GRP_FULL_ENABLE": {
- "value": "0"
- },
- "PCW_UART0_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_UART0_UART0_IO": {
- "value": "MIO 46 .. 47"
- },
- "PCW_UART1_GRP_FULL_ENABLE": {
- "value": "0"
- },
- "PCW_UART1_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_UART1_UART1_IO": {
- "value": "MIO 48 .. 49"
- },
- "PCW_UART_PERIPHERAL_FREQMHZ": {
- "value": "100"
- },
- "PCW_UART_PERIPHERAL_VALID": {
- "value": "1"
- },
- "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
- "value": "500.000000"
- },
- "PCW_UIPARAM_DDR_BL": {
- "value": "8"
- },
- "PCW_UIPARAM_DDR_BUS_WIDTH": {
- "value": "16 Bit"
- },
- "PCW_UIPARAM_DDR_ECC": {
- "value": "Disabled"
- },
- "PCW_UIPARAM_DDR_FREQ_MHZ": {
- "value": "500"
- },
- "PCW_UIPARAM_DDR_MEMORY_TYPE": {
- "value": "DDR 3 (Low Voltage)"
- },
- "PCW_UIPARAM_DDR_PARTNO": {
- "value": "MT41K128M16 JT-125"
- },
- "PCW_USB0_PERIPHERAL_ENABLE": {
- "value": "1"
- },
- "PCW_USB0_RESET_ENABLE": {
- "value": "0"
- },
- "PCW_USB0_USB0_IO": {
- "value": "MIO 28 .. 39"
- },
- "PCW_USB_RESET_ENABLE": {
- "value": "1"
- },
- "PCW_USB_RESET_SELECT": {
- "value": "Share reset pin"
- }
- }
- },
- "util_vector_logic_0": {
- "vlnv": "xilinx.com:ip:util_vector_logic:2.0",
- "xci_name": "scalp_zynqps_util_vector_logic_0_0",
- "parameters": {
- "C_OPERATION": {
- "value": "or"
- },
- "C_SIZE": {
- "value": "1"
- }
- }
- },
- "util_vector_logic_1": {
- "vlnv": "xilinx.com:ip:util_vector_logic:2.0",
- "xci_name": "scalp_zynqps_util_vector_logic_1_0",
- "parameters": {
- "C_OPERATION": {
- "value": "not"
- },
- "C_SIZE": {
- "value": "1"
- }
- }
- },
- "vio_0": {
- "vlnv": "xilinx.com:ip:vio:3.0",
- "xci_name": "scalp_zynqps_vio_0_0",
- "parameters": {
- "C_NUM_PROBE_IN": {
- "value": "0"
- }
- }
- }
- },
- "interface_nets": {
- "processing_system7_0_FIXED_IO": {
- "interface_ports": [
- "FIXED_IO",
- "processing_system7_0/FIXED_IO"
- ]
- },
- "processing_system7_0_DDR": {
- "interface_ports": [
- "DDR",
- "processing_system7_0/DDR"
- ]
- }
- },
- "nets": {
- "USB0_VBUS_PWRFAULT_0_1": {
- "ports": [
- "Usb0VBusPwrFaultxSI",
- "processing_system7_0/USB0_VBUS_PWRFAULT"
- ]
- },
- "gnd_constant_dout": {
- "ports": [
- "gnd_constant/dout",
- "processing_system7_0/SPI1_MISO_I",
- "processing_system7_0/SPI1_MOSI_I",
- "processing_system7_0/SPI1_SCLK_I",
- "processing_system7_0/SPI1_SS_I"
- ]
- },
- "processing_system7_0_FCLK_CLK0": {
- "ports": [
- "processing_system7_0/FCLK_CLK0",
- "FclkClk0xCO",
- "processing_system7_0/M_AXI_GP0_ACLK",
- "vio_0/clk"
- ]
- },
- "processing_system7_0_FCLK_RESET0_N": {
- "ports": [
- "processing_system7_0/FCLK_RESET0_N",
- "util_vector_logic_1/Op1"
- ]
- },
- "processing_system7_0_SPI1_MOSI_O": {
- "ports": [
- "processing_system7_0/SPI1_MOSI_O",
- "Spi1MOSIxSO"
- ]
- },
- "processing_system7_0_SPI1_SCLK_O": {
- "ports": [
- "processing_system7_0/SPI1_SCLK_O",
- "Spi1SclkxCO"
- ]
- },
- "processing_system7_0_SPI1_SS_O": {
- "ports": [
- "processing_system7_0/SPI1_SS_O",
- "Spi1SSxSO"
- ]
- },
- "util_vector_logic_0_Res": {
- "ports": [
- "util_vector_logic_0/Res",
- "FclkReset0xRO"
- ]
- },
- "util_vector_logic_1_Res": {
- "ports": [
- "util_vector_logic_1/Res",
- "util_vector_logic_0/Op1"
- ]
- },
- "vio_0_probe_out0": {
- "ports": [
- "vio_0/probe_out0",
- "util_vector_logic_0/Op2"
- ]
- }
- },
- "addressing": {
- "/processing_system7_0": {
- "address_spaces": {
- "Data": {
- "range": "4G",
- "width": "32"
- }
- }
- }
- }
- }
-}
\ No newline at end of file
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml
deleted file mode 100644
index 3726baf6541a38bbcbd5835124624702a7831f5e..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml
+++ /dev/null
@@ -1,89 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Root MajorVersion="0" MinorVersion="39">
- <CompositeFile CompositeFileTopName="scalp_zynqps" CanBeSetAsTop="false" CanDisplayChildGraph="true">
- <Description>Composite Fileset</Description>
- <Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1599472369"/>
- <Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1599472369"/>
- <Generation Name="SIMULATION" State="GENERATED" Timestamp="1599472369"/>
- <Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1599472369"/>
- <FileCollection Name="SOURCES" Type="SOURCES">
- <File Name="ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xci" Type="IP">
- <Instance HierarchyPath="gnd_constant"/>
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SYNTHESIS"/>
- <UsedIn Val="IMPLEMENTATION"/>
- <UsedIn Val="SIMULATION"/>
- </File>
- <File Name="ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci" Type="IP">
- <Instance HierarchyPath="processing_system7_0"/>
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SYNTHESIS"/>
- <UsedIn Val="IMPLEMENTATION"/>
- <UsedIn Val="SIMULATION"/>
- </File>
- <File Name="ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci" Type="IP">
- <Instance HierarchyPath="util_vector_logic_0"/>
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SYNTHESIS"/>
- <UsedIn Val="IMPLEMENTATION"/>
- <UsedIn Val="SIMULATION"/>
- </File>
- <File Name="ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci" Type="IP">
- <Instance HierarchyPath="util_vector_logic_1"/>
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SYNTHESIS"/>
- <UsedIn Val="IMPLEMENTATION"/>
- <UsedIn Val="SIMULATION"/>
- </File>
- <File Name="ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci" Type="IP">
- <Instance HierarchyPath="vio_0"/>
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SYNTHESIS"/>
- <UsedIn Val="IMPLEMENTATION"/>
- <UsedIn Val="SIMULATION"/>
- </File>
- <File Name="synth/scalp_zynqps.vhd" Type="VHDL">
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SYNTHESIS"/>
- </File>
- <File Name="sim/scalp_zynqps.vhd" Type="VHDL">
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SIMULATION"/>
- </File>
- <File Name="scalp_zynqps_ooc.xdc" Type="XDC">
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SYNTHESIS"/>
- <UsedIn Val="IMPLEMENTATION"/>
- <UsedIn Val="OUT_OF_CONTEXT"/>
- </File>
- <File Name="hw_handoff/scalp_zynqps.hwh" Type="HwHandoff">
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="HW_HANDOFF"/>
- </File>
- <File Name="hw_handoff/scalp_zynqps_bd.tcl">
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="HW_HANDOFF"/>
- </File>
- <File Name="synth/scalp_zynqps.hwdef">
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="HW_HANDOFF"/>
- </File>
- <File Name="sim/scalp_zynqps.protoinst">
- <Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
- <Library Name="xil_defaultlib"/>
- <UsedIn Val="SIMULATION"/>
- </File>
- </FileCollection>
- </CompositeFile>
-</Root>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps_ooc.xdc b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps_ooc.xdc
deleted file mode 100644
index cd83b08a4d8a914bd173a0134a0a629678b03073..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps_ooc.xdc
+++ /dev/null
@@ -1,11 +0,0 @@
-################################################################################
-
-# This XDC is used only for OOC mode of synthesis, implementation
-# This constraints file contains default clock frequencies to be used during
-# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
-# This constraints file is not used in normal top-down synthesis (default flow
-# of Vivado)
-################################################################################
-create_clock -name processing_system7_0_FCLK_CLK0 -period 8 [get_pins processing_system7_0/FCLK_CLK0]
-
-################################################################################
\ No newline at end of file
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/sim/scalp_zynqps.vhd b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/sim/scalp_zynqps.vhd
deleted file mode 100644
index 2212d122492ba735c98d6a85a186e7a8e2712748..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/sim/scalp_zynqps.vhd
+++ /dev/null
@@ -1,361 +0,0 @@
---Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
---Date : Mon Sep 7 11:52:31 2020
---Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
---Command : generate_target scalp_zynqps.bd
---Design : scalp_zynqps
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity scalp_zynqps is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC;
- FclkClk0xCO : out STD_LOGIC;
- FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
- Spi1MOSIxSO : out STD_LOGIC;
- Spi1SSxSO : out STD_LOGIC;
- Spi1SclkxCO : out STD_LOGIC;
- Usb0VBusPwrFaultxSI : in STD_LOGIC
- );
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of scalp_zynqps : entity is "scalp_zynqps,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=scalp_zynqps,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
- attribute HW_HANDOFF : string;
- attribute HW_HANDOFF of scalp_zynqps : entity is "scalp_zynqps.hwdef";
-end scalp_zynqps;
-
-architecture STRUCTURE of scalp_zynqps is
- component scalp_zynqps_gnd_constant_0 is
- port (
- dout : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_gnd_constant_0;
- component scalp_zynqps_processing_system7_0_0 is
- port (
- SPI1_SCLK_I : in STD_LOGIC;
- SPI1_SCLK_O : out STD_LOGIC;
- SPI1_SCLK_T : out STD_LOGIC;
- SPI1_MOSI_I : in STD_LOGIC;
- SPI1_MOSI_O : out STD_LOGIC;
- SPI1_MOSI_T : out STD_LOGIC;
- SPI1_MISO_I : in STD_LOGIC;
- SPI1_MISO_O : out STD_LOGIC;
- SPI1_MISO_T : out STD_LOGIC;
- SPI1_SS_I : in STD_LOGIC;
- SPI1_SS_O : out STD_LOGIC;
- SPI1_SS1_O : out STD_LOGIC;
- SPI1_SS2_O : out STD_LOGIC;
- SPI1_SS_T : out STD_LOGIC;
- USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
- USB0_VBUS_PWRSELECT : out STD_LOGIC;
- USB0_VBUS_PWRFAULT : in STD_LOGIC;
- M_AXI_GP0_ARVALID : out STD_LOGIC;
- M_AXI_GP0_AWVALID : out STD_LOGIC;
- M_AXI_GP0_BREADY : out STD_LOGIC;
- M_AXI_GP0_RREADY : out STD_LOGIC;
- M_AXI_GP0_WLAST : out STD_LOGIC;
- M_AXI_GP0_WVALID : out STD_LOGIC;
- M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ACLK : in STD_LOGIC;
- M_AXI_GP0_ARREADY : in STD_LOGIC;
- M_AXI_GP0_AWREADY : in STD_LOGIC;
- M_AXI_GP0_BVALID : in STD_LOGIC;
- M_AXI_GP0_RLAST : in STD_LOGIC;
- M_AXI_GP0_RVALID : in STD_LOGIC;
- M_AXI_GP0_WREADY : in STD_LOGIC;
- M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- FCLK_CLK0 : out STD_LOGIC;
- FCLK_RESET0_N : out STD_LOGIC;
- MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- DDR_CAS_n : inout STD_LOGIC;
- DDR_CKE : inout STD_LOGIC;
- DDR_Clk_n : inout STD_LOGIC;
- DDR_Clk : inout STD_LOGIC;
- DDR_CS_n : inout STD_LOGIC;
- DDR_DRSTB : inout STD_LOGIC;
- DDR_ODT : inout STD_LOGIC;
- DDR_RAS_n : inout STD_LOGIC;
- DDR_WEB : inout STD_LOGIC;
- DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_VRN : inout STD_LOGIC;
- DDR_VRP : inout STD_LOGIC;
- DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- PS_SRSTB : inout STD_LOGIC;
- PS_CLK : inout STD_LOGIC;
- PS_PORB : inout STD_LOGIC
- );
- end component scalp_zynqps_processing_system7_0_0;
- component scalp_zynqps_util_vector_logic_0_0 is
- port (
- Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Res : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_util_vector_logic_0_0;
- component scalp_zynqps_util_vector_logic_1_0 is
- port (
- Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Res : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_util_vector_logic_1_0;
- component scalp_zynqps_vio_0_0 is
- port (
- clk : in STD_LOGIC;
- probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_vio_0_0;
- signal USB0_VBUS_PWRFAULT_0_1 : STD_LOGIC;
- signal gnd_constant_dout : STD_LOGIC_VECTOR ( 0 to 0 );
- signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_CKE : STD_LOGIC;
- signal processing_system7_0_DDR_CK_N : STD_LOGIC;
- signal processing_system7_0_DDR_CK_P : STD_LOGIC;
- signal processing_system7_0_DDR_CS_N : STD_LOGIC;
- signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_ODT : STD_LOGIC;
- signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
- signal processing_system7_0_DDR_WE_N : STD_LOGIC;
- signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
- signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
- signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
- signal processing_system7_0_SPI1_MOSI_O : STD_LOGIC;
- signal processing_system7_0_SPI1_SCLK_O : STD_LOGIC;
- signal processing_system7_0_SPI1_SS_O : STD_LOGIC;
- signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
- signal util_vector_logic_1_Res : STD_LOGIC_VECTOR ( 0 to 0 );
- signal vio_0_probe_out0 : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute X_INTERFACE_INFO : string;
- attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
- attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
- attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
- attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
- attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
- attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
- attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
- attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
- attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
- attribute X_INTERFACE_PARAMETER : string;
- attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
- attribute X_INTERFACE_INFO of FclkClk0xCO : signal is "xilinx.com:signal:clock:1.0 CLK.FCLKCLK0XCO CLK";
- attribute X_INTERFACE_PARAMETER of FclkClk0xCO : signal is "XIL_INTERFACENAME CLK.FCLKCLK0XCO, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, FREQ_HZ 125000000, INSERT_VIP 0, PHASE 0.000";
- attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
- attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
- attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
- attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
- attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
- attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
- attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
- attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
-begin
- FclkClk0xCO <= processing_system7_0_FCLK_CLK0;
- FclkReset0xRO(0) <= util_vector_logic_0_Res(0);
- Spi1MOSIxSO <= processing_system7_0_SPI1_MOSI_O;
- Spi1SSxSO <= processing_system7_0_SPI1_SS_O;
- Spi1SclkxCO <= processing_system7_0_SPI1_SCLK_O;
- USB0_VBUS_PWRFAULT_0_1 <= Usb0VBusPwrFaultxSI;
-gnd_constant: component scalp_zynqps_gnd_constant_0
- port map (
- dout(0) => gnd_constant_dout(0)
- );
-processing_system7_0: component scalp_zynqps_processing_system7_0_0
- port map (
- DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
- DDR_CAS_n => DDR_cas_n,
- DDR_CKE => DDR_cke,
- DDR_CS_n => DDR_cs_n,
- DDR_Clk => DDR_ck_p,
- DDR_Clk_n => DDR_ck_n,
- DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
- DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
- DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_DRSTB => DDR_reset_n,
- DDR_ODT => DDR_odt,
- DDR_RAS_n => DDR_ras_n,
- DDR_VRN => FIXED_IO_ddr_vrn,
- DDR_VRP => FIXED_IO_ddr_vrp,
- DDR_WEB => DDR_we_n,
- FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
- FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
- MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
- M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
- M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
- M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
- M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
- M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
- M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARREADY => '0',
- M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
- M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
- M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
- M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
- M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
- M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
- M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWREADY => '0',
- M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
- M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
- M_AXI_GP0_BID(11 downto 0) => B"000000000000",
- M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
- M_AXI_GP0_BRESP(1 downto 0) => B"00",
- M_AXI_GP0_BVALID => '0',
- M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
- M_AXI_GP0_RID(11 downto 0) => B"000000000000",
- M_AXI_GP0_RLAST => '0',
- M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
- M_AXI_GP0_RRESP(1 downto 0) => B"00",
- M_AXI_GP0_RVALID => '0',
- M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
- M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
- M_AXI_GP0_WREADY => '0',
- M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
- M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
- PS_CLK => FIXED_IO_ps_clk,
- PS_PORB => FIXED_IO_ps_porb,
- PS_SRSTB => FIXED_IO_ps_srstb,
- SPI1_MISO_I => gnd_constant_dout(0),
- SPI1_MISO_O => NLW_processing_system7_0_SPI1_MISO_O_UNCONNECTED,
- SPI1_MISO_T => NLW_processing_system7_0_SPI1_MISO_T_UNCONNECTED,
- SPI1_MOSI_I => gnd_constant_dout(0),
- SPI1_MOSI_O => processing_system7_0_SPI1_MOSI_O,
- SPI1_MOSI_T => NLW_processing_system7_0_SPI1_MOSI_T_UNCONNECTED,
- SPI1_SCLK_I => gnd_constant_dout(0),
- SPI1_SCLK_O => processing_system7_0_SPI1_SCLK_O,
- SPI1_SCLK_T => NLW_processing_system7_0_SPI1_SCLK_T_UNCONNECTED,
- SPI1_SS1_O => NLW_processing_system7_0_SPI1_SS1_O_UNCONNECTED,
- SPI1_SS2_O => NLW_processing_system7_0_SPI1_SS2_O_UNCONNECTED,
- SPI1_SS_I => gnd_constant_dout(0),
- SPI1_SS_O => processing_system7_0_SPI1_SS_O,
- SPI1_SS_T => NLW_processing_system7_0_SPI1_SS_T_UNCONNECTED,
- USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
- USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT_0_1,
- USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
- );
-util_vector_logic_0: component scalp_zynqps_util_vector_logic_0_0
- port map (
- Op1(0) => util_vector_logic_1_Res(0),
- Op2(0) => vio_0_probe_out0(0),
- Res(0) => util_vector_logic_0_Res(0)
- );
-util_vector_logic_1: component scalp_zynqps_util_vector_logic_1_0
- port map (
- Op1(0) => processing_system7_0_FCLK_RESET0_N,
- Res(0) => util_vector_logic_1_Res(0)
- );
-vio_0: component scalp_zynqps_vio_0_0
- port map (
- clk => processing_system7_0_FCLK_CLK0,
- probe_out0(0) => vio_0_probe_out0(0)
- );
-end STRUCTURE;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd
deleted file mode 100644
index 2212d122492ba735c98d6a85a186e7a8e2712748..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd
+++ /dev/null
@@ -1,361 +0,0 @@
---Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
---Date : Mon Sep 7 11:52:31 2020
---Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
---Command : generate_target scalp_zynqps.bd
---Design : scalp_zynqps
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity scalp_zynqps is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC;
- FclkClk0xCO : out STD_LOGIC;
- FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
- Spi1MOSIxSO : out STD_LOGIC;
- Spi1SSxSO : out STD_LOGIC;
- Spi1SclkxCO : out STD_LOGIC;
- Usb0VBusPwrFaultxSI : in STD_LOGIC
- );
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of scalp_zynqps : entity is "scalp_zynqps,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=scalp_zynqps,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
- attribute HW_HANDOFF : string;
- attribute HW_HANDOFF of scalp_zynqps : entity is "scalp_zynqps.hwdef";
-end scalp_zynqps;
-
-architecture STRUCTURE of scalp_zynqps is
- component scalp_zynqps_gnd_constant_0 is
- port (
- dout : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_gnd_constant_0;
- component scalp_zynqps_processing_system7_0_0 is
- port (
- SPI1_SCLK_I : in STD_LOGIC;
- SPI1_SCLK_O : out STD_LOGIC;
- SPI1_SCLK_T : out STD_LOGIC;
- SPI1_MOSI_I : in STD_LOGIC;
- SPI1_MOSI_O : out STD_LOGIC;
- SPI1_MOSI_T : out STD_LOGIC;
- SPI1_MISO_I : in STD_LOGIC;
- SPI1_MISO_O : out STD_LOGIC;
- SPI1_MISO_T : out STD_LOGIC;
- SPI1_SS_I : in STD_LOGIC;
- SPI1_SS_O : out STD_LOGIC;
- SPI1_SS1_O : out STD_LOGIC;
- SPI1_SS2_O : out STD_LOGIC;
- SPI1_SS_T : out STD_LOGIC;
- USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
- USB0_VBUS_PWRSELECT : out STD_LOGIC;
- USB0_VBUS_PWRFAULT : in STD_LOGIC;
- M_AXI_GP0_ARVALID : out STD_LOGIC;
- M_AXI_GP0_AWVALID : out STD_LOGIC;
- M_AXI_GP0_BREADY : out STD_LOGIC;
- M_AXI_GP0_RREADY : out STD_LOGIC;
- M_AXI_GP0_WLAST : out STD_LOGIC;
- M_AXI_GP0_WVALID : out STD_LOGIC;
- M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ACLK : in STD_LOGIC;
- M_AXI_GP0_ARREADY : in STD_LOGIC;
- M_AXI_GP0_AWREADY : in STD_LOGIC;
- M_AXI_GP0_BVALID : in STD_LOGIC;
- M_AXI_GP0_RLAST : in STD_LOGIC;
- M_AXI_GP0_RVALID : in STD_LOGIC;
- M_AXI_GP0_WREADY : in STD_LOGIC;
- M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- FCLK_CLK0 : out STD_LOGIC;
- FCLK_RESET0_N : out STD_LOGIC;
- MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- DDR_CAS_n : inout STD_LOGIC;
- DDR_CKE : inout STD_LOGIC;
- DDR_Clk_n : inout STD_LOGIC;
- DDR_Clk : inout STD_LOGIC;
- DDR_CS_n : inout STD_LOGIC;
- DDR_DRSTB : inout STD_LOGIC;
- DDR_ODT : inout STD_LOGIC;
- DDR_RAS_n : inout STD_LOGIC;
- DDR_WEB : inout STD_LOGIC;
- DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_VRN : inout STD_LOGIC;
- DDR_VRP : inout STD_LOGIC;
- DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- PS_SRSTB : inout STD_LOGIC;
- PS_CLK : inout STD_LOGIC;
- PS_PORB : inout STD_LOGIC
- );
- end component scalp_zynqps_processing_system7_0_0;
- component scalp_zynqps_util_vector_logic_0_0 is
- port (
- Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Res : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_util_vector_logic_0_0;
- component scalp_zynqps_util_vector_logic_1_0 is
- port (
- Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Res : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_util_vector_logic_1_0;
- component scalp_zynqps_vio_0_0 is
- port (
- clk : in STD_LOGIC;
- probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_vio_0_0;
- signal USB0_VBUS_PWRFAULT_0_1 : STD_LOGIC;
- signal gnd_constant_dout : STD_LOGIC_VECTOR ( 0 to 0 );
- signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_CKE : STD_LOGIC;
- signal processing_system7_0_DDR_CK_N : STD_LOGIC;
- signal processing_system7_0_DDR_CK_P : STD_LOGIC;
- signal processing_system7_0_DDR_CS_N : STD_LOGIC;
- signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_ODT : STD_LOGIC;
- signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
- signal processing_system7_0_DDR_WE_N : STD_LOGIC;
- signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
- signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
- signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
- signal processing_system7_0_SPI1_MOSI_O : STD_LOGIC;
- signal processing_system7_0_SPI1_SCLK_O : STD_LOGIC;
- signal processing_system7_0_SPI1_SS_O : STD_LOGIC;
- signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
- signal util_vector_logic_1_Res : STD_LOGIC_VECTOR ( 0 to 0 );
- signal vio_0_probe_out0 : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute X_INTERFACE_INFO : string;
- attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
- attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
- attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
- attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
- attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
- attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
- attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
- attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
- attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
- attribute X_INTERFACE_PARAMETER : string;
- attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
- attribute X_INTERFACE_INFO of FclkClk0xCO : signal is "xilinx.com:signal:clock:1.0 CLK.FCLKCLK0XCO CLK";
- attribute X_INTERFACE_PARAMETER of FclkClk0xCO : signal is "XIL_INTERFACENAME CLK.FCLKCLK0XCO, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, FREQ_HZ 125000000, INSERT_VIP 0, PHASE 0.000";
- attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
- attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
- attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
- attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
- attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
- attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
- attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
- attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
-begin
- FclkClk0xCO <= processing_system7_0_FCLK_CLK0;
- FclkReset0xRO(0) <= util_vector_logic_0_Res(0);
- Spi1MOSIxSO <= processing_system7_0_SPI1_MOSI_O;
- Spi1SSxSO <= processing_system7_0_SPI1_SS_O;
- Spi1SclkxCO <= processing_system7_0_SPI1_SCLK_O;
- USB0_VBUS_PWRFAULT_0_1 <= Usb0VBusPwrFaultxSI;
-gnd_constant: component scalp_zynqps_gnd_constant_0
- port map (
- dout(0) => gnd_constant_dout(0)
- );
-processing_system7_0: component scalp_zynqps_processing_system7_0_0
- port map (
- DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
- DDR_CAS_n => DDR_cas_n,
- DDR_CKE => DDR_cke,
- DDR_CS_n => DDR_cs_n,
- DDR_Clk => DDR_ck_p,
- DDR_Clk_n => DDR_ck_n,
- DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
- DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
- DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_DRSTB => DDR_reset_n,
- DDR_ODT => DDR_odt,
- DDR_RAS_n => DDR_ras_n,
- DDR_VRN => FIXED_IO_ddr_vrn,
- DDR_VRP => FIXED_IO_ddr_vrp,
- DDR_WEB => DDR_we_n,
- FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
- FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
- MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
- M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
- M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
- M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
- M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
- M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
- M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARREADY => '0',
- M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
- M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
- M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
- M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
- M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
- M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
- M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWREADY => '0',
- M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
- M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
- M_AXI_GP0_BID(11 downto 0) => B"000000000000",
- M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
- M_AXI_GP0_BRESP(1 downto 0) => B"00",
- M_AXI_GP0_BVALID => '0',
- M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
- M_AXI_GP0_RID(11 downto 0) => B"000000000000",
- M_AXI_GP0_RLAST => '0',
- M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
- M_AXI_GP0_RRESP(1 downto 0) => B"00",
- M_AXI_GP0_RVALID => '0',
- M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
- M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
- M_AXI_GP0_WREADY => '0',
- M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
- M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
- PS_CLK => FIXED_IO_ps_clk,
- PS_PORB => FIXED_IO_ps_porb,
- PS_SRSTB => FIXED_IO_ps_srstb,
- SPI1_MISO_I => gnd_constant_dout(0),
- SPI1_MISO_O => NLW_processing_system7_0_SPI1_MISO_O_UNCONNECTED,
- SPI1_MISO_T => NLW_processing_system7_0_SPI1_MISO_T_UNCONNECTED,
- SPI1_MOSI_I => gnd_constant_dout(0),
- SPI1_MOSI_O => processing_system7_0_SPI1_MOSI_O,
- SPI1_MOSI_T => NLW_processing_system7_0_SPI1_MOSI_T_UNCONNECTED,
- SPI1_SCLK_I => gnd_constant_dout(0),
- SPI1_SCLK_O => processing_system7_0_SPI1_SCLK_O,
- SPI1_SCLK_T => NLW_processing_system7_0_SPI1_SCLK_T_UNCONNECTED,
- SPI1_SS1_O => NLW_processing_system7_0_SPI1_SS1_O_UNCONNECTED,
- SPI1_SS2_O => NLW_processing_system7_0_SPI1_SS2_O_UNCONNECTED,
- SPI1_SS_I => gnd_constant_dout(0),
- SPI1_SS_O => processing_system7_0_SPI1_SS_O,
- SPI1_SS_T => NLW_processing_system7_0_SPI1_SS_T_UNCONNECTED,
- USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
- USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT_0_1,
- USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
- );
-util_vector_logic_0: component scalp_zynqps_util_vector_logic_0_0
- port map (
- Op1(0) => util_vector_logic_1_Res(0),
- Op2(0) => vio_0_probe_out0(0),
- Res(0) => util_vector_logic_0_Res(0)
- );
-util_vector_logic_1: component scalp_zynqps_util_vector_logic_1_0
- port map (
- Op1(0) => processing_system7_0_FCLK_RESET0_N,
- Res(0) => util_vector_logic_1_Res(0)
- );
-vio_0: component scalp_zynqps_vio_0_0
- port map (
- clk => processing_system7_0_FCLK_CLK0,
- probe_out0(0) => vio_0_probe_out0(0)
- );
-end STRUCTURE;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui b/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui
deleted file mode 100644
index e0744ffe19a6afefc30d28812f3a39e207187900..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui
+++ /dev/null
@@ -1,37 +0,0 @@
-{
- "ActiveEmotionalView":"Default View",
- "Default View_ScaleFactor":"0.748649",
- "Default View_TopLeft":"-383,-9",
- "ExpandedHierarchyInLayout":"",
- "guistr":"# # String gsaved with Nlview 7.0.21 2019-05-29 bk=1.5064 VDI=41 GEI=36 GUI=JA:9.0 TLS
-# -string -flagsOSRD
-preplace port DDR -pg 1 -lvl 3 -x 840 -y 50 -defaultsOSRD
-preplace port FIXED_IO -pg 1 -lvl 3 -x 840 -y 70 -defaultsOSRD
-preplace port FclkClk0xCO -pg 1 -lvl 3 -x 840 -y 310 -defaultsOSRD
-preplace port Spi1MOSIxSO -pg 1 -lvl 3 -x 840 -y 170 -defaultsOSRD
-preplace port Spi1SSxSO -pg 1 -lvl 3 -x 840 -y 230 -defaultsOSRD
-preplace port Spi1SclkxCO -pg 1 -lvl 3 -x 840 -y 130 -defaultsOSRD
-preplace port Usb0VBusPwrFaultxSI -pg 1 -lvl 0 -x -10 -y 500 -defaultsOSRD
-preplace portBus FclkReset0xRO -pg 1 -lvl 3 -x 840 -y 580 -defaultsOSRD
-preplace inst gnd_constant -pg 1 -lvl 2 -x 560 -y 430 -defaultsOSRD
-preplace inst processing_system7_0 -pg 1 -lvl 2 -x 560 -y 190 -defaultsOSRD
-preplace inst util_vector_logic_0 -pg 1 -lvl 2 -x 560 -y 580 -defaultsOSRD
-preplace inst util_vector_logic_1 -pg 1 -lvl 1 -x 180 -y 570 -defaultsOSRD
-preplace inst vio_0 -pg 1 -lvl 1 -x 180 -y 670 -defaultsOSRD
-preplace netloc USB0_VBUS_PWRFAULT_0_1 1 0 3 10J 490 NJ 490 800
-preplace netloc gnd_constant_dout 1 2 1 810 110n
-preplace netloc processing_system7_0_FCLK_CLK0 1 0 3 20 500 330 500 820
-preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 3 30 510 NJ 510 790
-preplace netloc processing_system7_0_SPI1_MOSI_O 1 2 1 NJ 170
-preplace netloc processing_system7_0_SPI1_SCLK_O 1 2 1 NJ 130
-preplace netloc processing_system7_0_SPI1_SS_O 1 2 1 NJ 230
-preplace netloc util_vector_logic_0_Res 1 2 1 NJ 580
-preplace netloc util_vector_logic_1_Res 1 1 1 NJ 570
-preplace netloc vio_0_probe_out0 1 1 1 330J 590n
-preplace netloc processing_system7_0_FIXED_IO 1 2 1 NJ 70
-preplace netloc processing_system7_0_DDR 1 2 1 NJ 50
-levelinfo -pg 1 -10 180 560 840
-pagesize -pg 1 -db -bbox -sgen -220 -10 1040 730
-"
-}
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/0e76e0055f23d5f9.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/0e76e0055f23d5f9.xci
deleted file mode 100644
index d3d445137dc256f45fb2e66b38d634f4a0824a7f..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/0e76e0055f23d5f9.xci
+++ /dev/null
@@ -1,40 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>ipcache</spirit:library>
- <spirit:name>0e76e0055f23d5f9</spirit:name>
- <spirit:version>0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>scalp_zynqps_util_vector_logic_1_0</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_vector_logic" spirit:version="2.0"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPERATION">not</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">scalp_zynqps_util_vector_logic_1_0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOGO_FILE">data/sym_notgate.png</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">0e76e0055f23d5f9</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">234</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0.dcp
deleted file mode 100644
index 4b62257945b7aa01879d5ce36e88920bfc8d3a50..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
deleted file mode 100755
index 11f053403b576c568eb427a0f525854b022dbdaa..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
+++ /dev/null
@@ -1,101 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:28 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
-// Design : scalp_zynqps_util_vector_logic_1_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_util_vector_logic_1_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
- (Op1,
- Res);
- input [0:0]Op1;
- output [0:0]Res;
-
- wire [0:0]Op1;
- wire [0:0]Res;
-
- LUT1 #(
- .INIT(2'h1))
- \Res[0]_INST_0
- (.I0(Op1),
- .O(Res));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0_stub.v
deleted file mode 100755
index 3e83b10151aea68258769bf8fb642f3085b2b914..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/0e76e0055f23d5f9/scalp_zynqps_util_vector_logic_1_0_stub.v
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:28 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_1_0_stub.v
-// Design : scalp_zynqps_util_vector_logic_1_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Op1, Res)
-/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Res[0:0]" */;
- input [0:0]Op1;
- output [0:0]Res;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/2e46931808b7c212.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/2e46931808b7c212.xci
deleted file mode 100644
index ff18a3b2360f1bb70e1b381378a557ed03add125..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/2e46931808b7c212.xci
+++ /dev/null
@@ -1,40 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>ipcache</spirit:library>
- <spirit:name>2e46931808b7c212</spirit:name>
- <spirit:version>0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>scalp_zynqps_util_vector_logic_0_0</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_vector_logic" spirit:version="2.0"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_OPERATION">or</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">scalp_zynqps_util_vector_logic_0_0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOGO_FILE">data/sym_orgate.png</spirit:configurableElementValue>
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- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
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diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0.dcp
deleted file mode 100644
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Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
deleted file mode 100755
index a4109c79c504541073fb5a00f955321333a212b9..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
+++ /dev/null
@@ -1,105 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:28 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
-// Design : scalp_zynqps_util_vector_logic_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_util_vector_logic_0_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
- (Op1,
- Op2,
- Res);
- input [0:0]Op1;
- input [0:0]Op2;
- output [0:0]Res;
-
- wire [0:0]Op1;
- wire [0:0]Op2;
- wire [0:0]Res;
-
- LUT2 #(
- .INIT(4'hE))
- \Res[0]_INST_0
- (.I0(Op1),
- .I1(Op2),
- .O(Res));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0_stub.v
deleted file mode 100755
index 37a75881a3b177ab982fa63d210514957b43b6dd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/2e46931808b7c212/scalp_zynqps_util_vector_logic_0_0_stub.v
+++ /dev/null
@@ -1,22 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:28 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_0_0_stub.v
-// Design : scalp_zynqps_util_vector_logic_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2019.2" *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(Op1, Op2, Res)
-/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
- input [0:0]Op1;
- input [0:0]Op2;
- output [0:0]Res;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/afab8f8185921798.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/afab8f8185921798.xci
deleted file mode 100644
index 144121f6306e29e053e6d281eb38b3ff9f999d25..0000000000000000000000000000000000000000
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+++ /dev/null
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- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT84_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_INIT_VAL">0x0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">scalp_zynqps_vio_0_0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">afab8f8185921798</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">93940d4a</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">241</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0.dcp
deleted file mode 100644
index f019df12663f2c0d4c0c0756e7168dabe3612c77..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0_sim_netlist.v
deleted file mode 100755
index 7d50f39cdb71ad37cb2d6d46c8f1e777cf467a12..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0_sim_netlist.v
+++ /dev/null
@@ -1,7217 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:35 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_vio_0_0_sim_netlist.v
-// Design : scalp_zynqps_vio_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_vio_0_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
- (clk,
- probe_out0);
- input clk;
- output [0:0]probe_out0;
-
- wire clk;
- wire [0:0]probe_out0;
- wire [0:0]NLW_inst_probe_out1_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out10_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out100_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out101_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out102_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out103_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out104_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out105_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out106_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out107_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out108_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out109_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out11_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out110_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out111_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out112_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out113_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out114_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out115_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out116_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out117_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out118_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out119_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out12_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out120_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out121_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out122_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out123_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out124_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out125_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out126_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out127_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out128_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out129_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out13_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out130_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out131_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out132_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out133_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out134_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out135_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out136_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out137_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out138_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out139_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out14_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out140_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out141_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out142_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out143_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out144_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out145_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out146_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out147_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out148_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out149_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out15_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out150_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out151_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out152_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out153_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out154_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out155_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out156_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out157_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out158_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out159_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out16_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out160_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out161_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out162_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out163_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out164_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out165_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out166_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out167_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out168_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out169_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out17_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out170_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out171_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out172_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out173_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out174_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out175_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out176_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out177_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out178_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out179_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out18_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out180_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out181_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out182_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out183_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out184_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out185_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out186_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out187_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out188_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out189_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out19_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out190_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out191_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out192_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out193_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out194_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out195_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out196_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out197_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out198_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out199_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out2_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out20_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out200_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out201_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out202_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out203_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out204_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out205_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out206_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out207_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out208_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out209_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out21_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out210_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out211_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out212_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out213_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out214_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out215_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out216_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out217_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out218_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out219_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out22_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out220_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out221_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out222_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out223_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out224_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out225_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out226_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out227_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out228_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out229_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out23_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out230_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out231_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out232_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out233_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out234_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out235_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out236_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out237_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out238_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out239_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out24_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out240_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out241_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out242_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out243_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out244_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out245_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out246_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out247_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out248_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out249_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out25_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out250_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out251_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out252_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out253_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out254_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out255_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out26_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out27_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out28_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out29_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out3_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out30_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out31_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out32_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out33_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out34_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out35_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out36_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out37_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out38_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out39_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out4_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out40_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out41_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out42_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out43_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out44_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out45_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out46_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out47_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out48_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out49_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out5_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out50_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out51_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out52_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out53_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out54_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out55_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out56_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out57_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out58_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out59_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out6_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out60_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out61_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out62_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out63_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out64_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out65_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out66_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out67_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out68_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out69_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out7_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out70_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out71_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out72_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out73_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out74_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out75_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out76_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out77_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out78_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out79_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out8_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out80_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out81_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out82_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out83_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out84_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out85_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out86_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out87_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out88_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out89_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out9_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out90_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out91_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out92_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out93_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out94_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out95_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out96_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out97_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out98_UNCONNECTED;
- wire [0:0]NLW_inst_probe_out99_UNCONNECTED;
- wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;
-
- (* C_BUILD_REVISION = "0" *)
- (* C_BUS_ADDR_WIDTH = "17" *)
- (* C_BUS_DATA_WIDTH = "16" *)
- (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_MAJOR_VER = "2" *)
- (* C_CORE_MINOR_ALPHA_VER = "97" *)
- (* C_CORE_MINOR_VER = "0" *)
- (* C_CORE_TYPE = "2" *)
- (* C_CSE_DRV_VER = "1" *)
- (* C_EN_PROBE_IN_ACTIVITY = "0" *)
- (* C_EN_SYNCHRONIZATION = "1" *)
- (* C_MAJOR_VERSION = "2013" *)
- (* C_MAX_NUM_PROBE = "256" *)
- (* C_MAX_WIDTH_PER_PROBE = "256" *)
- (* C_MINOR_VERSION = "1" *)
- (* C_NEXT_SLAVE = "0" *)
- (* C_NUM_PROBE_IN = "0" *)
- (* C_NUM_PROBE_OUT = "1" *)
- (* C_PIPE_IFACE = "0" *)
- (* C_PROBE_IN0_WIDTH = "1" *)
- (* C_PROBE_IN100_WIDTH = "1" *)
- (* C_PROBE_IN101_WIDTH = "1" *)
- (* C_PROBE_IN102_WIDTH = "1" *)
- (* C_PROBE_IN103_WIDTH = "1" *)
- (* C_PROBE_IN104_WIDTH = "1" *)
- (* C_PROBE_IN105_WIDTH = "1" *)
- (* C_PROBE_IN106_WIDTH = "1" *)
- (* C_PROBE_IN107_WIDTH = "1" *)
- (* C_PROBE_IN108_WIDTH = "1" *)
- (* C_PROBE_IN109_WIDTH = "1" *)
- (* C_PROBE_IN10_WIDTH = "1" *)
- (* C_PROBE_IN110_WIDTH = "1" *)
- (* C_PROBE_IN111_WIDTH = "1" *)
- (* C_PROBE_IN112_WIDTH = "1" *)
- (* C_PROBE_IN113_WIDTH = "1" *)
- (* C_PROBE_IN114_WIDTH = "1" *)
- (* C_PROBE_IN115_WIDTH = "1" *)
- (* C_PROBE_IN116_WIDTH = "1" *)
- (* C_PROBE_IN117_WIDTH = "1" *)
- (* C_PROBE_IN118_WIDTH = "1" *)
- (* C_PROBE_IN119_WIDTH = "1" *)
- (* C_PROBE_IN11_WIDTH = "1" *)
- (* C_PROBE_IN120_WIDTH = "1" *)
- (* C_PROBE_IN121_WIDTH = "1" *)
- (* C_PROBE_IN122_WIDTH = "1" *)
- (* C_PROBE_IN123_WIDTH = "1" *)
- (* C_PROBE_IN124_WIDTH = "1" *)
- (* C_PROBE_IN125_WIDTH = "1" *)
- (* C_PROBE_IN126_WIDTH = "1" *)
- (* C_PROBE_IN127_WIDTH = "1" *)
- (* C_PROBE_IN128_WIDTH = "1" *)
- (* C_PROBE_IN129_WIDTH = "1" *)
- (* C_PROBE_IN12_WIDTH = "1" *)
- (* C_PROBE_IN130_WIDTH = "1" *)
- (* C_PROBE_IN131_WIDTH = "1" *)
- (* C_PROBE_IN132_WIDTH = "1" *)
- (* C_PROBE_IN133_WIDTH = "1" *)
- (* C_PROBE_IN134_WIDTH = "1" *)
- (* C_PROBE_IN135_WIDTH = "1" *)
- (* C_PROBE_IN136_WIDTH = "1" *)
- (* C_PROBE_IN137_WIDTH = "1" *)
- (* C_PROBE_IN138_WIDTH = "1" *)
- (* C_PROBE_IN139_WIDTH = "1" *)
- (* C_PROBE_IN13_WIDTH = "1" *)
- (* C_PROBE_IN140_WIDTH = "1" *)
- (* C_PROBE_IN141_WIDTH = "1" *)
- (* C_PROBE_IN142_WIDTH = "1" *)
- (* C_PROBE_IN143_WIDTH = "1" *)
- (* C_PROBE_IN144_WIDTH = "1" *)
- (* C_PROBE_IN145_WIDTH = "1" *)
- (* C_PROBE_IN146_WIDTH = "1" *)
- (* C_PROBE_IN147_WIDTH = "1" *)
- (* C_PROBE_IN148_WIDTH = "1" *)
- (* C_PROBE_IN149_WIDTH = "1" *)
- (* C_PROBE_IN14_WIDTH = "1" *)
- (* C_PROBE_IN150_WIDTH = "1" *)
- (* C_PROBE_IN151_WIDTH = "1" *)
- (* C_PROBE_IN152_WIDTH = "1" *)
- (* C_PROBE_IN153_WIDTH = "1" *)
- (* C_PROBE_IN154_WIDTH = "1" *)
- (* C_PROBE_IN155_WIDTH = "1" *)
- (* C_PROBE_IN156_WIDTH = "1" *)
- (* C_PROBE_IN157_WIDTH = "1" *)
- (* C_PROBE_IN158_WIDTH = "1" *)
- (* C_PROBE_IN159_WIDTH = "1" *)
- (* C_PROBE_IN15_WIDTH = "1" *)
- (* C_PROBE_IN160_WIDTH = "1" *)
- (* C_PROBE_IN161_WIDTH = "1" *)
- (* C_PROBE_IN162_WIDTH = "1" *)
- (* C_PROBE_IN163_WIDTH = "1" *)
- (* C_PROBE_IN164_WIDTH = "1" *)
- (* C_PROBE_IN165_WIDTH = "1" *)
- (* C_PROBE_IN166_WIDTH = "1" *)
- (* C_PROBE_IN167_WIDTH = "1" *)
- (* C_PROBE_IN168_WIDTH = "1" *)
- (* C_PROBE_IN169_WIDTH = "1" *)
- (* C_PROBE_IN16_WIDTH = "1" *)
- (* C_PROBE_IN170_WIDTH = "1" *)
- (* C_PROBE_IN171_WIDTH = "1" *)
- (* C_PROBE_IN172_WIDTH = "1" *)
- (* C_PROBE_IN173_WIDTH = "1" *)
- (* C_PROBE_IN174_WIDTH = "1" *)
- (* C_PROBE_IN175_WIDTH = "1" *)
- (* C_PROBE_IN176_WIDTH = "1" *)
- (* C_PROBE_IN177_WIDTH = "1" *)
- (* C_PROBE_IN178_WIDTH = "1" *)
- (* C_PROBE_IN179_WIDTH = "1" *)
- (* C_PROBE_IN17_WIDTH = "1" *)
- (* C_PROBE_IN180_WIDTH = "1" *)
- (* C_PROBE_IN181_WIDTH = "1" *)
- (* C_PROBE_IN182_WIDTH = "1" *)
- (* C_PROBE_IN183_WIDTH = "1" *)
- (* C_PROBE_IN184_WIDTH = "1" *)
- (* C_PROBE_IN185_WIDTH = "1" *)
- (* C_PROBE_IN186_WIDTH = "1" *)
- (* C_PROBE_IN187_WIDTH = "1" *)
- (* C_PROBE_IN188_WIDTH = "1" *)
- (* C_PROBE_IN189_WIDTH = "1" *)
- (* C_PROBE_IN18_WIDTH = "1" *)
- (* C_PROBE_IN190_WIDTH = "1" *)
- (* C_PROBE_IN191_WIDTH = "1" *)
- (* C_PROBE_IN192_WIDTH = "1" *)
- (* C_PROBE_IN193_WIDTH = "1" *)
- (* C_PROBE_IN194_WIDTH = "1" *)
- (* C_PROBE_IN195_WIDTH = "1" *)
- (* C_PROBE_IN196_WIDTH = "1" *)
- (* C_PROBE_IN197_WIDTH = "1" *)
- (* C_PROBE_IN198_WIDTH = "1" *)
- (* C_PROBE_IN199_WIDTH = "1" *)
- (* C_PROBE_IN19_WIDTH = "1" *)
- (* C_PROBE_IN1_WIDTH = "1" *)
- (* C_PROBE_IN200_WIDTH = "1" *)
- (* C_PROBE_IN201_WIDTH = "1" *)
- (* C_PROBE_IN202_WIDTH = "1" *)
- (* C_PROBE_IN203_WIDTH = "1" *)
- (* C_PROBE_IN204_WIDTH = "1" *)
- (* C_PROBE_IN205_WIDTH = "1" *)
- (* C_PROBE_IN206_WIDTH = "1" *)
- (* C_PROBE_IN207_WIDTH = "1" *)
- (* C_PROBE_IN208_WIDTH = "1" *)
- (* C_PROBE_IN209_WIDTH = "1" *)
- (* C_PROBE_IN20_WIDTH = "1" *)
- (* C_PROBE_IN210_WIDTH = "1" *)
- (* C_PROBE_IN211_WIDTH = "1" *)
- (* C_PROBE_IN212_WIDTH = "1" *)
- (* C_PROBE_IN213_WIDTH = "1" *)
- (* C_PROBE_IN214_WIDTH = "1" *)
- (* C_PROBE_IN215_WIDTH = "1" *)
- (* C_PROBE_IN216_WIDTH = "1" *)
- (* C_PROBE_IN217_WIDTH = "1" *)
- (* C_PROBE_IN218_WIDTH = "1" *)
- (* C_PROBE_IN219_WIDTH = "1" *)
- (* C_PROBE_IN21_WIDTH = "1" *)
- (* C_PROBE_IN220_WIDTH = "1" *)
- (* C_PROBE_IN221_WIDTH = "1" *)
- (* C_PROBE_IN222_WIDTH = "1" *)
- (* C_PROBE_IN223_WIDTH = "1" *)
- (* C_PROBE_IN224_WIDTH = "1" *)
- (* C_PROBE_IN225_WIDTH = "1" *)
- (* C_PROBE_IN226_WIDTH = "1" *)
- (* C_PROBE_IN227_WIDTH = "1" *)
- (* C_PROBE_IN228_WIDTH = "1" *)
- (* C_PROBE_IN229_WIDTH = "1" *)
- (* C_PROBE_IN22_WIDTH = "1" *)
- (* C_PROBE_IN230_WIDTH = "1" *)
- (* C_PROBE_IN231_WIDTH = "1" *)
- (* C_PROBE_IN232_WIDTH = "1" *)
- (* C_PROBE_IN233_WIDTH = "1" *)
- (* C_PROBE_IN234_WIDTH = "1" *)
- (* C_PROBE_IN235_WIDTH = "1" *)
- (* C_PROBE_IN236_WIDTH = "1" *)
- (* C_PROBE_IN237_WIDTH = "1" *)
- (* C_PROBE_IN238_WIDTH = "1" *)
- (* C_PROBE_IN239_WIDTH = "1" *)
- (* C_PROBE_IN23_WIDTH = "1" *)
- (* C_PROBE_IN240_WIDTH = "1" *)
- (* C_PROBE_IN241_WIDTH = "1" *)
- (* C_PROBE_IN242_WIDTH = "1" *)
- (* C_PROBE_IN243_WIDTH = "1" *)
- (* C_PROBE_IN244_WIDTH = "1" *)
- (* C_PROBE_IN245_WIDTH = "1" *)
- (* C_PROBE_IN246_WIDTH = "1" *)
- (* C_PROBE_IN247_WIDTH = "1" *)
- (* C_PROBE_IN248_WIDTH = "1" *)
- (* C_PROBE_IN249_WIDTH = "1" *)
- (* C_PROBE_IN24_WIDTH = "1" *)
- (* C_PROBE_IN250_WIDTH = "1" *)
- (* C_PROBE_IN251_WIDTH = "1" *)
- (* C_PROBE_IN252_WIDTH = "1" *)
- (* C_PROBE_IN253_WIDTH = "1" *)
- (* C_PROBE_IN254_WIDTH = "1" *)
- (* C_PROBE_IN255_WIDTH = "1" *)
- (* C_PROBE_IN25_WIDTH = "1" *)
- (* C_PROBE_IN26_WIDTH = "1" *)
- (* C_PROBE_IN27_WIDTH = "1" *)
- (* C_PROBE_IN28_WIDTH = "1" *)
- (* C_PROBE_IN29_WIDTH = "1" *)
- (* C_PROBE_IN2_WIDTH = "1" *)
- (* C_PROBE_IN30_WIDTH = "1" *)
- (* C_PROBE_IN31_WIDTH = "1" *)
- (* C_PROBE_IN32_WIDTH = "1" *)
- (* C_PROBE_IN33_WIDTH = "1" *)
- (* C_PROBE_IN34_WIDTH = "1" *)
- (* C_PROBE_IN35_WIDTH = "1" *)
- (* C_PROBE_IN36_WIDTH = "1" *)
- (* C_PROBE_IN37_WIDTH = "1" *)
- (* C_PROBE_IN38_WIDTH = "1" *)
- (* C_PROBE_IN39_WIDTH = "1" *)
- (* C_PROBE_IN3_WIDTH = "1" *)
- (* C_PROBE_IN40_WIDTH = "1" *)
- (* C_PROBE_IN41_WIDTH = "1" *)
- (* C_PROBE_IN42_WIDTH = "1" *)
- (* C_PROBE_IN43_WIDTH = "1" *)
- (* C_PROBE_IN44_WIDTH = "1" *)
- (* C_PROBE_IN45_WIDTH = "1" *)
- (* C_PROBE_IN46_WIDTH = "1" *)
- (* C_PROBE_IN47_WIDTH = "1" *)
- (* C_PROBE_IN48_WIDTH = "1" *)
- (* C_PROBE_IN49_WIDTH = "1" *)
- (* C_PROBE_IN4_WIDTH = "1" *)
- (* C_PROBE_IN50_WIDTH = "1" *)
- (* C_PROBE_IN51_WIDTH = "1" *)
- (* C_PROBE_IN52_WIDTH = "1" *)
- (* C_PROBE_IN53_WIDTH = "1" *)
- (* C_PROBE_IN54_WIDTH = "1" *)
- (* C_PROBE_IN55_WIDTH = "1" *)
- (* C_PROBE_IN56_WIDTH = "1" *)
- (* C_PROBE_IN57_WIDTH = "1" *)
- (* C_PROBE_IN58_WIDTH = "1" *)
- (* C_PROBE_IN59_WIDTH = "1" *)
- (* C_PROBE_IN5_WIDTH = "1" *)
- (* C_PROBE_IN60_WIDTH = "1" *)
- (* C_PROBE_IN61_WIDTH = "1" *)
- (* C_PROBE_IN62_WIDTH = "1" *)
- (* C_PROBE_IN63_WIDTH = "1" *)
- (* C_PROBE_IN64_WIDTH = "1" *)
- (* C_PROBE_IN65_WIDTH = "1" *)
- (* C_PROBE_IN66_WIDTH = "1" *)
- (* C_PROBE_IN67_WIDTH = "1" *)
- (* C_PROBE_IN68_WIDTH = "1" *)
- (* C_PROBE_IN69_WIDTH = "1" *)
- (* C_PROBE_IN6_WIDTH = "1" *)
- (* C_PROBE_IN70_WIDTH = "1" *)
- (* C_PROBE_IN71_WIDTH = "1" *)
- (* C_PROBE_IN72_WIDTH = "1" *)
- (* C_PROBE_IN73_WIDTH = "1" *)
- (* C_PROBE_IN74_WIDTH = "1" *)
- (* C_PROBE_IN75_WIDTH = "1" *)
- (* C_PROBE_IN76_WIDTH = "1" *)
- (* C_PROBE_IN77_WIDTH = "1" *)
- (* C_PROBE_IN78_WIDTH = "1" *)
- (* C_PROBE_IN79_WIDTH = "1" *)
- (* C_PROBE_IN7_WIDTH = "1" *)
- (* C_PROBE_IN80_WIDTH = "1" *)
- (* C_PROBE_IN81_WIDTH = "1" *)
- (* C_PROBE_IN82_WIDTH = "1" *)
- (* C_PROBE_IN83_WIDTH = "1" *)
- (* C_PROBE_IN84_WIDTH = "1" *)
- (* C_PROBE_IN85_WIDTH = "1" *)
- (* C_PROBE_IN86_WIDTH = "1" *)
- (* C_PROBE_IN87_WIDTH = "1" *)
- (* C_PROBE_IN88_WIDTH = "1" *)
- (* C_PROBE_IN89_WIDTH = "1" *)
- (* C_PROBE_IN8_WIDTH = "1" *)
- (* C_PROBE_IN90_WIDTH = "1" *)
- (* C_PROBE_IN91_WIDTH = "1" *)
- (* C_PROBE_IN92_WIDTH = "1" *)
- (* C_PROBE_IN93_WIDTH = "1" *)
- (* C_PROBE_IN94_WIDTH = "1" *)
- (* C_PROBE_IN95_WIDTH = "1" *)
- (* C_PROBE_IN96_WIDTH = "1" *)
- (* C_PROBE_IN97_WIDTH = "1" *)
- (* C_PROBE_IN98_WIDTH = "1" *)
- (* C_PROBE_IN99_WIDTH = "1" *)
- (* C_PROBE_IN9_WIDTH = "1" *)
- (* C_PROBE_OUT0_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT0_WIDTH = "1" *)
- (* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT100_WIDTH = "1" *)
- (* C_PROBE_OUT101_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT101_WIDTH = "1" *)
- (* C_PROBE_OUT102_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT102_WIDTH = "1" *)
- (* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT103_WIDTH = "1" *)
- (* C_PROBE_OUT104_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT104_WIDTH = "1" *)
- (* C_PROBE_OUT105_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT105_WIDTH = "1" *)
- (* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT106_WIDTH = "1" *)
- (* C_PROBE_OUT107_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT107_WIDTH = "1" *)
- (* C_PROBE_OUT108_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT108_WIDTH = "1" *)
- (* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT109_WIDTH = "1" *)
- (* C_PROBE_OUT10_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT10_WIDTH = "1" *)
- (* C_PROBE_OUT110_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT110_WIDTH = "1" *)
- (* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT111_WIDTH = "1" *)
- (* C_PROBE_OUT112_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT112_WIDTH = "1" *)
- (* C_PROBE_OUT113_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT113_WIDTH = "1" *)
- (* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT114_WIDTH = "1" *)
- (* C_PROBE_OUT115_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT115_WIDTH = "1" *)
- (* C_PROBE_OUT116_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT116_WIDTH = "1" *)
- (* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT117_WIDTH = "1" *)
- (* C_PROBE_OUT118_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT118_WIDTH = "1" *)
- (* C_PROBE_OUT119_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT119_WIDTH = "1" *)
- (* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT11_WIDTH = "1" *)
- (* C_PROBE_OUT120_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT120_WIDTH = "1" *)
- (* C_PROBE_OUT121_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT121_WIDTH = "1" *)
- (* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT122_WIDTH = "1" *)
- (* C_PROBE_OUT123_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT123_WIDTH = "1" *)
- (* C_PROBE_OUT124_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT124_WIDTH = "1" *)
- (* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT125_WIDTH = "1" *)
- (* C_PROBE_OUT126_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT126_WIDTH = "1" *)
- (* C_PROBE_OUT127_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT127_WIDTH = "1" *)
- (* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT128_WIDTH = "1" *)
- (* C_PROBE_OUT129_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT129_WIDTH = "1" *)
- (* C_PROBE_OUT12_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT12_WIDTH = "1" *)
- (* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT130_WIDTH = "1" *)
- (* C_PROBE_OUT131_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT131_WIDTH = "1" *)
- (* C_PROBE_OUT132_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT132_WIDTH = "1" *)
- (* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT133_WIDTH = "1" *)
- (* C_PROBE_OUT134_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT134_WIDTH = "1" *)
- (* C_PROBE_OUT135_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT135_WIDTH = "1" *)
- (* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT136_WIDTH = "1" *)
- (* C_PROBE_OUT137_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT137_WIDTH = "1" *)
- (* C_PROBE_OUT138_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT138_WIDTH = "1" *)
- (* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT139_WIDTH = "1" *)
- (* C_PROBE_OUT13_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT13_WIDTH = "1" *)
- (* C_PROBE_OUT140_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT140_WIDTH = "1" *)
- (* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT141_WIDTH = "1" *)
- (* C_PROBE_OUT142_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT142_WIDTH = "1" *)
- (* C_PROBE_OUT143_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT143_WIDTH = "1" *)
- (* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT144_WIDTH = "1" *)
- (* C_PROBE_OUT145_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT145_WIDTH = "1" *)
- (* C_PROBE_OUT146_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT146_WIDTH = "1" *)
- (* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT147_WIDTH = "1" *)
- (* C_PROBE_OUT148_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT148_WIDTH = "1" *)
- (* C_PROBE_OUT149_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT149_WIDTH = "1" *)
- (* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT14_WIDTH = "1" *)
- (* C_PROBE_OUT150_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT150_WIDTH = "1" *)
- (* C_PROBE_OUT151_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT151_WIDTH = "1" *)
- (* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT152_WIDTH = "1" *)
- (* C_PROBE_OUT153_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT153_WIDTH = "1" *)
- (* C_PROBE_OUT154_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT154_WIDTH = "1" *)
- (* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT155_WIDTH = "1" *)
- (* C_PROBE_OUT156_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT156_WIDTH = "1" *)
- (* C_PROBE_OUT157_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT157_WIDTH = "1" *)
- (* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT158_WIDTH = "1" *)
- (* C_PROBE_OUT159_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT159_WIDTH = "1" *)
- (* C_PROBE_OUT15_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT15_WIDTH = "1" *)
- (* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT160_WIDTH = "1" *)
- (* C_PROBE_OUT161_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT161_WIDTH = "1" *)
- (* C_PROBE_OUT162_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT162_WIDTH = "1" *)
- (* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT163_WIDTH = "1" *)
- (* C_PROBE_OUT164_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT164_WIDTH = "1" *)
- (* C_PROBE_OUT165_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT165_WIDTH = "1" *)
- (* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT166_WIDTH = "1" *)
- (* C_PROBE_OUT167_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT167_WIDTH = "1" *)
- (* C_PROBE_OUT168_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT168_WIDTH = "1" *)
- (* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT169_WIDTH = "1" *)
- (* C_PROBE_OUT16_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT16_WIDTH = "1" *)
- (* C_PROBE_OUT170_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT170_WIDTH = "1" *)
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- (* C_PROBE_OUT171_WIDTH = "1" *)
- (* C_PROBE_OUT172_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT172_WIDTH = "1" *)
- (* C_PROBE_OUT173_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT173_WIDTH = "1" *)
- (* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT174_WIDTH = "1" *)
- (* C_PROBE_OUT175_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT175_WIDTH = "1" *)
- (* C_PROBE_OUT176_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT176_WIDTH = "1" *)
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- (* C_PROBE_OUT177_WIDTH = "1" *)
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- (* C_PROBE_OUT178_WIDTH = "1" *)
- (* C_PROBE_OUT179_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT179_WIDTH = "1" *)
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- (* C_PROBE_OUT17_WIDTH = "1" *)
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- (* C_PROBE_OUT180_WIDTH = "1" *)
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- (* C_PROBE_OUT181_WIDTH = "1" *)
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- (* C_PROBE_OUT182_WIDTH = "1" *)
- (* C_PROBE_OUT183_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT183_WIDTH = "1" *)
- (* C_PROBE_OUT184_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT184_WIDTH = "1" *)
- (* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT185_WIDTH = "1" *)
- (* C_PROBE_OUT186_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT186_WIDTH = "1" *)
- (* C_PROBE_OUT187_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT187_WIDTH = "1" *)
- (* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT188_WIDTH = "1" *)
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- (* C_PROBE_OUT189_WIDTH = "1" *)
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- (* C_PROBE_OUT18_WIDTH = "1" *)
- (* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT190_WIDTH = "1" *)
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- (* C_PROBE_OUT191_WIDTH = "1" *)
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- (* C_PROBE_OUT192_WIDTH = "1" *)
- (* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT193_WIDTH = "1" *)
- (* C_PROBE_OUT194_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT194_WIDTH = "1" *)
- (* C_PROBE_OUT195_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT195_WIDTH = "1" *)
- (* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT196_WIDTH = "1" *)
- (* C_PROBE_OUT197_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT197_WIDTH = "1" *)
- (* C_PROBE_OUT198_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT198_WIDTH = "1" *)
- (* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT199_WIDTH = "1" *)
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- (* C_PROBE_OUT19_WIDTH = "1" *)
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- (* C_PROBE_OUT1_WIDTH = "1" *)
- (* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT200_WIDTH = "1" *)
- (* C_PROBE_OUT201_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT201_WIDTH = "1" *)
- (* C_PROBE_OUT202_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT202_WIDTH = "1" *)
- (* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT203_WIDTH = "1" *)
- (* C_PROBE_OUT204_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT204_WIDTH = "1" *)
- (* C_PROBE_OUT205_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT205_WIDTH = "1" *)
- (* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT206_WIDTH = "1" *)
- (* C_PROBE_OUT207_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT207_WIDTH = "1" *)
- (* C_PROBE_OUT208_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT208_WIDTH = "1" *)
- (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT209_WIDTH = "1" *)
- (* C_PROBE_OUT20_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT20_WIDTH = "1" *)
- (* C_PROBE_OUT210_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT210_WIDTH = "1" *)
- (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT211_WIDTH = "1" *)
- (* C_PROBE_OUT212_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT212_WIDTH = "1" *)
- (* C_PROBE_OUT213_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT213_WIDTH = "1" *)
- (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT214_WIDTH = "1" *)
- (* C_PROBE_OUT215_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT215_WIDTH = "1" *)
- (* C_PROBE_OUT216_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT216_WIDTH = "1" *)
- (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT217_WIDTH = "1" *)
- (* C_PROBE_OUT218_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT218_WIDTH = "1" *)
- (* C_PROBE_OUT219_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT219_WIDTH = "1" *)
- (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT21_WIDTH = "1" *)
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- (* C_PROBE_OUT220_WIDTH = "1" *)
- (* C_PROBE_OUT221_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT221_WIDTH = "1" *)
- (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT222_WIDTH = "1" *)
- (* C_PROBE_OUT223_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT223_WIDTH = "1" *)
- (* C_PROBE_OUT224_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT224_WIDTH = "1" *)
- (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT225_WIDTH = "1" *)
- (* C_PROBE_OUT226_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT226_WIDTH = "1" *)
- (* C_PROBE_OUT227_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT227_WIDTH = "1" *)
- (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT228_WIDTH = "1" *)
- (* C_PROBE_OUT229_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT229_WIDTH = "1" *)
- (* C_PROBE_OUT22_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT22_WIDTH = "1" *)
- (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT230_WIDTH = "1" *)
- (* C_PROBE_OUT231_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT231_WIDTH = "1" *)
- (* C_PROBE_OUT232_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT232_WIDTH = "1" *)
- (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT233_WIDTH = "1" *)
- (* C_PROBE_OUT234_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT234_WIDTH = "1" *)
- (* C_PROBE_OUT235_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT235_WIDTH = "1" *)
- (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT236_WIDTH = "1" *)
- (* C_PROBE_OUT237_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT237_WIDTH = "1" *)
- (* C_PROBE_OUT238_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT238_WIDTH = "1" *)
- (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT239_WIDTH = "1" *)
- (* C_PROBE_OUT23_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT23_WIDTH = "1" *)
- (* C_PROBE_OUT240_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT240_WIDTH = "1" *)
- (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT241_WIDTH = "1" *)
- (* C_PROBE_OUT242_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT242_WIDTH = "1" *)
- (* C_PROBE_OUT243_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT243_WIDTH = "1" *)
- (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT244_WIDTH = "1" *)
- (* C_PROBE_OUT245_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT245_WIDTH = "1" *)
- (* C_PROBE_OUT246_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT246_WIDTH = "1" *)
- (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT247_WIDTH = "1" *)
- (* C_PROBE_OUT248_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT248_WIDTH = "1" *)
- (* C_PROBE_OUT249_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT249_WIDTH = "1" *)
- (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT24_WIDTH = "1" *)
- (* C_PROBE_OUT250_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT250_WIDTH = "1" *)
- (* C_PROBE_OUT251_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT251_WIDTH = "1" *)
- (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT252_WIDTH = "1" *)
- (* C_PROBE_OUT253_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT253_WIDTH = "1" *)
- (* C_PROBE_OUT254_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT254_WIDTH = "1" *)
- (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT255_WIDTH = "1" *)
- (* C_PROBE_OUT25_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT25_WIDTH = "1" *)
- (* C_PROBE_OUT26_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT26_WIDTH = "1" *)
- (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT27_WIDTH = "1" *)
- (* C_PROBE_OUT28_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT28_WIDTH = "1" *)
- (* C_PROBE_OUT29_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT29_WIDTH = "1" *)
- (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT2_WIDTH = "1" *)
- (* C_PROBE_OUT30_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT30_WIDTH = "1" *)
- (* C_PROBE_OUT31_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT31_WIDTH = "1" *)
- (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT32_WIDTH = "1" *)
- (* C_PROBE_OUT33_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT33_WIDTH = "1" *)
- (* C_PROBE_OUT34_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT34_WIDTH = "1" *)
- (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT35_WIDTH = "1" *)
- (* C_PROBE_OUT36_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT36_WIDTH = "1" *)
- (* C_PROBE_OUT37_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT37_WIDTH = "1" *)
- (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT38_WIDTH = "1" *)
- (* C_PROBE_OUT39_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT39_WIDTH = "1" *)
- (* C_PROBE_OUT3_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT3_WIDTH = "1" *)
- (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT40_WIDTH = "1" *)
- (* C_PROBE_OUT41_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT41_WIDTH = "1" *)
- (* C_PROBE_OUT42_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT42_WIDTH = "1" *)
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- (* C_PROBE_OUT43_WIDTH = "1" *)
- (* C_PROBE_OUT44_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT44_WIDTH = "1" *)
- (* C_PROBE_OUT45_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT45_WIDTH = "1" *)
- (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT46_WIDTH = "1" *)
- (* C_PROBE_OUT47_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT47_WIDTH = "1" *)
- (* C_PROBE_OUT48_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT48_WIDTH = "1" *)
- (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT49_WIDTH = "1" *)
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- (* C_PROBE_OUT50_INIT_VAL = "1'b0" *)
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- (* C_PROBE_OUT51_WIDTH = "1" *)
- (* C_PROBE_OUT52_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT52_WIDTH = "1" *)
- (* C_PROBE_OUT53_INIT_VAL = "1'b0" *)
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- (* C_PROBE_OUT55_WIDTH = "1" *)
- (* C_PROBE_OUT56_INIT_VAL = "1'b0" *)
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- (* C_PROBE_OUT72_INIT_VAL = "1'b0" *)
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- (* C_PROBE_OUT75_INIT_VAL = "1'b0" *)
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- (* C_PROBE_OUT76_WIDTH = "1" *)
- (* C_PROBE_OUT77_INIT_VAL = "1'b0" *)
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- (* C_PROBE_OUT78_INIT_VAL = "1'b0" *)
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- (* C_PROBE_OUT80_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT80_WIDTH = "1" *)
- (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT81_WIDTH = "1" *)
- (* C_PROBE_OUT82_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT82_WIDTH = "1" *)
- (* C_PROBE_OUT83_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT83_WIDTH = "1" *)
- (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT84_WIDTH = "1" *)
- (* C_PROBE_OUT85_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT85_WIDTH = "1" *)
- (* C_PROBE_OUT86_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT86_WIDTH = "1" *)
- (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT87_WIDTH = "1" *)
- (* C_PROBE_OUT88_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT88_WIDTH = "1" *)
- (* C_PROBE_OUT89_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT89_WIDTH = "1" *)
- (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT8_WIDTH = "1" *)
- (* C_PROBE_OUT90_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT90_WIDTH = "1" *)
- (* C_PROBE_OUT91_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT91_WIDTH = "1" *)
- (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT92_WIDTH = "1" *)
- (* C_PROBE_OUT93_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT93_WIDTH = "1" *)
- (* C_PROBE_OUT94_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT94_WIDTH = "1" *)
- (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT95_WIDTH = "1" *)
- (* C_PROBE_OUT96_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT96_WIDTH = "1" *)
- (* C_PROBE_OUT97_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT97_WIDTH = "1" *)
- (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT98_WIDTH = "1" *)
- (* C_PROBE_OUT99_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT99_WIDTH = "1" *)
- (* C_PROBE_OUT9_INIT_VAL = "1'b0" *)
- (* C_PROBE_OUT9_WIDTH = "1" *)
- (* C_USE_TEST_REG = "1" *)
- (* C_XDEVICEFAMILY = "zynq" *)
- (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *)
- (* C_XSDB_SLAVE_TYPE = "33" *)
- (* DONT_TOUCH *)
- (* DowngradeIPIdentifiedWarnings = "yes" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
- (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
- (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
- (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
- (* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
- (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
- (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
- (* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
- (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
- (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
- (* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
- (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
- (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* LC_TOTAL_PROBE_IN_WIDTH = "0" *)
- (* LC_TOTAL_PROBE_OUT_WIDTH = "1" *)
- (* syn_noprune = "1" *)
- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_vio inst
- (.clk(clk),
- .probe_in0(1'b0),
- .probe_in1(1'b0),
- .probe_in10(1'b0),
- .probe_in100(1'b0),
- .probe_in101(1'b0),
- .probe_in102(1'b0),
- .probe_in103(1'b0),
- .probe_in104(1'b0),
- .probe_in105(1'b0),
- .probe_in106(1'b0),
- .probe_in107(1'b0),
- .probe_in108(1'b0),
- .probe_in109(1'b0),
- .probe_in11(1'b0),
- .probe_in110(1'b0),
- .probe_in111(1'b0),
- .probe_in112(1'b0),
- .probe_in113(1'b0),
- .probe_in114(1'b0),
- .probe_in115(1'b0),
- .probe_in116(1'b0),
- .probe_in117(1'b0),
- .probe_in118(1'b0),
- .probe_in119(1'b0),
- .probe_in12(1'b0),
- .probe_in120(1'b0),
- .probe_in121(1'b0),
- .probe_in122(1'b0),
- .probe_in123(1'b0),
- .probe_in124(1'b0),
- .probe_in125(1'b0),
- .probe_in126(1'b0),
- .probe_in127(1'b0),
- .probe_in128(1'b0),
- .probe_in129(1'b0),
- .probe_in13(1'b0),
- .probe_in130(1'b0),
- .probe_in131(1'b0),
- .probe_in132(1'b0),
- .probe_in133(1'b0),
- .probe_in134(1'b0),
- .probe_in135(1'b0),
- .probe_in136(1'b0),
- .probe_in137(1'b0),
- .probe_in138(1'b0),
- .probe_in139(1'b0),
- .probe_in14(1'b0),
- .probe_in140(1'b0),
- .probe_in141(1'b0),
- .probe_in142(1'b0),
- .probe_in143(1'b0),
- .probe_in144(1'b0),
- .probe_in145(1'b0),
- .probe_in146(1'b0),
- .probe_in147(1'b0),
- .probe_in148(1'b0),
- .probe_in149(1'b0),
- .probe_in15(1'b0),
- .probe_in150(1'b0),
- .probe_in151(1'b0),
- .probe_in152(1'b0),
- .probe_in153(1'b0),
- .probe_in154(1'b0),
- .probe_in155(1'b0),
- .probe_in156(1'b0),
- .probe_in157(1'b0),
- .probe_in158(1'b0),
- .probe_in159(1'b0),
- .probe_in16(1'b0),
- .probe_in160(1'b0),
- .probe_in161(1'b0),
- .probe_in162(1'b0),
- .probe_in163(1'b0),
- .probe_in164(1'b0),
- .probe_in165(1'b0),
- .probe_in166(1'b0),
- .probe_in167(1'b0),
- .probe_in168(1'b0),
- .probe_in169(1'b0),
- .probe_in17(1'b0),
- .probe_in170(1'b0),
- .probe_in171(1'b0),
- .probe_in172(1'b0),
- .probe_in173(1'b0),
- .probe_in174(1'b0),
- .probe_in175(1'b0),
- .probe_in176(1'b0),
- .probe_in177(1'b0),
- .probe_in178(1'b0),
- .probe_in179(1'b0),
- .probe_in18(1'b0),
- .probe_in180(1'b0),
- .probe_in181(1'b0),
- .probe_in182(1'b0),
- .probe_in183(1'b0),
- .probe_in184(1'b0),
- .probe_in185(1'b0),
- .probe_in186(1'b0),
- .probe_in187(1'b0),
- .probe_in188(1'b0),
- .probe_in189(1'b0),
- .probe_in19(1'b0),
- .probe_in190(1'b0),
- .probe_in191(1'b0),
- .probe_in192(1'b0),
- .probe_in193(1'b0),
- .probe_in194(1'b0),
- .probe_in195(1'b0),
- .probe_in196(1'b0),
- .probe_in197(1'b0),
- .probe_in198(1'b0),
- .probe_in199(1'b0),
- .probe_in2(1'b0),
- .probe_in20(1'b0),
- .probe_in200(1'b0),
- .probe_in201(1'b0),
- .probe_in202(1'b0),
- .probe_in203(1'b0),
- .probe_in204(1'b0),
- .probe_in205(1'b0),
- .probe_in206(1'b0),
- .probe_in207(1'b0),
- .probe_in208(1'b0),
- .probe_in209(1'b0),
- .probe_in21(1'b0),
- .probe_in210(1'b0),
- .probe_in211(1'b0),
- .probe_in212(1'b0),
- .probe_in213(1'b0),
- .probe_in214(1'b0),
- .probe_in215(1'b0),
- .probe_in216(1'b0),
- .probe_in217(1'b0),
- .probe_in218(1'b0),
- .probe_in219(1'b0),
- .probe_in22(1'b0),
- .probe_in220(1'b0),
- .probe_in221(1'b0),
- .probe_in222(1'b0),
- .probe_in223(1'b0),
- .probe_in224(1'b0),
- .probe_in225(1'b0),
- .probe_in226(1'b0),
- .probe_in227(1'b0),
- .probe_in228(1'b0),
- .probe_in229(1'b0),
- .probe_in23(1'b0),
- .probe_in230(1'b0),
- .probe_in231(1'b0),
- .probe_in232(1'b0),
- .probe_in233(1'b0),
- .probe_in234(1'b0),
- .probe_in235(1'b0),
- .probe_in236(1'b0),
- .probe_in237(1'b0),
- .probe_in238(1'b0),
- .probe_in239(1'b0),
- .probe_in24(1'b0),
- .probe_in240(1'b0),
- .probe_in241(1'b0),
- .probe_in242(1'b0),
- .probe_in243(1'b0),
- .probe_in244(1'b0),
- .probe_in245(1'b0),
- .probe_in246(1'b0),
- .probe_in247(1'b0),
- .probe_in248(1'b0),
- .probe_in249(1'b0),
- .probe_in25(1'b0),
- .probe_in250(1'b0),
- .probe_in251(1'b0),
- .probe_in252(1'b0),
- .probe_in253(1'b0),
- .probe_in254(1'b0),
- .probe_in255(1'b0),
- .probe_in26(1'b0),
- .probe_in27(1'b0),
- .probe_in28(1'b0),
- .probe_in29(1'b0),
- .probe_in3(1'b0),
- .probe_in30(1'b0),
- .probe_in31(1'b0),
- .probe_in32(1'b0),
- .probe_in33(1'b0),
- .probe_in34(1'b0),
- .probe_in35(1'b0),
- .probe_in36(1'b0),
- .probe_in37(1'b0),
- .probe_in38(1'b0),
- .probe_in39(1'b0),
- .probe_in4(1'b0),
- .probe_in40(1'b0),
- .probe_in41(1'b0),
- .probe_in42(1'b0),
- .probe_in43(1'b0),
- .probe_in44(1'b0),
- .probe_in45(1'b0),
- .probe_in46(1'b0),
- .probe_in47(1'b0),
- .probe_in48(1'b0),
- .probe_in49(1'b0),
- .probe_in5(1'b0),
- .probe_in50(1'b0),
- .probe_in51(1'b0),
- .probe_in52(1'b0),
- .probe_in53(1'b0),
- .probe_in54(1'b0),
- .probe_in55(1'b0),
- .probe_in56(1'b0),
- .probe_in57(1'b0),
- .probe_in58(1'b0),
- .probe_in59(1'b0),
- .probe_in6(1'b0),
- .probe_in60(1'b0),
- .probe_in61(1'b0),
- .probe_in62(1'b0),
- .probe_in63(1'b0),
- .probe_in64(1'b0),
- .probe_in65(1'b0),
- .probe_in66(1'b0),
- .probe_in67(1'b0),
- .probe_in68(1'b0),
- .probe_in69(1'b0),
- .probe_in7(1'b0),
- .probe_in70(1'b0),
- .probe_in71(1'b0),
- .probe_in72(1'b0),
- .probe_in73(1'b0),
- .probe_in74(1'b0),
- .probe_in75(1'b0),
- .probe_in76(1'b0),
- .probe_in77(1'b0),
- .probe_in78(1'b0),
- .probe_in79(1'b0),
- .probe_in8(1'b0),
- .probe_in80(1'b0),
- .probe_in81(1'b0),
- .probe_in82(1'b0),
- .probe_in83(1'b0),
- .probe_in84(1'b0),
- .probe_in85(1'b0),
- .probe_in86(1'b0),
- .probe_in87(1'b0),
- .probe_in88(1'b0),
- .probe_in89(1'b0),
- .probe_in9(1'b0),
- .probe_in90(1'b0),
- .probe_in91(1'b0),
- .probe_in92(1'b0),
- .probe_in93(1'b0),
- .probe_in94(1'b0),
- .probe_in95(1'b0),
- .probe_in96(1'b0),
- .probe_in97(1'b0),
- .probe_in98(1'b0),
- .probe_in99(1'b0),
- .probe_out0(probe_out0),
- .probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]),
- .probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]),
- .probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]),
- .probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]),
- .probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]),
- .probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]),
- .probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]),
- .probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]),
- .probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]),
- .probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]),
- .probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]),
- .probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]),
- .probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]),
- .probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]),
- .probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]),
- .probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]),
- .probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]),
- .probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]),
- .probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]),
- .probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]),
- .probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]),
- .probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]),
- .probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]),
- .probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]),
- .probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]),
- .probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]),
- .probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]),
- .probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]),
- .probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]),
- .probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]),
- .probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]),
- .probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]),
- .probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]),
- .probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]),
- .probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]),
- .probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]),
- .probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]),
- .probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]),
- .probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]),
- .probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]),
- .probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]),
- .probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]),
- .probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]),
- .probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]),
- .probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]),
- .probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]),
- .probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]),
- .probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]),
- .probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]),
- .probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]),
- .probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]),
- .probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]),
- .probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]),
- .probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]),
- .probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]),
- .probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]),
- .probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]),
- .probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]),
- .probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]),
- .probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]),
- .probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]),
- .probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]),
- .probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]),
- .probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]),
- .probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]),
- .probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]),
- .probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]),
- .probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]),
- .probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]),
- .probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]),
- .probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]),
- .probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]),
- .probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]),
- .probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]),
- .probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]),
- .probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]),
- .probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]),
- .probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]),
- .probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]),
- .probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]),
- .probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]),
- .probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]),
- .probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]),
- .probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]),
- .probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]),
- .probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]),
- .probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]),
- .probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]),
- .probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]),
- .probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]),
- .probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]),
- .probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]),
- .probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]),
- .probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]),
- .probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]),
- .probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]),
- .probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]),
- .probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]),
- .probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]),
- .probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]),
- .probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]),
- .probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]),
- .probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]),
- .probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]),
- .probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]),
- .probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]),
- .probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]),
- .probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]),
- .probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]),
- .probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]),
- .probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]),
- .probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]),
- .probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]),
- .probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]),
- .probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]),
- .probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]),
- .probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]),
- .probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]),
- .probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]),
- .probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]),
- .probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]),
- .probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]),
- .probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]),
- .probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]),
- .probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]),
- .probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]),
- .probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]),
- .probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]),
- .probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]),
- .probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]),
- .probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]),
- .probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]),
- .probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]),
- .probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]),
- .probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]),
- .probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]),
- .probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]),
- .probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]),
- .probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]),
- .probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]),
- .probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]),
- .probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]),
- .probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]),
- .probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]),
- .probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]),
- .probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]),
- .probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]),
- .probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]),
- .probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]),
- .probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]),
- .probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]),
- .probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]),
- .probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]),
- .probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]),
- .probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]),
- .probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]),
- .probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]),
- .probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]),
- .probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]),
- .probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]),
- .probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]),
- .probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]),
- .probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]),
- .probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]),
- .probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]),
- .probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]),
- .probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]),
- .probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]),
- .probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]),
- .probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]),
- .probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]),
- .probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]),
- .probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]),
- .probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]),
- .probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]),
- .probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]),
- .probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]),
- .probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]),
- .probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]),
- .probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]),
- .probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]),
- .probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]),
- .probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]),
- .probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]),
- .probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]),
- .probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]),
- .probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]),
- .probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]),
- .probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]),
- .probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]),
- .probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]),
- .probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]),
- .probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]),
- .probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]),
- .probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]),
- .probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]),
- .probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]),
- .probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]),
- .probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]),
- .probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]),
- .probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]),
- .probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]),
- .probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]),
- .probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]),
- .probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]),
- .probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]),
- .probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]),
- .probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]),
- .probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]),
- .probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]),
- .probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]),
- .probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]),
- .probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]),
- .probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]),
- .probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]),
- .probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]),
- .probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]),
- .probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]),
- .probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]),
- .probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]),
- .probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]),
- .probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]),
- .probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]),
- .probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]),
- .probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]),
- .probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]),
- .probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]),
- .probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]),
- .probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]),
- .probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]),
- .probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]),
- .probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]),
- .probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]),
- .probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]),
- .probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]),
- .probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]),
- .probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]),
- .probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]),
- .probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]),
- .probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]),
- .probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]),
- .probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]),
- .probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]),
- .probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]),
- .probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]),
- .probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]),
- .probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]),
- .probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]),
- .probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]),
- .probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]),
- .probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]),
- .probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]),
- .probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]),
- .probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]),
- .probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]),
- .sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]));
-endmodule
-
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_decoder
- (s_drdy_i,
- in0,
- SR,
- xsdb_wr__0,
- \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ,
- \G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ,
- s_do_i,
- s_rst_o,
- out,
- s_daddr_o,
- s_den_o,
- s_dwe_o,
- Q,
- Probe_out_reg);
- output s_drdy_i;
- output in0;
- output [0:0]SR;
- output xsdb_wr__0;
- output \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ;
- output \G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ;
- output [15:0]s_do_i;
- input s_rst_o;
- input out;
- input [16:0]s_daddr_o;
- input s_den_o;
- input s_dwe_o;
- input [15:0]Q;
- input [0:0]Probe_out_reg;
-
- wire \Bus_data_out[0]_i_1_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ;
- wire [0:0]Probe_out_reg;
- wire [15:0]Q;
- wire [0:0]SR;
- wire clear_int_i_1_n_0;
- wire committ_int_i_1_n_0;
- wire [15:0]data_info_probe_in;
- wire in0;
- wire int_cnt_rst;
- wire int_cnt_rst_i_1_n_0;
- wire out;
- wire [15:0]probe_out_modified;
- wire rd_en_p1;
- wire rd_en_p2;
- wire [16:0]s_daddr_o;
- wire s_den_o;
- wire [15:0]s_do_i;
- wire s_drdy_i;
- wire s_dwe_o;
- wire s_rst_o;
- wire wr_control_reg;
- wire \wr_en[2]_i_1_n_0 ;
- wire \wr_en[2]_i_2_n_0 ;
- wire \wr_en[4]_i_1_n_0 ;
- wire \wr_en[4]_i_2_n_0 ;
- wire \wr_en[4]_i_3_n_0 ;
- wire wr_probe_out_modified;
- wire [2:0]xsdb_addr_2_0_p1;
- wire [2:0]xsdb_addr_2_0_p2;
- wire xsdb_addr_8_p1;
- wire xsdb_addr_8_p2;
- wire xsdb_drdy_i_1_n_0;
- wire xsdb_rd;
- wire xsdb_wr__0;
-
- LUT3 #(
- .INIT(8'hB8))
- \Bus_data_out[0]_i_1
- (.I0(Probe_out_reg),
- .I1(xsdb_addr_8_p2),
- .I2(data_info_probe_in[0]),
- .O(\Bus_data_out[0]_i_1_n_0 ));
- LUT5 #(
- .INIT(32'h054A004A))
- \Bus_data_out[0]_i_2
- (.I0(xsdb_addr_2_0_p2[0]),
- .I1(in0),
- .I2(xsdb_addr_2_0_p2[1]),
- .I3(xsdb_addr_2_0_p2[2]),
- .I4(probe_out_modified[0]),
- .O(data_info_probe_in[0]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[10]_i_1
- (.I0(probe_out_modified[10]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[10]));
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[11]_i_1
- (.I0(probe_out_modified[11]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[11]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[12]_i_1
- (.I0(probe_out_modified[12]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[12]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[13]_i_1
- (.I0(probe_out_modified[13]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[13]));
- (* SOFT_HLUTNM = "soft_lutpair16" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[14]_i_1
- (.I0(probe_out_modified[14]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[14]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[15]_i_1
- (.I0(probe_out_modified[15]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[15]));
- LUT5 #(
- .INIT(32'h05400040))
- \Bus_data_out[1]_i_1
- (.I0(xsdb_addr_2_0_p2[0]),
- .I1(probe_out_modified[1]),
- .I2(xsdb_addr_2_0_p2[2]),
- .I3(xsdb_addr_2_0_p2[1]),
- .I4(SR),
- .O(data_info_probe_in[1]));
- LUT5 #(
- .INIT(32'h05400040))
- \Bus_data_out[2]_i_1
- (.I0(xsdb_addr_2_0_p2[0]),
- .I1(probe_out_modified[2]),
- .I2(xsdb_addr_2_0_p2[2]),
- .I3(xsdb_addr_2_0_p2[1]),
- .I4(int_cnt_rst),
- .O(data_info_probe_in[2]));
- (* SOFT_HLUTNM = "soft_lutpair11" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[3]_i_1
- (.I0(probe_out_modified[3]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[3]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[4]_i_1
- (.I0(probe_out_modified[4]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[4]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[5]_i_1
- (.I0(probe_out_modified[5]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[5]));
- (* SOFT_HLUTNM = "soft_lutpair12" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[6]_i_1
- (.I0(probe_out_modified[6]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[6]));
- (* SOFT_HLUTNM = "soft_lutpair13" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[7]_i_1
- (.I0(probe_out_modified[7]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[7]));
- (* SOFT_HLUTNM = "soft_lutpair14" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[8]_i_1
- (.I0(probe_out_modified[8]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[8]));
- (* SOFT_HLUTNM = "soft_lutpair15" *)
- LUT4 #(
- .INIT(16'h0008))
- \Bus_data_out[9]_i_1
- (.I0(probe_out_modified[9]),
- .I1(xsdb_addr_2_0_p2[2]),
- .I2(xsdb_addr_2_0_p2[0]),
- .I3(xsdb_addr_2_0_p2[1]),
- .O(data_info_probe_in[9]));
- FDRE \Bus_data_out_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(\Bus_data_out[0]_i_1_n_0 ),
- .Q(s_do_i[0]),
- .R(1'b0));
- FDRE \Bus_data_out_reg[10]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[10]),
- .Q(s_do_i[10]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[11]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[11]),
- .Q(s_do_i[11]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[12]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[12]),
- .Q(s_do_i[12]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[13]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[13]),
- .Q(s_do_i[13]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[14]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[14]),
- .Q(s_do_i[14]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[15]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[15]),
- .Q(s_do_i[15]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[1]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[1]),
- .Q(s_do_i[1]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[2]),
- .Q(s_do_i[2]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[3]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[3]),
- .Q(s_do_i[3]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[4]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[4]),
- .Q(s_do_i[4]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[5]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[5]),
- .Q(s_do_i[5]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[6]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[6]),
- .Q(s_do_i[6]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[7]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[7]),
- .Q(s_do_i[7]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[8]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[8]),
- .Q(s_do_i[8]),
- .R(xsdb_addr_8_p2));
- FDRE \Bus_data_out_reg[9]
- (.C(out),
- .CE(1'b1),
- .D(data_info_probe_in[9]),
- .Q(s_do_i[9]),
- .R(xsdb_addr_8_p2));
- LUT2 #(
- .INIT(4'h8))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_2
- (.I0(s_den_o),
- .I1(s_dwe_o),
- .O(xsdb_wr__0));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_4
- (.I0(s_daddr_o[14]),
- .I1(s_daddr_o[15]),
- .I2(s_daddr_o[12]),
- .I3(s_daddr_o[13]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_6
- (.I0(s_daddr_o[6]),
- .I1(s_daddr_o[7]),
- .I2(s_daddr_o[4]),
- .I3(s_daddr_o[5]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ));
- LUT3 #(
- .INIT(8'hB8))
- clear_int_i_1
- (.I0(Q[1]),
- .I1(wr_control_reg),
- .I2(SR),
- .O(clear_int_i_1_n_0));
- FDRE clear_int_reg
- (.C(out),
- .CE(1'b1),
- .D(clear_int_i_1_n_0),
- .Q(SR),
- .R(s_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT3 #(
- .INIT(8'hB8))
- committ_int_i_1
- (.I0(Q[0]),
- .I1(wr_control_reg),
- .I2(in0),
- .O(committ_int_i_1_n_0));
- FDRE committ_int_reg
- (.C(out),
- .CE(1'b1),
- .D(committ_int_i_1_n_0),
- .Q(in0),
- .R(s_rst_o));
- (* SOFT_HLUTNM = "soft_lutpair17" *)
- LUT3 #(
- .INIT(8'hB8))
- int_cnt_rst_i_1
- (.I0(Q[2]),
- .I1(wr_control_reg),
- .I2(int_cnt_rst),
- .O(int_cnt_rst_i_1_n_0));
- FDRE int_cnt_rst_reg
- (.C(out),
- .CE(1'b1),
- .D(int_cnt_rst_i_1_n_0),
- .Q(int_cnt_rst),
- .R(s_rst_o));
- FDRE \probe_out_modified_reg[0]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[0]),
- .Q(probe_out_modified[0]),
- .R(SR));
- FDRE \probe_out_modified_reg[10]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[10]),
- .Q(probe_out_modified[10]),
- .R(SR));
- FDRE \probe_out_modified_reg[11]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[11]),
- .Q(probe_out_modified[11]),
- .R(SR));
- FDRE \probe_out_modified_reg[12]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[12]),
- .Q(probe_out_modified[12]),
- .R(SR));
- FDRE \probe_out_modified_reg[13]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[13]),
- .Q(probe_out_modified[13]),
- .R(SR));
- FDRE \probe_out_modified_reg[14]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[14]),
- .Q(probe_out_modified[14]),
- .R(SR));
- FDRE \probe_out_modified_reg[15]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[15]),
- .Q(probe_out_modified[15]),
- .R(SR));
- FDRE \probe_out_modified_reg[1]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[1]),
- .Q(probe_out_modified[1]),
- .R(SR));
- FDRE \probe_out_modified_reg[2]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[2]),
- .Q(probe_out_modified[2]),
- .R(SR));
- FDRE \probe_out_modified_reg[3]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[3]),
- .Q(probe_out_modified[3]),
- .R(SR));
- FDRE \probe_out_modified_reg[4]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[4]),
- .Q(probe_out_modified[4]),
- .R(SR));
- FDRE \probe_out_modified_reg[5]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[5]),
- .Q(probe_out_modified[5]),
- .R(SR));
- FDRE \probe_out_modified_reg[6]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[6]),
- .Q(probe_out_modified[6]),
- .R(SR));
- FDRE \probe_out_modified_reg[7]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[7]),
- .Q(probe_out_modified[7]),
- .R(SR));
- FDRE \probe_out_modified_reg[8]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[8]),
- .Q(probe_out_modified[8]),
- .R(SR));
- FDRE \probe_out_modified_reg[9]
- (.C(out),
- .CE(wr_probe_out_modified),
- .D(Q[9]),
- .Q(probe_out_modified[9]),
- .R(SR));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT2 #(
- .INIT(4'h2))
- rd_en_p1_i_1
- (.I0(s_den_o),
- .I1(s_dwe_o),
- .O(xsdb_rd));
- FDRE rd_en_p1_reg
- (.C(out),
- .CE(1'b1),
- .D(xsdb_rd),
- .Q(rd_en_p1),
- .R(s_rst_o));
- FDRE rd_en_p2_reg
- (.C(out),
- .CE(1'b1),
- .D(rd_en_p1),
- .Q(rd_en_p2),
- .R(s_rst_o));
- LUT6 #(
- .INIT(64'h0000000200000000))
- \wr_en[2]_i_1
- (.I0(xsdb_wr__0),
- .I1(\wr_en[4]_i_2_n_0 ),
- .I2(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ),
- .I3(\wr_en[2]_i_2_n_0 ),
- .I4(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ),
- .I5(s_daddr_o[1]),
- .O(\wr_en[2]_i_1_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \wr_en[2]_i_2
- (.I0(s_daddr_o[2]),
- .I1(s_daddr_o[3]),
- .I2(s_daddr_o[0]),
- .I3(s_daddr_o[16]),
- .O(\wr_en[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h0000000200000000))
- \wr_en[4]_i_1
- (.I0(xsdb_wr__0),
- .I1(\wr_en[4]_i_2_n_0 ),
- .I2(\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 ),
- .I3(\wr_en[4]_i_3_n_0 ),
- .I4(\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 ),
- .I5(s_daddr_o[2]),
- .O(\wr_en[4]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \wr_en[4]_i_2
- (.I0(s_daddr_o[10]),
- .I1(s_daddr_o[11]),
- .I2(s_daddr_o[8]),
- .I3(s_daddr_o[9]),
- .O(\wr_en[4]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair10" *)
- LUT4 #(
- .INIT(16'hFFFE))
- \wr_en[4]_i_3
- (.I0(s_daddr_o[16]),
- .I1(s_daddr_o[3]),
- .I2(s_daddr_o[0]),
- .I3(s_daddr_o[1]),
- .O(\wr_en[4]_i_3_n_0 ));
- FDRE \wr_en_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(\wr_en[2]_i_1_n_0 ),
- .Q(wr_control_reg),
- .R(1'b0));
- FDRE \wr_en_reg[4]
- (.C(out),
- .CE(1'b1),
- .D(\wr_en[4]_i_1_n_0 ),
- .Q(wr_probe_out_modified),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p1_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[0]),
- .Q(xsdb_addr_2_0_p1[0]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p1_reg[1]
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[1]),
- .Q(xsdb_addr_2_0_p1[1]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p1_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[2]),
- .Q(xsdb_addr_2_0_p1[2]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p2_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_2_0_p1[0]),
- .Q(xsdb_addr_2_0_p2[0]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p2_reg[1]
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_2_0_p1[1]),
- .Q(xsdb_addr_2_0_p2[1]),
- .R(1'b0));
- FDRE \xsdb_addr_2_0_p2_reg[2]
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_2_0_p1[2]),
- .Q(xsdb_addr_2_0_p2[2]),
- .R(1'b0));
- FDRE xsdb_addr_8_p1_reg
- (.C(out),
- .CE(1'b1),
- .D(s_daddr_o[8]),
- .Q(xsdb_addr_8_p1),
- .R(1'b0));
- FDRE xsdb_addr_8_p2_reg
- (.C(out),
- .CE(1'b1),
- .D(xsdb_addr_8_p1),
- .Q(xsdb_addr_8_p2),
- .R(1'b0));
- (* SOFT_HLUTNM = "soft_lutpair18" *)
- LUT3 #(
- .INIT(8'hF8))
- xsdb_drdy_i_1
- (.I0(s_dwe_o),
- .I1(s_den_o),
- .I2(rd_en_p2),
- .O(xsdb_drdy_i_1_n_0));
- FDRE xsdb_drdy_reg
- (.C(out),
- .CE(1'b1),
- .D(xsdb_drdy_i_1_n_0),
- .Q(s_drdy_i),
- .R(s_rst_o));
-endmodule
-
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_probe_out_all
- (probe_out0,
- Probe_out_reg,
- SR,
- in0,
- clk,
- out,
- xsdb_wr__0,
- \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ,
- \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ,
- s_daddr_o,
- Q);
- output [0:0]probe_out0;
- output [0:0]Probe_out_reg;
- input [0:0]SR;
- input in0;
- input clk;
- input out;
- input xsdb_wr__0;
- input \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ;
- input \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ;
- input [8:0]s_daddr_o;
- input [0:0]Q;
-
- (* async_reg = "true" *) wire Committ_1;
- (* async_reg = "true" *) wire Committ_2;
- wire \G_PROBE_OUT[0].PROBE_OUT0_INST_n_1 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out[0]_i_5_n_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ;
- wire \G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ;
- wire \G_PROBE_OUT[0].wr_probe_out_reg_n_0_[0] ;
- wire [0:0]Probe_out_reg;
- wire [0:0]Q;
- wire [0:0]SR;
- wire clk;
- wire in0;
- wire out;
- wire [0:0]probe_out0;
- wire [8:0]s_daddr_o;
- wire xsdb_wr__0;
-
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- FDRE Committ_1_reg
- (.C(clk),
- .CE(1'b1),
- .D(in0),
- .Q(Committ_1),
- .R(1'b0));
- (* ASYNC_REG *)
- (* KEEP = "yes" *)
- FDRE Committ_2_reg
- (.C(clk),
- .CE(1'b1),
- .D(Committ_1),
- .Q(Committ_2),
- .R(1'b0));
- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_probe_out_one \G_PROBE_OUT[0].PROBE_OUT0_INST
- (.Q(Q),
- .SR(SR),
- .clk(clk),
- .\data_int_reg[0]_0 (\G_PROBE_OUT[0].PROBE_OUT0_INST_n_1 ),
- .\data_int_reg[0]_1 (out),
- .\data_int_reg[0]_2 (\G_PROBE_OUT[0].wr_probe_out_reg_n_0_[0] ),
- .out(Committ_2),
- .probe_out0(probe_out0));
- LUT6 #(
- .INIT(64'h0000000200000000))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_1
- (.I0(xsdb_wr__0),
- .I1(\G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0 ),
- .I2(\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 ),
- .I3(\G_PROBE_OUT[0].wr_probe_out[0]_i_5_n_0 ),
- .I4(\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 ),
- .I5(s_daddr_o[4]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_3
- (.I0(s_daddr_o[6]),
- .I1(s_daddr_o[7]),
- .I2(s_daddr_o[8]),
- .I3(s_daddr_o[5]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_3_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \G_PROBE_OUT[0].wr_probe_out[0]_i_5
- (.I0(s_daddr_o[2]),
- .I1(s_daddr_o[3]),
- .I2(s_daddr_o[0]),
- .I3(s_daddr_o[1]),
- .O(\G_PROBE_OUT[0].wr_probe_out[0]_i_5_n_0 ));
- FDRE \G_PROBE_OUT[0].wr_probe_out_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(\G_PROBE_OUT[0].wr_probe_out[0]_i_1_n_0 ),
- .Q(\G_PROBE_OUT[0].wr_probe_out_reg_n_0_[0] ),
- .R(1'b0));
- FDRE \Probe_out_reg_int_reg[0]
- (.C(out),
- .CE(1'b1),
- .D(\G_PROBE_OUT[0].PROBE_OUT0_INST_n_1 ),
- .Q(Probe_out_reg),
- .R(1'b0));
-endmodule
-
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_probe_out_one
- (probe_out0,
- \data_int_reg[0]_0 ,
- SR,
- out,
- clk,
- \data_int_reg[0]_1 ,
- Q,
- \data_int_reg[0]_2 );
- output [0:0]probe_out0;
- output \data_int_reg[0]_0 ;
- input [0:0]SR;
- input out;
- input clk;
- input \data_int_reg[0]_1 ;
- input [0:0]Q;
- input \data_int_reg[0]_2 ;
-
- wire [0:0]Q;
- (* DIRECT_RESET *) wire [0:0]SR;
- wire clk;
- wire \data_int[0]_i_1_n_0 ;
- wire \data_int_reg[0]_0 ;
- wire \data_int_reg[0]_1 ;
- wire \data_int_reg[0]_2 ;
- wire out;
- (* DONT_TOUCH *) wire [0:0]probe_out0;
-
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- FDRE \Probe_out_reg[0]
- (.C(clk),
- .CE(out),
- .D(\data_int_reg[0]_0 ),
- .Q(probe_out0),
- .R(SR));
- LUT3 #(
- .INIT(8'hB8))
- \data_int[0]_i_1
- (.I0(Q),
- .I1(\data_int_reg[0]_2 ),
- .I2(\data_int_reg[0]_0 ),
- .O(\data_int[0]_i_1_n_0 ));
- FDRE \data_int_reg[0]
- (.C(\data_int_reg[0]_1 ),
- .CE(1'b1),
- .D(\data_int[0]_i_1_n_0 ),
- .Q(\data_int_reg[0]_0 ),
- .R(SR));
-endmodule
-
-(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *)
-(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *)
-(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
-(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "0" *) (* C_EN_SYNCHRONIZATION = "1" *)
-(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *)
-(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "0" *)
-(* C_NUM_PROBE_OUT = "1" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *)
-(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *)
-(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *)
-(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *)
-(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *)
-(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *)
-(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *)
-(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *)
-(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *)
-(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *)
-(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *)
-(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *)
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-(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *)
-(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *)
-(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *)
-(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *)
-(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *)
-(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *)
-(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *)
-(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *)
-(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *)
-(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *)
-(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *)
-(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *)
-(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *)
-(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *)
-(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *)
-(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *)
-(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *)
-(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *)
-(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *)
-(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *)
-(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *)
-(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *)
-(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *)
-(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *)
-(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *)
-(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *)
-(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *)
-(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *)
-(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *)
-(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *)
-(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *)
-(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *)
-(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *)
-(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *)
-(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *)
-(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *)
-(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *)
-(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *)
-(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *)
-(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *)
-(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *)
-(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *)
-(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *)
-(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *)
-(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *)
-(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
-(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *)
-(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *)
-(* C_XDEVICEFAMILY = "zynq" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *)
-(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
-(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
-(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
-(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
-(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
-(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
-(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
-(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
-(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
-(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
-(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
-(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_TOTAL_PROBE_IN_WIDTH = "0" *)
-(* LC_TOTAL_PROBE_OUT_WIDTH = "1" *) (* dont_touch = "true" *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_vio
- (clk,
- probe_in0,
- probe_in1,
- probe_in2,
- probe_in3,
- probe_in4,
- probe_in5,
- probe_in6,
- probe_in7,
- probe_in8,
- probe_in9,
- probe_in10,
- probe_in11,
- probe_in12,
- probe_in13,
- probe_in14,
- probe_in15,
- probe_in16,
- probe_in17,
- probe_in18,
- probe_in19,
- probe_in20,
- probe_in21,
- probe_in22,
- probe_in23,
- probe_in24,
- probe_in25,
- probe_in26,
- probe_in27,
- probe_in28,
- probe_in29,
- probe_in30,
- probe_in31,
- probe_in32,
- probe_in33,
- probe_in34,
- probe_in35,
- probe_in36,
- probe_in37,
- probe_in38,
- probe_in39,
- probe_in40,
- probe_in41,
- probe_in42,
- probe_in43,
- probe_in44,
- probe_in45,
- probe_in46,
- probe_in47,
- probe_in48,
- probe_in49,
- probe_in50,
- probe_in51,
- probe_in52,
- probe_in53,
- probe_in54,
- probe_in55,
- probe_in56,
- probe_in57,
- probe_in58,
- probe_in59,
- probe_in60,
- probe_in61,
- probe_in62,
- probe_in63,
- probe_in64,
- probe_in65,
- probe_in66,
- probe_in67,
- probe_in68,
- probe_in69,
- probe_in70,
- probe_in71,
- probe_in72,
- probe_in73,
- probe_in74,
- probe_in75,
- probe_in76,
- probe_in77,
- probe_in78,
- probe_in79,
- probe_in80,
- probe_in81,
- probe_in82,
- probe_in83,
- probe_in84,
- probe_in85,
- probe_in86,
- probe_in87,
- probe_in88,
- probe_in89,
- probe_in90,
- probe_in91,
- probe_in92,
- probe_in93,
- probe_in94,
- probe_in95,
- probe_in96,
- probe_in97,
- probe_in98,
- probe_in99,
- probe_in100,
- probe_in101,
- probe_in102,
- probe_in103,
- probe_in104,
- probe_in105,
- probe_in106,
- probe_in107,
- probe_in108,
- probe_in109,
- probe_in110,
- probe_in111,
- probe_in112,
- probe_in113,
- probe_in114,
- probe_in115,
- probe_in116,
- probe_in117,
- probe_in118,
- probe_in119,
- probe_in120,
- probe_in121,
- probe_in122,
- probe_in123,
- probe_in124,
- probe_in125,
- probe_in126,
- probe_in127,
- probe_in128,
- probe_in129,
- probe_in130,
- probe_in131,
- probe_in132,
- probe_in133,
- probe_in134,
- probe_in135,
- probe_in136,
- probe_in137,
- probe_in138,
- probe_in139,
- probe_in140,
- probe_in141,
- probe_in142,
- probe_in143,
- probe_in144,
- probe_in145,
- probe_in146,
- probe_in147,
- probe_in148,
- probe_in149,
- probe_in150,
- probe_in151,
- probe_in152,
- probe_in153,
- probe_in154,
- probe_in155,
- probe_in156,
- probe_in157,
- probe_in158,
- probe_in159,
- probe_in160,
- probe_in161,
- probe_in162,
- probe_in163,
- probe_in164,
- probe_in165,
- probe_in166,
- probe_in167,
- probe_in168,
- probe_in169,
- probe_in170,
- probe_in171,
- probe_in172,
- probe_in173,
- probe_in174,
- probe_in175,
- probe_in176,
- probe_in177,
- probe_in178,
- probe_in179,
- probe_in180,
- probe_in181,
- probe_in182,
- probe_in183,
- probe_in184,
- probe_in185,
- probe_in186,
- probe_in187,
- probe_in188,
- probe_in189,
- probe_in190,
- probe_in191,
- probe_in192,
- probe_in193,
- probe_in194,
- probe_in195,
- probe_in196,
- probe_in197,
- probe_in198,
- probe_in199,
- probe_in200,
- probe_in201,
- probe_in202,
- probe_in203,
- probe_in204,
- probe_in205,
- probe_in206,
- probe_in207,
- probe_in208,
- probe_in209,
- probe_in210,
- probe_in211,
- probe_in212,
- probe_in213,
- probe_in214,
- probe_in215,
- probe_in216,
- probe_in217,
- probe_in218,
- probe_in219,
- probe_in220,
- probe_in221,
- probe_in222,
- probe_in223,
- probe_in224,
- probe_in225,
- probe_in226,
- probe_in227,
- probe_in228,
- probe_in229,
- probe_in230,
- probe_in231,
- probe_in232,
- probe_in233,
- probe_in234,
- probe_in235,
- probe_in236,
- probe_in237,
- probe_in238,
- probe_in239,
- probe_in240,
- probe_in241,
- probe_in242,
- probe_in243,
- probe_in244,
- probe_in245,
- probe_in246,
- probe_in247,
- probe_in248,
- probe_in249,
- probe_in250,
- probe_in251,
- probe_in252,
- probe_in253,
- probe_in254,
- probe_in255,
- sl_iport0,
- sl_oport0,
- probe_out0,
- probe_out1,
- probe_out2,
- probe_out3,
- probe_out4,
- probe_out5,
- probe_out6,
- probe_out7,
- probe_out8,
- probe_out9,
- probe_out10,
- probe_out11,
- probe_out12,
- probe_out13,
- probe_out14,
- probe_out15,
- probe_out16,
- probe_out17,
- probe_out18,
- probe_out19,
- probe_out20,
- probe_out21,
- probe_out22,
- probe_out23,
- probe_out24,
- probe_out25,
- probe_out26,
- probe_out27,
- probe_out28,
- probe_out29,
- probe_out30,
- probe_out31,
- probe_out32,
- probe_out33,
- probe_out34,
- probe_out35,
- probe_out36,
- probe_out37,
- probe_out38,
- probe_out39,
- probe_out40,
- probe_out41,
- probe_out42,
- probe_out43,
- probe_out44,
- probe_out45,
- probe_out46,
- probe_out47,
- probe_out48,
- probe_out49,
- probe_out50,
- probe_out51,
- probe_out52,
- probe_out53,
- probe_out54,
- probe_out55,
- probe_out56,
- probe_out57,
- probe_out58,
- probe_out59,
- probe_out60,
- probe_out61,
- probe_out62,
- probe_out63,
- probe_out64,
- probe_out65,
- probe_out66,
- probe_out67,
- probe_out68,
- probe_out69,
- probe_out70,
- probe_out71,
- probe_out72,
- probe_out73,
- probe_out74,
- probe_out75,
- probe_out76,
- probe_out77,
- probe_out78,
- probe_out79,
- probe_out80,
- probe_out81,
- probe_out82,
- probe_out83,
- probe_out84,
- probe_out85,
- probe_out86,
- probe_out87,
- probe_out88,
- probe_out89,
- probe_out90,
- probe_out91,
- probe_out92,
- probe_out93,
- probe_out94,
- probe_out95,
- probe_out96,
- probe_out97,
- probe_out98,
- probe_out99,
- probe_out100,
- probe_out101,
- probe_out102,
- probe_out103,
- probe_out104,
- probe_out105,
- probe_out106,
- probe_out107,
- probe_out108,
- probe_out109,
- probe_out110,
- probe_out111,
- probe_out112,
- probe_out113,
- probe_out114,
- probe_out115,
- probe_out116,
- probe_out117,
- probe_out118,
- probe_out119,
- probe_out120,
- probe_out121,
- probe_out122,
- probe_out123,
- probe_out124,
- probe_out125,
- probe_out126,
- probe_out127,
- probe_out128,
- probe_out129,
- probe_out130,
- probe_out131,
- probe_out132,
- probe_out133,
- probe_out134,
- probe_out135,
- probe_out136,
- probe_out137,
- probe_out138,
- probe_out139,
- probe_out140,
- probe_out141,
- probe_out142,
- probe_out143,
- probe_out144,
- probe_out145,
- probe_out146,
- probe_out147,
- probe_out148,
- probe_out149,
- probe_out150,
- probe_out151,
- probe_out152,
- probe_out153,
- probe_out154,
- probe_out155,
- probe_out156,
- probe_out157,
- probe_out158,
- probe_out159,
- probe_out160,
- probe_out161,
- probe_out162,
- probe_out163,
- probe_out164,
- probe_out165,
- probe_out166,
- probe_out167,
- probe_out168,
- probe_out169,
- probe_out170,
- probe_out171,
- probe_out172,
- probe_out173,
- probe_out174,
- probe_out175,
- probe_out176,
- probe_out177,
- probe_out178,
- probe_out179,
- probe_out180,
- probe_out181,
- probe_out182,
- probe_out183,
- probe_out184,
- probe_out185,
- probe_out186,
- probe_out187,
- probe_out188,
- probe_out189,
- probe_out190,
- probe_out191,
- probe_out192,
- probe_out193,
- probe_out194,
- probe_out195,
- probe_out196,
- probe_out197,
- probe_out198,
- probe_out199,
- probe_out200,
- probe_out201,
- probe_out202,
- probe_out203,
- probe_out204,
- probe_out205,
- probe_out206,
- probe_out207,
- probe_out208,
- probe_out209,
- probe_out210,
- probe_out211,
- probe_out212,
- probe_out213,
- probe_out214,
- probe_out215,
- probe_out216,
- probe_out217,
- probe_out218,
- probe_out219,
- probe_out220,
- probe_out221,
- probe_out222,
- probe_out223,
- probe_out224,
- probe_out225,
- probe_out226,
- probe_out227,
- probe_out228,
- probe_out229,
- probe_out230,
- probe_out231,
- probe_out232,
- probe_out233,
- probe_out234,
- probe_out235,
- probe_out236,
- probe_out237,
- probe_out238,
- probe_out239,
- probe_out240,
- probe_out241,
- probe_out242,
- probe_out243,
- probe_out244,
- probe_out245,
- probe_out246,
- probe_out247,
- probe_out248,
- probe_out249,
- probe_out250,
- probe_out251,
- probe_out252,
- probe_out253,
- probe_out254,
- probe_out255);
- input clk;
- input [0:0]probe_in0;
- input [0:0]probe_in1;
- input [0:0]probe_in2;
- input [0:0]probe_in3;
- input [0:0]probe_in4;
- input [0:0]probe_in5;
- input [0:0]probe_in6;
- input [0:0]probe_in7;
- input [0:0]probe_in8;
- input [0:0]probe_in9;
- input [0:0]probe_in10;
- input [0:0]probe_in11;
- input [0:0]probe_in12;
- input [0:0]probe_in13;
- input [0:0]probe_in14;
- input [0:0]probe_in15;
- input [0:0]probe_in16;
- input [0:0]probe_in17;
- input [0:0]probe_in18;
- input [0:0]probe_in19;
- input [0:0]probe_in20;
- input [0:0]probe_in21;
- input [0:0]probe_in22;
- input [0:0]probe_in23;
- input [0:0]probe_in24;
- input [0:0]probe_in25;
- input [0:0]probe_in26;
- input [0:0]probe_in27;
- input [0:0]probe_in28;
- input [0:0]probe_in29;
- input [0:0]probe_in30;
- input [0:0]probe_in31;
- input [0:0]probe_in32;
- input [0:0]probe_in33;
- input [0:0]probe_in34;
- input [0:0]probe_in35;
- input [0:0]probe_in36;
- input [0:0]probe_in37;
- input [0:0]probe_in38;
- input [0:0]probe_in39;
- input [0:0]probe_in40;
- input [0:0]probe_in41;
- input [0:0]probe_in42;
- input [0:0]probe_in43;
- input [0:0]probe_in44;
- input [0:0]probe_in45;
- input [0:0]probe_in46;
- input [0:0]probe_in47;
- input [0:0]probe_in48;
- input [0:0]probe_in49;
- input [0:0]probe_in50;
- input [0:0]probe_in51;
- input [0:0]probe_in52;
- input [0:0]probe_in53;
- input [0:0]probe_in54;
- input [0:0]probe_in55;
- input [0:0]probe_in56;
- input [0:0]probe_in57;
- input [0:0]probe_in58;
- input [0:0]probe_in59;
- input [0:0]probe_in60;
- input [0:0]probe_in61;
- input [0:0]probe_in62;
- input [0:0]probe_in63;
- input [0:0]probe_in64;
- input [0:0]probe_in65;
- input [0:0]probe_in66;
- input [0:0]probe_in67;
- input [0:0]probe_in68;
- input [0:0]probe_in69;
- input [0:0]probe_in70;
- input [0:0]probe_in71;
- input [0:0]probe_in72;
- input [0:0]probe_in73;
- input [0:0]probe_in74;
- input [0:0]probe_in75;
- input [0:0]probe_in76;
- input [0:0]probe_in77;
- input [0:0]probe_in78;
- input [0:0]probe_in79;
- input [0:0]probe_in80;
- input [0:0]probe_in81;
- input [0:0]probe_in82;
- input [0:0]probe_in83;
- input [0:0]probe_in84;
- input [0:0]probe_in85;
- input [0:0]probe_in86;
- input [0:0]probe_in87;
- input [0:0]probe_in88;
- input [0:0]probe_in89;
- input [0:0]probe_in90;
- input [0:0]probe_in91;
- input [0:0]probe_in92;
- input [0:0]probe_in93;
- input [0:0]probe_in94;
- input [0:0]probe_in95;
- input [0:0]probe_in96;
- input [0:0]probe_in97;
- input [0:0]probe_in98;
- input [0:0]probe_in99;
- input [0:0]probe_in100;
- input [0:0]probe_in101;
- input [0:0]probe_in102;
- input [0:0]probe_in103;
- input [0:0]probe_in104;
- input [0:0]probe_in105;
- input [0:0]probe_in106;
- input [0:0]probe_in107;
- input [0:0]probe_in108;
- input [0:0]probe_in109;
- input [0:0]probe_in110;
- input [0:0]probe_in111;
- input [0:0]probe_in112;
- input [0:0]probe_in113;
- input [0:0]probe_in114;
- input [0:0]probe_in115;
- input [0:0]probe_in116;
- input [0:0]probe_in117;
- input [0:0]probe_in118;
- input [0:0]probe_in119;
- input [0:0]probe_in120;
- input [0:0]probe_in121;
- input [0:0]probe_in122;
- input [0:0]probe_in123;
- input [0:0]probe_in124;
- input [0:0]probe_in125;
- input [0:0]probe_in126;
- input [0:0]probe_in127;
- input [0:0]probe_in128;
- input [0:0]probe_in129;
- input [0:0]probe_in130;
- input [0:0]probe_in131;
- input [0:0]probe_in132;
- input [0:0]probe_in133;
- input [0:0]probe_in134;
- input [0:0]probe_in135;
- input [0:0]probe_in136;
- input [0:0]probe_in137;
- input [0:0]probe_in138;
- input [0:0]probe_in139;
- input [0:0]probe_in140;
- input [0:0]probe_in141;
- input [0:0]probe_in142;
- input [0:0]probe_in143;
- input [0:0]probe_in144;
- input [0:0]probe_in145;
- input [0:0]probe_in146;
- input [0:0]probe_in147;
- input [0:0]probe_in148;
- input [0:0]probe_in149;
- input [0:0]probe_in150;
- input [0:0]probe_in151;
- input [0:0]probe_in152;
- input [0:0]probe_in153;
- input [0:0]probe_in154;
- input [0:0]probe_in155;
- input [0:0]probe_in156;
- input [0:0]probe_in157;
- input [0:0]probe_in158;
- input [0:0]probe_in159;
- input [0:0]probe_in160;
- input [0:0]probe_in161;
- input [0:0]probe_in162;
- input [0:0]probe_in163;
- input [0:0]probe_in164;
- input [0:0]probe_in165;
- input [0:0]probe_in166;
- input [0:0]probe_in167;
- input [0:0]probe_in168;
- input [0:0]probe_in169;
- input [0:0]probe_in170;
- input [0:0]probe_in171;
- input [0:0]probe_in172;
- input [0:0]probe_in173;
- input [0:0]probe_in174;
- input [0:0]probe_in175;
- input [0:0]probe_in176;
- input [0:0]probe_in177;
- input [0:0]probe_in178;
- input [0:0]probe_in179;
- input [0:0]probe_in180;
- input [0:0]probe_in181;
- input [0:0]probe_in182;
- input [0:0]probe_in183;
- input [0:0]probe_in184;
- input [0:0]probe_in185;
- input [0:0]probe_in186;
- input [0:0]probe_in187;
- input [0:0]probe_in188;
- input [0:0]probe_in189;
- input [0:0]probe_in190;
- input [0:0]probe_in191;
- input [0:0]probe_in192;
- input [0:0]probe_in193;
- input [0:0]probe_in194;
- input [0:0]probe_in195;
- input [0:0]probe_in196;
- input [0:0]probe_in197;
- input [0:0]probe_in198;
- input [0:0]probe_in199;
- input [0:0]probe_in200;
- input [0:0]probe_in201;
- input [0:0]probe_in202;
- input [0:0]probe_in203;
- input [0:0]probe_in204;
- input [0:0]probe_in205;
- input [0:0]probe_in206;
- input [0:0]probe_in207;
- input [0:0]probe_in208;
- input [0:0]probe_in209;
- input [0:0]probe_in210;
- input [0:0]probe_in211;
- input [0:0]probe_in212;
- input [0:0]probe_in213;
- input [0:0]probe_in214;
- input [0:0]probe_in215;
- input [0:0]probe_in216;
- input [0:0]probe_in217;
- input [0:0]probe_in218;
- input [0:0]probe_in219;
- input [0:0]probe_in220;
- input [0:0]probe_in221;
- input [0:0]probe_in222;
- input [0:0]probe_in223;
- input [0:0]probe_in224;
- input [0:0]probe_in225;
- input [0:0]probe_in226;
- input [0:0]probe_in227;
- input [0:0]probe_in228;
- input [0:0]probe_in229;
- input [0:0]probe_in230;
- input [0:0]probe_in231;
- input [0:0]probe_in232;
- input [0:0]probe_in233;
- input [0:0]probe_in234;
- input [0:0]probe_in235;
- input [0:0]probe_in236;
- input [0:0]probe_in237;
- input [0:0]probe_in238;
- input [0:0]probe_in239;
- input [0:0]probe_in240;
- input [0:0]probe_in241;
- input [0:0]probe_in242;
- input [0:0]probe_in243;
- input [0:0]probe_in244;
- input [0:0]probe_in245;
- input [0:0]probe_in246;
- input [0:0]probe_in247;
- input [0:0]probe_in248;
- input [0:0]probe_in249;
- input [0:0]probe_in250;
- input [0:0]probe_in251;
- input [0:0]probe_in252;
- input [0:0]probe_in253;
- input [0:0]probe_in254;
- input [0:0]probe_in255;
- (* dont_touch = "true" *) input [36:0]sl_iport0;
- (* dont_touch = "true" *) output [16:0]sl_oport0;
- output [0:0]probe_out0;
- output [0:0]probe_out1;
- output [0:0]probe_out2;
- output [0:0]probe_out3;
- output [0:0]probe_out4;
- output [0:0]probe_out5;
- output [0:0]probe_out6;
- output [0:0]probe_out7;
- output [0:0]probe_out8;
- output [0:0]probe_out9;
- output [0:0]probe_out10;
- output [0:0]probe_out11;
- output [0:0]probe_out12;
- output [0:0]probe_out13;
- output [0:0]probe_out14;
- output [0:0]probe_out15;
- output [0:0]probe_out16;
- output [0:0]probe_out17;
- output [0:0]probe_out18;
- output [0:0]probe_out19;
- output [0:0]probe_out20;
- output [0:0]probe_out21;
- output [0:0]probe_out22;
- output [0:0]probe_out23;
- output [0:0]probe_out24;
- output [0:0]probe_out25;
- output [0:0]probe_out26;
- output [0:0]probe_out27;
- output [0:0]probe_out28;
- output [0:0]probe_out29;
- output [0:0]probe_out30;
- output [0:0]probe_out31;
- output [0:0]probe_out32;
- output [0:0]probe_out33;
- output [0:0]probe_out34;
- output [0:0]probe_out35;
- output [0:0]probe_out36;
- output [0:0]probe_out37;
- output [0:0]probe_out38;
- output [0:0]probe_out39;
- output [0:0]probe_out40;
- output [0:0]probe_out41;
- output [0:0]probe_out42;
- output [0:0]probe_out43;
- output [0:0]probe_out44;
- output [0:0]probe_out45;
- output [0:0]probe_out46;
- output [0:0]probe_out47;
- output [0:0]probe_out48;
- output [0:0]probe_out49;
- output [0:0]probe_out50;
- output [0:0]probe_out51;
- output [0:0]probe_out52;
- output [0:0]probe_out53;
- output [0:0]probe_out54;
- output [0:0]probe_out55;
- output [0:0]probe_out56;
- output [0:0]probe_out57;
- output [0:0]probe_out58;
- output [0:0]probe_out59;
- output [0:0]probe_out60;
- output [0:0]probe_out61;
- output [0:0]probe_out62;
- output [0:0]probe_out63;
- output [0:0]probe_out64;
- output [0:0]probe_out65;
- output [0:0]probe_out66;
- output [0:0]probe_out67;
- output [0:0]probe_out68;
- output [0:0]probe_out69;
- output [0:0]probe_out70;
- output [0:0]probe_out71;
- output [0:0]probe_out72;
- output [0:0]probe_out73;
- output [0:0]probe_out74;
- output [0:0]probe_out75;
- output [0:0]probe_out76;
- output [0:0]probe_out77;
- output [0:0]probe_out78;
- output [0:0]probe_out79;
- output [0:0]probe_out80;
- output [0:0]probe_out81;
- output [0:0]probe_out82;
- output [0:0]probe_out83;
- output [0:0]probe_out84;
- output [0:0]probe_out85;
- output [0:0]probe_out86;
- output [0:0]probe_out87;
- output [0:0]probe_out88;
- output [0:0]probe_out89;
- output [0:0]probe_out90;
- output [0:0]probe_out91;
- output [0:0]probe_out92;
- output [0:0]probe_out93;
- output [0:0]probe_out94;
- output [0:0]probe_out95;
- output [0:0]probe_out96;
- output [0:0]probe_out97;
- output [0:0]probe_out98;
- output [0:0]probe_out99;
- output [0:0]probe_out100;
- output [0:0]probe_out101;
- output [0:0]probe_out102;
- output [0:0]probe_out103;
- output [0:0]probe_out104;
- output [0:0]probe_out105;
- output [0:0]probe_out106;
- output [0:0]probe_out107;
- output [0:0]probe_out108;
- output [0:0]probe_out109;
- output [0:0]probe_out110;
- output [0:0]probe_out111;
- output [0:0]probe_out112;
- output [0:0]probe_out113;
- output [0:0]probe_out114;
- output [0:0]probe_out115;
- output [0:0]probe_out116;
- output [0:0]probe_out117;
- output [0:0]probe_out118;
- output [0:0]probe_out119;
- output [0:0]probe_out120;
- output [0:0]probe_out121;
- output [0:0]probe_out122;
- output [0:0]probe_out123;
- output [0:0]probe_out124;
- output [0:0]probe_out125;
- output [0:0]probe_out126;
- output [0:0]probe_out127;
- output [0:0]probe_out128;
- output [0:0]probe_out129;
- output [0:0]probe_out130;
- output [0:0]probe_out131;
- output [0:0]probe_out132;
- output [0:0]probe_out133;
- output [0:0]probe_out134;
- output [0:0]probe_out135;
- output [0:0]probe_out136;
- output [0:0]probe_out137;
- output [0:0]probe_out138;
- output [0:0]probe_out139;
- output [0:0]probe_out140;
- output [0:0]probe_out141;
- output [0:0]probe_out142;
- output [0:0]probe_out143;
- output [0:0]probe_out144;
- output [0:0]probe_out145;
- output [0:0]probe_out146;
- output [0:0]probe_out147;
- output [0:0]probe_out148;
- output [0:0]probe_out149;
- output [0:0]probe_out150;
- output [0:0]probe_out151;
- output [0:0]probe_out152;
- output [0:0]probe_out153;
- output [0:0]probe_out154;
- output [0:0]probe_out155;
- output [0:0]probe_out156;
- output [0:0]probe_out157;
- output [0:0]probe_out158;
- output [0:0]probe_out159;
- output [0:0]probe_out160;
- output [0:0]probe_out161;
- output [0:0]probe_out162;
- output [0:0]probe_out163;
- output [0:0]probe_out164;
- output [0:0]probe_out165;
- output [0:0]probe_out166;
- output [0:0]probe_out167;
- output [0:0]probe_out168;
- output [0:0]probe_out169;
- output [0:0]probe_out170;
- output [0:0]probe_out171;
- output [0:0]probe_out172;
- output [0:0]probe_out173;
- output [0:0]probe_out174;
- output [0:0]probe_out175;
- output [0:0]probe_out176;
- output [0:0]probe_out177;
- output [0:0]probe_out178;
- output [0:0]probe_out179;
- output [0:0]probe_out180;
- output [0:0]probe_out181;
- output [0:0]probe_out182;
- output [0:0]probe_out183;
- output [0:0]probe_out184;
- output [0:0]probe_out185;
- output [0:0]probe_out186;
- output [0:0]probe_out187;
- output [0:0]probe_out188;
- output [0:0]probe_out189;
- output [0:0]probe_out190;
- output [0:0]probe_out191;
- output [0:0]probe_out192;
- output [0:0]probe_out193;
- output [0:0]probe_out194;
- output [0:0]probe_out195;
- output [0:0]probe_out196;
- output [0:0]probe_out197;
- output [0:0]probe_out198;
- output [0:0]probe_out199;
- output [0:0]probe_out200;
- output [0:0]probe_out201;
- output [0:0]probe_out202;
- output [0:0]probe_out203;
- output [0:0]probe_out204;
- output [0:0]probe_out205;
- output [0:0]probe_out206;
- output [0:0]probe_out207;
- output [0:0]probe_out208;
- output [0:0]probe_out209;
- output [0:0]probe_out210;
- output [0:0]probe_out211;
- output [0:0]probe_out212;
- output [0:0]probe_out213;
- output [0:0]probe_out214;
- output [0:0]probe_out215;
- output [0:0]probe_out216;
- output [0:0]probe_out217;
- output [0:0]probe_out218;
- output [0:0]probe_out219;
- output [0:0]probe_out220;
- output [0:0]probe_out221;
- output [0:0]probe_out222;
- output [0:0]probe_out223;
- output [0:0]probe_out224;
- output [0:0]probe_out225;
- output [0:0]probe_out226;
- output [0:0]probe_out227;
- output [0:0]probe_out228;
- output [0:0]probe_out229;
- output [0:0]probe_out230;
- output [0:0]probe_out231;
- output [0:0]probe_out232;
- output [0:0]probe_out233;
- output [0:0]probe_out234;
- output [0:0]probe_out235;
- output [0:0]probe_out236;
- output [0:0]probe_out237;
- output [0:0]probe_out238;
- output [0:0]probe_out239;
- output [0:0]probe_out240;
- output [0:0]probe_out241;
- output [0:0]probe_out242;
- output [0:0]probe_out243;
- output [0:0]probe_out244;
- output [0:0]probe_out245;
- output [0:0]probe_out246;
- output [0:0]probe_out247;
- output [0:0]probe_out248;
- output [0:0]probe_out249;
- output [0:0]probe_out250;
- output [0:0]probe_out251;
- output [0:0]probe_out252;
- output [0:0]probe_out253;
- output [0:0]probe_out254;
- output [0:0]probe_out255;
-
- wire \<const0> ;
- wire DECODER_INST_n_4;
- wire DECODER_INST_n_5;
- wire [0:0]Probe_out_reg;
- wire [16:0]bus_addr;
- (* DONT_TOUCH *) wire bus_clk;
- wire \bus_data_int_reg_n_0_[10] ;
- wire \bus_data_int_reg_n_0_[11] ;
- wire \bus_data_int_reg_n_0_[12] ;
- wire \bus_data_int_reg_n_0_[13] ;
- wire \bus_data_int_reg_n_0_[14] ;
- wire \bus_data_int_reg_n_0_[15] ;
- wire \bus_data_int_reg_n_0_[2] ;
- wire \bus_data_int_reg_n_0_[3] ;
- wire \bus_data_int_reg_n_0_[4] ;
- wire \bus_data_int_reg_n_0_[5] ;
- wire \bus_data_int_reg_n_0_[6] ;
- wire \bus_data_int_reg_n_0_[7] ;
- wire \bus_data_int_reg_n_0_[8] ;
- wire \bus_data_int_reg_n_0_[9] ;
- wire bus_den;
- wire [15:0]bus_di;
- wire [15:0]bus_do;
- wire bus_drdy;
- wire bus_dwe;
- wire bus_rst;
- wire clear;
- wire clk;
- wire committ;
- wire p_0_in;
- wire p_2_in;
- wire [0:0]probe_out0;
- (* DONT_TOUCH *) wire [36:0]sl_iport0;
- (* DONT_TOUCH *) wire [16:0]sl_oport0;
- wire xsdb_wr__0;
-
- assign probe_out1[0] = \<const0> ;
- assign probe_out10[0] = \<const0> ;
- assign probe_out100[0] = \<const0> ;
- assign probe_out101[0] = \<const0> ;
- assign probe_out102[0] = \<const0> ;
- assign probe_out103[0] = \<const0> ;
- assign probe_out104[0] = \<const0> ;
- assign probe_out105[0] = \<const0> ;
- assign probe_out106[0] = \<const0> ;
- assign probe_out107[0] = \<const0> ;
- assign probe_out108[0] = \<const0> ;
- assign probe_out109[0] = \<const0> ;
- assign probe_out11[0] = \<const0> ;
- assign probe_out110[0] = \<const0> ;
- assign probe_out111[0] = \<const0> ;
- assign probe_out112[0] = \<const0> ;
- assign probe_out113[0] = \<const0> ;
- assign probe_out114[0] = \<const0> ;
- assign probe_out115[0] = \<const0> ;
- assign probe_out116[0] = \<const0> ;
- assign probe_out117[0] = \<const0> ;
- assign probe_out118[0] = \<const0> ;
- assign probe_out119[0] = \<const0> ;
- assign probe_out12[0] = \<const0> ;
- assign probe_out120[0] = \<const0> ;
- assign probe_out121[0] = \<const0> ;
- assign probe_out122[0] = \<const0> ;
- assign probe_out123[0] = \<const0> ;
- assign probe_out124[0] = \<const0> ;
- assign probe_out125[0] = \<const0> ;
- assign probe_out126[0] = \<const0> ;
- assign probe_out127[0] = \<const0> ;
- assign probe_out128[0] = \<const0> ;
- assign probe_out129[0] = \<const0> ;
- assign probe_out13[0] = \<const0> ;
- assign probe_out130[0] = \<const0> ;
- assign probe_out131[0] = \<const0> ;
- assign probe_out132[0] = \<const0> ;
- assign probe_out133[0] = \<const0> ;
- assign probe_out134[0] = \<const0> ;
- assign probe_out135[0] = \<const0> ;
- assign probe_out136[0] = \<const0> ;
- assign probe_out137[0] = \<const0> ;
- assign probe_out138[0] = \<const0> ;
- assign probe_out139[0] = \<const0> ;
- assign probe_out14[0] = \<const0> ;
- assign probe_out140[0] = \<const0> ;
- assign probe_out141[0] = \<const0> ;
- assign probe_out142[0] = \<const0> ;
- assign probe_out143[0] = \<const0> ;
- assign probe_out144[0] = \<const0> ;
- assign probe_out145[0] = \<const0> ;
- assign probe_out146[0] = \<const0> ;
- assign probe_out147[0] = \<const0> ;
- assign probe_out148[0] = \<const0> ;
- assign probe_out149[0] = \<const0> ;
- assign probe_out15[0] = \<const0> ;
- assign probe_out150[0] = \<const0> ;
- assign probe_out151[0] = \<const0> ;
- assign probe_out152[0] = \<const0> ;
- assign probe_out153[0] = \<const0> ;
- assign probe_out154[0] = \<const0> ;
- assign probe_out155[0] = \<const0> ;
- assign probe_out156[0] = \<const0> ;
- assign probe_out157[0] = \<const0> ;
- assign probe_out158[0] = \<const0> ;
- assign probe_out159[0] = \<const0> ;
- assign probe_out16[0] = \<const0> ;
- assign probe_out160[0] = \<const0> ;
- assign probe_out161[0] = \<const0> ;
- assign probe_out162[0] = \<const0> ;
- assign probe_out163[0] = \<const0> ;
- assign probe_out164[0] = \<const0> ;
- assign probe_out165[0] = \<const0> ;
- assign probe_out166[0] = \<const0> ;
- assign probe_out167[0] = \<const0> ;
- assign probe_out168[0] = \<const0> ;
- assign probe_out169[0] = \<const0> ;
- assign probe_out17[0] = \<const0> ;
- assign probe_out170[0] = \<const0> ;
- assign probe_out171[0] = \<const0> ;
- assign probe_out172[0] = \<const0> ;
- assign probe_out173[0] = \<const0> ;
- assign probe_out174[0] = \<const0> ;
- assign probe_out175[0] = \<const0> ;
- assign probe_out176[0] = \<const0> ;
- assign probe_out177[0] = \<const0> ;
- assign probe_out178[0] = \<const0> ;
- assign probe_out179[0] = \<const0> ;
- assign probe_out18[0] = \<const0> ;
- assign probe_out180[0] = \<const0> ;
- assign probe_out181[0] = \<const0> ;
- assign probe_out182[0] = \<const0> ;
- assign probe_out183[0] = \<const0> ;
- assign probe_out184[0] = \<const0> ;
- assign probe_out185[0] = \<const0> ;
- assign probe_out186[0] = \<const0> ;
- assign probe_out187[0] = \<const0> ;
- assign probe_out188[0] = \<const0> ;
- assign probe_out189[0] = \<const0> ;
- assign probe_out19[0] = \<const0> ;
- assign probe_out190[0] = \<const0> ;
- assign probe_out191[0] = \<const0> ;
- assign probe_out192[0] = \<const0> ;
- assign probe_out193[0] = \<const0> ;
- assign probe_out194[0] = \<const0> ;
- assign probe_out195[0] = \<const0> ;
- assign probe_out196[0] = \<const0> ;
- assign probe_out197[0] = \<const0> ;
- assign probe_out198[0] = \<const0> ;
- assign probe_out199[0] = \<const0> ;
- assign probe_out2[0] = \<const0> ;
- assign probe_out20[0] = \<const0> ;
- assign probe_out200[0] = \<const0> ;
- assign probe_out201[0] = \<const0> ;
- assign probe_out202[0] = \<const0> ;
- assign probe_out203[0] = \<const0> ;
- assign probe_out204[0] = \<const0> ;
- assign probe_out205[0] = \<const0> ;
- assign probe_out206[0] = \<const0> ;
- assign probe_out207[0] = \<const0> ;
- assign probe_out208[0] = \<const0> ;
- assign probe_out209[0] = \<const0> ;
- assign probe_out21[0] = \<const0> ;
- assign probe_out210[0] = \<const0> ;
- assign probe_out211[0] = \<const0> ;
- assign probe_out212[0] = \<const0> ;
- assign probe_out213[0] = \<const0> ;
- assign probe_out214[0] = \<const0> ;
- assign probe_out215[0] = \<const0> ;
- assign probe_out216[0] = \<const0> ;
- assign probe_out217[0] = \<const0> ;
- assign probe_out218[0] = \<const0> ;
- assign probe_out219[0] = \<const0> ;
- assign probe_out22[0] = \<const0> ;
- assign probe_out220[0] = \<const0> ;
- assign probe_out221[0] = \<const0> ;
- assign probe_out222[0] = \<const0> ;
- assign probe_out223[0] = \<const0> ;
- assign probe_out224[0] = \<const0> ;
- assign probe_out225[0] = \<const0> ;
- assign probe_out226[0] = \<const0> ;
- assign probe_out227[0] = \<const0> ;
- assign probe_out228[0] = \<const0> ;
- assign probe_out229[0] = \<const0> ;
- assign probe_out23[0] = \<const0> ;
- assign probe_out230[0] = \<const0> ;
- assign probe_out231[0] = \<const0> ;
- assign probe_out232[0] = \<const0> ;
- assign probe_out233[0] = \<const0> ;
- assign probe_out234[0] = \<const0> ;
- assign probe_out235[0] = \<const0> ;
- assign probe_out236[0] = \<const0> ;
- assign probe_out237[0] = \<const0> ;
- assign probe_out238[0] = \<const0> ;
- assign probe_out239[0] = \<const0> ;
- assign probe_out24[0] = \<const0> ;
- assign probe_out240[0] = \<const0> ;
- assign probe_out241[0] = \<const0> ;
- assign probe_out242[0] = \<const0> ;
- assign probe_out243[0] = \<const0> ;
- assign probe_out244[0] = \<const0> ;
- assign probe_out245[0] = \<const0> ;
- assign probe_out246[0] = \<const0> ;
- assign probe_out247[0] = \<const0> ;
- assign probe_out248[0] = \<const0> ;
- assign probe_out249[0] = \<const0> ;
- assign probe_out25[0] = \<const0> ;
- assign probe_out250[0] = \<const0> ;
- assign probe_out251[0] = \<const0> ;
- assign probe_out252[0] = \<const0> ;
- assign probe_out253[0] = \<const0> ;
- assign probe_out254[0] = \<const0> ;
- assign probe_out255[0] = \<const0> ;
- assign probe_out26[0] = \<const0> ;
- assign probe_out27[0] = \<const0> ;
- assign probe_out28[0] = \<const0> ;
- assign probe_out29[0] = \<const0> ;
- assign probe_out3[0] = \<const0> ;
- assign probe_out30[0] = \<const0> ;
- assign probe_out31[0] = \<const0> ;
- assign probe_out32[0] = \<const0> ;
- assign probe_out33[0] = \<const0> ;
- assign probe_out34[0] = \<const0> ;
- assign probe_out35[0] = \<const0> ;
- assign probe_out36[0] = \<const0> ;
- assign probe_out37[0] = \<const0> ;
- assign probe_out38[0] = \<const0> ;
- assign probe_out39[0] = \<const0> ;
- assign probe_out4[0] = \<const0> ;
- assign probe_out40[0] = \<const0> ;
- assign probe_out41[0] = \<const0> ;
- assign probe_out42[0] = \<const0> ;
- assign probe_out43[0] = \<const0> ;
- assign probe_out44[0] = \<const0> ;
- assign probe_out45[0] = \<const0> ;
- assign probe_out46[0] = \<const0> ;
- assign probe_out47[0] = \<const0> ;
- assign probe_out48[0] = \<const0> ;
- assign probe_out49[0] = \<const0> ;
- assign probe_out5[0] = \<const0> ;
- assign probe_out50[0] = \<const0> ;
- assign probe_out51[0] = \<const0> ;
- assign probe_out52[0] = \<const0> ;
- assign probe_out53[0] = \<const0> ;
- assign probe_out54[0] = \<const0> ;
- assign probe_out55[0] = \<const0> ;
- assign probe_out56[0] = \<const0> ;
- assign probe_out57[0] = \<const0> ;
- assign probe_out58[0] = \<const0> ;
- assign probe_out59[0] = \<const0> ;
- assign probe_out6[0] = \<const0> ;
- assign probe_out60[0] = \<const0> ;
- assign probe_out61[0] = \<const0> ;
- assign probe_out62[0] = \<const0> ;
- assign probe_out63[0] = \<const0> ;
- assign probe_out64[0] = \<const0> ;
- assign probe_out65[0] = \<const0> ;
- assign probe_out66[0] = \<const0> ;
- assign probe_out67[0] = \<const0> ;
- assign probe_out68[0] = \<const0> ;
- assign probe_out69[0] = \<const0> ;
- assign probe_out7[0] = \<const0> ;
- assign probe_out70[0] = \<const0> ;
- assign probe_out71[0] = \<const0> ;
- assign probe_out72[0] = \<const0> ;
- assign probe_out73[0] = \<const0> ;
- assign probe_out74[0] = \<const0> ;
- assign probe_out75[0] = \<const0> ;
- assign probe_out76[0] = \<const0> ;
- assign probe_out77[0] = \<const0> ;
- assign probe_out78[0] = \<const0> ;
- assign probe_out79[0] = \<const0> ;
- assign probe_out8[0] = \<const0> ;
- assign probe_out80[0] = \<const0> ;
- assign probe_out81[0] = \<const0> ;
- assign probe_out82[0] = \<const0> ;
- assign probe_out83[0] = \<const0> ;
- assign probe_out84[0] = \<const0> ;
- assign probe_out85[0] = \<const0> ;
- assign probe_out86[0] = \<const0> ;
- assign probe_out87[0] = \<const0> ;
- assign probe_out88[0] = \<const0> ;
- assign probe_out89[0] = \<const0> ;
- assign probe_out9[0] = \<const0> ;
- assign probe_out90[0] = \<const0> ;
- assign probe_out91[0] = \<const0> ;
- assign probe_out92[0] = \<const0> ;
- assign probe_out93[0] = \<const0> ;
- assign probe_out94[0] = \<const0> ;
- assign probe_out95[0] = \<const0> ;
- assign probe_out96[0] = \<const0> ;
- assign probe_out97[0] = \<const0> ;
- assign probe_out98[0] = \<const0> ;
- assign probe_out99[0] = \<const0> ;
- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_decoder DECODER_INST
- (.\G_PROBE_OUT[0].wr_probe_out[0]_i_4_0 (DECODER_INST_n_4),
- .\G_PROBE_OUT[0].wr_probe_out[0]_i_6_0 (DECODER_INST_n_5),
- .Probe_out_reg(Probe_out_reg),
- .Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,p_2_in}),
- .SR(clear),
- .in0(committ),
- .out(bus_clk),
- .s_daddr_o(bus_addr),
- .s_den_o(bus_den),
- .s_do_i(bus_do),
- .s_drdy_i(bus_drdy),
- .s_dwe_o(bus_dwe),
- .s_rst_o(bus_rst),
- .xsdb_wr__0(xsdb_wr__0));
- GND GND
- (.G(\<const0> ));
- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_19_probe_out_all PROBE_OUT_ALL_INST
- (.\G_PROBE_OUT[0].wr_probe_out_reg[0]_0 (DECODER_INST_n_4),
- .\G_PROBE_OUT[0].wr_probe_out_reg[0]_1 (DECODER_INST_n_5),
- .Probe_out_reg(Probe_out_reg),
- .Q(p_2_in),
- .SR(clear),
- .clk(clk),
- .in0(committ),
- .out(bus_clk),
- .probe_out0(probe_out0),
- .s_daddr_o({bus_addr[16],bus_addr[11:8],bus_addr[3:0]}),
- .xsdb_wr__0(xsdb_wr__0));
- (* C_BUILD_REVISION = "0" *)
- (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
- (* C_CORE_MAJOR_VER = "2" *)
- (* C_CORE_MINOR_VER = "0" *)
- (* C_CORE_TYPE = "2" *)
- (* C_CSE_DRV_VER = "1" *)
- (* C_MAJOR_VERSION = "2013" *)
- (* C_MINOR_VERSION = "1" *)
- (* C_NEXT_SLAVE = "0" *)
- (* C_PIPE_IFACE = "0" *)
- (* C_USE_TEST_REG = "1" *)
- (* C_XDEVICEFAMILY = "zynq" *)
- (* C_XSDB_SLAVE_TYPE = "33" *)
- (* DONT_TOUCH *)
- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
- (.s_daddr_o(bus_addr),
- .s_dclk_o(bus_clk),
- .s_den_o(bus_den),
- .s_di_o(bus_di),
- .s_do_i(bus_do),
- .s_drdy_i(bus_drdy),
- .s_dwe_o(bus_dwe),
- .s_rst_o(bus_rst),
- .sl_iport_i(sl_iport0),
- .sl_oport_o(sl_oport0));
- FDRE \bus_data_int_reg[0]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[0]),
- .Q(p_2_in),
- .R(1'b0));
- FDRE \bus_data_int_reg[10]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[10]),
- .Q(\bus_data_int_reg_n_0_[10] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[11]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[11]),
- .Q(\bus_data_int_reg_n_0_[11] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[12]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[12]),
- .Q(\bus_data_int_reg_n_0_[12] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[13]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[13]),
- .Q(\bus_data_int_reg_n_0_[13] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[14]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[14]),
- .Q(\bus_data_int_reg_n_0_[14] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[15]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[15]),
- .Q(\bus_data_int_reg_n_0_[15] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[1]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[1]),
- .Q(p_0_in),
- .R(1'b0));
- FDRE \bus_data_int_reg[2]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[2]),
- .Q(\bus_data_int_reg_n_0_[2] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[3]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[3]),
- .Q(\bus_data_int_reg_n_0_[3] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[4]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[4]),
- .Q(\bus_data_int_reg_n_0_[4] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[5]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[5]),
- .Q(\bus_data_int_reg_n_0_[5] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[6]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[6]),
- .Q(\bus_data_int_reg_n_0_[6] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[7]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[7]),
- .Q(\bus_data_int_reg_n_0_[7] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[8]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[8]),
- .Q(\bus_data_int_reg_n_0_[8] ),
- .R(1'b0));
- FDRE \bus_data_int_reg[9]
- (.C(bus_clk),
- .CE(1'b1),
- .D(bus_di[9]),
- .Q(\bus_data_int_reg_n_0_[9] ),
- .R(1'b0));
-endmodule
-
-(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
-(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
-(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *)
-(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *)
-(* C_XDEVICEFAMILY = "zynq" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* dont_touch = "true" *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
- (s_rst_o,
- s_dclk_o,
- s_den_o,
- s_dwe_o,
- s_daddr_o,
- s_di_o,
- sl_oport_o,
- s_do_i,
- sl_iport_i,
- s_drdy_i);
- output s_rst_o;
- output s_dclk_o;
- output s_den_o;
- output s_dwe_o;
- output [16:0]s_daddr_o;
- output [15:0]s_di_o;
- output [16:0]sl_oport_o;
- input [15:0]s_do_i;
- input [36:0]sl_iport_i;
- input s_drdy_i;
-
- wire [15:0]reg_do;
- wire \reg_do[0]_i_2_n_0 ;
- wire \reg_do[0]_i_3_n_0 ;
- wire \reg_do[0]_i_4_n_0 ;
- wire \reg_do[10]_i_2_n_0 ;
- wire \reg_do[10]_i_3_n_0 ;
- wire \reg_do[10]_i_4_n_0 ;
- wire \reg_do[10]_i_5_n_0 ;
- wire \reg_do[11]_i_2_n_0 ;
- wire \reg_do[11]_i_3_n_0 ;
- wire \reg_do[12]_i_2_n_0 ;
- wire \reg_do[12]_i_3_n_0 ;
- wire \reg_do[13]_i_2_n_0 ;
- wire \reg_do[13]_i_3_n_0 ;
- wire \reg_do[14]_i_2_n_0 ;
- wire \reg_do[14]_i_3_n_0 ;
- wire \reg_do[15]_i_2_n_0 ;
- wire \reg_do[15]_i_3_n_0 ;
- wire \reg_do[15]_i_4_n_0 ;
- wire \reg_do[15]_i_5_n_0 ;
- wire \reg_do[15]_i_6_n_0 ;
- wire \reg_do[1]_i_2_n_0 ;
- wire \reg_do[1]_i_3_n_0 ;
- wire \reg_do[1]_i_4_n_0 ;
- wire \reg_do[2]_i_2_n_0 ;
- wire \reg_do[2]_i_3_n_0 ;
- wire \reg_do[2]_i_4_n_0 ;
- wire \reg_do[3]_i_2_n_0 ;
- wire \reg_do[3]_i_3_n_0 ;
- wire \reg_do[3]_i_4_n_0 ;
- wire \reg_do[4]_i_2_n_0 ;
- wire \reg_do[4]_i_3_n_0 ;
- wire \reg_do[4]_i_4_n_0 ;
- wire \reg_do[5]_i_2_n_0 ;
- wire \reg_do[5]_i_3_n_0 ;
- wire \reg_do[5]_i_4_n_0 ;
- wire \reg_do[5]_i_5_n_0 ;
- wire \reg_do[6]_i_2_n_0 ;
- wire \reg_do[6]_i_3_n_0 ;
- wire \reg_do[6]_i_4_n_0 ;
- wire \reg_do[7]_i_2_n_0 ;
- wire \reg_do[7]_i_3_n_0 ;
- wire \reg_do[7]_i_4_n_0 ;
- wire \reg_do[8]_i_2_n_0 ;
- wire \reg_do[8]_i_3_n_0 ;
- wire \reg_do[8]_i_4_n_0 ;
- wire \reg_do[9]_i_2_n_0 ;
- wire \reg_do[9]_i_3_n_0 ;
- wire \reg_do[9]_i_4_n_0 ;
- wire \reg_do[9]_i_5_n_0 ;
- wire \reg_do[9]_i_6_n_0 ;
- wire \reg_do_reg_n_0_[0] ;
- wire \reg_do_reg_n_0_[10] ;
- wire \reg_do_reg_n_0_[11] ;
- wire \reg_do_reg_n_0_[12] ;
- wire \reg_do_reg_n_0_[13] ;
- wire \reg_do_reg_n_0_[14] ;
- wire \reg_do_reg_n_0_[15] ;
- wire \reg_do_reg_n_0_[1] ;
- wire \reg_do_reg_n_0_[2] ;
- wire \reg_do_reg_n_0_[3] ;
- wire \reg_do_reg_n_0_[4] ;
- wire \reg_do_reg_n_0_[5] ;
- wire \reg_do_reg_n_0_[6] ;
- wire \reg_do_reg_n_0_[7] ;
- wire \reg_do_reg_n_0_[8] ;
- wire \reg_do_reg_n_0_[9] ;
- wire reg_drdy;
- wire reg_drdy_i_1_n_0;
- wire [15:0]reg_test;
- wire reg_test0;
- wire s_den_o;
- wire s_den_o_INST_0_i_1_n_0;
- wire [15:0]s_do_i;
- wire s_drdy_i;
- wire [36:0]sl_iport_i;
- wire [16:0]sl_oport_o;
- (* DONT_TOUCH *) (* UUID = "1" *) wire [127:0]uuid_stamp;
-
- assign s_daddr_o[16:0] = sl_iport_i[20:4];
- assign s_dclk_o = sl_iport_i[1];
- assign s_di_o[15:0] = sl_iport_i[36:21];
- assign s_dwe_o = sl_iport_i[3];
- assign s_rst_o = sl_iport_i[0];
- LUT6 #(
- .INIT(64'hAAAAAAAA0020AAAA))
- \reg_do[0]_i_1
- (.I0(\reg_do[0]_i_2_n_0 ),
- .I1(\reg_do[9]_i_3_n_0 ),
- .I2(reg_test[0]),
- .I3(sl_iport_i[4]),
- .I4(sl_iport_i[5]),
- .I5(\reg_do[9]_i_2_n_0 ),
- .O(reg_do[0]));
- LUT6 #(
- .INIT(64'hABABABAAAAAAABAA))
- \reg_do[0]_i_2
- (.I0(\reg_do[5]_i_3_n_0 ),
- .I1(sl_iport_i[8]),
- .I2(sl_iport_i[7]),
- .I3(\reg_do[0]_i_3_n_0 ),
- .I4(sl_iport_i[6]),
- .I5(\reg_do[0]_i_4_n_0 ),
- .O(\reg_do[0]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[0]_i_3
- (.I0(uuid_stamp[48]),
- .I1(uuid_stamp[32]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[16]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[0]),
- .O(\reg_do[0]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[0]_i_4
- (.I0(uuid_stamp[112]),
- .I1(uuid_stamp[96]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[80]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[64]),
- .O(\reg_do[0]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF2808))
- \reg_do[10]_i_1
- (.I0(\reg_do[10]_i_2_n_0 ),
- .I1(sl_iport_i[4]),
- .I2(sl_iport_i[5]),
- .I3(reg_test[10]),
- .I4(\reg_do[10]_i_3_n_0 ),
- .O(reg_do[10]));
- LUT6 #(
- .INIT(64'h0800000000000000))
- \reg_do[10]_i_2
- (.I0(sl_iport_i[6]),
- .I1(sl_iport_i[9]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(sl_iport_i[11]),
- .I5(sl_iport_i[10]),
- .O(\reg_do[10]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[10]_i_3
- (.I0(\reg_do[10]_i_4_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[10]_i_5_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[10]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[10]_i_4
- (.I0(uuid_stamp[122]),
- .I1(uuid_stamp[106]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[90]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[74]),
- .O(\reg_do[10]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[10]_i_5
- (.I0(uuid_stamp[58]),
- .I1(uuid_stamp[42]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[26]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[10]),
- .O(\reg_do[10]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'h4540FFFF45404540))
- \reg_do[11]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[11]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[11]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[11]),
- .O(reg_do[11]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[11]_i_2
- (.I0(uuid_stamp[59]),
- .I1(uuid_stamp[43]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[27]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[11]),
- .O(\reg_do[11]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[11]_i_3
- (.I0(uuid_stamp[123]),
- .I1(uuid_stamp[107]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[91]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[75]),
- .O(\reg_do[11]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h5404FFFF54045404))
- \reg_do[12]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[12]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[12]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[12]),
- .O(reg_do[12]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[12]_i_2
- (.I0(uuid_stamp[124]),
- .I1(uuid_stamp[108]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[92]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[76]),
- .O(\reg_do[12]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[12]_i_3
- (.I0(uuid_stamp[60]),
- .I1(uuid_stamp[44]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[28]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[12]),
- .O(\reg_do[12]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h4540FFFF45404540))
- \reg_do[13]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[13]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[13]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[13]),
- .O(reg_do[13]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[13]_i_2
- (.I0(uuid_stamp[61]),
- .I1(uuid_stamp[45]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[29]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[13]),
- .O(\reg_do[13]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[13]_i_3
- (.I0(uuid_stamp[125]),
- .I1(uuid_stamp[109]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[93]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[77]),
- .O(\reg_do[13]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h4540FFFF45404540))
- \reg_do[14]_i_1
- (.I0(\reg_do[15]_i_4_n_0 ),
- .I1(\reg_do[14]_i_2_n_0 ),
- .I2(\reg_do[15]_i_2_n_0 ),
- .I3(\reg_do[14]_i_3_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[14]),
- .O(reg_do[14]));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[14]_i_2
- (.I0(uuid_stamp[62]),
- .I1(uuid_stamp[46]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[30]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[14]),
- .O(\reg_do[14]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[14]_i_3
- (.I0(uuid_stamp[126]),
- .I1(uuid_stamp[110]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[94]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[78]),
- .O(\reg_do[14]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h0B01FFFF0B010B01))
- \reg_do[15]_i_1
- (.I0(\reg_do[15]_i_2_n_0 ),
- .I1(\reg_do[15]_i_3_n_0 ),
- .I2(\reg_do[15]_i_4_n_0 ),
- .I3(\reg_do[15]_i_5_n_0 ),
- .I4(\reg_do[15]_i_6_n_0 ),
- .I5(reg_test[15]),
- .O(reg_do[15]));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT3 #(
- .INIT(8'h45))
- \reg_do[15]_i_2
- (.I0(sl_iport_i[8]),
- .I1(sl_iport_i[7]),
- .I2(sl_iport_i[6]),
- .O(\reg_do[15]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'h505F3030505F3F3F))
- \reg_do[15]_i_3
- (.I0(uuid_stamp[127]),
- .I1(uuid_stamp[111]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[95]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[79]),
- .O(\reg_do[15]_i_3_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFFFFFFFE))
- \reg_do[15]_i_4
- (.I0(sl_iport_i[7]),
- .I1(sl_iport_i[8]),
- .I2(sl_iport_i[9]),
- .I3(sl_iport_i[11]),
- .I4(sl_iport_i[10]),
- .O(\reg_do[15]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[15]_i_5
- (.I0(uuid_stamp[63]),
- .I1(uuid_stamp[47]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[31]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[15]),
- .O(\reg_do[15]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFD0FFFFFFFF))
- \reg_do[15]_i_6
- (.I0(sl_iport_i[6]),
- .I1(sl_iport_i[7]),
- .I2(sl_iport_i[8]),
- .I3(\reg_do[9]_i_2_n_0 ),
- .I4(sl_iport_i[4]),
- .I5(sl_iport_i[5]),
- .O(\reg_do[15]_i_6_n_0 ));
- LUT6 #(
- .INIT(64'hAAAAAAAAAAAAFEAA))
- \reg_do[1]_i_1
- (.I0(\reg_do[1]_i_2_n_0 ),
- .I1(reg_test[1]),
- .I2(\reg_do[9]_i_3_n_0 ),
- .I3(sl_iport_i[5]),
- .I4(sl_iport_i[4]),
- .I5(\reg_do[9]_i_2_n_0 ),
- .O(reg_do[1]));
- LUT6 #(
- .INIT(64'h00000000FFAE00A2))
- \reg_do[1]_i_2
- (.I0(\reg_do[1]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[1]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[1]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[1]_i_3
- (.I0(uuid_stamp[49]),
- .I1(uuid_stamp[33]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[17]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[1]),
- .O(\reg_do[1]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[1]_i_4
- (.I0(uuid_stamp[113]),
- .I1(uuid_stamp[97]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[81]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[65]),
- .O(\reg_do[1]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[2]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[2]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[2]_i_2_n_0 ),
- .O(reg_do[2]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[2]_i_2
- (.I0(\reg_do[2]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[2]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[2]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[2]_i_3
- (.I0(uuid_stamp[114]),
- .I1(uuid_stamp[98]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[82]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[66]),
- .O(\reg_do[2]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[2]_i_4
- (.I0(uuid_stamp[50]),
- .I1(uuid_stamp[34]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[18]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[2]),
- .O(\reg_do[2]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[3]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[3]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[3]_i_2_n_0 ),
- .O(reg_do[3]));
- LUT6 #(
- .INIT(64'h000000003333AA3A))
- \reg_do[3]_i_2
- (.I0(\reg_do[3]_i_3_n_0 ),
- .I1(\reg_do[3]_i_4_n_0 ),
- .I2(sl_iport_i[6]),
- .I3(sl_iport_i[7]),
- .I4(sl_iport_i[8]),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[3]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[3]_i_3
- (.I0(uuid_stamp[51]),
- .I1(uuid_stamp[35]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[19]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[3]),
- .O(\reg_do[3]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h05F5030305F5F3F3))
- \reg_do[3]_i_4
- (.I0(uuid_stamp[83]),
- .I1(uuid_stamp[67]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[115]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[99]),
- .O(\reg_do[3]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[4]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[4]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[4]_i_2_n_0 ),
- .O(reg_do[4]));
- LUT6 #(
- .INIT(64'h00000000FFAE00A2))
- \reg_do[4]_i_2
- (.I0(\reg_do[4]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[4]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[4]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[4]_i_3
- (.I0(uuid_stamp[52]),
- .I1(uuid_stamp[36]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[20]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[4]),
- .O(\reg_do[4]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[4]_i_4
- (.I0(uuid_stamp[116]),
- .I1(uuid_stamp[100]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[84]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[68]),
- .O(\reg_do[4]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'h888888888A88A8A8))
- \reg_do[5]_i_1
- (.I0(\reg_do[5]_i_2_n_0 ),
- .I1(\reg_do[9]_i_2_n_0 ),
- .I2(\reg_do[9]_i_3_n_0 ),
- .I3(reg_test[5]),
- .I4(sl_iport_i[5]),
- .I5(sl_iport_i[4]),
- .O(reg_do[5]));
- LUT6 #(
- .INIT(64'hABABABAAAAAAABAA))
- \reg_do[5]_i_2
- (.I0(\reg_do[5]_i_3_n_0 ),
- .I1(sl_iport_i[8]),
- .I2(sl_iport_i[7]),
- .I3(\reg_do[5]_i_4_n_0 ),
- .I4(sl_iport_i[6]),
- .I5(\reg_do[5]_i_5_n_0 ),
- .O(\reg_do[5]_i_2_n_0 ));
- LUT4 #(
- .INIT(16'hFFFE))
- \reg_do[5]_i_3
- (.I0(sl_iport_i[10]),
- .I1(sl_iport_i[11]),
- .I2(sl_iport_i[9]),
- .I3(sl_iport_i[8]),
- .O(\reg_do[5]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[5]_i_4
- (.I0(uuid_stamp[53]),
- .I1(uuid_stamp[37]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[21]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[5]),
- .O(\reg_do[5]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[5]_i_5
- (.I0(uuid_stamp[117]),
- .I1(uuid_stamp[101]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[85]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[69]),
- .O(\reg_do[5]_i_5_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[6]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[6]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[6]_i_2_n_0 ),
- .O(reg_do[6]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[6]_i_2
- (.I0(\reg_do[6]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[6]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[6]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[6]_i_3
- (.I0(uuid_stamp[118]),
- .I1(uuid_stamp[102]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[86]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[70]),
- .O(\reg_do[6]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[6]_i_4
- (.I0(uuid_stamp[54]),
- .I1(uuid_stamp[38]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[22]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[6]),
- .O(\reg_do[6]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF6200))
- \reg_do[7]_i_1
- (.I0(sl_iport_i[4]),
- .I1(sl_iport_i[5]),
- .I2(reg_test[7]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[7]_i_2_n_0 ),
- .O(reg_do[7]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[7]_i_2
- (.I0(\reg_do[7]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[7]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[7]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[7]_i_3
- (.I0(uuid_stamp[119]),
- .I1(uuid_stamp[103]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[87]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[71]),
- .O(\reg_do[7]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[7]_i_4
- (.I0(uuid_stamp[55]),
- .I1(uuid_stamp[39]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[23]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[7]),
- .O(\reg_do[7]_i_4_n_0 ));
- LUT5 #(
- .INIT(32'hFFFF7500))
- \reg_do[8]_i_1
- (.I0(sl_iport_i[5]),
- .I1(sl_iport_i[4]),
- .I2(reg_test[8]),
- .I3(\reg_do[10]_i_2_n_0 ),
- .I4(\reg_do[8]_i_2_n_0 ),
- .O(reg_do[8]));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[8]_i_2
- (.I0(\reg_do[8]_i_3_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[8]_i_4_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[8]_i_2_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[8]_i_3
- (.I0(uuid_stamp[120]),
- .I1(uuid_stamp[104]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[88]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[72]),
- .O(\reg_do[8]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[8]_i_4
- (.I0(uuid_stamp[56]),
- .I1(uuid_stamp[40]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[24]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[8]),
- .O(\reg_do[8]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hFFFFFFFF40144010))
- \reg_do[9]_i_1
- (.I0(\reg_do[9]_i_2_n_0 ),
- .I1(sl_iport_i[5]),
- .I2(sl_iport_i[4]),
- .I3(\reg_do[9]_i_3_n_0 ),
- .I4(reg_test[9]),
- .I5(\reg_do[9]_i_4_n_0 ),
- .O(reg_do[9]));
- (* SOFT_HLUTNM = "soft_lutpair0" *)
- LUT5 #(
- .INIT(32'hFF7FFFFF))
- \reg_do[9]_i_2
- (.I0(sl_iport_i[10]),
- .I1(sl_iport_i[11]),
- .I2(sl_iport_i[8]),
- .I3(sl_iport_i[7]),
- .I4(sl_iport_i[9]),
- .O(\reg_do[9]_i_2_n_0 ));
- (* SOFT_HLUTNM = "soft_lutpair9" *)
- LUT3 #(
- .INIT(8'h8A))
- \reg_do[9]_i_3
- (.I0(sl_iport_i[8]),
- .I1(sl_iport_i[7]),
- .I2(sl_iport_i[6]),
- .O(\reg_do[9]_i_3_n_0 ));
- LUT6 #(
- .INIT(64'h00000000AAFBAA08))
- \reg_do[9]_i_4
- (.I0(\reg_do[9]_i_5_n_0 ),
- .I1(sl_iport_i[6]),
- .I2(sl_iport_i[7]),
- .I3(sl_iport_i[8]),
- .I4(\reg_do[9]_i_6_n_0 ),
- .I5(\reg_do[15]_i_4_n_0 ),
- .O(\reg_do[9]_i_4_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[9]_i_5
- (.I0(uuid_stamp[121]),
- .I1(uuid_stamp[105]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[89]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[73]),
- .O(\reg_do[9]_i_5_n_0 ));
- LUT6 #(
- .INIT(64'hAFA0CFCFAFA0C0C0))
- \reg_do[9]_i_6
- (.I0(uuid_stamp[57]),
- .I1(uuid_stamp[41]),
- .I2(sl_iport_i[5]),
- .I3(uuid_stamp[25]),
- .I4(sl_iport_i[4]),
- .I5(uuid_stamp[9]),
- .O(\reg_do[9]_i_6_n_0 ));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[0]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[0]),
- .Q(\reg_do_reg_n_0_[0] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[10]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[10]),
- .Q(\reg_do_reg_n_0_[10] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[11]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[11]),
- .Q(\reg_do_reg_n_0_[11] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[12]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[12]),
- .Q(\reg_do_reg_n_0_[12] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[13]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[13]),
- .Q(\reg_do_reg_n_0_[13] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[14]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[14]),
- .Q(\reg_do_reg_n_0_[14] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[15]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[15]),
- .Q(\reg_do_reg_n_0_[15] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[1]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[1]),
- .Q(\reg_do_reg_n_0_[1] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[2]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[2]),
- .Q(\reg_do_reg_n_0_[2] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[3]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[3]),
- .Q(\reg_do_reg_n_0_[3] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[4]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[4]),
- .Q(\reg_do_reg_n_0_[4] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[5]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[5]),
- .Q(\reg_do_reg_n_0_[5] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[6]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[6]),
- .Q(\reg_do_reg_n_0_[6] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[7]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[7]),
- .Q(\reg_do_reg_n_0_[7] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[8]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[8]),
- .Q(\reg_do_reg_n_0_[8] ),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_do_reg[9]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_do[9]),
- .Q(\reg_do_reg_n_0_[9] ),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h0000800000000000))
- reg_drdy_i_1
- (.I0(s_den_o_INST_0_i_1_n_0),
- .I1(sl_iport_i[12]),
- .I2(sl_iport_i[13]),
- .I3(sl_iport_i[14]),
- .I4(sl_iport_i[0]),
- .I5(sl_iport_i[2]),
- .O(reg_drdy_i_1_n_0));
- FDRE #(
- .INIT(1'b0))
- reg_drdy_reg
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(reg_drdy_i_1_n_0),
- .Q(reg_drdy),
- .R(1'b0));
- LUT6 #(
- .INIT(64'h8000000000000000))
- \reg_test[15]_i_1
- (.I0(s_den_o_INST_0_i_1_n_0),
- .I1(sl_iport_i[12]),
- .I2(sl_iport_i[13]),
- .I3(sl_iport_i[14]),
- .I4(sl_iport_i[3]),
- .I5(sl_iport_i[2]),
- .O(reg_test0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[0]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[21]),
- .Q(reg_test[0]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[10]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[31]),
- .Q(reg_test[10]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[11]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[32]),
- .Q(reg_test[11]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[12]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[33]),
- .Q(reg_test[12]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[13]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[34]),
- .Q(reg_test[13]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[14]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[35]),
- .Q(reg_test[14]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[15]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[36]),
- .Q(reg_test[15]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[1]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[22]),
- .Q(reg_test[1]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[2]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[23]),
- .Q(reg_test[2]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[3]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[24]),
- .Q(reg_test[3]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[4]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[25]),
- .Q(reg_test[4]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[5]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[26]),
- .Q(reg_test[5]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[6]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[27]),
- .Q(reg_test[6]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[7]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[28]),
- .Q(reg_test[7]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[8]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[29]),
- .Q(reg_test[8]),
- .R(1'b0));
- FDRE #(
- .INIT(1'b0))
- \reg_test_reg[9]
- (.C(sl_iport_i[1]),
- .CE(reg_test0),
- .D(sl_iport_i[30]),
- .Q(reg_test[9]),
- .R(1'b0));
- LUT5 #(
- .INIT(32'h7FFF0000))
- s_den_o_INST_0
- (.I0(s_den_o_INST_0_i_1_n_0),
- .I1(sl_iport_i[12]),
- .I2(sl_iport_i[13]),
- .I3(sl_iport_i[14]),
- .I4(sl_iport_i[2]),
- .O(s_den_o));
- LUT6 #(
- .INIT(64'h8000000000000000))
- s_den_o_INST_0_i_1
- (.I0(sl_iport_i[15]),
- .I1(sl_iport_i[16]),
- .I2(sl_iport_i[17]),
- .I3(sl_iport_i[18]),
- .I4(sl_iport_i[20]),
- .I5(sl_iport_i[19]),
- .O(s_den_o_INST_0_i_1_n_0));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT2 #(
- .INIT(4'hE))
- \sl_oport_o[0]_INST_0
- (.I0(reg_drdy),
- .I1(s_drdy_i),
- .O(sl_oport_o[0]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[10]_INST_0
- (.I0(\reg_do_reg_n_0_[9] ),
- .I1(reg_drdy),
- .I2(s_do_i[9]),
- .O(sl_oport_o[10]));
- (* SOFT_HLUTNM = "soft_lutpair6" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[11]_INST_0
- (.I0(\reg_do_reg_n_0_[10] ),
- .I1(reg_drdy),
- .I2(s_do_i[10]),
- .O(sl_oport_o[11]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[12]_INST_0
- (.I0(\reg_do_reg_n_0_[11] ),
- .I1(reg_drdy),
- .I2(s_do_i[11]),
- .O(sl_oport_o[12]));
- (* SOFT_HLUTNM = "soft_lutpair7" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[13]_INST_0
- (.I0(\reg_do_reg_n_0_[12] ),
- .I1(reg_drdy),
- .I2(s_do_i[12]),
- .O(sl_oport_o[13]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[14]_INST_0
- (.I0(\reg_do_reg_n_0_[13] ),
- .I1(reg_drdy),
- .I2(s_do_i[13]),
- .O(sl_oport_o[14]));
- (* SOFT_HLUTNM = "soft_lutpair8" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[15]_INST_0
- (.I0(\reg_do_reg_n_0_[14] ),
- .I1(reg_drdy),
- .I2(s_do_i[14]),
- .O(sl_oport_o[15]));
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[16]_INST_0
- (.I0(\reg_do_reg_n_0_[15] ),
- .I1(reg_drdy),
- .I2(s_do_i[15]),
- .O(sl_oport_o[16]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[1]_INST_0
- (.I0(\reg_do_reg_n_0_[0] ),
- .I1(reg_drdy),
- .I2(s_do_i[0]),
- .O(sl_oport_o[1]));
- (* SOFT_HLUTNM = "soft_lutpair1" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[2]_INST_0
- (.I0(\reg_do_reg_n_0_[1] ),
- .I1(reg_drdy),
- .I2(s_do_i[1]),
- .O(sl_oport_o[2]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[3]_INST_0
- (.I0(\reg_do_reg_n_0_[2] ),
- .I1(reg_drdy),
- .I2(s_do_i[2]),
- .O(sl_oport_o[3]));
- (* SOFT_HLUTNM = "soft_lutpair2" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[4]_INST_0
- (.I0(\reg_do_reg_n_0_[3] ),
- .I1(reg_drdy),
- .I2(s_do_i[3]),
- .O(sl_oport_o[4]));
- (* SOFT_HLUTNM = "soft_lutpair3" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[5]_INST_0
- (.I0(\reg_do_reg_n_0_[4] ),
- .I1(reg_drdy),
- .I2(s_do_i[4]),
- .O(sl_oport_o[5]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[6]_INST_0
- (.I0(\reg_do_reg_n_0_[5] ),
- .I1(reg_drdy),
- .I2(s_do_i[5]),
- .O(sl_oport_o[6]));
- (* SOFT_HLUTNM = "soft_lutpair4" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[7]_INST_0
- (.I0(\reg_do_reg_n_0_[6] ),
- .I1(reg_drdy),
- .I2(s_do_i[6]),
- .O(sl_oport_o[7]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[8]_INST_0
- (.I0(\reg_do_reg_n_0_[7] ),
- .I1(reg_drdy),
- .I2(s_do_i[7]),
- .O(sl_oport_o[8]));
- (* SOFT_HLUTNM = "soft_lutpair5" *)
- LUT3 #(
- .INIT(8'hB8))
- \sl_oport_o[9]_INST_0
- (.I0(\reg_do_reg_n_0_[8] ),
- .I1(reg_drdy),
- .I2(s_do_i[8]),
- .O(sl_oport_o[9]));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[0]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[0]),
- .Q(uuid_stamp[0]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[100]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[100]),
- .Q(uuid_stamp[100]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[101]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[101]),
- .Q(uuid_stamp[101]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[102]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[102]),
- .Q(uuid_stamp[102]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[103]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[103]),
- .Q(uuid_stamp[103]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[104]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[104]),
- .Q(uuid_stamp[104]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[105]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[105]),
- .Q(uuid_stamp[105]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[106]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[106]),
- .Q(uuid_stamp[106]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[107]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[107]),
- .Q(uuid_stamp[107]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[108]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[108]),
- .Q(uuid_stamp[108]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[109]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[109]),
- .Q(uuid_stamp[109]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[10]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[10]),
- .Q(uuid_stamp[10]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[110]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[110]),
- .Q(uuid_stamp[110]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[111]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[111]),
- .Q(uuid_stamp[111]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[112]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[112]),
- .Q(uuid_stamp[112]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[113]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[113]),
- .Q(uuid_stamp[113]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[114]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[114]),
- .Q(uuid_stamp[114]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[115]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[115]),
- .Q(uuid_stamp[115]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[116]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[116]),
- .Q(uuid_stamp[116]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[117]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[117]),
- .Q(uuid_stamp[117]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[118]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[118]),
- .Q(uuid_stamp[118]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[119]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[119]),
- .Q(uuid_stamp[119]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[11]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[11]),
- .Q(uuid_stamp[11]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[120]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[120]),
- .Q(uuid_stamp[120]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[121]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[121]),
- .Q(uuid_stamp[121]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[122]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[122]),
- .Q(uuid_stamp[122]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[123]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[123]),
- .Q(uuid_stamp[123]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[124]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[124]),
- .Q(uuid_stamp[124]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[125]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[125]),
- .Q(uuid_stamp[125]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[126]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[126]),
- .Q(uuid_stamp[126]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[127]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[127]),
- .Q(uuid_stamp[127]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[12]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[12]),
- .Q(uuid_stamp[12]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[13]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[13]),
- .Q(uuid_stamp[13]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[14]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[14]),
- .Q(uuid_stamp[14]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[15]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[15]),
- .Q(uuid_stamp[15]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[16]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[16]),
- .Q(uuid_stamp[16]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[17]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[17]),
- .Q(uuid_stamp[17]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[18]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[18]),
- .Q(uuid_stamp[18]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[19]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[19]),
- .Q(uuid_stamp[19]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[1]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[1]),
- .Q(uuid_stamp[1]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[20]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[20]),
- .Q(uuid_stamp[20]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[21]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[21]),
- .Q(uuid_stamp[21]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[22]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[22]),
- .Q(uuid_stamp[22]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[23]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[23]),
- .Q(uuid_stamp[23]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[24]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[24]),
- .Q(uuid_stamp[24]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[25]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[25]),
- .Q(uuid_stamp[25]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[26]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[26]),
- .Q(uuid_stamp[26]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[27]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[27]),
- .Q(uuid_stamp[27]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[28]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[28]),
- .Q(uuid_stamp[28]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[29]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[29]),
- .Q(uuid_stamp[29]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[2]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[2]),
- .Q(uuid_stamp[2]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[30]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[30]),
- .Q(uuid_stamp[30]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[31]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[31]),
- .Q(uuid_stamp[31]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[32]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[32]),
- .Q(uuid_stamp[32]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[33]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[33]),
- .Q(uuid_stamp[33]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[34]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[34]),
- .Q(uuid_stamp[34]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[35]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[35]),
- .Q(uuid_stamp[35]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[36]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[36]),
- .Q(uuid_stamp[36]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[37]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[37]),
- .Q(uuid_stamp[37]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[38]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[38]),
- .Q(uuid_stamp[38]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[39]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[39]),
- .Q(uuid_stamp[39]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[3]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[3]),
- .Q(uuid_stamp[3]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[40]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[40]),
- .Q(uuid_stamp[40]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[41]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[41]),
- .Q(uuid_stamp[41]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[42]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[42]),
- .Q(uuid_stamp[42]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[43]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[43]),
- .Q(uuid_stamp[43]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[44]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[44]),
- .Q(uuid_stamp[44]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[45]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[45]),
- .Q(uuid_stamp[45]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[46]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[46]),
- .Q(uuid_stamp[46]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[47]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[47]),
- .Q(uuid_stamp[47]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[48]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[48]),
- .Q(uuid_stamp[48]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[49]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[49]),
- .Q(uuid_stamp[49]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[4]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[4]),
- .Q(uuid_stamp[4]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[50]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[50]),
- .Q(uuid_stamp[50]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[51]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[51]),
- .Q(uuid_stamp[51]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[52]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[52]),
- .Q(uuid_stamp[52]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[53]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[53]),
- .Q(uuid_stamp[53]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[54]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[54]),
- .Q(uuid_stamp[54]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[55]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[55]),
- .Q(uuid_stamp[55]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[56]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[56]),
- .Q(uuid_stamp[56]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[57]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[57]),
- .Q(uuid_stamp[57]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[58]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[58]),
- .Q(uuid_stamp[58]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[59]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[59]),
- .Q(uuid_stamp[59]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[5]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[5]),
- .Q(uuid_stamp[5]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[60]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[60]),
- .Q(uuid_stamp[60]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[61]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[61]),
- .Q(uuid_stamp[61]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[62]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[62]),
- .Q(uuid_stamp[62]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[63]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[63]),
- .Q(uuid_stamp[63]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[64]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[64]),
- .Q(uuid_stamp[64]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[65]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[65]),
- .Q(uuid_stamp[65]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[66]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[66]),
- .Q(uuid_stamp[66]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[67]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[67]),
- .Q(uuid_stamp[67]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[68]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[68]),
- .Q(uuid_stamp[68]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[69]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[69]),
- .Q(uuid_stamp[69]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[6]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[6]),
- .Q(uuid_stamp[6]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[70]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[70]),
- .Q(uuid_stamp[70]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[71]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[71]),
- .Q(uuid_stamp[71]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[72]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[72]),
- .Q(uuid_stamp[72]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[73]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[73]),
- .Q(uuid_stamp[73]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[74]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[74]),
- .Q(uuid_stamp[74]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[75]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[75]),
- .Q(uuid_stamp[75]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[76]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[76]),
- .Q(uuid_stamp[76]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[77]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[77]),
- .Q(uuid_stamp[77]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[78]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[78]),
- .Q(uuid_stamp[78]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[79]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[79]),
- .Q(uuid_stamp[79]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[7]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[7]),
- .Q(uuid_stamp[7]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[80]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[80]),
- .Q(uuid_stamp[80]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[81]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[81]),
- .Q(uuid_stamp[81]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[82]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[82]),
- .Q(uuid_stamp[82]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[83]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[83]),
- .Q(uuid_stamp[83]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[84]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[84]),
- .Q(uuid_stamp[84]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[85]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[85]),
- .Q(uuid_stamp[85]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[86]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[86]),
- .Q(uuid_stamp[86]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[87]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[87]),
- .Q(uuid_stamp[87]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[88]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[88]),
- .Q(uuid_stamp[88]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[89]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[89]),
- .Q(uuid_stamp[89]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[8]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[8]),
- .Q(uuid_stamp[8]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[90]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[90]),
- .Q(uuid_stamp[90]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[91]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[91]),
- .Q(uuid_stamp[91]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[92]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[92]),
- .Q(uuid_stamp[92]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[93]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[93]),
- .Q(uuid_stamp[93]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[94]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[94]),
- .Q(uuid_stamp[94]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[95]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[95]),
- .Q(uuid_stamp[95]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[96]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[96]),
- .Q(uuid_stamp[96]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[97]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[97]),
- .Q(uuid_stamp[97]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[98]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[98]),
- .Q(uuid_stamp[98]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[99]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[99]),
- .Q(uuid_stamp[99]),
- .R(1'b0));
- (* DONT_TOUCH *)
- (* KEEP = "yes" *)
- (* UUID = "1" *)
- FDRE \uuid_stamp_reg[9]
- (.C(sl_iport_i[1]),
- .CE(1'b1),
- .D(uuid_stamp[9]),
- .Q(uuid_stamp[9]),
- .R(1'b0));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0_stub.v
deleted file mode 100755
index 7eae7b1dcf58698dfffbfb2309b4afdcaa272796..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/afab8f8185921798/scalp_zynqps_vio_0_0_stub.v
+++ /dev/null
@@ -1,21 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:35 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_vio_0_0_stub.v
-// Design : scalp_zynqps_vio_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "vio,Vivado 2019.2" *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0]" */;
- input clk;
- output [0:0]probe_out0;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/b32362bd6ba3a9e9.xci b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/b32362bd6ba3a9e9.xci
deleted file mode 100644
index 56eb53aebce38e02a83a590e163ba3c9cf1c1b55..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/b32362bd6ba3a9e9.xci
+++ /dev/null
@@ -1,916 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
- <spirit:vendor>xilinx.com</spirit:vendor>
- <spirit:library>ipcache</spirit:library>
- <spirit:name>b32362bd6ba3a9e9</spirit:name>
- <spirit:version>0</spirit:version>
- <spirit:componentInstances>
- <spirit:componentInstance>
- <spirit:instanceName>scalp_zynqps_processing_system7_0_0</spirit:instanceName>
- <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="processing_system7" spirit:version="5.5"/>
- <spirit:configurableElementValues>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FCLK_CLK0.FREQ_HZ">125000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0.FREQ_HZ">125000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI_GP0_ACLK.FREQ_HZ">125000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">scalp_zynqps_processing_system7_0_0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_APU_PERIPHERAL_FREQMHZ">750.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_CAN_PERIPHERAL_FREQMHZ">97.222221</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_DCI_PERIPHERAL_FREQMHZ">10.204082</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_I2C_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ">194.444443</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ">134.615387</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ">97.222221</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_SMC_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_SPI_PERIPHERAL_FREQMHZ">159.090912</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ">200.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_TTC_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_UART_PERIPHERAL_FREQMHZ">97.222221</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_USB0_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_USB1_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ACT_WDT_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_APU_CLK_RATIO_ENABLE">6:2:1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_APU_PERIPHERAL_FREQMHZ">750</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ARMPLL_CTRL_FBDIV">30</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_BASEADDR">0xE0008000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_CAN0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_GRP_CLK_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_GRP_CLK_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_HIGHADDR">0xE0008FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN0_PERIPHERAL_FREQMHZ">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_BASEADDR">0xE0009000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_CAN1_IO">MIO 52 .. 53</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_GRP_CLK_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_GRP_CLK_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_HIGHADDR">0xE0009FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN1_PERIPHERAL_FREQMHZ">-1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR0">18</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CAN_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK0_FREQ">125000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK1_FREQ">10000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK2_FREQ">10000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CLK3_FREQ">10000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE0_FIQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE0_IRQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE1_FIQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CORE1_IRQ_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_CPU_6X4X_MAX_RANGE">767</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_CPU_PLL_FREQMHZ">1500.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_PERIPHERAL_CLKSRC">ARM PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CPU_PERIPHERAL_DIVISOR0">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_CRYSTAL_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_CLKSRC">DDR PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_DIVISOR0">49</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_DIVISOR1">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DCI_PERIPHERAL_FREQMHZ">10.159</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDRPLL_CTRL_FBDIV">20</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_DDR_PLL_FREQMHZ">1000.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_HPRLPR_QUEUE_PARTITION">HPR(0)/LPR(32)</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL">15</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PERIPHERAL_CLKSRC">DDR PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PERIPHERAL_DIVISOR0">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT0_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT1_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT2_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PORT3_HPR_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_0"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_1"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_2"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_READPORT_3"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_0"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_1"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_2"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_PRIORITY_WRITEPORT_3"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_RAM_BASEADDR">0x00100000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_RAM_HIGHADDR">0x0FFFFFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DM_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DQS_WIDTH">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DQ_WIDTH">32</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DUAL_PARALLEL_QSPI_DATA_MODE"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_DUAL_STACK_QSPI_DATA_MODE"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_BASEADDR">0xE000B000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_ENET0_IO">MIO 16 .. 27</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_HIGHADDR">0xE000BFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_DIVISOR0">14</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_PERIPHERAL_FREQMHZ">1000 Mbps</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_BASEADDR">0xE000C000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_ENET1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_GRP_MDIO_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_GRP_MDIO_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_HIGHADDR">0xE000CFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_PERIPHERAL_FREQMHZ">1000 Mbps</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET1_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET_RESET_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET_RESET_POLARITY">Active Low</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET_RESET_SELECT">Share reset pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_4K_TIMER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CAN0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CAN1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK0_PORT">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK1_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK2_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLK3_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG0_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG1_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG2_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_CLKTRIG3_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_DDR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CAN0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CAN1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_CD_SDIO1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_ENET0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_ENET1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_GPIO">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_I2C0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_I2C1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_MODEM_UART0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_MODEM_UART1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_PJTAG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SDIO1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SPI0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SPI1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_SRAM_INT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_TRACE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_TTC0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_TTC1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_UART0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_UART1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WDT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_ENET0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_ENET1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_GPIO">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_I2C0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_I2C1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_MODEM_UART0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_MODEM_UART1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_PJTAG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_PTP_ENET0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_PTP_ENET1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_QSPI">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST0_PORT">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST1_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST2_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_RST3_PORT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SDIO0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SDIO1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SMC">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SPI0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_SPI1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_TRACE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_TTC0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_TTC1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_UART0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_UART1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_USB0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_USB1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_WDT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_DIVISOR0">7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK0_PERIPHERAL_DIVISOR1">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK1_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK2_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK3_PERIPHERAL_DIVISOR1">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK0_BUF">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK1_BUF">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK2_BUF">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FCLK_CLK3_BUF">FALSE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA0_PERIPHERAL_FREQMHZ">125</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA1_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA2_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA3_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK0_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK2_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FPGA_FCLK3_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN0">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN1">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN2">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_IN3">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT0">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT1">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT2">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_FTM_CTI_OUT3">DISABLED</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP0_EN_MODIFIABLE_TXN">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP0_NUM_READ_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP0_NUM_WRITE_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP1_EN_MODIFIABLE_TXN">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP1_NUM_READ_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GP1_NUM_WRITE_THREADS">4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_BASEADDR">0xE000A000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_EMIO_GPIO_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_HIGHADDR">0xE000AFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_MIO_GPIO_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_MIO_GPIO_IO">MIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_GPIO_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_BASEADDR">0xE0004000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_GRP_INT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_GRP_INT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_HIGHADDR">0xE0004FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_I2C0_IO">MIO 50 .. 51</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C0_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_BASEADDR">0xE0005000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_GRP_INT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_GRP_INT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_HIGHADDR">0xE0005FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_I2C1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C1_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_PERIPHERAL_FREQMHZ">125.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_RESET_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_RESET_POLARITY">Active Low</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_I2C_RESET_SELECT">Share reset pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IMPORT_BOARD_PRESET">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_INCLUDE_ACP_TRANS_CHECK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_INCLUDE_TRACE_BUFFER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IOPLL_CTRL_FBDIV">35</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IO_IO_PLL_FREQMHZ">1750.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IRQ_F2P_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_IRQ_F2P_MODE">DIRECT</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_0_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_10_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_11_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_12_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_13_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_14_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_15_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_16_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_17_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_18_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_19_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_1_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_20_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_21_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_22_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_23_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_24_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_25_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_26_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_27_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_28_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_29_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_2_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_30_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_31_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_32_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_33_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_34_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_35_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_36_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_37_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_38_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_39_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_3_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_40_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_41_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_42_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_43_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_44_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_45_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_46_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_47_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_48_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_49_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_4_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_50_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_51_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_52_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_IOTYPE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_53_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_DIRECTION">inout</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_5_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_6_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_7_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_DIRECTION">out</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_PULLUP">disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_8_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_DIRECTION">in</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_PULLUP">enabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_9_SLEW">slow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_PRIMITIVE">54</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_TREE_PERIPHERALS">GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#SPI 0#UART 0#UART 0#UART 1#UART 1#I2C 0#I2C 0#CAN 1#CAN 1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_MIO_TREE_SIGNALS">gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_FREQMHZ">125</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP0_THREAD_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_M_AXI_GP1_THREAD_ID_WIDTH">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_AR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_CLR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_REA">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_RR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_CYCLES_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_GRP_D8_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_GRP_D8_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_NAND_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NAND_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS0_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_CS1_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_A25_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_A25_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS0_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_CS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_CS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_GRP_SRAM_INT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_NOR_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS0_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_CEOE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_PC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_RC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_TR">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WC">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_T_WP">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NOR_SRAM_CS1_WE_TIME">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_NUM_F2P_INTR_INPUTS">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_OVERRIDE_BASIC_CLOCK">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_CAN0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_CAN1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_CTI_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC2_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC3_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC4_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC5_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC6_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC7_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_DMAC_ABORT_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_ENET0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_ENET1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_GPIO_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_I2C0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_I2C1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_QSPI_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SDIO0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SDIO1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SMC_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SPI0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_SPI1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_UART0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_UART1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_USB0_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_P2F_USB1_INTR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY0">0.075</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY1">0.070</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY2">0.077</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_BOARD_DELAY3">0.094</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0">-0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1">-0.001</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2">0.004</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3">-0.035</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PACKAGE_NAME">clg485</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_DIVISOR0">9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PCAP_PERIPHERAL_FREQMHZ">200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PERIPHERAL_BOARD_PRESET">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PJTAG_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PJTAG_PJTAG_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PLL_BYPASSMODE_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PRESET_BANK0_VOLTAGE">LVCMOS 3.3V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PRESET_BANK1_VOLTAGE">LVCMOS 2.5V</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_PS7_SI_REV">PRODUCTION</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_FBCLK_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_IO1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_IO1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SINGLE_SS_IO">MIO 1 .. 6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_GRP_SS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_INTERNAL_HIGHADDRESS">0xFCFFFFFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_DIVISOR0">13</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_PERIPHERAL_FREQMHZ">133</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_QSPI_QSPI_IO">MIO 1 .. 6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_CD_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_CD_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_POW_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_POW_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_SD0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_CD_IO">MIO 9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_POW_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_POW_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_WP_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_GRP_WP_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD1_SD1_IO">MIO 10 .. 15</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO0_BASEADDR">0xE0100000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO0_HIGHADDR">0xE0100FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO1_BASEADDR">0xE0101000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO1_HIGHADDR">0xE0101FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_DIVISOR0">18</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SDIO_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SINGLE_QSPI_DATA_MODE">x4</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T0">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T1">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T2">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T3">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T4">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T5">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_CYCLE_T6">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SMC_PERIPHERAL_VALID">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_BASEADDR">0xE0006000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS0_IO">MIO 42</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_GRP_SS2_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_HIGHADDR">0xE0006FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI0_SPI0_IO">MIO 40 .. 45</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_BASEADDR">0xE0007000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS0_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS1_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_GRP_SS2_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_HIGHADDR">0xE0007FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI1_SPI1_IO">EMIO</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_DIVISOR0">11</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_FREQMHZ">166.666666</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SPI_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_ARUSER_VAL">31</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_AWUSER_VAL">31</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_ACP_ID_WIDTH">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP0_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_GP1_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP0_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP1_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP2_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_DATA_WIDTH">64</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_FREQMHZ">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_S_AXI_HP3_ID_WIDTH">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TPIU_PERIPHERAL_FREQMHZ">200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_BUFFER_CLOCK_DELAY">12</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_BUFFER_FIFO_SIZE">128</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_16BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_16BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_2BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_2BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_32BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_32BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_4BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_4BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_8BIT_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_GRP_8BIT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_INTERNAL_WIDTH">2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_PIPELINE_WIDTH">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TRACE_TRACE_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_BASEADDR">0xE0104000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_HIGHADDR">0xE0104fff</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC0_TTC0_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_BASEADDR">0xE0105000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_HIGHADDR">0xE0105fff</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC1_TTC1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_TTC_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_BASEADDR">0xE0000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_BAUD_RATE">115200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_GRP_FULL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_GRP_FULL_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_HIGHADDR">0xE0000FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART0_UART0_IO">MIO 46 .. 47</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_BASEADDR">0xE0001000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_BAUD_RATE">115200</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_GRP_FULL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_GRP_FULL_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_HIGHADDR">0xE0001FFF</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART1_UART1_IO">MIO 48 .. 49</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_DIVISOR0">18</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UART_PERIPHERAL_VALID">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_ACT_DDR_FREQ_MHZ">500.000000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ADV_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_AL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BANK_ADDR_COUNT">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BL">8</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY0">0.25</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY1">0.25</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY2">0.25</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BOARD_DELAY3">0.25</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_BUS_WIDTH">16 Bit</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CL">7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH">76.428</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH">76.428</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH">76.428</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH">76.428</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CLOCK_STOP_EN">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_COL_ADDR_COUNT">10</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_CWL">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DEVICE_CAPACITY">2048 MBits</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH">76.687</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH">77.8025</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH">72.8405</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH">111.904</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3">0.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH">73.119</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH">63.8935</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH">77.045</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH">111.903</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY">160</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_DRAM_WIDTH">16 Bits</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ECC">Disabled</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_FREQ_MHZ">500</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_HIGH_TEMP">Normal (0-85)</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_MEMORY_TYPE">DDR 3 (Low Voltage)</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_PARTNO">MT41K128M16 JT-125</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_ROW_ADDR_COUNT">14</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_SPEED_BIN">DDR3_1066F</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_TRAIN_DATA_EYE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_TRAIN_READ_GATE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_FAW">40.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RAS_MIN">35.0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RC">48.75</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RCD">7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_T_RP">7</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_DDR_USE_INTERNAL_VREF">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_UIPARAM_GENERATE_SUMMARY">NA</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB0_BASEADDR">0xE0102000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB0_HIGHADDR">0xE0102fff</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB0_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB0_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB0_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB0_USB0_IO">MIO 28 .. 39</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB1_BASEADDR">0xE0103000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB1_HIGHADDR">0xE0103fff</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB1_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB1_RESET_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB1_RESET_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB1_USB1_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB_RESET_ENABLE">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB_RESET_POLARITY">Active Low</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USB_RESET_SELECT">Share reset pin</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_AXI_FABRIC_IDLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_AXI_NONSECURE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_CORESIGHT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_CROSS_TRIGGER">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_CR_FABRIC">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_DDR_BYPASS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_DEBUG">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_DEFAULT_ACP_USER_VAL">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_DMA0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_DMA1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_DMA2">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_DMA3">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_EXPANDED_IOP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_EXPANDED_PS_SLCR_REGISTERS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_FABRIC_INTERRUPT">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_HIGH_OCM">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_M_AXI_GP0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_M_AXI_GP1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_PROC_EVENT_BUS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_PS_SLCR_REGISTERS">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_S_AXI_ACP">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_S_AXI_GP0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_S_AXI_GP1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP0">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP1">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP2">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_S_AXI_HP3">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_TRACE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_USE_TRACE_DATA_EDGE_DETECTOR">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_VALUE_SILVERSION">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_DIVISOR0">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_WDT_PERIPHERAL_FREQMHZ">133.333333</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_WDT_WDT_IO"><Select></spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.preset">None</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">b32362bd6ba3a9e9</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">244</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
- </spirit:configurableElementValues>
- </spirit:componentInstance>
- </spirit:componentInstances>
-</spirit:design>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0.dcp
deleted file mode 100644
index 2b52f400fefbf2083f28ba491bd2af5dcd5b2c53..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0_sim_netlist.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0_sim_netlist.v
deleted file mode 100755
index 712041c4d05a2e4c750c605f8a6f90a5cc55162d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0_sim_netlist.v
+++ /dev/null
@@ -1,5232 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:38 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_processing_system7_0_0_sim_netlist.v
-// Design : scalp_zynqps_processing_system7_0_0
-// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
-// or synthesized. This netlist cannot be used for SDF annotated simulation.
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-`timescale 1 ps / 1 ps
-
-(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
-(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
-(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
-(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
-(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
-(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
-(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
-(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
-(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg485" *) (* C_PS7_SI_REV = "PRODUCTION" *)
-(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
-(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
-(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
-(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
-(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
-(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
-(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
-(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
-(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
-(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "scalp_zynqps_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={750} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SPI} ioStandard={} bidis={2} ioBank={} clockFreq={159.090912} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS25} bidis={5} ioBank={Vcco_p1} clockFreq={159.090912} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={97.222221} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={133} usageRate={0.5} /><PLL domain={Processor} vco={1500.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1750.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>" *)
-(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
- (CAN0_PHY_TX,
- CAN0_PHY_RX,
- CAN1_PHY_TX,
- CAN1_PHY_RX,
- ENET0_GMII_TX_EN,
- ENET0_GMII_TX_ER,
- ENET0_MDIO_MDC,
- ENET0_MDIO_O,
- ENET0_MDIO_T,
- ENET0_PTP_DELAY_REQ_RX,
- ENET0_PTP_DELAY_REQ_TX,
- ENET0_PTP_PDELAY_REQ_RX,
- ENET0_PTP_PDELAY_REQ_TX,
- ENET0_PTP_PDELAY_RESP_RX,
- ENET0_PTP_PDELAY_RESP_TX,
- ENET0_PTP_SYNC_FRAME_RX,
- ENET0_PTP_SYNC_FRAME_TX,
- ENET0_SOF_RX,
- ENET0_SOF_TX,
- ENET0_GMII_TXD,
- ENET0_GMII_COL,
- ENET0_GMII_CRS,
- ENET0_GMII_RX_CLK,
- ENET0_GMII_RX_DV,
- ENET0_GMII_RX_ER,
- ENET0_GMII_TX_CLK,
- ENET0_MDIO_I,
- ENET0_EXT_INTIN,
- ENET0_GMII_RXD,
- ENET1_GMII_TX_EN,
- ENET1_GMII_TX_ER,
- ENET1_MDIO_MDC,
- ENET1_MDIO_O,
- ENET1_MDIO_T,
- ENET1_PTP_DELAY_REQ_RX,
- ENET1_PTP_DELAY_REQ_TX,
- ENET1_PTP_PDELAY_REQ_RX,
- ENET1_PTP_PDELAY_REQ_TX,
- ENET1_PTP_PDELAY_RESP_RX,
- ENET1_PTP_PDELAY_RESP_TX,
- ENET1_PTP_SYNC_FRAME_RX,
- ENET1_PTP_SYNC_FRAME_TX,
- ENET1_SOF_RX,
- ENET1_SOF_TX,
- ENET1_GMII_TXD,
- ENET1_GMII_COL,
- ENET1_GMII_CRS,
- ENET1_GMII_RX_CLK,
- ENET1_GMII_RX_DV,
- ENET1_GMII_RX_ER,
- ENET1_GMII_TX_CLK,
- ENET1_MDIO_I,
- ENET1_EXT_INTIN,
- ENET1_GMII_RXD,
- GPIO_I,
- GPIO_O,
- GPIO_T,
- I2C0_SDA_I,
- I2C0_SDA_O,
- I2C0_SDA_T,
- I2C0_SCL_I,
- I2C0_SCL_O,
- I2C0_SCL_T,
- I2C1_SDA_I,
- I2C1_SDA_O,
- I2C1_SDA_T,
- I2C1_SCL_I,
- I2C1_SCL_O,
- I2C1_SCL_T,
- PJTAG_TCK,
- PJTAG_TMS,
- PJTAG_TDI,
- PJTAG_TDO,
- SDIO0_CLK,
- SDIO0_CLK_FB,
- SDIO0_CMD_O,
- SDIO0_CMD_I,
- SDIO0_CMD_T,
- SDIO0_DATA_I,
- SDIO0_DATA_O,
- SDIO0_DATA_T,
- SDIO0_LED,
- SDIO0_CDN,
- SDIO0_WP,
- SDIO0_BUSPOW,
- SDIO0_BUSVOLT,
- SDIO1_CLK,
- SDIO1_CLK_FB,
- SDIO1_CMD_O,
- SDIO1_CMD_I,
- SDIO1_CMD_T,
- SDIO1_DATA_I,
- SDIO1_DATA_O,
- SDIO1_DATA_T,
- SDIO1_LED,
- SDIO1_CDN,
- SDIO1_WP,
- SDIO1_BUSPOW,
- SDIO1_BUSVOLT,
- SPI0_SCLK_I,
- SPI0_SCLK_O,
- SPI0_SCLK_T,
- SPI0_MOSI_I,
- SPI0_MOSI_O,
- SPI0_MOSI_T,
- SPI0_MISO_I,
- SPI0_MISO_O,
- SPI0_MISO_T,
- SPI0_SS_I,
- SPI0_SS_O,
- SPI0_SS1_O,
- SPI0_SS2_O,
- SPI0_SS_T,
- SPI1_SCLK_I,
- SPI1_SCLK_O,
- SPI1_SCLK_T,
- SPI1_MOSI_I,
- SPI1_MOSI_O,
- SPI1_MOSI_T,
- SPI1_MISO_I,
- SPI1_MISO_O,
- SPI1_MISO_T,
- SPI1_SS_I,
- SPI1_SS_O,
- SPI1_SS1_O,
- SPI1_SS2_O,
- SPI1_SS_T,
- UART0_DTRN,
- UART0_RTSN,
- UART0_TX,
- UART0_CTSN,
- UART0_DCDN,
- UART0_DSRN,
- UART0_RIN,
- UART0_RX,
- UART1_DTRN,
- UART1_RTSN,
- UART1_TX,
- UART1_CTSN,
- UART1_DCDN,
- UART1_DSRN,
- UART1_RIN,
- UART1_RX,
- TTC0_WAVE0_OUT,
- TTC0_WAVE1_OUT,
- TTC0_WAVE2_OUT,
- TTC0_CLK0_IN,
- TTC0_CLK1_IN,
- TTC0_CLK2_IN,
- TTC1_WAVE0_OUT,
- TTC1_WAVE1_OUT,
- TTC1_WAVE2_OUT,
- TTC1_CLK0_IN,
- TTC1_CLK1_IN,
- TTC1_CLK2_IN,
- WDT_CLK_IN,
- WDT_RST_OUT,
- TRACE_CLK,
- TRACE_CTL,
- TRACE_DATA,
- TRACE_CLK_OUT,
- USB0_PORT_INDCTL,
- USB0_VBUS_PWRSELECT,
- USB0_VBUS_PWRFAULT,
- USB1_PORT_INDCTL,
- USB1_VBUS_PWRSELECT,
- USB1_VBUS_PWRFAULT,
- SRAM_INTIN,
- M_AXI_GP0_ARESETN,
- M_AXI_GP0_ARVALID,
- M_AXI_GP0_AWVALID,
- M_AXI_GP0_BREADY,
- M_AXI_GP0_RREADY,
- M_AXI_GP0_WLAST,
- M_AXI_GP0_WVALID,
- M_AXI_GP0_ARID,
- M_AXI_GP0_AWID,
- M_AXI_GP0_WID,
- M_AXI_GP0_ARBURST,
- M_AXI_GP0_ARLOCK,
- M_AXI_GP0_ARSIZE,
- M_AXI_GP0_AWBURST,
- M_AXI_GP0_AWLOCK,
- M_AXI_GP0_AWSIZE,
- M_AXI_GP0_ARPROT,
- M_AXI_GP0_AWPROT,
- M_AXI_GP0_ARADDR,
- M_AXI_GP0_AWADDR,
- M_AXI_GP0_WDATA,
- M_AXI_GP0_ARCACHE,
- M_AXI_GP0_ARLEN,
- M_AXI_GP0_ARQOS,
- M_AXI_GP0_AWCACHE,
- M_AXI_GP0_AWLEN,
- M_AXI_GP0_AWQOS,
- M_AXI_GP0_WSTRB,
- M_AXI_GP0_ACLK,
- M_AXI_GP0_ARREADY,
- M_AXI_GP0_AWREADY,
- M_AXI_GP0_BVALID,
- M_AXI_GP0_RLAST,
- M_AXI_GP0_RVALID,
- M_AXI_GP0_WREADY,
- M_AXI_GP0_BID,
- M_AXI_GP0_RID,
- M_AXI_GP0_BRESP,
- M_AXI_GP0_RRESP,
- M_AXI_GP0_RDATA,
- M_AXI_GP1_ARESETN,
- M_AXI_GP1_ARVALID,
- M_AXI_GP1_AWVALID,
- M_AXI_GP1_BREADY,
- M_AXI_GP1_RREADY,
- M_AXI_GP1_WLAST,
- M_AXI_GP1_WVALID,
- M_AXI_GP1_ARID,
- M_AXI_GP1_AWID,
- M_AXI_GP1_WID,
- M_AXI_GP1_ARBURST,
- M_AXI_GP1_ARLOCK,
- M_AXI_GP1_ARSIZE,
- M_AXI_GP1_AWBURST,
- M_AXI_GP1_AWLOCK,
- M_AXI_GP1_AWSIZE,
- M_AXI_GP1_ARPROT,
- M_AXI_GP1_AWPROT,
- M_AXI_GP1_ARADDR,
- M_AXI_GP1_AWADDR,
- M_AXI_GP1_WDATA,
- M_AXI_GP1_ARCACHE,
- M_AXI_GP1_ARLEN,
- M_AXI_GP1_ARQOS,
- M_AXI_GP1_AWCACHE,
- M_AXI_GP1_AWLEN,
- M_AXI_GP1_AWQOS,
- M_AXI_GP1_WSTRB,
- M_AXI_GP1_ACLK,
- M_AXI_GP1_ARREADY,
- M_AXI_GP1_AWREADY,
- M_AXI_GP1_BVALID,
- M_AXI_GP1_RLAST,
- M_AXI_GP1_RVALID,
- M_AXI_GP1_WREADY,
- M_AXI_GP1_BID,
- M_AXI_GP1_RID,
- M_AXI_GP1_BRESP,
- M_AXI_GP1_RRESP,
- M_AXI_GP1_RDATA,
- S_AXI_GP0_ARESETN,
- S_AXI_GP0_ARREADY,
- S_AXI_GP0_AWREADY,
- S_AXI_GP0_BVALID,
- S_AXI_GP0_RLAST,
- S_AXI_GP0_RVALID,
- S_AXI_GP0_WREADY,
- S_AXI_GP0_BRESP,
- S_AXI_GP0_RRESP,
- S_AXI_GP0_RDATA,
- S_AXI_GP0_BID,
- S_AXI_GP0_RID,
- S_AXI_GP0_ACLK,
- S_AXI_GP0_ARVALID,
- S_AXI_GP0_AWVALID,
- S_AXI_GP0_BREADY,
- S_AXI_GP0_RREADY,
- S_AXI_GP0_WLAST,
- S_AXI_GP0_WVALID,
- S_AXI_GP0_ARBURST,
- S_AXI_GP0_ARLOCK,
- S_AXI_GP0_ARSIZE,
- S_AXI_GP0_AWBURST,
- S_AXI_GP0_AWLOCK,
- S_AXI_GP0_AWSIZE,
- S_AXI_GP0_ARPROT,
- S_AXI_GP0_AWPROT,
- S_AXI_GP0_ARADDR,
- S_AXI_GP0_AWADDR,
- S_AXI_GP0_WDATA,
- S_AXI_GP0_ARCACHE,
- S_AXI_GP0_ARLEN,
- S_AXI_GP0_ARQOS,
- S_AXI_GP0_AWCACHE,
- S_AXI_GP0_AWLEN,
- S_AXI_GP0_AWQOS,
- S_AXI_GP0_WSTRB,
- S_AXI_GP0_ARID,
- S_AXI_GP0_AWID,
- S_AXI_GP0_WID,
- S_AXI_GP1_ARESETN,
- S_AXI_GP1_ARREADY,
- S_AXI_GP1_AWREADY,
- S_AXI_GP1_BVALID,
- S_AXI_GP1_RLAST,
- S_AXI_GP1_RVALID,
- S_AXI_GP1_WREADY,
- S_AXI_GP1_BRESP,
- S_AXI_GP1_RRESP,
- S_AXI_GP1_RDATA,
- S_AXI_GP1_BID,
- S_AXI_GP1_RID,
- S_AXI_GP1_ACLK,
- S_AXI_GP1_ARVALID,
- S_AXI_GP1_AWVALID,
- S_AXI_GP1_BREADY,
- S_AXI_GP1_RREADY,
- S_AXI_GP1_WLAST,
- S_AXI_GP1_WVALID,
- S_AXI_GP1_ARBURST,
- S_AXI_GP1_ARLOCK,
- S_AXI_GP1_ARSIZE,
- S_AXI_GP1_AWBURST,
- S_AXI_GP1_AWLOCK,
- S_AXI_GP1_AWSIZE,
- S_AXI_GP1_ARPROT,
- S_AXI_GP1_AWPROT,
- S_AXI_GP1_ARADDR,
- S_AXI_GP1_AWADDR,
- S_AXI_GP1_WDATA,
- S_AXI_GP1_ARCACHE,
- S_AXI_GP1_ARLEN,
- S_AXI_GP1_ARQOS,
- S_AXI_GP1_AWCACHE,
- S_AXI_GP1_AWLEN,
- S_AXI_GP1_AWQOS,
- S_AXI_GP1_WSTRB,
- S_AXI_GP1_ARID,
- S_AXI_GP1_AWID,
- S_AXI_GP1_WID,
- S_AXI_ACP_ARESETN,
- S_AXI_ACP_ARREADY,
- S_AXI_ACP_AWREADY,
- S_AXI_ACP_BVALID,
- S_AXI_ACP_RLAST,
- S_AXI_ACP_RVALID,
- S_AXI_ACP_WREADY,
- S_AXI_ACP_BRESP,
- S_AXI_ACP_RRESP,
- S_AXI_ACP_BID,
- S_AXI_ACP_RID,
- S_AXI_ACP_RDATA,
- S_AXI_ACP_ACLK,
- S_AXI_ACP_ARVALID,
- S_AXI_ACP_AWVALID,
- S_AXI_ACP_BREADY,
- S_AXI_ACP_RREADY,
- S_AXI_ACP_WLAST,
- S_AXI_ACP_WVALID,
- S_AXI_ACP_ARID,
- S_AXI_ACP_ARPROT,
- S_AXI_ACP_AWID,
- S_AXI_ACP_AWPROT,
- S_AXI_ACP_WID,
- S_AXI_ACP_ARADDR,
- S_AXI_ACP_AWADDR,
- S_AXI_ACP_ARCACHE,
- S_AXI_ACP_ARLEN,
- S_AXI_ACP_ARQOS,
- S_AXI_ACP_AWCACHE,
- S_AXI_ACP_AWLEN,
- S_AXI_ACP_AWQOS,
- S_AXI_ACP_ARBURST,
- S_AXI_ACP_ARLOCK,
- S_AXI_ACP_ARSIZE,
- S_AXI_ACP_AWBURST,
- S_AXI_ACP_AWLOCK,
- S_AXI_ACP_AWSIZE,
- S_AXI_ACP_ARUSER,
- S_AXI_ACP_AWUSER,
- S_AXI_ACP_WDATA,
- S_AXI_ACP_WSTRB,
- S_AXI_HP0_ARESETN,
- S_AXI_HP0_ARREADY,
- S_AXI_HP0_AWREADY,
- S_AXI_HP0_BVALID,
- S_AXI_HP0_RLAST,
- S_AXI_HP0_RVALID,
- S_AXI_HP0_WREADY,
- S_AXI_HP0_BRESP,
- S_AXI_HP0_RRESP,
- S_AXI_HP0_BID,
- S_AXI_HP0_RID,
- S_AXI_HP0_RDATA,
- S_AXI_HP0_RCOUNT,
- S_AXI_HP0_WCOUNT,
- S_AXI_HP0_RACOUNT,
- S_AXI_HP0_WACOUNT,
- S_AXI_HP0_ACLK,
- S_AXI_HP0_ARVALID,
- S_AXI_HP0_AWVALID,
- S_AXI_HP0_BREADY,
- S_AXI_HP0_RDISSUECAP1_EN,
- S_AXI_HP0_RREADY,
- S_AXI_HP0_WLAST,
- S_AXI_HP0_WRISSUECAP1_EN,
- S_AXI_HP0_WVALID,
- S_AXI_HP0_ARBURST,
- S_AXI_HP0_ARLOCK,
- S_AXI_HP0_ARSIZE,
- S_AXI_HP0_AWBURST,
- S_AXI_HP0_AWLOCK,
- S_AXI_HP0_AWSIZE,
- S_AXI_HP0_ARPROT,
- S_AXI_HP0_AWPROT,
- S_AXI_HP0_ARADDR,
- S_AXI_HP0_AWADDR,
- S_AXI_HP0_ARCACHE,
- S_AXI_HP0_ARLEN,
- S_AXI_HP0_ARQOS,
- S_AXI_HP0_AWCACHE,
- S_AXI_HP0_AWLEN,
- S_AXI_HP0_AWQOS,
- S_AXI_HP0_ARID,
- S_AXI_HP0_AWID,
- S_AXI_HP0_WID,
- S_AXI_HP0_WDATA,
- S_AXI_HP0_WSTRB,
- S_AXI_HP1_ARESETN,
- S_AXI_HP1_ARREADY,
- S_AXI_HP1_AWREADY,
- S_AXI_HP1_BVALID,
- S_AXI_HP1_RLAST,
- S_AXI_HP1_RVALID,
- S_AXI_HP1_WREADY,
- S_AXI_HP1_BRESP,
- S_AXI_HP1_RRESP,
- S_AXI_HP1_BID,
- S_AXI_HP1_RID,
- S_AXI_HP1_RDATA,
- S_AXI_HP1_RCOUNT,
- S_AXI_HP1_WCOUNT,
- S_AXI_HP1_RACOUNT,
- S_AXI_HP1_WACOUNT,
- S_AXI_HP1_ACLK,
- S_AXI_HP1_ARVALID,
- S_AXI_HP1_AWVALID,
- S_AXI_HP1_BREADY,
- S_AXI_HP1_RDISSUECAP1_EN,
- S_AXI_HP1_RREADY,
- S_AXI_HP1_WLAST,
- S_AXI_HP1_WRISSUECAP1_EN,
- S_AXI_HP1_WVALID,
- S_AXI_HP1_ARBURST,
- S_AXI_HP1_ARLOCK,
- S_AXI_HP1_ARSIZE,
- S_AXI_HP1_AWBURST,
- S_AXI_HP1_AWLOCK,
- S_AXI_HP1_AWSIZE,
- S_AXI_HP1_ARPROT,
- S_AXI_HP1_AWPROT,
- S_AXI_HP1_ARADDR,
- S_AXI_HP1_AWADDR,
- S_AXI_HP1_ARCACHE,
- S_AXI_HP1_ARLEN,
- S_AXI_HP1_ARQOS,
- S_AXI_HP1_AWCACHE,
- S_AXI_HP1_AWLEN,
- S_AXI_HP1_AWQOS,
- S_AXI_HP1_ARID,
- S_AXI_HP1_AWID,
- S_AXI_HP1_WID,
- S_AXI_HP1_WDATA,
- S_AXI_HP1_WSTRB,
- S_AXI_HP2_ARESETN,
- S_AXI_HP2_ARREADY,
- S_AXI_HP2_AWREADY,
- S_AXI_HP2_BVALID,
- S_AXI_HP2_RLAST,
- S_AXI_HP2_RVALID,
- S_AXI_HP2_WREADY,
- S_AXI_HP2_BRESP,
- S_AXI_HP2_RRESP,
- S_AXI_HP2_BID,
- S_AXI_HP2_RID,
- S_AXI_HP2_RDATA,
- S_AXI_HP2_RCOUNT,
- S_AXI_HP2_WCOUNT,
- S_AXI_HP2_RACOUNT,
- S_AXI_HP2_WACOUNT,
- S_AXI_HP2_ACLK,
- S_AXI_HP2_ARVALID,
- S_AXI_HP2_AWVALID,
- S_AXI_HP2_BREADY,
- S_AXI_HP2_RDISSUECAP1_EN,
- S_AXI_HP2_RREADY,
- S_AXI_HP2_WLAST,
- S_AXI_HP2_WRISSUECAP1_EN,
- S_AXI_HP2_WVALID,
- S_AXI_HP2_ARBURST,
- S_AXI_HP2_ARLOCK,
- S_AXI_HP2_ARSIZE,
- S_AXI_HP2_AWBURST,
- S_AXI_HP2_AWLOCK,
- S_AXI_HP2_AWSIZE,
- S_AXI_HP2_ARPROT,
- S_AXI_HP2_AWPROT,
- S_AXI_HP2_ARADDR,
- S_AXI_HP2_AWADDR,
- S_AXI_HP2_ARCACHE,
- S_AXI_HP2_ARLEN,
- S_AXI_HP2_ARQOS,
- S_AXI_HP2_AWCACHE,
- S_AXI_HP2_AWLEN,
- S_AXI_HP2_AWQOS,
- S_AXI_HP2_ARID,
- S_AXI_HP2_AWID,
- S_AXI_HP2_WID,
- S_AXI_HP2_WDATA,
- S_AXI_HP2_WSTRB,
- S_AXI_HP3_ARESETN,
- S_AXI_HP3_ARREADY,
- S_AXI_HP3_AWREADY,
- S_AXI_HP3_BVALID,
- S_AXI_HP3_RLAST,
- S_AXI_HP3_RVALID,
- S_AXI_HP3_WREADY,
- S_AXI_HP3_BRESP,
- S_AXI_HP3_RRESP,
- S_AXI_HP3_BID,
- S_AXI_HP3_RID,
- S_AXI_HP3_RDATA,
- S_AXI_HP3_RCOUNT,
- S_AXI_HP3_WCOUNT,
- S_AXI_HP3_RACOUNT,
- S_AXI_HP3_WACOUNT,
- S_AXI_HP3_ACLK,
- S_AXI_HP3_ARVALID,
- S_AXI_HP3_AWVALID,
- S_AXI_HP3_BREADY,
- S_AXI_HP3_RDISSUECAP1_EN,
- S_AXI_HP3_RREADY,
- S_AXI_HP3_WLAST,
- S_AXI_HP3_WRISSUECAP1_EN,
- S_AXI_HP3_WVALID,
- S_AXI_HP3_ARBURST,
- S_AXI_HP3_ARLOCK,
- S_AXI_HP3_ARSIZE,
- S_AXI_HP3_AWBURST,
- S_AXI_HP3_AWLOCK,
- S_AXI_HP3_AWSIZE,
- S_AXI_HP3_ARPROT,
- S_AXI_HP3_AWPROT,
- S_AXI_HP3_ARADDR,
- S_AXI_HP3_AWADDR,
- S_AXI_HP3_ARCACHE,
- S_AXI_HP3_ARLEN,
- S_AXI_HP3_ARQOS,
- S_AXI_HP3_AWCACHE,
- S_AXI_HP3_AWLEN,
- S_AXI_HP3_AWQOS,
- S_AXI_HP3_ARID,
- S_AXI_HP3_AWID,
- S_AXI_HP3_WID,
- S_AXI_HP3_WDATA,
- S_AXI_HP3_WSTRB,
- IRQ_P2F_DMAC_ABORT,
- IRQ_P2F_DMAC0,
- IRQ_P2F_DMAC1,
- IRQ_P2F_DMAC2,
- IRQ_P2F_DMAC3,
- IRQ_P2F_DMAC4,
- IRQ_P2F_DMAC5,
- IRQ_P2F_DMAC6,
- IRQ_P2F_DMAC7,
- IRQ_P2F_SMC,
- IRQ_P2F_QSPI,
- IRQ_P2F_CTI,
- IRQ_P2F_GPIO,
- IRQ_P2F_USB0,
- IRQ_P2F_ENET0,
- IRQ_P2F_ENET_WAKE0,
- IRQ_P2F_SDIO0,
- IRQ_P2F_I2C0,
- IRQ_P2F_SPI0,
- IRQ_P2F_UART0,
- IRQ_P2F_CAN0,
- IRQ_P2F_USB1,
- IRQ_P2F_ENET1,
- IRQ_P2F_ENET_WAKE1,
- IRQ_P2F_SDIO1,
- IRQ_P2F_I2C1,
- IRQ_P2F_SPI1,
- IRQ_P2F_UART1,
- IRQ_P2F_CAN1,
- IRQ_F2P,
- Core0_nFIQ,
- Core0_nIRQ,
- Core1_nFIQ,
- Core1_nIRQ,
- DMA0_DATYPE,
- DMA0_DAVALID,
- DMA0_DRREADY,
- DMA0_RSTN,
- DMA1_DATYPE,
- DMA1_DAVALID,
- DMA1_DRREADY,
- DMA1_RSTN,
- DMA2_DATYPE,
- DMA2_DAVALID,
- DMA2_DRREADY,
- DMA2_RSTN,
- DMA3_DATYPE,
- DMA3_DAVALID,
- DMA3_DRREADY,
- DMA3_RSTN,
- DMA0_ACLK,
- DMA0_DAREADY,
- DMA0_DRLAST,
- DMA0_DRVALID,
- DMA1_ACLK,
- DMA1_DAREADY,
- DMA1_DRLAST,
- DMA1_DRVALID,
- DMA2_ACLK,
- DMA2_DAREADY,
- DMA2_DRLAST,
- DMA2_DRVALID,
- DMA3_ACLK,
- DMA3_DAREADY,
- DMA3_DRLAST,
- DMA3_DRVALID,
- DMA0_DRTYPE,
- DMA1_DRTYPE,
- DMA2_DRTYPE,
- DMA3_DRTYPE,
- FCLK_CLK3,
- FCLK_CLK2,
- FCLK_CLK1,
- FCLK_CLK0,
- FCLK_CLKTRIG3_N,
- FCLK_CLKTRIG2_N,
- FCLK_CLKTRIG1_N,
- FCLK_CLKTRIG0_N,
- FCLK_RESET3_N,
- FCLK_RESET2_N,
- FCLK_RESET1_N,
- FCLK_RESET0_N,
- FTMD_TRACEIN_DATA,
- FTMD_TRACEIN_VALID,
- FTMD_TRACEIN_CLK,
- FTMD_TRACEIN_ATID,
- FTMT_F2P_TRIG_0,
- FTMT_F2P_TRIGACK_0,
- FTMT_F2P_TRIG_1,
- FTMT_F2P_TRIGACK_1,
- FTMT_F2P_TRIG_2,
- FTMT_F2P_TRIGACK_2,
- FTMT_F2P_TRIG_3,
- FTMT_F2P_TRIGACK_3,
- FTMT_F2P_DEBUG,
- FTMT_P2F_TRIGACK_0,
- FTMT_P2F_TRIG_0,
- FTMT_P2F_TRIGACK_1,
- FTMT_P2F_TRIG_1,
- FTMT_P2F_TRIGACK_2,
- FTMT_P2F_TRIG_2,
- FTMT_P2F_TRIGACK_3,
- FTMT_P2F_TRIG_3,
- FTMT_P2F_DEBUG,
- FPGA_IDLE_N,
- EVENT_EVENTO,
- EVENT_STANDBYWFE,
- EVENT_STANDBYWFI,
- EVENT_EVENTI,
- DDR_ARB,
- MIO,
- DDR_CAS_n,
- DDR_CKE,
- DDR_Clk_n,
- DDR_Clk,
- DDR_CS_n,
- DDR_DRSTB,
- DDR_ODT,
- DDR_RAS_n,
- DDR_WEB,
- DDR_BankAddr,
- DDR_Addr,
- DDR_VRN,
- DDR_VRP,
- DDR_DM,
- DDR_DQ,
- DDR_DQS_n,
- DDR_DQS,
- PS_SRSTB,
- PS_CLK,
- PS_PORB);
- output CAN0_PHY_TX;
- input CAN0_PHY_RX;
- output CAN1_PHY_TX;
- input CAN1_PHY_RX;
- output ENET0_GMII_TX_EN;
- output ENET0_GMII_TX_ER;
- output ENET0_MDIO_MDC;
- output ENET0_MDIO_O;
- output ENET0_MDIO_T;
- output ENET0_PTP_DELAY_REQ_RX;
- output ENET0_PTP_DELAY_REQ_TX;
- output ENET0_PTP_PDELAY_REQ_RX;
- output ENET0_PTP_PDELAY_REQ_TX;
- output ENET0_PTP_PDELAY_RESP_RX;
- output ENET0_PTP_PDELAY_RESP_TX;
- output ENET0_PTP_SYNC_FRAME_RX;
- output ENET0_PTP_SYNC_FRAME_TX;
- output ENET0_SOF_RX;
- output ENET0_SOF_TX;
- output [7:0]ENET0_GMII_TXD;
- input ENET0_GMII_COL;
- input ENET0_GMII_CRS;
- input ENET0_GMII_RX_CLK;
- input ENET0_GMII_RX_DV;
- input ENET0_GMII_RX_ER;
- input ENET0_GMII_TX_CLK;
- input ENET0_MDIO_I;
- input ENET0_EXT_INTIN;
- input [7:0]ENET0_GMII_RXD;
- output ENET1_GMII_TX_EN;
- output ENET1_GMII_TX_ER;
- output ENET1_MDIO_MDC;
- output ENET1_MDIO_O;
- output ENET1_MDIO_T;
- output ENET1_PTP_DELAY_REQ_RX;
- output ENET1_PTP_DELAY_REQ_TX;
- output ENET1_PTP_PDELAY_REQ_RX;
- output ENET1_PTP_PDELAY_REQ_TX;
- output ENET1_PTP_PDELAY_RESP_RX;
- output ENET1_PTP_PDELAY_RESP_TX;
- output ENET1_PTP_SYNC_FRAME_RX;
- output ENET1_PTP_SYNC_FRAME_TX;
- output ENET1_SOF_RX;
- output ENET1_SOF_TX;
- output [7:0]ENET1_GMII_TXD;
- input ENET1_GMII_COL;
- input ENET1_GMII_CRS;
- input ENET1_GMII_RX_CLK;
- input ENET1_GMII_RX_DV;
- input ENET1_GMII_RX_ER;
- input ENET1_GMII_TX_CLK;
- input ENET1_MDIO_I;
- input ENET1_EXT_INTIN;
- input [7:0]ENET1_GMII_RXD;
- input [63:0]GPIO_I;
- output [63:0]GPIO_O;
- output [63:0]GPIO_T;
- input I2C0_SDA_I;
- output I2C0_SDA_O;
- output I2C0_SDA_T;
- input I2C0_SCL_I;
- output I2C0_SCL_O;
- output I2C0_SCL_T;
- input I2C1_SDA_I;
- output I2C1_SDA_O;
- output I2C1_SDA_T;
- input I2C1_SCL_I;
- output I2C1_SCL_O;
- output I2C1_SCL_T;
- input PJTAG_TCK;
- input PJTAG_TMS;
- input PJTAG_TDI;
- output PJTAG_TDO;
- output SDIO0_CLK;
- input SDIO0_CLK_FB;
- output SDIO0_CMD_O;
- input SDIO0_CMD_I;
- output SDIO0_CMD_T;
- input [3:0]SDIO0_DATA_I;
- output [3:0]SDIO0_DATA_O;
- output [3:0]SDIO0_DATA_T;
- output SDIO0_LED;
- input SDIO0_CDN;
- input SDIO0_WP;
- output SDIO0_BUSPOW;
- output [2:0]SDIO0_BUSVOLT;
- output SDIO1_CLK;
- input SDIO1_CLK_FB;
- output SDIO1_CMD_O;
- input SDIO1_CMD_I;
- output SDIO1_CMD_T;
- input [3:0]SDIO1_DATA_I;
- output [3:0]SDIO1_DATA_O;
- output [3:0]SDIO1_DATA_T;
- output SDIO1_LED;
- input SDIO1_CDN;
- input SDIO1_WP;
- output SDIO1_BUSPOW;
- output [2:0]SDIO1_BUSVOLT;
- input SPI0_SCLK_I;
- output SPI0_SCLK_O;
- output SPI0_SCLK_T;
- input SPI0_MOSI_I;
- output SPI0_MOSI_O;
- output SPI0_MOSI_T;
- input SPI0_MISO_I;
- output SPI0_MISO_O;
- output SPI0_MISO_T;
- input SPI0_SS_I;
- output SPI0_SS_O;
- output SPI0_SS1_O;
- output SPI0_SS2_O;
- output SPI0_SS_T;
- input SPI1_SCLK_I;
- output SPI1_SCLK_O;
- output SPI1_SCLK_T;
- input SPI1_MOSI_I;
- output SPI1_MOSI_O;
- output SPI1_MOSI_T;
- input SPI1_MISO_I;
- output SPI1_MISO_O;
- output SPI1_MISO_T;
- input SPI1_SS_I;
- output SPI1_SS_O;
- output SPI1_SS1_O;
- output SPI1_SS2_O;
- output SPI1_SS_T;
- output UART0_DTRN;
- output UART0_RTSN;
- output UART0_TX;
- input UART0_CTSN;
- input UART0_DCDN;
- input UART0_DSRN;
- input UART0_RIN;
- input UART0_RX;
- output UART1_DTRN;
- output UART1_RTSN;
- output UART1_TX;
- input UART1_CTSN;
- input UART1_DCDN;
- input UART1_DSRN;
- input UART1_RIN;
- input UART1_RX;
- output TTC0_WAVE0_OUT;
- output TTC0_WAVE1_OUT;
- output TTC0_WAVE2_OUT;
- input TTC0_CLK0_IN;
- input TTC0_CLK1_IN;
- input TTC0_CLK2_IN;
- output TTC1_WAVE0_OUT;
- output TTC1_WAVE1_OUT;
- output TTC1_WAVE2_OUT;
- input TTC1_CLK0_IN;
- input TTC1_CLK1_IN;
- input TTC1_CLK2_IN;
- input WDT_CLK_IN;
- output WDT_RST_OUT;
- input TRACE_CLK;
- output TRACE_CTL;
- output [1:0]TRACE_DATA;
- output TRACE_CLK_OUT;
- output [1:0]USB0_PORT_INDCTL;
- output USB0_VBUS_PWRSELECT;
- input USB0_VBUS_PWRFAULT;
- output [1:0]USB1_PORT_INDCTL;
- output USB1_VBUS_PWRSELECT;
- input USB1_VBUS_PWRFAULT;
- input SRAM_INTIN;
- output M_AXI_GP0_ARESETN;
- output M_AXI_GP0_ARVALID;
- output M_AXI_GP0_AWVALID;
- output M_AXI_GP0_BREADY;
- output M_AXI_GP0_RREADY;
- output M_AXI_GP0_WLAST;
- output M_AXI_GP0_WVALID;
- output [11:0]M_AXI_GP0_ARID;
- output [11:0]M_AXI_GP0_AWID;
- output [11:0]M_AXI_GP0_WID;
- output [1:0]M_AXI_GP0_ARBURST;
- output [1:0]M_AXI_GP0_ARLOCK;
- output [2:0]M_AXI_GP0_ARSIZE;
- output [1:0]M_AXI_GP0_AWBURST;
- output [1:0]M_AXI_GP0_AWLOCK;
- output [2:0]M_AXI_GP0_AWSIZE;
- output [2:0]M_AXI_GP0_ARPROT;
- output [2:0]M_AXI_GP0_AWPROT;
- output [31:0]M_AXI_GP0_ARADDR;
- output [31:0]M_AXI_GP0_AWADDR;
- output [31:0]M_AXI_GP0_WDATA;
- output [3:0]M_AXI_GP0_ARCACHE;
- output [3:0]M_AXI_GP0_ARLEN;
- output [3:0]M_AXI_GP0_ARQOS;
- output [3:0]M_AXI_GP0_AWCACHE;
- output [3:0]M_AXI_GP0_AWLEN;
- output [3:0]M_AXI_GP0_AWQOS;
- output [3:0]M_AXI_GP0_WSTRB;
- input M_AXI_GP0_ACLK;
- input M_AXI_GP0_ARREADY;
- input M_AXI_GP0_AWREADY;
- input M_AXI_GP0_BVALID;
- input M_AXI_GP0_RLAST;
- input M_AXI_GP0_RVALID;
- input M_AXI_GP0_WREADY;
- input [11:0]M_AXI_GP0_BID;
- input [11:0]M_AXI_GP0_RID;
- input [1:0]M_AXI_GP0_BRESP;
- input [1:0]M_AXI_GP0_RRESP;
- input [31:0]M_AXI_GP0_RDATA;
- output M_AXI_GP1_ARESETN;
- output M_AXI_GP1_ARVALID;
- output M_AXI_GP1_AWVALID;
- output M_AXI_GP1_BREADY;
- output M_AXI_GP1_RREADY;
- output M_AXI_GP1_WLAST;
- output M_AXI_GP1_WVALID;
- output [11:0]M_AXI_GP1_ARID;
- output [11:0]M_AXI_GP1_AWID;
- output [11:0]M_AXI_GP1_WID;
- output [1:0]M_AXI_GP1_ARBURST;
- output [1:0]M_AXI_GP1_ARLOCK;
- output [2:0]M_AXI_GP1_ARSIZE;
- output [1:0]M_AXI_GP1_AWBURST;
- output [1:0]M_AXI_GP1_AWLOCK;
- output [2:0]M_AXI_GP1_AWSIZE;
- output [2:0]M_AXI_GP1_ARPROT;
- output [2:0]M_AXI_GP1_AWPROT;
- output [31:0]M_AXI_GP1_ARADDR;
- output [31:0]M_AXI_GP1_AWADDR;
- output [31:0]M_AXI_GP1_WDATA;
- output [3:0]M_AXI_GP1_ARCACHE;
- output [3:0]M_AXI_GP1_ARLEN;
- output [3:0]M_AXI_GP1_ARQOS;
- output [3:0]M_AXI_GP1_AWCACHE;
- output [3:0]M_AXI_GP1_AWLEN;
- output [3:0]M_AXI_GP1_AWQOS;
- output [3:0]M_AXI_GP1_WSTRB;
- input M_AXI_GP1_ACLK;
- input M_AXI_GP1_ARREADY;
- input M_AXI_GP1_AWREADY;
- input M_AXI_GP1_BVALID;
- input M_AXI_GP1_RLAST;
- input M_AXI_GP1_RVALID;
- input M_AXI_GP1_WREADY;
- input [11:0]M_AXI_GP1_BID;
- input [11:0]M_AXI_GP1_RID;
- input [1:0]M_AXI_GP1_BRESP;
- input [1:0]M_AXI_GP1_RRESP;
- input [31:0]M_AXI_GP1_RDATA;
- output S_AXI_GP0_ARESETN;
- output S_AXI_GP0_ARREADY;
- output S_AXI_GP0_AWREADY;
- output S_AXI_GP0_BVALID;
- output S_AXI_GP0_RLAST;
- output S_AXI_GP0_RVALID;
- output S_AXI_GP0_WREADY;
- output [1:0]S_AXI_GP0_BRESP;
- output [1:0]S_AXI_GP0_RRESP;
- output [31:0]S_AXI_GP0_RDATA;
- output [5:0]S_AXI_GP0_BID;
- output [5:0]S_AXI_GP0_RID;
- input S_AXI_GP0_ACLK;
- input S_AXI_GP0_ARVALID;
- input S_AXI_GP0_AWVALID;
- input S_AXI_GP0_BREADY;
- input S_AXI_GP0_RREADY;
- input S_AXI_GP0_WLAST;
- input S_AXI_GP0_WVALID;
- input [1:0]S_AXI_GP0_ARBURST;
- input [1:0]S_AXI_GP0_ARLOCK;
- input [2:0]S_AXI_GP0_ARSIZE;
- input [1:0]S_AXI_GP0_AWBURST;
- input [1:0]S_AXI_GP0_AWLOCK;
- input [2:0]S_AXI_GP0_AWSIZE;
- input [2:0]S_AXI_GP0_ARPROT;
- input [2:0]S_AXI_GP0_AWPROT;
- input [31:0]S_AXI_GP0_ARADDR;
- input [31:0]S_AXI_GP0_AWADDR;
- input [31:0]S_AXI_GP0_WDATA;
- input [3:0]S_AXI_GP0_ARCACHE;
- input [3:0]S_AXI_GP0_ARLEN;
- input [3:0]S_AXI_GP0_ARQOS;
- input [3:0]S_AXI_GP0_AWCACHE;
- input [3:0]S_AXI_GP0_AWLEN;
- input [3:0]S_AXI_GP0_AWQOS;
- input [3:0]S_AXI_GP0_WSTRB;
- input [5:0]S_AXI_GP0_ARID;
- input [5:0]S_AXI_GP0_AWID;
- input [5:0]S_AXI_GP0_WID;
- output S_AXI_GP1_ARESETN;
- output S_AXI_GP1_ARREADY;
- output S_AXI_GP1_AWREADY;
- output S_AXI_GP1_BVALID;
- output S_AXI_GP1_RLAST;
- output S_AXI_GP1_RVALID;
- output S_AXI_GP1_WREADY;
- output [1:0]S_AXI_GP1_BRESP;
- output [1:0]S_AXI_GP1_RRESP;
- output [31:0]S_AXI_GP1_RDATA;
- output [5:0]S_AXI_GP1_BID;
- output [5:0]S_AXI_GP1_RID;
- input S_AXI_GP1_ACLK;
- input S_AXI_GP1_ARVALID;
- input S_AXI_GP1_AWVALID;
- input S_AXI_GP1_BREADY;
- input S_AXI_GP1_RREADY;
- input S_AXI_GP1_WLAST;
- input S_AXI_GP1_WVALID;
- input [1:0]S_AXI_GP1_ARBURST;
- input [1:0]S_AXI_GP1_ARLOCK;
- input [2:0]S_AXI_GP1_ARSIZE;
- input [1:0]S_AXI_GP1_AWBURST;
- input [1:0]S_AXI_GP1_AWLOCK;
- input [2:0]S_AXI_GP1_AWSIZE;
- input [2:0]S_AXI_GP1_ARPROT;
- input [2:0]S_AXI_GP1_AWPROT;
- input [31:0]S_AXI_GP1_ARADDR;
- input [31:0]S_AXI_GP1_AWADDR;
- input [31:0]S_AXI_GP1_WDATA;
- input [3:0]S_AXI_GP1_ARCACHE;
- input [3:0]S_AXI_GP1_ARLEN;
- input [3:0]S_AXI_GP1_ARQOS;
- input [3:0]S_AXI_GP1_AWCACHE;
- input [3:0]S_AXI_GP1_AWLEN;
- input [3:0]S_AXI_GP1_AWQOS;
- input [3:0]S_AXI_GP1_WSTRB;
- input [5:0]S_AXI_GP1_ARID;
- input [5:0]S_AXI_GP1_AWID;
- input [5:0]S_AXI_GP1_WID;
- output S_AXI_ACP_ARESETN;
- output S_AXI_ACP_ARREADY;
- output S_AXI_ACP_AWREADY;
- output S_AXI_ACP_BVALID;
- output S_AXI_ACP_RLAST;
- output S_AXI_ACP_RVALID;
- output S_AXI_ACP_WREADY;
- output [1:0]S_AXI_ACP_BRESP;
- output [1:0]S_AXI_ACP_RRESP;
- output [2:0]S_AXI_ACP_BID;
- output [2:0]S_AXI_ACP_RID;
- output [63:0]S_AXI_ACP_RDATA;
- input S_AXI_ACP_ACLK;
- input S_AXI_ACP_ARVALID;
- input S_AXI_ACP_AWVALID;
- input S_AXI_ACP_BREADY;
- input S_AXI_ACP_RREADY;
- input S_AXI_ACP_WLAST;
- input S_AXI_ACP_WVALID;
- input [2:0]S_AXI_ACP_ARID;
- input [2:0]S_AXI_ACP_ARPROT;
- input [2:0]S_AXI_ACP_AWID;
- input [2:0]S_AXI_ACP_AWPROT;
- input [2:0]S_AXI_ACP_WID;
- input [31:0]S_AXI_ACP_ARADDR;
- input [31:0]S_AXI_ACP_AWADDR;
- input [3:0]S_AXI_ACP_ARCACHE;
- input [3:0]S_AXI_ACP_ARLEN;
- input [3:0]S_AXI_ACP_ARQOS;
- input [3:0]S_AXI_ACP_AWCACHE;
- input [3:0]S_AXI_ACP_AWLEN;
- input [3:0]S_AXI_ACP_AWQOS;
- input [1:0]S_AXI_ACP_ARBURST;
- input [1:0]S_AXI_ACP_ARLOCK;
- input [2:0]S_AXI_ACP_ARSIZE;
- input [1:0]S_AXI_ACP_AWBURST;
- input [1:0]S_AXI_ACP_AWLOCK;
- input [2:0]S_AXI_ACP_AWSIZE;
- input [4:0]S_AXI_ACP_ARUSER;
- input [4:0]S_AXI_ACP_AWUSER;
- input [63:0]S_AXI_ACP_WDATA;
- input [7:0]S_AXI_ACP_WSTRB;
- output S_AXI_HP0_ARESETN;
- output S_AXI_HP0_ARREADY;
- output S_AXI_HP0_AWREADY;
- output S_AXI_HP0_BVALID;
- output S_AXI_HP0_RLAST;
- output S_AXI_HP0_RVALID;
- output S_AXI_HP0_WREADY;
- output [1:0]S_AXI_HP0_BRESP;
- output [1:0]S_AXI_HP0_RRESP;
- output [5:0]S_AXI_HP0_BID;
- output [5:0]S_AXI_HP0_RID;
- output [63:0]S_AXI_HP0_RDATA;
- output [7:0]S_AXI_HP0_RCOUNT;
- output [7:0]S_AXI_HP0_WCOUNT;
- output [2:0]S_AXI_HP0_RACOUNT;
- output [5:0]S_AXI_HP0_WACOUNT;
- input S_AXI_HP0_ACLK;
- input S_AXI_HP0_ARVALID;
- input S_AXI_HP0_AWVALID;
- input S_AXI_HP0_BREADY;
- input S_AXI_HP0_RDISSUECAP1_EN;
- input S_AXI_HP0_RREADY;
- input S_AXI_HP0_WLAST;
- input S_AXI_HP0_WRISSUECAP1_EN;
- input S_AXI_HP0_WVALID;
- input [1:0]S_AXI_HP0_ARBURST;
- input [1:0]S_AXI_HP0_ARLOCK;
- input [2:0]S_AXI_HP0_ARSIZE;
- input [1:0]S_AXI_HP0_AWBURST;
- input [1:0]S_AXI_HP0_AWLOCK;
- input [2:0]S_AXI_HP0_AWSIZE;
- input [2:0]S_AXI_HP0_ARPROT;
- input [2:0]S_AXI_HP0_AWPROT;
- input [31:0]S_AXI_HP0_ARADDR;
- input [31:0]S_AXI_HP0_AWADDR;
- input [3:0]S_AXI_HP0_ARCACHE;
- input [3:0]S_AXI_HP0_ARLEN;
- input [3:0]S_AXI_HP0_ARQOS;
- input [3:0]S_AXI_HP0_AWCACHE;
- input [3:0]S_AXI_HP0_AWLEN;
- input [3:0]S_AXI_HP0_AWQOS;
- input [5:0]S_AXI_HP0_ARID;
- input [5:0]S_AXI_HP0_AWID;
- input [5:0]S_AXI_HP0_WID;
- input [63:0]S_AXI_HP0_WDATA;
- input [7:0]S_AXI_HP0_WSTRB;
- output S_AXI_HP1_ARESETN;
- output S_AXI_HP1_ARREADY;
- output S_AXI_HP1_AWREADY;
- output S_AXI_HP1_BVALID;
- output S_AXI_HP1_RLAST;
- output S_AXI_HP1_RVALID;
- output S_AXI_HP1_WREADY;
- output [1:0]S_AXI_HP1_BRESP;
- output [1:0]S_AXI_HP1_RRESP;
- output [5:0]S_AXI_HP1_BID;
- output [5:0]S_AXI_HP1_RID;
- output [63:0]S_AXI_HP1_RDATA;
- output [7:0]S_AXI_HP1_RCOUNT;
- output [7:0]S_AXI_HP1_WCOUNT;
- output [2:0]S_AXI_HP1_RACOUNT;
- output [5:0]S_AXI_HP1_WACOUNT;
- input S_AXI_HP1_ACLK;
- input S_AXI_HP1_ARVALID;
- input S_AXI_HP1_AWVALID;
- input S_AXI_HP1_BREADY;
- input S_AXI_HP1_RDISSUECAP1_EN;
- input S_AXI_HP1_RREADY;
- input S_AXI_HP1_WLAST;
- input S_AXI_HP1_WRISSUECAP1_EN;
- input S_AXI_HP1_WVALID;
- input [1:0]S_AXI_HP1_ARBURST;
- input [1:0]S_AXI_HP1_ARLOCK;
- input [2:0]S_AXI_HP1_ARSIZE;
- input [1:0]S_AXI_HP1_AWBURST;
- input [1:0]S_AXI_HP1_AWLOCK;
- input [2:0]S_AXI_HP1_AWSIZE;
- input [2:0]S_AXI_HP1_ARPROT;
- input [2:0]S_AXI_HP1_AWPROT;
- input [31:0]S_AXI_HP1_ARADDR;
- input [31:0]S_AXI_HP1_AWADDR;
- input [3:0]S_AXI_HP1_ARCACHE;
- input [3:0]S_AXI_HP1_ARLEN;
- input [3:0]S_AXI_HP1_ARQOS;
- input [3:0]S_AXI_HP1_AWCACHE;
- input [3:0]S_AXI_HP1_AWLEN;
- input [3:0]S_AXI_HP1_AWQOS;
- input [5:0]S_AXI_HP1_ARID;
- input [5:0]S_AXI_HP1_AWID;
- input [5:0]S_AXI_HP1_WID;
- input [63:0]S_AXI_HP1_WDATA;
- input [7:0]S_AXI_HP1_WSTRB;
- output S_AXI_HP2_ARESETN;
- output S_AXI_HP2_ARREADY;
- output S_AXI_HP2_AWREADY;
- output S_AXI_HP2_BVALID;
- output S_AXI_HP2_RLAST;
- output S_AXI_HP2_RVALID;
- output S_AXI_HP2_WREADY;
- output [1:0]S_AXI_HP2_BRESP;
- output [1:0]S_AXI_HP2_RRESP;
- output [5:0]S_AXI_HP2_BID;
- output [5:0]S_AXI_HP2_RID;
- output [63:0]S_AXI_HP2_RDATA;
- output [7:0]S_AXI_HP2_RCOUNT;
- output [7:0]S_AXI_HP2_WCOUNT;
- output [2:0]S_AXI_HP2_RACOUNT;
- output [5:0]S_AXI_HP2_WACOUNT;
- input S_AXI_HP2_ACLK;
- input S_AXI_HP2_ARVALID;
- input S_AXI_HP2_AWVALID;
- input S_AXI_HP2_BREADY;
- input S_AXI_HP2_RDISSUECAP1_EN;
- input S_AXI_HP2_RREADY;
- input S_AXI_HP2_WLAST;
- input S_AXI_HP2_WRISSUECAP1_EN;
- input S_AXI_HP2_WVALID;
- input [1:0]S_AXI_HP2_ARBURST;
- input [1:0]S_AXI_HP2_ARLOCK;
- input [2:0]S_AXI_HP2_ARSIZE;
- input [1:0]S_AXI_HP2_AWBURST;
- input [1:0]S_AXI_HP2_AWLOCK;
- input [2:0]S_AXI_HP2_AWSIZE;
- input [2:0]S_AXI_HP2_ARPROT;
- input [2:0]S_AXI_HP2_AWPROT;
- input [31:0]S_AXI_HP2_ARADDR;
- input [31:0]S_AXI_HP2_AWADDR;
- input [3:0]S_AXI_HP2_ARCACHE;
- input [3:0]S_AXI_HP2_ARLEN;
- input [3:0]S_AXI_HP2_ARQOS;
- input [3:0]S_AXI_HP2_AWCACHE;
- input [3:0]S_AXI_HP2_AWLEN;
- input [3:0]S_AXI_HP2_AWQOS;
- input [5:0]S_AXI_HP2_ARID;
- input [5:0]S_AXI_HP2_AWID;
- input [5:0]S_AXI_HP2_WID;
- input [63:0]S_AXI_HP2_WDATA;
- input [7:0]S_AXI_HP2_WSTRB;
- output S_AXI_HP3_ARESETN;
- output S_AXI_HP3_ARREADY;
- output S_AXI_HP3_AWREADY;
- output S_AXI_HP3_BVALID;
- output S_AXI_HP3_RLAST;
- output S_AXI_HP3_RVALID;
- output S_AXI_HP3_WREADY;
- output [1:0]S_AXI_HP3_BRESP;
- output [1:0]S_AXI_HP3_RRESP;
- output [5:0]S_AXI_HP3_BID;
- output [5:0]S_AXI_HP3_RID;
- output [63:0]S_AXI_HP3_RDATA;
- output [7:0]S_AXI_HP3_RCOUNT;
- output [7:0]S_AXI_HP3_WCOUNT;
- output [2:0]S_AXI_HP3_RACOUNT;
- output [5:0]S_AXI_HP3_WACOUNT;
- input S_AXI_HP3_ACLK;
- input S_AXI_HP3_ARVALID;
- input S_AXI_HP3_AWVALID;
- input S_AXI_HP3_BREADY;
- input S_AXI_HP3_RDISSUECAP1_EN;
- input S_AXI_HP3_RREADY;
- input S_AXI_HP3_WLAST;
- input S_AXI_HP3_WRISSUECAP1_EN;
- input S_AXI_HP3_WVALID;
- input [1:0]S_AXI_HP3_ARBURST;
- input [1:0]S_AXI_HP3_ARLOCK;
- input [2:0]S_AXI_HP3_ARSIZE;
- input [1:0]S_AXI_HP3_AWBURST;
- input [1:0]S_AXI_HP3_AWLOCK;
- input [2:0]S_AXI_HP3_AWSIZE;
- input [2:0]S_AXI_HP3_ARPROT;
- input [2:0]S_AXI_HP3_AWPROT;
- input [31:0]S_AXI_HP3_ARADDR;
- input [31:0]S_AXI_HP3_AWADDR;
- input [3:0]S_AXI_HP3_ARCACHE;
- input [3:0]S_AXI_HP3_ARLEN;
- input [3:0]S_AXI_HP3_ARQOS;
- input [3:0]S_AXI_HP3_AWCACHE;
- input [3:0]S_AXI_HP3_AWLEN;
- input [3:0]S_AXI_HP3_AWQOS;
- input [5:0]S_AXI_HP3_ARID;
- input [5:0]S_AXI_HP3_AWID;
- input [5:0]S_AXI_HP3_WID;
- input [63:0]S_AXI_HP3_WDATA;
- input [7:0]S_AXI_HP3_WSTRB;
- output IRQ_P2F_DMAC_ABORT;
- output IRQ_P2F_DMAC0;
- output IRQ_P2F_DMAC1;
- output IRQ_P2F_DMAC2;
- output IRQ_P2F_DMAC3;
- output IRQ_P2F_DMAC4;
- output IRQ_P2F_DMAC5;
- output IRQ_P2F_DMAC6;
- output IRQ_P2F_DMAC7;
- output IRQ_P2F_SMC;
- output IRQ_P2F_QSPI;
- output IRQ_P2F_CTI;
- output IRQ_P2F_GPIO;
- output IRQ_P2F_USB0;
- output IRQ_P2F_ENET0;
- output IRQ_P2F_ENET_WAKE0;
- output IRQ_P2F_SDIO0;
- output IRQ_P2F_I2C0;
- output IRQ_P2F_SPI0;
- output IRQ_P2F_UART0;
- output IRQ_P2F_CAN0;
- output IRQ_P2F_USB1;
- output IRQ_P2F_ENET1;
- output IRQ_P2F_ENET_WAKE1;
- output IRQ_P2F_SDIO1;
- output IRQ_P2F_I2C1;
- output IRQ_P2F_SPI1;
- output IRQ_P2F_UART1;
- output IRQ_P2F_CAN1;
- input [0:0]IRQ_F2P;
- input Core0_nFIQ;
- input Core0_nIRQ;
- input Core1_nFIQ;
- input Core1_nIRQ;
- output [1:0]DMA0_DATYPE;
- output DMA0_DAVALID;
- output DMA0_DRREADY;
- output DMA0_RSTN;
- output [1:0]DMA1_DATYPE;
- output DMA1_DAVALID;
- output DMA1_DRREADY;
- output DMA1_RSTN;
- output [1:0]DMA2_DATYPE;
- output DMA2_DAVALID;
- output DMA2_DRREADY;
- output DMA2_RSTN;
- output [1:0]DMA3_DATYPE;
- output DMA3_DAVALID;
- output DMA3_DRREADY;
- output DMA3_RSTN;
- input DMA0_ACLK;
- input DMA0_DAREADY;
- input DMA0_DRLAST;
- input DMA0_DRVALID;
- input DMA1_ACLK;
- input DMA1_DAREADY;
- input DMA1_DRLAST;
- input DMA1_DRVALID;
- input DMA2_ACLK;
- input DMA2_DAREADY;
- input DMA2_DRLAST;
- input DMA2_DRVALID;
- input DMA3_ACLK;
- input DMA3_DAREADY;
- input DMA3_DRLAST;
- input DMA3_DRVALID;
- input [1:0]DMA0_DRTYPE;
- input [1:0]DMA1_DRTYPE;
- input [1:0]DMA2_DRTYPE;
- input [1:0]DMA3_DRTYPE;
- output FCLK_CLK3;
- output FCLK_CLK2;
- output FCLK_CLK1;
- output FCLK_CLK0;
- input FCLK_CLKTRIG3_N;
- input FCLK_CLKTRIG2_N;
- input FCLK_CLKTRIG1_N;
- input FCLK_CLKTRIG0_N;
- output FCLK_RESET3_N;
- output FCLK_RESET2_N;
- output FCLK_RESET1_N;
- output FCLK_RESET0_N;
- input [31:0]FTMD_TRACEIN_DATA;
- input FTMD_TRACEIN_VALID;
- input FTMD_TRACEIN_CLK;
- input [3:0]FTMD_TRACEIN_ATID;
- input FTMT_F2P_TRIG_0;
- output FTMT_F2P_TRIGACK_0;
- input FTMT_F2P_TRIG_1;
- output FTMT_F2P_TRIGACK_1;
- input FTMT_F2P_TRIG_2;
- output FTMT_F2P_TRIGACK_2;
- input FTMT_F2P_TRIG_3;
- output FTMT_F2P_TRIGACK_3;
- input [31:0]FTMT_F2P_DEBUG;
- input FTMT_P2F_TRIGACK_0;
- output FTMT_P2F_TRIG_0;
- input FTMT_P2F_TRIGACK_1;
- output FTMT_P2F_TRIG_1;
- input FTMT_P2F_TRIGACK_2;
- output FTMT_P2F_TRIG_2;
- input FTMT_P2F_TRIGACK_3;
- output FTMT_P2F_TRIG_3;
- output [31:0]FTMT_P2F_DEBUG;
- input FPGA_IDLE_N;
- output EVENT_EVENTO;
- output [1:0]EVENT_STANDBYWFE;
- output [1:0]EVENT_STANDBYWFI;
- input EVENT_EVENTI;
- input [3:0]DDR_ARB;
- inout [53:0]MIO;
- inout DDR_CAS_n;
- inout DDR_CKE;
- inout DDR_Clk_n;
- inout DDR_Clk;
- inout DDR_CS_n;
- inout DDR_DRSTB;
- inout DDR_ODT;
- inout DDR_RAS_n;
- inout DDR_WEB;
- inout [2:0]DDR_BankAddr;
- inout [14:0]DDR_Addr;
- inout DDR_VRN;
- inout DDR_VRP;
- inout [3:0]DDR_DM;
- inout [31:0]DDR_DQ;
- inout [3:0]DDR_DQS_n;
- inout [3:0]DDR_DQS;
- inout PS_SRSTB;
- inout PS_CLK;
- inout PS_PORB;
-
- wire \<const0> ;
- wire \<const1> ;
- wire CAN0_PHY_RX;
- wire CAN0_PHY_TX;
- wire CAN1_PHY_RX;
- wire CAN1_PHY_TX;
- wire Core0_nFIQ;
- wire Core0_nIRQ;
- wire Core1_nFIQ;
- wire Core1_nIRQ;
- wire [3:0]DDR_ARB;
- wire [14:0]DDR_Addr;
- wire [2:0]DDR_BankAddr;
- wire DDR_CAS_n;
- wire DDR_CKE;
- wire DDR_CS_n;
- wire DDR_Clk;
- wire DDR_Clk_n;
- wire [3:0]DDR_DM;
- wire [31:0]DDR_DQ;
- wire [3:0]DDR_DQS;
- wire [3:0]DDR_DQS_n;
- wire DDR_DRSTB;
- wire DDR_ODT;
- wire DDR_RAS_n;
- wire DDR_VRN;
- wire DDR_VRP;
- wire DDR_WEB;
- wire DMA0_ACLK;
- wire DMA0_DAREADY;
- wire [1:0]DMA0_DATYPE;
- wire DMA0_DAVALID;
- wire DMA0_DRLAST;
- wire DMA0_DRREADY;
- wire [1:0]DMA0_DRTYPE;
- wire DMA0_DRVALID;
- wire DMA0_RSTN;
- wire DMA1_ACLK;
- wire DMA1_DAREADY;
- wire [1:0]DMA1_DATYPE;
- wire DMA1_DAVALID;
- wire DMA1_DRLAST;
- wire DMA1_DRREADY;
- wire [1:0]DMA1_DRTYPE;
- wire DMA1_DRVALID;
- wire DMA1_RSTN;
- wire DMA2_ACLK;
- wire DMA2_DAREADY;
- wire [1:0]DMA2_DATYPE;
- wire DMA2_DAVALID;
- wire DMA2_DRLAST;
- wire DMA2_DRREADY;
- wire [1:0]DMA2_DRTYPE;
- wire DMA2_DRVALID;
- wire DMA2_RSTN;
- wire DMA3_ACLK;
- wire DMA3_DAREADY;
- wire [1:0]DMA3_DATYPE;
- wire DMA3_DAVALID;
- wire DMA3_DRLAST;
- wire DMA3_DRREADY;
- wire [1:0]DMA3_DRTYPE;
- wire DMA3_DRVALID;
- wire DMA3_RSTN;
- wire ENET0_EXT_INTIN;
- wire ENET0_GMII_RX_CLK;
- wire ENET0_GMII_TX_CLK;
- wire ENET0_MDIO_I;
- wire ENET0_MDIO_MDC;
- wire ENET0_MDIO_O;
- wire ENET0_MDIO_T;
- wire ENET0_MDIO_T_n;
- wire ENET0_PTP_DELAY_REQ_RX;
- wire ENET0_PTP_DELAY_REQ_TX;
- wire ENET0_PTP_PDELAY_REQ_RX;
- wire ENET0_PTP_PDELAY_REQ_TX;
- wire ENET0_PTP_PDELAY_RESP_RX;
- wire ENET0_PTP_PDELAY_RESP_TX;
- wire ENET0_PTP_SYNC_FRAME_RX;
- wire ENET0_PTP_SYNC_FRAME_TX;
- wire ENET0_SOF_RX;
- wire ENET0_SOF_TX;
- wire ENET1_EXT_INTIN;
- wire ENET1_GMII_RX_CLK;
- wire ENET1_GMII_TX_CLK;
- wire ENET1_MDIO_I;
- wire ENET1_MDIO_MDC;
- wire ENET1_MDIO_O;
- wire ENET1_MDIO_T;
- wire ENET1_MDIO_T_n;
- wire ENET1_PTP_DELAY_REQ_RX;
- wire ENET1_PTP_DELAY_REQ_TX;
- wire ENET1_PTP_PDELAY_REQ_RX;
- wire ENET1_PTP_PDELAY_REQ_TX;
- wire ENET1_PTP_PDELAY_RESP_RX;
- wire ENET1_PTP_PDELAY_RESP_TX;
- wire ENET1_PTP_SYNC_FRAME_RX;
- wire ENET1_PTP_SYNC_FRAME_TX;
- wire ENET1_SOF_RX;
- wire ENET1_SOF_TX;
- wire EVENT_EVENTI;
- wire EVENT_EVENTO;
- wire [1:0]EVENT_STANDBYWFE;
- wire [1:0]EVENT_STANDBYWFI;
- wire FCLK_CLK0;
- wire FCLK_CLK1;
- wire FCLK_CLK2;
- wire FCLK_CLK3;
- wire [0:0]FCLK_CLK_unbuffered;
- wire FCLK_RESET0_N;
- wire FCLK_RESET1_N;
- wire FCLK_RESET2_N;
- wire FCLK_RESET3_N;
- wire FPGA_IDLE_N;
- wire FTMD_TRACEIN_CLK;
- wire [31:0]FTMT_F2P_DEBUG;
- wire FTMT_F2P_TRIGACK_0;
- wire FTMT_F2P_TRIGACK_1;
- wire FTMT_F2P_TRIGACK_2;
- wire FTMT_F2P_TRIGACK_3;
- wire FTMT_F2P_TRIG_0;
- wire FTMT_F2P_TRIG_1;
- wire FTMT_F2P_TRIG_2;
- wire FTMT_F2P_TRIG_3;
- wire [31:0]FTMT_P2F_DEBUG;
- wire FTMT_P2F_TRIGACK_0;
- wire FTMT_P2F_TRIGACK_1;
- wire FTMT_P2F_TRIGACK_2;
- wire FTMT_P2F_TRIGACK_3;
- wire FTMT_P2F_TRIG_0;
- wire FTMT_P2F_TRIG_1;
- wire FTMT_P2F_TRIG_2;
- wire FTMT_P2F_TRIG_3;
- wire [63:0]GPIO_I;
- wire [63:0]GPIO_O;
- wire [63:0]GPIO_T;
- wire I2C0_SCL_I;
- wire I2C0_SCL_O;
- wire I2C0_SCL_T;
- wire I2C0_SCL_T_n;
- wire I2C0_SDA_I;
- wire I2C0_SDA_O;
- wire I2C0_SDA_T;
- wire I2C0_SDA_T_n;
- wire I2C1_SCL_I;
- wire I2C1_SCL_O;
- wire I2C1_SCL_T;
- wire I2C1_SCL_T_n;
- wire I2C1_SDA_I;
- wire I2C1_SDA_O;
- wire I2C1_SDA_T;
- wire I2C1_SDA_T_n;
- wire [0:0]IRQ_F2P;
- wire IRQ_P2F_CAN0;
- wire IRQ_P2F_CAN1;
- wire IRQ_P2F_CTI;
- wire IRQ_P2F_DMAC0;
- wire IRQ_P2F_DMAC1;
- wire IRQ_P2F_DMAC2;
- wire IRQ_P2F_DMAC3;
- wire IRQ_P2F_DMAC4;
- wire IRQ_P2F_DMAC5;
- wire IRQ_P2F_DMAC6;
- wire IRQ_P2F_DMAC7;
- wire IRQ_P2F_DMAC_ABORT;
- wire IRQ_P2F_ENET0;
- wire IRQ_P2F_ENET1;
- wire IRQ_P2F_ENET_WAKE0;
- wire IRQ_P2F_ENET_WAKE1;
- wire IRQ_P2F_GPIO;
- wire IRQ_P2F_I2C0;
- wire IRQ_P2F_I2C1;
- wire IRQ_P2F_QSPI;
- wire IRQ_P2F_SDIO0;
- wire IRQ_P2F_SDIO1;
- wire IRQ_P2F_SMC;
- wire IRQ_P2F_SPI0;
- wire IRQ_P2F_SPI1;
- wire IRQ_P2F_UART0;
- wire IRQ_P2F_UART1;
- wire IRQ_P2F_USB0;
- wire IRQ_P2F_USB1;
- wire [53:0]MIO;
- wire M_AXI_GP0_ACLK;
- wire [31:0]M_AXI_GP0_ARADDR;
- wire [1:0]M_AXI_GP0_ARBURST;
- wire [3:0]\^M_AXI_GP0_ARCACHE ;
- wire M_AXI_GP0_ARESETN;
- wire [11:0]M_AXI_GP0_ARID;
- wire [3:0]M_AXI_GP0_ARLEN;
- wire [1:0]M_AXI_GP0_ARLOCK;
- wire [2:0]M_AXI_GP0_ARPROT;
- wire [3:0]M_AXI_GP0_ARQOS;
- wire M_AXI_GP0_ARREADY;
- wire [1:0]\^M_AXI_GP0_ARSIZE ;
- wire M_AXI_GP0_ARVALID;
- wire [31:0]M_AXI_GP0_AWADDR;
- wire [1:0]M_AXI_GP0_AWBURST;
- wire [3:0]\^M_AXI_GP0_AWCACHE ;
- wire [11:0]M_AXI_GP0_AWID;
- wire [3:0]M_AXI_GP0_AWLEN;
- wire [1:0]M_AXI_GP0_AWLOCK;
- wire [2:0]M_AXI_GP0_AWPROT;
- wire [3:0]M_AXI_GP0_AWQOS;
- wire M_AXI_GP0_AWREADY;
- wire [1:0]\^M_AXI_GP0_AWSIZE ;
- wire M_AXI_GP0_AWVALID;
- wire [11:0]M_AXI_GP0_BID;
- wire M_AXI_GP0_BREADY;
- wire [1:0]M_AXI_GP0_BRESP;
- wire M_AXI_GP0_BVALID;
- wire [31:0]M_AXI_GP0_RDATA;
- wire [11:0]M_AXI_GP0_RID;
- wire M_AXI_GP0_RLAST;
- wire M_AXI_GP0_RREADY;
- wire [1:0]M_AXI_GP0_RRESP;
- wire M_AXI_GP0_RVALID;
- wire [31:0]M_AXI_GP0_WDATA;
- wire [11:0]M_AXI_GP0_WID;
- wire M_AXI_GP0_WLAST;
- wire M_AXI_GP0_WREADY;
- wire [3:0]M_AXI_GP0_WSTRB;
- wire M_AXI_GP0_WVALID;
- wire M_AXI_GP1_ACLK;
- wire [31:0]M_AXI_GP1_ARADDR;
- wire [1:0]M_AXI_GP1_ARBURST;
- wire [3:0]\^M_AXI_GP1_ARCACHE ;
- wire M_AXI_GP1_ARESETN;
- wire [11:0]M_AXI_GP1_ARID;
- wire [3:0]M_AXI_GP1_ARLEN;
- wire [1:0]M_AXI_GP1_ARLOCK;
- wire [2:0]M_AXI_GP1_ARPROT;
- wire [3:0]M_AXI_GP1_ARQOS;
- wire M_AXI_GP1_ARREADY;
- wire [1:0]\^M_AXI_GP1_ARSIZE ;
- wire M_AXI_GP1_ARVALID;
- wire [31:0]M_AXI_GP1_AWADDR;
- wire [1:0]M_AXI_GP1_AWBURST;
- wire [3:0]\^M_AXI_GP1_AWCACHE ;
- wire [11:0]M_AXI_GP1_AWID;
- wire [3:0]M_AXI_GP1_AWLEN;
- wire [1:0]M_AXI_GP1_AWLOCK;
- wire [2:0]M_AXI_GP1_AWPROT;
- wire [3:0]M_AXI_GP1_AWQOS;
- wire M_AXI_GP1_AWREADY;
- wire [1:0]\^M_AXI_GP1_AWSIZE ;
- wire M_AXI_GP1_AWVALID;
- wire [11:0]M_AXI_GP1_BID;
- wire M_AXI_GP1_BREADY;
- wire [1:0]M_AXI_GP1_BRESP;
- wire M_AXI_GP1_BVALID;
- wire [31:0]M_AXI_GP1_RDATA;
- wire [11:0]M_AXI_GP1_RID;
- wire M_AXI_GP1_RLAST;
- wire M_AXI_GP1_RREADY;
- wire [1:0]M_AXI_GP1_RRESP;
- wire M_AXI_GP1_RVALID;
- wire [31:0]M_AXI_GP1_WDATA;
- wire [11:0]M_AXI_GP1_WID;
- wire M_AXI_GP1_WLAST;
- wire M_AXI_GP1_WREADY;
- wire [3:0]M_AXI_GP1_WSTRB;
- wire M_AXI_GP1_WVALID;
- wire PJTAG_TCK;
- wire PJTAG_TDI;
- wire PJTAG_TMS;
- wire PS_CLK;
- wire PS_PORB;
- wire PS_SRSTB;
- wire SDIO0_BUSPOW;
- wire [2:0]SDIO0_BUSVOLT;
- wire SDIO0_CDN;
- wire SDIO0_CLK;
- wire SDIO0_CLK_FB;
- wire SDIO0_CMD_I;
- wire SDIO0_CMD_O;
- wire SDIO0_CMD_T;
- wire SDIO0_CMD_T_n;
- wire [3:0]SDIO0_DATA_I;
- wire [3:0]SDIO0_DATA_O;
- wire [3:0]SDIO0_DATA_T;
- wire [3:0]SDIO0_DATA_T_n;
- wire SDIO0_LED;
- wire SDIO0_WP;
- wire SDIO1_BUSPOW;
- wire [2:0]SDIO1_BUSVOLT;
- wire SDIO1_CDN;
- wire SDIO1_CLK;
- wire SDIO1_CLK_FB;
- wire SDIO1_CMD_I;
- wire SDIO1_CMD_O;
- wire SDIO1_CMD_T;
- wire SDIO1_CMD_T_n;
- wire [3:0]SDIO1_DATA_I;
- wire [3:0]SDIO1_DATA_O;
- wire [3:0]SDIO1_DATA_T;
- wire [3:0]SDIO1_DATA_T_n;
- wire SDIO1_LED;
- wire SDIO1_WP;
- wire SPI0_MISO_I;
- wire SPI0_MISO_O;
- wire SPI0_MISO_T;
- wire SPI0_MISO_T_n;
- wire SPI0_MOSI_I;
- wire SPI0_MOSI_O;
- wire SPI0_MOSI_T;
- wire SPI0_MOSI_T_n;
- wire SPI0_SCLK_I;
- wire SPI0_SCLK_O;
- wire SPI0_SCLK_T;
- wire SPI0_SCLK_T_n;
- wire SPI0_SS1_O;
- wire SPI0_SS2_O;
- wire SPI0_SS_I;
- wire SPI0_SS_O;
- wire SPI0_SS_T;
- wire SPI0_SS_T_n;
- wire SPI1_MISO_I;
- wire SPI1_MISO_O;
- wire SPI1_MISO_T;
- wire SPI1_MISO_T_n;
- wire SPI1_MOSI_I;
- wire SPI1_MOSI_O;
- wire SPI1_MOSI_T;
- wire SPI1_MOSI_T_n;
- wire SPI1_SCLK_I;
- wire SPI1_SCLK_O;
- wire SPI1_SCLK_T;
- wire SPI1_SCLK_T_n;
- wire SPI1_SS1_O;
- wire SPI1_SS2_O;
- wire SPI1_SS_I;
- wire SPI1_SS_O;
- wire SPI1_SS_T;
- wire SPI1_SS_T_n;
- wire SRAM_INTIN;
- wire S_AXI_ACP_ACLK;
- wire [31:0]S_AXI_ACP_ARADDR;
- wire [1:0]S_AXI_ACP_ARBURST;
- wire [3:0]S_AXI_ACP_ARCACHE;
- wire S_AXI_ACP_ARESETN;
- wire [2:0]S_AXI_ACP_ARID;
- wire [3:0]S_AXI_ACP_ARLEN;
- wire [1:0]S_AXI_ACP_ARLOCK;
- wire [2:0]S_AXI_ACP_ARPROT;
- wire [3:0]S_AXI_ACP_ARQOS;
- wire S_AXI_ACP_ARREADY;
- wire [2:0]S_AXI_ACP_ARSIZE;
- wire [4:0]S_AXI_ACP_ARUSER;
- wire S_AXI_ACP_ARVALID;
- wire [31:0]S_AXI_ACP_AWADDR;
- wire [1:0]S_AXI_ACP_AWBURST;
- wire [3:0]S_AXI_ACP_AWCACHE;
- wire [2:0]S_AXI_ACP_AWID;
- wire [3:0]S_AXI_ACP_AWLEN;
- wire [1:0]S_AXI_ACP_AWLOCK;
- wire [2:0]S_AXI_ACP_AWPROT;
- wire [3:0]S_AXI_ACP_AWQOS;
- wire S_AXI_ACP_AWREADY;
- wire [2:0]S_AXI_ACP_AWSIZE;
- wire [4:0]S_AXI_ACP_AWUSER;
- wire S_AXI_ACP_AWVALID;
- wire [2:0]S_AXI_ACP_BID;
- wire S_AXI_ACP_BREADY;
- wire [1:0]S_AXI_ACP_BRESP;
- wire S_AXI_ACP_BVALID;
- wire [63:0]S_AXI_ACP_RDATA;
- wire [2:0]S_AXI_ACP_RID;
- wire S_AXI_ACP_RLAST;
- wire S_AXI_ACP_RREADY;
- wire [1:0]S_AXI_ACP_RRESP;
- wire S_AXI_ACP_RVALID;
- wire [63:0]S_AXI_ACP_WDATA;
- wire [2:0]S_AXI_ACP_WID;
- wire S_AXI_ACP_WLAST;
- wire S_AXI_ACP_WREADY;
- wire [7:0]S_AXI_ACP_WSTRB;
- wire S_AXI_ACP_WVALID;
- wire S_AXI_GP0_ACLK;
- wire [31:0]S_AXI_GP0_ARADDR;
- wire [1:0]S_AXI_GP0_ARBURST;
- wire [3:0]S_AXI_GP0_ARCACHE;
- wire S_AXI_GP0_ARESETN;
- wire [5:0]S_AXI_GP0_ARID;
- wire [3:0]S_AXI_GP0_ARLEN;
- wire [1:0]S_AXI_GP0_ARLOCK;
- wire [2:0]S_AXI_GP0_ARPROT;
- wire [3:0]S_AXI_GP0_ARQOS;
- wire S_AXI_GP0_ARREADY;
- wire [2:0]S_AXI_GP0_ARSIZE;
- wire S_AXI_GP0_ARVALID;
- wire [31:0]S_AXI_GP0_AWADDR;
- wire [1:0]S_AXI_GP0_AWBURST;
- wire [3:0]S_AXI_GP0_AWCACHE;
- wire [5:0]S_AXI_GP0_AWID;
- wire [3:0]S_AXI_GP0_AWLEN;
- wire [1:0]S_AXI_GP0_AWLOCK;
- wire [2:0]S_AXI_GP0_AWPROT;
- wire [3:0]S_AXI_GP0_AWQOS;
- wire S_AXI_GP0_AWREADY;
- wire [2:0]S_AXI_GP0_AWSIZE;
- wire S_AXI_GP0_AWVALID;
- wire [5:0]S_AXI_GP0_BID;
- wire S_AXI_GP0_BREADY;
- wire [1:0]S_AXI_GP0_BRESP;
- wire S_AXI_GP0_BVALID;
- wire [31:0]S_AXI_GP0_RDATA;
- wire [5:0]S_AXI_GP0_RID;
- wire S_AXI_GP0_RLAST;
- wire S_AXI_GP0_RREADY;
- wire [1:0]S_AXI_GP0_RRESP;
- wire S_AXI_GP0_RVALID;
- wire [31:0]S_AXI_GP0_WDATA;
- wire [5:0]S_AXI_GP0_WID;
- wire S_AXI_GP0_WLAST;
- wire S_AXI_GP0_WREADY;
- wire [3:0]S_AXI_GP0_WSTRB;
- wire S_AXI_GP0_WVALID;
- wire S_AXI_GP1_ACLK;
- wire [31:0]S_AXI_GP1_ARADDR;
- wire [1:0]S_AXI_GP1_ARBURST;
- wire [3:0]S_AXI_GP1_ARCACHE;
- wire S_AXI_GP1_ARESETN;
- wire [5:0]S_AXI_GP1_ARID;
- wire [3:0]S_AXI_GP1_ARLEN;
- wire [1:0]S_AXI_GP1_ARLOCK;
- wire [2:0]S_AXI_GP1_ARPROT;
- wire [3:0]S_AXI_GP1_ARQOS;
- wire S_AXI_GP1_ARREADY;
- wire [2:0]S_AXI_GP1_ARSIZE;
- wire S_AXI_GP1_ARVALID;
- wire [31:0]S_AXI_GP1_AWADDR;
- wire [1:0]S_AXI_GP1_AWBURST;
- wire [3:0]S_AXI_GP1_AWCACHE;
- wire [5:0]S_AXI_GP1_AWID;
- wire [3:0]S_AXI_GP1_AWLEN;
- wire [1:0]S_AXI_GP1_AWLOCK;
- wire [2:0]S_AXI_GP1_AWPROT;
- wire [3:0]S_AXI_GP1_AWQOS;
- wire S_AXI_GP1_AWREADY;
- wire [2:0]S_AXI_GP1_AWSIZE;
- wire S_AXI_GP1_AWVALID;
- wire [5:0]S_AXI_GP1_BID;
- wire S_AXI_GP1_BREADY;
- wire [1:0]S_AXI_GP1_BRESP;
- wire S_AXI_GP1_BVALID;
- wire [31:0]S_AXI_GP1_RDATA;
- wire [5:0]S_AXI_GP1_RID;
- wire S_AXI_GP1_RLAST;
- wire S_AXI_GP1_RREADY;
- wire [1:0]S_AXI_GP1_RRESP;
- wire S_AXI_GP1_RVALID;
- wire [31:0]S_AXI_GP1_WDATA;
- wire [5:0]S_AXI_GP1_WID;
- wire S_AXI_GP1_WLAST;
- wire S_AXI_GP1_WREADY;
- wire [3:0]S_AXI_GP1_WSTRB;
- wire S_AXI_GP1_WVALID;
- wire S_AXI_HP0_ACLK;
- wire [31:0]S_AXI_HP0_ARADDR;
- wire [1:0]S_AXI_HP0_ARBURST;
- wire [3:0]S_AXI_HP0_ARCACHE;
- wire S_AXI_HP0_ARESETN;
- wire [5:0]S_AXI_HP0_ARID;
- wire [3:0]S_AXI_HP0_ARLEN;
- wire [1:0]S_AXI_HP0_ARLOCK;
- wire [2:0]S_AXI_HP0_ARPROT;
- wire [3:0]S_AXI_HP0_ARQOS;
- wire S_AXI_HP0_ARREADY;
- wire [2:0]S_AXI_HP0_ARSIZE;
- wire S_AXI_HP0_ARVALID;
- wire [31:0]S_AXI_HP0_AWADDR;
- wire [1:0]S_AXI_HP0_AWBURST;
- wire [3:0]S_AXI_HP0_AWCACHE;
- wire [5:0]S_AXI_HP0_AWID;
- wire [3:0]S_AXI_HP0_AWLEN;
- wire [1:0]S_AXI_HP0_AWLOCK;
- wire [2:0]S_AXI_HP0_AWPROT;
- wire [3:0]S_AXI_HP0_AWQOS;
- wire S_AXI_HP0_AWREADY;
- wire [2:0]S_AXI_HP0_AWSIZE;
- wire S_AXI_HP0_AWVALID;
- wire [5:0]S_AXI_HP0_BID;
- wire S_AXI_HP0_BREADY;
- wire [1:0]S_AXI_HP0_BRESP;
- wire S_AXI_HP0_BVALID;
- wire [2:0]S_AXI_HP0_RACOUNT;
- wire [7:0]S_AXI_HP0_RCOUNT;
- wire [63:0]S_AXI_HP0_RDATA;
- wire S_AXI_HP0_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP0_RID;
- wire S_AXI_HP0_RLAST;
- wire S_AXI_HP0_RREADY;
- wire [1:0]S_AXI_HP0_RRESP;
- wire S_AXI_HP0_RVALID;
- wire [5:0]S_AXI_HP0_WACOUNT;
- wire [7:0]S_AXI_HP0_WCOUNT;
- wire [63:0]S_AXI_HP0_WDATA;
- wire [5:0]S_AXI_HP0_WID;
- wire S_AXI_HP0_WLAST;
- wire S_AXI_HP0_WREADY;
- wire S_AXI_HP0_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP0_WSTRB;
- wire S_AXI_HP0_WVALID;
- wire S_AXI_HP1_ACLK;
- wire [31:0]S_AXI_HP1_ARADDR;
- wire [1:0]S_AXI_HP1_ARBURST;
- wire [3:0]S_AXI_HP1_ARCACHE;
- wire S_AXI_HP1_ARESETN;
- wire [5:0]S_AXI_HP1_ARID;
- wire [3:0]S_AXI_HP1_ARLEN;
- wire [1:0]S_AXI_HP1_ARLOCK;
- wire [2:0]S_AXI_HP1_ARPROT;
- wire [3:0]S_AXI_HP1_ARQOS;
- wire S_AXI_HP1_ARREADY;
- wire [2:0]S_AXI_HP1_ARSIZE;
- wire S_AXI_HP1_ARVALID;
- wire [31:0]S_AXI_HP1_AWADDR;
- wire [1:0]S_AXI_HP1_AWBURST;
- wire [3:0]S_AXI_HP1_AWCACHE;
- wire [5:0]S_AXI_HP1_AWID;
- wire [3:0]S_AXI_HP1_AWLEN;
- wire [1:0]S_AXI_HP1_AWLOCK;
- wire [2:0]S_AXI_HP1_AWPROT;
- wire [3:0]S_AXI_HP1_AWQOS;
- wire S_AXI_HP1_AWREADY;
- wire [2:0]S_AXI_HP1_AWSIZE;
- wire S_AXI_HP1_AWVALID;
- wire [5:0]S_AXI_HP1_BID;
- wire S_AXI_HP1_BREADY;
- wire [1:0]S_AXI_HP1_BRESP;
- wire S_AXI_HP1_BVALID;
- wire [2:0]S_AXI_HP1_RACOUNT;
- wire [7:0]S_AXI_HP1_RCOUNT;
- wire [63:0]S_AXI_HP1_RDATA;
- wire S_AXI_HP1_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP1_RID;
- wire S_AXI_HP1_RLAST;
- wire S_AXI_HP1_RREADY;
- wire [1:0]S_AXI_HP1_RRESP;
- wire S_AXI_HP1_RVALID;
- wire [5:0]S_AXI_HP1_WACOUNT;
- wire [7:0]S_AXI_HP1_WCOUNT;
- wire [63:0]S_AXI_HP1_WDATA;
- wire [5:0]S_AXI_HP1_WID;
- wire S_AXI_HP1_WLAST;
- wire S_AXI_HP1_WREADY;
- wire S_AXI_HP1_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP1_WSTRB;
- wire S_AXI_HP1_WVALID;
- wire S_AXI_HP2_ACLK;
- wire [31:0]S_AXI_HP2_ARADDR;
- wire [1:0]S_AXI_HP2_ARBURST;
- wire [3:0]S_AXI_HP2_ARCACHE;
- wire S_AXI_HP2_ARESETN;
- wire [5:0]S_AXI_HP2_ARID;
- wire [3:0]S_AXI_HP2_ARLEN;
- wire [1:0]S_AXI_HP2_ARLOCK;
- wire [2:0]S_AXI_HP2_ARPROT;
- wire [3:0]S_AXI_HP2_ARQOS;
- wire S_AXI_HP2_ARREADY;
- wire [2:0]S_AXI_HP2_ARSIZE;
- wire S_AXI_HP2_ARVALID;
- wire [31:0]S_AXI_HP2_AWADDR;
- wire [1:0]S_AXI_HP2_AWBURST;
- wire [3:0]S_AXI_HP2_AWCACHE;
- wire [5:0]S_AXI_HP2_AWID;
- wire [3:0]S_AXI_HP2_AWLEN;
- wire [1:0]S_AXI_HP2_AWLOCK;
- wire [2:0]S_AXI_HP2_AWPROT;
- wire [3:0]S_AXI_HP2_AWQOS;
- wire S_AXI_HP2_AWREADY;
- wire [2:0]S_AXI_HP2_AWSIZE;
- wire S_AXI_HP2_AWVALID;
- wire [5:0]S_AXI_HP2_BID;
- wire S_AXI_HP2_BREADY;
- wire [1:0]S_AXI_HP2_BRESP;
- wire S_AXI_HP2_BVALID;
- wire [2:0]S_AXI_HP2_RACOUNT;
- wire [7:0]S_AXI_HP2_RCOUNT;
- wire [63:0]S_AXI_HP2_RDATA;
- wire S_AXI_HP2_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP2_RID;
- wire S_AXI_HP2_RLAST;
- wire S_AXI_HP2_RREADY;
- wire [1:0]S_AXI_HP2_RRESP;
- wire S_AXI_HP2_RVALID;
- wire [5:0]S_AXI_HP2_WACOUNT;
- wire [7:0]S_AXI_HP2_WCOUNT;
- wire [63:0]S_AXI_HP2_WDATA;
- wire [5:0]S_AXI_HP2_WID;
- wire S_AXI_HP2_WLAST;
- wire S_AXI_HP2_WREADY;
- wire S_AXI_HP2_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP2_WSTRB;
- wire S_AXI_HP2_WVALID;
- wire S_AXI_HP3_ACLK;
- wire [31:0]S_AXI_HP3_ARADDR;
- wire [1:0]S_AXI_HP3_ARBURST;
- wire [3:0]S_AXI_HP3_ARCACHE;
- wire S_AXI_HP3_ARESETN;
- wire [5:0]S_AXI_HP3_ARID;
- wire [3:0]S_AXI_HP3_ARLEN;
- wire [1:0]S_AXI_HP3_ARLOCK;
- wire [2:0]S_AXI_HP3_ARPROT;
- wire [3:0]S_AXI_HP3_ARQOS;
- wire S_AXI_HP3_ARREADY;
- wire [2:0]S_AXI_HP3_ARSIZE;
- wire S_AXI_HP3_ARVALID;
- wire [31:0]S_AXI_HP3_AWADDR;
- wire [1:0]S_AXI_HP3_AWBURST;
- wire [3:0]S_AXI_HP3_AWCACHE;
- wire [5:0]S_AXI_HP3_AWID;
- wire [3:0]S_AXI_HP3_AWLEN;
- wire [1:0]S_AXI_HP3_AWLOCK;
- wire [2:0]S_AXI_HP3_AWPROT;
- wire [3:0]S_AXI_HP3_AWQOS;
- wire S_AXI_HP3_AWREADY;
- wire [2:0]S_AXI_HP3_AWSIZE;
- wire S_AXI_HP3_AWVALID;
- wire [5:0]S_AXI_HP3_BID;
- wire S_AXI_HP3_BREADY;
- wire [1:0]S_AXI_HP3_BRESP;
- wire S_AXI_HP3_BVALID;
- wire [2:0]S_AXI_HP3_RACOUNT;
- wire [7:0]S_AXI_HP3_RCOUNT;
- wire [63:0]S_AXI_HP3_RDATA;
- wire S_AXI_HP3_RDISSUECAP1_EN;
- wire [5:0]S_AXI_HP3_RID;
- wire S_AXI_HP3_RLAST;
- wire S_AXI_HP3_RREADY;
- wire [1:0]S_AXI_HP3_RRESP;
- wire S_AXI_HP3_RVALID;
- wire [5:0]S_AXI_HP3_WACOUNT;
- wire [7:0]S_AXI_HP3_WCOUNT;
- wire [63:0]S_AXI_HP3_WDATA;
- wire [5:0]S_AXI_HP3_WID;
- wire S_AXI_HP3_WLAST;
- wire S_AXI_HP3_WREADY;
- wire S_AXI_HP3_WRISSUECAP1_EN;
- wire [7:0]S_AXI_HP3_WSTRB;
- wire S_AXI_HP3_WVALID;
- wire TRACE_CLK;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
- (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
- (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
- wire TTC0_CLK0_IN;
- wire TTC0_CLK1_IN;
- wire TTC0_CLK2_IN;
- wire TTC0_WAVE0_OUT;
- wire TTC0_WAVE1_OUT;
- wire TTC0_WAVE2_OUT;
- wire TTC1_CLK0_IN;
- wire TTC1_CLK1_IN;
- wire TTC1_CLK2_IN;
- wire TTC1_WAVE0_OUT;
- wire TTC1_WAVE1_OUT;
- wire TTC1_WAVE2_OUT;
- wire UART0_CTSN;
- wire UART0_DCDN;
- wire UART0_DSRN;
- wire UART0_DTRN;
- wire UART0_RIN;
- wire UART0_RTSN;
- wire UART0_RX;
- wire UART0_TX;
- wire UART1_CTSN;
- wire UART1_DCDN;
- wire UART1_DSRN;
- wire UART1_DTRN;
- wire UART1_RIN;
- wire UART1_RTSN;
- wire UART1_RX;
- wire UART1_TX;
- wire [1:0]USB0_PORT_INDCTL;
- wire USB0_VBUS_PWRFAULT;
- wire USB0_VBUS_PWRSELECT;
- wire [1:0]USB1_PORT_INDCTL;
- wire USB1_VBUS_PWRFAULT;
- wire USB1_VBUS_PWRSELECT;
- wire WDT_CLK_IN;
- wire WDT_RST_OUT;
- wire [14:0]buffered_DDR_Addr;
- wire [2:0]buffered_DDR_BankAddr;
- wire buffered_DDR_CAS_n;
- wire buffered_DDR_CKE;
- wire buffered_DDR_CS_n;
- wire buffered_DDR_Clk;
- wire buffered_DDR_Clk_n;
- wire [3:0]buffered_DDR_DM;
- wire [31:0]buffered_DDR_DQ;
- wire [3:0]buffered_DDR_DQS;
- wire [3:0]buffered_DDR_DQS_n;
- wire buffered_DDR_DRSTB;
- wire buffered_DDR_ODT;
- wire buffered_DDR_RAS_n;
- wire buffered_DDR_VRN;
- wire buffered_DDR_VRP;
- wire buffered_DDR_WEB;
- wire [53:0]buffered_MIO;
- wire buffered_PS_CLK;
- wire buffered_PS_PORB;
- wire buffered_PS_SRSTB;
- wire [63:0]gpio_out_t_n;
- wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
- wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
- wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
- wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
- wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
- wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
- wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
- wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
- wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
- wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
- wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
-
- assign ENET0_GMII_TXD[7] = \<const0> ;
- assign ENET0_GMII_TXD[6] = \<const0> ;
- assign ENET0_GMII_TXD[5] = \<const0> ;
- assign ENET0_GMII_TXD[4] = \<const0> ;
- assign ENET0_GMII_TXD[3] = \<const0> ;
- assign ENET0_GMII_TXD[2] = \<const0> ;
- assign ENET0_GMII_TXD[1] = \<const0> ;
- assign ENET0_GMII_TXD[0] = \<const0> ;
- assign ENET0_GMII_TX_EN = \<const0> ;
- assign ENET0_GMII_TX_ER = \<const0> ;
- assign ENET1_GMII_TXD[7] = \<const0> ;
- assign ENET1_GMII_TXD[6] = \<const0> ;
- assign ENET1_GMII_TXD[5] = \<const0> ;
- assign ENET1_GMII_TXD[4] = \<const0> ;
- assign ENET1_GMII_TXD[3] = \<const0> ;
- assign ENET1_GMII_TXD[2] = \<const0> ;
- assign ENET1_GMII_TXD[1] = \<const0> ;
- assign ENET1_GMII_TXD[0] = \<const0> ;
- assign ENET1_GMII_TX_EN = \<const0> ;
- assign ENET1_GMII_TX_ER = \<const0> ;
- assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
- assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
- assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
- assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
- assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
- assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
- assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
- assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
- assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
- assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
- assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
- assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
- assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
- assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
- assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
- assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
- assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
- assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
- assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
- assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
- assign PJTAG_TDO = \<const0> ;
- assign TRACE_CLK_OUT = \<const0> ;
- assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
- assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_CAS_n_BIBUF
- (.IO(buffered_DDR_CAS_n),
- .PAD(DDR_CAS_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_CKE_BIBUF
- (.IO(buffered_DDR_CKE),
- .PAD(DDR_CKE));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_CS_n_BIBUF
- (.IO(buffered_DDR_CS_n),
- .PAD(DDR_CS_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_Clk_BIBUF
- (.IO(buffered_DDR_Clk),
- .PAD(DDR_Clk));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_Clk_n_BIBUF
- (.IO(buffered_DDR_Clk_n),
- .PAD(DDR_Clk_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_DRSTB_BIBUF
- (.IO(buffered_DDR_DRSTB),
- .PAD(DDR_DRSTB));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_ODT_BIBUF
- (.IO(buffered_DDR_ODT),
- .PAD(DDR_ODT));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_RAS_n_BIBUF
- (.IO(buffered_DDR_RAS_n),
- .PAD(DDR_RAS_n));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_VRN_BIBUF
- (.IO(buffered_DDR_VRN),
- .PAD(DDR_VRN));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_VRP_BIBUF
- (.IO(buffered_DDR_VRP),
- .PAD(DDR_VRP));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF DDR_WEB_BIBUF
- (.IO(buffered_DDR_WEB),
- .PAD(DDR_WEB));
- LUT1 #(
- .INIT(2'h1))
- ENET0_MDIO_T_INST_0
- (.I0(ENET0_MDIO_T_n),
- .O(ENET0_MDIO_T));
- LUT1 #(
- .INIT(2'h1))
- ENET1_MDIO_T_INST_0
- (.I0(ENET1_MDIO_T_n),
- .O(ENET1_MDIO_T));
- GND GND
- (.G(\<const0> ));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[0]_INST_0
- (.I0(gpio_out_t_n[0]),
- .O(GPIO_T[0]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[10]_INST_0
- (.I0(gpio_out_t_n[10]),
- .O(GPIO_T[10]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[11]_INST_0
- (.I0(gpio_out_t_n[11]),
- .O(GPIO_T[11]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[12]_INST_0
- (.I0(gpio_out_t_n[12]),
- .O(GPIO_T[12]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[13]_INST_0
- (.I0(gpio_out_t_n[13]),
- .O(GPIO_T[13]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[14]_INST_0
- (.I0(gpio_out_t_n[14]),
- .O(GPIO_T[14]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[15]_INST_0
- (.I0(gpio_out_t_n[15]),
- .O(GPIO_T[15]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[16]_INST_0
- (.I0(gpio_out_t_n[16]),
- .O(GPIO_T[16]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[17]_INST_0
- (.I0(gpio_out_t_n[17]),
- .O(GPIO_T[17]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[18]_INST_0
- (.I0(gpio_out_t_n[18]),
- .O(GPIO_T[18]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[19]_INST_0
- (.I0(gpio_out_t_n[19]),
- .O(GPIO_T[19]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[1]_INST_0
- (.I0(gpio_out_t_n[1]),
- .O(GPIO_T[1]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[20]_INST_0
- (.I0(gpio_out_t_n[20]),
- .O(GPIO_T[20]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[21]_INST_0
- (.I0(gpio_out_t_n[21]),
- .O(GPIO_T[21]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[22]_INST_0
- (.I0(gpio_out_t_n[22]),
- .O(GPIO_T[22]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[23]_INST_0
- (.I0(gpio_out_t_n[23]),
- .O(GPIO_T[23]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[24]_INST_0
- (.I0(gpio_out_t_n[24]),
- .O(GPIO_T[24]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[25]_INST_0
- (.I0(gpio_out_t_n[25]),
- .O(GPIO_T[25]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[26]_INST_0
- (.I0(gpio_out_t_n[26]),
- .O(GPIO_T[26]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[27]_INST_0
- (.I0(gpio_out_t_n[27]),
- .O(GPIO_T[27]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[28]_INST_0
- (.I0(gpio_out_t_n[28]),
- .O(GPIO_T[28]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[29]_INST_0
- (.I0(gpio_out_t_n[29]),
- .O(GPIO_T[29]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[2]_INST_0
- (.I0(gpio_out_t_n[2]),
- .O(GPIO_T[2]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[30]_INST_0
- (.I0(gpio_out_t_n[30]),
- .O(GPIO_T[30]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[31]_INST_0
- (.I0(gpio_out_t_n[31]),
- .O(GPIO_T[31]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[32]_INST_0
- (.I0(gpio_out_t_n[32]),
- .O(GPIO_T[32]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[33]_INST_0
- (.I0(gpio_out_t_n[33]),
- .O(GPIO_T[33]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[34]_INST_0
- (.I0(gpio_out_t_n[34]),
- .O(GPIO_T[34]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[35]_INST_0
- (.I0(gpio_out_t_n[35]),
- .O(GPIO_T[35]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[36]_INST_0
- (.I0(gpio_out_t_n[36]),
- .O(GPIO_T[36]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[37]_INST_0
- (.I0(gpio_out_t_n[37]),
- .O(GPIO_T[37]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[38]_INST_0
- (.I0(gpio_out_t_n[38]),
- .O(GPIO_T[38]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[39]_INST_0
- (.I0(gpio_out_t_n[39]),
- .O(GPIO_T[39]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[3]_INST_0
- (.I0(gpio_out_t_n[3]),
- .O(GPIO_T[3]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[40]_INST_0
- (.I0(gpio_out_t_n[40]),
- .O(GPIO_T[40]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[41]_INST_0
- (.I0(gpio_out_t_n[41]),
- .O(GPIO_T[41]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[42]_INST_0
- (.I0(gpio_out_t_n[42]),
- .O(GPIO_T[42]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[43]_INST_0
- (.I0(gpio_out_t_n[43]),
- .O(GPIO_T[43]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[44]_INST_0
- (.I0(gpio_out_t_n[44]),
- .O(GPIO_T[44]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[45]_INST_0
- (.I0(gpio_out_t_n[45]),
- .O(GPIO_T[45]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[46]_INST_0
- (.I0(gpio_out_t_n[46]),
- .O(GPIO_T[46]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[47]_INST_0
- (.I0(gpio_out_t_n[47]),
- .O(GPIO_T[47]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[48]_INST_0
- (.I0(gpio_out_t_n[48]),
- .O(GPIO_T[48]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[49]_INST_0
- (.I0(gpio_out_t_n[49]),
- .O(GPIO_T[49]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[4]_INST_0
- (.I0(gpio_out_t_n[4]),
- .O(GPIO_T[4]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[50]_INST_0
- (.I0(gpio_out_t_n[50]),
- .O(GPIO_T[50]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[51]_INST_0
- (.I0(gpio_out_t_n[51]),
- .O(GPIO_T[51]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[52]_INST_0
- (.I0(gpio_out_t_n[52]),
- .O(GPIO_T[52]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[53]_INST_0
- (.I0(gpio_out_t_n[53]),
- .O(GPIO_T[53]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[54]_INST_0
- (.I0(gpio_out_t_n[54]),
- .O(GPIO_T[54]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[55]_INST_0
- (.I0(gpio_out_t_n[55]),
- .O(GPIO_T[55]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[56]_INST_0
- (.I0(gpio_out_t_n[56]),
- .O(GPIO_T[56]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[57]_INST_0
- (.I0(gpio_out_t_n[57]),
- .O(GPIO_T[57]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[58]_INST_0
- (.I0(gpio_out_t_n[58]),
- .O(GPIO_T[58]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[59]_INST_0
- (.I0(gpio_out_t_n[59]),
- .O(GPIO_T[59]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[5]_INST_0
- (.I0(gpio_out_t_n[5]),
- .O(GPIO_T[5]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[60]_INST_0
- (.I0(gpio_out_t_n[60]),
- .O(GPIO_T[60]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[61]_INST_0
- (.I0(gpio_out_t_n[61]),
- .O(GPIO_T[61]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[62]_INST_0
- (.I0(gpio_out_t_n[62]),
- .O(GPIO_T[62]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[63]_INST_0
- (.I0(gpio_out_t_n[63]),
- .O(GPIO_T[63]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[6]_INST_0
- (.I0(gpio_out_t_n[6]),
- .O(GPIO_T[6]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[7]_INST_0
- (.I0(gpio_out_t_n[7]),
- .O(GPIO_T[7]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[8]_INST_0
- (.I0(gpio_out_t_n[8]),
- .O(GPIO_T[8]));
- LUT1 #(
- .INIT(2'h1))
- \GPIO_T[9]_INST_0
- (.I0(gpio_out_t_n[9]),
- .O(GPIO_T[9]));
- LUT1 #(
- .INIT(2'h1))
- I2C0_SCL_T_INST_0
- (.I0(I2C0_SCL_T_n),
- .O(I2C0_SCL_T));
- LUT1 #(
- .INIT(2'h1))
- I2C0_SDA_T_INST_0
- (.I0(I2C0_SDA_T_n),
- .O(I2C0_SDA_T));
- LUT1 #(
- .INIT(2'h1))
- I2C1_SCL_T_INST_0
- (.I0(I2C1_SCL_T_n),
- .O(I2C1_SCL_T));
- LUT1 #(
- .INIT(2'h1))
- I2C1_SDA_T_INST_0
- (.I0(I2C1_SDA_T_n),
- .O(I2C1_SDA_T));
- (* BOX_TYPE = "PRIMITIVE" *)
- PS7 PS7_i
- (.DDRA(buffered_DDR_Addr),
- .DDRARB(DDR_ARB),
- .DDRBA(buffered_DDR_BankAddr),
- .DDRCASB(buffered_DDR_CAS_n),
- .DDRCKE(buffered_DDR_CKE),
- .DDRCKN(buffered_DDR_Clk_n),
- .DDRCKP(buffered_DDR_Clk),
- .DDRCSB(buffered_DDR_CS_n),
- .DDRDM(buffered_DDR_DM),
- .DDRDQ(buffered_DDR_DQ),
- .DDRDQSN(buffered_DDR_DQS_n),
- .DDRDQSP(buffered_DDR_DQS),
- .DDRDRSTB(buffered_DDR_DRSTB),
- .DDRODT(buffered_DDR_ODT),
- .DDRRASB(buffered_DDR_RAS_n),
- .DDRVRN(buffered_DDR_VRN),
- .DDRVRP(buffered_DDR_VRP),
- .DDRWEB(buffered_DDR_WEB),
- .DMA0ACLK(DMA0_ACLK),
- .DMA0DAREADY(DMA0_DAREADY),
- .DMA0DATYPE(DMA0_DATYPE),
- .DMA0DAVALID(DMA0_DAVALID),
- .DMA0DRLAST(DMA0_DRLAST),
- .DMA0DRREADY(DMA0_DRREADY),
- .DMA0DRTYPE(DMA0_DRTYPE),
- .DMA0DRVALID(DMA0_DRVALID),
- .DMA0RSTN(DMA0_RSTN),
- .DMA1ACLK(DMA1_ACLK),
- .DMA1DAREADY(DMA1_DAREADY),
- .DMA1DATYPE(DMA1_DATYPE),
- .DMA1DAVALID(DMA1_DAVALID),
- .DMA1DRLAST(DMA1_DRLAST),
- .DMA1DRREADY(DMA1_DRREADY),
- .DMA1DRTYPE(DMA1_DRTYPE),
- .DMA1DRVALID(DMA1_DRVALID),
- .DMA1RSTN(DMA1_RSTN),
- .DMA2ACLK(DMA2_ACLK),
- .DMA2DAREADY(DMA2_DAREADY),
- .DMA2DATYPE(DMA2_DATYPE),
- .DMA2DAVALID(DMA2_DAVALID),
- .DMA2DRLAST(DMA2_DRLAST),
- .DMA2DRREADY(DMA2_DRREADY),
- .DMA2DRTYPE(DMA2_DRTYPE),
- .DMA2DRVALID(DMA2_DRVALID),
- .DMA2RSTN(DMA2_RSTN),
- .DMA3ACLK(DMA3_ACLK),
- .DMA3DAREADY(DMA3_DAREADY),
- .DMA3DATYPE(DMA3_DATYPE),
- .DMA3DAVALID(DMA3_DAVALID),
- .DMA3DRLAST(DMA3_DRLAST),
- .DMA3DRREADY(DMA3_DRREADY),
- .DMA3DRTYPE(DMA3_DRTYPE),
- .DMA3DRVALID(DMA3_DRVALID),
- .DMA3RSTN(DMA3_RSTN),
- .EMIOCAN0PHYRX(CAN0_PHY_RX),
- .EMIOCAN0PHYTX(CAN0_PHY_TX),
- .EMIOCAN1PHYRX(CAN1_PHY_RX),
- .EMIOCAN1PHYTX(CAN1_PHY_TX),
- .EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
- .EMIOENET0GMIICOL(1'b0),
- .EMIOENET0GMIICRS(1'b0),
- .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
- .EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .EMIOENET0GMIIRXDV(1'b0),
- .EMIOENET0GMIIRXER(1'b0),
- .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
- .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
- .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
- .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
- .EMIOENET0MDIOI(ENET0_MDIO_I),
- .EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
- .EMIOENET0MDIOO(ENET0_MDIO_O),
- .EMIOENET0MDIOTN(ENET0_MDIO_T_n),
- .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
- .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
- .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
- .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
- .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
- .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
- .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
- .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
- .EMIOENET0SOFRX(ENET0_SOF_RX),
- .EMIOENET0SOFTX(ENET0_SOF_TX),
- .EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
- .EMIOENET1GMIICOL(1'b0),
- .EMIOENET1GMIICRS(1'b0),
- .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
- .EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .EMIOENET1GMIIRXDV(1'b0),
- .EMIOENET1GMIIRXER(1'b0),
- .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
- .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
- .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
- .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
- .EMIOENET1MDIOI(ENET1_MDIO_I),
- .EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
- .EMIOENET1MDIOO(ENET1_MDIO_O),
- .EMIOENET1MDIOTN(ENET1_MDIO_T_n),
- .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
- .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
- .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
- .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
- .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
- .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
- .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
- .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
- .EMIOENET1SOFRX(ENET1_SOF_RX),
- .EMIOENET1SOFTX(ENET1_SOF_TX),
- .EMIOGPIOI(GPIO_I),
- .EMIOGPIOO(GPIO_O),
- .EMIOGPIOTN(gpio_out_t_n),
- .EMIOI2C0SCLI(I2C0_SCL_I),
- .EMIOI2C0SCLO(I2C0_SCL_O),
- .EMIOI2C0SCLTN(I2C0_SCL_T_n),
- .EMIOI2C0SDAI(I2C0_SDA_I),
- .EMIOI2C0SDAO(I2C0_SDA_O),
- .EMIOI2C0SDATN(I2C0_SDA_T_n),
- .EMIOI2C1SCLI(I2C1_SCL_I),
- .EMIOI2C1SCLO(I2C1_SCL_O),
- .EMIOI2C1SCLTN(I2C1_SCL_T_n),
- .EMIOI2C1SDAI(I2C1_SDA_I),
- .EMIOI2C1SDAO(I2C1_SDA_O),
- .EMIOI2C1SDATN(I2C1_SDA_T_n),
- .EMIOPJTAGTCK(PJTAG_TCK),
- .EMIOPJTAGTDI(PJTAG_TDI),
- .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
- .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
- .EMIOPJTAGTMS(PJTAG_TMS),
- .EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
- .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
- .EMIOSDIO0CDN(SDIO0_CDN),
- .EMIOSDIO0CLK(SDIO0_CLK),
- .EMIOSDIO0CLKFB(SDIO0_CLK_FB),
- .EMIOSDIO0CMDI(SDIO0_CMD_I),
- .EMIOSDIO0CMDO(SDIO0_CMD_O),
- .EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
- .EMIOSDIO0DATAI(SDIO0_DATA_I),
- .EMIOSDIO0DATAO(SDIO0_DATA_O),
- .EMIOSDIO0DATATN(SDIO0_DATA_T_n),
- .EMIOSDIO0LED(SDIO0_LED),
- .EMIOSDIO0WP(SDIO0_WP),
- .EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
- .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
- .EMIOSDIO1CDN(SDIO1_CDN),
- .EMIOSDIO1CLK(SDIO1_CLK),
- .EMIOSDIO1CLKFB(SDIO1_CLK_FB),
- .EMIOSDIO1CMDI(SDIO1_CMD_I),
- .EMIOSDIO1CMDO(SDIO1_CMD_O),
- .EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
- .EMIOSDIO1DATAI(SDIO1_DATA_I),
- .EMIOSDIO1DATAO(SDIO1_DATA_O),
- .EMIOSDIO1DATATN(SDIO1_DATA_T_n),
- .EMIOSDIO1LED(SDIO1_LED),
- .EMIOSDIO1WP(SDIO1_WP),
- .EMIOSPI0MI(SPI0_MISO_I),
- .EMIOSPI0MO(SPI0_MOSI_O),
- .EMIOSPI0MOTN(SPI0_MOSI_T_n),
- .EMIOSPI0SCLKI(SPI0_SCLK_I),
- .EMIOSPI0SCLKO(SPI0_SCLK_O),
- .EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
- .EMIOSPI0SI(SPI0_MOSI_I),
- .EMIOSPI0SO(SPI0_MISO_O),
- .EMIOSPI0SSIN(SPI0_SS_I),
- .EMIOSPI0SSNTN(SPI0_SS_T_n),
- .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
- .EMIOSPI0STN(SPI0_MISO_T_n),
- .EMIOSPI1MI(SPI1_MISO_I),
- .EMIOSPI1MO(SPI1_MOSI_O),
- .EMIOSPI1MOTN(SPI1_MOSI_T_n),
- .EMIOSPI1SCLKI(SPI1_SCLK_I),
- .EMIOSPI1SCLKO(SPI1_SCLK_O),
- .EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
- .EMIOSPI1SI(SPI1_MOSI_I),
- .EMIOSPI1SO(SPI1_MISO_O),
- .EMIOSPI1SSIN(SPI1_SS_I),
- .EMIOSPI1SSNTN(SPI1_SS_T_n),
- .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
- .EMIOSPI1STN(SPI1_MISO_T_n),
- .EMIOSRAMINTIN(SRAM_INTIN),
- .EMIOTRACECLK(TRACE_CLK),
- .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
- .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
- .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
- .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
- .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
- .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
- .EMIOUART0CTSN(UART0_CTSN),
- .EMIOUART0DCDN(UART0_DCDN),
- .EMIOUART0DSRN(UART0_DSRN),
- .EMIOUART0DTRN(UART0_DTRN),
- .EMIOUART0RIN(UART0_RIN),
- .EMIOUART0RTSN(UART0_RTSN),
- .EMIOUART0RX(UART0_RX),
- .EMIOUART0TX(UART0_TX),
- .EMIOUART1CTSN(UART1_CTSN),
- .EMIOUART1DCDN(UART1_DCDN),
- .EMIOUART1DSRN(UART1_DSRN),
- .EMIOUART1DTRN(UART1_DTRN),
- .EMIOUART1RIN(UART1_RIN),
- .EMIOUART1RTSN(UART1_RTSN),
- .EMIOUART1RX(UART1_RX),
- .EMIOUART1TX(UART1_TX),
- .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
- .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
- .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
- .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
- .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
- .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
- .EMIOWDTCLKI(WDT_CLK_IN),
- .EMIOWDTRSTO(WDT_RST_OUT),
- .EVENTEVENTI(EVENT_EVENTI),
- .EVENTEVENTO(EVENT_EVENTO),
- .EVENTSTANDBYWFE(EVENT_STANDBYWFE),
- .EVENTSTANDBYWFI(EVENT_STANDBYWFI),
- .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
- .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
- .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
- .FPGAIDLEN(FPGA_IDLE_N),
- .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
- .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
- .FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .FTMDTRACEINVALID(1'b0),
- .FTMTF2PDEBUG(FTMT_F2P_DEBUG),
- .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
- .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
- .FTMTP2FDEBUG(FTMT_P2F_DEBUG),
- .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
- .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
- .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
- .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
- .MAXIGP0ACLK(M_AXI_GP0_ACLK),
- .MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
- .MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
- .MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
- .MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
- .MAXIGP0ARID(M_AXI_GP0_ARID),
- .MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
- .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
- .MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
- .MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
- .MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
- .MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
- .MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
- .MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
- .MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
- .MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
- .MAXIGP0AWID(M_AXI_GP0_AWID),
- .MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
- .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
- .MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
- .MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
- .MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
- .MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
- .MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
- .MAXIGP0BID(M_AXI_GP0_BID),
- .MAXIGP0BREADY(M_AXI_GP0_BREADY),
- .MAXIGP0BRESP(M_AXI_GP0_BRESP),
- .MAXIGP0BVALID(M_AXI_GP0_BVALID),
- .MAXIGP0RDATA(M_AXI_GP0_RDATA),
- .MAXIGP0RID(M_AXI_GP0_RID),
- .MAXIGP0RLAST(M_AXI_GP0_RLAST),
- .MAXIGP0RREADY(M_AXI_GP0_RREADY),
- .MAXIGP0RRESP(M_AXI_GP0_RRESP),
- .MAXIGP0RVALID(M_AXI_GP0_RVALID),
- .MAXIGP0WDATA(M_AXI_GP0_WDATA),
- .MAXIGP0WID(M_AXI_GP0_WID),
- .MAXIGP0WLAST(M_AXI_GP0_WLAST),
- .MAXIGP0WREADY(M_AXI_GP0_WREADY),
- .MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
- .MAXIGP0WVALID(M_AXI_GP0_WVALID),
- .MAXIGP1ACLK(M_AXI_GP1_ACLK),
- .MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
- .MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
- .MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
- .MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
- .MAXIGP1ARID(M_AXI_GP1_ARID),
- .MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
- .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
- .MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
- .MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
- .MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
- .MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
- .MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
- .MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
- .MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
- .MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
- .MAXIGP1AWID(M_AXI_GP1_AWID),
- .MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
- .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
- .MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
- .MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
- .MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
- .MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
- .MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
- .MAXIGP1BID(M_AXI_GP1_BID),
- .MAXIGP1BREADY(M_AXI_GP1_BREADY),
- .MAXIGP1BRESP(M_AXI_GP1_BRESP),
- .MAXIGP1BVALID(M_AXI_GP1_BVALID),
- .MAXIGP1RDATA(M_AXI_GP1_RDATA),
- .MAXIGP1RID(M_AXI_GP1_RID),
- .MAXIGP1RLAST(M_AXI_GP1_RLAST),
- .MAXIGP1RREADY(M_AXI_GP1_RREADY),
- .MAXIGP1RRESP(M_AXI_GP1_RRESP),
- .MAXIGP1RVALID(M_AXI_GP1_RVALID),
- .MAXIGP1WDATA(M_AXI_GP1_WDATA),
- .MAXIGP1WID(M_AXI_GP1_WID),
- .MAXIGP1WLAST(M_AXI_GP1_WLAST),
- .MAXIGP1WREADY(M_AXI_GP1_WREADY),
- .MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
- .MAXIGP1WVALID(M_AXI_GP1_WVALID),
- .MIO(buffered_MIO),
- .PSCLK(buffered_PS_CLK),
- .PSPORB(buffered_PS_PORB),
- .PSSRSTB(buffered_PS_SRSTB),
- .SAXIACPACLK(S_AXI_ACP_ACLK),
- .SAXIACPARADDR(S_AXI_ACP_ARADDR),
- .SAXIACPARBURST(S_AXI_ACP_ARBURST),
- .SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
- .SAXIACPARESETN(S_AXI_ACP_ARESETN),
- .SAXIACPARID(S_AXI_ACP_ARID),
- .SAXIACPARLEN(S_AXI_ACP_ARLEN),
- .SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
- .SAXIACPARPROT(S_AXI_ACP_ARPROT),
- .SAXIACPARQOS(S_AXI_ACP_ARQOS),
- .SAXIACPARREADY(S_AXI_ACP_ARREADY),
- .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
- .SAXIACPARUSER(S_AXI_ACP_ARUSER),
- .SAXIACPARVALID(S_AXI_ACP_ARVALID),
- .SAXIACPAWADDR(S_AXI_ACP_AWADDR),
- .SAXIACPAWBURST(S_AXI_ACP_AWBURST),
- .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
- .SAXIACPAWID(S_AXI_ACP_AWID),
- .SAXIACPAWLEN(S_AXI_ACP_AWLEN),
- .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
- .SAXIACPAWPROT(S_AXI_ACP_AWPROT),
- .SAXIACPAWQOS(S_AXI_ACP_AWQOS),
- .SAXIACPAWREADY(S_AXI_ACP_AWREADY),
- .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
- .SAXIACPAWUSER(S_AXI_ACP_AWUSER),
- .SAXIACPAWVALID(S_AXI_ACP_AWVALID),
- .SAXIACPBID(S_AXI_ACP_BID),
- .SAXIACPBREADY(S_AXI_ACP_BREADY),
- .SAXIACPBRESP(S_AXI_ACP_BRESP),
- .SAXIACPBVALID(S_AXI_ACP_BVALID),
- .SAXIACPRDATA(S_AXI_ACP_RDATA),
- .SAXIACPRID(S_AXI_ACP_RID),
- .SAXIACPRLAST(S_AXI_ACP_RLAST),
- .SAXIACPRREADY(S_AXI_ACP_RREADY),
- .SAXIACPRRESP(S_AXI_ACP_RRESP),
- .SAXIACPRVALID(S_AXI_ACP_RVALID),
- .SAXIACPWDATA(S_AXI_ACP_WDATA),
- .SAXIACPWID(S_AXI_ACP_WID),
- .SAXIACPWLAST(S_AXI_ACP_WLAST),
- .SAXIACPWREADY(S_AXI_ACP_WREADY),
- .SAXIACPWSTRB(S_AXI_ACP_WSTRB),
- .SAXIACPWVALID(S_AXI_ACP_WVALID),
- .SAXIGP0ACLK(S_AXI_GP0_ACLK),
- .SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
- .SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
- .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
- .SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
- .SAXIGP0ARID(S_AXI_GP0_ARID),
- .SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
- .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
- .SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
- .SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
- .SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
- .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
- .SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
- .SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
- .SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
- .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
- .SAXIGP0AWID(S_AXI_GP0_AWID),
- .SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
- .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
- .SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
- .SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
- .SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
- .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
- .SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
- .SAXIGP0BID(S_AXI_GP0_BID),
- .SAXIGP0BREADY(S_AXI_GP0_BREADY),
- .SAXIGP0BRESP(S_AXI_GP0_BRESP),
- .SAXIGP0BVALID(S_AXI_GP0_BVALID),
- .SAXIGP0RDATA(S_AXI_GP0_RDATA),
- .SAXIGP0RID(S_AXI_GP0_RID),
- .SAXIGP0RLAST(S_AXI_GP0_RLAST),
- .SAXIGP0RREADY(S_AXI_GP0_RREADY),
- .SAXIGP0RRESP(S_AXI_GP0_RRESP),
- .SAXIGP0RVALID(S_AXI_GP0_RVALID),
- .SAXIGP0WDATA(S_AXI_GP0_WDATA),
- .SAXIGP0WID(S_AXI_GP0_WID),
- .SAXIGP0WLAST(S_AXI_GP0_WLAST),
- .SAXIGP0WREADY(S_AXI_GP0_WREADY),
- .SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
- .SAXIGP0WVALID(S_AXI_GP0_WVALID),
- .SAXIGP1ACLK(S_AXI_GP1_ACLK),
- .SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
- .SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
- .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
- .SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
- .SAXIGP1ARID(S_AXI_GP1_ARID),
- .SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
- .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
- .SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
- .SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
- .SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
- .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
- .SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
- .SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
- .SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
- .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
- .SAXIGP1AWID(S_AXI_GP1_AWID),
- .SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
- .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
- .SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
- .SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
- .SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
- .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
- .SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
- .SAXIGP1BID(S_AXI_GP1_BID),
- .SAXIGP1BREADY(S_AXI_GP1_BREADY),
- .SAXIGP1BRESP(S_AXI_GP1_BRESP),
- .SAXIGP1BVALID(S_AXI_GP1_BVALID),
- .SAXIGP1RDATA(S_AXI_GP1_RDATA),
- .SAXIGP1RID(S_AXI_GP1_RID),
- .SAXIGP1RLAST(S_AXI_GP1_RLAST),
- .SAXIGP1RREADY(S_AXI_GP1_RREADY),
- .SAXIGP1RRESP(S_AXI_GP1_RRESP),
- .SAXIGP1RVALID(S_AXI_GP1_RVALID),
- .SAXIGP1WDATA(S_AXI_GP1_WDATA),
- .SAXIGP1WID(S_AXI_GP1_WID),
- .SAXIGP1WLAST(S_AXI_GP1_WLAST),
- .SAXIGP1WREADY(S_AXI_GP1_WREADY),
- .SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
- .SAXIGP1WVALID(S_AXI_GP1_WVALID),
- .SAXIHP0ACLK(S_AXI_HP0_ACLK),
- .SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
- .SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
- .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
- .SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
- .SAXIHP0ARID(S_AXI_HP0_ARID),
- .SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
- .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
- .SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
- .SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
- .SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
- .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
- .SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
- .SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
- .SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
- .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
- .SAXIHP0AWID(S_AXI_HP0_AWID),
- .SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
- .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
- .SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
- .SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
- .SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
- .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
- .SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
- .SAXIHP0BID(S_AXI_HP0_BID),
- .SAXIHP0BREADY(S_AXI_HP0_BREADY),
- .SAXIHP0BRESP(S_AXI_HP0_BRESP),
- .SAXIHP0BVALID(S_AXI_HP0_BVALID),
- .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
- .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
- .SAXIHP0RDATA(S_AXI_HP0_RDATA),
- .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
- .SAXIHP0RID(S_AXI_HP0_RID),
- .SAXIHP0RLAST(S_AXI_HP0_RLAST),
- .SAXIHP0RREADY(S_AXI_HP0_RREADY),
- .SAXIHP0RRESP(S_AXI_HP0_RRESP),
- .SAXIHP0RVALID(S_AXI_HP0_RVALID),
- .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
- .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
- .SAXIHP0WDATA(S_AXI_HP0_WDATA),
- .SAXIHP0WID(S_AXI_HP0_WID),
- .SAXIHP0WLAST(S_AXI_HP0_WLAST),
- .SAXIHP0WREADY(S_AXI_HP0_WREADY),
- .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
- .SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
- .SAXIHP0WVALID(S_AXI_HP0_WVALID),
- .SAXIHP1ACLK(S_AXI_HP1_ACLK),
- .SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
- .SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
- .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
- .SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
- .SAXIHP1ARID(S_AXI_HP1_ARID),
- .SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
- .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
- .SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
- .SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
- .SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
- .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
- .SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
- .SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
- .SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
- .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
- .SAXIHP1AWID(S_AXI_HP1_AWID),
- .SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
- .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
- .SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
- .SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
- .SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
- .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
- .SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
- .SAXIHP1BID(S_AXI_HP1_BID),
- .SAXIHP1BREADY(S_AXI_HP1_BREADY),
- .SAXIHP1BRESP(S_AXI_HP1_BRESP),
- .SAXIHP1BVALID(S_AXI_HP1_BVALID),
- .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
- .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
- .SAXIHP1RDATA(S_AXI_HP1_RDATA),
- .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
- .SAXIHP1RID(S_AXI_HP1_RID),
- .SAXIHP1RLAST(S_AXI_HP1_RLAST),
- .SAXIHP1RREADY(S_AXI_HP1_RREADY),
- .SAXIHP1RRESP(S_AXI_HP1_RRESP),
- .SAXIHP1RVALID(S_AXI_HP1_RVALID),
- .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
- .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
- .SAXIHP1WDATA(S_AXI_HP1_WDATA),
- .SAXIHP1WID(S_AXI_HP1_WID),
- .SAXIHP1WLAST(S_AXI_HP1_WLAST),
- .SAXIHP1WREADY(S_AXI_HP1_WREADY),
- .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
- .SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
- .SAXIHP1WVALID(S_AXI_HP1_WVALID),
- .SAXIHP2ACLK(S_AXI_HP2_ACLK),
- .SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
- .SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
- .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
- .SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
- .SAXIHP2ARID(S_AXI_HP2_ARID),
- .SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
- .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
- .SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
- .SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
- .SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
- .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
- .SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
- .SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
- .SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
- .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
- .SAXIHP2AWID(S_AXI_HP2_AWID),
- .SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
- .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
- .SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
- .SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
- .SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
- .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
- .SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
- .SAXIHP2BID(S_AXI_HP2_BID),
- .SAXIHP2BREADY(S_AXI_HP2_BREADY),
- .SAXIHP2BRESP(S_AXI_HP2_BRESP),
- .SAXIHP2BVALID(S_AXI_HP2_BVALID),
- .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
- .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
- .SAXIHP2RDATA(S_AXI_HP2_RDATA),
- .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
- .SAXIHP2RID(S_AXI_HP2_RID),
- .SAXIHP2RLAST(S_AXI_HP2_RLAST),
- .SAXIHP2RREADY(S_AXI_HP2_RREADY),
- .SAXIHP2RRESP(S_AXI_HP2_RRESP),
- .SAXIHP2RVALID(S_AXI_HP2_RVALID),
- .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
- .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
- .SAXIHP2WDATA(S_AXI_HP2_WDATA),
- .SAXIHP2WID(S_AXI_HP2_WID),
- .SAXIHP2WLAST(S_AXI_HP2_WLAST),
- .SAXIHP2WREADY(S_AXI_HP2_WREADY),
- .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
- .SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
- .SAXIHP2WVALID(S_AXI_HP2_WVALID),
- .SAXIHP3ACLK(S_AXI_HP3_ACLK),
- .SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
- .SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
- .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
- .SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
- .SAXIHP3ARID(S_AXI_HP3_ARID),
- .SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
- .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
- .SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
- .SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
- .SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
- .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
- .SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
- .SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
- .SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
- .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
- .SAXIHP3AWID(S_AXI_HP3_AWID),
- .SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
- .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
- .SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
- .SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
- .SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
- .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
- .SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
- .SAXIHP3BID(S_AXI_HP3_BID),
- .SAXIHP3BREADY(S_AXI_HP3_BREADY),
- .SAXIHP3BRESP(S_AXI_HP3_BRESP),
- .SAXIHP3BVALID(S_AXI_HP3_BVALID),
- .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
- .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
- .SAXIHP3RDATA(S_AXI_HP3_RDATA),
- .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
- .SAXIHP3RID(S_AXI_HP3_RID),
- .SAXIHP3RLAST(S_AXI_HP3_RLAST),
- .SAXIHP3RREADY(S_AXI_HP3_RREADY),
- .SAXIHP3RRESP(S_AXI_HP3_RRESP),
- .SAXIHP3RVALID(S_AXI_HP3_RVALID),
- .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
- .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
- .SAXIHP3WDATA(S_AXI_HP3_WDATA),
- .SAXIHP3WID(S_AXI_HP3_WID),
- .SAXIHP3WLAST(S_AXI_HP3_WLAST),
- .SAXIHP3WREADY(S_AXI_HP3_WREADY),
- .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
- .SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
- .SAXIHP3WVALID(S_AXI_HP3_WVALID));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF PS_CLK_BIBUF
- (.IO(buffered_PS_CLK),
- .PAD(PS_CLK));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF PS_PORB_BIBUF
- (.IO(buffered_PS_PORB),
- .PAD(PS_PORB));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF PS_SRSTB_BIBUF
- (.IO(buffered_PS_SRSTB),
- .PAD(PS_SRSTB));
- LUT1 #(
- .INIT(2'h1))
- SDIO0_CMD_T_INST_0
- (.I0(SDIO0_CMD_T_n),
- .O(SDIO0_CMD_T));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[0]_INST_0
- (.I0(SDIO0_DATA_T_n[0]),
- .O(SDIO0_DATA_T[0]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[1]_INST_0
- (.I0(SDIO0_DATA_T_n[1]),
- .O(SDIO0_DATA_T[1]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[2]_INST_0
- (.I0(SDIO0_DATA_T_n[2]),
- .O(SDIO0_DATA_T[2]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO0_DATA_T[3]_INST_0
- (.I0(SDIO0_DATA_T_n[3]),
- .O(SDIO0_DATA_T[3]));
- LUT1 #(
- .INIT(2'h1))
- SDIO1_CMD_T_INST_0
- (.I0(SDIO1_CMD_T_n),
- .O(SDIO1_CMD_T));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[0]_INST_0
- (.I0(SDIO1_DATA_T_n[0]),
- .O(SDIO1_DATA_T[0]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[1]_INST_0
- (.I0(SDIO1_DATA_T_n[1]),
- .O(SDIO1_DATA_T[1]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[2]_INST_0
- (.I0(SDIO1_DATA_T_n[2]),
- .O(SDIO1_DATA_T[2]));
- LUT1 #(
- .INIT(2'h1))
- \SDIO1_DATA_T[3]_INST_0
- (.I0(SDIO1_DATA_T_n[3]),
- .O(SDIO1_DATA_T[3]));
- LUT1 #(
- .INIT(2'h1))
- SPI0_MISO_T_INST_0
- (.I0(SPI0_MISO_T_n),
- .O(SPI0_MISO_T));
- LUT1 #(
- .INIT(2'h1))
- SPI0_MOSI_T_INST_0
- (.I0(SPI0_MOSI_T_n),
- .O(SPI0_MOSI_T));
- LUT1 #(
- .INIT(2'h1))
- SPI0_SCLK_T_INST_0
- (.I0(SPI0_SCLK_T_n),
- .O(SPI0_SCLK_T));
- LUT1 #(
- .INIT(2'h1))
- SPI0_SS_T_INST_0
- (.I0(SPI0_SS_T_n),
- .O(SPI0_SS_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_MISO_T_INST_0
- (.I0(SPI1_MISO_T_n),
- .O(SPI1_MISO_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_MOSI_T_INST_0
- (.I0(SPI1_MOSI_T_n),
- .O(SPI1_MOSI_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_SCLK_T_INST_0
- (.I0(SPI1_SCLK_T_n),
- .O(SPI1_SCLK_T));
- LUT1 #(
- .INIT(2'h1))
- SPI1_SS_T_INST_0
- (.I0(SPI1_SS_T_n),
- .O(SPI1_SS_T));
- VCC VCC
- (.P(\<const1> ));
- (* BOX_TYPE = "PRIMITIVE" *)
- BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
- (.I(FCLK_CLK_unbuffered),
- .O(FCLK_CLK0));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[0].MIO_BIBUF
- (.IO(buffered_MIO[0]),
- .PAD(MIO[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[10].MIO_BIBUF
- (.IO(buffered_MIO[10]),
- .PAD(MIO[10]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[11].MIO_BIBUF
- (.IO(buffered_MIO[11]),
- .PAD(MIO[11]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[12].MIO_BIBUF
- (.IO(buffered_MIO[12]),
- .PAD(MIO[12]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[13].MIO_BIBUF
- (.IO(buffered_MIO[13]),
- .PAD(MIO[13]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[14].MIO_BIBUF
- (.IO(buffered_MIO[14]),
- .PAD(MIO[14]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[15].MIO_BIBUF
- (.IO(buffered_MIO[15]),
- .PAD(MIO[15]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[16].MIO_BIBUF
- (.IO(buffered_MIO[16]),
- .PAD(MIO[16]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[17].MIO_BIBUF
- (.IO(buffered_MIO[17]),
- .PAD(MIO[17]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[18].MIO_BIBUF
- (.IO(buffered_MIO[18]),
- .PAD(MIO[18]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[19].MIO_BIBUF
- (.IO(buffered_MIO[19]),
- .PAD(MIO[19]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[1].MIO_BIBUF
- (.IO(buffered_MIO[1]),
- .PAD(MIO[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[20].MIO_BIBUF
- (.IO(buffered_MIO[20]),
- .PAD(MIO[20]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[21].MIO_BIBUF
- (.IO(buffered_MIO[21]),
- .PAD(MIO[21]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[22].MIO_BIBUF
- (.IO(buffered_MIO[22]),
- .PAD(MIO[22]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[23].MIO_BIBUF
- (.IO(buffered_MIO[23]),
- .PAD(MIO[23]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[24].MIO_BIBUF
- (.IO(buffered_MIO[24]),
- .PAD(MIO[24]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[25].MIO_BIBUF
- (.IO(buffered_MIO[25]),
- .PAD(MIO[25]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[26].MIO_BIBUF
- (.IO(buffered_MIO[26]),
- .PAD(MIO[26]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[27].MIO_BIBUF
- (.IO(buffered_MIO[27]),
- .PAD(MIO[27]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[28].MIO_BIBUF
- (.IO(buffered_MIO[28]),
- .PAD(MIO[28]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[29].MIO_BIBUF
- (.IO(buffered_MIO[29]),
- .PAD(MIO[29]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[2].MIO_BIBUF
- (.IO(buffered_MIO[2]),
- .PAD(MIO[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[30].MIO_BIBUF
- (.IO(buffered_MIO[30]),
- .PAD(MIO[30]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[31].MIO_BIBUF
- (.IO(buffered_MIO[31]),
- .PAD(MIO[31]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[32].MIO_BIBUF
- (.IO(buffered_MIO[32]),
- .PAD(MIO[32]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[33].MIO_BIBUF
- (.IO(buffered_MIO[33]),
- .PAD(MIO[33]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[34].MIO_BIBUF
- (.IO(buffered_MIO[34]),
- .PAD(MIO[34]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[35].MIO_BIBUF
- (.IO(buffered_MIO[35]),
- .PAD(MIO[35]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[36].MIO_BIBUF
- (.IO(buffered_MIO[36]),
- .PAD(MIO[36]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[37].MIO_BIBUF
- (.IO(buffered_MIO[37]),
- .PAD(MIO[37]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[38].MIO_BIBUF
- (.IO(buffered_MIO[38]),
- .PAD(MIO[38]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[39].MIO_BIBUF
- (.IO(buffered_MIO[39]),
- .PAD(MIO[39]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[3].MIO_BIBUF
- (.IO(buffered_MIO[3]),
- .PAD(MIO[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[40].MIO_BIBUF
- (.IO(buffered_MIO[40]),
- .PAD(MIO[40]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[41].MIO_BIBUF
- (.IO(buffered_MIO[41]),
- .PAD(MIO[41]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[42].MIO_BIBUF
- (.IO(buffered_MIO[42]),
- .PAD(MIO[42]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[43].MIO_BIBUF
- (.IO(buffered_MIO[43]),
- .PAD(MIO[43]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[44].MIO_BIBUF
- (.IO(buffered_MIO[44]),
- .PAD(MIO[44]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[45].MIO_BIBUF
- (.IO(buffered_MIO[45]),
- .PAD(MIO[45]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[46].MIO_BIBUF
- (.IO(buffered_MIO[46]),
- .PAD(MIO[46]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[47].MIO_BIBUF
- (.IO(buffered_MIO[47]),
- .PAD(MIO[47]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[48].MIO_BIBUF
- (.IO(buffered_MIO[48]),
- .PAD(MIO[48]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[49].MIO_BIBUF
- (.IO(buffered_MIO[49]),
- .PAD(MIO[49]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[4].MIO_BIBUF
- (.IO(buffered_MIO[4]),
- .PAD(MIO[4]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[50].MIO_BIBUF
- (.IO(buffered_MIO[50]),
- .PAD(MIO[50]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[51].MIO_BIBUF
- (.IO(buffered_MIO[51]),
- .PAD(MIO[51]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[52].MIO_BIBUF
- (.IO(buffered_MIO[52]),
- .PAD(MIO[52]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[53].MIO_BIBUF
- (.IO(buffered_MIO[53]),
- .PAD(MIO[53]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[5].MIO_BIBUF
- (.IO(buffered_MIO[5]),
- .PAD(MIO[5]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[6].MIO_BIBUF
- (.IO(buffered_MIO[6]),
- .PAD(MIO[6]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[7].MIO_BIBUF
- (.IO(buffered_MIO[7]),
- .PAD(MIO[7]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[8].MIO_BIBUF
- (.IO(buffered_MIO[8]),
- .PAD(MIO[8]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk13[9].MIO_BIBUF
- (.IO(buffered_MIO[9]),
- .PAD(MIO[9]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk14[0].DDR_BankAddr_BIBUF
- (.IO(buffered_DDR_BankAddr[0]),
- .PAD(DDR_BankAddr[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk14[1].DDR_BankAddr_BIBUF
- (.IO(buffered_DDR_BankAddr[1]),
- .PAD(DDR_BankAddr[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk14[2].DDR_BankAddr_BIBUF
- (.IO(buffered_DDR_BankAddr[2]),
- .PAD(DDR_BankAddr[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[0].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[0]),
- .PAD(DDR_Addr[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[10].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[10]),
- .PAD(DDR_Addr[10]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[11].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[11]),
- .PAD(DDR_Addr[11]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[12].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[12]),
- .PAD(DDR_Addr[12]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[13].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[13]),
- .PAD(DDR_Addr[13]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[14].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[14]),
- .PAD(DDR_Addr[14]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[1].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[1]),
- .PAD(DDR_Addr[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[2].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[2]),
- .PAD(DDR_Addr[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[3].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[3]),
- .PAD(DDR_Addr[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[4].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[4]),
- .PAD(DDR_Addr[4]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[5].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[5]),
- .PAD(DDR_Addr[5]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[6].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[6]),
- .PAD(DDR_Addr[6]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[7].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[7]),
- .PAD(DDR_Addr[7]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[8].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[8]),
- .PAD(DDR_Addr[8]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk15[9].DDR_Addr_BIBUF
- (.IO(buffered_DDR_Addr[9]),
- .PAD(DDR_Addr[9]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[0].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[0]),
- .PAD(DDR_DM[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[1].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[1]),
- .PAD(DDR_DM[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[2].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[2]),
- .PAD(DDR_DM[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk16[3].DDR_DM_BIBUF
- (.IO(buffered_DDR_DM[3]),
- .PAD(DDR_DM[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[0].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[0]),
- .PAD(DDR_DQ[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[10].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[10]),
- .PAD(DDR_DQ[10]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[11].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[11]),
- .PAD(DDR_DQ[11]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[12].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[12]),
- .PAD(DDR_DQ[12]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[13].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[13]),
- .PAD(DDR_DQ[13]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[14].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[14]),
- .PAD(DDR_DQ[14]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[15].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[15]),
- .PAD(DDR_DQ[15]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[16].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[16]),
- .PAD(DDR_DQ[16]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[17].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[17]),
- .PAD(DDR_DQ[17]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[18].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[18]),
- .PAD(DDR_DQ[18]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[19].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[19]),
- .PAD(DDR_DQ[19]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[1].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[1]),
- .PAD(DDR_DQ[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[20].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[20]),
- .PAD(DDR_DQ[20]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[21].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[21]),
- .PAD(DDR_DQ[21]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[22].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[22]),
- .PAD(DDR_DQ[22]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[23].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[23]),
- .PAD(DDR_DQ[23]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[24].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[24]),
- .PAD(DDR_DQ[24]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[25].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[25]),
- .PAD(DDR_DQ[25]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[26].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[26]),
- .PAD(DDR_DQ[26]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[27].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[27]),
- .PAD(DDR_DQ[27]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[28].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[28]),
- .PAD(DDR_DQ[28]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[29].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[29]),
- .PAD(DDR_DQ[29]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[2].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[2]),
- .PAD(DDR_DQ[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[30].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[30]),
- .PAD(DDR_DQ[30]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[31].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[31]),
- .PAD(DDR_DQ[31]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[3].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[3]),
- .PAD(DDR_DQ[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[4].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[4]),
- .PAD(DDR_DQ[4]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[5].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[5]),
- .PAD(DDR_DQ[5]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[6].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[6]),
- .PAD(DDR_DQ[6]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[7].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[7]),
- .PAD(DDR_DQ[7]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[8].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[8]),
- .PAD(DDR_DQ[8]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk17[9].DDR_DQ_BIBUF
- (.IO(buffered_DDR_DQ[9]),
- .PAD(DDR_DQ[9]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[0].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[0]),
- .PAD(DDR_DQS_n[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[1].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[1]),
- .PAD(DDR_DQS_n[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[2].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[2]),
- .PAD(DDR_DQS_n[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk18[3].DDR_DQS_n_BIBUF
- (.IO(buffered_DDR_DQS_n[3]),
- .PAD(DDR_DQS_n[3]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[0].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[0]),
- .PAD(DDR_DQS[0]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[1].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[1]),
- .PAD(DDR_DQS[1]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[2].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[2]),
- .PAD(DDR_DQS[2]));
- (* BOX_TYPE = "PRIMITIVE" *)
- BIBUF \genblk19[3].DDR_DQS_BIBUF
- (.IO(buffered_DDR_DQS[3]),
- .PAD(DDR_DQS[3]));
- LUT1 #(
- .INIT(2'h2))
- i_0
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[0] ));
- LUT1 #(
- .INIT(2'h2))
- i_1
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[0] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_10
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[7] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_11
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[7] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_12
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[6] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_13
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[6] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_14
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[5] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_15
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[5] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_16
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[4] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_17
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[4] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_18
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[3] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_19
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[3] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_2
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[0] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_20
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[2] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_21
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[2] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_22
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[1] [1]));
- LUT1 #(
- .INIT(2'h2))
- i_23
- (.I0(1'b0),
- .O(\TRACE_DATA_PIPE[1] [0]));
- LUT1 #(
- .INIT(2'h2))
- i_3
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[7] ));
- LUT1 #(
- .INIT(2'h2))
- i_4
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[6] ));
- LUT1 #(
- .INIT(2'h2))
- i_5
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[5] ));
- LUT1 #(
- .INIT(2'h2))
- i_6
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[4] ));
- LUT1 #(
- .INIT(2'h2))
- i_7
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[3] ));
- LUT1 #(
- .INIT(2'h2))
- i_8
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[2] ));
- LUT1 #(
- .INIT(2'h2))
- i_9
- (.I0(1'b0),
- .O(\TRACE_CTL_PIPE[1] ));
-endmodule
-
-(* CHECK_LICENSE_TYPE = "scalp_zynqps_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.2" *)
-(* NotValidForBitStream *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
- (SPI1_SCLK_I,
- SPI1_SCLK_O,
- SPI1_SCLK_T,
- SPI1_MOSI_I,
- SPI1_MOSI_O,
- SPI1_MOSI_T,
- SPI1_MISO_I,
- SPI1_MISO_O,
- SPI1_MISO_T,
- SPI1_SS_I,
- SPI1_SS_O,
- SPI1_SS1_O,
- SPI1_SS2_O,
- SPI1_SS_T,
- USB0_PORT_INDCTL,
- USB0_VBUS_PWRSELECT,
- USB0_VBUS_PWRFAULT,
- M_AXI_GP0_ARVALID,
- M_AXI_GP0_AWVALID,
- M_AXI_GP0_BREADY,
- M_AXI_GP0_RREADY,
- M_AXI_GP0_WLAST,
- M_AXI_GP0_WVALID,
- M_AXI_GP0_ARID,
- M_AXI_GP0_AWID,
- M_AXI_GP0_WID,
- M_AXI_GP0_ARBURST,
- M_AXI_GP0_ARLOCK,
- M_AXI_GP0_ARSIZE,
- M_AXI_GP0_AWBURST,
- M_AXI_GP0_AWLOCK,
- M_AXI_GP0_AWSIZE,
- M_AXI_GP0_ARPROT,
- M_AXI_GP0_AWPROT,
- M_AXI_GP0_ARADDR,
- M_AXI_GP0_AWADDR,
- M_AXI_GP0_WDATA,
- M_AXI_GP0_ARCACHE,
- M_AXI_GP0_ARLEN,
- M_AXI_GP0_ARQOS,
- M_AXI_GP0_AWCACHE,
- M_AXI_GP0_AWLEN,
- M_AXI_GP0_AWQOS,
- M_AXI_GP0_WSTRB,
- M_AXI_GP0_ACLK,
- M_AXI_GP0_ARREADY,
- M_AXI_GP0_AWREADY,
- M_AXI_GP0_BVALID,
- M_AXI_GP0_RLAST,
- M_AXI_GP0_RVALID,
- M_AXI_GP0_WREADY,
- M_AXI_GP0_BID,
- M_AXI_GP0_RID,
- M_AXI_GP0_BRESP,
- M_AXI_GP0_RRESP,
- M_AXI_GP0_RDATA,
- FCLK_CLK0,
- FCLK_RESET0_N,
- MIO,
- DDR_CAS_n,
- DDR_CKE,
- DDR_Clk_n,
- DDR_Clk,
- DDR_CS_n,
- DDR_DRSTB,
- DDR_ODT,
- DDR_RAS_n,
- DDR_WEB,
- DDR_BankAddr,
- DDR_Addr,
- DDR_VRN,
- DDR_VRP,
- DDR_DM,
- DDR_DQ,
- DDR_DQS_n,
- DDR_DQS,
- PS_SRSTB,
- PS_CLK,
- PS_PORB);
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) input SPI1_SCLK_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) output SPI1_SCLK_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) output SPI1_SCLK_T;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) input SPI1_MOSI_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) output SPI1_MOSI_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) output SPI1_MOSI_T;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) input SPI1_MISO_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) output SPI1_MISO_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) output SPI1_MISO_T;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) input SPI1_SS_I;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) output SPI1_SS_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) output SPI1_SS1_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) output SPI1_SS2_O;
- (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) output SPI1_SS_T;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
- (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input M_AXI_GP0_ACLK;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
- (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 125000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [31:0]M_AXI_GP0_RDATA;
- (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) output FCLK_CLK0;
- (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
- (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
- (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
-
- wire [14:0]DDR_Addr;
- wire [2:0]DDR_BankAddr;
- wire DDR_CAS_n;
- wire DDR_CKE;
- wire DDR_CS_n;
- wire DDR_Clk;
- wire DDR_Clk_n;
- wire [3:0]DDR_DM;
- wire [31:0]DDR_DQ;
- wire [3:0]DDR_DQS;
- wire [3:0]DDR_DQS_n;
- wire DDR_DRSTB;
- wire DDR_ODT;
- wire DDR_RAS_n;
- wire DDR_VRN;
- wire DDR_VRP;
- wire DDR_WEB;
- wire FCLK_CLK0;
- wire FCLK_RESET0_N;
- wire [53:0]MIO;
- wire M_AXI_GP0_ACLK;
- wire [31:0]M_AXI_GP0_ARADDR;
- wire [1:0]M_AXI_GP0_ARBURST;
- wire [3:0]M_AXI_GP0_ARCACHE;
- wire [11:0]M_AXI_GP0_ARID;
- wire [3:0]M_AXI_GP0_ARLEN;
- wire [1:0]M_AXI_GP0_ARLOCK;
- wire [2:0]M_AXI_GP0_ARPROT;
- wire [3:0]M_AXI_GP0_ARQOS;
- wire M_AXI_GP0_ARREADY;
- wire [2:0]M_AXI_GP0_ARSIZE;
- wire M_AXI_GP0_ARVALID;
- wire [31:0]M_AXI_GP0_AWADDR;
- wire [1:0]M_AXI_GP0_AWBURST;
- wire [3:0]M_AXI_GP0_AWCACHE;
- wire [11:0]M_AXI_GP0_AWID;
- wire [3:0]M_AXI_GP0_AWLEN;
- wire [1:0]M_AXI_GP0_AWLOCK;
- wire [2:0]M_AXI_GP0_AWPROT;
- wire [3:0]M_AXI_GP0_AWQOS;
- wire M_AXI_GP0_AWREADY;
- wire [2:0]M_AXI_GP0_AWSIZE;
- wire M_AXI_GP0_AWVALID;
- wire [11:0]M_AXI_GP0_BID;
- wire M_AXI_GP0_BREADY;
- wire [1:0]M_AXI_GP0_BRESP;
- wire M_AXI_GP0_BVALID;
- wire [31:0]M_AXI_GP0_RDATA;
- wire [11:0]M_AXI_GP0_RID;
- wire M_AXI_GP0_RLAST;
- wire M_AXI_GP0_RREADY;
- wire [1:0]M_AXI_GP0_RRESP;
- wire M_AXI_GP0_RVALID;
- wire [31:0]M_AXI_GP0_WDATA;
- wire [11:0]M_AXI_GP0_WID;
- wire M_AXI_GP0_WLAST;
- wire M_AXI_GP0_WREADY;
- wire [3:0]M_AXI_GP0_WSTRB;
- wire M_AXI_GP0_WVALID;
- wire PS_CLK;
- wire PS_PORB;
- wire PS_SRSTB;
- wire SPI1_MISO_I;
- wire SPI1_MISO_O;
- wire SPI1_MISO_T;
- wire SPI1_MOSI_I;
- wire SPI1_MOSI_O;
- wire SPI1_MOSI_T;
- wire SPI1_SCLK_I;
- wire SPI1_SCLK_O;
- wire SPI1_SCLK_T;
- wire SPI1_SS1_O;
- wire SPI1_SS2_O;
- wire SPI1_SS_I;
- wire SPI1_SS_O;
- wire SPI1_SS_T;
- wire [1:0]USB0_PORT_INDCTL;
- wire USB0_VBUS_PWRFAULT;
- wire USB0_VBUS_PWRSELECT;
- wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
- wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
- wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA0_RSTN_UNCONNECTED;
- wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA1_RSTN_UNCONNECTED;
- wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA2_RSTN_UNCONNECTED;
- wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
- wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
- wire NLW_inst_DMA3_RSTN_UNCONNECTED;
- wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
- wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
- wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
- wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
- wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
- wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
- wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
- wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
- wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
- wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
- wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
- wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
- wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
- wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
- wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
- wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
- wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
- wire NLW_inst_FCLK_CLK1_UNCONNECTED;
- wire NLW_inst_FCLK_CLK2_UNCONNECTED;
- wire NLW_inst_FCLK_CLK3_UNCONNECTED;
- wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
- wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
- wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
- wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
- wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
- wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
- wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
- wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
- wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
- wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
- wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
- wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
- wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
- wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
- wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
- wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
- wire NLW_inst_PJTAG_TDO_UNCONNECTED;
- wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
- wire NLW_inst_SDIO0_CLK_UNCONNECTED;
- wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
- wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
- wire NLW_inst_SDIO0_LED_UNCONNECTED;
- wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
- wire NLW_inst_SDIO1_CLK_UNCONNECTED;
- wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
- wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
- wire NLW_inst_SDIO1_LED_UNCONNECTED;
- wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
- wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
- wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
- wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
- wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
- wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
- wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
- wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
- wire NLW_inst_SPI0_SS_O_UNCONNECTED;
- wire NLW_inst_SPI0_SS_T_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
- wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
- wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
- wire NLW_inst_TRACE_CTL_UNCONNECTED;
- wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
- wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
- wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
- wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
- wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
- wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
- wire NLW_inst_UART0_DTRN_UNCONNECTED;
- wire NLW_inst_UART0_RTSN_UNCONNECTED;
- wire NLW_inst_UART0_TX_UNCONNECTED;
- wire NLW_inst_UART1_DTRN_UNCONNECTED;
- wire NLW_inst_UART1_RTSN_UNCONNECTED;
- wire NLW_inst_UART1_TX_UNCONNECTED;
- wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
- wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
- wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
- wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
- wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
- wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
- wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
- wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
- wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
- wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
- wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
- wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
- wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
- wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
- wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
- wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
- wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
- wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
- wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
- wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
- wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
- wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
- wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
- wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
- wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
- wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
- wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
- wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
- wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
- wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
- wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
- wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
- wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
- wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
-
- (* C_DM_WIDTH = "4" *)
- (* C_DQS_WIDTH = "4" *)
- (* C_DQ_WIDTH = "32" *)
- (* C_EMIO_GPIO_WIDTH = "64" *)
- (* C_EN_EMIO_ENET0 = "0" *)
- (* C_EN_EMIO_ENET1 = "0" *)
- (* C_EN_EMIO_PJTAG = "0" *)
- (* C_EN_EMIO_TRACE = "0" *)
- (* C_FCLK_CLK0_BUF = "TRUE" *)
- (* C_FCLK_CLK1_BUF = "FALSE" *)
- (* C_FCLK_CLK2_BUF = "FALSE" *)
- (* C_FCLK_CLK3_BUF = "FALSE" *)
- (* C_GP0_EN_MODIFIABLE_TXN = "1" *)
- (* C_GP1_EN_MODIFIABLE_TXN = "1" *)
- (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
- (* C_INCLUDE_TRACE_BUFFER = "0" *)
- (* C_IRQ_F2P_MODE = "DIRECT" *)
- (* C_MIO_PRIMITIVE = "54" *)
- (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
- (* C_M_AXI_GP0_ID_WIDTH = "12" *)
- (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
- (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
- (* C_M_AXI_GP1_ID_WIDTH = "12" *)
- (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
- (* C_NUM_F2P_INTR_INPUTS = "1" *)
- (* C_PACKAGE_NAME = "clg485" *)
- (* C_PS7_SI_REV = "PRODUCTION" *)
- (* C_S_AXI_ACP_ARUSER_VAL = "31" *)
- (* C_S_AXI_ACP_AWUSER_VAL = "31" *)
- (* C_S_AXI_ACP_ID_WIDTH = "3" *)
- (* C_S_AXI_GP0_ID_WIDTH = "6" *)
- (* C_S_AXI_GP1_ID_WIDTH = "6" *)
- (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP0_ID_WIDTH = "6" *)
- (* C_S_AXI_HP1_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP1_ID_WIDTH = "6" *)
- (* C_S_AXI_HP2_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP2_ID_WIDTH = "6" *)
- (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
- (* C_S_AXI_HP3_ID_WIDTH = "6" *)
- (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
- (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
- (* C_TRACE_INTERNAL_WIDTH = "2" *)
- (* C_TRACE_PIPELINE_WIDTH = "8" *)
- (* C_USE_AXI_NONSECURE = "0" *)
- (* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
- (* C_USE_M_AXI_GP0 = "1" *)
- (* C_USE_M_AXI_GP1 = "0" *)
- (* C_USE_S_AXI_ACP = "0" *)
- (* C_USE_S_AXI_GP0 = "0" *)
- (* C_USE_S_AXI_GP1 = "0" *)
- (* C_USE_S_AXI_HP0 = "0" *)
- (* C_USE_S_AXI_HP1 = "0" *)
- (* C_USE_S_AXI_HP2 = "0" *)
- (* C_USE_S_AXI_HP3 = "0" *)
- (* HW_HANDOFF = "scalp_zynqps_processing_system7_0_0.hwdef" *)
- (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={750} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={16} clockFreq={500} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={3} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SPI} ioStandard={} bidis={2} ioBank={} clockFreq={159.090912} usageRate={0.5} /><IO interface={SPI} ioStandard={LVCMOS25} bidis={5} ioBank={Vcco_p1} clockFreq={159.090912} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS25} bidis={2} ioBank={Vcco_p1} clockFreq={97.222221} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={97.222221} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS25} bidis={12} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={133} usageRate={0.5} /><PLL domain={Processor} vco={1500.000} /><PLL domain={Memory} vco={1000.000} /><PLL domain={IO} vco={1750.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>" *)
- (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
- (.CAN0_PHY_RX(1'b0),
- .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
- .CAN1_PHY_RX(1'b0),
- .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
- .Core0_nFIQ(1'b0),
- .Core0_nIRQ(1'b0),
- .Core1_nFIQ(1'b0),
- .Core1_nIRQ(1'b0),
- .DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
- .DDR_Addr(DDR_Addr),
- .DDR_BankAddr(DDR_BankAddr),
- .DDR_CAS_n(DDR_CAS_n),
- .DDR_CKE(DDR_CKE),
- .DDR_CS_n(DDR_CS_n),
- .DDR_Clk(DDR_Clk),
- .DDR_Clk_n(DDR_Clk_n),
- .DDR_DM(DDR_DM),
- .DDR_DQ(DDR_DQ),
- .DDR_DQS(DDR_DQS),
- .DDR_DQS_n(DDR_DQS_n),
- .DDR_DRSTB(DDR_DRSTB),
- .DDR_ODT(DDR_ODT),
- .DDR_RAS_n(DDR_RAS_n),
- .DDR_VRN(DDR_VRN),
- .DDR_VRP(DDR_VRP),
- .DDR_WEB(DDR_WEB),
- .DMA0_ACLK(1'b0),
- .DMA0_DAREADY(1'b0),
- .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
- .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
- .DMA0_DRLAST(1'b0),
- .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
- .DMA0_DRTYPE({1'b0,1'b0}),
- .DMA0_DRVALID(1'b0),
- .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
- .DMA1_ACLK(1'b0),
- .DMA1_DAREADY(1'b0),
- .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
- .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
- .DMA1_DRLAST(1'b0),
- .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
- .DMA1_DRTYPE({1'b0,1'b0}),
- .DMA1_DRVALID(1'b0),
- .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
- .DMA2_ACLK(1'b0),
- .DMA2_DAREADY(1'b0),
- .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
- .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
- .DMA2_DRLAST(1'b0),
- .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
- .DMA2_DRTYPE({1'b0,1'b0}),
- .DMA2_DRVALID(1'b0),
- .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
- .DMA3_ACLK(1'b0),
- .DMA3_DAREADY(1'b0),
- .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
- .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
- .DMA3_DRLAST(1'b0),
- .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
- .DMA3_DRTYPE({1'b0,1'b0}),
- .DMA3_DRVALID(1'b0),
- .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
- .ENET0_EXT_INTIN(1'b0),
- .ENET0_GMII_COL(1'b0),
- .ENET0_GMII_CRS(1'b0),
- .ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ENET0_GMII_RX_CLK(1'b0),
- .ENET0_GMII_RX_DV(1'b0),
- .ENET0_GMII_RX_ER(1'b0),
- .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
- .ENET0_GMII_TX_CLK(1'b0),
- .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
- .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
- .ENET0_MDIO_I(1'b0),
- .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
- .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
- .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
- .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
- .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
- .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
- .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
- .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
- .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
- .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
- .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
- .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
- .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
- .ENET1_EXT_INTIN(1'b0),
- .ENET1_GMII_COL(1'b0),
- .ENET1_GMII_CRS(1'b0),
- .ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .ENET1_GMII_RX_CLK(1'b0),
- .ENET1_GMII_RX_DV(1'b0),
- .ENET1_GMII_RX_ER(1'b0),
- .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
- .ENET1_GMII_TX_CLK(1'b0),
- .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
- .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
- .ENET1_MDIO_I(1'b0),
- .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
- .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
- .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
- .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
- .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
- .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
- .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
- .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
- .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
- .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
- .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
- .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
- .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
- .EVENT_EVENTI(1'b0),
- .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
- .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
- .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
- .FCLK_CLK0(FCLK_CLK0),
- .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
- .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
- .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
- .FCLK_CLKTRIG0_N(1'b0),
- .FCLK_CLKTRIG1_N(1'b0),
- .FCLK_CLKTRIG2_N(1'b0),
- .FCLK_CLKTRIG3_N(1'b0),
- .FCLK_RESET0_N(FCLK_RESET0_N),
- .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
- .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
- .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
- .FPGA_IDLE_N(1'b0),
- .FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
- .FTMD_TRACEIN_CLK(1'b0),
- .FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .FTMD_TRACEIN_VALID(1'b0),
- .FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
- .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
- .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
- .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
- .FTMT_F2P_TRIG_0(1'b0),
- .FTMT_F2P_TRIG_1(1'b0),
- .FTMT_F2P_TRIG_2(1'b0),
- .FTMT_F2P_TRIG_3(1'b0),
- .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
- .FTMT_P2F_TRIGACK_0(1'b0),
- .FTMT_P2F_TRIGACK_1(1'b0),
- .FTMT_P2F_TRIGACK_2(1'b0),
- .FTMT_P2F_TRIGACK_3(1'b0),
- .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
- .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
- .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
- .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
- .GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
- .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
- .I2C0_SCL_I(1'b0),
- .I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
- .I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
- .I2C0_SDA_I(1'b0),
- .I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
- .I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
- .I2C1_SCL_I(1'b0),
- .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
- .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
- .I2C1_SDA_I(1'b0),
- .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
- .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
- .IRQ_F2P(1'b0),
- .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
- .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
- .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
- .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
- .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
- .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
- .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
- .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
- .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
- .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
- .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
- .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
- .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
- .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
- .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
- .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
- .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
- .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
- .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
- .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
- .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
- .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
- .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
- .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
- .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
- .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
- .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
- .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
- .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
- .MIO(MIO),
- .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
- .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
- .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
- .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
- .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
- .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
- .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
- .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
- .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
- .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
- .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
- .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
- .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
- .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
- .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
- .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
- .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
- .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
- .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
- .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
- .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
- .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
- .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
- .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
- .M_AXI_GP0_BID(M_AXI_GP0_BID),
- .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
- .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
- .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
- .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
- .M_AXI_GP0_RID(M_AXI_GP0_RID),
- .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
- .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
- .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
- .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
- .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
- .M_AXI_GP0_WID(M_AXI_GP0_WID),
- .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
- .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
- .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
- .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
- .M_AXI_GP1_ACLK(1'b0),
- .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
- .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
- .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
- .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
- .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
- .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
- .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
- .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
- .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
- .M_AXI_GP1_ARREADY(1'b0),
- .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
- .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
- .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
- .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
- .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
- .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
- .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
- .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
- .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
- .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
- .M_AXI_GP1_AWREADY(1'b0),
- .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
- .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
- .M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
- .M_AXI_GP1_BRESP({1'b0,1'b0}),
- .M_AXI_GP1_BVALID(1'b0),
- .M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .M_AXI_GP1_RLAST(1'b0),
- .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
- .M_AXI_GP1_RRESP({1'b0,1'b0}),
- .M_AXI_GP1_RVALID(1'b0),
- .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
- .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
- .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
- .M_AXI_GP1_WREADY(1'b0),
- .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
- .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
- .PJTAG_TCK(1'b0),
- .PJTAG_TDI(1'b0),
- .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
- .PJTAG_TMS(1'b0),
- .PS_CLK(PS_CLK),
- .PS_PORB(PS_PORB),
- .PS_SRSTB(PS_SRSTB),
- .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
- .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
- .SDIO0_CDN(1'b0),
- .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
- .SDIO0_CLK_FB(1'b0),
- .SDIO0_CMD_I(1'b0),
- .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
- .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
- .SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
- .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
- .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
- .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
- .SDIO0_WP(1'b0),
- .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
- .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
- .SDIO1_CDN(1'b0),
- .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
- .SDIO1_CLK_FB(1'b0),
- .SDIO1_CMD_I(1'b0),
- .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
- .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
- .SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
- .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
- .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
- .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
- .SDIO1_WP(1'b0),
- .SPI0_MISO_I(1'b0),
- .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
- .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
- .SPI0_MOSI_I(1'b0),
- .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
- .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
- .SPI0_SCLK_I(1'b0),
- .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
- .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
- .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
- .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
- .SPI0_SS_I(1'b0),
- .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
- .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
- .SPI1_MISO_I(SPI1_MISO_I),
- .SPI1_MISO_O(SPI1_MISO_O),
- .SPI1_MISO_T(SPI1_MISO_T),
- .SPI1_MOSI_I(SPI1_MOSI_I),
- .SPI1_MOSI_O(SPI1_MOSI_O),
- .SPI1_MOSI_T(SPI1_MOSI_T),
- .SPI1_SCLK_I(SPI1_SCLK_I),
- .SPI1_SCLK_O(SPI1_SCLK_O),
- .SPI1_SCLK_T(SPI1_SCLK_T),
- .SPI1_SS1_O(SPI1_SS1_O),
- .SPI1_SS2_O(SPI1_SS2_O),
- .SPI1_SS_I(SPI1_SS_I),
- .SPI1_SS_O(SPI1_SS_O),
- .SPI1_SS_T(SPI1_SS_T),
- .SRAM_INTIN(1'b0),
- .S_AXI_ACP_ACLK(1'b0),
- .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARBURST({1'b0,1'b0}),
- .S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
- .S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARLOCK({1'b0,1'b0}),
- .S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
- .S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_ARVALID(1'b0),
- .S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWBURST({1'b0,1'b0}),
- .S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWLOCK({1'b0,1'b0}),
- .S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
- .S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_AWVALID(1'b0),
- .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
- .S_AXI_ACP_BREADY(1'b0),
- .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
- .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
- .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
- .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
- .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
- .S_AXI_ACP_RREADY(1'b0),
- .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
- .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
- .S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
- .S_AXI_ACP_WLAST(1'b0),
- .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
- .S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_ACP_WVALID(1'b0),
- .S_AXI_GP0_ACLK(1'b0),
- .S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARBURST({1'b0,1'b0}),
- .S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
- .S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARLOCK({1'b0,1'b0}),
- .S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
- .S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_ARVALID(1'b0),
- .S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWBURST({1'b0,1'b0}),
- .S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWLOCK({1'b0,1'b0}),
- .S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
- .S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP0_AWVALID(1'b0),
- .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
- .S_AXI_GP0_BREADY(1'b0),
- .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
- .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
- .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
- .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
- .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
- .S_AXI_GP0_RREADY(1'b0),
- .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
- .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
- .S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_WLAST(1'b0),
- .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
- .S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP0_WVALID(1'b0),
- .S_AXI_GP1_ACLK(1'b0),
- .S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARBURST({1'b0,1'b0}),
- .S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
- .S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARLOCK({1'b0,1'b0}),
- .S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
- .S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_ARVALID(1'b0),
- .S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWBURST({1'b0,1'b0}),
- .S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWLOCK({1'b0,1'b0}),
- .S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
- .S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_GP1_AWVALID(1'b0),
- .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
- .S_AXI_GP1_BREADY(1'b0),
- .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
- .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
- .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
- .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
- .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
- .S_AXI_GP1_RREADY(1'b0),
- .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
- .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
- .S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_WLAST(1'b0),
- .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
- .S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_GP1_WVALID(1'b0),
- .S_AXI_HP0_ACLK(1'b0),
- .S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARBURST({1'b0,1'b0}),
- .S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
- .S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
- .S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_ARVALID(1'b0),
- .S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWBURST({1'b0,1'b0}),
- .S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
- .S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP0_AWVALID(1'b0),
- .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
- .S_AXI_HP0_BREADY(1'b0),
- .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
- .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP0_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
- .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
- .S_AXI_HP0_RREADY(1'b0),
- .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
- .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_WLAST(1'b0),
- .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
- .S_AXI_HP0_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP0_WVALID(1'b0),
- .S_AXI_HP1_ACLK(1'b0),
- .S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARBURST({1'b0,1'b0}),
- .S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
- .S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
- .S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_ARVALID(1'b0),
- .S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWBURST({1'b0,1'b0}),
- .S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
- .S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP1_AWVALID(1'b0),
- .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
- .S_AXI_HP1_BREADY(1'b0),
- .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
- .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP1_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
- .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
- .S_AXI_HP1_RREADY(1'b0),
- .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
- .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_WLAST(1'b0),
- .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
- .S_AXI_HP1_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP1_WVALID(1'b0),
- .S_AXI_HP2_ACLK(1'b0),
- .S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARBURST({1'b0,1'b0}),
- .S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
- .S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
- .S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_ARVALID(1'b0),
- .S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWBURST({1'b0,1'b0}),
- .S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
- .S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP2_AWVALID(1'b0),
- .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
- .S_AXI_HP2_BREADY(1'b0),
- .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
- .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP2_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
- .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
- .S_AXI_HP2_RREADY(1'b0),
- .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
- .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_WLAST(1'b0),
- .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
- .S_AXI_HP2_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP2_WVALID(1'b0),
- .S_AXI_HP3_ACLK(1'b0),
- .S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARBURST({1'b0,1'b0}),
- .S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
- .S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARLOCK({1'b0,1'b0}),
- .S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
- .S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_ARVALID(1'b0),
- .S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWBURST({1'b0,1'b0}),
- .S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWLOCK({1'b0,1'b0}),
- .S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
- .S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
- .S_AXI_HP3_AWVALID(1'b0),
- .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
- .S_AXI_HP3_BREADY(1'b0),
- .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
- .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
- .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
- .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
- .S_AXI_HP3_RDISSUECAP1_EN(1'b0),
- .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
- .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
- .S_AXI_HP3_RREADY(1'b0),
- .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
- .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
- .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
- .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
- .S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_WLAST(1'b0),
- .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
- .S_AXI_HP3_WRISSUECAP1_EN(1'b0),
- .S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
- .S_AXI_HP3_WVALID(1'b0),
- .TRACE_CLK(1'b0),
- .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
- .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
- .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
- .TTC0_CLK0_IN(1'b0),
- .TTC0_CLK1_IN(1'b0),
- .TTC0_CLK2_IN(1'b0),
- .TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
- .TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
- .TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
- .TTC1_CLK0_IN(1'b0),
- .TTC1_CLK1_IN(1'b0),
- .TTC1_CLK2_IN(1'b0),
- .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
- .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
- .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
- .UART0_CTSN(1'b0),
- .UART0_DCDN(1'b0),
- .UART0_DSRN(1'b0),
- .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
- .UART0_RIN(1'b0),
- .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
- .UART0_RX(1'b1),
- .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
- .UART1_CTSN(1'b0),
- .UART1_DCDN(1'b0),
- .UART1_DSRN(1'b0),
- .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
- .UART1_RIN(1'b0),
- .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
- .UART1_RX(1'b1),
- .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
- .USB0_PORT_INDCTL(USB0_PORT_INDCTL),
- .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
- .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
- .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
- .USB1_VBUS_PWRFAULT(1'b0),
- .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
- .WDT_CLK_IN(1'b0),
- .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
-endmodule
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0_stub.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0_stub.v
deleted file mode 100755
index e29603e74492379ee9bab7bd44ed9642a0c8cf88..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip/2019.2/b32362bd6ba3a9e9/scalp_zynqps_processing_system7_0_0_stub.v
+++ /dev/null
@@ -1,111 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-// Date : Mon Sep 7 11:58:38 2020
-// Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_processing_system7_0_0_stub.v
-// Design : scalp_zynqps_processing_system7_0_0
-// Purpose : Stub declaration of top-level module interface
-// Device : xc7z015clg485-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.2" *)
-module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T,
- SPI1_MOSI_I, SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I,
- SPI1_SS_O, SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
- USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
- M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
- M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
- M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
- M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
- M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
- M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
- M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
- M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
- DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
- DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
-/* synthesis syn_black_box black_box_pad_pin="SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
- input SPI1_SCLK_I;
- output SPI1_SCLK_O;
- output SPI1_SCLK_T;
- input SPI1_MOSI_I;
- output SPI1_MOSI_O;
- output SPI1_MOSI_T;
- input SPI1_MISO_I;
- output SPI1_MISO_O;
- output SPI1_MISO_T;
- input SPI1_SS_I;
- output SPI1_SS_O;
- output SPI1_SS1_O;
- output SPI1_SS2_O;
- output SPI1_SS_T;
- output [1:0]USB0_PORT_INDCTL;
- output USB0_VBUS_PWRSELECT;
- input USB0_VBUS_PWRFAULT;
- output M_AXI_GP0_ARVALID;
- output M_AXI_GP0_AWVALID;
- output M_AXI_GP0_BREADY;
- output M_AXI_GP0_RREADY;
- output M_AXI_GP0_WLAST;
- output M_AXI_GP0_WVALID;
- output [11:0]M_AXI_GP0_ARID;
- output [11:0]M_AXI_GP0_AWID;
- output [11:0]M_AXI_GP0_WID;
- output [1:0]M_AXI_GP0_ARBURST;
- output [1:0]M_AXI_GP0_ARLOCK;
- output [2:0]M_AXI_GP0_ARSIZE;
- output [1:0]M_AXI_GP0_AWBURST;
- output [1:0]M_AXI_GP0_AWLOCK;
- output [2:0]M_AXI_GP0_AWSIZE;
- output [2:0]M_AXI_GP0_ARPROT;
- output [2:0]M_AXI_GP0_AWPROT;
- output [31:0]M_AXI_GP0_ARADDR;
- output [31:0]M_AXI_GP0_AWADDR;
- output [31:0]M_AXI_GP0_WDATA;
- output [3:0]M_AXI_GP0_ARCACHE;
- output [3:0]M_AXI_GP0_ARLEN;
- output [3:0]M_AXI_GP0_ARQOS;
- output [3:0]M_AXI_GP0_AWCACHE;
- output [3:0]M_AXI_GP0_AWLEN;
- output [3:0]M_AXI_GP0_AWQOS;
- output [3:0]M_AXI_GP0_WSTRB;
- input M_AXI_GP0_ACLK;
- input M_AXI_GP0_ARREADY;
- input M_AXI_GP0_AWREADY;
- input M_AXI_GP0_BVALID;
- input M_AXI_GP0_RLAST;
- input M_AXI_GP0_RVALID;
- input M_AXI_GP0_WREADY;
- input [11:0]M_AXI_GP0_BID;
- input [11:0]M_AXI_GP0_RID;
- input [1:0]M_AXI_GP0_BRESP;
- input [1:0]M_AXI_GP0_RRESP;
- input [31:0]M_AXI_GP0_RDATA;
- output FCLK_CLK0;
- output FCLK_RESET0_N;
- inout [53:0]MIO;
- inout DDR_CAS_n;
- inout DDR_CKE;
- inout DDR_Clk_n;
- inout DDR_Clk;
- inout DDR_CS_n;
- inout DDR_DRSTB;
- inout DDR_ODT;
- inout DDR_RAS_n;
- inout DDR_WEB;
- inout [2:0]DDR_BankAddr;
- inout [14:0]DDR_Addr;
- inout DDR_VRN;
- inout DDR_VRP;
- inout [3:0]DDR_DM;
- inout [31:0]DDR_DQ;
- inout [3:0]DDR_DQS_n;
- inout [3:0]DDR_DQS;
- inout PS_SRSTB;
- inout PS_CLK;
- inout PS_PORB;
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml
deleted file mode 100644
index 327dde7ea690cde73925c6b70ec73b17dab5405c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml
+++ /dev/null
@@ -1,52 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<document>
-<!--The data in this file is primarily intended for consumption by Xilinx tools.
-The structure and the elements are likely to change over the next few releases.
-This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Mon Sep 7 13:34:51 2020">
-<section name="Project Information" visible="false">
-<property name="ProjectID" value="4f59540fcef14713bed3e418c6dd0597" type="ProjectID"/>
-<property name="ProjectIteration" value="1" type="ProjectIteration"/>
-</section>
-<section name="PlanAhead Usage" visible="true">
-<item name="Project Data">
-<property name="SrcSetCount" value="1" type="SrcSetCount"/>
-<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
-<property name="DesignMode" value="RTL" type="DesignMode"/>
-<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
-<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
-</item>
-<item name="Java Command Handlers">
-<property name="FileExit" value="1" type="JavaHandler"/>
-<property name="ManageCompositeTargets" value="1" type="JavaHandler"/>
-<property name="RunSynthesis" value="1" type="JavaHandler"/>
-<property name="ViewInstTempl" value="1" type="JavaHandler"/>
-<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
-</item>
-<item name="Gui Handlers">
-<property name="BaseDialog_OK" value="2" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="14" type="GuiHandlerData"/>
-<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_CHECKPOINT" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_CONSTRAINTS" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_IMPORT" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_IP" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_TEXT_EDITOR" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_EXIT" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
-<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_VIEW_INST_TEMPL" value="1" type="GuiHandlerData"/>
-<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
-<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
-</item>
-<item name="Other">
-<property name="GuiMode" value="130" type="GuiMode"/>
-<property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="123" type="TclMode"/>
-</item>
-</section>
-</application>
-</document>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt
deleted file mode 100644
index 023052cab505345c50834e560e42db8c25daf798..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt
+++ /dev/null
@@ -1 +0,0 @@
-The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v
deleted file mode 100644
index efcfe970834e2414e5c26606f7f23769378194aa..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v
+++ /dev/null
@@ -1,68 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 6
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_gnd_constant_0 (
- dout
-);
-
-output wire [0 : 0] dout;
-
- xlconstant_v1_1_6_xlconstant #(
- .CONST_WIDTH(1),
- .CONST_VAL('H0)
- ) inst (
- .dout(dout)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v
deleted file mode 100644
index 561083ed29e20fa15b7673a7dc2201820954d69d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v
+++ /dev/null
@@ -1,612 +0,0 @@
-
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-
-`timescale 1ns/1ps
-
-module scalp_zynqps_processing_system7_0_0 (
-SPI1_SCLK_I,
-SPI1_SCLK_O,
-SPI1_SCLK_T,
-SPI1_MOSI_I,
-SPI1_MOSI_O,
-SPI1_MOSI_T,
-SPI1_MISO_I,
-SPI1_MISO_O,
-SPI1_MISO_T,
-SPI1_SS_I,
-SPI1_SS_O,
-SPI1_SS1_O,
-SPI1_SS2_O,
-SPI1_SS_T,
-USB0_PORT_INDCTL,
-USB0_VBUS_PWRSELECT,
-USB0_VBUS_PWRFAULT,
-M_AXI_GP0_ARVALID,
-M_AXI_GP0_AWVALID,
-M_AXI_GP0_BREADY,
-M_AXI_GP0_RREADY,
-M_AXI_GP0_WLAST,
-M_AXI_GP0_WVALID,
-M_AXI_GP0_ARID,
-M_AXI_GP0_AWID,
-M_AXI_GP0_WID,
-M_AXI_GP0_ARBURST,
-M_AXI_GP0_ARLOCK,
-M_AXI_GP0_ARSIZE,
-M_AXI_GP0_AWBURST,
-M_AXI_GP0_AWLOCK,
-M_AXI_GP0_AWSIZE,
-M_AXI_GP0_ARPROT,
-M_AXI_GP0_AWPROT,
-M_AXI_GP0_ARADDR,
-M_AXI_GP0_AWADDR,
-M_AXI_GP0_WDATA,
-M_AXI_GP0_ARCACHE,
-M_AXI_GP0_ARLEN,
-M_AXI_GP0_ARQOS,
-M_AXI_GP0_AWCACHE,
-M_AXI_GP0_AWLEN,
-M_AXI_GP0_AWQOS,
-M_AXI_GP0_WSTRB,
-M_AXI_GP0_ACLK,
-M_AXI_GP0_ARREADY,
-M_AXI_GP0_AWREADY,
-M_AXI_GP0_BVALID,
-M_AXI_GP0_RLAST,
-M_AXI_GP0_RVALID,
-M_AXI_GP0_WREADY,
-M_AXI_GP0_BID,
-M_AXI_GP0_RID,
-M_AXI_GP0_BRESP,
-M_AXI_GP0_RRESP,
-M_AXI_GP0_RDATA,
-FCLK_CLK0,
-FCLK_RESET0_N,
-MIO,
-DDR_CAS_n,
-DDR_CKE,
-DDR_Clk_n,
-DDR_Clk,
-DDR_CS_n,
-DDR_DRSTB,
-DDR_ODT,
-DDR_RAS_n,
-DDR_WEB,
-DDR_BankAddr,
-DDR_Addr,
-DDR_VRN,
-DDR_VRP,
-DDR_DM,
-DDR_DQ,
-DDR_DQS_n,
-DDR_DQS,
-PS_SRSTB,
-PS_CLK,
-PS_PORB
-);
-input SPI1_SCLK_I;
-output SPI1_SCLK_O;
-output SPI1_SCLK_T;
-input SPI1_MOSI_I;
-output SPI1_MOSI_O;
-output SPI1_MOSI_T;
-input SPI1_MISO_I;
-output SPI1_MISO_O;
-output SPI1_MISO_T;
-input SPI1_SS_I;
-output SPI1_SS_O;
-output SPI1_SS1_O;
-output SPI1_SS2_O;
-output SPI1_SS_T;
-output [1 : 0] USB0_PORT_INDCTL;
-output USB0_VBUS_PWRSELECT;
-input USB0_VBUS_PWRFAULT;
-output M_AXI_GP0_ARVALID;
-output M_AXI_GP0_AWVALID;
-output M_AXI_GP0_BREADY;
-output M_AXI_GP0_RREADY;
-output M_AXI_GP0_WLAST;
-output M_AXI_GP0_WVALID;
-output [11 : 0] M_AXI_GP0_ARID;
-output [11 : 0] M_AXI_GP0_AWID;
-output [11 : 0] M_AXI_GP0_WID;
-output [1 : 0] M_AXI_GP0_ARBURST;
-output [1 : 0] M_AXI_GP0_ARLOCK;
-output [2 : 0] M_AXI_GP0_ARSIZE;
-output [1 : 0] M_AXI_GP0_AWBURST;
-output [1 : 0] M_AXI_GP0_AWLOCK;
-output [2 : 0] M_AXI_GP0_AWSIZE;
-output [2 : 0] M_AXI_GP0_ARPROT;
-output [2 : 0] M_AXI_GP0_AWPROT;
-output [31 : 0] M_AXI_GP0_ARADDR;
-output [31 : 0] M_AXI_GP0_AWADDR;
-output [31 : 0] M_AXI_GP0_WDATA;
-output [3 : 0] M_AXI_GP0_ARCACHE;
-output [3 : 0] M_AXI_GP0_ARLEN;
-output [3 : 0] M_AXI_GP0_ARQOS;
-output [3 : 0] M_AXI_GP0_AWCACHE;
-output [3 : 0] M_AXI_GP0_AWLEN;
-output [3 : 0] M_AXI_GP0_AWQOS;
-output [3 : 0] M_AXI_GP0_WSTRB;
-input M_AXI_GP0_ACLK;
-input M_AXI_GP0_ARREADY;
-input M_AXI_GP0_AWREADY;
-input M_AXI_GP0_BVALID;
-input M_AXI_GP0_RLAST;
-input M_AXI_GP0_RVALID;
-input M_AXI_GP0_WREADY;
-input [11 : 0] M_AXI_GP0_BID;
-input [11 : 0] M_AXI_GP0_RID;
-input [1 : 0] M_AXI_GP0_BRESP;
-input [1 : 0] M_AXI_GP0_RRESP;
-input [31 : 0] M_AXI_GP0_RDATA;
-output FCLK_CLK0;
-output FCLK_RESET0_N;
-input [53 : 0] MIO;
-input DDR_CAS_n;
-input DDR_CKE;
-input DDR_Clk_n;
-input DDR_Clk;
-input DDR_CS_n;
-input DDR_DRSTB;
-input DDR_ODT;
-input DDR_RAS_n;
-input DDR_WEB;
-input [2 : 0] DDR_BankAddr;
-input [14 : 0] DDR_Addr;
-input DDR_VRN;
-input DDR_VRP;
-input [3 : 0] DDR_DM;
-input [31 : 0] DDR_DQ;
-input [3 : 0] DDR_DQS_n;
-input [3 : 0] DDR_DQS;
-input PS_SRSTB;
-input PS_CLK;
-input PS_PORB;
-
- processing_system7_vip_v1_0_8 #(
- .C_USE_M_AXI_GP0(1),
- .C_USE_M_AXI_GP1(0),
- .C_USE_S_AXI_ACP(0),
- .C_USE_S_AXI_GP0(0),
- .C_USE_S_AXI_GP1(0),
- .C_USE_S_AXI_HP0(0),
- .C_USE_S_AXI_HP1(0),
- .C_USE_S_AXI_HP2(0),
- .C_USE_S_AXI_HP3(0),
- .C_S_AXI_HP0_DATA_WIDTH(64),
- .C_S_AXI_HP1_DATA_WIDTH(64),
- .C_S_AXI_HP2_DATA_WIDTH(64),
- .C_S_AXI_HP3_DATA_WIDTH(64),
- .C_HIGH_OCM_EN(0),
- .C_FCLK_CLK0_FREQ(125.0),
- .C_FCLK_CLK1_FREQ(10.0),
- .C_FCLK_CLK2_FREQ(10.0),
- .C_FCLK_CLK3_FREQ(10.0),
- .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
- .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
- .C_M_AXI_GP0_THREAD_ID_WIDTH (12),
- .C_M_AXI_GP1_THREAD_ID_WIDTH (12)
- ) inst (
- .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
- .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
- .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
- .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
- .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
- .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
- .M_AXI_GP0_ARID(M_AXI_GP0_ARID),
- .M_AXI_GP0_AWID(M_AXI_GP0_AWID),
- .M_AXI_GP0_WID(M_AXI_GP0_WID),
- .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
- .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
- .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
- .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
- .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
- .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
- .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
- .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
- .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
- .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
- .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
- .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
- .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
- .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
- .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
- .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
- .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
- .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
- .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
- .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
- .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
- .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
- .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
- .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
- .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
- .M_AXI_GP0_BID(M_AXI_GP0_BID),
- .M_AXI_GP0_RID(M_AXI_GP0_RID),
- .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
- .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
- .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
- .M_AXI_GP1_ARVALID(),
- .M_AXI_GP1_AWVALID(),
- .M_AXI_GP1_BREADY(),
- .M_AXI_GP1_RREADY(),
- .M_AXI_GP1_WLAST(),
- .M_AXI_GP1_WVALID(),
- .M_AXI_GP1_ARID(),
- .M_AXI_GP1_AWID(),
- .M_AXI_GP1_WID(),
- .M_AXI_GP1_ARBURST(),
- .M_AXI_GP1_ARLOCK(),
- .M_AXI_GP1_ARSIZE(),
- .M_AXI_GP1_AWBURST(),
- .M_AXI_GP1_AWLOCK(),
- .M_AXI_GP1_AWSIZE(),
- .M_AXI_GP1_ARPROT(),
- .M_AXI_GP1_AWPROT(),
- .M_AXI_GP1_ARADDR(),
- .M_AXI_GP1_AWADDR(),
- .M_AXI_GP1_WDATA(),
- .M_AXI_GP1_ARCACHE(),
- .M_AXI_GP1_ARLEN(),
- .M_AXI_GP1_ARQOS(),
- .M_AXI_GP1_AWCACHE(),
- .M_AXI_GP1_AWLEN(),
- .M_AXI_GP1_AWQOS(),
- .M_AXI_GP1_WSTRB(),
- .M_AXI_GP1_ACLK(1'B0),
- .M_AXI_GP1_ARREADY(1'B0),
- .M_AXI_GP1_AWREADY(1'B0),
- .M_AXI_GP1_BVALID(1'B0),
- .M_AXI_GP1_RLAST(1'B0),
- .M_AXI_GP1_RVALID(1'B0),
- .M_AXI_GP1_WREADY(1'B0),
- .M_AXI_GP1_BID(12'B0),
- .M_AXI_GP1_RID(12'B0),
- .M_AXI_GP1_BRESP(2'B0),
- .M_AXI_GP1_RRESP(2'B0),
- .M_AXI_GP1_RDATA(32'B0),
- .S_AXI_GP0_ARREADY(),
- .S_AXI_GP0_AWREADY(),
- .S_AXI_GP0_BVALID(),
- .S_AXI_GP0_RLAST(),
- .S_AXI_GP0_RVALID(),
- .S_AXI_GP0_WREADY(),
- .S_AXI_GP0_BRESP(),
- .S_AXI_GP0_RRESP(),
- .S_AXI_GP0_RDATA(),
- .S_AXI_GP0_BID(),
- .S_AXI_GP0_RID(),
- .S_AXI_GP0_ACLK(1'B0),
- .S_AXI_GP0_ARVALID(1'B0),
- .S_AXI_GP0_AWVALID(1'B0),
- .S_AXI_GP0_BREADY(1'B0),
- .S_AXI_GP0_RREADY(1'B0),
- .S_AXI_GP0_WLAST(1'B0),
- .S_AXI_GP0_WVALID(1'B0),
- .S_AXI_GP0_ARBURST(2'B0),
- .S_AXI_GP0_ARLOCK(2'B0),
- .S_AXI_GP0_ARSIZE(3'B0),
- .S_AXI_GP0_AWBURST(2'B0),
- .S_AXI_GP0_AWLOCK(2'B0),
- .S_AXI_GP0_AWSIZE(3'B0),
- .S_AXI_GP0_ARPROT(3'B0),
- .S_AXI_GP0_AWPROT(3'B0),
- .S_AXI_GP0_ARADDR(32'B0),
- .S_AXI_GP0_AWADDR(32'B0),
- .S_AXI_GP0_WDATA(32'B0),
- .S_AXI_GP0_ARCACHE(4'B0),
- .S_AXI_GP0_ARLEN(4'B0),
- .S_AXI_GP0_ARQOS(4'B0),
- .S_AXI_GP0_AWCACHE(4'B0),
- .S_AXI_GP0_AWLEN(4'B0),
- .S_AXI_GP0_AWQOS(4'B0),
- .S_AXI_GP0_WSTRB(4'B0),
- .S_AXI_GP0_ARID(6'B0),
- .S_AXI_GP0_AWID(6'B0),
- .S_AXI_GP0_WID(6'B0),
- .S_AXI_GP1_ARREADY(),
- .S_AXI_GP1_AWREADY(),
- .S_AXI_GP1_BVALID(),
- .S_AXI_GP1_RLAST(),
- .S_AXI_GP1_RVALID(),
- .S_AXI_GP1_WREADY(),
- .S_AXI_GP1_BRESP(),
- .S_AXI_GP1_RRESP(),
- .S_AXI_GP1_RDATA(),
- .S_AXI_GP1_BID(),
- .S_AXI_GP1_RID(),
- .S_AXI_GP1_ACLK(1'B0),
- .S_AXI_GP1_ARVALID(1'B0),
- .S_AXI_GP1_AWVALID(1'B0),
- .S_AXI_GP1_BREADY(1'B0),
- .S_AXI_GP1_RREADY(1'B0),
- .S_AXI_GP1_WLAST(1'B0),
- .S_AXI_GP1_WVALID(1'B0),
- .S_AXI_GP1_ARBURST(2'B0),
- .S_AXI_GP1_ARLOCK(2'B0),
- .S_AXI_GP1_ARSIZE(3'B0),
- .S_AXI_GP1_AWBURST(2'B0),
- .S_AXI_GP1_AWLOCK(2'B0),
- .S_AXI_GP1_AWSIZE(3'B0),
- .S_AXI_GP1_ARPROT(3'B0),
- .S_AXI_GP1_AWPROT(3'B0),
- .S_AXI_GP1_ARADDR(32'B0),
- .S_AXI_GP1_AWADDR(32'B0),
- .S_AXI_GP1_WDATA(32'B0),
- .S_AXI_GP1_ARCACHE(4'B0),
- .S_AXI_GP1_ARLEN(4'B0),
- .S_AXI_GP1_ARQOS(4'B0),
- .S_AXI_GP1_AWCACHE(4'B0),
- .S_AXI_GP1_AWLEN(4'B0),
- .S_AXI_GP1_AWQOS(4'B0),
- .S_AXI_GP1_WSTRB(4'B0),
- .S_AXI_GP1_ARID(6'B0),
- .S_AXI_GP1_AWID(6'B0),
- .S_AXI_GP1_WID(6'B0),
- .S_AXI_ACP_ARREADY(),
- .S_AXI_ACP_AWREADY(),
- .S_AXI_ACP_BVALID(),
- .S_AXI_ACP_RLAST(),
- .S_AXI_ACP_RVALID(),
- .S_AXI_ACP_WREADY(),
- .S_AXI_ACP_BRESP(),
- .S_AXI_ACP_RRESP(),
- .S_AXI_ACP_BID(),
- .S_AXI_ACP_RID(),
- .S_AXI_ACP_RDATA(),
- .S_AXI_ACP_ACLK(1'B0),
- .S_AXI_ACP_ARVALID(1'B0),
- .S_AXI_ACP_AWVALID(1'B0),
- .S_AXI_ACP_BREADY(1'B0),
- .S_AXI_ACP_RREADY(1'B0),
- .S_AXI_ACP_WLAST(1'B0),
- .S_AXI_ACP_WVALID(1'B0),
- .S_AXI_ACP_ARID(3'B0),
- .S_AXI_ACP_ARPROT(3'B0),
- .S_AXI_ACP_AWID(3'B0),
- .S_AXI_ACP_AWPROT(3'B0),
- .S_AXI_ACP_WID(3'B0),
- .S_AXI_ACP_ARADDR(32'B0),
- .S_AXI_ACP_AWADDR(32'B0),
- .S_AXI_ACP_ARCACHE(4'B0),
- .S_AXI_ACP_ARLEN(4'B0),
- .S_AXI_ACP_ARQOS(4'B0),
- .S_AXI_ACP_AWCACHE(4'B0),
- .S_AXI_ACP_AWLEN(4'B0),
- .S_AXI_ACP_AWQOS(4'B0),
- .S_AXI_ACP_ARBURST(2'B0),
- .S_AXI_ACP_ARLOCK(2'B0),
- .S_AXI_ACP_ARSIZE(3'B0),
- .S_AXI_ACP_AWBURST(2'B0),
- .S_AXI_ACP_AWLOCK(2'B0),
- .S_AXI_ACP_AWSIZE(3'B0),
- .S_AXI_ACP_ARUSER(5'B0),
- .S_AXI_ACP_AWUSER(5'B0),
- .S_AXI_ACP_WDATA(64'B0),
- .S_AXI_ACP_WSTRB(8'B0),
- .S_AXI_HP0_ARREADY(),
- .S_AXI_HP0_AWREADY(),
- .S_AXI_HP0_BVALID(),
- .S_AXI_HP0_RLAST(),
- .S_AXI_HP0_RVALID(),
- .S_AXI_HP0_WREADY(),
- .S_AXI_HP0_BRESP(),
- .S_AXI_HP0_RRESP(),
- .S_AXI_HP0_BID(),
- .S_AXI_HP0_RID(),
- .S_AXI_HP0_RDATA(),
- .S_AXI_HP0_ACLK(1'B0),
- .S_AXI_HP0_ARVALID(1'B0),
- .S_AXI_HP0_AWVALID(1'B0),
- .S_AXI_HP0_BREADY(1'B0),
- .S_AXI_HP0_RREADY(1'B0),
- .S_AXI_HP0_WLAST(1'B0),
- .S_AXI_HP0_WVALID(1'B0),
- .S_AXI_HP0_ARBURST(2'B0),
- .S_AXI_HP0_ARLOCK(2'B0),
- .S_AXI_HP0_ARSIZE(3'B0),
- .S_AXI_HP0_AWBURST(2'B0),
- .S_AXI_HP0_AWLOCK(2'B0),
- .S_AXI_HP0_AWSIZE(3'B0),
- .S_AXI_HP0_ARPROT(3'B0),
- .S_AXI_HP0_AWPROT(3'B0),
- .S_AXI_HP0_ARADDR(32'B0),
- .S_AXI_HP0_AWADDR(32'B0),
- .S_AXI_HP0_ARCACHE(4'B0),
- .S_AXI_HP0_ARLEN(4'B0),
- .S_AXI_HP0_ARQOS(4'B0),
- .S_AXI_HP0_AWCACHE(4'B0),
- .S_AXI_HP0_AWLEN(4'B0),
- .S_AXI_HP0_AWQOS(4'B0),
- .S_AXI_HP0_ARID(6'B0),
- .S_AXI_HP0_AWID(6'B0),
- .S_AXI_HP0_WID(6'B0),
- .S_AXI_HP0_WDATA(64'B0),
- .S_AXI_HP0_WSTRB(8'B0),
- .S_AXI_HP1_ARREADY(),
- .S_AXI_HP1_AWREADY(),
- .S_AXI_HP1_BVALID(),
- .S_AXI_HP1_RLAST(),
- .S_AXI_HP1_RVALID(),
- .S_AXI_HP1_WREADY(),
- .S_AXI_HP1_BRESP(),
- .S_AXI_HP1_RRESP(),
- .S_AXI_HP1_BID(),
- .S_AXI_HP1_RID(),
- .S_AXI_HP1_RDATA(),
- .S_AXI_HP1_ACLK(1'B0),
- .S_AXI_HP1_ARVALID(1'B0),
- .S_AXI_HP1_AWVALID(1'B0),
- .S_AXI_HP1_BREADY(1'B0),
- .S_AXI_HP1_RREADY(1'B0),
- .S_AXI_HP1_WLAST(1'B0),
- .S_AXI_HP1_WVALID(1'B0),
- .S_AXI_HP1_ARBURST(2'B0),
- .S_AXI_HP1_ARLOCK(2'B0),
- .S_AXI_HP1_ARSIZE(3'B0),
- .S_AXI_HP1_AWBURST(2'B0),
- .S_AXI_HP1_AWLOCK(2'B0),
- .S_AXI_HP1_AWSIZE(3'B0),
- .S_AXI_HP1_ARPROT(3'B0),
- .S_AXI_HP1_AWPROT(3'B0),
- .S_AXI_HP1_ARADDR(32'B0),
- .S_AXI_HP1_AWADDR(32'B0),
- .S_AXI_HP1_ARCACHE(4'B0),
- .S_AXI_HP1_ARLEN(4'B0),
- .S_AXI_HP1_ARQOS(4'B0),
- .S_AXI_HP1_AWCACHE(4'B0),
- .S_AXI_HP1_AWLEN(4'B0),
- .S_AXI_HP1_AWQOS(4'B0),
- .S_AXI_HP1_ARID(6'B0),
- .S_AXI_HP1_AWID(6'B0),
- .S_AXI_HP1_WID(6'B0),
- .S_AXI_HP1_WDATA(64'B0),
- .S_AXI_HP1_WSTRB(8'B0),
- .S_AXI_HP2_ARREADY(),
- .S_AXI_HP2_AWREADY(),
- .S_AXI_HP2_BVALID(),
- .S_AXI_HP2_RLAST(),
- .S_AXI_HP2_RVALID(),
- .S_AXI_HP2_WREADY(),
- .S_AXI_HP2_BRESP(),
- .S_AXI_HP2_RRESP(),
- .S_AXI_HP2_BID(),
- .S_AXI_HP2_RID(),
- .S_AXI_HP2_RDATA(),
- .S_AXI_HP2_ACLK(1'B0),
- .S_AXI_HP2_ARVALID(1'B0),
- .S_AXI_HP2_AWVALID(1'B0),
- .S_AXI_HP2_BREADY(1'B0),
- .S_AXI_HP2_RREADY(1'B0),
- .S_AXI_HP2_WLAST(1'B0),
- .S_AXI_HP2_WVALID(1'B0),
- .S_AXI_HP2_ARBURST(2'B0),
- .S_AXI_HP2_ARLOCK(2'B0),
- .S_AXI_HP2_ARSIZE(3'B0),
- .S_AXI_HP2_AWBURST(2'B0),
- .S_AXI_HP2_AWLOCK(2'B0),
- .S_AXI_HP2_AWSIZE(3'B0),
- .S_AXI_HP2_ARPROT(3'B0),
- .S_AXI_HP2_AWPROT(3'B0),
- .S_AXI_HP2_ARADDR(32'B0),
- .S_AXI_HP2_AWADDR(32'B0),
- .S_AXI_HP2_ARCACHE(4'B0),
- .S_AXI_HP2_ARLEN(4'B0),
- .S_AXI_HP2_ARQOS(4'B0),
- .S_AXI_HP2_AWCACHE(4'B0),
- .S_AXI_HP2_AWLEN(4'B0),
- .S_AXI_HP2_AWQOS(4'B0),
- .S_AXI_HP2_ARID(6'B0),
- .S_AXI_HP2_AWID(6'B0),
- .S_AXI_HP2_WID(6'B0),
- .S_AXI_HP2_WDATA(64'B0),
- .S_AXI_HP2_WSTRB(8'B0),
- .S_AXI_HP3_ARREADY(),
- .S_AXI_HP3_AWREADY(),
- .S_AXI_HP3_BVALID(),
- .S_AXI_HP3_RLAST(),
- .S_AXI_HP3_RVALID(),
- .S_AXI_HP3_WREADY(),
- .S_AXI_HP3_BRESP(),
- .S_AXI_HP3_RRESP(),
- .S_AXI_HP3_BID(),
- .S_AXI_HP3_RID(),
- .S_AXI_HP3_RDATA(),
- .S_AXI_HP3_ACLK(1'B0),
- .S_AXI_HP3_ARVALID(1'B0),
- .S_AXI_HP3_AWVALID(1'B0),
- .S_AXI_HP3_BREADY(1'B0),
- .S_AXI_HP3_RREADY(1'B0),
- .S_AXI_HP3_WLAST(1'B0),
- .S_AXI_HP3_WVALID(1'B0),
- .S_AXI_HP3_ARBURST(2'B0),
- .S_AXI_HP3_ARLOCK(2'B0),
- .S_AXI_HP3_ARSIZE(3'B0),
- .S_AXI_HP3_AWBURST(2'B0),
- .S_AXI_HP3_AWLOCK(2'B0),
- .S_AXI_HP3_AWSIZE(3'B0),
- .S_AXI_HP3_ARPROT(3'B0),
- .S_AXI_HP3_AWPROT(3'B0),
- .S_AXI_HP3_ARADDR(32'B0),
- .S_AXI_HP3_AWADDR(32'B0),
- .S_AXI_HP3_ARCACHE(4'B0),
- .S_AXI_HP3_ARLEN(4'B0),
- .S_AXI_HP3_ARQOS(4'B0),
- .S_AXI_HP3_AWCACHE(4'B0),
- .S_AXI_HP3_AWLEN(4'B0),
- .S_AXI_HP3_AWQOS(4'B0),
- .S_AXI_HP3_ARID(6'B0),
- .S_AXI_HP3_AWID(6'B0),
- .S_AXI_HP3_WID(6'B0),
- .S_AXI_HP3_WDATA(64'B0),
- .S_AXI_HP3_WSTRB(8'B0),
- .FCLK_CLK0(FCLK_CLK0),
-
- .FCLK_CLK1(),
-
- .FCLK_CLK2(),
-
- .FCLK_CLK3(),
- .FCLK_RESET0_N(FCLK_RESET0_N),
- .FCLK_RESET1_N(),
- .FCLK_RESET2_N(),
- .FCLK_RESET3_N(),
- .IRQ_F2P(16'B0),
- .PS_SRSTB(PS_SRSTB),
- .PS_CLK(PS_CLK),
- .PS_PORB(PS_PORB)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v
deleted file mode 100644
index 065a5263fe61893f53dc350541bd9f82a5797211..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v
+++ /dev/null
@@ -1,74 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-// IP Revision: 1
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_util_vector_logic_0_0 (
- Op1,
- Op2,
- Res
-);
-
-input wire [0 : 0] Op1;
-input wire [0 : 0] Op2;
-output wire [0 : 0] Res;
-
- util_vector_logic_v2_0_1_util_vector_logic #(
- .C_OPERATION("or"),
- .C_SIZE(1)
- ) inst (
- .Op1(Op1),
- .Op2(Op2),
- .Res(Res)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v
deleted file mode 100644
index 7a36d0de7ed6ecff815ed13285e8a76934e637d5..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v
+++ /dev/null
@@ -1,72 +0,0 @@
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-// IP Revision: 1
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module scalp_zynqps_util_vector_logic_1_0 (
- Op1,
- Res
-);
-
-input wire [0 : 0] Op1;
-output wire [0 : 0] Res;
-
- util_vector_logic_v2_0_1_util_vector_logic #(
- .C_OPERATION("not"),
- .C_SIZE(1)
- ) inst (
- .Op1(Op1),
- .Op2(1'B0),
- .Res(Res)
- );
-endmodule
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd
deleted file mode 100644
index e32bf2606b62245018c2e55c73ab80a27d49fdcd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
--- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
---
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
---
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
---
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
--- DO NOT MODIFY THIS FILE.
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY scalp_zynqps_vio_0_0 IS
-PORT (
-CLK : IN STD_LOGIC;
-
-probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) := "0"
-);
-END scalp_zynqps_vio_0_0;
-ARCHITECTURE scalp_zynqps_vio_0_0_arch OF scalp_zynqps_vio_0_0 IS
-BEGIN
-END scalp_zynqps_vio_0_0_arch;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/sim/scalp_zynqps.vhd b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/sim/scalp_zynqps.vhd
deleted file mode 100644
index 2212d122492ba735c98d6a85a186e7a8e2712748..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/bd/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/sim/scalp_zynqps.vhd
+++ /dev/null
@@ -1,361 +0,0 @@
---Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------
---Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
---Date : Mon Sep 7 11:52:31 2020
---Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
---Command : generate_target scalp_zynqps.bd
---Design : scalp_zynqps
---Purpose : IP block netlist
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-entity scalp_zynqps is
- port (
- DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_cas_n : inout STD_LOGIC;
- DDR_ck_n : inout STD_LOGIC;
- DDR_ck_p : inout STD_LOGIC;
- DDR_cke : inout STD_LOGIC;
- DDR_cs_n : inout STD_LOGIC;
- DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_odt : inout STD_LOGIC;
- DDR_ras_n : inout STD_LOGIC;
- DDR_reset_n : inout STD_LOGIC;
- DDR_we_n : inout STD_LOGIC;
- FIXED_IO_ddr_vrn : inout STD_LOGIC;
- FIXED_IO_ddr_vrp : inout STD_LOGIC;
- FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- FIXED_IO_ps_clk : inout STD_LOGIC;
- FIXED_IO_ps_porb : inout STD_LOGIC;
- FIXED_IO_ps_srstb : inout STD_LOGIC;
- FclkClk0xCO : out STD_LOGIC;
- FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
- Spi1MOSIxSO : out STD_LOGIC;
- Spi1SSxSO : out STD_LOGIC;
- Spi1SclkxCO : out STD_LOGIC;
- Usb0VBusPwrFaultxSI : in STD_LOGIC
- );
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of scalp_zynqps : entity is "scalp_zynqps,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=scalp_zynqps,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=5,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
- attribute HW_HANDOFF : string;
- attribute HW_HANDOFF of scalp_zynqps : entity is "scalp_zynqps.hwdef";
-end scalp_zynqps;
-
-architecture STRUCTURE of scalp_zynqps is
- component scalp_zynqps_gnd_constant_0 is
- port (
- dout : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_gnd_constant_0;
- component scalp_zynqps_processing_system7_0_0 is
- port (
- SPI1_SCLK_I : in STD_LOGIC;
- SPI1_SCLK_O : out STD_LOGIC;
- SPI1_SCLK_T : out STD_LOGIC;
- SPI1_MOSI_I : in STD_LOGIC;
- SPI1_MOSI_O : out STD_LOGIC;
- SPI1_MOSI_T : out STD_LOGIC;
- SPI1_MISO_I : in STD_LOGIC;
- SPI1_MISO_O : out STD_LOGIC;
- SPI1_MISO_T : out STD_LOGIC;
- SPI1_SS_I : in STD_LOGIC;
- SPI1_SS_O : out STD_LOGIC;
- SPI1_SS1_O : out STD_LOGIC;
- SPI1_SS2_O : out STD_LOGIC;
- SPI1_SS_T : out STD_LOGIC;
- USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
- USB0_VBUS_PWRSELECT : out STD_LOGIC;
- USB0_VBUS_PWRFAULT : in STD_LOGIC;
- M_AXI_GP0_ARVALID : out STD_LOGIC;
- M_AXI_GP0_AWVALID : out STD_LOGIC;
- M_AXI_GP0_BREADY : out STD_LOGIC;
- M_AXI_GP0_RREADY : out STD_LOGIC;
- M_AXI_GP0_WLAST : out STD_LOGIC;
- M_AXI_GP0_WVALID : out STD_LOGIC;
- M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
- M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
- M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
- M_AXI_GP0_ACLK : in STD_LOGIC;
- M_AXI_GP0_ARREADY : in STD_LOGIC;
- M_AXI_GP0_AWREADY : in STD_LOGIC;
- M_AXI_GP0_BVALID : in STD_LOGIC;
- M_AXI_GP0_RLAST : in STD_LOGIC;
- M_AXI_GP0_RVALID : in STD_LOGIC;
- M_AXI_GP0_WREADY : in STD_LOGIC;
- M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
- M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
- M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
- FCLK_CLK0 : out STD_LOGIC;
- FCLK_RESET0_N : out STD_LOGIC;
- MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
- DDR_CAS_n : inout STD_LOGIC;
- DDR_CKE : inout STD_LOGIC;
- DDR_Clk_n : inout STD_LOGIC;
- DDR_Clk : inout STD_LOGIC;
- DDR_CS_n : inout STD_LOGIC;
- DDR_DRSTB : inout STD_LOGIC;
- DDR_ODT : inout STD_LOGIC;
- DDR_RAS_n : inout STD_LOGIC;
- DDR_WEB : inout STD_LOGIC;
- DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
- DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
- DDR_VRN : inout STD_LOGIC;
- DDR_VRP : inout STD_LOGIC;
- DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
- DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
- PS_SRSTB : inout STD_LOGIC;
- PS_CLK : inout STD_LOGIC;
- PS_PORB : inout STD_LOGIC
- );
- end component scalp_zynqps_processing_system7_0_0;
- component scalp_zynqps_util_vector_logic_0_0 is
- port (
- Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Res : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_util_vector_logic_0_0;
- component scalp_zynqps_util_vector_logic_1_0 is
- port (
- Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
- Res : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_util_vector_logic_1_0;
- component scalp_zynqps_vio_0_0 is
- port (
- clk : in STD_LOGIC;
- probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 )
- );
- end component scalp_zynqps_vio_0_0;
- signal USB0_VBUS_PWRFAULT_0_1 : STD_LOGIC;
- signal gnd_constant_dout : STD_LOGIC_VECTOR ( 0 to 0 );
- signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_CKE : STD_LOGIC;
- signal processing_system7_0_DDR_CK_N : STD_LOGIC;
- signal processing_system7_0_DDR_CK_P : STD_LOGIC;
- signal processing_system7_0_DDR_CS_N : STD_LOGIC;
- signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal processing_system7_0_DDR_ODT : STD_LOGIC;
- signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
- signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
- signal processing_system7_0_DDR_WE_N : STD_LOGIC;
- signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
- signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
- signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
- signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
- signal processing_system7_0_SPI1_MOSI_O : STD_LOGIC;
- signal processing_system7_0_SPI1_SCLK_O : STD_LOGIC;
- signal processing_system7_0_SPI1_SS_O : STD_LOGIC;
- signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
- signal util_vector_logic_1_Res : STD_LOGIC_VECTOR ( 0 to 0 );
- signal vio_0_probe_out0 : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
- signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
- signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- attribute X_INTERFACE_INFO : string;
- attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
- attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
- attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
- attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
- attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
- attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
- attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
- attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
- attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
- attribute X_INTERFACE_PARAMETER : string;
- attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
- attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
- attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
- attribute X_INTERFACE_INFO of FclkClk0xCO : signal is "xilinx.com:signal:clock:1.0 CLK.FCLKCLK0XCO CLK";
- attribute X_INTERFACE_PARAMETER of FclkClk0xCO : signal is "XIL_INTERFACENAME CLK.FCLKCLK0XCO, CLK_DOMAIN scalp_zynqps_processing_system7_0_0_FCLK_CLK0, FREQ_HZ 125000000, INSERT_VIP 0, PHASE 0.000";
- attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
- attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
- attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
- attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
- attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
- attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
- attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
- attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
-begin
- FclkClk0xCO <= processing_system7_0_FCLK_CLK0;
- FclkReset0xRO(0) <= util_vector_logic_0_Res(0);
- Spi1MOSIxSO <= processing_system7_0_SPI1_MOSI_O;
- Spi1SSxSO <= processing_system7_0_SPI1_SS_O;
- Spi1SclkxCO <= processing_system7_0_SPI1_SCLK_O;
- USB0_VBUS_PWRFAULT_0_1 <= Usb0VBusPwrFaultxSI;
-gnd_constant: component scalp_zynqps_gnd_constant_0
- port map (
- dout(0) => gnd_constant_dout(0)
- );
-processing_system7_0: component scalp_zynqps_processing_system7_0_0
- port map (
- DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
- DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
- DDR_CAS_n => DDR_cas_n,
- DDR_CKE => DDR_cke,
- DDR_CS_n => DDR_cs_n,
- DDR_Clk => DDR_ck_p,
- DDR_Clk_n => DDR_ck_n,
- DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
- DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
- DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
- DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
- DDR_DRSTB => DDR_reset_n,
- DDR_ODT => DDR_odt,
- DDR_RAS_n => DDR_ras_n,
- DDR_VRN => FIXED_IO_ddr_vrn,
- DDR_VRP => FIXED_IO_ddr_vrp,
- DDR_WEB => DDR_we_n,
- FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
- FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
- MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
- M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
- M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
- M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
- M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
- M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
- M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
- M_AXI_GP0_ARREADY => '0',
- M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
- M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
- M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
- M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
- M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
- M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
- M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
- M_AXI_GP0_AWREADY => '0',
- M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
- M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
- M_AXI_GP0_BID(11 downto 0) => B"000000000000",
- M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
- M_AXI_GP0_BRESP(1 downto 0) => B"00",
- M_AXI_GP0_BVALID => '0',
- M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
- M_AXI_GP0_RID(11 downto 0) => B"000000000000",
- M_AXI_GP0_RLAST => '0',
- M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
- M_AXI_GP0_RRESP(1 downto 0) => B"00",
- M_AXI_GP0_RVALID => '0',
- M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
- M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
- M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
- M_AXI_GP0_WREADY => '0',
- M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
- M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
- PS_CLK => FIXED_IO_ps_clk,
- PS_PORB => FIXED_IO_ps_porb,
- PS_SRSTB => FIXED_IO_ps_srstb,
- SPI1_MISO_I => gnd_constant_dout(0),
- SPI1_MISO_O => NLW_processing_system7_0_SPI1_MISO_O_UNCONNECTED,
- SPI1_MISO_T => NLW_processing_system7_0_SPI1_MISO_T_UNCONNECTED,
- SPI1_MOSI_I => gnd_constant_dout(0),
- SPI1_MOSI_O => processing_system7_0_SPI1_MOSI_O,
- SPI1_MOSI_T => NLW_processing_system7_0_SPI1_MOSI_T_UNCONNECTED,
- SPI1_SCLK_I => gnd_constant_dout(0),
- SPI1_SCLK_O => processing_system7_0_SPI1_SCLK_O,
- SPI1_SCLK_T => NLW_processing_system7_0_SPI1_SCLK_T_UNCONNECTED,
- SPI1_SS1_O => NLW_processing_system7_0_SPI1_SS1_O_UNCONNECTED,
- SPI1_SS2_O => NLW_processing_system7_0_SPI1_SS2_O_UNCONNECTED,
- SPI1_SS_I => gnd_constant_dout(0),
- SPI1_SS_O => processing_system7_0_SPI1_SS_O,
- SPI1_SS_T => NLW_processing_system7_0_SPI1_SS_T_UNCONNECTED,
- USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
- USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT_0_1,
- USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
- );
-util_vector_logic_0: component scalp_zynqps_util_vector_logic_0_0
- port map (
- Op1(0) => util_vector_logic_1_Res(0),
- Op2(0) => vio_0_probe_out0(0),
- Res(0) => util_vector_logic_0_Res(0)
- );
-util_vector_logic_1: component scalp_zynqps_util_vector_logic_1_0
- port map (
- Op1(0) => processing_system7_0_FCLK_RESET0_N,
- Res(0) => util_vector_logic_1_Res(0)
- );
-vio_0: component scalp_zynqps_vio_0_0
- port map (
- clk => processing_system7_0_FCLK_CLK0,
- probe_out0(0) => vio_0_probe_out0(0)
- );
-end STRUCTURE;
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/mem_init_files/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/README.txt
deleted file mode 100644
index 3cd3d87d0b8ef0b464f315d784343c8a9f1cd21c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/README.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required
-# to simulate the design for a simulator, the directory structure
-# and the generated exported files.
-#
-################################################################################
-
-1. Simulate Design
-
-To simulate design, cd to the simulator directory and execute the script.
-
-For example:-
-
-% cd questa
-% ./top.sh
-
-The export simulation flow requires the Xilinx pre-compiled simulation library
-components for the target simulator. These components are referred using the
-'-lib_map_path' switch. If this switch is specified, then the export simulation
-will automatically set this library path in the generated script and update,
-copy the simulator setup file(s) in the exported directory.
-
-If '-lib_map_path' is not specified, then the pre-compiled simulation library
-information will not be included in the exported scripts and that may cause
-simulation errors when running this script. Alternatively, you can provide the
-library information using this switch while executing the generated script.
-
-For example:-
-
-% ./top.sh -lib_map_path /design/questa/clibs
-
-Please refer to the generated script header 'Prerequisite' section for more details.
-
-2. Directory Structure
-
-By default, if the -directory switch is not specified, export_simulation will
-create the following directory structure:-
-
-<current_working_directory>/export_sim/<simulator>
-
-For example, if the current working directory is /tmp/test, export_simulation
-will create the following directory path:-
-
-/tmp/test/export_sim/questa
-
-If -directory switch is specified, export_simulation will create a simulator
-sub-directory under the specified directory path.
-
-For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
-command will create the following directory:-
-
-/tmp/test/my_test_area/func_sim/questa
-
-By default, if -simulator is not specified, export_simulation will create a
-simulator sub-directory for each simulator and export the files for each simulator
-in this sub-directory respectively.
-
-IMPORTANT: Please note that the simulation library path must be specified manually
-in the generated script for the respective simulator. Please refer to the generated
-script header 'Prerequisite' section for more details.
-
-3. Exported script and files
-
-Export simulation will create the driver shell script, setup files and copy the
-design sources in the output directory path.
-
-By default, when the -script_name switch is not specified, export_simulation will
-create the following script name:-
-
-<simulation_top>.sh (Unix)
-When exporting the files for an IP using the -of_objects switch, export_simulation
-will create the following script name:-
-
-<ip-name>.sh (Unix)
-Export simulation will create the setup files for the target simulator specified
-with the -simulator switch.
-
-For example, if the target simulator is "ies", export_simulation will create the
-'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
-file.
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/README.txt
deleted file mode 100644
index 00160c0b49260e1dec6b312a6f45263dd2685900..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/README.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/file_info.txt
deleted file mode 100644
index 2af2242e8d69103c35a06dc2273c4ab7ff829b79..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/file_info.txt
+++ /dev/null
@@ -1,21 +0,0 @@
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-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
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-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps.sh
deleted file mode 100755
index 8db0d04959de2267131542322d500f6de28b002b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps.sh
+++ /dev/null
@@ -1,152 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Aldec Active-HDL Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'scalp_zynqps.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- compile
- simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
- # Compile design files
- source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
- runvsimsa -l simulate.log -do "do {simulate.do}"
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
- map_setup_file $2
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- map_setup_file $2
- esac
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Map library.cfg file
-map_setup_file()
-{
- file="library.cfg"
- lib_map_path=""
- if [[ ($1 != "") ]]; then
- lib_map_path="$1"
- fi
- if [[ ($lib_map_path != "") ]]; then
- src_file="$lib_map_path/$file"
- if [[ -e $src_file ]]; then
- vmap -link $lib_map_path
- fi
- fi
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/activehdl/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/README.txt
deleted file mode 100644
index 5029d3619b7761e164bcf336bcb025889403889a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/README.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'execute' function for the single-step flow. This
-function is called from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/file_info.txt
deleted file mode 100644
index dbced05951139a713133fb775e2d3f0f409fa75c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/file_info.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_gnd_constant_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/dc12/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_8,../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_processing_system7_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../../.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps.sh
deleted file mode 100755
index 4285e737782558f0afbd776ee2950827545b375a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps.sh
+++ /dev/null
@@ -1,184 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Cadence Incisive Enterprise Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'scalp_zynqps.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-# Directory path for design sources and include directories (if any) wrt this path
-ref_dir="."
-
-# Override directory with 'export_sim_ref_dir' env path value if set in the shell
-if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
- ref_dir="$export_sim_ref_dir"
-fi
-
-# Set the compiled library directory
-ref_lib_dir="."
-
-# Command line options
-irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
-
-# Design libraries
-design_libs=(xilinx_vip xlconstant_v1_1_6 xil_defaultlib axi_infrastructure_v1_1_0 axi_vip_v1_1_6 processing_system7_vip_v1_0_8 util_vector_logic_v2_0_1)
-
-# Simulation root library directory
-sim_lib_dir="ies_lib"
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- execute
-}
-
-# RUN_STEP: <execute>
-execute()
-{
- irun $irun_opts \
- -reflib "$ref_lib_dir/unisim:unisim" \
- -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
- -reflib "$ref_lib_dir/secureip:secureip" \
- -reflib "$ref_lib_dir/unimacro:unimacro" \
- -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
- -top xil_defaultlib.scalp_zynqps \
- -f run.f \
- -top glbl \
- glbl.v \
- +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" \
- +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" \
- +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include"
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- else
- ref_lib_dir=$2
- fi
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- esac
-
- create_lib_dir
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Create design library directory paths
-create_lib_dir()
-{
- if [[ -e $sim_lib_dir ]]; then
- rm -rf $sim_lib_dir
- fi
-
- for (( i=0; i<${#design_libs[*]}; i++ )); do
- lib="${design_libs[i]}"
- lib_dir="$sim_lib_dir/$lib"
- if [[ ! -e $lib_dir ]]; then
- mkdir -p $lib_dir
- fi
- done
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-
- create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/ies/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/README.txt
deleted file mode 100644
index 00160c0b49260e1dec6b312a6f45263dd2685900..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/README.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/file_info.txt
deleted file mode 100644
index 2af2242e8d69103c35a06dc2273c4ab7ff829b79..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/file_info.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_gnd_constant_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/dc12/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_8,../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_processing_system7_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../../.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps.sh
deleted file mode 100755
index e3676a8f3dee43c7e12cddd0a95c9584e9a568ee..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps.sh
+++ /dev/null
@@ -1,167 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Mentor Graphics ModelSim Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'scalp_zynqps.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- compile
- simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
- # Compile design files
- source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
- vsim -64 -c -do "do {simulate.do}" -l simulate.log
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
- copy_setup_file $2
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- copy_setup_file $2
- esac
-
- create_lib_dir
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Copy modelsim.ini file
-copy_setup_file()
-{
- file="modelsim.ini"
- if [[ ($1 != "") ]]; then
- lib_map_path="$1"
- else
- lib_map_path="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/compile_simlib/modelsim"
- fi
- if [[ ($lib_map_path != "") ]]; then
- src_file="$lib_map_path/$file"
- cp $src_file .
- fi
-}
-
-# Create design library directory
-create_lib_dir()
-{
- lib_dir="modelsim_lib"
- if [[ -e $lib_dir ]]; then
- rm -rf $lib_dir
- fi
-
- mkdir $lib_dir
-
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-
- create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/modelsim/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/README.txt
deleted file mode 100644
index 00160c0b49260e1dec6b312a6f45263dd2685900..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/README.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/file_info.txt
deleted file mode 100644
index 2af2242e8d69103c35a06dc2273c4ab7ff829b79..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/file_info.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_gnd_constant_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/dc12/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_8,../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_processing_system7_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../../.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps.sh
deleted file mode 100755
index 761bbdd50565da9514d102b10d9078ebb618116d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps.sh
+++ /dev/null
@@ -1,174 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Mentor Graphics Questa Advanced Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'scalp_zynqps.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- compile
- elaborate
- simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
- # Compile design files
- source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <elaborate>
-elaborate()
-{
- source elaborate.do 2>&1 | tee -a elaborate.log
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
- vsim -64 -c -do "do {simulate.do}" -l simulate.log
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
- copy_setup_file $2
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- copy_setup_file $2
- esac
-
- create_lib_dir
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Copy modelsim.ini file
-copy_setup_file()
-{
- file="modelsim.ini"
- if [[ ($1 != "") ]]; then
- lib_map_path="$1"
- else
- lib_map_path="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/compile_simlib/questa"
- fi
- if [[ ($lib_map_path != "") ]]; then
- src_file="$lib_map_path/$file"
- cp $src_file .
- fi
-}
-
-# Create design library directory
-create_lib_dir()
-{
- lib_dir="questa_lib"
- if [[ -e $lib_dir ]]; then
- rm -rf $lib_dir
- fi
-
- mkdir $lib_dir
-
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-
- create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/questa/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/README.txt
deleted file mode 100644
index 00160c0b49260e1dec6b312a6f45263dd2685900..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/README.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/file_info.txt
deleted file mode 100644
index 2af2242e8d69103c35a06dc2273c4ab7ff829b79..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/file_info.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_gnd_constant_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/dc12/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_8,../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_processing_system7_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../../.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps.sh
deleted file mode 100755
index 0c47f84406bbab5f52dccdc175f3926f28e93ddf..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps.sh
+++ /dev/null
@@ -1,153 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Aldec Riviera-PRO Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'scalp_zynqps.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- compile
- simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
- # Compile design files
- source compile.do 2>&1 | tee -a compile.log
-
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
- runvsimsa -l simulate.log -do "do {simulate.do}"
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
- map_setup_file $2
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- map_setup_file $2
- esac
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Map library.cfg file
-map_setup_file()
-{
- file="library.cfg"
- if [[ ($1 != "") ]]; then
- lib_map_path="$1"
- else
- lib_map_path="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/compile_simlib/riviera"
- fi
- if [[ ($lib_map_path != "") ]]; then
- src_file="$lib_map_path/$file"
- if [[ -e $src_file ]]; then
- vmap -link $lib_map_path
- fi
- fi
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/riviera/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/README.txt
deleted file mode 100644
index 00160c0b49260e1dec6b312a6f45263dd2685900..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/README.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/file_info.txt
deleted file mode 100644
index dbced05951139a713133fb775e2d3f0f409fa75c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/file_info.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_gnd_constant_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/dc12/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_8,../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_processing_system7_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../../.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps.sh
deleted file mode 100755
index 1b1eb0dc6c385622de1bb3d1072bdfd8b6677f70..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps.sh
+++ /dev/null
@@ -1,267 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Synopsys Verilog Compiler Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'scalp_zynqps.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-# Directory path for design sources and include directories (if any) wrt this path
-ref_dir="."
-
-# Override directory with 'export_sim_ref_dir' env path value if set in the shell
-if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
- ref_dir="$export_sim_ref_dir"
-fi
-
-# Command line options
-vlogan_opts="-full64"
-vhdlan_opts="-full64"
-vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
-vcs_sim_opts="-ucli -licqueue -l simulate.log"
-
-# Design libraries
-design_libs=(xilinx_vip xlconstant_v1_1_6 xil_defaultlib axi_infrastructure_v1_1_0 axi_vip_v1_1_6 processing_system7_vip_v1_0_8 util_vector_logic_v2_0_1)
-
-# Simulation root library directory
-sim_lib_dir="vcs_lib"
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- compile
- elaborate
- simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
- # Compile design files
- vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
- "/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work xlconstant_v1_1_6 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work axi_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work axi_vip_v1_1_6 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/dc12/hdl/axi_vip_v1_1_vl_rfs.sv" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work processing_system7_vip_v1_0_8 $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work util_vector_logic_v2_0_1 $vlogan_opts +v2k +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v" \
- 2>&1 | tee -a vlogan.log
-
- vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v" \
- 2>&1 | tee -a vlogan.log
-
- vhdlan -work xil_defaultlib $vhdlan_opts \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd" \
- "$ref_dir/../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd" \
- 2>&1 | tee -a vhdlan.log
-
-
- vlogan -work xil_defaultlib $vlogan_opts +v2k \
- glbl.v \
- 2>&1 | tee -a vlogan.log
-
-}
-
-# RUN_STEP: <elaborate>
-elaborate()
-{
- vcs $vcs_elab_opts xil_defaultlib.scalp_zynqps xil_defaultlib.glbl -o scalp_zynqps_simv
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
- ./scalp_zynqps_simv $vcs_sim_opts -do simulate.do
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
- create_lib_mappings $2
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- create_lib_mappings $2
- esac
-
- create_lib_dir
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Define design library mappings
-create_lib_mappings()
-{
- file="synopsys_sim.setup"
- if [[ -e $file ]]; then
- if [[ ($1 == "") ]]; then
- return
- else
- rm -rf $file
- fi
- fi
-
- touch $file
-
- if [[ ($1 != "") ]]; then
- lib_map_path="$1"
- else
- lib_map_path="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/compile_simlib/vcs"
- fi
-
- for (( i=0; i<${#design_libs[*]}; i++ )); do
- lib="${design_libs[i]}"
- mapping="$lib:$sim_lib_dir/$lib"
- echo $mapping >> $file
- done
-
- if [[ ($lib_map_path != "") ]]; then
- incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
- echo $incl_ref >> $file
- fi
-}
-
-# Create design library directory paths
-create_lib_dir()
-{
- if [[ -e $sim_lib_dir ]]; then
- rm -rf $sim_lib_dir
- fi
-
- for (( i=0; i<${#design_libs[*]}; i++ )); do
- lib="${design_libs[i]}"
- lib_dir="$sim_lib_dir/$lib"
- if [[ ! -e $lib_dir ]]; then
- mkdir -p $lib_dir
- fi
- done
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(ucli.key scalp_zynqps_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc scalp_zynqps_simv.daidir)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-
- create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/vcs/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/README.txt
deleted file mode 100644
index 5029d3619b7761e164bcf336bcb025889403889a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/README.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'execute' function for the single-step flow. This
-function is called from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/file_info.txt
deleted file mode 100644
index dbced05951139a713133fb775e2d3f0f409fa75c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/file_info.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../../../../../../../../opt/Xilinx/Vivado/2019.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-xlconstant_v1_1_vl_rfs.v,verilog,xlconstant_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_gnd_constant_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_6,../../../../../.scripts/scalp_zynqps/ipshared/dc12/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_8,../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_processing_system7_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-util_vector_logic_v2_0_vl_rfs.v,verilog,util_vector_logic_v2_0_1,../../../../../.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps.sh
deleted file mode 100755
index c84ca0819be028a2d97dc1948851c3ff1fb1bffa..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps.sh
+++ /dev/null
@@ -1,184 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Cadence Xcelium Parallel Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
-# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
-# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
-# that points to these libraries and rerun export_simulation. For more information about this switch please
-# type 'export_simulation -help' in the Tcl shell.
-#
-# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
-# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'scalp_zynqps.sh -help' for more information.
-#
-# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
-#
-#*********************************************************************************************************
-
-# Directory path for design sources and include directories (if any) wrt this path
-ref_dir="."
-
-# Override directory with 'export_sim_ref_dir' env path value if set in the shell
-if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
- ref_dir="$export_sim_ref_dir"
-fi
-
-# Set the compiled library directory
-ref_lib_dir="."
-
-# Command line options
-xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
-
-# Design libraries
-design_libs=(xilinx_vip xlconstant_v1_1_6 xil_defaultlib axi_infrastructure_v1_1_0 axi_vip_v1_1_6 processing_system7_vip_v1_0_8 util_vector_logic_v2_0_1)
-
-# Simulation root library directory
-sim_lib_dir="xcelium_lib"
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- execute
-}
-
-# RUN_STEP: <execute>
-execute()
-{
- xrun $xrun_opts \
- -reflib "$ref_lib_dir/unisim:unisim" \
- -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
- -reflib "$ref_lib_dir/secureip:secureip" \
- -reflib "$ref_lib_dir/unimacro:unimacro" \
- -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
- -top xil_defaultlib.scalp_zynqps \
- -f run.f \
- -top glbl \
- glbl.v \
- +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" \
- +incdir+"$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" \
- +incdir+"../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" \
- +incdir+"/opt/Xilinx/Vivado/2019.2/data/xilinx_vip/include"
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- else
- ref_lib_dir=$2
- fi
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- esac
-
- create_lib_dir
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Create design library directory paths
-create_lib_dir()
-{
- if [[ -e $sim_lib_dir ]]; then
- rm -rf $sim_lib_dir
- fi
-
- for (( i=0; i<${#design_libs[*]}; i++ )); do
- lib="${design_libs[i]}"
- lib_dir="$sim_lib_dir/$lib"
- if [[ ! -e $lib_dir ]]; then
- mkdir -p $lib_dir
- fi
- done
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-
- create_lib_dir
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xcelium/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/README.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/README.txt
deleted file mode 100644
index 00160c0b49260e1dec6b312a6f45263dd2685900..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/README.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-################################################################################
-# Vivado (TM) v2019.2 (64-bit)
-#
-# README.txt: Please read the sections below to understand the steps required to
-# run the exported script and information about the source files.
-#
-# Generated by export_simulation on Mon Sep 07 11:53:40 CEST 2020
-#
-################################################################################
-
-1. How to run the generated simulation script:-
-
-From the shell prompt in the current directory, issue the following command:-
-
-./scalp_zynqps.sh
-
-This command will launch the 'compile', 'elaborate' and 'simulate' functions
-implemented in the script file for the 3-step flow. These functions are called
-from the main 'run' function in the script file.
-
-The 'run' function first executes the 'setup' function, the purpose of which is to
-create simulator specific setup files, create design library mappings and library
-directories and copy 'glbl.v' from the Vivado software install location into the
-current directory.
-
-The 'setup' function is also used for removing the simulator generated data in
-order to reset the current directory to the original state when export_simulation
-was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './scalp_zynqps.sh' script.
-
-./scalp_zynqps.sh -reset_run
-
-To keep the generated data from the previous run but regenerate the setup files and
-library directories, use the '-noclean_files' switch.
-
-./scalp_zynqps.sh -noclean_files
-
-For more information on the script, please type './scalp_zynqps.sh -help'.
-
-2. Additional design information files:-
-
-export_simulation generates following additional file that can be used for fetching
-the design files information or for integrating with external custom scripts.
-
-Name : file_info.txt
-Purpose: This file contains detail design file information based on the compile order
- when export_simulation was executed from Vivado. The file contains information
- about the file type, name, whether it is part of the IP, associated library
- and the file path information.
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/b_transport_converter.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/b_transport_converter.h
deleted file mode 100755
index 10539ef357b5066ec901f6805154d1e08933561d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/b_transport_converter.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// (c) Copyright(C) 2013 - 2018 by Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-
-#ifndef _B_TRANSPORT_CONVERTER_H_
-#define _B_TRANSPORT_CONVERTER_H_
-
-#include <systemc>
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include <utility>
-#include <vector>
-
-template<int IN_WIDTH, int OUT_WIDTH>
-class b_transport_converter: public sc_core::sc_module
-{
- enum TLM_IF_TYPE
- {
- B_TRANSPORT = 0,
- NB_TRANSPORT,
- TRANSPORT_DBG,
- DMI_IF,
- INVALID_IF
- };
- typedef std::vector<std::pair<sc_dt::uint64, sc_dt::uint64>> addr_range_list;
-
- public:
- SC_HAS_PROCESS(b_transport_converter);
- b_transport_converter<IN_WIDTH, OUT_WIDTH>(sc_core::sc_module_name name):
- sc_module(name)
- {
- target_socket.register_b_transport(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::b_transport);
- initiator_socket.register_nb_transport_bw(
- this, &b_transport_converter<IN_WIDTH, OUT_WIDTH>::nb_transport_bw);
-
- }
-
- //simple tlm target/initiator socket...
- tlm_utils::simple_target_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, IN_WIDTH> target_socket;
- tlm_utils::simple_initiator_socket<b_transport_converter<IN_WIDTH, OUT_WIDTH>, OUT_WIDTH> initiator_socket;
-
-
- public:
- void b_transport(tlm::tlm_generic_payload& payload, sc_core::sc_time& time)
- {
- tlm::tlm_phase phase = tlm::BEGIN_REQ; //for nb_transport_fw
- switch(get_tlm_if_type(payload.get_address()))
- {
- case B_TRANSPORT:
- initiator_socket->b_transport(payload, time);
- break;
-
- case NB_TRANSPORT:
- initiator_socket->nb_transport_fw(payload, phase, time);
- wait(resp_complete_event); //! Wait for the response to complete
- break;
-
- case TRANSPORT_DBG:
- initiator_socket->transport_dbg(payload);
- break;
-
- case DMI_IF:
- break;
-
- default:
- SC_REPORT_ERROR(this->name(), "Address not mapped to any of the TLM IF type");
- }
- }
-
- tlm::tlm_sync_enum
- nb_transport_bw(tlm::tlm_generic_payload& payload,
- tlm::tlm_phase& phase, sc_core::sc_time& time)
- {
- if(phase == tlm::BEGIN_RESP) {
- resp_complete_event.notify();
- phase = tlm::END_RESP;
- return tlm::TLM_UPDATED;
- }
- return tlm::TLM_ACCEPTED;
- }
-
- private:
- TLM_IF_TYPE get_tlm_if_type(unsigned long long address)
- {
- //check for b_transport addresses
- for(auto& addr_range: m_b_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return B_TRANSPORT;
- }
- }
-
- //check for nb_transport addresses
- for(auto& addr_range: m_nb_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return NB_TRANSPORT;
- }
- }
- //check for dbg_transport addresses
- for(auto& addr_range: m_dbg_transport_addr_list) {
- if(address >= addr_range.first && address < addr_range.second) {
- return TRANSPORT_DBG;
- }
- }
-
- //By default return NB_TRANSPORT
- return NB_TRANSPORT;
- }
-
- //Start and End Address List for each of interfaces...
- static addr_range_list m_b_transport_addr_list;
- static addr_range_list m_nb_transport_addr_list;
- static addr_range_list m_dbg_transport_addr_list;
-
- //event to notify completion of transaction
- sc_core::sc_event resp_complete_event;
-};
-
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_b_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_nb_transport_addr_list = {std::make_pair(0, 0)};
-template<int IN_WIDTH, int OUT_WIDTH>
-typename b_transport_converter<IN_WIDTH,OUT_WIDTH>::addr_range_list b_transport_converter<IN_WIDTH,OUT_WIDTH>::m_dbg_transport_addr_list = {std::make_pair(0, 0)};
-
-
-#endif /* _B_TRANSPORT_CONVERTER_H_ */
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/cmd.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/cmd.tcl
deleted file mode 100644
index eef7a0f0f87e4717b7640d1bdeafaaec5afd9048..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/cmd.tcl
+++ /dev/null
@@ -1,12 +0,0 @@
-set curr_wave [current_wave_config]
-if { [string length $curr_wave] == 0 } {
- if { [llength [get_objects]] > 0} {
- add_wave /
- set_property needs_save false [current_wave_config]
- } else {
- send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
- }
-}
-
-run -all
-quit
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/file_info.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/file_info.txt
deleted file mode 100644
index 2c975a3ed8b2d6ea612ea5da2e195ebd022b81a4..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/file_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-scalp_zynqps_gnd_constant_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_processing_system7_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_0_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_util_vector_logic_1_0.v,verilog,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps_vio_0_0.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-scalp_zynqps.vhd,vhdl,xil_defaultlib,../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd,incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="$ref_dir/../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl"incdir="../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl"incdir="../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0"incdir="../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog"incdir="../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl"
-glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/glbl.v b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/glbl.v
deleted file mode 100644
index be6423350a1b441d65c2ad7bf71b300b20dc7026..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/glbl.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
-`ifndef GLBL
-`define GLBL
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
-//-------- STARTUP Globals --------------
- wire GSR;
- wire GTS;
- wire GWE;
- wire PRLD;
- tri1 p_up_tmp;
- tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
-
- wire PROGB_GLBL;
- wire CCLKO_GLBL;
- wire FCSBO_GLBL;
- wire [3:0] DO_GLBL;
- wire [3:0] DI_GLBL;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
- reg JTAG_RUNTEST_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (strong1, weak0) GSR = GSR_int;
- assign (strong1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-`endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/processing_system7_v5_5_tlm.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/processing_system7_v5_5_tlm.h
deleted file mode 100755
index bdf5c50ce1462e7d10c19798a900b17632d55f7a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/processing_system7_v5_5_tlm.h
+++ /dev/null
@@ -1,232 +0,0 @@
-
-
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
-// IP Revision: 1
-#ifndef __PS7_H__
-#define __PS7_H__
-
-#include "systemc.h"
-#include "xtlm.h"
-#include "xtlm_adaptors/xaximm_xtlm2tlm.h"
-#include "xtlm_adaptors/xaximm_tlm2xtlm.h"
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "genattr.h"
-#include "xilinx-zynq.h"
-#include "b_transport_converter.h"
-
-/***************************************************************************************
-*
-* A Simple Converter which converts Remote-port's simplae_intiator_sockets<32>->b_transport()
-* calls to xTLM sockets bn_transport_x() calls..
-*
-* This is Only specific to remote-port so not creating seperate header for it.
-*
-***************************************************************************************/
-template <int IN_WIDTH, int OUT_WIDTH>
-class rptlm2xtlm_converter : public sc_module{
- public:
- tlm::tlm_target_socket<IN_WIDTH> target_socket;
- xtlm::xtlm_aximm_initiator_socket wr_socket;
- xtlm::xtlm_aximm_initiator_socket rd_socket;
- rptlm2xtlm_converter<IN_WIDTH, OUT_WIDTH>(sc_module_name name);//:sc_module(name)
- void registerUserExtensionHandlerCallback(
- void (*callback)(xtlm::aximm_payload*,
- const tlm::tlm_generic_payload*));
-
- private:
- b_transport_converter<IN_WIDTH, OUT_WIDTH> m_btrans_conv;
- xtlm::xaximm_tlm2xtlm_t<OUT_WIDTH> xtlm_bridge;
-};
-
-/***************************************************************************************
-* Global method, get registered with tlm2xtlm bridge
-* This function is called when tlm2xtlm bridge convert tlm payload to xtlm payload.
-*
-* caller: tlm2xtlm bridge
-* purpose: To get master id and other parameters out of genattr_extension
-* and use master id to AxUSER PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void get_extensions_from_tlm(xtlm::aximm_payload* xtlm_pay, const tlm::tlm_generic_payload* gp);
-
-/***************************************************************************************
-* Global method, get registered with xtlm2tlm bridge
-* This function is called when xtlm2tlm bridge convert xtlm payload to tlm payload.
-*
-* caller: xtlm2tlm bridge
-* purpose: To create and add master id and other parameters to genattr_extension.
-* Master id red from AxID PIN of xtlm payload.
-*
-*
-***************************************************************************************/
-extern void add_extensions_to_tlm(const xtlm::aximm_payload* xtlm_pay, tlm::tlm_generic_payload* gp);
-
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-// //
-// File: processing_system7_tlm.h //
-// //
-// Description: zynq_ultra_ps_e_tlm class is a sc_module, act as intermediate layer between //
-// xilinx_zynq qemu wrapper and Vivado generated systemc simulation ip wrapper. //
-// it's basically created for supporting tlm based xilinx_zynq from xtlm based vivado //
-// generated systemc wrapper. this wrapper is live only when SELECTED_SIM_MODEL is set //
-// to tlm. it's also act as bridge between vivado wrapper and xilinx_zynq wrapper. //
-// it fill the the gap between input/output ports of vivado generated wrapper to //
-// xilinx_zynq wrapper signals. This wrapper is auto generated by ttcl scripts //
-// based on IP configuration in vivado. //
-// //
-// //
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-class processing_system7_v5_5_tlm : public sc_core::sc_module {
-
- public:
- // Non-AXI ports are declared here
- sc_core::sc_in<bool> SPI1_SCLK_I;
- sc_core::sc_out<bool> SPI1_SCLK_O;
- sc_core::sc_out<bool> SPI1_SCLK_T;
- sc_core::sc_in<bool> SPI1_MOSI_I;
- sc_core::sc_out<bool> SPI1_MOSI_O;
- sc_core::sc_out<bool> SPI1_MOSI_T;
- sc_core::sc_in<bool> SPI1_MISO_I;
- sc_core::sc_out<bool> SPI1_MISO_O;
- sc_core::sc_out<bool> SPI1_MISO_T;
- sc_core::sc_in<bool> SPI1_SS_I;
- sc_core::sc_out<bool> SPI1_SS_O;
- sc_core::sc_out<bool> SPI1_SS1_O;
- sc_core::sc_out<bool> SPI1_SS2_O;
- sc_core::sc_out<bool> SPI1_SS_T;
- sc_core::sc_out<sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out<bool> USB0_VBUS_PWRSELECT;
- sc_core::sc_in<bool> USB0_VBUS_PWRFAULT;
- sc_core::sc_in<bool> M_AXI_GP0_ACLK;
- sc_core::sc_out<bool> FCLK_CLK0;
- sc_core::sc_out<bool> FCLK_RESET0_N;
- sc_core::sc_inout<sc_dt::sc_bv<54> > MIO;
- sc_core::sc_inout<bool> DDR_CAS_n;
- sc_core::sc_inout<bool> DDR_CKE;
- sc_core::sc_inout<bool> DDR_Clk_n;
- sc_core::sc_inout<bool> DDR_Clk;
- sc_core::sc_inout<bool> DDR_CS_n;
- sc_core::sc_inout<bool> DDR_DRSTB;
- sc_core::sc_inout<bool> DDR_ODT;
- sc_core::sc_inout<bool> DDR_RAS_n;
- sc_core::sc_inout<bool> DDR_WEB;
- sc_core::sc_inout<sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_inout<sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_inout<bool> DDR_VRN;
- sc_core::sc_inout<bool> DDR_VRP;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_inout<sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_inout<sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_inout<bool> PS_SRSTB;
- sc_core::sc_inout<bool> PS_CLK;
- sc_core::sc_inout<bool> PS_PORB;
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
-
- //constructor having three paramters
- // 1. module name in sc_module_name objec,
- // 2. reference to map object of name and integer value pairs
- // 3. reference to map object of name and string value pairs
- // All the model parameters (integer and string) which are configuration parameters
- // of Processing System 7 IP propogated from Vivado
-processing_system7_v5_5_tlm(sc_core::sc_module_name name,
- xsc::common_cpp::properties&);
-
- ~processing_system7_v5_5_tlm();
- SC_HAS_PROCESS(processing_system7_v5_5_tlm);
-
- private:
-
- //zynq tlm wrapper provided by Edgar
- //module with interfaces of standard tlm
- //and input/output ports at signal level
- xilinx_zynq* m_zynq_tlm_model;
-
- // Xtlm2tlm_t Bridges
- // Converts Xtlm transactions to tlm transactions
- // Bridge's Xtlm wr/rd target sockets binds with
- // xtlm initiator sockets of processing_system7_tlm and tlm simple initiator
- // socket with xilinx_zynq's target socket
-
- // This Bridges converts b_transport to nb_transports and also
- // Converts tlm transactions to xtlm transactions.
- // Bridge's tlm simple target socket binds with
- // simple initiator socket of xilinx_zynqmp and xtlm
- // socket with xilinx_zynq's simple target socket
- rptlm2xtlm_converter<32, 32> m_rp_bridge_M_AXI_GP0;
-
- // sc_clocks for generating pl clocks
- // output pins FCLK_CLK0..3 are drived by these clocks
- sc_core::sc_clock FCLK_CLK0_clk;
-
-
- //Method which is sentive to FCLK_CLK0_clk sc_clock object
- //FCLK_CLK0 pin written based on FCLK_CLK0_clk clock value
- void trigger_FCLK_CLK0_pin();
-
- //FCLK_RESET0 output reset pin get toggle when emio bank 2's 31th signal gets toggled
- //EMIO[2] bank 31th(GPIO[95] signal)acts as reset signal to the PL(refer Zynq UltraScale+ TRM, page no:761)
- void FCLK_RESET0_N_trigger();
-
- sc_signal<bool> qemu_rst;
- void start_of_simulation();
-
- xsc::common_cpp::properties prop;
-
-};
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/ps7_init.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/ps7_init.tcl
deleted file mode 100755
index 304b14b49345ca0f3eb3ec48ecb76becb8313ca7..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/ps7_init.tcl
+++ /dev/null
@@ -1,835 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x0007FFFF 0x00001079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0x7FDFFFFC 0x270872B0
- mask_write 0XF8006024 0x0FFFFFC3 0x00000000
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00000003 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x0003F03F 0x0003C008
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x00010000 0x00000000
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x00000200 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFCF 0x40000001
- mask_write 0XF800611C 0x7FFFFFCF 0x40000001
- mask_write 0XF8006120 0x7FFFFFCF 0x40000000
- mask_write 0XF8006124 0x7FFFFFCF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0x6FFFFEFE 0x00040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000703FF 0x000003FF
- mask_write 0XF800620C 0x000703FF 0x000003FF
- mask_write 0XF8006210 0x000703FF 0x000003FF
- mask_write 0XF8006214 0x000703FF 0x000003FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF5 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000001 0x00000001
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FEFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x000003FF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x000003FF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF8006078 0x03FFFFFF 0x00455111
- mask_write 0XF800607C 0x000FFFFF 0x00032222
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x00007FFF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000110 0x003FFFF0 0x001452C0
- mask_write 0XF8000100 0x0007F000 0x0001E000
- mask_write 0XF8000100 0x00000010 0x00000010
- mask_write 0XF8000100 0x00000001 0x00000001
- mask_write 0XF8000100 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000001
- mask_write 0XF8000100 0x00000010 0x00000000
- mask_write 0XF8000120 0x1F003F30 0x1F000200
- mask_write 0XF8000114 0x003FFFF0 0x001F42C0
- mask_write 0XF8000104 0x0007F000 0x00014000
- mask_write 0XF8000104 0x00000010 0x00000010
- mask_write 0XF8000104 0x00000001 0x00000001
- mask_write 0XF8000104 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000002
- mask_write 0XF8000104 0x00000010 0x00000000
- mask_write 0XF8000124 0xFFF00003 0x0C200003
- mask_write 0XF8000118 0x003FFFF0 0x00113220
- mask_write 0XF8000108 0x0007F000 0x00023000
- mask_write 0XF8000108 0x00000010 0x00000010
- mask_write 0XF8000108 0x00000001 0x00000001
- mask_write 0XF8000108 0x00000001 0x00000000
- mask_poll 0XF800010C 0x00000004
- mask_write 0XF8000108 0x00000010 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000128 0x03F03F01 0x00203101
- mask_write 0XF8000138 0x00000011 0x00000001
- mask_write 0XF8000140 0x03F03F71 0x00100E01
- mask_write 0XF800014C 0x00003F31 0x00000D01
- mask_write 0XF8000150 0x00003F33 0x00001202
- mask_write 0XF8000154 0x00003F33 0x00001203
- mask_write 0XF8000158 0x00003F33 0x00000B03
- mask_write 0XF800015C 0x03F03F33 0x00101202
- mask_write 0XF8000160 0x007F007F 0x00000000
- mask_write 0XF8000168 0x00003F31 0x00000901
- mask_write 0XF8000170 0x03F03F30 0x00200700
- mask_write 0XF80001C4 0x00000001 0x00000001
- mask_write 0XF800012C 0x01FFCCCD 0x01FEC84D
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
- mask_write 0XF8006000 0x0001FFFF 0x00000084
- mask_write 0XF8006004 0x1FFFFFFF 0x00081079
- mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
- mask_write 0XF800600C 0x03FFFFFF 0x02001001
- mask_write 0XF8006010 0x03FFFFFF 0x00014001
- mask_write 0XF8006014 0x001FFFFF 0x00041419
- mask_write 0XF8006018 0xF7FFFFFF 0x44A250D2
- mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
- mask_write 0XF8006020 0xFFFFFFFC 0x272872B0
- mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
- mask_write 0XF8006028 0x00003FFF 0x00002007
- mask_write 0XF800602C 0xFFFFFFFF 0x00000008
- mask_write 0XF8006030 0xFFFFFFFF 0x00040930
- mask_write 0XF8006034 0x13FF3FFF 0x00011564
- mask_write 0XF8006038 0x00001FC3 0x00000000
- mask_write 0XF800603C 0x000FFFFF 0x00000666
- mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
- mask_write 0XF8006044 0x0FFFFFFF 0x0FF55555
- mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
- mask_write 0XF8006050 0xFF0F8FFF 0x77010800
- mask_write 0XF8006058 0x0001FFFF 0x00000101
- mask_write 0XF800605C 0x0000FFFF 0x00005003
- mask_write 0XF8006060 0x000017FF 0x0000003E
- mask_write 0XF8006064 0x00021FE0 0x00020000
- mask_write 0XF8006068 0x03FFFFFF 0x00284141
- mask_write 0XF800606C 0x0000FFFF 0x00001610
- mask_write 0XF80060A0 0x00FFFFFF 0x00008000
- mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
- mask_write 0XF80060A8 0x0FFFFFFF 0x0620BEBC
- mask_write 0XF80060AC 0x000001FF 0x000001EA
- mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
- mask_write 0XF80060B4 0x000007FF 0x00000200
- mask_write 0XF80060B8 0x01FFFFFF 0x00200066
- mask_write 0XF80060C4 0x00000003 0x00000000
- mask_write 0XF80060C8 0x000000FF 0x00000000
- mask_write 0XF80060DC 0x00000001 0x00000000
- mask_write 0XF80060F0 0x0000FFFF 0x00000000
- mask_write 0XF80060F4 0x0000000F 0x00000008
- mask_write 0XF8006114 0x000000FF 0x00000000
- mask_write 0XF8006118 0x7FFFFFFF 0x40000001
- mask_write 0XF800611C 0x7FFFFFFF 0x40000001
- mask_write 0XF8006120 0x7FFFFFFF 0x40000000
- mask_write 0XF8006124 0x7FFFFFFF 0x40000000
- mask_write 0XF800612C 0x000FFFFF 0x00028000
- mask_write 0XF8006130 0x000FFFFF 0x00028000
- mask_write 0XF8006134 0x000FFFFF 0x00028000
- mask_write 0XF8006138 0x000FFFFF 0x00028000
- mask_write 0XF8006140 0x000FFFFF 0x00000035
- mask_write 0XF8006144 0x000FFFFF 0x00000035
- mask_write 0XF8006148 0x000FFFFF 0x00000035
- mask_write 0XF800614C 0x000FFFFF 0x00000035
- mask_write 0XF8006154 0x000FFFFF 0x00000080
- mask_write 0XF8006158 0x000FFFFF 0x00000080
- mask_write 0XF800615C 0x000FFFFF 0x00000080
- mask_write 0XF8006160 0x000FFFFF 0x00000080
- mask_write 0XF8006168 0x001FFFFF 0x000000F5
- mask_write 0XF800616C 0x001FFFFF 0x000000F5
- mask_write 0XF8006170 0x001FFFFF 0x000000F5
- mask_write 0XF8006174 0x001FFFFF 0x000000F5
- mask_write 0XF800617C 0x000FFFFF 0x000000C0
- mask_write 0XF8006180 0x000FFFFF 0x000000C0
- mask_write 0XF8006184 0x000FFFFF 0x000000C0
- mask_write 0XF8006188 0x000FFFFF 0x000000C0
- mask_write 0XF8006190 0xFFFFFFFF 0x10040080
- mask_write 0XF8006194 0x000FFFFF 0x0001FC82
- mask_write 0XF8006204 0xFFFFFFFF 0x00000000
- mask_write 0XF8006208 0x000F03FF 0x000803FF
- mask_write 0XF800620C 0x000F03FF 0x000803FF
- mask_write 0XF8006210 0x000F03FF 0x000803FF
- mask_write 0XF8006214 0x000F03FF 0x000803FF
- mask_write 0XF8006218 0x000F03FF 0x000003FF
- mask_write 0XF800621C 0x000F03FF 0x000003FF
- mask_write 0XF8006220 0x000F03FF 0x000003FF
- mask_write 0XF8006224 0x000F03FF 0x000003FF
- mask_write 0XF80062A8 0x00000FF7 0x00000000
- mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
- mask_write 0XF80062B0 0x003FFFFF 0x00005115
- mask_write 0XF80062B4 0x0003FFFF 0x0000119E
- mask_poll 0XF8000B74 0x00002000
- mask_write 0XF8006000 0x0001FFFF 0x00000085
- mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B40 0x00000FFF 0x00000600
- mask_write 0XF8000B44 0x00000FFF 0x00000600
- mask_write 0XF8000B48 0x00000FFF 0x00000672
- mask_write 0XF8000B4C 0x00000FFF 0x00000800
- mask_write 0XF8000B50 0x00000FFF 0x00000674
- mask_write 0XF8000B54 0x00000FFF 0x00000800
- mask_write 0XF8000B58 0x00000FFF 0x00000600
- mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
- mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068
- mask_write 0XF8000B6C 0x000073FF 0x00000220
- mask_write 0XF8000B70 0x00000021 0x00000021
- mask_write 0XF8000B70 0x00000021 0x00000020
- mask_write 0XF8000B70 0x07FFFFFF 0x00000823
- mask_write 0XF8000700 0x00003FFF 0x00001600
- mask_write 0XF8000704 0x00003FFF 0x00001602
- mask_write 0XF8000708 0x00003FFF 0x00000602
- mask_write 0XF800070C 0x00003FFF 0x00000602
- mask_write 0XF8000710 0x00003FFF 0x00000602
- mask_write 0XF8000714 0x00003FFF 0x00000602
- mask_write 0XF8000718 0x00003FFF 0x00000602
- mask_write 0XF800071C 0x00003FFF 0x00000600
- mask_write 0XF8000720 0x00003FFF 0x00000600
- mask_write 0XF8000724 0x00003F01 0x00001601
- mask_write 0XF8000728 0x00003FFF 0x00001680
- mask_write 0XF800072C 0x00003FFF 0x00001680
- mask_write 0XF8000730 0x00003FFF 0x00001680
- mask_write 0XF8000734 0x00003FFF 0x00001680
- mask_write 0XF8000738 0x00003FFF 0x00001680
- mask_write 0XF800073C 0x00003FFF 0x00001680
- mask_write 0XF8000740 0x00003FFF 0x00001402
- mask_write 0XF8000744 0x00003FFF 0x00001402
- mask_write 0XF8000748 0x00003FFF 0x00001402
- mask_write 0XF800074C 0x00003FFF 0x00001402
- mask_write 0XF8000750 0x00003FFF 0x00001402
- mask_write 0XF8000754 0x00003FFF 0x00001402
- mask_write 0XF8000758 0x00003FFF 0x00001403
- mask_write 0XF800075C 0x00003FFF 0x00001403
- mask_write 0XF8000760 0x00003FFF 0x00001403
- mask_write 0XF8000764 0x00003FFF 0x00001403
- mask_write 0XF8000768 0x00003FFF 0x00001403
- mask_write 0XF800076C 0x00003FFF 0x00001403
- mask_write 0XF8000770 0x00003FFF 0x00001404
- mask_write 0XF8000774 0x00003FFF 0x00001405
- mask_write 0XF8000778 0x00003FFF 0x00001404
- mask_write 0XF800077C 0x00003FFF 0x00001405
- mask_write 0XF8000780 0x00003FFF 0x00001404
- mask_write 0XF8000784 0x00003FFF 0x00001404
- mask_write 0XF8000788 0x00003FFF 0x00001404
- mask_write 0XF800078C 0x00003FFF 0x00001404
- mask_write 0XF8000790 0x00003FFF 0x00001405
- mask_write 0XF8000794 0x00003FFF 0x00001404
- mask_write 0XF8000798 0x00003FFF 0x00001404
- mask_write 0XF800079C 0x00003FFF 0x00001404
- mask_write 0XF80007A0 0x00003FFF 0x000014A0
- mask_write 0XF80007A4 0x00003FFF 0x000014A0
- mask_write 0XF80007A8 0x00003FFF 0x000014A0
- mask_write 0XF80007AC 0x00003FFF 0x00001400
- mask_write 0XF80007B0 0x00003FFF 0x00001400
- mask_write 0XF80007B4 0x00003FFF 0x000014A0
- mask_write 0XF80007B8 0x00003FFF 0x000014E1
- mask_write 0XF80007BC 0x00003FFF 0x000014E0
- mask_write 0XF80007C0 0x00003FFF 0x000014E0
- mask_write 0XF80007C4 0x00003FFF 0x000014E1
- mask_write 0XF80007C8 0x00003FFF 0x00001440
- mask_write 0XF80007CC 0x00003FFF 0x00001440
- mask_write 0XF80007D0 0x00003FFF 0x00001420
- mask_write 0XF80007D4 0x00003FFF 0x00001421
- mask_write 0XF8000834 0x003F003F 0x00090039
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000B48 0x00000180 0x00000180
- mask_write 0XF8000B4C 0x00000180 0x00000000
- mask_write 0XF8000B50 0x00000180 0x00000180
- mask_write 0XF8000B54 0x00000180 0x00000000
- mwr -force 0XF8000004 0x0000767B
- mask_write 0XE0001034 0x000000FF 0x00000006
- mask_write 0XE0001018 0x0000FFFF 0x0000007C
- mask_write 0XE0001000 0x000001FF 0x00000017
- mask_write 0XE0001004 0x00000FFF 0x00000020
- mask_write 0XE0000034 0x000000FF 0x00000006
- mask_write 0XE0000018 0x0000FFFF 0x0000007C
- mask_write 0XE0000000 0x000001FF 0x00000017
- mask_write 0XE0000004 0x00000FFF 0x00000020
- mask_write 0XE000D000 0x00080000 0x00080000
- mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
- mwr -force 0XF8000008 0x0000DF0D
- mask_write 0XF8000900 0x0000000F 0x0000000F
- mask_write 0XF8000240 0xFFFFFFFF 0x00000000
- mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
- mwr -force 0XF8898FB0 0xC5ACCE55
- mwr -force 0XF8899FB0 0xC5ACCE55
- mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ 750000000
-
-
-
-proc mask_poll { addr mask } {
- set count 1
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- while { $maskedval == 0 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval & $mask}]
- set count [ expr { $count + 1 } ]
- if { $count == 100000000 } {
- puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
- break
- }
- }
-}
-
-
-
-proc mask_delay { addr val } {
- set delay [ get_number_of_cycles_for_delay $val ]
- perf_reset_and_start_timer
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- while { $maskedval == 1 } {
- set curval "0x[string range [mrd $addr] end-8 end]"
- set maskedval [expr {$curval < $delay}]
- }
- perf_reset_clock
-}
-
-proc ps_version { } {
- set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
- set mask_sil_ver "0x[expr {$si_ver >> 28}]"
- return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
- set saved_mode [configparams force-mem-accesses]
- configparams force-mem-accesses 1
-
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_post_config_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_post_config_2_0
- } else {
- ps7_post_config_3_0
- }
- configparams force-mem-accesses $saved_mode
-}
-
-proc ps7_debug {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
-
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_debug_1_0
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_debug_2_0
- } else {
- ps7_debug_3_0
- }
-}
-proc ps7_init {} {
- variable PCW_SILICON_VER_1_0
- variable PCW_SILICON_VER_2_0
- variable PCW_SILICON_VER_3_0
- set sil_ver [ps_version]
- if { $sil_ver == $PCW_SILICON_VER_1_0} {
- ps7_mio_init_data_1_0
- ps7_pll_init_data_1_0
- ps7_clock_init_data_1_0
- ps7_ddr_init_data_1_0
- ps7_peripherals_init_data_1_0
- #puts "PCW Silicon Version : 1.0"
- } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
- ps7_mio_init_data_2_0
- ps7_pll_init_data_2_0
- ps7_clock_init_data_2_0
- ps7_ddr_init_data_2_0
- ps7_peripherals_init_data_2_0
- #puts "PCW Silicon Version : 2.0"
- } else {
- ps7_mio_init_data_3_0
- ps7_pll_init_data_3_0
- ps7_clock_init_data_3_0
- ps7_ddr_init_data_3_0
- ps7_peripherals_init_data_3_0
- #puts "PCW Silicon Version : 3.0"
- }
-}
-
-
-# For delay calculation using global timer
-
-# start timer
- proc perf_start_clock { } {
-
- #writing SCU_GLOBAL_TIMER_CONTROL register
-
- mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs
- proc perf_reset_clock { } {
- perf_disable_clock
- mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
- mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
- # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
- variable APU_FREQ
- return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer
-proc perf_disable_clock {} {
- mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
-}
-
-proc perf_reset_and_start_timer {} {
- perf_reset_clock
- perf_start_clock
-}
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps.sh
deleted file mode 100755
index c695c0ec8a322890c6d5ac4d58797291bf3c10aa..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps.sh
+++ /dev/null
@@ -1,214 +0,0 @@
-#!/bin/bash -f
-#*********************************************************************************************************
-# Vivado (TM) v2019.2 (64-bit)
-#
-# Filename : scalp_zynqps.sh
-# Simulator : Xilinx Vivado Simulator
-# Description : Simulation script for compiling, elaborating and verifying the project source files.
-# The script will automatically create the design libraries sub-directories in the run
-# directory, add the library logical mappings in the simulator setup file, create default
-# 'do/prj' file, execute compilation, elaboration and simulation steps.
-#
-# Generated by Vivado on Mon Sep 07 11:53:40 CEST 2020
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-#
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-# usage: scalp_zynqps.sh [-help]
-# usage: scalp_zynqps.sh [-lib_map_path]
-# usage: scalp_zynqps.sh [-noclean_files]
-# usage: scalp_zynqps.sh [-reset_run]
-#
-#*********************************************************************************************************
-
-# Command line options
-xv_boost_lib_path=/opt/Xilinx/Vivado/2019.2/tps/boost_1_64_0
-xvlog_opts="--relax -L axi_vip_v1_1_6 -L processing_system7_vip_v1_0_8 -L xilinx_vip"
-xvhdl_opts="--relax"
-
-
-# Script info
-echo -e "scalp_zynqps.sh - Script generated by export_simulation (Vivado v2019.2 (64-bit)-id)\n"
-
-# Main steps
-run()
-{
- check_args $# $1
- setup $1 $2
- compile
- elaborate
- simulate
-}
-
-# RUN_STEP: <compile>
-compile()
-{
- # Compile design files
- xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
- xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
-
-}
-
-# RUN_STEP: <elaborate>
-elaborate()
-{
- xelab --relax --debug typical --mt auto -L xlconstant_v1_1_6 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_6 -L processing_system7_vip_v1_0_8 -L util_vector_logic_v2_0_1 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot scalp_zynqps xil_defaultlib.scalp_zynqps xil_defaultlib.glbl -log elaborate.log
-}
-
-# RUN_STEP: <simulate>
-simulate()
-{
- xsim scalp_zynqps -key {Behavioral:sim_1:Functional:scalp_zynqps} -tclbatch cmd.tcl -protoinst "protoinst_files/scalp_zynqps.protoinst" -log simulate.log
-}
-
-# STEP: setup
-setup()
-{
- case $1 in
- "-lib_map_path" )
- if [[ ($2 == "") ]]; then
- echo -e "ERROR: Simulation library directory path not specified (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
- copy_setup_file $2
- ;;
- "-reset_run" )
- reset_run
- echo -e "INFO: Simulation run files deleted.\n"
- exit 0
- ;;
- "-noclean_files" )
- # do not remove previous data
- ;;
- * )
- copy_setup_file $2
- esac
-
- # Add any setup/initialization commands here:-
-
- # <user specific commands>
-
-}
-
-# Copy xsim.ini file
-copy_setup_file()
-{
- file="xsim.ini"
- lib_map_path="/opt/Xilinx/Vivado/2019.2/data/xsim"
- if [[ ($1 != "") ]]; then
- lib_map_path="$1"
- fi
- if [[ ($lib_map_path != "") ]]; then
- src_file="$lib_map_path/$file"
- if [[ -e $src_file ]]; then
- cp $src_file .
- fi
-
- # Map local design libraries to xsim.ini
- map_local_libs
-
- fi
-}
-
-# Map local design libraries
-map_local_libs()
-{
- updated_mappings=()
- local_mappings=()
-
- # Local design libraries
- local_libs=(xil_defaultlib)
-
- if [[ 0 == ${#local_libs[@]} ]]; then
- return
- fi
-
- file="xsim.ini"
- file_backup="xsim.ini.bak"
-
- if [[ -e $file ]]; then
- rm -f $file_backup
- # Create a backup copy of the xsim.ini file
- cp $file $file_backup
- # Read libraries from backup file and search in local library collection
- while read -r line
- do
- IN=$line
- # Split mapping entry with '=' delimiter to fetch library name and mapping
- read lib_name mapping <<<$(IFS="="; echo $IN)
- # If local library found, then construct the local mapping and add to local mapping collection
- if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
- line="$lib_name=xsim.dir/$lib_name"
- local_mappings+=("$lib_name")
- fi
- # Add to updated library mapping collection
- updated_mappings+=("$line")
- done < "$file_backup"
- # Append local libraries not found originally from xsim.ini
- for (( i=0; i<${#local_libs[*]}; i++ )); do
- lib_name="${local_libs[i]}"
- if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
- line="$lib_name=xsim.dir/$lib_name"
- updated_mappings+=("$line")
- fi
- done
- # Write updated mappings in xsim.ini
- rm -f $file
- for (( i=0; i<${#updated_mappings[*]}; i++ )); do
- lib_name="${updated_mappings[i]}"
- echo $lib_name >> $file
- done
- else
- for (( i=0; i<${#local_libs[*]}; i++ )); do
- lib_name="${local_libs[i]}"
- mapping="$lib_name=xsim.dir/$lib_name"
- echo $mapping >> $file
- done
- fi
-}
-
-# Delete generated data from the previous run
-reset_run()
-{
- files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb scalp_zynqps.wdb xsim.dir)
- for (( i=0; i<${#files_to_remove[*]}; i++ )); do
- file="${files_to_remove[i]}"
- if [[ -e $file ]]; then
- rm -rf $file
- fi
- done
-}
-
-# Check command line arguments
-check_args()
-{
- if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
- echo -e "ERROR: Unknown option specified '$2' (type \"./scalp_zynqps.sh -help\" for more information)\n"
- exit 1
- fi
-
- if [[ ($2 == "-help" || $2 == "-h") ]]; then
- usage
- fi
-}
-
-# Script usage
-usage()
-{
- msg="Usage: scalp_zynqps.sh [-help]\n\
-Usage: scalp_zynqps.sh [-lib_map_path]\n\
-Usage: scalp_zynqps.sh [-reset_run]\n\
-Usage: scalp_zynqps.sh [-noclean_files]\n\n\
-[-help] -- Print help information for this script\n\n\
-[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
-using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
-[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
-from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
--noclean_files switch.\n\n\
-[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
- echo -e $msg
- exit 1
-}
-
-# Launch script
-run $1 $2
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_gnd_constant_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_gnd_constant_0.h
deleted file mode 100755
index ed20803c3eb49565cc51eda2a909ec1da4515002..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_gnd_constant_0.h
+++ /dev/null
@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _scalp_zynqps_gnd_constant_0_H_
-#define _scalp_zynqps_gnd_constant_0_H_
-
-#include "xlconstant_v1_1_6.h"
-#include "systemc.h"
-class scalp_zynqps_gnd_constant_0 : public sc_module {
- public:
-xlconstant_v1_1_6<1,0> mod;
- sc_out< sc_bv<1> > dout;
-scalp_zynqps_gnd_constant_0 (sc_core::sc_module_name name) :sc_module(name), mod("mod") {
- mod.dout(dout);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_processing_system7_0_0.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_processing_system7_0_0.h
deleted file mode 100755
index 218c2a2ab3da876018e5a746f193b7291c16d1d0..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_processing_system7_0_0.h
+++ /dev/null
@@ -1,178 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-#include "scalp_zynqps_processing_system7_0_0_sc.h"
-
-class DllExport scalp_zynqps_processing_system7_0_0 : public scalp_zynqps_processing_system7_0_0_sc
-{
-public:
-
- scalp_zynqps_processing_system7_0_0(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0();
-
- // module pin-to-pin RTL interface
-
- sc_core::sc_in< bool > SPI1_SCLK_I;
- sc_core::sc_out< bool > SPI1_SCLK_O;
- sc_core::sc_out< bool > SPI1_SCLK_T;
- sc_core::sc_in< bool > SPI1_MOSI_I;
- sc_core::sc_out< bool > SPI1_MOSI_O;
- sc_core::sc_out< bool > SPI1_MOSI_T;
- sc_core::sc_in< bool > SPI1_MISO_I;
- sc_core::sc_out< bool > SPI1_MISO_O;
- sc_core::sc_out< bool > SPI1_MISO_T;
- sc_core::sc_in< bool > SPI1_SS_I;
- sc_core::sc_out< bool > SPI1_SS_O;
- sc_core::sc_out< bool > SPI1_SS1_O;
- sc_core::sc_out< bool > SPI1_SS2_O;
- sc_core::sc_out< bool > SPI1_SS_T;
- sc_core::sc_out< sc_dt::sc_bv<2> > USB0_PORT_INDCTL;
- sc_core::sc_out< bool > USB0_VBUS_PWRSELECT;
- sc_core::sc_in< bool > USB0_VBUS_PWRFAULT;
- sc_core::sc_out< bool > M_AXI_GP0_ARVALID;
- sc_core::sc_out< bool > M_AXI_GP0_AWVALID;
- sc_core::sc_out< bool > M_AXI_GP0_BREADY;
- sc_core::sc_out< bool > M_AXI_GP0_RREADY;
- sc_core::sc_out< bool > M_AXI_GP0_WLAST;
- sc_core::sc_out< bool > M_AXI_GP0_WVALID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_ARID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_AWID;
- sc_core::sc_out< sc_dt::sc_bv<12> > M_AXI_GP0_WID;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_ARLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARSIZE;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWBURST;
- sc_core::sc_out< sc_dt::sc_bv<2> > M_AXI_GP0_AWLOCK;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWSIZE;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_ARPROT;
- sc_core::sc_out< sc_dt::sc_bv<3> > M_AXI_GP0_AWPROT;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_ARADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_AWADDR;
- sc_core::sc_out< sc_dt::sc_bv<32> > M_AXI_GP0_WDATA;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_ARQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWCACHE;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWLEN;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_AWQOS;
- sc_core::sc_out< sc_dt::sc_bv<4> > M_AXI_GP0_WSTRB;
- sc_core::sc_in< bool > M_AXI_GP0_ACLK;
- sc_core::sc_in< bool > M_AXI_GP0_ARREADY;
- sc_core::sc_in< bool > M_AXI_GP0_AWREADY;
- sc_core::sc_in< bool > M_AXI_GP0_BVALID;
- sc_core::sc_in< bool > M_AXI_GP0_RLAST;
- sc_core::sc_in< bool > M_AXI_GP0_RVALID;
- sc_core::sc_in< bool > M_AXI_GP0_WREADY;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_BID;
- sc_core::sc_in< sc_dt::sc_bv<12> > M_AXI_GP0_RID;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_BRESP;
- sc_core::sc_in< sc_dt::sc_bv<2> > M_AXI_GP0_RRESP;
- sc_core::sc_in< sc_dt::sc_bv<32> > M_AXI_GP0_RDATA;
- sc_core::sc_out< bool > FCLK_CLK0;
- sc_core::sc_out< bool > FCLK_RESET0_N;
- sc_core::sc_out< sc_dt::sc_bv<54> > MIO;
- sc_core::sc_out< bool > DDR_CAS_n;
- sc_core::sc_out< bool > DDR_CKE;
- sc_core::sc_out< bool > DDR_Clk_n;
- sc_core::sc_out< bool > DDR_Clk;
- sc_core::sc_out< bool > DDR_CS_n;
- sc_core::sc_out< bool > DDR_DRSTB;
- sc_core::sc_out< bool > DDR_ODT;
- sc_core::sc_out< bool > DDR_RAS_n;
- sc_core::sc_out< bool > DDR_WEB;
- sc_core::sc_out< sc_dt::sc_bv<3> > DDR_BankAddr;
- sc_core::sc_out< sc_dt::sc_bv<15> > DDR_Addr;
- sc_core::sc_out< bool > DDR_VRN;
- sc_core::sc_out< bool > DDR_VRP;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DM;
- sc_core::sc_out< sc_dt::sc_bv<32> > DDR_DQ;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS_n;
- sc_core::sc_out< sc_dt::sc_bv<4> > DDR_DQS;
- sc_core::sc_out< bool > PS_SRSTB;
- sc_core::sc_out< bool > PS_CLK;
- sc_core::sc_out< bool > PS_PORB;
-
-protected:
-
- virtual void before_end_of_elaboration();
-
-private:
-
- xtlm::xaximm_xtlm2pin_t<32,32,12,1,1,1,1,1>* mp_M_AXI_GP0_transactor;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_ARLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_ARLOCK_converter_signal;
- xsc::common::scalar2vectorN_converter<2>* mp_M_AXI_GP0_AWLOCK_converter;
- sc_signal< bool > m_M_AXI_GP0_AWLOCK_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_ARLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_ARLEN_converter_signal;
- xsc::common::vector2vector_converter<8,4>* mp_M_AXI_GP0_AWLEN_converter;
- sc_signal< sc_bv<8> > m_M_AXI_GP0_AWLEN_converter_signal;
- sc_signal< bool > m_M_AXI_GP0_transactor_rst_signal;
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_processing_system7_0_0_sc.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_processing_system7_0_0_sc.h
deleted file mode 100755
index b41eca21fc87a6bfdd76a90e6f95a7491b0b9bdd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/scalp_zynqps_processing_system7_0_0_sc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-#ifndef IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-#define IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
-
-// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-#ifndef XTLM
-#include "xtlm.h"
-#endif
-
-#ifndef SYSTEMC_INCLUDED
-#include <systemc>
-#endif
-
-#if defined(_MSC_VER)
-#define DllExport __declspec(dllexport)
-#elif defined(__GNUC__)
-#define DllExport __attribute__ ((visibility("default")))
-#else
-#define DllExport
-#endif
-
-class processing_system7_v5_5_tlm;
-
-class DllExport scalp_zynqps_processing_system7_0_0_sc : public sc_core::sc_module
-{
-public:
-
- scalp_zynqps_processing_system7_0_0_sc(const sc_core::sc_module_name& nm);
- virtual ~scalp_zynqps_processing_system7_0_0_sc();
-
-public: // module socket-to-socket TLM interface
-
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_rd_socket;
- xtlm::xtlm_aximm_initiator_socket* M_AXI_GP0_wr_socket;
-
-protected:
-
- processing_system7_v5_5_tlm* mp_impl;
-
-private:
-
- scalp_zynqps_processing_system7_0_0_sc(const scalp_zynqps_processing_system7_0_0_sc&);
- const scalp_zynqps_processing_system7_0_0_sc& operator=(const scalp_zynqps_processing_system7_0_0_sc&);
-
-};
-
-#endif // IP_SCALP_ZYNQPS_PROCESSING_SYSTEM7_0_0_SC_H_
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/vhdl.prj b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/vhdl.prj
deleted file mode 100644
index 529904c79dd4dfe6ddf61ed7651413029b68bb0c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/vhdl.prj
+++ /dev/null
@@ -1,5 +0,0 @@
-vhdl xil_defaultlib \
-"../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/sim/scalp_zynqps_vio_0_0.vhd" \
-"../../../../../.scripts/scalp_zynqps/sim/scalp_zynqps.vhd" \
-
-nosort
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/vlog.prj b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/vlog.prj
deleted file mode 100644
index 9c72217fa873418ae8c0a7c6cc26abdc652ab8ca..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/vlog.prj
+++ /dev/null
@@ -1,9 +0,0 @@
-verilog xil_defaultlib --include "../../../../../.scripts/scalp_zynqps/ipshared/ec67/hdl" --include "../../../../../.scripts/scalp_zynqps/ipshared/2d50/hdl" --include "../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0" --include "../../../../../.scripts/scalp_zynqps/ipshared/1b7e/hdl/verilog" --include "../../../../../.scripts/scalp_zynqps/ipshared/122e/hdl/verilog" --include "../../../../../.scripts/scalp_zynqps/ipshared/46fd/hdl" \
-"../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v" \
-"../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/sim/scalp_zynqps_processing_system7_0_0.v" \
-"../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/sim/scalp_zynqps_util_vector_logic_0_0.v" \
-"../../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/sim/scalp_zynqps_util_vector_logic_1_0.v" \
-
-verilog xil_defaultlib "glbl.v"
-
-nosort
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/xilinx-zynq.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/xilinx-zynq.h
deleted file mode 100755
index 6d14b94860e4c60a5c784ae9b91216a9b528eb30..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/xilinx-zynq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Xilinx SystemC/TLM-2.0 Zynq Wrapper.
- *
- * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
- *
- * Copyright (c) 2016, Xilinx Inc.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "systemc.h"
-
-#include "tlm_utils/simple_initiator_socket.h"
-#include "tlm_utils/simple_target_socket.h"
-#include "tlm_utils/tlm_quantumkeeper.h"
-
-#include "remote-port-tlm.h"
-#include "remote-port-tlm-memory-master.h"
-#include "remote-port-tlm-memory-slave.h"
-#include "remote-port-tlm-wires.h"
-
-class xilinx_zynq
-: public remoteport_tlm
-{
-private:
- remoteport_tlm_memory_master rp_m_axi_gp0;
- remoteport_tlm_memory_master rp_m_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_gp0;
- remoteport_tlm_memory_slave rp_s_axi_gp1;
-
- remoteport_tlm_memory_slave rp_s_axi_hp0;
- remoteport_tlm_memory_slave rp_s_axi_hp1;
- remoteport_tlm_memory_slave rp_s_axi_hp2;
- remoteport_tlm_memory_slave rp_s_axi_hp3;
-
- remoteport_tlm_memory_slave rp_s_axi_acp;
-
- remoteport_tlm_wires rp_wires_in;
- remoteport_tlm_wires rp_wires_out;
- remoteport_tlm_wires rp_irq_out;
-
-public:
- /*
- * M_AXI_GP 0 - 1.
- * These sockets represent the High speed PS to PL interfaces.
- * These are AXI Slave ports on the PS side and AXI Master ports
- * on the PL side.
- *
- * Used to transfer data from the PS to the PL.
- */
- tlm_utils::simple_initiator_socket<remoteport_tlm_memory_master> *m_axi_gp[2];
-
- /*
- * S_AXI_GP0 - 1.
- * These sockets represent the High speed IO Coherent PL to PS
- * interfaces.
- *
- * HP0 - 3.
- * These sockets represent the High performance dataflow PL to PS interfaces.
- *
- * ACP
- * Accelerator Coherency Port, used to transfered coherent data to
- * the PS via the Cortex-A9 subsystem.
- *
- * These are AXI Master ports on the PS side and AXI Slave ports
- * on the PL side.
- *
- * Used to transfer data from the PL to the PS.
- */
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_gp[2];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_hp[4];
- tlm_utils::simple_target_socket<remoteport_tlm_memory_slave> *s_axi_acp;
-
- /* PL (fabric) to PS interrupt signals. */
- sc_vector<sc_signal<bool> > pl2ps_irq;
-
- /* PS to PL Interrupt signals. */
- sc_vector<sc_signal<bool> > ps2pl_irq;
-
- /* FPGA out resets. */
- sc_vector<sc_signal<bool> > ps2pl_rst;
-
- xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr);
- //xilinx_zynq(sc_core::sc_module_name name, const char *sk_descr,
- // Iremoteport_tlm_sync *sync = NULL);
-};
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/xlconstant_v1_1_6.h b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/xlconstant_v1_1_6.h
deleted file mode 100755
index 73a7cd353b492b4b05e536c4f6f27347641da90b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/sim_scripts/scalp_zynqps/xsim/xlconstant_v1_1_6.h
+++ /dev/null
@@ -1,69 +0,0 @@
-// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:xlconstant:1.1
-// IP Revision: 1
-
-#ifndef _xlconstant_v1_1_6_H_
-#define _xlconstant_v1_1_6_H_
-
-#include "systemc.h"
-template<int CONST_WIDTH,int CONST_VAL>
-SC_MODULE(xlconstant_v1_1_6) {
- public:
- sc_out< sc_bv<CONST_WIDTH> > dout;
- void init() {
- dout.write(CONST_VAL);
- }
- SC_CTOR(xlconstant_v1_1_6) {
- SC_METHOD(init);
- }
-};
-
-#endif
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/.jobs/vrs_config_1.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/.jobs/vrs_config_1.xml
deleted file mode 100644
index 07f8a0b6cd7dcfcfdaf381cb8335abfecd87b541..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/.jobs/vrs_config_1.xml
+++ /dev/null
@@ -1,12 +0,0 @@
-<?xml version="1.0"?>
-<Runs Version="1" Minor="0">
- <Run Id="scalp_zynqps_processing_system7_0_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Run Id="scalp_zynqps_util_vector_logic_0_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Run Id="scalp_zynqps_util_vector_logic_1_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Run Id="scalp_zynqps_vio_0_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Parameters>
- <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
- <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
- </Parameters>
-</Runs>
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/.jobs/vrs_config_2.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/.jobs/vrs_config_2.xml
deleted file mode 100644
index 3d0945630b26eb094ea5d89060af4c6262784202..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/.jobs/vrs_config_2.xml
+++ /dev/null
@@ -1,18 +0,0 @@
-<?xml version="1.0"?>
-<Runs Version="1" Minor="0">
- <Run Id="scalp_zynqps_processing_system7_0_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Run Id="scalp_zynqps_util_vector_logic_0_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Run Id="scalp_zynqps_util_vector_logic_1_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Run Id="scalp_zynqps_vio_0_0_synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
- <Run Id="synth_1" LaunchDir="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado">
- <Parent Id="scalp_zynqps_processing_system7_0_0_synth_1"/>
- <Parent Id="scalp_zynqps_util_vector_logic_0_0_synth_1"/>
- <Parent Id="scalp_zynqps_util_vector_logic_1_0_synth_1"/>
- <Parent Id="scalp_zynqps_vio_0_0_synth_1"/>
- </Run>
- <Parameters>
- <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
- <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
- </Parameters>
-</Runs>
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/.Xil/scalp_zynqps_processing_system7_0_0_propImpl.xdc b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/.Xil/scalp_zynqps_processing_system7_0_0_propImpl.xdc
deleted file mode 100644
index 9540867cc0e549e68503066cb85a4b29c6f24c4c..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/.Xil/scalp_zynqps_processing_system7_0_0_propImpl.xdc
+++ /dev/null
@@ -1,264 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc rfile:../../../../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design]
-current_instance inst
-set_property src_info {type:SCOPED_XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
-set_input_jitter clk_fpga_0 0.24
-set_property src_info {type:SCOPED_XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C11" [get_ports "MIO[53]"]
-set_property src_info {type:SCOPED_XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D13" [get_ports "MIO[52]"]
-set_property src_info {type:SCOPED_XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C13" [get_ports "MIO[51]"]
-set_property src_info {type:SCOPED_XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D10" [get_ports "MIO[50]"]
-set_property src_info {type:SCOPED_XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C9" [get_ports "MIO[49]"]
-set_property src_info {type:SCOPED_XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D12" [get_ports "MIO[48]"]
-set_property src_info {type:SCOPED_XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B13" [get_ports "MIO[47]"]
-set_property src_info {type:SCOPED_XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D11" [get_ports "MIO[46]"]
-set_property src_info {type:SCOPED_XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B14" [get_ports "MIO[45]"]
-set_property src_info {type:SCOPED_XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E10" [get_ports "MIO[44]"]
-set_property src_info {type:SCOPED_XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B12" [get_ports "MIO[43]"]
-set_property src_info {type:SCOPED_XDC file:1 line:108 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D15" [get_ports "MIO[42]"]
-set_property src_info {type:SCOPED_XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C15" [get_ports "MIO[41]"]
-set_property src_info {type:SCOPED_XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E9" [get_ports "MIO[40]"]
-set_property src_info {type:SCOPED_XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C10" [get_ports "MIO[39]"]
-set_property src_info {type:SCOPED_XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F10" [get_ports "MIO[38]"]
-set_property src_info {type:SCOPED_XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B9" [get_ports "MIO[37]"]
-set_property src_info {type:SCOPED_XDC file:1 line:150 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A14" [get_ports "MIO[36]"]
-set_property src_info {type:SCOPED_XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F9" [get_ports "MIO[35]"]
-set_property src_info {type:SCOPED_XDC file:1 line:164 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B11" [get_ports "MIO[34]"]
-set_property src_info {type:SCOPED_XDC file:1 line:171 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "G11" [get_ports "MIO[33]"]
-set_property src_info {type:SCOPED_XDC file:1 line:178 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C16" [get_ports "MIO[32]"]
-set_property src_info {type:SCOPED_XDC file:1 line:185 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F14" [get_ports "MIO[31]"]
-set_property src_info {type:SCOPED_XDC file:1 line:192 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A12" [get_ports "MIO[30]"]
-set_property src_info {type:SCOPED_XDC file:1 line:199 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E15" [get_ports "MIO[29]"]
-set_property src_info {type:SCOPED_XDC file:1 line:206 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A11" [get_ports "MIO[28]"]
-set_property src_info {type:SCOPED_XDC file:1 line:213 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D16" [get_ports "MIO[27]"]
-set_property src_info {type:SCOPED_XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A10" [get_ports "MIO[26]"]
-set_property src_info {type:SCOPED_XDC file:1 line:227 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F11" [get_ports "MIO[25]"]
-set_property src_info {type:SCOPED_XDC file:1 line:234 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B16" [get_ports "MIO[24]"]
-set_property src_info {type:SCOPED_XDC file:1 line:241 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E12" [get_ports "MIO[23]"]
-set_property src_info {type:SCOPED_XDC file:1 line:248 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A9" [get_ports "MIO[22]"]
-set_property src_info {type:SCOPED_XDC file:1 line:255 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F12" [get_ports "MIO[21]"]
-set_property src_info {type:SCOPED_XDC file:1 line:262 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A15" [get_ports "MIO[20]"]
-set_property src_info {type:SCOPED_XDC file:1 line:269 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E13" [get_ports "MIO[19]"]
-set_property src_info {type:SCOPED_XDC file:1 line:276 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A16" [get_ports "MIO[18]"]
-set_property src_info {type:SCOPED_XDC file:1 line:283 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E14" [get_ports "MIO[17]"]
-set_property src_info {type:SCOPED_XDC file:1 line:290 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D17" [get_ports "MIO[16]"]
-set_property src_info {type:SCOPED_XDC file:1 line:297 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E17" [get_ports "MIO[15]"]
-set_property src_info {type:SCOPED_XDC file:1 line:304 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B17" [get_ports "MIO[14]"]
-set_property src_info {type:SCOPED_XDC file:1 line:311 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A17" [get_ports "MIO[13]"]
-set_property src_info {type:SCOPED_XDC file:1 line:318 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C18" [get_ports "MIO[12]"]
-set_property src_info {type:SCOPED_XDC file:1 line:325 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B19" [get_ports "MIO[11]"]
-set_property src_info {type:SCOPED_XDC file:1 line:332 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "G16" [get_ports "MIO[10]"]
-set_property src_info {type:SCOPED_XDC file:1 line:339 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C19" [get_ports "MIO[9]"]
-set_property src_info {type:SCOPED_XDC file:1 line:346 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E18" [get_ports "MIO[8]"]
-set_property src_info {type:SCOPED_XDC file:1 line:352 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D18" [get_ports "MIO[7]"]
-set_property src_info {type:SCOPED_XDC file:1 line:358 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A19" [get_ports "MIO[6]"]
-set_property src_info {type:SCOPED_XDC file:1 line:364 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A20" [get_ports "MIO[5]"]
-set_property src_info {type:SCOPED_XDC file:1 line:370 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E19" [get_ports "MIO[4]"]
-set_property src_info {type:SCOPED_XDC file:1 line:376 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F17" [get_ports "MIO[3]"]
-set_property src_info {type:SCOPED_XDC file:1 line:382 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A21" [get_ports "MIO[2]"]
-set_property src_info {type:SCOPED_XDC file:1 line:388 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "A22" [get_ports "MIO[1]"]
-set_property src_info {type:SCOPED_XDC file:1 line:395 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "G17" [get_ports "MIO[0]"]
-set_property src_info {type:SCOPED_XDC file:1 line:401 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "N16" [get_ports "DDR_VRP"]
-set_property src_info {type:SCOPED_XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "M16" [get_ports "DDR_VRN"]
-set_property src_info {type:SCOPED_XDC file:1 line:409 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "R19" [get_ports "DDR_WEB"]
-set_property src_info {type:SCOPED_XDC file:1 line:413 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "R18" [get_ports "DDR_RAS_n"]
-set_property src_info {type:SCOPED_XDC file:1 line:417 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "P18" [get_ports "DDR_ODT"]
-set_property src_info {type:SCOPED_XDC file:1 line:421 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F20" [get_ports "DDR_DRSTB"]
-set_property src_info {type:SCOPED_XDC file:1 line:425 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "V21" [get_ports "DDR_DQS[3]"]
-set_property src_info {type:SCOPED_XDC file:1 line:430 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "N21" [get_ports "DDR_DQS[2]"]
-set_property src_info {type:SCOPED_XDC file:1 line:435 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "H21" [get_ports "DDR_DQS[1]"]
-set_property src_info {type:SCOPED_XDC file:1 line:439 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C21" [get_ports "DDR_DQS[0]"]
-set_property src_info {type:SCOPED_XDC file:1 line:443 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "W21" [get_ports "DDR_DQS_n[3]"]
-set_property src_info {type:SCOPED_XDC file:1 line:448 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "P21" [get_ports "DDR_DQS_n[2]"]
-set_property src_info {type:SCOPED_XDC file:1 line:453 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "J21" [get_ports "DDR_DQS_n[1]"]
-set_property src_info {type:SCOPED_XDC file:1 line:457 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D21" [get_ports "DDR_DQS_n[0]"]
-set_property src_info {type:SCOPED_XDC file:1 line:461 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "G22" [get_ports "DDR_DQ[9]"]
-set_property src_info {type:SCOPED_XDC file:1 line:465 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "G21" [get_ports "DDR_DQ[8]"]
-set_property src_info {type:SCOPED_XDC file:1 line:469 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F22" [get_ports "DDR_DQ[7]"]
-set_property src_info {type:SCOPED_XDC file:1 line:473 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F21" [get_ports "DDR_DQ[6]"]
-set_property src_info {type:SCOPED_XDC file:1 line:477 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E22" [get_ports "DDR_DQ[5]"]
-set_property src_info {type:SCOPED_XDC file:1 line:481 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "E20" [get_ports "DDR_DQ[4]"]
-set_property src_info {type:SCOPED_XDC file:1 line:485 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D20" [get_ports "DDR_DQ[3]"]
-set_property src_info {type:SCOPED_XDC file:1 line:489 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "Y22" [get_ports "DDR_DQ[31]"]
-set_property src_info {type:SCOPED_XDC file:1 line:494 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "V20" [get_ports "DDR_DQ[30]"]
-set_property src_info {type:SCOPED_XDC file:1 line:499 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B21" [get_ports "DDR_DQ[2]"]
-set_property src_info {type:SCOPED_XDC file:1 line:503 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "W20" [get_ports "DDR_DQ[29]"]
-set_property src_info {type:SCOPED_XDC file:1 line:508 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "W22" [get_ports "DDR_DQ[28]"]
-set_property src_info {type:SCOPED_XDC file:1 line:513 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "U21" [get_ports "DDR_DQ[27]"]
-set_property src_info {type:SCOPED_XDC file:1 line:518 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "AA22" [get_ports "DDR_DQ[26]"]
-set_property src_info {type:SCOPED_XDC file:1 line:523 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "U22" [get_ports "DDR_DQ[25]"]
-set_property src_info {type:SCOPED_XDC file:1 line:528 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "Y20" [get_ports "DDR_DQ[24]"]
-set_property src_info {type:SCOPED_XDC file:1 line:533 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "R22" [get_ports "DDR_DQ[23]"]
-set_property src_info {type:SCOPED_XDC file:1 line:538 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "M21" [get_ports "DDR_DQ[22]"]
-set_property src_info {type:SCOPED_XDC file:1 line:543 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "T21" [get_ports "DDR_DQ[21]"]
-set_property src_info {type:SCOPED_XDC file:1 line:548 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "R20" [get_ports "DDR_DQ[20]"]
-set_property src_info {type:SCOPED_XDC file:1 line:553 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C20" [get_ports "DDR_DQ[1]"]
-set_property src_info {type:SCOPED_XDC file:1 line:557 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "T22" [get_ports "DDR_DQ[19]"]
-set_property src_info {type:SCOPED_XDC file:1 line:562 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "N20" [get_ports "DDR_DQ[18]"]
-set_property src_info {type:SCOPED_XDC file:1 line:567 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "T20" [get_ports "DDR_DQ[17]"]
-set_property src_info {type:SCOPED_XDC file:1 line:572 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "M22" [get_ports "DDR_DQ[16]"]
-set_property src_info {type:SCOPED_XDC file:1 line:577 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "K20" [get_ports "DDR_DQ[15]"]
-set_property src_info {type:SCOPED_XDC file:1 line:581 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "J22" [get_ports "DDR_DQ[14]"]
-set_property src_info {type:SCOPED_XDC file:1 line:585 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "K22" [get_ports "DDR_DQ[13]"]
-set_property src_info {type:SCOPED_XDC file:1 line:589 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "L20" [get_ports "DDR_DQ[12]"]
-set_property src_info {type:SCOPED_XDC file:1 line:593 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "L21" [get_ports "DDR_DQ[11]"]
-set_property src_info {type:SCOPED_XDC file:1 line:597 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "L22" [get_ports "DDR_DQ[10]"]
-set_property src_info {type:SCOPED_XDC file:1 line:601 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "D22" [get_ports "DDR_DQ[0]"]
-set_property src_info {type:SCOPED_XDC file:1 line:605 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "AA21" [get_ports "DDR_DM[3]"]
-set_property src_info {type:SCOPED_XDC file:1 line:610 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "P22" [get_ports "DDR_DM[2]"]
-set_property src_info {type:SCOPED_XDC file:1 line:615 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "H20" [get_ports "DDR_DM[1]"]
-set_property src_info {type:SCOPED_XDC file:1 line:619 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B22" [get_ports "DDR_DM[0]"]
-set_property src_info {type:SCOPED_XDC file:1 line:623 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "P17" [get_ports "DDR_CS_n"]
-set_property src_info {type:SCOPED_XDC file:1 line:627 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "T19" [get_ports "DDR_CKE"]
-set_property src_info {type:SCOPED_XDC file:1 line:631 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "N19" [get_ports "DDR_Clk"]
-set_property src_info {type:SCOPED_XDC file:1 line:635 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "N18" [get_ports "DDR_Clk_n"]
-set_property src_info {type:SCOPED_XDC file:1 line:639 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "P20" [get_ports "DDR_CAS_n"]
-set_property src_info {type:SCOPED_XDC file:1 line:643 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "M17" [get_ports "DDR_BankAddr[2]"]
-set_property src_info {type:SCOPED_XDC file:1 line:647 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "L17" [get_ports "DDR_BankAddr[1]"]
-set_property src_info {type:SCOPED_XDC file:1 line:651 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "L16" [get_ports "DDR_BankAddr[0]"]
-set_property src_info {type:SCOPED_XDC file:1 line:655 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "H18" [get_ports "DDR_Addr[9]"]
-set_property src_info {type:SCOPED_XDC file:1 line:659 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "J18" [get_ports "DDR_Addr[8]"]
-set_property src_info {type:SCOPED_XDC file:1 line:663 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "J17" [get_ports "DDR_Addr[7]"]
-set_property src_info {type:SCOPED_XDC file:1 line:667 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "J16" [get_ports "DDR_Addr[6]"]
-set_property src_info {type:SCOPED_XDC file:1 line:671 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "K18" [get_ports "DDR_Addr[5]"]
-set_property src_info {type:SCOPED_XDC file:1 line:675 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "K17" [get_ports "DDR_Addr[4]"]
-set_property src_info {type:SCOPED_XDC file:1 line:679 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "L19" [get_ports "DDR_Addr[3]"]
-set_property src_info {type:SCOPED_XDC file:1 line:683 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "K19" [get_ports "DDR_Addr[2]"]
-set_property src_info {type:SCOPED_XDC file:1 line:687 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "M18" [get_ports "DDR_Addr[1]"]
-set_property src_info {type:SCOPED_XDC file:1 line:691 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "G19" [get_ports "DDR_Addr[14]"]
-set_property src_info {type:SCOPED_XDC file:1 line:695 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F19" [get_ports "DDR_Addr[13]"]
-set_property src_info {type:SCOPED_XDC file:1 line:699 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "H19" [get_ports "DDR_Addr[12]"]
-set_property src_info {type:SCOPED_XDC file:1 line:703 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "G18" [get_ports "DDR_Addr[11]"]
-set_property src_info {type:SCOPED_XDC file:1 line:707 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "J20" [get_ports "DDR_Addr[10]"]
-set_property src_info {type:SCOPED_XDC file:1 line:711 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "M19" [get_ports "DDR_Addr[0]"]
-set_property src_info {type:SCOPED_XDC file:1 line:715 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "B18" [get_ports "PS_PORB"]
-set_property src_info {type:SCOPED_XDC file:1 line:718 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "C14" [get_ports "PS_SRSTB"]
-set_property src_info {type:SCOPED_XDC file:1 line:721 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN "F16" [get_ports "PS_CLK"]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/ISEWrap.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/ISEWrap.sh
deleted file mode 100755
index f679f2e86873e3482adf4a51d722e917f3d4aab2..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/ISEWrap.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# ISEWrap.sh: Vivado Runs Script for UNIX
-# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-#
-
-HD_LOG=$1
-shift
-
-# CHECK for a STOP FILE
-if [ -f .stop.rst ]
-then
-echo "" >> $HD_LOG
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
-echo "" >> $HD_LOG
-exit 1
-fi
-
-ISE_STEP=$1
-shift
-
-# WRITE STEP HEADER to LOG
-echo "" >> $HD_LOG
-echo "*** Running $ISE_STEP" >> $HD_LOG
-echo " with args $@" >> $HD_LOG
-echo "" >> $HD_LOG
-
-# LAUNCH!
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
-
-# BEGIN file creation
-ISE_PID=$!
-if [ X != X$HOSTNAME ]
-then
-ISE_HOST=$HOSTNAME #bash
-else
-ISE_HOST=$HOST #csh
-fi
-ISE_USER=$USER
-
-ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
-ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
-
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
-/bin/touch $ISE_BEGINFILE
-echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
-echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
-echo " </Process>" >> $ISE_BEGINFILE
-echo "</ProcessHandle>" >> $ISE_BEGINFILE
-
-# WAIT for ISEStep to finish
-wait $ISE_PID
-
-# END/ERROR file creation
-RETVAL=$?
-if [ $RETVAL -eq 0 ]
-then
- /bin/touch .$ISE_STEP.end.rst
-else
- /bin/touch .$ISE_STEP.error.rst
-fi
-
-exit $RETVAL
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/dont_touch.xdc b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/dont_touch.xdc
deleted file mode 100644
index 7228705cf5d8f36fe1966230c2f47a51c0e8ace9..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/dont_touch.xdc
+++ /dev/null
@@ -1,16 +0,0 @@
-# This file is automatically generated.
-# It contains project source information necessary for synthesis and implementation.
-
-# IP: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci
-# IP: The module: 'scalp_zynqps_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
-
-# XDC: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc
-# XDC: The top module name and the constraint reference have the same name: 'scalp_zynqps_processing_system7_0_0'. Do not add the DONT_TOUCH constraint.
-set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
-
-# IP: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci
-# IP: The module: 'scalp_zynqps_processing_system7_0_0' is the root of the design. Do not add the DONT_TOUCH constraint.
-
-# XDC: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc
-# XDC: The top module name and the constraint reference have the same name: 'scalp_zynqps_processing_system7_0_0'. Do not add the DONT_TOUCH constraint.
-#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/gen_run.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/gen_run.xml
deleted file mode 100644
index 5858788b076d0cb5a1188a10a2f328fb23643131..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/gen_run.xml
+++ /dev/null
@@ -1,54 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="scalp_zynqps_processing_system7_0_0_synth_1" LaunchPart="xc7z015clg485-2" LaunchTime="1599472465">
- <File Type="VDS-TIMING-PB" Name="scalp_zynqps_processing_system7_0_0_timing_summary_synth.pb"/>
- <File Type="VDS-TIMINGSUMMARY" Name="scalp_zynqps_processing_system7_0_0_timing_summary_synth.rpt"/>
- <File Type="RDS-DCP" Name="scalp_zynqps_processing_system7_0_0.dcp"/>
- <File Type="RDS-UTIL-PB" Name="scalp_zynqps_processing_system7_0_0_utilization_synth.pb"/>
- <File Type="RDS-UTIL" Name="scalp_zynqps_processing_system7_0_0_utilization_synth.rpt"/>
- <File Type="RDS-PROPCONSTRS" Name="scalp_zynqps_processing_system7_0_0_drc_synth.rpt"/>
- <File Type="RDS-RDS" Name="scalp_zynqps_processing_system7_0_0.vds"/>
- <File Type="REPORTS-TCL" Name="scalp_zynqps_processing_system7_0_0_reports.tcl"/>
- <File Type="PA-TCL" Name="scalp_zynqps_processing_system7_0_0.tcl"/>
- <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_processing_system7_0_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_processing_system7_0_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_processing_system7_0_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_processing_system7_0_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
- <Filter Type="Utils"/>
- <Config>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
- <Step Id="synth_design"/>
- </Strategy>
-</GenRun>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/htr.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/htr.txt
deleted file mode 100644
index 1fcc48b90b2e7b07193e123c2c148d25b22a0167..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/htr.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-# the basic steps of a run. Note that runme.bat/sh needs
-# to be invoked for Vivado to track run status.
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-vivado -log scalp_zynqps_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_processing_system7_0_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/runme.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/runme.sh
deleted file mode 100755
index 544f64a8105f565fe8996254c91622e86741e976..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/runme.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# runme.sh: a Vivado-generated Runs Script for UNIX
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-if [ -z "$PATH" ]; then
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin
-else
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin:$PATH
-fi
-export PATH
-
-if [ -z "$LD_LIBRARY_PATH" ]; then
- LD_LIBRARY_PATH=
-else
- LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
-fi
-export LD_LIBRARY_PATH
-
-HD_PWD='/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1'
-cd "$HD_PWD"
-
-HD_LOG=runme.log
-/bin/touch $HD_LOG
-
-ISEStep="./ISEWrap.sh"
-EAStep()
-{
- $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
- if [ $? -ne 0 ]
- then
- exit
- fi
-}
-
-EAStep vivado -log scalp_zynqps_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_processing_system7_0_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.dcp
deleted file mode 100644
index e81d6690a9a631b5127cd968836d28866827def0..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.tcl
deleted file mode 100644
index c0eab0f088cd96ae106acad7a7c083af5808713a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.tcl
+++ /dev/null
@@ -1,171 +0,0 @@
-#
-# Synthesis run script generated by Vivado
-#
-
-set TIME_start [clock seconds]
-proc create_report { reportName command } {
- set status "."
- append status $reportName ".fail"
- if { [file exists $status] } {
- eval file delete [glob $status]
- }
- send_msg_id runtcl-4 info "Executing : $command"
- set retval [eval catch { $command } msg]
- if { $retval != 0 } {
- set fp [open $status w]
- close $fp
- send_msg_id runtcl-5 warning "$msg"
- }
-}
-set_param project.vivado.isBlockSynthRun true
-set_msg_config -msgmgr_mode ooc_run
-create_project -in_memory -part xc7z015clg485-2
-
-set_param project.singleFileAddWarning.threshold 0
-set_param project.compositeFile.enableAutoGeneration 0
-set_param synth.vivado.isSynthRun true
-set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
-set_property webtalk.parent_dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt [current_project]
-set_property parent.project_path /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr [current_project]
-set_property default_lib xil_defaultlib [current_project]
-set_property target_language VHDL [current_project]
-set_property ip_repo_paths /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw [current_project]
-update_ip_catalog
-set_property ip_output_repo /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip [current_project]
-set_property ip_cache_permissions {read write} [current_project]
-read_ip -quiet /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci
-set_property used_in_implementation false [get_files -all /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc]
-
-# Mark all dcp files as not used in implementation to prevent them from being
-# stitched into the results of this synthesis run. Any black boxes in the
-# design are intentionally left as such for best results. Dcp files will be
-# stitched into the design at a later time, either when this synthesis run is
-# opened, or when it is stitched into a dependent implementation run.
-foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
- set_property used_in_implementation false $dcp
-}
-read_xdc dont_touch.xdc
-set_property used_in_implementation false [get_files dont_touch.xdc]
-set_param ips.enableIPCacheLiteLoad 1
-
-set cached_ip [config_ip_cache -export -no_bom -dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1 -new_name scalp_zynqps_processing_system7_0_0 -ip [get_ips scalp_zynqps_processing_system7_0_0]]
-
-if { $cached_ip eq {} } {
-close [open __synthesis_is_running__ w]
-
-synth_design -top scalp_zynqps_processing_system7_0_0 -part xc7z015clg485-2 -mode out_of_context
-
-#---------------------------------------------------------
-# Generate Checkpoint/Stub/Simulation Files For IP Cache
-#---------------------------------------------------------
-# disable binary constraint mode for IPCache checkpoints
-set_param constraints.enableBinaryConstraints false
-
-catch {
- write_checkpoint -force -noxdef -rename_prefix scalp_zynqps_processing_system7_0_0_ scalp_zynqps_processing_system7_0_0.dcp
-
- set ipCachedFiles {}
- write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_processing_system7_0_0_stub.v
- lappend ipCachedFiles scalp_zynqps_processing_system7_0_0_stub.v
-
- write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_processing_system7_0_0_stub.vhdl
- lappend ipCachedFiles scalp_zynqps_processing_system7_0_0_stub.vhdl
-
- write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_processing_system7_0_0_sim_netlist.v
- lappend ipCachedFiles scalp_zynqps_processing_system7_0_0_sim_netlist.v
-
- write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_processing_system7_0_0_sim_netlist.vhdl
- lappend ipCachedFiles scalp_zynqps_processing_system7_0_0_sim_netlist.vhdl
-set TIME_taken [expr [clock seconds] - $TIME_start]
-
- config_ip_cache -add -dcp scalp_zynqps_processing_system7_0_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips scalp_zynqps_processing_system7_0_0]
-}
-
-rename_ref -prefix_all scalp_zynqps_processing_system7_0_0_
-
-# disable binary constraint mode for synth run checkpoints
-set_param constraints.enableBinaryConstraints false
-write_checkpoint -force -noxdef scalp_zynqps_processing_system7_0_0.dcp
-create_report "scalp_zynqps_processing_system7_0_0_synth_1_synth_report_utilization_0" "report_utilization -file scalp_zynqps_processing_system7_0_0_utilization_synth.rpt -pb scalp_zynqps_processing_system7_0_0_utilization_synth.pb"
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- write_verilog -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_verilog -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-
-} else {
-
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_sim_netlist.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_sim_netlist.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-}; # end if cached_ip
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_processing_system7_0_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_processing_system7_0_0
- }
-}
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_processing_system7_0_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_processing_system7_0_0
- }
-}
-file delete __synthesis_is_running__
-close [open __synthesis_is_complete__ w]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.vds b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.vds
deleted file mode 100644
index 5bc0b7e8b9aa4fe3829aeaa0a1ff9ab34a559a73..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.vds
+++ /dev/null
@@ -1,442 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21731
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1
-# Command line: vivado -log scalp_zynqps_processing_system7_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_processing_system7_0_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_processing_system7_0_0.tcl -notrace
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw'.
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
-Command: synth_design -top scalp_zynqps_processing_system7_0_0 -part xc7z015clg485-2 -mode out_of_context
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Device 21-403] Loading part xc7z015clg485-2
-INFO: Launching helper process for spawning children vivado processes
-INFO: Helper process launched with PID 22481
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1871.648 ; gain = 200.570 ; free physical = 6225 ; free virtual = 18763
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'scalp_zynqps_processing_system7_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/synth/scalp_zynqps_processing_system7_0_0.v:60]
-INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
- Parameter C_USE_DEFAULT_ACP_USER_VAL bound to: 0 - type: integer
- Parameter C_S_AXI_ACP_ARUSER_VAL bound to: 31 - type: integer
- Parameter C_S_AXI_ACP_AWUSER_VAL bound to: 31 - type: integer
- Parameter C_M_AXI_GP0_THREAD_ID_WIDTH bound to: 12 - type: integer
- Parameter C_M_AXI_GP1_THREAD_ID_WIDTH bound to: 12 - type: integer
- Parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP bound to: 0 - type: integer
- Parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP bound to: 0 - type: integer
- Parameter C_M_AXI_GP0_ID_WIDTH bound to: 12 - type: integer
- Parameter C_M_AXI_GP1_ID_WIDTH bound to: 12 - type: integer
- Parameter C_S_AXI_GP0_ID_WIDTH bound to: 6 - type: integer
- Parameter C_S_AXI_GP1_ID_WIDTH bound to: 6 - type: integer
- Parameter C_S_AXI_HP0_ID_WIDTH bound to: 6 - type: integer
- Parameter C_S_AXI_HP1_ID_WIDTH bound to: 6 - type: integer
- Parameter C_S_AXI_HP2_ID_WIDTH bound to: 6 - type: integer
- Parameter C_S_AXI_HP3_ID_WIDTH bound to: 6 - type: integer
- Parameter C_S_AXI_ACP_ID_WIDTH bound to: 3 - type: integer
- Parameter C_S_AXI_HP0_DATA_WIDTH bound to: 64 - type: integer
- Parameter C_S_AXI_HP1_DATA_WIDTH bound to: 64 - type: integer
- Parameter C_S_AXI_HP2_DATA_WIDTH bound to: 64 - type: integer
- Parameter C_S_AXI_HP3_DATA_WIDTH bound to: 64 - type: integer
- Parameter C_INCLUDE_ACP_TRANS_CHECK bound to: 0 - type: integer
- Parameter C_NUM_F2P_INTR_INPUTS bound to: 1 - type: integer
- Parameter C_FCLK_CLK0_BUF bound to: TRUE - type: string
- Parameter C_FCLK_CLK1_BUF bound to: FALSE - type: string
- Parameter C_FCLK_CLK2_BUF bound to: FALSE - type: string
- Parameter C_FCLK_CLK3_BUF bound to: FALSE - type: string
- Parameter C_EMIO_GPIO_WIDTH bound to: 64 - type: integer
- Parameter C_INCLUDE_TRACE_BUFFER bound to: 0 - type: integer
- Parameter C_TRACE_BUFFER_FIFO_SIZE bound to: 128 - type: integer
- Parameter C_TRACE_BUFFER_CLOCK_DELAY bound to: 12 - type: integer
- Parameter USE_TRACE_DATA_EDGE_DETECTOR bound to: 0 - type: integer
- Parameter C_TRACE_PIPELINE_WIDTH bound to: 8 - type: integer
- Parameter C_PS7_SI_REV bound to: PRODUCTION - type: string
- Parameter C_EN_EMIO_ENET0 bound to: 0 - type: integer
- Parameter C_EN_EMIO_ENET1 bound to: 0 - type: integer
- Parameter C_EN_EMIO_TRACE bound to: 0 - type: integer
- Parameter C_DQ_WIDTH bound to: 32 - type: integer
- Parameter C_DQS_WIDTH bound to: 4 - type: integer
- Parameter C_DM_WIDTH bound to: 4 - type: integer
- Parameter C_MIO_PRIMITIVE bound to: 54 - type: integer
- Parameter C_PACKAGE_NAME bound to: clg485 - type: string
- Parameter C_IRQ_F2P_MODE bound to: DIRECT - type: string
- Parameter C_TRACE_INTERNAL_WIDTH bound to: 2 - type: integer
- Parameter C_EN_EMIO_PJTAG bound to: 0 - type: integer
- Parameter C_USE_AXI_NONSECURE bound to: 0 - type: integer
- Parameter C_USE_S_AXI_HP0 bound to: 0 - type: integer
- Parameter C_USE_S_AXI_HP1 bound to: 0 - type: integer
- Parameter C_USE_S_AXI_HP2 bound to: 0 - type: integer
- Parameter C_USE_S_AXI_HP3 bound to: 0 - type: integer
- Parameter C_USE_M_AXI_GP0 bound to: 1 - type: integer
- Parameter C_USE_M_AXI_GP1 bound to: 0 - type: integer
- Parameter C_USE_S_AXI_GP0 bound to: 0 - type: integer
- Parameter C_USE_S_AXI_GP1 bound to: 0 - type: integer
- Parameter C_USE_S_AXI_ACP bound to: 0 - type: integer
- Parameter C_GP0_EN_MODIFIABLE_TXN bound to: 1 - type: integer
- Parameter C_GP1_EN_MODIFIABLE_TXN bound to: 1 - type: integer
-INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1348]
-INFO: [Synth 8-5534] Detected attribute (* keep = "true" *) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:1349]
-INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1075]
-INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:1075]
-INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:722]
-INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (2#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:722]
-INFO: [Synth 8-6157] synthesizing module 'PS7' [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:61924]
-INFO: [Synth 8-6155] done synthesizing module 'PS7' (3#1) [/opt/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:61924]
-INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (4#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162]
-WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/synth/scalp_zynqps_processing_system7_0_0.v:365]
-INFO: [Synth 8-6155] done synthesizing module 'scalp_zynqps_processing_system7_0_0' (5#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/synth/scalp_zynqps_processing_system7_0_0.v:60]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_COL
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_CRS
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_DV
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_ER
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[7]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[6]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[5]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[4]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[3]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[1]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[0]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_COL
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_CRS
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_DV
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_ER
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[7]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[6]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[5]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[4]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[3]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[1]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[0]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP0_ARSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP0_AWSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP1_ARSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_GP1_AWSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_ACP_ARSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_ACP_AWSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP0_ARSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP0_AWSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP1_ARSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP1_AWSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP2_ARSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP2_AWSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP3_ARSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port S_AXI_HP3_AWSIZE[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG3_N
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG2_N
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG1_N
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FCLK_CLKTRIG0_N
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[31]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[30]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[29]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[28]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[27]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[26]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[25]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[24]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[23]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[22]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[21]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[20]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[19]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[18]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[17]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[16]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[15]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[14]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[13]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[12]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[11]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[10]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[9]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[8]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[7]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[6]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[5]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[4]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[3]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[1]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_DATA[0]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_VALID
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[3]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[1]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[0]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1935.367 ; gain = 264.289 ; free physical = 6175 ; free virtual = 18704
----------------------------------------------------------------------------------
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1935.367 ; gain = 264.289 ; free physical = 6204 ; free virtual = 18736
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1935.367 ; gain = 264.289 ; free physical = 6204 ; free virtual = 18737
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1946.273 ; gain = 0.000 ; free physical = 6244 ; free virtual = 18777
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc] for cell 'inst'
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc] for cell 'inst'
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/scalp_zynqps_processing_system7_0_0_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/scalp_zynqps_processing_system7_0_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/dont_touch.xdc]
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/dont_touch.xdc]
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2028.148 ; gain = 0.000 ; free physical = 6109 ; free virtual = 18655
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2028.148 ; gain = 0.000 ; free physical = 6111 ; free virtual = 18658
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2028.148 ; gain = 357.070 ; free physical = 6109 ; free virtual = 18673
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7z015clg485-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2028.148 ; gain = 357.070 ; free physical = 6109 ; free virtual = 18673
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
-Applied set_property DONT_TOUCH = true for inst. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/dont_touch.xdc, line 9).
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.148 ; gain = 357.070 ; free physical = 6102 ; free virtual = 18651
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 2028.148 ; gain = 357.070 ; free physical = 6083 ; free virtual = 18633
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
-Hierarchical RTL Component report
----------------------------------------------------------------------------------
-Finished RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 160 (col length:60)
-BRAMs: 190 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-Warning: Parallel synthesis criteria is not met
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_COL
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_CRS
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_DV
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RX_ER
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[7]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[6]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[5]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[4]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[3]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[2]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[1]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET0_GMII_RXD[0]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_COL
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_CRS
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_DV
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RX_ER
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[7]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[6]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[5]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[4]
-WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[3]
-INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2028.148 ; gain = 357.070 ; free physical = 6035 ; free virtual = 18589
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2173.133 ; gain = 502.055 ; free physical = 4999 ; free virtual = 17557
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2192.141 ; gain = 521.062 ; free physical = 4986 ; free virtual = 17543
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2200.148 ; gain = 529.070 ; free physical = 5035 ; free virtual = 17589
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.055 ; gain = 539.977 ; free physical = 7322 ; free virtual = 19877
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.055 ; gain = 539.977 ; free physical = 7322 ; free virtual = 19877
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.055 ; gain = 539.977 ; free physical = 7322 ; free virtual = 19877
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.055 ; gain = 539.977 ; free physical = 7322 ; free virtual = 19877
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.055 ; gain = 539.977 ; free physical = 7322 ; free virtual = 19877
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.055 ; gain = 539.977 ; free physical = 7322 ; free virtual = 19877
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+------+------+
-| |Cell |Count |
-+------+------+------+
-|1 |BIBUF | 130|
-|2 |BUFG | 1|
-|3 |LUT1 | 112|
-|4 |PS7 | 1|
-+------+------+------+
-
-Report Instance Areas:
-+------+---------+-------------------------------------------+------+
-| |Instance |Module |Cells |
-+------+---------+-------------------------------------------+------+
-|1 |top | | 244|
-|2 | inst |processing_system7_v5_5_processing_system7 | 244|
-+------+---------+-------------------------------------------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.055 ; gain = 539.977 ; free physical = 7322 ; free virtual = 19877
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 79 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2211.055 ; gain = 447.195 ; free physical = 7374 ; free virtual = 19929
-Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2211.062 ; gain = 539.977 ; free physical = 7374 ; free virtual = 19929
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2211.062 ; gain = 0.000 ; free physical = 7459 ; free virtual = 20014
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2220.961 ; gain = 0.000 ; free physical = 7413 ; free virtual = 19952
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-INFO: [Common 17-83] Releasing license: Synthesis
-26 Infos, 101 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:04:02 . Memory (MB): peak = 2220.961 ; gain = 738.773 ; free physical = 7676 ; free virtual = 20223
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2220.961 ; gain = 0.000 ; free physical = 7676 ; free virtual = 20223
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.dcp' has been generated.
-WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
-INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP scalp_zynqps_processing_system7_0_0, cache-ID = b32362bd6ba3a9e9
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2220.961 ; gain = 0.000 ; free physical = 7664 ; free virtual = 20220
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.dcp' has been generated.
-INFO: [runtcl-4] Executing : report_utilization -file scalp_zynqps_processing_system7_0_0_utilization_synth.rpt -pb scalp_zynqps_processing_system7_0_0_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Mon Sep 7 11:58:39 2020...
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_utilization_synth.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_utilization_synth.pb
deleted file mode 100644
index e530b0562e35ab392e3aaa2d2da0dafb9e41e350..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_utilization_synth.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_utilization_synth.rpt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_utilization_synth.rpt
deleted file mode 100644
index b5c8cee42a7973be6dac7503911aca53b7af1a92..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0_utilization_synth.rpt
+++ /dev/null
@@ -1,175 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-| Date : Mon Sep 7 11:58:39 2020
-| Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-| Command : report_utilization -file scalp_zynqps_processing_system7_0_0_utilization_synth.rpt -pb scalp_zynqps_processing_system7_0_0_utilization_synth.pb
-| Design : scalp_zynqps_processing_system7_0_0
-| Device : 7z015clg485-2
-| Design State : Synthesized
------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Memory
-3. DSP
-4. IO and GT Specific
-5. Clocking
-6. Specific Feature
-7. Primitives
-8. Black Boxes
-9. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+-------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------------------+------+-------+-----------+-------+
-| Slice LUTs* | 112 | 0 | 46200 | 0.24 |
-| LUT as Logic | 112 | 0 | 46200 | 0.24 |
-| LUT as Memory | 0 | 0 | 14400 | 0.00 |
-| Slice Registers | 0 | 0 | 92400 | 0.00 |
-| Register as Flip Flop | 0 | 0 | 92400 | 0.00 |
-| Register as Latch | 0 | 0 | 92400 | 0.00 |
-| F7 Muxes | 0 | 0 | 23100 | 0.00 |
-| F8 Muxes | 0 | 0 | 11550 | 0.00 |
-+-------------------------+------+-------+-----------+-------+
-* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0 | _ | - | - |
-| 0 | _ | - | Set |
-| 0 | _ | - | Reset |
-| 0 | _ | Set | - |
-| 0 | _ | Reset | - |
-| 0 | Yes | - | - |
-| 0 | Yes | - | Set |
-| 0 | Yes | - | Reset |
-| 0 | Yes | Set | - |
-| 0 | Yes | Reset | - |
-+-------+--------------+-------------+--------------+
-
-
-2. Memory
----------
-
-+----------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+----------------+------+-------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 95 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 95 | 0.00 |
-| RAMB18 | 0 | 0 | 190 | 0.00 |
-+----------------+------+-------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-3. DSP
-------
-
-+-----------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------+------+-------+-----------+-------+
-| DSPs | 0 | 0 | 160 | 0.00 |
-+-----------+------+-------+-----------+-------+
-
-
-4. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+-----------+--------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------------------------+------+-------+-----------+--------+
-| Bonded IOB | 0 | 0 | 150 | 0.00 |
-| Bonded IPADs | 0 | 0 | 14 | 0.00 |
-| Bonded OPADs | 0 | 0 | 8 | 0.00 |
-| Bonded IOPADs | 130 | 0 | 130 | 100.00 |
-| PHY_CONTROL | 0 | 0 | 3 | 0.00 |
-| PHASER_REF | 0 | 0 | 3 | 0.00 |
-| OUT_FIFO | 0 | 0 | 12 | 0.00 |
-| IN_FIFO | 0 | 0 | 12 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 3 | 0.00 |
-| IBUFDS | 0 | 0 | 144 | 0.00 |
-| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 12 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 12 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
-| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
-| ILOGIC | 0 | 0 | 150 | 0.00 |
-| OLOGIC | 0 | 0 | 150 | 0.00 |
-+-----------------------------+------+-------+-----------+--------+
-
-
-5. Clocking
------------
-
-+------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+------------+------+-------+-----------+-------+
-| BUFGCTRL | 1 | 0 | 32 | 3.13 |
-| BUFIO | 0 | 0 | 12 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 3 | 0.00 |
-| PLLE2_ADV | 0 | 0 | 3 | 0.00 |
-| BUFMRCE | 0 | 0 | 6 | 0.00 |
-| BUFHCE | 0 | 0 | 72 | 0.00 |
-| BUFR | 0 | 0 | 12 | 0.00 |
-+------------+------+-------+-----------+-------+
-
-
-6. Specific Feature
--------------------
-
-+-------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------+------+-------+-----------+-------+
-| BSCANE2 | 0 | 0 | 4 | 0.00 |
-| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
-| DNA_PORT | 0 | 0 | 1 | 0.00 |
-| EFUSE_USR | 0 | 0 | 1 | 0.00 |
-| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
-| ICAPE2 | 0 | 0 | 2 | 0.00 |
-| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
-| STARTUPE2 | 0 | 0 | 1 | 0.00 |
-| XADC | 0 | 0 | 1 | 0.00 |
-+-------------+------+-------+-----------+-------+
-
-
-7. Primitives
--------------
-
-+----------+------+----------------------+
-| Ref Name | Used | Functional Category |
-+----------+------+----------------------+
-| BIBUF | 130 | IO |
-| LUT1 | 112 | LUT |
-| PS7 | 1 | Specialized Resource |
-| BUFG | 1 | Clock |
-+----------+------+----------------------+
-
-
-8. Black Boxes
---------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
-9. Instantiated Netlists
-------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.jou b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.jou
deleted file mode 100644
index 855a6d6b386759326f1b05a5175b60dcee7791f9..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.jou
+++ /dev/null
@@ -1,12 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21731
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1
-# Command line: vivado -log scalp_zynqps_processing_system7_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_processing_system7_0_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/scalp_zynqps_processing_system7_0_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_processing_system7_0_0.tcl -notrace
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.pb
deleted file mode 100644
index f9e600ade809019f8eb6d3d49743d021a64af335..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_processing_system7_0_0_synth_1/vivado.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/ISEWrap.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/ISEWrap.sh
deleted file mode 100755
index f679f2e86873e3482adf4a51d722e917f3d4aab2..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/ISEWrap.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# ISEWrap.sh: Vivado Runs Script for UNIX
-# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-#
-
-HD_LOG=$1
-shift
-
-# CHECK for a STOP FILE
-if [ -f .stop.rst ]
-then
-echo "" >> $HD_LOG
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
-echo "" >> $HD_LOG
-exit 1
-fi
-
-ISE_STEP=$1
-shift
-
-# WRITE STEP HEADER to LOG
-echo "" >> $HD_LOG
-echo "*** Running $ISE_STEP" >> $HD_LOG
-echo " with args $@" >> $HD_LOG
-echo "" >> $HD_LOG
-
-# LAUNCH!
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
-
-# BEGIN file creation
-ISE_PID=$!
-if [ X != X$HOSTNAME ]
-then
-ISE_HOST=$HOSTNAME #bash
-else
-ISE_HOST=$HOST #csh
-fi
-ISE_USER=$USER
-
-ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
-ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
-
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
-/bin/touch $ISE_BEGINFILE
-echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
-echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
-echo " </Process>" >> $ISE_BEGINFILE
-echo "</ProcessHandle>" >> $ISE_BEGINFILE
-
-# WAIT for ISEStep to finish
-wait $ISE_PID
-
-# END/ERROR file creation
-RETVAL=$?
-if [ $RETVAL -eq 0 ]
-then
- /bin/touch .$ISE_STEP.end.rst
-else
- /bin/touch .$ISE_STEP.error.rst
-fi
-
-exit $RETVAL
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/gen_run.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/gen_run.xml
deleted file mode 100644
index 5d74098056e81397bdfbe4249801a2860f675fbb..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/gen_run.xml
+++ /dev/null
@@ -1,54 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="scalp_zynqps_util_vector_logic_0_0_synth_1" LaunchPart="xc7z015clg485-2" LaunchTime="1599472465">
- <File Type="VDS-TIMING-PB" Name="scalp_zynqps_util_vector_logic_0_0_timing_summary_synth.pb"/>
- <File Type="VDS-TIMINGSUMMARY" Name="scalp_zynqps_util_vector_logic_0_0_timing_summary_synth.rpt"/>
- <File Type="RDS-DCP" Name="scalp_zynqps_util_vector_logic_0_0.dcp"/>
- <File Type="RDS-UTIL-PB" Name="scalp_zynqps_util_vector_logic_0_0_utilization_synth.pb"/>
- <File Type="RDS-UTIL" Name="scalp_zynqps_util_vector_logic_0_0_utilization_synth.rpt"/>
- <File Type="RDS-PROPCONSTRS" Name="scalp_zynqps_util_vector_logic_0_0_drc_synth.rpt"/>
- <File Type="RDS-RDS" Name="scalp_zynqps_util_vector_logic_0_0.vds"/>
- <File Type="REPORTS-TCL" Name="scalp_zynqps_util_vector_logic_0_0_reports.tcl"/>
- <File Type="PA-TCL" Name="scalp_zynqps_util_vector_logic_0_0.tcl"/>
- <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_util_vector_logic_0_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_util_vector_logic_0_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_util_vector_logic_0_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_util_vector_logic_0_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
- <Filter Type="Utils"/>
- <Config>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
- <Step Id="synth_design"/>
- </Strategy>
-</GenRun>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/htr.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/htr.txt
deleted file mode 100644
index c415fd376e1a2a5546f69640674cff6f24c4bf35..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/htr.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-# the basic steps of a run. Note that runme.bat/sh needs
-# to be invoked for Vivado to track run status.
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-vivado -log scalp_zynqps_util_vector_logic_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_0_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/runme.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/runme.sh
deleted file mode 100755
index 5427523ee026f549bbcea3f3caf91f023b94fe78..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/runme.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# runme.sh: a Vivado-generated Runs Script for UNIX
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-if [ -z "$PATH" ]; then
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin
-else
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin:$PATH
-fi
-export PATH
-
-if [ -z "$LD_LIBRARY_PATH" ]; then
- LD_LIBRARY_PATH=
-else
- LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
-fi
-export LD_LIBRARY_PATH
-
-HD_PWD='/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1'
-cd "$HD_PWD"
-
-HD_LOG=runme.log
-/bin/touch $HD_LOG
-
-ISEStep="./ISEWrap.sh"
-EAStep()
-{
- $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
- if [ $? -ne 0 ]
- then
- exit
- fi
-}
-
-EAStep vivado -log scalp_zynqps_util_vector_logic_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_0_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.dcp
deleted file mode 100644
index 9f2b6ef7a33fc2e214f7c42aab5a238f645faaa9..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.tcl
deleted file mode 100644
index fc128b74d00d101167b1fd967d784657c9c3657e..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.tcl
+++ /dev/null
@@ -1,168 +0,0 @@
-#
-# Synthesis run script generated by Vivado
-#
-
-set TIME_start [clock seconds]
-proc create_report { reportName command } {
- set status "."
- append status $reportName ".fail"
- if { [file exists $status] } {
- eval file delete [glob $status]
- }
- send_msg_id runtcl-4 info "Executing : $command"
- set retval [eval catch { $command } msg]
- if { $retval != 0 } {
- set fp [open $status w]
- close $fp
- send_msg_id runtcl-5 warning "$msg"
- }
-}
-set_param project.vivado.isBlockSynthRun true
-set_msg_config -msgmgr_mode ooc_run
-create_project -in_memory -part xc7z015clg485-2
-
-set_param project.singleFileAddWarning.threshold 0
-set_param project.compositeFile.enableAutoGeneration 0
-set_param synth.vivado.isSynthRun true
-set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
-set_property webtalk.parent_dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt [current_project]
-set_property parent.project_path /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr [current_project]
-set_property default_lib xil_defaultlib [current_project]
-set_property target_language VHDL [current_project]
-set_property ip_repo_paths /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw [current_project]
-update_ip_catalog
-set_property ip_output_repo /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip [current_project]
-set_property ip_cache_permissions {read write} [current_project]
-read_ip -quiet /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci
-
-# Mark all dcp files as not used in implementation to prevent them from being
-# stitched into the results of this synthesis run. Any black boxes in the
-# design are intentionally left as such for best results. Dcp files will be
-# stitched into the design at a later time, either when this synthesis run is
-# opened, or when it is stitched into a dependent implementation run.
-foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
- set_property used_in_implementation false $dcp
-}
-set_param ips.enableIPCacheLiteLoad 1
-
-set cached_ip [config_ip_cache -export -no_bom -dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1 -new_name scalp_zynqps_util_vector_logic_0_0 -ip [get_ips scalp_zynqps_util_vector_logic_0_0]]
-
-if { $cached_ip eq {} } {
-close [open __synthesis_is_running__ w]
-
-synth_design -top scalp_zynqps_util_vector_logic_0_0 -part xc7z015clg485-2 -mode out_of_context
-
-#---------------------------------------------------------
-# Generate Checkpoint/Stub/Simulation Files For IP Cache
-#---------------------------------------------------------
-# disable binary constraint mode for IPCache checkpoints
-set_param constraints.enableBinaryConstraints false
-
-catch {
- write_checkpoint -force -noxdef -rename_prefix scalp_zynqps_util_vector_logic_0_0_ scalp_zynqps_util_vector_logic_0_0.dcp
-
- set ipCachedFiles {}
- write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_0_0_stub.v
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_0_0_stub.v
-
- write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_0_0_stub.vhdl
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_0_0_stub.vhdl
-
- write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
-
- write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_0_0_sim_netlist.vhdl
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_0_0_sim_netlist.vhdl
-set TIME_taken [expr [clock seconds] - $TIME_start]
-
- config_ip_cache -add -dcp scalp_zynqps_util_vector_logic_0_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips scalp_zynqps_util_vector_logic_0_0]
-}
-
-rename_ref -prefix_all scalp_zynqps_util_vector_logic_0_0_
-
-# disable binary constraint mode for synth run checkpoints
-set_param constraints.enableBinaryConstraints false
-write_checkpoint -force -noxdef scalp_zynqps_util_vector_logic_0_0.dcp
-create_report "scalp_zynqps_util_vector_logic_0_0_synth_1_synth_report_utilization_0" "report_utilization -file scalp_zynqps_util_vector_logic_0_0_utilization_synth.rpt -pb scalp_zynqps_util_vector_logic_0_0_utilization_synth.pb"
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- write_verilog -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_verilog -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-
-} else {
-
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_sim_netlist.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-}; # end if cached_ip
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_0_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_0_0
- }
-}
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_0_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_0_0
- }
-}
-file delete __synthesis_is_running__
-close [open __synthesis_is_complete__ w]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.vds b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.vds
deleted file mode 100644
index 4441f4c37169cc87c8b8148f8d0a8b583eba47dd..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.vds
+++ /dev/null
@@ -1,232 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21733
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1
-# Command line: vivado -log scalp_zynqps_util_vector_logic_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_0_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_util_vector_logic_0_0.tcl -notrace
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw'.
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
-Command: synth_design -top scalp_zynqps_util_vector_logic_0_0 -part xc7z015clg485-2 -mode out_of_context
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: Launching helper process for spawning children vivado processes
-INFO: Helper process launched with PID 21809
----------------------------------------------------------------------------------
-Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1628.906 ; gain = 146.570 ; free physical = 7582 ; free virtual = 20049
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'scalp_zynqps_util_vector_logic_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/synth/scalp_zynqps_util_vector_logic_0_0.v:57]
-INFO: [Synth 8-6157] synthesizing module 'util_vector_logic_v2_0_1_util_vector_logic' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v:45]
- Parameter C_OPERATION bound to: or - type: string
- Parameter C_SIZE bound to: 1 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'util_vector_logic_v2_0_1_util_vector_logic' (1#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v:45]
-INFO: [Synth 8-6155] done synthesizing module 'scalp_zynqps_util_vector_logic_0_0' (2#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/synth/scalp_zynqps_util_vector_logic_0_0.v:57]
----------------------------------------------------------------------------------
-Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1690.656 ; gain = 208.320 ; free physical = 7557 ; free virtual = 20027
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1693.625 ; gain = 211.289 ; free physical = 7538 ; free virtual = 20009
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7z015clg485-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1701.629 ; gain = 219.293 ; free physical = 7538 ; free virtual = 20009
----------------------------------------------------------------------------------
-INFO: [Device 21-403] Loading part xc7z015clg485-2
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1712.535 ; gain = 230.199 ; free physical = 7536 ; free virtual = 20007
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-No constraint files found.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
-Hierarchical RTL Component report
----------------------------------------------------------------------------------
-Finished RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 160 (col length:60)
-BRAMs: 190 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
-No constraint files found.
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-Warning: Parallel synthesis criteria is not met
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7161 ; free virtual = 19633
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-No constraint files found.
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7159 ; free virtual = 19632
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7159 ; free virtual = 19632
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7239 ; free virtual = 19712
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7239 ; free virtual = 19712
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7239 ; free virtual = 19712
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7239 ; free virtual = 19712
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7239 ; free virtual = 19712
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7239 ; free virtual = 19712
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----+------+
-| |Cell |Count |
-+------+-----+------+
-|1 |LUT2 | 1|
-+------+-----+------+
-
-Report Instance Areas:
-+------+---------+-------+------+
-| |Instance |Module |Cells |
-+------+---------+-------+------+
-|1 |top | | 1|
-+------+---------+-------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7239 ; free virtual = 19712
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.973 ; gain = 354.637 ; free physical = 7243 ; free virtual = 19716
-Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 1836.980 ; gain = 354.637 ; free physical = 7243 ; free virtual = 19716
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1854.051 ; gain = 0.000 ; free physical = 6057 ; free virtual = 18609
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1932.738 ; gain = 0.000 ; free physical = 5973 ; free virtual = 18527
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-INFO: [Common 17-83] Releasing license: Synthesis
-14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:03:41 . Memory (MB): peak = 1932.738 ; gain = 450.551 ; free physical = 6075 ; free virtual = 18629
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1932.738 ; gain = 0.000 ; free physical = 6075 ; free virtual = 18628
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 2276.922 ; gain = 344.184 ; free physical = 5304 ; free virtual = 17838
-WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
-INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP scalp_zynqps_util_vector_logic_0_0, cache-ID = 2e46931808b7c212
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2276.922 ; gain = 0.000 ; free physical = 5301 ; free virtual = 17836
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.dcp' has been generated.
-INFO: [runtcl-4] Executing : report_utilization -file scalp_zynqps_util_vector_logic_0_0_utilization_synth.rpt -pb scalp_zynqps_util_vector_logic_0_0_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Mon Sep 7 11:58:29 2020...
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_utilization_synth.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_utilization_synth.pb
deleted file mode 100644
index e3127a60803c7be6294c96e3c3ace390dc474fca..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_utilization_synth.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_utilization_synth.rpt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_utilization_synth.rpt
deleted file mode 100644
index 9d1649dcb83f64d151391342c825399cc3372e35..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0_utilization_synth.rpt
+++ /dev/null
@@ -1,172 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-| Date : Mon Sep 7 11:58:28 2020
-| Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-| Command : report_utilization -file scalp_zynqps_util_vector_logic_0_0_utilization_synth.rpt -pb scalp_zynqps_util_vector_logic_0_0_utilization_synth.pb
-| Design : scalp_zynqps_util_vector_logic_0_0
-| Device : 7z015clg485-2
-| Design State : Synthesized
----------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Memory
-3. DSP
-4. IO and GT Specific
-5. Clocking
-6. Specific Feature
-7. Primitives
-8. Black Boxes
-9. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+-------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------------------+------+-------+-----------+-------+
-| Slice LUTs* | 1 | 0 | 46200 | <0.01 |
-| LUT as Logic | 1 | 0 | 46200 | <0.01 |
-| LUT as Memory | 0 | 0 | 14400 | 0.00 |
-| Slice Registers | 0 | 0 | 92400 | 0.00 |
-| Register as Flip Flop | 0 | 0 | 92400 | 0.00 |
-| Register as Latch | 0 | 0 | 92400 | 0.00 |
-| F7 Muxes | 0 | 0 | 23100 | 0.00 |
-| F8 Muxes | 0 | 0 | 11550 | 0.00 |
-+-------------------------+------+-------+-----------+-------+
-* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0 | _ | - | - |
-| 0 | _ | - | Set |
-| 0 | _ | - | Reset |
-| 0 | _ | Set | - |
-| 0 | _ | Reset | - |
-| 0 | Yes | - | - |
-| 0 | Yes | - | Set |
-| 0 | Yes | - | Reset |
-| 0 | Yes | Set | - |
-| 0 | Yes | Reset | - |
-+-------+--------------+-------------+--------------+
-
-
-2. Memory
----------
-
-+----------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+----------------+------+-------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 95 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 95 | 0.00 |
-| RAMB18 | 0 | 0 | 190 | 0.00 |
-+----------------+------+-------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-3. DSP
-------
-
-+-----------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------+------+-------+-----------+-------+
-| DSPs | 0 | 0 | 160 | 0.00 |
-+-----------+------+-------+-----------+-------+
-
-
-4. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------------------------+------+-------+-----------+-------+
-| Bonded IOB | 0 | 0 | 150 | 0.00 |
-| Bonded IPADs | 0 | 0 | 14 | 0.00 |
-| Bonded OPADs | 0 | 0 | 8 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 3 | 0.00 |
-| PHASER_REF | 0 | 0 | 3 | 0.00 |
-| OUT_FIFO | 0 | 0 | 12 | 0.00 |
-| IN_FIFO | 0 | 0 | 12 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 3 | 0.00 |
-| IBUFDS | 0 | 0 | 144 | 0.00 |
-| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 12 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 12 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
-| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
-| ILOGIC | 0 | 0 | 150 | 0.00 |
-| OLOGIC | 0 | 0 | 150 | 0.00 |
-+-----------------------------+------+-------+-----------+-------+
-
-
-5. Clocking
------------
-
-+------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+------------+------+-------+-----------+-------+
-| BUFGCTRL | 0 | 0 | 32 | 0.00 |
-| BUFIO | 0 | 0 | 12 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 3 | 0.00 |
-| PLLE2_ADV | 0 | 0 | 3 | 0.00 |
-| BUFMRCE | 0 | 0 | 6 | 0.00 |
-| BUFHCE | 0 | 0 | 72 | 0.00 |
-| BUFR | 0 | 0 | 12 | 0.00 |
-+------------+------+-------+-----------+-------+
-
-
-6. Specific Feature
--------------------
-
-+-------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------+------+-------+-----------+-------+
-| BSCANE2 | 0 | 0 | 4 | 0.00 |
-| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
-| DNA_PORT | 0 | 0 | 1 | 0.00 |
-| EFUSE_USR | 0 | 0 | 1 | 0.00 |
-| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
-| ICAPE2 | 0 | 0 | 2 | 0.00 |
-| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
-| STARTUPE2 | 0 | 0 | 1 | 0.00 |
-| XADC | 0 | 0 | 1 | 0.00 |
-+-------------+------+-------+-----------+-------+
-
-
-7. Primitives
--------------
-
-+----------+------+---------------------+
-| Ref Name | Used | Functional Category |
-+----------+------+---------------------+
-| LUT2 | 1 | LUT |
-+----------+------+---------------------+
-
-
-8. Black Boxes
---------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
-9. Instantiated Netlists
-------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.jou b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.jou
deleted file mode 100644
index 9799cd3544131d7a7fe9137950fe2d140e7c6d04..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.jou
+++ /dev/null
@@ -1,12 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21733
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1
-# Command line: vivado -log scalp_zynqps_util_vector_logic_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_0_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/scalp_zynqps_util_vector_logic_0_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_util_vector_logic_0_0.tcl -notrace
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.pb
deleted file mode 100644
index 15e0f22aa9ba58c499ce3625d72fdcf3c3095c82..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_0_0_synth_1/vivado.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/ISEWrap.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/ISEWrap.sh
deleted file mode 100755
index f679f2e86873e3482adf4a51d722e917f3d4aab2..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/ISEWrap.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# ISEWrap.sh: Vivado Runs Script for UNIX
-# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-#
-
-HD_LOG=$1
-shift
-
-# CHECK for a STOP FILE
-if [ -f .stop.rst ]
-then
-echo "" >> $HD_LOG
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
-echo "" >> $HD_LOG
-exit 1
-fi
-
-ISE_STEP=$1
-shift
-
-# WRITE STEP HEADER to LOG
-echo "" >> $HD_LOG
-echo "*** Running $ISE_STEP" >> $HD_LOG
-echo " with args $@" >> $HD_LOG
-echo "" >> $HD_LOG
-
-# LAUNCH!
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
-
-# BEGIN file creation
-ISE_PID=$!
-if [ X != X$HOSTNAME ]
-then
-ISE_HOST=$HOSTNAME #bash
-else
-ISE_HOST=$HOST #csh
-fi
-ISE_USER=$USER
-
-ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
-ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
-
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
-/bin/touch $ISE_BEGINFILE
-echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
-echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
-echo " </Process>" >> $ISE_BEGINFILE
-echo "</ProcessHandle>" >> $ISE_BEGINFILE
-
-# WAIT for ISEStep to finish
-wait $ISE_PID
-
-# END/ERROR file creation
-RETVAL=$?
-if [ $RETVAL -eq 0 ]
-then
- /bin/touch .$ISE_STEP.end.rst
-else
- /bin/touch .$ISE_STEP.error.rst
-fi
-
-exit $RETVAL
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/gen_run.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/gen_run.xml
deleted file mode 100644
index cb3f0793f5f5d5d9843a9fd59274c032b99b4fd2..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/gen_run.xml
+++ /dev/null
@@ -1,54 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="scalp_zynqps_util_vector_logic_1_0_synth_1" LaunchPart="xc7z015clg485-2" LaunchTime="1599472465">
- <File Type="VDS-TIMING-PB" Name="scalp_zynqps_util_vector_logic_1_0_timing_summary_synth.pb"/>
- <File Type="VDS-TIMINGSUMMARY" Name="scalp_zynqps_util_vector_logic_1_0_timing_summary_synth.rpt"/>
- <File Type="RDS-DCP" Name="scalp_zynqps_util_vector_logic_1_0.dcp"/>
- <File Type="RDS-UTIL-PB" Name="scalp_zynqps_util_vector_logic_1_0_utilization_synth.pb"/>
- <File Type="RDS-UTIL" Name="scalp_zynqps_util_vector_logic_1_0_utilization_synth.rpt"/>
- <File Type="RDS-PROPCONSTRS" Name="scalp_zynqps_util_vector_logic_1_0_drc_synth.rpt"/>
- <File Type="RDS-RDS" Name="scalp_zynqps_util_vector_logic_1_0.vds"/>
- <File Type="REPORTS-TCL" Name="scalp_zynqps_util_vector_logic_1_0_reports.tcl"/>
- <File Type="PA-TCL" Name="scalp_zynqps_util_vector_logic_1_0.tcl"/>
- <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_util_vector_logic_1_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_util_vector_logic_1_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_util_vector_logic_1_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_util_vector_logic_1_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
- <Filter Type="Utils"/>
- <Config>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
- <Step Id="synth_design"/>
- </Strategy>
-</GenRun>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/htr.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/htr.txt
deleted file mode 100644
index ed45ba72f9adbb2e1780e3b1682f698c8790d5ff..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/htr.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-# the basic steps of a run. Note that runme.bat/sh needs
-# to be invoked for Vivado to track run status.
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-vivado -log scalp_zynqps_util_vector_logic_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_1_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/runme.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/runme.sh
deleted file mode 100755
index 936a387014dad63a808a5d4b8222dfb526a3917a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/runme.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# runme.sh: a Vivado-generated Runs Script for UNIX
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-if [ -z "$PATH" ]; then
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin
-else
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin:$PATH
-fi
-export PATH
-
-if [ -z "$LD_LIBRARY_PATH" ]; then
- LD_LIBRARY_PATH=
-else
- LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
-fi
-export LD_LIBRARY_PATH
-
-HD_PWD='/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1'
-cd "$HD_PWD"
-
-HD_LOG=runme.log
-/bin/touch $HD_LOG
-
-ISEStep="./ISEWrap.sh"
-EAStep()
-{
- $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
- if [ $? -ne 0 ]
- then
- exit
- fi
-}
-
-EAStep vivado -log scalp_zynqps_util_vector_logic_1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_1_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.dcp
deleted file mode 100644
index 62f466899c0664a4928dca81e66e553e3e156de1..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.tcl
deleted file mode 100644
index cbf1fef02aade50286fe7c13aba1783462cfc20f..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.tcl
+++ /dev/null
@@ -1,168 +0,0 @@
-#
-# Synthesis run script generated by Vivado
-#
-
-set TIME_start [clock seconds]
-proc create_report { reportName command } {
- set status "."
- append status $reportName ".fail"
- if { [file exists $status] } {
- eval file delete [glob $status]
- }
- send_msg_id runtcl-4 info "Executing : $command"
- set retval [eval catch { $command } msg]
- if { $retval != 0 } {
- set fp [open $status w]
- close $fp
- send_msg_id runtcl-5 warning "$msg"
- }
-}
-set_param project.vivado.isBlockSynthRun true
-set_msg_config -msgmgr_mode ooc_run
-create_project -in_memory -part xc7z015clg485-2
-
-set_param project.singleFileAddWarning.threshold 0
-set_param project.compositeFile.enableAutoGeneration 0
-set_param synth.vivado.isSynthRun true
-set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
-set_property webtalk.parent_dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt [current_project]
-set_property parent.project_path /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr [current_project]
-set_property default_lib xil_defaultlib [current_project]
-set_property target_language VHDL [current_project]
-set_property ip_repo_paths /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw [current_project]
-update_ip_catalog
-set_property ip_output_repo /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip [current_project]
-set_property ip_cache_permissions {read write} [current_project]
-read_ip -quiet /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci
-
-# Mark all dcp files as not used in implementation to prevent them from being
-# stitched into the results of this synthesis run. Any black boxes in the
-# design are intentionally left as such for best results. Dcp files will be
-# stitched into the design at a later time, either when this synthesis run is
-# opened, or when it is stitched into a dependent implementation run.
-foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
- set_property used_in_implementation false $dcp
-}
-set_param ips.enableIPCacheLiteLoad 1
-
-set cached_ip [config_ip_cache -export -no_bom -dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1 -new_name scalp_zynqps_util_vector_logic_1_0 -ip [get_ips scalp_zynqps_util_vector_logic_1_0]]
-
-if { $cached_ip eq {} } {
-close [open __synthesis_is_running__ w]
-
-synth_design -top scalp_zynqps_util_vector_logic_1_0 -part xc7z015clg485-2 -mode out_of_context
-
-#---------------------------------------------------------
-# Generate Checkpoint/Stub/Simulation Files For IP Cache
-#---------------------------------------------------------
-# disable binary constraint mode for IPCache checkpoints
-set_param constraints.enableBinaryConstraints false
-
-catch {
- write_checkpoint -force -noxdef -rename_prefix scalp_zynqps_util_vector_logic_1_0_ scalp_zynqps_util_vector_logic_1_0.dcp
-
- set ipCachedFiles {}
- write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_1_0_stub.v
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_1_0_stub.v
-
- write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_1_0_stub.vhdl
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_1_0_stub.vhdl
-
- write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
-
- write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_util_vector_logic_1_0_sim_netlist.vhdl
- lappend ipCachedFiles scalp_zynqps_util_vector_logic_1_0_sim_netlist.vhdl
-set TIME_taken [expr [clock seconds] - $TIME_start]
-
- config_ip_cache -add -dcp scalp_zynqps_util_vector_logic_1_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips scalp_zynqps_util_vector_logic_1_0]
-}
-
-rename_ref -prefix_all scalp_zynqps_util_vector_logic_1_0_
-
-# disable binary constraint mode for synth run checkpoints
-set_param constraints.enableBinaryConstraints false
-write_checkpoint -force -noxdef scalp_zynqps_util_vector_logic_1_0.dcp
-create_report "scalp_zynqps_util_vector_logic_1_0_synth_1_synth_report_utilization_0" "report_utilization -file scalp_zynqps_util_vector_logic_1_0_utilization_synth.rpt -pb scalp_zynqps_util_vector_logic_1_0_utilization_synth.pb"
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- write_verilog -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_verilog -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-
-} else {
-
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_sim_netlist.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-}; # end if cached_ip
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_1_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_1_0
- }
-}
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_1_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_util_vector_logic_1_0
- }
-}
-file delete __synthesis_is_running__
-close [open __synthesis_is_complete__ w]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.vds b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.vds
deleted file mode 100644
index 6db841ab105019688b8b25aaea5e93b6868cdd1b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.vds
+++ /dev/null
@@ -1,233 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21734
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1
-# Command line: vivado -log scalp_zynqps_util_vector_logic_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_1_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_util_vector_logic_1_0.tcl -notrace
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw'.
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
-Command: synth_design -top scalp_zynqps_util_vector_logic_1_0 -part xc7z015clg485-2 -mode out_of_context
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: Launching helper process for spawning children vivado processes
-INFO: Helper process launched with PID 21773
----------------------------------------------------------------------------------
-Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1628.934 ; gain = 145.570 ; free physical = 7872 ; free virtual = 20340
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'scalp_zynqps_util_vector_logic_1_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/synth/scalp_zynqps_util_vector_logic_1_0.v:57]
-INFO: [Synth 8-6157] synthesizing module 'util_vector_logic_v2_0_1_util_vector_logic' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v:45]
- Parameter C_OPERATION bound to: not - type: string
- Parameter C_SIZE bound to: 1 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'util_vector_logic_v2_0_1_util_vector_logic' (1#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/2137/hdl/util_vector_logic_v2_0_vl_rfs.v:45]
-INFO: [Synth 8-6155] done synthesizing module 'scalp_zynqps_util_vector_logic_1_0' (2#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/synth/scalp_zynqps_util_vector_logic_1_0.v:57]
-WARNING: [Synth 8-3331] design util_vector_logic_v2_0_1_util_vector_logic has unconnected port Op2[0]
----------------------------------------------------------------------------------
-Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1690.684 ; gain = 207.320 ; free physical = 7637 ; free virtual = 20105
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1693.652 ; gain = 210.289 ; free physical = 7587 ; free virtual = 20056
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7z015clg485-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1701.656 ; gain = 218.293 ; free physical = 7585 ; free virtual = 20053
----------------------------------------------------------------------------------
-INFO: [Device 21-403] Loading part xc7z015clg485-2
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 1709.594 ; gain = 226.230 ; free physical = 7575 ; free virtual = 20044
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-No constraint files found.
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
-Hierarchical RTL Component report
----------------------------------------------------------------------------------
-Finished RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 160 (col length:60)
-BRAMs: 190 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
-No constraint files found.
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-Warning: Parallel synthesis criteria is not met
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7209 ; free virtual = 19682
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-No constraint files found.
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7187 ; free virtual = 19660
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7186 ; free virtual = 19659
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----+------+
-| |Cell |Count |
-+------+-----+------+
-|1 |LUT1 | 1|
-+------+-----+------+
-
-Report Instance Areas:
-+------+---------+-------+------+
-| |Instance |Module |Cells |
-+------+---------+-------+------+
-|1 |top | | 1|
-+------+---------+-------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.000 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
-Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1838.008 ; gain = 354.637 ; free physical = 7158 ; free virtual = 19631
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1854.109 ; gain = 0.000 ; free physical = 6071 ; free virtual = 18624
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1933.766 ; gain = 0.000 ; free physical = 6067 ; free virtual = 18621
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-INFO: [Common 17-83] Releasing license: Synthesis
-14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:03:42 . Memory (MB): peak = 1933.766 ; gain = 450.551 ; free physical = 6172 ; free virtual = 18734
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1933.766 ; gain = 0.000 ; free physical = 6172 ; free virtual = 18733
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.dcp' has been generated.
-write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 2276.949 ; gain = 343.184 ; free physical = 5308 ; free virtual = 17841
-WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
-INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP scalp_zynqps_util_vector_logic_1_0, cache-ID = 0e76e0055f23d5f9
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2276.949 ; gain = 0.000 ; free physical = 5297 ; free virtual = 17831
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.dcp' has been generated.
-INFO: [runtcl-4] Executing : report_utilization -file scalp_zynqps_util_vector_logic_1_0_utilization_synth.rpt -pb scalp_zynqps_util_vector_logic_1_0_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Mon Sep 7 11:58:29 2020...
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_utilization_synth.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_utilization_synth.pb
deleted file mode 100644
index e3127a60803c7be6294c96e3c3ace390dc474fca..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_utilization_synth.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_utilization_synth.rpt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_utilization_synth.rpt
deleted file mode 100644
index e0018a6df679896e4f80f237cd9ea19fc66eb798..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0_utilization_synth.rpt
+++ /dev/null
@@ -1,172 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-| Date : Mon Sep 7 11:58:28 2020
-| Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-| Command : report_utilization -file scalp_zynqps_util_vector_logic_1_0_utilization_synth.rpt -pb scalp_zynqps_util_vector_logic_1_0_utilization_synth.pb
-| Design : scalp_zynqps_util_vector_logic_1_0
-| Device : 7z015clg485-2
-| Design State : Synthesized
----------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Memory
-3. DSP
-4. IO and GT Specific
-5. Clocking
-6. Specific Feature
-7. Primitives
-8. Black Boxes
-9. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+-------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------------------+------+-------+-----------+-------+
-| Slice LUTs* | 1 | 0 | 46200 | <0.01 |
-| LUT as Logic | 1 | 0 | 46200 | <0.01 |
-| LUT as Memory | 0 | 0 | 14400 | 0.00 |
-| Slice Registers | 0 | 0 | 92400 | 0.00 |
-| Register as Flip Flop | 0 | 0 | 92400 | 0.00 |
-| Register as Latch | 0 | 0 | 92400 | 0.00 |
-| F7 Muxes | 0 | 0 | 23100 | 0.00 |
-| F8 Muxes | 0 | 0 | 11550 | 0.00 |
-+-------------------------+------+-------+-----------+-------+
-* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0 | _ | - | - |
-| 0 | _ | - | Set |
-| 0 | _ | - | Reset |
-| 0 | _ | Set | - |
-| 0 | _ | Reset | - |
-| 0 | Yes | - | - |
-| 0 | Yes | - | Set |
-| 0 | Yes | - | Reset |
-| 0 | Yes | Set | - |
-| 0 | Yes | Reset | - |
-+-------+--------------+-------------+--------------+
-
-
-2. Memory
----------
-
-+----------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+----------------+------+-------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 95 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 95 | 0.00 |
-| RAMB18 | 0 | 0 | 190 | 0.00 |
-+----------------+------+-------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-3. DSP
-------
-
-+-----------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------+------+-------+-----------+-------+
-| DSPs | 0 | 0 | 160 | 0.00 |
-+-----------+------+-------+-----------+-------+
-
-
-4. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------------------------+------+-------+-----------+-------+
-| Bonded IOB | 0 | 0 | 150 | 0.00 |
-| Bonded IPADs | 0 | 0 | 14 | 0.00 |
-| Bonded OPADs | 0 | 0 | 8 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 3 | 0.00 |
-| PHASER_REF | 0 | 0 | 3 | 0.00 |
-| OUT_FIFO | 0 | 0 | 12 | 0.00 |
-| IN_FIFO | 0 | 0 | 12 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 3 | 0.00 |
-| IBUFDS | 0 | 0 | 144 | 0.00 |
-| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 12 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 12 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
-| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
-| ILOGIC | 0 | 0 | 150 | 0.00 |
-| OLOGIC | 0 | 0 | 150 | 0.00 |
-+-----------------------------+------+-------+-----------+-------+
-
-
-5. Clocking
------------
-
-+------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+------------+------+-------+-----------+-------+
-| BUFGCTRL | 0 | 0 | 32 | 0.00 |
-| BUFIO | 0 | 0 | 12 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 3 | 0.00 |
-| PLLE2_ADV | 0 | 0 | 3 | 0.00 |
-| BUFMRCE | 0 | 0 | 6 | 0.00 |
-| BUFHCE | 0 | 0 | 72 | 0.00 |
-| BUFR | 0 | 0 | 12 | 0.00 |
-+------------+------+-------+-----------+-------+
-
-
-6. Specific Feature
--------------------
-
-+-------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------+------+-------+-----------+-------+
-| BSCANE2 | 0 | 0 | 4 | 0.00 |
-| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
-| DNA_PORT | 0 | 0 | 1 | 0.00 |
-| EFUSE_USR | 0 | 0 | 1 | 0.00 |
-| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
-| ICAPE2 | 0 | 0 | 2 | 0.00 |
-| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
-| STARTUPE2 | 0 | 0 | 1 | 0.00 |
-| XADC | 0 | 0 | 1 | 0.00 |
-+-------------+------+-------+-----------+-------+
-
-
-7. Primitives
--------------
-
-+----------+------+---------------------+
-| Ref Name | Used | Functional Category |
-+----------+------+---------------------+
-| LUT1 | 1 | LUT |
-+----------+------+---------------------+
-
-
-8. Black Boxes
---------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
-9. Instantiated Netlists
-------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.jou b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.jou
deleted file mode 100644
index 5780d45656759cab8cb76559801d952f08e4afca..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.jou
+++ /dev/null
@@ -1,12 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21734
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1
-# Command line: vivado -log scalp_zynqps_util_vector_logic_1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_util_vector_logic_1_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/scalp_zynqps_util_vector_logic_1_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_util_vector_logic_1_0.tcl -notrace
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.pb
deleted file mode 100644
index be36729afb4c83c301d673fc6082a39aa7599daa..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_util_vector_logic_1_0_synth_1/vivado.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/ISEWrap.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/ISEWrap.sh
deleted file mode 100755
index f679f2e86873e3482adf4a51d722e917f3d4aab2..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/ISEWrap.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# ISEWrap.sh: Vivado Runs Script for UNIX
-# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-#
-
-HD_LOG=$1
-shift
-
-# CHECK for a STOP FILE
-if [ -f .stop.rst ]
-then
-echo "" >> $HD_LOG
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
-echo "" >> $HD_LOG
-exit 1
-fi
-
-ISE_STEP=$1
-shift
-
-# WRITE STEP HEADER to LOG
-echo "" >> $HD_LOG
-echo "*** Running $ISE_STEP" >> $HD_LOG
-echo " with args $@" >> $HD_LOG
-echo "" >> $HD_LOG
-
-# LAUNCH!
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
-
-# BEGIN file creation
-ISE_PID=$!
-if [ X != X$HOSTNAME ]
-then
-ISE_HOST=$HOSTNAME #bash
-else
-ISE_HOST=$HOST #csh
-fi
-ISE_USER=$USER
-
-ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
-ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
-
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
-/bin/touch $ISE_BEGINFILE
-echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
-echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
-echo " </Process>" >> $ISE_BEGINFILE
-echo "</ProcessHandle>" >> $ISE_BEGINFILE
-
-# WAIT for ISEStep to finish
-wait $ISE_PID
-
-# END/ERROR file creation
-RETVAL=$?
-if [ $RETVAL -eq 0 ]
-then
- /bin/touch .$ISE_STEP.end.rst
-else
- /bin/touch .$ISE_STEP.error.rst
-fi
-
-exit $RETVAL
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/gen_run.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/gen_run.xml
deleted file mode 100644
index 30f1528bf750cfb001abaddcbed63c9035a7bcad..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/gen_run.xml
+++ /dev/null
@@ -1,54 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="scalp_zynqps_vio_0_0_synth_1" LaunchPart="xc7z015clg485-2" LaunchTime="1599472465">
- <File Type="VDS-TIMING-PB" Name="scalp_zynqps_vio_0_0_timing_summary_synth.pb"/>
- <File Type="VDS-TIMINGSUMMARY" Name="scalp_zynqps_vio_0_0_timing_summary_synth.rpt"/>
- <File Type="RDS-DCP" Name="scalp_zynqps_vio_0_0.dcp"/>
- <File Type="RDS-UTIL-PB" Name="scalp_zynqps_vio_0_0_utilization_synth.pb"/>
- <File Type="RDS-UTIL" Name="scalp_zynqps_vio_0_0_utilization_synth.rpt"/>
- <File Type="RDS-PROPCONSTRS" Name="scalp_zynqps_vio_0_0_drc_synth.rpt"/>
- <File Type="RDS-RDS" Name="scalp_zynqps_vio_0_0.vds"/>
- <File Type="REPORTS-TCL" Name="scalp_zynqps_vio_0_0_reports.tcl"/>
- <File Type="PA-TCL" Name="scalp_zynqps_vio_0_0.tcl"/>
- <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_vio_0_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_vio_0_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/scalp_zynqps_vio_0_0">
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci">
- <FileInfo>
- <Attr Name="Library" Val="xil_defaultlib"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- <Attr Name="ProcessingOrder" Val="EARLY"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="TopModule" Val="scalp_zynqps_vio_0_0"/>
- <Option Name="UseBlackboxStub" Val="1"/>
- </Config>
- </FileSet>
- <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
- <Filter Type="Utils"/>
- <Config>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
- <Step Id="synth_design"/>
- </Strategy>
-</GenRun>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/htr.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/htr.txt
deleted file mode 100644
index 8d5854a2a598f08ca4cf0b60a892cbc826cdc100..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/htr.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-# the basic steps of a run. Note that runme.bat/sh needs
-# to be invoked for Vivado to track run status.
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-vivado -log scalp_zynqps_vio_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_vio_0_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/runme.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/runme.sh
deleted file mode 100755
index fe6581270a9ff3fd31a877b5edf864eceee7bce8..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/runme.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# runme.sh: a Vivado-generated Runs Script for UNIX
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-if [ -z "$PATH" ]; then
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin
-else
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin:$PATH
-fi
-export PATH
-
-if [ -z "$LD_LIBRARY_PATH" ]; then
- LD_LIBRARY_PATH=
-else
- LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
-fi
-export LD_LIBRARY_PATH
-
-HD_PWD='/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1'
-cd "$HD_PWD"
-
-HD_LOG=runme.log
-/bin/touch $HD_LOG
-
-ISEStep="./ISEWrap.sh"
-EAStep()
-{
- $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
- if [ $? -ne 0 ]
- then
- exit
- fi
-}
-
-EAStep vivado -log scalp_zynqps_vio_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_vio_0_0.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.dcp
deleted file mode 100644
index 4a0e84e0f7ae92d858b9b9a6fadd94bb49cb45b7..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.tcl
deleted file mode 100644
index 3760b26f74ffe36b8bd7b456bd45a354f3d56d6f..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.tcl
+++ /dev/null
@@ -1,170 +0,0 @@
-#
-# Synthesis run script generated by Vivado
-#
-
-set TIME_start [clock seconds]
-proc create_report { reportName command } {
- set status "."
- append status $reportName ".fail"
- if { [file exists $status] } {
- eval file delete [glob $status]
- }
- send_msg_id runtcl-4 info "Executing : $command"
- set retval [eval catch { $command } msg]
- if { $retval != 0 } {
- set fp [open $status w]
- close $fp
- send_msg_id runtcl-5 warning "$msg"
- }
-}
-set_param project.vivado.isBlockSynthRun true
-set_msg_config -msgmgr_mode ooc_run
-create_project -in_memory -part xc7z015clg485-2
-
-set_param project.singleFileAddWarning.threshold 0
-set_param project.compositeFile.enableAutoGeneration 0
-set_param synth.vivado.isSynthRun true
-set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
-set_property webtalk.parent_dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt [current_project]
-set_property parent.project_path /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr [current_project]
-set_property default_lib xil_defaultlib [current_project]
-set_property target_language VHDL [current_project]
-set_property ip_repo_paths /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw [current_project]
-update_ip_catalog
-set_property ip_output_repo /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip [current_project]
-set_property ip_cache_permissions {read write} [current_project]
-read_ip -quiet /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci
-set_property used_in_implementation false [get_files -all /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xdc]
-set_property used_in_implementation false [get_files -all /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_ooc.xdc]
-
-# Mark all dcp files as not used in implementation to prevent them from being
-# stitched into the results of this synthesis run. Any black boxes in the
-# design are intentionally left as such for best results. Dcp files will be
-# stitched into the design at a later time, either when this synthesis run is
-# opened, or when it is stitched into a dependent implementation run.
-foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
- set_property used_in_implementation false $dcp
-}
-set_param ips.enableIPCacheLiteLoad 1
-
-set cached_ip [config_ip_cache -export -no_bom -dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1 -new_name scalp_zynqps_vio_0_0 -ip [get_ips scalp_zynqps_vio_0_0]]
-
-if { $cached_ip eq {} } {
-close [open __synthesis_is_running__ w]
-
-synth_design -top scalp_zynqps_vio_0_0 -part xc7z015clg485-2 -mode out_of_context
-
-#---------------------------------------------------------
-# Generate Checkpoint/Stub/Simulation Files For IP Cache
-#---------------------------------------------------------
-# disable binary constraint mode for IPCache checkpoints
-set_param constraints.enableBinaryConstraints false
-
-catch {
- write_checkpoint -force -noxdef -rename_prefix scalp_zynqps_vio_0_0_ scalp_zynqps_vio_0_0.dcp
-
- set ipCachedFiles {}
- write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_vio_0_0_stub.v
- lappend ipCachedFiles scalp_zynqps_vio_0_0_stub.v
-
- write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_vio_0_0_stub.vhdl
- lappend ipCachedFiles scalp_zynqps_vio_0_0_stub.vhdl
-
- write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_vio_0_0_sim_netlist.v
- lappend ipCachedFiles scalp_zynqps_vio_0_0_sim_netlist.v
-
- write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ scalp_zynqps_vio_0_0_sim_netlist.vhdl
- lappend ipCachedFiles scalp_zynqps_vio_0_0_sim_netlist.vhdl
-set TIME_taken [expr [clock seconds] - $TIME_start]
-
- config_ip_cache -add -dcp scalp_zynqps_vio_0_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips scalp_zynqps_vio_0_0]
-}
-
-rename_ref -prefix_all scalp_zynqps_vio_0_0_
-
-# disable binary constraint mode for synth run checkpoints
-set_param constraints.enableBinaryConstraints false
-write_checkpoint -force -noxdef scalp_zynqps_vio_0_0.dcp
-create_report "scalp_zynqps_vio_0_0_synth_1_synth_report_utilization_0" "report_utilization -file scalp_zynqps_vio_0_0_utilization_synth.rpt -pb scalp_zynqps_vio_0_0_utilization_synth.pb"
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- write_verilog -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode synth_stub /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_verilog -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- write_vhdl -force -mode funcsim /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-
-} else {
-
-
-if { [catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.dcp /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.dcp
-} _RESULT ] } {
- send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
- error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_sim_netlist.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.v
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-if { [catch {
- file rename -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_sim_netlist.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_sim_netlist.vhdl
-} _RESULT ] } {
- puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
-}
-
-}; # end if cached_ip
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_vio_0_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.v /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_vio_0_0
- }
-}
-
-if {[file isdir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_vio_0_0]} {
- catch {
- file copy -force /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_stub.vhdl /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/ip/scalp_zynqps_vio_0_0
- }
-}
-file delete __synthesis_is_running__
-close [open __synthesis_is_complete__ w]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.vds b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.vds
deleted file mode 100644
index 0ea7e7202fc4dec24a9a7ad63001b58f63a331b4..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.vds
+++ /dev/null
@@ -1,495 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21732
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1
-# Command line: vivado -log scalp_zynqps_vio_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_vio_0_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_vio_0_0.tcl -notrace
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw'.
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
-Command: synth_design -top scalp_zynqps_vio_0_0 -part xc7z015clg485-2 -mode out_of_context
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Device 21-403] Loading part xc7z015clg485-2
-INFO: Launching helper process for spawning children vivado processes
-INFO: Helper process launched with PID 22480
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1871.676 ; gain = 202.570 ; free physical = 6194 ; free virtual = 18731
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'scalp_zynqps_vio_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/synth/scalp_zynqps_vio_0_0.v:59]
-WARNING: [Synth 8-3848] Net sl_iport0 in module/entity scalp_zynqps_vio_0_0 does not have driver. [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/synth/scalp_zynqps_vio_0_0.v:71]
-INFO: [Synth 8-6155] done synthesizing module 'scalp_zynqps_vio_0_0' (6#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/synth/scalp_zynqps_vio_0_0.v:59]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_rst
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Read
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[15]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[14]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[13]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[12]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[11]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[10]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[9]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[8]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[7]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[6]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[5]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[4]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[3]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[2]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Bus_Data_in[1]
-WARNING: [Synth 8-3331] design vio_v3_0_19_probe_out_one has unconnected port Internal_cnt_rst
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in0[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in1[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in2[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in3[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in4[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in5[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in6[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in7[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in8[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in9[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in10[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in11[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in12[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in13[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in14[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in15[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in16[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in17[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in18[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in19[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in20[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in21[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in22[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in23[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in24[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in25[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in26[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in27[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in28[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in29[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in30[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in31[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in32[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in33[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in34[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in35[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in36[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in37[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in38[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in39[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in40[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in41[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in42[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in43[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in44[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in45[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in46[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in47[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in48[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in49[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in50[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in51[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in52[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in53[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in54[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in55[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in56[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in57[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in58[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in59[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in60[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in61[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in62[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in63[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in64[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in65[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in66[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in67[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in68[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in69[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in70[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in71[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in72[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in73[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in74[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in75[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in76[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in77[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in78[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in79[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in80[0]
-WARNING: [Synth 8-3331] design vio_v3_0_19_vio has unconnected port probe_in81[0]
-INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1938.395 ; gain = 269.289 ; free physical = 6242 ; free virtual = 18776
----------------------------------------------------------------------------------
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1938.395 ; gain = 269.289 ; free physical = 6216 ; free virtual = 18751
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1938.395 ; gain = 269.289 ; free physical = 6216 ; free virtual = 18751
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1938.395 ; gain = 0.000 ; free physical = 6206 ; free virtual = 18738
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_ooc.xdc]
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_ooc.xdc]
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xdc]
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xdc]
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.113 ; gain = 0.000 ; free physical = 5975 ; free virtual = 18521
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2090.113 ; gain = 0.000 ; free physical = 5974 ; free virtual = 18521
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 6073 ; free virtual = 18636
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7z015clg485-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 6073 ; free virtual = 18636
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 6079 ; free virtual = 18643
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 6092 ; free virtual = 18657
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
-+---Registers :
- 128 Bit Registers := 1
- 16 Bit Registers := 7
- 7 Bit Registers := 1
- 5 Bit Registers := 1
- 3 Bit Registers := 2
- 1 Bit Registers := 14
-+---Muxes :
- 2 Input 16 Bit Muxes := 2
- 2 Input 1 Bit Muxes := 7
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
-Hierarchical RTL Component report
-Module vio_v3_0_19_probe_out_one
-Detailed RTL Component Info :
-+---Registers :
- 16 Bit Registers := 1
- 1 Bit Registers := 1
-+---Muxes :
- 2 Input 1 Bit Muxes := 1
-Module vio_v3_0_19_probe_out_all
-Detailed RTL Component Info :
-+---Registers :
- 16 Bit Registers := 1
- 1 Bit Registers := 3
-+---Muxes :
- 2 Input 1 Bit Muxes := 2
-Module xsdbs_v1_0_2_xsdbs
-Detailed RTL Component Info :
-+---Registers :
- 128 Bit Registers := 1
- 16 Bit Registers := 2
- 1 Bit Registers := 1
-+---Muxes :
- 2 Input 16 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 1
-Module vio_v3_0_19_decoder
-Detailed RTL Component Info :
-+---Registers :
- 16 Bit Registers := 2
- 7 Bit Registers := 1
- 5 Bit Registers := 1
- 3 Bit Registers := 2
- 1 Bit Registers := 9
-+---Muxes :
- 2 Input 16 Bit Muxes := 1
- 2 Input 1 Bit Muxes := 3
-Module vio_v3_0_19_vio
-Detailed RTL Component Info :
-+---Registers :
- 16 Bit Registers := 1
----------------------------------------------------------------------------------
-Finished RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 160 (col length:60)
-BRAMs: 190 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-Warning: Parallel synthesis criteria is not met
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] )
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[1]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[2]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[3]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[4]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[5]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[6]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[7]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[8]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[9]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[10]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[11]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[12]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[13]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[14]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
-INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15] )
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 6057 ; free virtual = 18610
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 5182 ; free virtual = 17736
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 5181 ; free virtual = 17735
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 5165 ; free virtual = 17720
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
-WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7141 ; free virtual = 19699
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7141 ; free virtual = 19699
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7139 ; free virtual = 19697
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7139 ; free virtual = 19696
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7144 ; free virtual = 19701
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7143 ; free virtual = 19701
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes:
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage:
-+------+-----+------+
-| |Cell |Count |
-+------+-----+------+
-|1 |LUT2 | 3|
-|2 |LUT3 | 24|
-|3 |LUT4 | 21|
-|4 |LUT5 | 13|
-|5 |LUT6 | 60|
-|6 |FDRE | 231|
-+------+-----+------+
-
-Report Instance Areas:
-+------+---------------------------------------+--------------------------+------+
-| |Instance |Module |Cells |
-+------+---------------------------------------+--------------------------+------+
-|1 |top | | 352|
-|2 | inst |vio_v3_0_19_vio | 352|
-|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248|
-|4 | DECODER_INST |vio_v3_0_19_decoder | 78|
-|5 | PROBE_OUT_ALL_INST |vio_v3_0_19_probe_out_all | 10|
-|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_19_probe_out_one | 3|
-+------+---------------------------------------+--------------------------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7143 ; free virtual = 19701
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 293 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2090.113 ; gain = 269.289 ; free physical = 7202 ; free virtual = 19759
-Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2090.113 ; gain = 421.008 ; free physical = 7202 ; free virtual = 19759
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2090.113 ; gain = 0.000 ; free physical = 7267 ; free virtual = 19825
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2093.082 ; gain = 0.000 ; free physical = 7197 ; free virtual = 19752
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-INFO: [Common 17-83] Releasing license: Synthesis
-45 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:03:59 . Memory (MB): peak = 2093.082 ; gain = 610.898 ; free physical = 7329 ; free virtual = 19884
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2093.082 ; gain = 0.000 ; free physical = 7328 ; free virtual = 19883
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.dcp' has been generated.
-WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
-INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP scalp_zynqps_vio_0_0, cache-ID = afab8f8185921798
-INFO: [Coretcl 2-1174] Renamed 5 cell refs.
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2117.094 ; gain = 0.000 ; free physical = 7326 ; free virtual = 19886
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.dcp' has been generated.
-INFO: [runtcl-4] Executing : report_utilization -file scalp_zynqps_vio_0_0_utilization_synth.rpt -pb scalp_zynqps_vio_0_0_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Mon Sep 7 11:58:36 2020...
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_utilization_synth.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_utilization_synth.pb
deleted file mode 100644
index 86882d6015363a6d0043a37b521ab881e00c14f0..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_utilization_synth.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_utilization_synth.rpt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_utilization_synth.rpt
deleted file mode 100644
index f225eb0fd7ab3e80c6a18c180268a0a2d3e13f7f..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0_utilization_synth.rpt
+++ /dev/null
@@ -1,177 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-| Date : Mon Sep 7 11:58:36 2020
-| Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-| Command : report_utilization -file scalp_zynqps_vio_0_0_utilization_synth.rpt -pb scalp_zynqps_vio_0_0_utilization_synth.pb
-| Design : scalp_zynqps_vio_0_0
-| Device : 7z015clg485-2
-| Design State : Synthesized
------------------------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Memory
-3. DSP
-4. IO and GT Specific
-5. Clocking
-6. Specific Feature
-7. Primitives
-8. Black Boxes
-9. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+-------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------------------+------+-------+-----------+-------+
-| Slice LUTs* | 102 | 0 | 46200 | 0.22 |
-| LUT as Logic | 102 | 0 | 46200 | 0.22 |
-| LUT as Memory | 0 | 0 | 14400 | 0.00 |
-| Slice Registers | 231 | 0 | 92400 | 0.25 |
-| Register as Flip Flop | 231 | 0 | 92400 | 0.25 |
-| Register as Latch | 0 | 0 | 92400 | 0.00 |
-| F7 Muxes | 0 | 0 | 23100 | 0.00 |
-| F8 Muxes | 0 | 0 | 11550 | 0.00 |
-+-------------------------+------+-------+-----------+-------+
-* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0 | _ | - | - |
-| 0 | _ | - | Set |
-| 0 | _ | - | Reset |
-| 0 | _ | Set | - |
-| 0 | _ | Reset | - |
-| 0 | Yes | - | - |
-| 0 | Yes | - | Set |
-| 0 | Yes | - | Reset |
-| 0 | Yes | Set | - |
-| 231 | Yes | Reset | - |
-+-------+--------------+-------------+--------------+
-
-
-2. Memory
----------
-
-+----------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+----------------+------+-------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 95 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 95 | 0.00 |
-| RAMB18 | 0 | 0 | 190 | 0.00 |
-+----------------+------+-------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-3. DSP
-------
-
-+-----------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------+------+-------+-----------+-------+
-| DSPs | 0 | 0 | 160 | 0.00 |
-+-----------+------+-------+-----------+-------+
-
-
-4. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------------------------+------+-------+-----------+-------+
-| Bonded IOB | 0 | 0 | 150 | 0.00 |
-| Bonded IPADs | 0 | 0 | 14 | 0.00 |
-| Bonded OPADs | 0 | 0 | 8 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 3 | 0.00 |
-| PHASER_REF | 0 | 0 | 3 | 0.00 |
-| OUT_FIFO | 0 | 0 | 12 | 0.00 |
-| IN_FIFO | 0 | 0 | 12 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 3 | 0.00 |
-| IBUFDS | 0 | 0 | 144 | 0.00 |
-| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 12 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 12 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
-| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
-| ILOGIC | 0 | 0 | 150 | 0.00 |
-| OLOGIC | 0 | 0 | 150 | 0.00 |
-+-----------------------------+------+-------+-----------+-------+
-
-
-5. Clocking
------------
-
-+------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+------------+------+-------+-----------+-------+
-| BUFGCTRL | 0 | 0 | 32 | 0.00 |
-| BUFIO | 0 | 0 | 12 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 3 | 0.00 |
-| PLLE2_ADV | 0 | 0 | 3 | 0.00 |
-| BUFMRCE | 0 | 0 | 6 | 0.00 |
-| BUFHCE | 0 | 0 | 72 | 0.00 |
-| BUFR | 0 | 0 | 12 | 0.00 |
-+------------+------+-------+-----------+-------+
-
-
-6. Specific Feature
--------------------
-
-+-------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------+------+-------+-----------+-------+
-| BSCANE2 | 0 | 0 | 4 | 0.00 |
-| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
-| DNA_PORT | 0 | 0 | 1 | 0.00 |
-| EFUSE_USR | 0 | 0 | 1 | 0.00 |
-| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
-| ICAPE2 | 0 | 0 | 2 | 0.00 |
-| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
-| STARTUPE2 | 0 | 0 | 1 | 0.00 |
-| XADC | 0 | 0 | 1 | 0.00 |
-+-------------+------+-------+-----------+-------+
-
-
-7. Primitives
--------------
-
-+----------+------+---------------------+
-| Ref Name | Used | Functional Category |
-+----------+------+---------------------+
-| FDRE | 231 | Flop & Latch |
-| LUT6 | 60 | LUT |
-| LUT3 | 24 | LUT |
-| LUT4 | 21 | LUT |
-| LUT5 | 13 | LUT |
-| LUT2 | 3 | LUT |
-+----------+------+---------------------+
-
-
-8. Black Boxes
---------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
-9. Instantiated Netlists
-------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.jou b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.jou
deleted file mode 100644
index 6f363df7fafcd04fee05cb3da0d1fbdf243a0ade..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.jou
+++ /dev/null
@@ -1,12 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:54:27 2020
-# Process ID: 21732
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1
-# Command line: vivado -log scalp_zynqps_vio_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps_vio_0_0.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/scalp_zynqps_vio_0_0.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps_vio_0_0.tcl -notrace
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.pb
deleted file mode 100644
index fa4405b919c63aae327144a042d720e060dc94db..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/scalp_zynqps_vio_0_0_synth_1/vivado.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/ISEWrap.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/ISEWrap.sh
deleted file mode 100755
index f679f2e86873e3482adf4a51d722e917f3d4aab2..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/ISEWrap.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# ISEWrap.sh: Vivado Runs Script for UNIX
-# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-#
-
-HD_LOG=$1
-shift
-
-# CHECK for a STOP FILE
-if [ -f .stop.rst ]
-then
-echo "" >> $HD_LOG
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
-echo "" >> $HD_LOG
-exit 1
-fi
-
-ISE_STEP=$1
-shift
-
-# WRITE STEP HEADER to LOG
-echo "" >> $HD_LOG
-echo "*** Running $ISE_STEP" >> $HD_LOG
-echo " with args $@" >> $HD_LOG
-echo "" >> $HD_LOG
-
-# LAUNCH!
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
-
-# BEGIN file creation
-ISE_PID=$!
-if [ X != X$HOSTNAME ]
-then
-ISE_HOST=$HOSTNAME #bash
-else
-ISE_HOST=$HOST #csh
-fi
-ISE_USER=$USER
-
-ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
-ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
-
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
-/bin/touch $ISE_BEGINFILE
-echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
-echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
-echo " </Process>" >> $ISE_BEGINFILE
-echo "</ProcessHandle>" >> $ISE_BEGINFILE
-
-# WAIT for ISEStep to finish
-wait $ISE_PID
-
-# END/ERROR file creation
-RETVAL=$?
-if [ $RETVAL -eq 0 ]
-then
- /bin/touch .$ISE_STEP.end.rst
-else
- /bin/touch .$ISE_STEP.error.rst
-fi
-
-exit $RETVAL
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/dont_touch.xdc b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/dont_touch.xdc
deleted file mode 100644
index 0f180a14532a9e008147dd1e222ce189ee10e557..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/dont_touch.xdc
+++ /dev/null
@@ -1,22 +0,0 @@
-# This file is automatically generated.
-# It contains project source information necessary for synthesis and implementation.
-
-# Block Designs: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
-# Block Designs: The module: 'scalp_zynqps' is the root of the design. Do not add the DONT_TOUCH constraint.
-
-# IP: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xci
-set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==scalp_zynqps_gnd_constant_0 || ORIG_REF_NAME==scalp_zynqps_gnd_constant_0} -quiet] -quiet
-
-# IP: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xci
-set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==scalp_zynqps_processing_system7_0_0 || ORIG_REF_NAME==scalp_zynqps_processing_system7_0_0} -quiet] -quiet
-
-# IP: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0.xci
-set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==scalp_zynqps_util_vector_logic_0_0 || ORIG_REF_NAME==scalp_zynqps_util_vector_logic_0_0} -quiet] -quiet
-
-# IP: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0.xci
-set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==scalp_zynqps_util_vector_logic_1_0 || ORIG_REF_NAME==scalp_zynqps_util_vector_logic_1_0} -quiet] -quiet
-
-# IP: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xci
-set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==scalp_zynqps_vio_0_0 || ORIG_REF_NAME==scalp_zynqps_vio_0_0} -quiet] -quiet
-
-# XDC: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps_ooc.xdc
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/gen_run.xml b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/gen_run.xml
deleted file mode 100644
index 5cf97caf0b331495de38fba2bb19a24cb8de3d5b..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/gen_run.xml
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7z015clg485-2" LaunchTime="1599472465">
- <File Type="VDS-TIMING-PB" Name="scalp_zynqps_timing_summary_synth.pb"/>
- <File Type="VDS-TIMINGSUMMARY" Name="scalp_zynqps_timing_summary_synth.rpt"/>
- <File Type="RDS-DCP" Name="scalp_zynqps.dcp"/>
- <File Type="PA-TCL" Name="scalp_zynqps.tcl"/>
- <File Type="REPORTS-TCL" Name="scalp_zynqps_reports.tcl"/>
- <File Type="RDS-RDS" Name="scalp_zynqps.vds"/>
- <File Type="RDS-PROPCONSTRS" Name="scalp_zynqps_drc_synth.rpt"/>
- <File Type="RDS-UTIL" Name="scalp_zynqps_utilization_synth.rpt"/>
- <File Type="RDS-UTIL-PB" Name="scalp_zynqps_utilization_synth.pb"/>
- <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
- <Filter Type="Srcs"/>
- <File Path="$PPRDIR/../.scripts/scalp_zynqps/scalp_zynqps.bd">
- <FileInfo>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="implementation"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <File Path="$PPRDIR/../../../../../hw/scalp_zynqps/src/hdl/scalp_zynqps.vhd">
- <FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
- <Attr Name="UsedIn" Val="synthesis"/>
- <Attr Name="UsedIn" Val="simulation"/>
- </FileInfo>
- </File>
- <Config>
- <Option Name="DesignMode" Val="RTL"/>
- <Option Name="TopModule" Val="scalp_zynqps"/>
- </Config>
- </FileSet>
- <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
- <Filter Type="Constrs"/>
- <Config>
- <Option Name="ConstrsType" Val="XDC"/>
- </Config>
- </FileSet>
- <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
- <Filter Type="Utils"/>
- <Config>
- <Option Name="TopAutoSet" Val="TRUE"/>
- </Config>
- </FileSet>
- <Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
- <Step Id="synth_design"/>
- </Strategy>
- <BlockFileSet Type="BlockSrcs" Name="scalp_zynqps_vio_0_0"/>
- <BlockFileSet Type="BlockSrcs" Name="scalp_zynqps_processing_system7_0_0"/>
- <BlockFileSet Type="BlockSrcs" Name="scalp_zynqps_util_vector_logic_1_0"/>
- <BlockFileSet Type="BlockSrcs" Name="scalp_zynqps_util_vector_logic_0_0"/>
-</GenRun>
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/htr.txt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/htr.txt
deleted file mode 100644
index 6cfd4603305fa797cb949d713d0d3dd2be04459d..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/htr.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-# the basic steps of a run. Note that runme.bat/sh needs
-# to be invoked for Vivado to track run status.
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-vivado -log scalp_zynqps.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/runme.sh b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/runme.sh
deleted file mode 100755
index 9719124715e4bae4666cf6487105b9fec8453dc9..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/runme.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/sh
-
-#
-# Vivado(TM)
-# runme.sh: a Vivado-generated Runs Script for UNIX
-# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-#
-
-if [ -z "$PATH" ]; then
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin
-else
- PATH=/opt/Xilinx/Vitis/2019.2/bin:/opt/Xilinx/Vivado/2019.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2019.2/bin:$PATH
-fi
-export PATH
-
-if [ -z "$LD_LIBRARY_PATH" ]; then
- LD_LIBRARY_PATH=
-else
- LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
-fi
-export LD_LIBRARY_PATH
-
-HD_PWD='/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1'
-cd "$HD_PWD"
-
-HD_LOG=runme.log
-/bin/touch $HD_LOG
-
-ISEStep="./ISEWrap.sh"
-EAStep()
-{
- $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
- if [ $? -ne 0 ]
- then
- exit
- fi
-}
-
-EAStep vivado -log scalp_zynqps.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps.tcl
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.dcp b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.dcp
deleted file mode 100644
index 366f382ea63aacdb3bb9c8675c355f1881d0e9ce..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.dcp and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.tcl b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.tcl
deleted file mode 100644
index 3d7621a3070f8351a0a344dda71379d3ce7bdfec..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.tcl
+++ /dev/null
@@ -1,61 +0,0 @@
-#
-# Synthesis run script generated by Vivado
-#
-
-set TIME_start [clock seconds]
-proc create_report { reportName command } {
- set status "."
- append status $reportName ".fail"
- if { [file exists $status] } {
- eval file delete [glob $status]
- }
- send_msg_id runtcl-4 info "Executing : $command"
- set retval [eval catch { $command } msg]
- if { $retval != 0 } {
- set fp [open $status w]
- close $fp
- send_msg_id runtcl-5 warning "$msg"
- }
-}
-create_project -in_memory -part xc7z015clg485-2
-
-set_param project.singleFileAddWarning.threshold 0
-set_param project.compositeFile.enableAutoGeneration 0
-set_param synth.vivado.isSynthRun true
-set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
-set_property webtalk.parent_dir /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt [current_project]
-set_property parent.project_path /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr [current_project]
-set_property default_lib xil_defaultlib [current_project]
-set_property target_language VHDL [current_project]
-set_property ip_repo_paths /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw [current_project]
-update_ip_catalog
-set_property ip_output_repo /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.cache/ip [current_project]
-set_property ip_cache_permissions {read write} [current_project]
-add_files /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
-set_property used_in_implementation false [get_files -all /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0.xdc]
-set_property used_in_implementation false [get_files -all /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0.xdc]
-set_property used_in_implementation false [get_files -all /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_ooc.xdc]
-set_property used_in_implementation false [get_files -all /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/scalp_zynqps_ooc.xdc]
-
-# Mark all dcp files as not used in implementation to prevent them from being
-# stitched into the results of this synthesis run. Any black boxes in the
-# design are intentionally left as such for best results. Dcp files will be
-# stitched into the design at a later time, either when this synthesis run is
-# opened, or when it is stitched into a dependent implementation run.
-foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
- set_property used_in_implementation false $dcp
-}
-read_xdc dont_touch.xdc
-set_property used_in_implementation false [get_files dont_touch.xdc]
-set_param ips.enableIPCacheLiteLoad 1
-close [open __synthesis_is_running__ w]
-
-synth_design -top scalp_zynqps -part xc7z015clg485-2
-
-
-# disable binary constraint mode for synth run checkpoints
-set_param constraints.enableBinaryConstraints false
-write_checkpoint -force -noxdef scalp_zynqps.dcp
-create_report "synth_1_synth_report_utilization_0" "report_utilization -file scalp_zynqps_utilization_synth.rpt -pb scalp_zynqps_utilization_synth.pb"
-file delete __synthesis_is_running__
-close [open __synthesis_is_complete__ w]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.vds b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.vds
deleted file mode 100644
index 2dfe57a5bf25877edf434e26c32a2014584bb40a..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.vds
+++ /dev/null
@@ -1,557 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:58:43 2020
-# Process ID: 22791
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1
-# Command line: vivado -log scalp_zynqps.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps.tcl -notrace
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/hw'.
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.2/data/ip'.
-Command: synth_design -top scalp_zynqps -part xc7z015clg485-2
-Starting synth_design
-Attempting to get a license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z015'
-INFO: [Device 21-403] Loading part xc7z015clg485-2
-INFO: Launching helper process for spawning children vivado processes
-INFO: Helper process launched with PID 23380
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1876.707 ; gain = 202.570 ; free physical = 8475 ; free virtual = 21047
----------------------------------------------------------------------------------
-INFO: [Synth 8-638] synthesizing module 'scalp_zynqps' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd:50]
-INFO: [Synth 8-3491] module 'scalp_zynqps_gnd_constant_0' declared at '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v:57' bound to instance 'gnd_constant' of component 'scalp_zynqps_gnd_constant_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd:259]
-INFO: [Synth 8-6157] synthesizing module 'scalp_zynqps_gnd_constant_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v:57]
-INFO: [Synth 8-6157] synthesizing module 'xlconstant_v1_1_6_xlconstant' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v:23]
- Parameter CONST_VAL bound to: 0 - type: integer
- Parameter CONST_WIDTH bound to: 1 - type: integer
-INFO: [Synth 8-6155] done synthesizing module 'xlconstant_v1_1_6_xlconstant' (1#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ipshared/34f7/hdl/xlconstant_v1_1_vl_rfs.v:23]
-INFO: [Synth 8-6155] done synthesizing module 'scalp_zynqps_gnd_constant_0' (2#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v:57]
-INFO: [Synth 8-3491] module 'scalp_zynqps_processing_system7_0_0' declared at '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_processing_system7_0_0_stub.vhdl:5' bound to instance 'processing_system7_0' of component 'scalp_zynqps_processing_system7_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd:263]
-INFO: [Synth 8-638] synthesizing module 'scalp_zynqps_processing_system7_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_processing_system7_0_0_stub.vhdl:90]
-INFO: [Synth 8-3491] module 'scalp_zynqps_util_vector_logic_0_0' declared at '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_util_vector_logic_0_0_stub.vhdl:5' bound to instance 'util_vector_logic_0' of component 'scalp_zynqps_util_vector_logic_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd:345]
-INFO: [Synth 8-638] synthesizing module 'scalp_zynqps_util_vector_logic_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_util_vector_logic_0_0_stub.vhdl:14]
-INFO: [Synth 8-3491] module 'scalp_zynqps_util_vector_logic_1_0' declared at '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_util_vector_logic_1_0_stub.vhdl:5' bound to instance 'util_vector_logic_1' of component 'scalp_zynqps_util_vector_logic_1_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd:351]
-INFO: [Synth 8-638] synthesizing module 'scalp_zynqps_util_vector_logic_1_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_util_vector_logic_1_0_stub.vhdl:13]
-INFO: [Synth 8-3491] module 'scalp_zynqps_vio_0_0' declared at '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_vio_0_0_stub.vhdl:5' bound to instance 'vio_0' of component 'scalp_zynqps_vio_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd:356]
-INFO: [Synth 8-638] synthesizing module 'scalp_zynqps_vio_0_0' [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/.Xil/Vivado-22791-xps13-debian/realtime/scalp_zynqps_vio_0_0_stub.vhdl:13]
-INFO: [Synth 8-256] done synthesizing module 'scalp_zynqps' (3#1) [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd:50]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1938.457 ; gain = 264.320 ; free physical = 8478 ; free virtual = 21053
----------------------------------------------------------------------------------
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1941.426 ; gain = 267.289 ; free physical = 8451 ; free virtual = 21049
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1941.426 ; gain = 267.289 ; free physical = 8451 ; free virtual = 21049
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1941.426 ; gain = 0.000 ; free physical = 8444 ; free virtual = 21042
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc] for cell 'processing_system7_0'
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc] for cell 'processing_system7_0'
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_in_context.xdc] for cell 'util_vector_logic_0'
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0/scalp_zynqps_util_vector_logic_0_0_in_context.xdc] for cell 'util_vector_logic_0'
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_in_context.xdc] for cell 'util_vector_logic_1'
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0/scalp_zynqps_util_vector_logic_1_0_in_context.xdc] for cell 'util_vector_logic_1'
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_in_context.xdc] for cell 'vio_0'
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0/scalp_zynqps_vio_0_0_in_context.xdc] for cell 'vio_0'
-Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/dont_touch.xdc]
-Finished Parsing XDC File [/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/dont_touch.xdc]
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2032.238 ; gain = 0.000 ; free physical = 8496 ; free virtual = 21058
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2032.238 ; gain = 0.000 ; free physical = 8496 ; free virtual = 21058
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8555 ; free virtual = 21117
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7z015clg485-2
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8555 ; free virtual = 21117
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 2).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 3).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 4).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 5).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 6).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 7).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 8).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 9).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 10).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 11).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 12).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 13).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 14).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 15).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 16).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 17).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 18).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 19).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 20).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 21).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 22).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 23).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 24).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 25).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 26).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 27).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 28).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 29).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 30).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 31).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 32).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 33).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 34).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 35).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 36).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 37).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 38).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 39).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 40).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 41).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 42).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 43).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 44).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 45).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 46).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 47).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 48).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 49).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 50).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 51).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 52).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 53).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 54).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 55).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 56).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 57).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 58).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 59).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 60).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 61).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 62).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 63).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 64).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 65).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 66).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 67).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 68).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 69).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 70).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 71).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 72).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 73).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 74).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 75).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 76).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 77).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 78).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 79).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 80).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 81).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 82).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 83).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 84).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 85).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 86).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 87).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 88).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 89).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 90).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 91).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 92).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 93).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 94).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 95).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 96).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 97).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 98).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 99).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 100).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 101).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 102).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 103).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 104).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 105).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 106).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 107).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 108).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 109).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 110).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 111).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 112).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 113).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 114).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 115).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 116).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 117).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 118).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 119).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 120).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 121).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 122).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 123).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 124).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 125).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 126).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 127).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 128).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 129).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 130).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 131).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 132).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 133).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 134).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 135).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 136).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 137).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 138).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 139).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 140).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 141).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 142).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 143).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 144).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 145).
-Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 146).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 147).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 148).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 149).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 150).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 151).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 152).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 153).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 154).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 155).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 156).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 157).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 158).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 159).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 160).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 161).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 162).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 163).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 164).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 165).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 166).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 167).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 168).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 169).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 170).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 171).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 172).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 173).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 174).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 175).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 176).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 177).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 178).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 179).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 180).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 181).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 182).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 183).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 184).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 185).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 186).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 187).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 188).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 189).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 190).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 191).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 192).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 193).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 194).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 195).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 196).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 197).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 198).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 199).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 200).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 201).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 202).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 203).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 204).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 205).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 206).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 207).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 208).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 209).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 210).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 211).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 212).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 213).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 214).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 215).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 216).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 217).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 218).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 219).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 220).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 221).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 222).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 223).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 224).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 225).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 226).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 227).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 228).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 229).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 230).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 231).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 232).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 233).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 234).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 235).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 236).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 237).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 238).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 239).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 240).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 241).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 242).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 243).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 244).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 245).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 246).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 247).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 248).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 249).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 250).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 251).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 252).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 253).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 254).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 255).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 256).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 257).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 258).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 259).
-Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 260).
-Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/scalp_zynqps/ip/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0/scalp_zynqps_processing_system7_0_0_in_context.xdc, line 261).
-Applied set_property DONT_TOUCH = true for gnd_constant. (constraint file auto generated constraint, line ).
-Applied set_property DONT_TOUCH = true for processing_system7_0. (constraint file auto generated constraint, line ).
-Applied set_property DONT_TOUCH = true for util_vector_logic_0. (constraint file auto generated constraint, line ).
-Applied set_property DONT_TOUCH = true for util_vector_logic_1. (constraint file auto generated constraint, line ).
-Applied set_property DONT_TOUCH = true for vio_0. (constraint file auto generated constraint, line ).
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8555 ; free virtual = 21117
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8556 ; free virtual = 21119
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start RTL Component Statistics
----------------------------------------------------------------------------------
-Detailed RTL Component Info :
----------------------------------------------------------------------------------
-Finished RTL Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
-Hierarchical RTL Component report
----------------------------------------------------------------------------------
-Finished RTL Hierarchical Component Statistics
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 160 (col length:60)
-BRAMs: 190 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
-Warning: Parallel synthesis criteria is not met
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8552 ; free virtual = 21119
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8416 ; free virtual = 20990
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8416 ; free virtual = 20990
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8414 ; free virtual = 20988
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8350 ; free virtual = 20953
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8350 ; free virtual = 20953
----------------------------------------------------------------------------------
-
-Report RTL Partitions:
-+-+--------------+------------+----------+
-| |RTL Partition |Replication |Instances |
-+-+--------------+------------+----------+
-+-+--------------+------------+----------+
-
-Report Check Netlist:
-+------+------------------+-------+---------+-------+------------------+
-| |Item |Errors |Warnings |Status |Description |
-+------+------------------+-------+---------+-------+------------------+
-|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
-+------+------------------+-------+---------+-------+------------------+
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8350 ; free virtual = 20953
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8350 ; free virtual = 20953
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8350 ; free virtual = 20953
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8350 ; free virtual = 20953
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes:
-+------+------------------------------------+----------+
-| |BlackBox name |Instances |
-+------+------------------------------------+----------+
-|1 |scalp_zynqps_processing_system7_0_0 | 1|
-|2 |scalp_zynqps_util_vector_logic_0_0 | 1|
-|3 |scalp_zynqps_util_vector_logic_1_0 | 1|
-|4 |scalp_zynqps_vio_0_0 | 1|
-+------+------------------------------------+----------+
-
-Report Cell Usage:
-+------+-------------------------------------------+------+
-| |Cell |Count |
-+------+-------------------------------------------+------+
-|1 |scalp_zynqps_processing_system7_0_0_bbox_0 | 1|
-|2 |scalp_zynqps_util_vector_logic_0_0_bbox_1 | 1|
-|3 |scalp_zynqps_util_vector_logic_1_0_bbox_2 | 1|
-|4 |scalp_zynqps_vio_0_0_bbox_3 | 1|
-|5 |IBUF | 1|
-|6 |OBUF | 5|
-+------+-------------------------------------------+------+
-
-Report Instance Areas:
-+------+---------------+----------------------------+------+
-| |Instance |Module |Cells |
-+------+---------------+----------------------------+------+
-|1 |top | | 210|
-|2 | gnd_constant |scalp_zynqps_gnd_constant_0 | 0|
-+------+---------------+----------------------------+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8350 ; free virtual = 20953
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2032.238 ; gain = 267.289 ; free physical = 8405 ; free virtual = 21008
-Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2032.238 ; gain = 358.102 ; free physical = 8405 ; free virtual = 21008
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2032.238 ; gain = 0.000 ; free physical = 8489 ; free virtual = 21092
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2038.051 ; gain = 0.000 ; free physical = 8423 ; free virtual = 21034
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-INFO: [Common 17-83] Releasing license: Synthesis
-27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:03:51 . Memory (MB): peak = 2038.051 ; gain = 600.922 ; free physical = 8545 ; free virtual = 21156
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2038.051 ; gain = 0.000 ; free physical = 8545 ; free virtual = 21156
-WARNING: [Constraints 18-5210] No constraints selected for write.
-Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
-INFO: [Common 17-1381] The checkpoint '/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.dcp' has been generated.
-INFO: [runtcl-4] Executing : report_utilization -file scalp_zynqps_utilization_synth.rpt -pb scalp_zynqps_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Mon Sep 7 12:02:44 2020...
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps_utilization_synth.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps_utilization_synth.pb
deleted file mode 100644
index eb20cbf30e81b3af79ea9cbdc52ef8c9b1f2d9c8..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps_utilization_synth.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps_utilization_synth.rpt b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps_utilization_synth.rpt
deleted file mode 100644
index 5333e97ef63d0a9d608279f05aad2a496e77d31f..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps_utilization_synth.rpt
+++ /dev/null
@@ -1,178 +0,0 @@
-Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
-| Date : Mon Sep 7 12:02:44 2020
-| Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
-| Command : report_utilization -file scalp_zynqps_utilization_synth.rpt -pb scalp_zynqps_utilization_synth.pb
-| Design : scalp_zynqps
-| Device : 7z015clg485-2
-| Design State : Synthesized
--------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Memory
-3. DSP
-4. IO and GT Specific
-5. Clocking
-6. Specific Feature
-7. Primitives
-8. Black Boxes
-9. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+-------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------------------+------+-------+-----------+-------+
-| Slice LUTs* | 0 | 0 | 46200 | 0.00 |
-| LUT as Logic | 0 | 0 | 46200 | 0.00 |
-| LUT as Memory | 0 | 0 | 14400 | 0.00 |
-| Slice Registers | 0 | 0 | 92400 | 0.00 |
-| Register as Flip Flop | 0 | 0 | 92400 | 0.00 |
-| Register as Latch | 0 | 0 | 92400 | 0.00 |
-| F7 Muxes | 0 | 0 | 23100 | 0.00 |
-| F8 Muxes | 0 | 0 | 11550 | 0.00 |
-+-------------------------+------+-------+-----------+-------+
-* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0 | _ | - | - |
-| 0 | _ | - | Set |
-| 0 | _ | - | Reset |
-| 0 | _ | Set | - |
-| 0 | _ | Reset | - |
-| 0 | Yes | - | - |
-| 0 | Yes | - | Set |
-| 0 | Yes | - | Reset |
-| 0 | Yes | Set | - |
-| 0 | Yes | Reset | - |
-+-------+--------------+-------------+--------------+
-
-
-2. Memory
----------
-
-+----------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+----------------+------+-------+-----------+-------+
-| Block RAM Tile | 0 | 0 | 95 | 0.00 |
-| RAMB36/FIFO* | 0 | 0 | 95 | 0.00 |
-| RAMB18 | 0 | 0 | 190 | 0.00 |
-+----------------+------+-------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-3. DSP
-------
-
-+-----------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------+------+-------+-----------+-------+
-| DSPs | 0 | 0 | 160 | 0.00 |
-+-----------+------+-------+-----------+-------+
-
-
-4. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-----------------------------+------+-------+-----------+-------+
-| Bonded IOB | 6 | 0 | 150 | 4.00 |
-| Bonded IPADs | 0 | 0 | 14 | 0.00 |
-| Bonded OPADs | 0 | 0 | 8 | 0.00 |
-| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
-| PHY_CONTROL | 0 | 0 | 3 | 0.00 |
-| PHASER_REF | 0 | 0 | 3 | 0.00 |
-| OUT_FIFO | 0 | 0 | 12 | 0.00 |
-| IN_FIFO | 0 | 0 | 12 | 0.00 |
-| IDELAYCTRL | 0 | 0 | 3 | 0.00 |
-| IBUFDS | 0 | 0 | 144 | 0.00 |
-| GTPE2_CHANNEL | 0 | 0 | 4 | 0.00 |
-| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 12 | 0.00 |
-| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 12 | 0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
-| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
-| ILOGIC | 0 | 0 | 150 | 0.00 |
-| OLOGIC | 0 | 0 | 150 | 0.00 |
-+-----------------------------+------+-------+-----------+-------+
-
-
-5. Clocking
------------
-
-+------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+------------+------+-------+-----------+-------+
-| BUFGCTRL | 0 | 0 | 32 | 0.00 |
-| BUFIO | 0 | 0 | 12 | 0.00 |
-| MMCME2_ADV | 0 | 0 | 3 | 0.00 |
-| PLLE2_ADV | 0 | 0 | 3 | 0.00 |
-| BUFMRCE | 0 | 0 | 6 | 0.00 |
-| BUFHCE | 0 | 0 | 72 | 0.00 |
-| BUFR | 0 | 0 | 12 | 0.00 |
-+------------+------+-------+-----------+-------+
-
-
-6. Specific Feature
--------------------
-
-+-------------+------+-------+-----------+-------+
-| Site Type | Used | Fixed | Available | Util% |
-+-------------+------+-------+-----------+-------+
-| BSCANE2 | 0 | 0 | 4 | 0.00 |
-| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
-| DNA_PORT | 0 | 0 | 1 | 0.00 |
-| EFUSE_USR | 0 | 0 | 1 | 0.00 |
-| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
-| ICAPE2 | 0 | 0 | 2 | 0.00 |
-| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
-| STARTUPE2 | 0 | 0 | 1 | 0.00 |
-| XADC | 0 | 0 | 1 | 0.00 |
-+-------------+------+-------+-----------+-------+
-
-
-7. Primitives
--------------
-
-+----------+------+---------------------+
-| Ref Name | Used | Functional Category |
-+----------+------+---------------------+
-| OBUF | 5 | IO |
-| IBUF | 1 | IO |
-+----------+------+---------------------+
-
-
-8. Black Boxes
---------------
-
-+-------------------------------------+------+
-| Ref Name | Used |
-+-------------------------------------+------+
-| scalp_zynqps_vio_0_0 | 1 |
-| scalp_zynqps_util_vector_logic_1_0 | 1 |
-| scalp_zynqps_util_vector_logic_0_0 | 1 |
-| scalp_zynqps_processing_system7_0_0 | 1 |
-+-------------------------------------+------+
-
-
-9. Instantiated Netlists
-------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.jou b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.jou
deleted file mode 100644
index 3010d23c1ea89b5f0cfca3a91666b70881fad743..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.jou
+++ /dev/null
@@ -1,12 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2019.2 (64-bit)
-# SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
-# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
-# Start of session at: Mon Sep 7 11:58:43 2020
-# Process ID: 22791
-# Current directory: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1
-# Command line: vivado -log scalp_zynqps.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source scalp_zynqps.tcl
-# Log file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/scalp_zynqps.vds
-# Journal file: /home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.jou
-#-----------------------------------------------------------
-source scalp_zynqps.tcl -notrace
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.pb b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.pb
deleted file mode 100644
index cd7526dd8a46f02418028999a8bc057d4b18a779..0000000000000000000000000000000000000000
Binary files a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.runs/synth_1/vivado.pb and /dev/null differ
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr b/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr
deleted file mode 100644
index 2641caec1724fbb657f0d14cb77d0e7920ad8247..0000000000000000000000000000000000000000
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr
+++ /dev/null
@@ -1,357 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2019.2 (64-bit) -->
-<!-- -->
-<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
-
-<Project Version="7" Minor="44" Path="/home/jo/Documents/Projets/Hepia/scalp_firmware/soc/vivado/scalp_zynqps/2019.2/lin64/scalp_zynqps/scalp_zynqps.xpr">
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