From 8b7824bf8a610c8e353c729da39e6eb4aaf307cb Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Fri, 7 May 2021 09:01:28 +0200
Subject: [PATCH] updated Scalp Router for debugging
---
.../2020.2/src/hdl/scalp_firmware.vhd | 44 ++++++++++++-------
1 file changed, 28 insertions(+), 16 deletions(-)
diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index d16273d..d0a23a7 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
--- Last update: 2021-05-06
+-- Last update: 2021-05-07
--
---------------------------------------------------------------------------------
@@ -539,10 +539,10 @@ architecture arch of scalp_firmware is
-- attribute keep of NorthTXM2SxD : signal is "true";
-- attribute mark_debug of NorthTXS2MxD : signal is "true";
-- attribute keep of NorthTXS2MxD : signal is "true";
- -- attribute mark_debug of EastTXM2SxD : signal is "true";
- -- attribute keep of EastTXM2SxD : signal is "true";
- -- attribute mark_debug of EastTXS2MxD : signal is "true";
- -- attribute keep of EastTXS2MxD : signal is "true";
+ attribute mark_debug of EastTXM2SxD : signal is "true";
+ attribute keep of EastTXM2SxD : signal is "true";
+ attribute mark_debug of EastTXS2MxD : signal is "true";
+ attribute keep of EastTXS2MxD : signal is "true";
-- attribute mark_debug of SouthTXM2SxD : signal is "true";
-- attribute keep of SouthTXM2SxD : signal is "true";
-- attribute mark_debug of SouthTXS2MxD : signal is "true";
@@ -1124,17 +1124,29 @@ begin
TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
QoSVectorxDI => QoSVectorxD);
- ScalpAxis2SPxI : entity work.scalp_axis_to_sp
- generic map (
- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
- C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY)
- port map (
- SysClkxCI => AuroraClkMasterxC.UserClkxC,
- SysRstxRNAI => ScalpRouterResetxRNA,
- ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
- ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
- ScalpPacketxDO => ScalpPacketLocalxD,
- ScalpPacketValidxSO => ScalpPacketValidLocalxS);
+ ReadLocalxP : process (AuroraClkMasterxC.UserClkxC,
+ ScalpRouterResetxRNA) is
+ begin -- process ReadLocalxP
+ if ScalpRouterResetxRNA = '0' then
+ TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '0';
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ if TXAxism2sVectorxD(C_LOCAL_IF_ID).ValidxS = '1' then
+ TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '1';
+ end if;
+ end if;
+ end process ReadLocalxP;
+
+ -- ScalpAxis2SPxI : entity work.scalp_axis_to_sp
+ -- generic map (
+ -- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
+ -- C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY)
+ -- port map (
+ -- SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- SysRstxRNAI => ScalpRouterResetxRNA,
+ -- ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
+ -- ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ -- ScalpPacketxDO => ScalpPacketLocalxD,
+ -- ScalpPacketValidxSO => ScalpPacketValidLocalxS);
WritePacketxB : block is
begin -- block WritePacketxB
--
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