diff --git a/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd b/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
index 1d9fdbad4c968f7333743588f5d2b5176362b8f9..3f8147f594fecc1378796dd5159aa026b33fe282 100644
--- a/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
+++ b/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_fast_router_firmware
--
--- Last update: 2021-09-29
+-- Last update: 2021-10-22
--
---------------------------------------------------------------------------------
@@ -356,6 +356,22 @@ architecture arch of scalp_fast_router_firmware is
AxisFifoErrorxDO : out t_axi4fifo_error);
end component scalp_aurora_phy;
+ component scalp_router is
+ generic (
+ C_SCALP_NUMBER_OF_INTERFACE : integer range 0 to 255;
+ C_SCALP_SCHEDULER_STRATEGY : string);
+ port (
+ SysClkxCI : in std_ulogic;
+ SysRstxRNAI : in std_ulogic;
+ LocNetAddrxDI : in t_scalp_netaddr;
+ RXAxism2sVectorxDI : in t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ RXAxiss2mVectorxDO : out t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ TXAxism2sVectorxDO : out t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ TXAxiss2mVectorxDI : in t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ QoSVectorPyhStatusxDI : in t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0));
+ end component scalp_router;
+
-- Signals
-- Clocks
-- Processing system clock
@@ -442,11 +458,13 @@ architecture arch of scalp_fast_router_firmware is
signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal QoSVectorPhyStatusxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
-- Scalp Axi Lite interface and IRQ
-- Zynq Reg Bank
signal LocalNetAddrxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RGBLed0xD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RGBLed1xD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal QoSPhyStatusxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal DMARXm2sxD : t_axi4m2s := C_NO_AXI4_M2S;
signal DMARXs2mxD : t_axi4s2m := C_NO_AXI4_S2M;
signal DMATXm2sxD : t_axi4m2s := C_NO_AXI4_M2S;
@@ -458,17 +476,19 @@ architecture arch of scalp_fast_router_firmware is
signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
- -- attribute mark_debug of LocNetAddrxD : signal is "true";
- -- attribute keep of LocNetAddrxD : signal is "true";
+ -- attribute mark_debug of QoSVectorPhyStatusxD : signal is "true";
+ -- attribute keep of QoSVectorPhyStatusxD : signal is "true";
+ -- attribute mark_debug of QoSPhyStatusxD : signal is "true";
+ -- attribute keep of QoSPhyStatusxD : signal is "true";
begin
@@ -516,6 +536,7 @@ begin
LocalNetAddrxDO => LocalNetAddrxD,
RGBLed0xDO => RGBLed0xD,
RGBLed1xDO => RGBLed1xD,
+ QoSPhyStatusxDI => QoSPhyStatusxD,
-- RX
DMARXm2sxDI => DMARXm2sxD,
DMARXs2mxDO => DMARXs2mxD,
@@ -984,19 +1005,46 @@ begin
end generate ScalpDMALoopBackxG;
+ QoSLaneChanUpxB : block is
+
+ signal PhyStatusxD : std_ulogic_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => '0');
+
+ begin -- block QoSLaneChanUpxB
+
+ -- Without TOP, BOTTOM and LOCAL (Only for GTP)
+ QoSLaneChanUpxG : for i in 0 to (C_SCALP_NUMBER_OF_INTERFACE - 4) generate
+
+ PhyStatusxAS : PhyStatusxD(i) <= (AuroraStatusxD.LaneUpxD(i)(0) and AuroraStatusxD.ChannelUpxD(i));
+ QoSVectorPhyStatusxAS : QoSVectorPhyStatusxD(i) <= to_unsigned(scalp_to_integer(PhyStatusxD(i)), C_SCALP_QOS_SIZE);
+ -- Register
+ QoSPhyStatusxAS : QoSPhyStatusxD(i) <= (AuroraStatusxD.LaneUpxD(i)(0) and AuroraStatusxD.ChannelUpxD(i));
+
+ end generate QoSLaneChanUpxG;
+
+ QoSVectorPhyStatusTopxAS : QoSVectorPhyStatusxD(C_TOP_IF_ID) <= to_unsigned(0, C_SCALP_QOS_SIZE);
+ QoSVectorPhyStatusBottomxAS : QoSVectorPhyStatusxD(C_BOTTOM_IF_ID) <= to_unsigned(0, C_SCALP_QOS_SIZE);
+ QoSVectorPhyStatusLocalxAS : QoSVectorPhyStatusxD(C_LOCAL_IF_ID) <= to_unsigned(1, C_SCALP_QOS_SIZE);
+ -- Register
+ QoSPhyStatusTopxAS : QoSPhyStatusxD(C_TOP_IF_ID) <= '0';
+ QoSPhyStatusBottomxAS : QoSPhyStatusxD(C_BOTTOM_IF_ID) <= '0';
+ QoSPhyStatusLocalxAS : QoSPhyStatusxD(C_LOCAL_IF_ID) <= '1';
+
+ end block QoSLaneChanUpxB;
+
ScalpRouterxI : entity work.scalp_router
generic map (
C_SCALP_NUMBER_OF_INTERFACE => C_SCALP_NUMBER_OF_INTERFACE,
C_SCALP_SCHEDULER_STRATEGY => C_SCALP_SCHEDULER_STRATEGY)
port map (
- SysClkxCI => AuroraClkMasterxC.UserClkxC,
- SysRstxRNAI => ScalpRouterResetxRNA,
- LocNetAddrxDI => LocNetAddrxD,
- RXAxism2sVectorxDI => RXAxism2sVectorxD,
- RXAxiss2mVectorxDO => RXAxiss2mVectorxD,
- TXAxism2sVectorxDO => TXAxism2sVectorxD,
- TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
- QoSVectorxDI => QoSVectorxD);
+ SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ SysRstxRNAI => ScalpRouterResetxRNA,
+ LocNetAddrxDI => LocNetAddrxD,
+ RXAxism2sVectorxDI => RXAxism2sVectorxD,
+ RXAxiss2mVectorxDO => RXAxiss2mVectorxD,
+ TXAxism2sVectorxDO => TXAxism2sVectorxD,
+ TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
+ QoSVectorxDI => QoSVectorxD,
+ QoSVectorPyhStatusxDI => QoSVectorPhyStatusxD);
end block NetworkLayerxB;
diff --git a/ips/hw/scalp_fast_router_registers/component.xml b/ips/hw/scalp_fast_router_registers/component.xml
index 57836391d464f5f49c88560897fdb88e1eda6691..b3245dd2dea9f6245c6a08598da7ac594bd009a0 100644
--- a/ips/hw/scalp_fast_router_registers/component.xml
+++ b/ips/hw/scalp_fast_router_registers/component.xml
@@ -3,7 +3,7 @@
<spirit:vendor>hepia.hesge.ch</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>scalp_fast_router_registers</spirit:name>
- <spirit:version>1.0</spirit:version>
+ <spirit:version>1.3</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>SAxiClkxCI</spirit:name>
@@ -28,7 +28,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
- <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_RESET">DMAFifoWrDataCntxDO:DMAFifoRrDataCntxDO:LocalNetAddrxDO:RGBLed0xDO:RGBLed1xDO:DMAFifoStatusxDI:DMAFifoWrDataCntxDI:DMAFifoRrDataCntxDI:SAxiRstxRANI:DMAFifoTXWrDataCntxDI:DMAFifoTXRrDataCntxDI:DMAFifoTXStatusxDI:DMAFifoRXWrDataCntxDI:DMAFifoRXRrDataCntxDI:DMAFifoRXStatusxDI</spirit:value>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_RESET">DMAFifoWrDataCntxDO:DMAFifoRrDataCntxDO:LocalNetAddrxDO:RGBLed0xDO:RGBLed1xDO:DMAFifoStatusxDI:DMAFifoWrDataCntxDI:DMAFifoRrDataCntxDI:SAxiRstxRANI:DMAFifoTXWrDataCntxDI:DMAFifoTXRrDataCntxDI:DMAFifoTXStatusxDI:DMAFifoRXWrDataCntxDI:DMAFifoRXRrDataCntxDI:DMAFifoRXStatusxDI:QoSPhyStatusxDI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
@@ -373,6 +373,23 @@
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>QoSPhyStatusxDI</spirit:name>
+ <spirit:displayName>QoSPhyStatusxDI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>QoSPhyStatusxDI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
@@ -400,7 +417,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>3899dd1b</spirit:value>
+ <spirit:value>1322956f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -416,7 +433,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>3899dd1b</spirit:value>
+ <spirit:value>1322956f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -864,6 +881,23 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
+ <spirit:port>
+ <spirit:name>QoSPhyStatusxDI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_DATA_SIZE')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
@@ -919,7 +953,7 @@
<spirit:file>
<spirit:name>src/hdl/scalp_fast_router_registers.vhd</spirit:name>
<spirit:userFileType>vhdlSource-2008</spirit:userFileType>
- <spirit:userFileType>CHECKSUM_3899dd1b</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_1322956f</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -932,14 +966,14 @@
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>xgui/scalp_fast_router_registers_v1_0.tcl</spirit:name>
+ <spirit:name>xgui/scalp_fast_router_registers_v1_3.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_94c74469</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
- <spirit:description>scalp_fast_router_registers_v1_0</spirit:description>
+ <spirit:description>scalp_fast_router_registers_v1_3</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_AXI4_ARADDR_SIZE</spirit:name>
@@ -1019,12 +1053,12 @@
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>scalp_fast_router_registers_v1_0</xilinx:displayName>
+ <xilinx:displayName>scalp_fast_router_registers_v1_3</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:vendorDisplayName>Scalp Fast Router Registers</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://hepia.hesge.ch</xilinx:vendorURL>
- <xilinx:coreRevision>9</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2021-09-23T07:29:00Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>10</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2021-10-21T06:51:53Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@14e5815b_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@61e1c054_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
@@ -1232,14 +1266,33 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@3c523cc3_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@35b347e6_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@28e2a15b_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c74087a_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@35b6fa91_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ae2c98a_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d2151fc_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@71ef886d_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2bd30f99_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3c497ae8_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4a1c3fcf_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@22beb436_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@35403f18_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1eb59555_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4972bac7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27b5b20_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@43927878_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d5f73d4_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2bc5b419_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6018bd4_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@99b6a4a_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@20d6a89e_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_fast_router_registers</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
- <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3cecaf9e"/>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9067f7bf"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="191f6c5f"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1f11f7c0"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="28a6075e"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af58bdbd"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="8f8baa03"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d2e1fb7a"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="d7187a94"/>
</xilinx:packagingInfo>
diff --git a/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd b/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
index 02780d8967d64078fe238c13770c37d62dcdd508..07215da0cb80fdcf1bbca3b1264b3dd12d5aaf1e 100644
--- a/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
+++ b/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
@@ -63,7 +63,8 @@ entity scalp_fast_router_registers is
DMAFifoTXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXRrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
- DMAFifoRXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
+ DMAFifoRXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
end scalp_fast_router_registers;
@@ -117,6 +118,8 @@ architecture behavioral of scalp_fast_router_registers is
signal DMAFifoRXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSPhyStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal QoSPhyStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
-- Attributes
attribute mark_debug : string;
@@ -299,9 +302,9 @@ begin
WriteRegPortxP : process (DMAFifoRXRrDataCntxDI, DMAFifoRXStatusxDI,
DMAFifoRXWrDataCntxDI, DMAFifoTXRrDataCntxDI,
DMAFifoTXStatusxDI, DMAFifoTXWrDataCntxDI,
- LocalNetAddrPortxDP, RGBLed0PortxDP,
- RGBLed1PortxDP, WrAddrxD, WrDataxD,
- WrValidxS) is
+ LocalNetAddrPortxDP, QoSPhyStatusxDI,
+ RGBLed0PortxDP, RGBLed1PortxDP, WrAddrxD,
+ WrDataxD, WrValidxS) is
begin -- process WriteRegPortxP
LocalNetAddrPortxDN <= LocalNetAddrPortxDP;
LocalNetAddrxDO <= LocalNetAddrPortxDP;
@@ -315,6 +318,7 @@ begin
DMAFifoRXWrDataCntPortxDN <= DMAFifoRXWrDataCntxDI;
DMAFifoRXRrDataCntPortxDN <= DMAFifoRXRrDataCntxDI;
DMAFifoRXStatusPortxDN <= DMAFifoRXStatusxDI;
+ QoSPhyStatusPortxDN <= QoSPhyStatusxDI;
if WrValidxS = '1' then
case WrAddrxD is
@@ -345,6 +349,7 @@ begin
when x"018" => RdDataxD <= DMAFifoRXWrDataCntPortxDP;
when x"01C" => RdDataxD <= DMAFifoRXRrDataCntPortxDP;
when x"020" => RdDataxD <= DMAFifoRXStatusPortxDP;
+ when x"024" => RdDataxD <= QoSPhyStatusPortxDP;
when others => RdDataxD <= (others => '0');
end case;
@@ -364,6 +369,7 @@ begin
DMAFifoRXWrDataCntPortxDP <= x"00000000";
DMAFifoRXRrDataCntPortxDP <= x"00000000";
DMAFifoRXStatusPortxDP <= x"00000000";
+ QoSPhyStatusPortxDP <= x"00000000";
elsif rising_edge(SAxiClkxC) then
LocalNetAddrPortxDP <= LocalNetAddrPortxDN;
@@ -375,6 +381,7 @@ begin
DMAFifoRXWrDataCntPortxDP <= DMAFifoRXWrDataCntPortxDN;
DMAFifoRXRrDataCntPortxDP <= DMAFifoRXRrDataCntPortxDN;
DMAFifoRXStatusPortxDP <= DMAFifoRXStatusPortxDN;
+ QoSPhyStatusPortxDP <= QoSPhyStatusPortxDN;
end if;
end process UpdateRegBankxP;
diff --git a/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_3.tcl b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_3.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38
--- /dev/null
+++ b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_3.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd b/ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d1806168ebb33b59b3a58be9d067e8aa5dea9be0
--- /dev/null
+++ b/ips/hw/scalp_router/src/hdl/scalp_dropbox.vhd
@@ -0,0 +1,120 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: scalp_dropbox.vhd
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Box for dropping packets.
+--
+-- Last update: 2021-10-22
+--
+---------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--use ieee.std_logic_unsigned.all;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_misc.all;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+use work.scalp_misc.all;
+
+entity scalp_dropbox is
+
+ generic (
+ C_SCALP_INTERFACE_VECTOR_SIZE : integer range 0 to 255 := 7);
+
+ port (
+ -- System Clock and Reset
+ SysClkxCI : in std_ulogic;
+ SysRstxRNAI : in std_ulogic;
+ -- Destination Interface Number
+ IfDstNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
+ IfNumValidxSI : in std_ulogic;
+ IfDstNumxDO : out integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
+ IfNumValidxSO : out std_ulogic;
+ -- QoS Vector
+ QoSVectorPhyStatusxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
+ -- Dropped signals
+ ToBeDroppedxSO : out std_ulogic;
+ IsDroppedxSI : in std_ulogic);
+
+end entity scalp_dropbox;
+
+architecture behavioral of scalp_dropbox is
+
+ constant C_SCALP_NO_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
+ constant C_SCALP_NORTH_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
+ constant C_SCALP_EAST_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 1;
+ constant C_SCALP_SOUTH_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 2;
+ constant C_SCALP_WEST_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 3;
+ constant C_SCALP_TOP_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 4;
+ constant C_SCALP_BOTTOM_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 5;
+ constant C_SCALP_LOCAL_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 6;
+
+ signal IfDstNumInxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
+ signal IfNumValidInxS : std_ulogic := '0';
+ signal IfDstNumOutxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
+ signal IfNumValidOutxS : std_ulogic := '0';
+ signal QoSVectorPhyStatusxD : t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal ToBeDroppedxS : std_ulogic := '0';
+ signal IsDroppedxS : std_ulogic := '0';
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+
+begin -- architecture behavioral
+
+ EntityIOxB : block is
+ begin -- block EntityIOxB
+ IfDstNumInxAS : IfDstNumInxD <= IfDstNumxDI;
+ IfNumValidInxAS : IfNumValidInxS <= IfNumValidxSI;
+ IfDstNumOutxAS : IfDstNumxDO <= IfDstNumOutxD;
+ IfNumValidOutxAS : IfNumValidxSO <= IfNumValidOutxS;
+ QoSVectorPhyStatusxAS : QoSVectorPhyStatusxD <= QoSVectorPhyStatusxDI;
+ ToBeDroppedxAS : ToBeDroppedxSO <= ToBeDroppedxS;
+ IsDroppedxAS : IsDroppedxS <= IsDroppedxSI;
+ end block EntityIOxB;
+
+ DropOrSendxP : process (SysClkxCI, SysRstxRNAI) is
+ begin -- process DropOrSendxP
+ if SysRstxRNAI = '0' then
+ ToBeDroppedxS <= '0';
+ IfNumValidOutxS <= '0';
+ IfDstNumOutxD <= C_SCALP_NO_NUM;
+ elsif rising_edge(SysClkxCI) then
+ ToBeDroppedxS <= ToBeDroppedxS;
+ IfNumValidOutxS <= '0';
+ IfDstNumOutxD <= C_SCALP_NO_NUM;
+
+ if (IfNumValidInxS = '1') and (to_integer(QoSVectorPhyStatusxD(IfDstNumInxD)) = 0) then
+ ToBeDroppedxS <= '1';
+ IfDstNumOutxD <= C_SCALP_NO_NUM;
+ IfNumValidOutxS <= '0';
+ elsif (IfNumValidInxS = '1') and (to_integer(QoSVectorPhyStatusxD(IfDstNumInxD)) = 1) then
+ ToBeDroppedxS <= '0';
+ IfDstNumOutxD <= IfDstNumInxD;
+ IfNumValidOutxS <= IfNumValidInxS;
+ end if;
+
+ if IsDroppedxS = '1' then
+ ToBeDroppedxS <= '0';
+ end if;
+ end if;
+ end process DropOrSendxP;
+
+end architecture behavioral;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
index 5c7904bf7f2bfc9a08c6b8f9d55317fd43aea13e..1463b013880215369de22f16338260255c4f4c7c 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2018.2
-- Description: Scalp Miscellanous
--
--- Last update: 2021-06-07
+-- Last update: 2021-10-21
--
---------------------------------------------------------------------------------
library ieee;
@@ -26,33 +26,37 @@ use work.axi4_pkg.all;
package scalp_misc is
- constant C_SCALP_X_RANGE_VALUE : integer range 0 to 255 := 255;
- constant C_SCALP_Y_RANGE_VALUE : integer range 0 to 255 := 255;
- constant C_SCALP_Z_RANGE_VALUE : integer range 0 to 255 := 255;
- constant C_SCALP_PACKET_TYPE_RANGE_VALUE : integer range 0 to 255 := 255;
- constant C_SCALP_PACKET_LENGTH_RANGE_VALUE : integer range 0 to 65535 := 65535;
- constant C_SCALP_ADDR_SIZE : integer range 0 to 255 := 8;
- constant C_BYTE_SIZE : integer range 0 to 255 := 8;
+ constant C_SCALP_X_RANGE_VALUE : integer range 0 to 255 := 255;
+ constant C_SCALP_Y_RANGE_VALUE : integer range 0 to 255 := 255;
+ constant C_SCALP_Z_RANGE_VALUE : integer range 0 to 255 := 255;
+ constant C_SCALP_PACKET_TYPE_RANGE_VALUE : integer range 0 to 255 := 255;
+ constant C_SCALP_PACKET_LENGTH_RANGE_VALUE : integer range 0 to 65535 := 65535;
+ constant C_SCALP_ADDR_SIZE : integer range 0 to 255 := 8;
+ constant C_BYTE_SIZE : integer range 0 to 255 := 8;
-- Scalp router interfaces id.
- constant C_NORTH_IF_ID : integer range 0 to 6 := 0;
- constant C_EAST_IF_ID : integer range 0 to 6 := 1;
- constant C_SOUTH_IF_ID : integer range 0 to 6 := 2;
- constant C_WEST_IF_ID : integer range 0 to 6 := 3;
- constant C_TOP_IF_ID : integer range 0 to 6 := 4;
- constant C_BOTTOM_IF_ID : integer range 0 to 6 := 5;
- constant C_LOCAL_IF_ID : integer range 0 to 6 := 6;
+ constant C_NORTH_IF_ID : integer range 0 to 6 := 0;
+ constant C_EAST_IF_ID : integer range 0 to 6 := 1;
+ constant C_SOUTH_IF_ID : integer range 0 to 6 := 2;
+ constant C_WEST_IF_ID : integer range 0 to 6 := 3;
+ constant C_TOP_IF_ID : integer range 0 to 6 := 4;
+ constant C_BOTTOM_IF_ID : integer range 0 to 6 := 5;
+ constant C_LOCAL_IF_ID : integer range 0 to 6 := 6;
+ -- Scalp packet type
+ constant C_SCALP_PACKET_TYPE_RESERVED_0 : integer range 0 to 255 := 0;
+ constant C_SCALP_PACKET_TYPE_UNICAST : integer range 0 to 255 := 1;
+ constant C_SCALP_PACKET_TYPE_UNICAST_NEIGHBORS : integer range 0 to 255 := 2;
-- Scalp payload sizes
- constant C_SCALP_PACKET_PAYLOAD_SIZE_1 : integer range 0 to 256 := 1;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_2 : integer range 0 to 256 := 2;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_4 : integer range 0 to 256 := 4;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_8 : integer range 0 to 256 := 8;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_16 : integer range 0 to 256 := 16;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_32 : integer range 0 to 256 := 32;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_64 : integer range 0 to 256 := 64;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_128 : integer range 0 to 256 := 128;
- constant C_SCALP_PACKET_PAYLOAD_SIZE_256 : integer range 0 to 256 := 256;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_1 : integer range 0 to 256 := 1;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_2 : integer range 0 to 256 := 2;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_4 : integer range 0 to 256 := 4;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_8 : integer range 0 to 256 := 8;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_16 : integer range 0 to 256 := 16;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_32 : integer range 0 to 256 := 32;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_64 : integer range 0 to 256 := 64;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_128 : integer range 0 to 256 := 128;
+ constant C_SCALP_PACKET_PAYLOAD_SIZE_256 : integer range 0 to 256 := 256;
-- Scalp Simulation
- constant C_SCALP_SIMULATION : boolean;
+ constant C_SCALP_SIMULATION : boolean;
-- Scalp Booking Vector States
type t_scalp_booking_vector_states is (E_SCALP_BOOKING_VECTOR_VALID_INDEX,
@@ -104,6 +108,12 @@ package scalp_misc is
type t_scalp_netaddr_vector is array (natural range <>) of t_scalp_netaddr;
+ type t_scalp_type is record
+ TypexD : integer range 0 to C_SCALP_PACKET_TYPE_RANGE_VALUE;
+ end record t_scalp_type;
+
+ constant C_SCALP_NO_TYPE : t_scalp_type := (TypexD => 0);
+
-- Scalp QoS Vector
constant C_SCALP_QOS_SIZE : integer range 0 to 7 := 7;
@@ -250,6 +260,10 @@ package scalp_misc is
function scalp_is_simulation
return boolean;
+ function scalp_to_integer(
+ s : std_logic)
+ return natural;
+
-- Fonction pour calculer l'index des vecteurs.
function scalp_matrix_idx (
IfSrcxD : integer;
@@ -267,6 +281,12 @@ package scalp_misc is
VecxD : std_logic_vector)
return std_logic_vector;
+ -- Fonction pour vérifier si un paquet doit être supprimé
+ function is_dropped (
+ QoSVectorPyhStatusxD : t_scalp_qos_vector;
+ IfScalpNumxD : integer)
+ return std_ulogic;
+
-- Fonction pour récupérer l'adresse de destination ou de source d'un paquet SCALP_PACKET
function scalp_peek_addr_ul (
DataxD : std_ulogic_vector)
@@ -290,12 +310,12 @@ package scalp_misc is
-- Fonction pour récupérer le type du paquet Scalp.
function scalp_peek_type_ul (
DataxD : std_ulogic_vector)
- return integer;
+ return t_scalp_type;
-- Fonction pour récupérer le type du paquet Scalp.
function scalp_peek_type (
DataxD : std_logic_vector)
- return integer;
+ return t_scalp_type;
---------------------------------------------------------------------------
@@ -487,6 +507,17 @@ package body scalp_misc is
constant C_SCALP_SIMULATION : boolean := scalp_is_simulation;
---------------------------------------------------------------------------
+ function scalp_to_integer(
+ s : std_logic)
+ return natural is
+ begin
+ if s = '1' then
+ return 1;
+ else
+ return 0;
+ end if;
+ end function scalp_to_integer;
+
-- Fonction pour calculer l'index des vecteurs.
function scalp_matrix_idx (
IfSrcxD : integer;
@@ -523,6 +554,22 @@ package body scalp_misc is
return std_logic_vector(change_endian_ul(std_ulogic_vector(VecxD)));
end function change_endian;
+ -- Fonction pour vérifier si un paquet doit être supprimé
+ function is_dropped (
+ QoSVectorPyhStatusxD : t_scalp_qos_vector;
+ IfScalpNumxD : integer)
+ return std_ulogic is
+ variable PktDropxS : std_ulogic := '0';
+ begin
+ if to_integer(QoSVectorPyhStatusxD(IfScalpNumxD)) /= 1 then
+ PktDropxS := '1';
+ else
+ PktDropxS := '0';
+ end if;
+
+ return PktDropxS;
+ end function is_dropped;
+
-- Fonction pour récupérer l'adresse de destination ou de source d'un paquet SCALP_PACKET
function scalp_peek_addr_ul (
DataxD : std_ulogic_vector)
@@ -550,6 +597,29 @@ package body scalp_misc is
return AddrxD;
end function scalp_peek_addr_ul;
+ -- Fonction pour récupérer le type du paquet Scalp.
+ function scalp_peek_type_ul (
+ DataxD : std_ulogic_vector)
+ return t_scalp_type is
+ variable PktTypexD : t_scalp_type := C_SCALP_NO_TYPE;
+ variable TypeMapRangexD : std_ulogic_vector(0 to (C_BYTE_SIZE - 1)) := (others => '0');
+ variable TypexD : std_ulogic_vector((C_BYTE_SIZE - 1) downto 0) := (others => '0');
+ begin -- function scalp_peek_type_ul
+ TypeMapRangexD(0 to (C_BYTE_SIZE - 1)) := DataxD(0 to (DataxD'high - (C_BYTE_SIZE * 3)));
+ TypexD := change_endian_ul(TypeMapRangexD);
+ PktTypexD.TypexD := to_integer(unsigned(TypexD));
+
+ return PktTypexD;
+ end function scalp_peek_type_ul;
+
+ -- Fonction pour récupérer le type du paquet Scalp.
+ function scalp_peek_type (
+ DataxD : std_logic_vector)
+ return t_scalp_type is
+ begin -- function scalp_peek_type
+ return scalp_peek_type_ul(std_ulogic_vector(DataxD));
+ end function scalp_peek_type;
+
-- Fonction pour récupérer l'adresse de destination ou de source d'un paquet SCALP_PACKET
function scalp_peek_addr (
DataxD : std_logic_vector)
@@ -579,26 +649,26 @@ package body scalp_misc is
return scalp_peek_pld_size_ul(std_ulogic_vector(DataxD));
end function scalp_peek_pld_size;
- -- Fonction pour récupérer le type du paquet Scalp.
- function scalp_peek_type_ul (
- DataxD : std_ulogic_vector)
- return integer is
- variable TypexD : std_ulogic_vector(((C_BYTE_SIZE * 1) - 1) downto 0) := (others => '0');
- variable ByteBigEndianxD : std_ulogic_vector(0 to (C_BYTE_SIZE - 1)) := (others => '0');
- begin -- function scalp_peek_type_ul
- ByteBigEndianxD(ByteBigEndianxD'left to ByteBigEndianxD'right)
- := DataxD((DataxD'left + (C_BYTE_SIZE * 3)) to (DataxD'left + ((C_BYTE_SIZE * 4) - 1)));
- TypexD := change_endian_ul(ByteBigEndianxD);
- return to_integer(unsigned(TypexD));
- end function scalp_peek_type_ul;
+ -- -- Fonction pour récupérer le type du paquet Scalp.
+ -- function scalp_peek_type_ul (
+ -- DataxD : std_ulogic_vector)
+ -- return integer is
+ -- variable TypexD : std_ulogic_vector(((C_BYTE_SIZE * 1) - 1) downto 0) := (others => '0');
+ -- variable ByteBigEndianxD : std_ulogic_vector(0 to (C_BYTE_SIZE - 1)) := (others => '0');
+ -- begin -- function scalp_peek_type_ul
+ -- ByteBigEndianxD(ByteBigEndianxD'left to ByteBigEndianxD'right)
+ -- := DataxD((DataxD'left + (C_BYTE_SIZE * 3)) to (DataxD'left + ((C_BYTE_SIZE * 4) - 1)));
+ -- TypexD := change_endian_ul(ByteBigEndianxD);
+ -- return to_integer(unsigned(TypexD));
+ -- end function scalp_peek_type_ul;
-- Fonction pour récupérer le type du paquet Scalp.
- function scalp_peek_type (
- DataxD : std_logic_vector)
- return integer is
- begin -- function scalp_peek_type
- return scalp_peek_type_ul(std_ulogic_vector(DataxD));
- end function scalp_peek_type;
+ -- function scalp_peek_type (
+ -- DataxD : std_logic_vector)
+ -- return integer is
+ -- begin -- function scalp_peek_type
+ -- return scalp_peek_type_ul(std_ulogic_vector(DataxD));
+ -- end function scalp_peek_type;
-- Fonction pour récupérer le payload.
function scalp_peek_pld_ul (
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router.vhd b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
index 633302cd70b11dc466252884282dc39f57a14c21..4715c4ec0c7fe30b296867e633587760fd04f8ba 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router (NoC).
--
--- Last update: 2021-09-07
+-- Last update: 2021-10-21
--
---------------------------------------------------------------------------------
library ieee;
@@ -44,22 +44,23 @@ entity scalp_router is
port (
-- System Clock and System nReset
-----------------------------------------------------------------------
- SysClkxCI : in std_ulogic;
- SysRstxRNAI : in std_ulogic;
+ SysClkxCI : in std_ulogic;
+ SysRstxRNAI : in std_ulogic;
-- Local Router Network Address
-----------------------------------------------------------------------
- LocNetAddrxDI : in t_scalp_netaddr;
+ LocNetAddrxDI : in t_scalp_netaddr;
-- Axi4 Stream
-----------------------------------------------------------------------
-- RX Side Vector
- RXAxism2sVectorxDI : in t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
- RXAxiss2mVectorxDO : out t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ RXAxism2sVectorxDI : in t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ RXAxiss2mVectorxDO : out t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
-- TX Side Vector
- TXAxism2sVectorxDO : out t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
- TXAxiss2mVectorxDI : in t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ TXAxism2sVectorxDO : out t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ TXAxiss2mVectorxDI : in t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
-- QoS Vector
-----------------------------------------------------------------------
- QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0));
+ QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0);
+ QoSVectorPyhStatusxDI : in t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0));
end entity scalp_router;
@@ -80,56 +81,58 @@ architecture rtl of scalp_router is
C_SCALP_SCHEDULER_STRATEGY : string);
port (
-- System Clock and System nReset
- SysClkxCI : in std_ulogic;
- SysRstxRNAI : in std_ulogic;
+ SysClkxCI : in std_ulogic;
+ SysRstxRNAI : in std_ulogic;
-- Local Router Network Address
- LocNetAddrxDI : in t_scalp_netaddr;
+ LocNetAddrxDI : in t_scalp_netaddr;
-- Axi4 Stream
-----------------------------------------------------------------------
-- Interface Input Side
- RXAxi4m2sIfxDI : in t_axi4m2s;
- RXAxi4s2mIfxDO : out t_axi4s2m;
+ RXAxi4m2sIfxDI : in t_axi4m2s;
+ RXAxi4s2mIfxDO : out t_axi4s2m;
-- Interface Output Side
- TXAxi4m2sIfxDO : out t_axi4m2s;
- TXAxi4s2mIfxDI : in t_axi4s2m;
+ TXAxi4m2sIfxDO : out t_axi4m2s;
+ TXAxi4s2mIfxDI : in t_axi4s2m;
-----------------------------------------------------------------------
-- Neighborhood Links Input Side
- RXAxi4m2sLinksxDI : in t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
- RXAxi4s2mLinksxDO : out t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ RXAxi4m2sLinksxDI : in t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ RXAxi4s2mLinksxDO : out t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Neighborhood Links Output Side
- TXAxi4m2sLinksxDO : out t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
- TXAxi4s2mLinksxDI : in t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ TXAxi4m2sLinksxDO : out t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ TXAxi4s2mLinksxDI : in t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-----------------------------------------------------------------------
-- Booking Vector
-- Input Side
- BookingVectorxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ BookingVectorxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Output Side
- BookingVectorxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ BookingVectorxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Scheduler Ack Vector
-- Input Side
- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ SchedulerAckxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Output Side
- SchedulerAckxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ SchedulerAckxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- QoS Vector
- QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0));
+ QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
+ QoSVectorPyhStatusxDI : in t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0));
end component scalp_router_interface;
-- Signals
-- Scalp Router
-- Local Router Network Address
- signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
-- Axi4 Stream Interfaces
- signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
- signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
-- Scalp QoS Vectors
- signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal QoSVectorPyhStatusxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
-- Axi4 Stream Cross-Links with Neighborhood
- signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
- signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
---------------------------------------------------------------------------
-- For Simulation With Vivado Only
-- Axi4 Stream Cross-Links with Neighborhood
@@ -139,26 +142,27 @@ architecture rtl of scalp_router is
-- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_SIM_AXISS2M_VECTOR);
---------------------------------------------------------------------------
-- Scalp Booking Vectors
- signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
-- Scalp Scheduler Ack Vectors
- signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
begin -- architecture rtl
EntityIOxB : block is
begin -- block EntityIOxB
- LocNetAddrxAS : LocNetAddrxD <= LocNetAddrxDI;
- RXAxism2sVectorxAS : RXAxism2sVectorxD <= RXAxism2sVectorxDI;
- RXAxiss2mVectorxAS : RXAxiss2mVectorxDO <= RXAxiss2mVectorxD;
- TXAxism2sVectorxAS : TXAxism2sVectorxDO <= TXAxism2sVectorxD;
- TXAxiss2mVectorxAS : TXAxiss2mVectorxD <= TXAxiss2mVectorxDI;
- QoSVectorxAS : QoSVectorxD <= QoSVectorxDI;
+ LocNetAddrxAS : LocNetAddrxD <= LocNetAddrxDI;
+ RXAxism2sVectorxAS : RXAxism2sVectorxD <= RXAxism2sVectorxDI;
+ RXAxiss2mVectorxAS : RXAxiss2mVectorxDO <= RXAxiss2mVectorxD;
+ TXAxism2sVectorxAS : TXAxism2sVectorxDO <= TXAxism2sVectorxD;
+ TXAxiss2mVectorxAS : TXAxiss2mVectorxD <= TXAxiss2mVectorxDI;
+ QoSVectorxAS : QoSVectorxD <= QoSVectorxDI;
+ QoSVectorPyhStatusxAS : QoSVectorPyhStatusxD <= QoSVectorPyhStatusxDI;
end block EntityIOxB;
ScalpRouterInterfacexG : for i in 0 to (C_SCALP_NUMBER_OF_INTERFACE - 1) generate
@@ -171,15 +175,15 @@ begin -- architecture rtl
integer'image(scalp_matrix_idx(j mod C_SCALP_NUMBER_OF_INTERFACE, i, C_SCALP_NUMBER_OF_INTERFACE))
severity note;
- -- Axi4 Stream Cross-Links with Neighborhood
+ -- Axi4 Stream Cross-Links with Neighborhood
RXTXm2sLinksxAS : RXAxi4m2sLinksxD(j mod C_SCALP_NUMBER_OF_INTERFACE)(scalp_matrix_idx(j mod C_SCALP_NUMBER_OF_INTERFACE, i, C_SCALP_NUMBER_OF_INTERFACE))
<= TXAxi4m2sLinksxD(i)(scalp_matrix_idx(i, j mod C_SCALP_NUMBER_OF_INTERFACE, C_SCALP_NUMBER_OF_INTERFACE));
RXTXs2mLinksxAS : TXAxi4s2mLinksxD(i)(scalp_matrix_idx(i, j mod C_SCALP_NUMBER_OF_INTERFACE, C_SCALP_NUMBER_OF_INTERFACE))
<= RXAxi4s2mLinksxD(j mod C_SCALP_NUMBER_OF_INTERFACE)(scalp_matrix_idx(j mod C_SCALP_NUMBER_OF_INTERFACE, i, C_SCALP_NUMBER_OF_INTERFACE));
- -- Booking Vectors Cross-Links with Neighborhood
+ -- Booking Vectors Cross-Links with Neighborhood
BookingVectorsxAS : BookingVectorsInxD(j mod C_SCALP_NUMBER_OF_INTERFACE)(scalp_matrix_idx(j mod C_SCALP_NUMBER_OF_INTERFACE, i, C_SCALP_NUMBER_OF_INTERFACE))
<= BookingVectorsOutxD(i)(scalp_matrix_idx(i, j mod C_SCALP_NUMBER_OF_INTERFACE, C_SCALP_NUMBER_OF_INTERFACE));
- -- Scalp Scheduler Ack Vectors
+ -- Scalp Scheduler Ack Vectors
SchedulerAckVectorsxAS : SchedulerAckVectorsInxD(i)(scalp_matrix_idx(i, j mod C_SCALP_NUMBER_OF_INTERFACE, C_SCALP_NUMBER_OF_INTERFACE)) <=
SchedulerAckVectorsOutxD(j mod C_SCALP_NUMBER_OF_INTERFACE)(scalp_matrix_idx(j mod C_SCALP_NUMBER_OF_INTERFACE, i, C_SCALP_NUMBER_OF_INTERFACE));
end generate CrossLinksxG;
@@ -192,39 +196,40 @@ begin -- architecture rtl
C_SCALP_SCHEDULER_ACK_VECTOR_SIZE => C_SCALP_SCHEDULER_ACK_VECTOR_SIZE,
C_SCALP_SCHEDULER_STRATEGY => C_SCALP_SCHEDULER_STRATEGY)
port map (
- -- System Clock and System nReset
- SysClkxCI => SysClkxCI,
- SysRstxRNAI => SysRstxRNAI,
- -- Local Router Network Address
- LocNetAddrxDI => LocNetAddrxD,
- -- Axi4 Stream
- -----------------------------------------------------------------------
- -- Interface Input Side
- RXAxi4m2sIfxDI => RXAxism2sVectorxD(i),
- RXAxi4s2mIfxDO => RXAxiss2mVectorxD(i),
- -- Interface Output Side
- TXAxi4m2sIfxDO => TXAxism2sVectorxD(i),
- TXAxi4s2mIfxDI => TXAxiss2mVectorxD(i),
- -----------------------------------------------------------------------
- -- Neighborhood Links Input Side
- RXAxi4m2sLinksxDI => RXAxi4m2sLinksxD(i),
- RXAxi4s2mLinksxDO => RXAxi4s2mLinksxD(i),
- -- Neighborhood Links Output Side
- TXAxi4m2sLinksxDO => TXAxi4m2sLinksxD(i),
- TXAxi4s2mLinksxDI => TXAxi4s2mLinksxD(i),
- -----------------------------------------------------------------------
- -- Booking Vector
- -- Input Side
- BookingVectorxDI => BookingVectorsInxD(i),
- -- Output Side
- BookingVectorxDO => BookingVectorsOutxD(i),
- -- Scheduler Ack Vector
- -- Input Side
- SchedulerAckxDI => SchedulerAckVectorsInxD(i),
- -- Output Side
- SchedulerAckxDO => SchedulerAckVectorsOutxD(i),
- -- QoS Vector
- QoSVectorxDI => QoSVectorxD);
+ -- System Clock and System nReset
+ SysClkxCI => SysClkxCI,
+ SysRstxRNAI => SysRstxRNAI,
+ -- Local Router Network Address
+ LocNetAddrxDI => LocNetAddrxD,
+ -- Axi4 Stream
+ -----------------------------------------------------------------------
+ -- Interface Input Side
+ RXAxi4m2sIfxDI => RXAxism2sVectorxD(i),
+ RXAxi4s2mIfxDO => RXAxiss2mVectorxD(i),
+ -- Interface Output Side
+ TXAxi4m2sIfxDO => TXAxism2sVectorxD(i),
+ TXAxi4s2mIfxDI => TXAxiss2mVectorxD(i),
+ -----------------------------------------------------------------------
+ -- Neighborhood Links Input Side
+ RXAxi4m2sLinksxDI => RXAxi4m2sLinksxD(i),
+ RXAxi4s2mLinksxDO => RXAxi4s2mLinksxD(i),
+ -- Neighborhood Links Output Side
+ TXAxi4m2sLinksxDO => TXAxi4m2sLinksxD(i),
+ TXAxi4s2mLinksxDI => TXAxi4s2mLinksxD(i),
+ -----------------------------------------------------------------------
+ -- Booking Vector
+ -- Input Side
+ BookingVectorxDI => BookingVectorsInxD(i),
+ -- Output Side
+ BookingVectorxDO => BookingVectorsOutxD(i),
+ -- Scheduler Ack Vector
+ -- Input Side
+ SchedulerAckxDI => SchedulerAckVectorsInxD(i),
+ -- Output Side
+ SchedulerAckxDO => SchedulerAckVectorsOutxD(i),
+ -- QoS Vector
+ QoSVectorxDI => QoSVectorxD,
+ QoSVectorPyhStatusxDI => QoSVectorPyhStatusxD);
end generate ScalpRouterInterfacexG;
end architecture rtl;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
index ddec2daf540b26e5afdbdb57bd3996391181b41e..d299524611a54791ac2fe597cfbc6b246a0b5a8d 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_core.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Core Algorithm
--
--- Last update: 2021-05-19
+-- Last update: 2021-10-22
--
---------------------------------------------------------------------------------
library ieee;
@@ -44,6 +44,10 @@ entity scalp_router_core is
LocRouterNetAddrxDI : in t_scalp_netaddr;
DstRouterNetAddrxDI : in t_scalp_netaddr;
RouterNetAddrValidxSI : in std_ulogic;
+ -- Packet type
+ PktTypexDI : in t_scalp_type;
+ -- Source Interfaces Number
+ IfSrcNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
-- Destination Interfaces Number
IfDstNumxDO : out integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSO : out std_ulogic;
@@ -54,6 +58,7 @@ end entity scalp_router_core;
architecture behavioral_xyz of scalp_router_core is
+ constant C_SCALP_NO_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
constant C_SCALP_NORTH_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
constant C_SCALP_EAST_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 1;
constant C_SCALP_SOUTH_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 2;
@@ -65,10 +70,17 @@ architecture behavioral_xyz of scalp_router_core is
signal LocRouterNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
signal DstRouterNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
signal RouterNetAddrValidxS : std_ulogic := '0';
+ signal PktTypexD : t_scalp_type := C_SCALP_NO_TYPE;
+ signal IfSrcNumxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfDstNumxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfNumValidxS : std_ulogic := '0';
signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+
begin -- architecture behavioral
EntityIOxB : block is
@@ -76,6 +88,8 @@ begin -- architecture behavioral
LocRouterNetAddrxAS : LocRouterNetAddrxD <= LocRouterNetAddrxDI;
DstRouterNetAddrxAS : DstRouterNetAddrxD <= DstRouterNetAddrxDI;
RouterNetAddrValidxAS : RouterNetAddrValidxS <= RouterNetAddrValidxSI;
+ PktTypexAS : PktTypexD <= PktTypexDI;
+ IfSrcNumxAS : IfSrcNumxD <= IfSrcNumxDI;
IfDstNumxAS : IfDstNumxDO <= IfDstNumxD;
IfNumValidxAS : IfNumValidxSO <= IfNumValidxS;
QoSVectorxAS : QoSVectorxD <= QoSVectorxDI;
@@ -84,33 +98,46 @@ begin -- architecture behavioral
ScalpRouterCorexP : process (SysClkxCI, SysRstxRNAI) is
begin -- process ScalpRouterCorexP
if SysRstxRNAI = '0' then
- IfDstNumxD <= C_SCALP_NORTH_NUM;
+ IfDstNumxD <= C_SCALP_NO_NUM;
IfNumValidxS <= '0';
elsif rising_edge(SysClkxCI) then
- IfDstNumxD <= C_SCALP_NORTH_NUM;
+ IfDstNumxD <= C_SCALP_NO_NUM;
IfNumValidxS <= '0';
if RouterNetAddrValidxS = '1' then
- IfNumValidxS <= '1';
- -- X-axis
- if LocRouterNetAddrxD.XxD < DstRouterNetAddrxD.XxD then
- IfDstNumxD <= C_SCALP_EAST_NUM;
- elsif LocRouterNetAddrxD.XxD > DstRouterNetAddrxD.XxD then
- IfDstNumxD <= C_SCALP_WEST_NUM;
+ -- Packet Type
+ if (PktTypexD.TypexD = C_SCALP_PACKET_TYPE_UNICAST_NEIGHBORS) and
+ (IfSrcNumxD /= C_SCALP_LOCAL_NUM) then
+ IfDstNumxD <= C_SCALP_LOCAL_NUM;
+ IfNumValidxS <= '1';
else
- -- Y-axis
- if LocRouterNetAddrxD.YxD < DstRouterNetAddrxD.YxD then
- IfDstNumxD <= C_SCALP_NORTH_NUM;
- elsif LocRouterNetAddrxD.YxD > DstRouterNetAddrxD.YxD then
- IfDstNumxD <= C_SCALP_SOUTH_NUM;
+ -- X-axis
+ if LocRouterNetAddrxD.XxD < DstRouterNetAddrxD.XxD then
+ IfDstNumxD <= C_SCALP_EAST_NUM;
+ IfNumValidxS <= '1';
+ elsif LocRouterNetAddrxD.XxD > DstRouterNetAddrxD.XxD then
+ IfDstNumxD <= C_SCALP_WEST_NUM;
+ IfNumValidxS <= '1';
else
- -- Z-axis
- if LocRouterNetAddrxD.ZxD < DstRouterNetAddrxD.ZxD then
- IfDstNumxD <= C_SCALP_TOP_NUM;
- elsif LocRouterNetAddrxD.ZxD > DstRouterNetAddrxD.ZxD then
- IfDstNumxD <= C_SCALP_BOTTOM_NUM;
+ -- Y-axis
+ if LocRouterNetAddrxD.YxD < DstRouterNetAddrxD.YxD then
+ IfDstNumxD <= C_SCALP_NORTH_NUM;
+ IfNumValidxS <= '1';
+ elsif LocRouterNetAddrxD.YxD > DstRouterNetAddrxD.YxD then
+ IfDstNumxD <= C_SCALP_SOUTH_NUM;
+ IfNumValidxS <= '1';
else
- IfDstNumxD <= C_SCALP_LOCAL_NUM;
+ -- Z-axis
+ if LocRouterNetAddrxD.ZxD < DstRouterNetAddrxD.ZxD then
+ IfDstNumxD <= C_SCALP_TOP_NUM;
+ IfNumValidxS <= '1';
+ elsif LocRouterNetAddrxD.ZxD > DstRouterNetAddrxD.ZxD then
+ IfDstNumxD <= C_SCALP_BOTTOM_NUM;
+ IfNumValidxS <= '1';
+ else
+ IfDstNumxD <= C_SCALP_LOCAL_NUM;
+ IfNumValidxS <= '1';
+ end if;
end if;
end if;
end if;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
index 6f089f07fcda73ff4633d9da8fb53291b9a2d25b..445b742e73b2e24420fb79db06ee97a4a72f7a92 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Interface.
--
--- Last update: 2021-09-07
+-- Last update: 2021-10-22
--
---------------------------------------------------------------------------------
library ieee;
@@ -44,38 +44,39 @@ entity scalp_router_interface is
port (
-- System Clock and System nReset
- SysClkxCI : in std_ulogic;
- SysRstxRNAI : in std_ulogic;
+ SysClkxCI : in std_ulogic;
+ SysRstxRNAI : in std_ulogic;
-- Local Router Network Address
- LocNetAddrxDI : in t_scalp_netaddr;
+ LocNetAddrxDI : in t_scalp_netaddr;
-- Axi4 Stream
-----------------------------------------------------------------------
-- Interface Input Side
- RXAxi4m2sIfxDI : in t_axi4m2s;
- RXAxi4s2mIfxDO : out t_axi4s2m;
+ RXAxi4m2sIfxDI : in t_axi4m2s;
+ RXAxi4s2mIfxDO : out t_axi4s2m;
-- Interface Output Side
- TXAxi4m2sIfxDO : out t_axi4m2s;
- TXAxi4s2mIfxDI : in t_axi4s2m;
+ TXAxi4m2sIfxDO : out t_axi4m2s;
+ TXAxi4s2mIfxDI : in t_axi4s2m;
-----------------------------------------------------------------------
-- Neighborhood Links Input Side
- RXAxi4m2sLinksxDI : in t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
- RXAxi4s2mLinksxDO : out t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ RXAxi4m2sLinksxDI : in t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ RXAxi4s2mLinksxDO : out t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Neighborhood Links Output Side
- TXAxi4m2sLinksxDO : out t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
- TXAxi4s2mLinksxDI : in t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ TXAxi4m2sLinksxDO : out t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ TXAxi4s2mLinksxDI : in t_axi4s2m_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-----------------------------------------------------------------------
-- Booking Vector
-- Input Side
- BookingVectorxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ BookingVectorxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Output Side
- BookingVectorxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ BookingVectorxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Scheduler Ack Vector
-- Input Side
- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ SchedulerAckxDI : in std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- Output Side
- SchedulerAckxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
+ SchedulerAckxDO : out std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0);
-- QoS Vector
- QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0));
+ QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
+ QoSVectorPyhStatusxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0));
end entity scalp_router_interface;
@@ -126,11 +127,23 @@ architecture rtl of scalp_router_interface is
LocRouterNetAddrxDI : in t_scalp_netaddr;
DstRouterNetAddrxDI : in t_scalp_netaddr;
RouterNetAddrValidxSI : in std_ulogic;
+ IfSrcNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfDstNumxDO : out integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSO : out std_ulogic;
QoSVectorxDI : in std_ulogic_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0));
end component scalp_router_core;
+ component scalp_dropbox is
+ generic (
+ C_SCALP_INTERFACE_VECTOR_SIZE : integer range 0 to 255);
+ port (
+ IfDstNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
+ IfNumValidxSI : in std_ulogic;
+ QoSVectorPhyStatusxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
+ ToBeDroppedxSO : out std_ulogic;
+ IsDroppedxSI : in std_ulogic);
+ end component scalp_dropbox;
+
component scalp_scheduler_ack is
generic (
C_SCALP_NEIGHBORS_VECTOR_SIZE : integer range 0 to 255;
@@ -191,9 +204,12 @@ architecture rtl of scalp_router_interface is
signal SchedulerAckInxD : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal SchedulerAckOutxD : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal QoSVectorPyhStatusxD : t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0) := (others => C_SCALP_NO_QOS);
-- Scalp TX Side
signal DstRouterNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
signal RouterNetAddrValidxS : std_ulogic := '0';
+ signal PktTypexD : t_scalp_type := C_SCALP_NO_TYPE;
+ signal ToBeDroppedxS : std_ulogic := '0';
signal BookingVectorValidxS : std_ulogic := '0';
signal SchedulerAckxD : std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal TXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
@@ -201,8 +217,10 @@ architecture rtl of scalp_router_interface is
-- Scalp RX Side
-- Scalp Router Core
signal LocRouterNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
- signal IfDstNumxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
- signal IfNumValidxS : std_ulogic := '0';
+ signal IfDstNumFromRCxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
+ signal IfNumValidFromRCxS : std_ulogic := '0';
+ signal IfDstNumFromDBxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
+ signal IfNumValidFromDBxS : std_ulogic := '0';
-- Scalp Scheduler Ack
-- Scalp Matrix Index
signal IfSrcNumxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := C_SCALP_INTERFACE_SOURCE_NUMBER;
@@ -215,28 +233,29 @@ architecture rtl of scalp_router_interface is
signal DTXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
begin -- architecture rtl
EntityIOxB : block is
begin -- block EntityIOxB
- LocNetAddrxAS : LocRouterNetAddrxD <= LocNetAddrxDI;
- RXAxi4m2sIfxAS : RXAxi4m2sIfxD <= RXAxi4m2sIfxDI;
- RXAxi4s2mIfxAS : RXAxi4s2mIfxDO <= RXAxi4s2mIfxD;
- TXAxi4m2sIfxAS : TXAxi4m2sIfxDO <= TXAxi4m2sIfxD;
- TXAxi4s2mIfxAS : TXAxi4s2mIfxD <= TXAxi4s2mIfxDI;
- RXAxi4m2sLinksxAS : RXAxi4m2sLinksxD <= RXAxi4m2sLinksxDI;
- RXAxi4s2mLinksxAS : RXAxi4s2mLinksxDO <= RXAxi4s2mLinksxD;
- TXAxi4m2sLinksxAS : TXAxi4m2sLinksxDO <= TXAxi4m2sLinksxD;
- TXAxi4s2mLinksxAS : TXAxi4s2mLinksxD <= TXAxi4s2mLinksxDI;
- BookingVectorInxAS : BookingVectorInxD <= BookingVectorxDI;
- BookingVectorOutxAS : BookingVectorxDO <= BookingVectorOutxD;
- SchedulerAckInxAS : SchedulerAckInxD <= SchedulerAckxDI;
- SchedulerAckOutxAS : SchedulerAckxDO <= SchedulerAckOutxD;
- QoSVectorxAS : QoSVectorxD <= QoSVectorxDI;
+ LocNetAddrxAS : LocRouterNetAddrxD <= LocNetAddrxDI;
+ RXAxi4m2sIfxAS : RXAxi4m2sIfxD <= RXAxi4m2sIfxDI;
+ RXAxi4s2mIfxAS : RXAxi4s2mIfxDO <= RXAxi4s2mIfxD;
+ TXAxi4m2sIfxAS : TXAxi4m2sIfxDO <= TXAxi4m2sIfxD;
+ TXAxi4s2mIfxAS : TXAxi4s2mIfxD <= TXAxi4s2mIfxDI;
+ RXAxi4m2sLinksxAS : RXAxi4m2sLinksxD <= RXAxi4m2sLinksxDI;
+ RXAxi4s2mLinksxAS : RXAxi4s2mLinksxDO <= RXAxi4s2mLinksxD;
+ TXAxi4m2sLinksxAS : TXAxi4m2sLinksxDO <= TXAxi4m2sLinksxD;
+ TXAxi4s2mLinksxAS : TXAxi4s2mLinksxD <= TXAxi4s2mLinksxDI;
+ BookingVectorInxAS : BookingVectorInxD <= BookingVectorxDI;
+ BookingVectorOutxAS : BookingVectorxDO <= BookingVectorOutxD;
+ SchedulerAckInxAS : SchedulerAckInxD <= SchedulerAckxDI;
+ SchedulerAckOutxAS : SchedulerAckxDO <= SchedulerAckOutxD;
+ QoSVectorxAS : QoSVectorxD <= QoSVectorxDI;
+ QoSVectorPyhStatusxAS : QoSVectorPyhStatusxD <= QoSVectorPyhStatusxDI;
end block EntityIOxB;
ScalpTXSidexI : entity work.scalp_tx_side
@@ -247,6 +266,8 @@ begin -- architecture rtl
SysRstxRNAI => SysRstxRNAI,
DstRouterNetAddrxDO => DstRouterNetAddrxD,
RouterNetAddrValidxSO => RouterNetAddrValidxS,
+ PktTypexDO => PktTypexD,
+ ToBeDroppedxSI => ToBeDroppedxS,
RXAxi4M2SLinkxDI => RXAxi4m2sIfxD,
RXAxi4S2MLinkxDO => RXAxi4s2mIfxD,
TXAxi4M2SLinkxDO => TXAxi4M2SLinkxD,
@@ -278,10 +299,26 @@ begin -- architecture rtl
LocRouterNetAddrxDI => LocRouterNetAddrxD,
DstRouterNetAddrxDI => DstRouterNetAddrxD,
RouterNetAddrValidxSI => RouterNetAddrValidxS,
- IfDstNumxDO => IfDstNumxD,
- IfNumValidxSO => IfNumValidxS,
+ PktTypexDI => PktTypexD,
+ IfSrcNumxDI => IfSrcNumxD,
+ IfDstNumxDO => IfDstNumFromRCxD,
+ IfNumValidxSO => IfNumValidFromRCxS,
QoSVectorxDI => QoSVectorxD);
+ ScalpDropBoxxI : entity work.scalp_dropbox
+ generic map (
+ C_SCALP_INTERFACE_VECTOR_SIZE => C_SCALP_INTERFACE_VECTOR_SIZE)
+ port map (
+ SysClkxCI => SysClkxCI,
+ SysRstxRNAI => SysRstxRNAI,
+ IfDstNumxDI => IfDstNumFromRCxD,
+ IfNumValidxSI => IfNumValidFromRCxS,
+ IfDstNumxDO => IfDstNumFromDBxD,
+ IfNumValidxSO => IfNumValidFromDBxS,
+ QoSVectorPhyStatusxDI => QoSVectorPyhStatusxD,
+ ToBeDroppedxSO => ToBeDroppedxS,
+ IsDroppedxSI => TXAxi4M2SLinkxD.LastxS); -- Finish
+
ScalpSchedulerAckxI : entity work.scalp_scheduler_ack
generic map (
C_SCALP_NEIGHBORS_VECTOR_SIZE => C_SCALP_NEIGHBORS_VECTOR_SIZE,
@@ -295,8 +332,8 @@ begin -- architecture rtl
C_SCALP_INTERFACE_VECTOR_SIZE => C_SCALP_INTERFACE_VECTOR_SIZE)
port map (
IfSrcNumxDI => IfSrcNumxD,
- IfDstNumxDI => IfDstNumxD,
- IfNumValidxSI => IfNumValidxS,
+ IfDstNumxDI => IfDstNumFromDBxD,
+ IfNumValidxSI => IfNumValidFromDBxS,
IfDstIdxxDO => IfDstIdxxD,
IfDstIdxValidxSO => IfDstIdxValidxS);
diff --git a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
index dd4e03cd560837f7a9035eb877a3e1a4dce235e4..80fa397d461f93fd3c3fa540d98b595a94c78179 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp TX side state machine.
--
--- Last update: 2021-09-07
+-- Last update: 2021-10-22
--
---------------------------------------------------------------------------------
library ieee;
@@ -44,6 +44,10 @@ entity scalp_tx_side is
-- Routeur Network Address
DstRouterNetAddrxDO : out t_scalp_netaddr;
RouterNetAddrValidxSO : out std_ulogic;
+ -- Packet type
+ PktTypexDO : out t_scalp_type;
+ -- Drop Packet
+ ToBeDroppedxSI : in std_ulogic;
-- Axi4 Stream
-- Input side
RXAxi4M2SLinkxDI : in t_axi4m2s;
@@ -73,6 +77,8 @@ architecture behavioral of scalp_tx_side is
signal DstRouterNetAddrxDN : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
signal RouterNetAddrValidxSP : std_ulogic := '0';
signal RouterNetAddrValidxSN : std_ulogic := '0';
+ signal PktTypexDP : t_scalp_type := C_SCALP_NO_TYPE;
+ signal PktTypexDN : t_scalp_type := C_SCALP_NO_TYPE;
signal RXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
signal RXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
signal TXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
@@ -83,10 +89,11 @@ architecture behavioral of scalp_tx_side is
-- Others
signal ReadyInxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EnPopxS : std_ulogic := '0';
+ signal ToBeDroppedxS : std_ulogic := '0';
attribute mark_debug : string;
attribute keep : string;
- --
+ --
begin -- architecture behavioral
@@ -96,6 +103,8 @@ begin -- architecture behavioral
begin -- block EntityIOxB
DstRouterNetAddrxAS : DstRouterNetAddrxDO <= DstRouterNetAddrxDP;
RouterNetAddrValidxAS : RouterNetAddrValidxSO <= RouterNetAddrValidxSP;
+ PktTypexAS : PktTypexDO <= PktTypexDP;
+ PktDropxAS : ToBeDroppedxS <= ToBeDroppedxSI;
-- Ext. Side
RXAxi4M2SLinkxAS : RXAxi4M2SLinkxD <= RXAxi4M2SLinkxDI;
RXAxi4S2MLinkxAS : RXAxi4S2MLinkxDO <= RXAxi4S2MLinkxD;
@@ -129,22 +138,26 @@ begin -- architecture behavioral
TXSideStatexDP <= E_SCALP_TX_IDLE;
DstRouterNetAddrxDP <= C_3D_MIN_SCALP_NETADDR;
RouterNetAddrValidxSP <= '0';
+ PktTypexDP <= C_SCALP_NO_TYPE;
elsif rising_edge(SysClkxCI) then
TXSideStatexDP <= TXSideStatexDN;
DstRouterNetAddrxDP <= DstRouterNetAddrxDN;
RouterNetAddrValidxSP <= RouterNetAddrValidxSN;
+ PktTypexDP <= PktTypexDN;
end if;
end process UpdateRegxP;
TXSideStateMachinexP : process (TXAxi4M2SLinkxD.DataxD,
TXAxi4M2SLinkxD.LastxS,
TXAxi4M2SLinkxD.ValidxS,
- TXAxi4S2MLinkxD.ReadyxS, TXSideStatexDP) is
+ TXAxi4S2MLinkxD.ReadyxS, TXSideStatexDP,
+ ToBeDroppedxS) is
begin -- process TXSideStateMachinexP
-- Default values
TXSideStatexDN <= TXSideStatexDP;
DstRouterNetAddrxDN <= C_3D_MIN_SCALP_NETADDR;
RouterNetAddrValidxSN <= '0';
+ PktTypexDN <= C_SCALP_NO_TYPE;
EnPopxS <= '0';
case TXSideStatexDP is
@@ -154,13 +167,14 @@ begin -- architecture behavioral
if TXAxi4M2SLinkxD.ValidxS = '1' then
EnPopxS <= '0';
DstRouterNetAddrxDN <= scalp_peek_addr_ul(TXAxi4M2SLinkxD.DataxD);
+ PktTypexDN <= scalp_peek_type_ul(TXAxi4M2SLinkxD.DataxD);
RouterNetAddrValidxSN <= '1';
TXSideStatexDN <= E_SCALP_TX_POP_N_PUSH;
end if;
when E_SCALP_TX_POP_N_PUSH =>
- if TXAxi4S2MLinkxD.ReadyxS = '1' then
+ if (TXAxi4S2MLinkxD.ReadyxS = '1') or (ToBeDroppedxS = '1') then
EnPopxS <= '1';
if TXAxi4M2SLinkxD.LastxS = '1' then
TXSideStatexDN <= E_SCALP_TX_IDLE;
diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
index 534153e3f4e5f632e8536fa39e947b1625a33880..fa4c6ef9f3d5093c0badddd2ee08ddbfe6ba719e 100644
--- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
--- Last update: 2021-10-04
+-- Last update: 2021-10-21
--
---------------------------------------------------------------------------------
@@ -68,6 +68,7 @@ entity scalp_zynqps_wrapper is
LocalNetAddrxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
RGBLed0xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
RGBLed1xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
-- RX
DMARXm2sxDI : in t_axi4m2s;
DMARXs2mxDO : out t_axi4s2m;
@@ -140,6 +141,7 @@ begin
LocalNetAddrxDO => LocalNetAddrxDO,
RGBLed0xDO => RGBLed0xDO,
RGBLed1xDO => RGBLed1xDO,
+ QoSPhyStatusxDI => QoSPhyStatusxDI,
-- AXIS
-- DMA
DMARXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => DMARXm2sxDI.DataxD,
diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index 68a435abec0f4cd41bcf41087c3fd137121b3b16..48af314cd62ad32ba1da753f8f8abeffa4b06303 100644
--- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -128,7 +128,7 @@ xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
hepia.hesge.ch:user:scalp_dma_fifo:1.0\
-hepia.hesge.ch:user:scalp_fast_router_registers:1.0\
+hepia.hesge.ch:user:scalp_fast_router_registers:1.3\
xilinx.com:ip:system_ila:1.1\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
@@ -257,6 +257,7 @@ proc create_root_design { parentCell } {
] $FclkClk0xCO
set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
set LocalNetAddrxDO [ create_bd_port -dir O -from 31 -to 0 -type data LocalNetAddrxDO ]
+ set QoSPhyStatusxDI [ create_bd_port -dir I -from 31 -to 0 -type data QoSPhyStatusxDI ]
set RGBLed0xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed0xDO ]
set RGBLed1xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed1xDO ]
set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
@@ -768,7 +769,7 @@ proc create_root_design { parentCell } {
set scalp_dma_fifo_tx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_tx_0 ]
# Create instance: scalp_fast_router_registers_0, and set properties
- set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.0 scalp_fast_router_registers_0 ]
+ set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.3 scalp_fast_router_registers_0 ]
# Create instance: system_ila_0, and set properties
set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
@@ -880,6 +881,7 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO] [g
connect_bd_intf_net -intf_net scalp_dma_fifo_tx_0_DMATXxDO [get_bd_intf_ports DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMATXxDO]
# Create port connections
+ connect_bd_net -net QoSPhyStatusxDI_0_1 [get_bd_ports QoSPhyStatusxDI] [get_bd_pins scalp_fast_router_registers_0/QoSPhyStatusxDI]
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins axi_clock_converter_2/s_axi_aclk] [get_bd_pins axi_clock_converter_3/m_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins scalp_dma_fifo_rx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_rx_0/TXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/TXClkxCI] [get_bd_pins scalp_fast_router_registers_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk]
connect_bd_net -net UserResetxRANI_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins axi_clock_converter_2/s_axi_aresetn] [get_bd_pins axi_clock_converter_3/m_axi_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins scalp_dma_fifo_rx_0/RXRstxRANI] [get_bd_pins scalp_dma_fifo_tx_0/RXRstxRANI] [get_bd_pins scalp_fast_router_registers_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn]
diff --git a/xgui/scalp_aurora_phy_rx_fifo_ip_wrapper_v1_0.tcl b/xgui/scalp_aurora_phy_rx_fifo_ip_wrapper_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..84c5be9204760054e3d8425896f4f42d9b63e943
--- /dev/null
+++ b/xgui/scalp_aurora_phy_rx_fifo_ip_wrapper_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_CTRL_TLAST" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_CTRL_TLAST { PARAM_VALUE.C_CTRL_TLAST } {
+ # Procedure called to update C_CTRL_TLAST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_CTRL_TLAST { PARAM_VALUE.C_CTRL_TLAST } {
+ # Procedure called to validate C_CTRL_TLAST
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_CTRL_TLAST { MODELPARAM_VALUE.C_CTRL_TLAST PARAM_VALUE.C_CTRL_TLAST } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_CTRL_TLAST}] ${MODELPARAM_VALUE.C_CTRL_TLAST}
+}
+