From 8fc4033083adb05574e459c9d329dc1587541987 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Fri, 15 Jan 2021 11:01:46 +0100
Subject: [PATCH] Updated the HDL scalp_firmware project to Vivado version
2020.2. This update concerns VHDL, TCL and XCI (IP Core) files.
---
.../2019.2/src/constrs/debug.xdc | 254 --
.../2019.2/src/hdl/scalp_firmware.vhd | 1871 --------------
.../2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl | 1 -
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../.scripts/clean_prj_scalp_firmware.sh | 6 +-
.../.scripts/create_prj_scalp_firmware.sh | 6 +-
.../.scripts/create_prj_scalp_firmware.tcl | 20 +-
.../.scripts/export_hw_scalp_firmware.sh | 6 +-
.../.scripts/export_hw_scalp_firmware.tcl | 6 +-
.../.scripts/gen_bitstream_scalp_firmware.sh | 6 +-
.../.scripts/gen_bitstream_scalp_firmware.tcl | 6 +-
.../.scripts/gen_sw_apps_scalp_firmware.sh | 6 +-
.../.scripts/gen_sw_apps_scalp_firmware.tcl | 6 +-
.../.scripts/load_bitstream_scalp_firmware.sh | 6 +-
.../load_bitstream_scalp_firmware.tcl | 6 +-
.../.scripts/load_sw_app_scalp_firmware.sh | 6 +-
.../.scripts/load_sw_app_scalp_firmware.tcl | 6 +-
.../lin64/.scripts/open_prj_scalp_firmware.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../2020.2/src/constrs/debug.xdc | 0
.../src/constrs/ibert_constraints.xdc | 0
.../src/constrs/scalp_firmware.xdc | 2 +
.../src/constrs/timing_constraints.xdc | 2 +
.../src/hdl/reset_delay_gen.vhd | 2 +-
.../2020.2/src/hdl/scalp_firmware.vhd | 2222 +++++++++++++++++
.../2020.2/src/ipi_tcl/scalp_firmware_ipi.tcl | 1 +
.../src/sim/tb_scalp_firmware.vhd | 6 +-
ips/hw/scalp_aurora_phy/src/hdl/cdc_sync.vhd | 2 +-
.../scalp_aurora_phy/src/hdl/clock_module.vhd | 2 +-
ips/hw/scalp_aurora_phy/src/hdl/gt_common.vhd | 2 +-
.../scalp_aurora_phy/src/hdl/reset_logic.vhd | 2 +-
.../src/hdl/scalp_aurora_phy.vhd | 128 +-
.../src/hdl/scalp_aurora_phy_wrapper.vhd | 2 +-
.../src/ip_core/east_channel/east_channel.xci | 55 +-
.../ip_core/north_channel/north_channel.xci | 55 +-
.../ip_core/south_channel/south_channel.xci | 55 +-
.../src/ip_core/west_channel/west_channel.xci | 55 +-
.../src/sim/tb_scalp_aurora_phy.vhd | 6 +-
.../src/hdl/scalp_aurora_phy_rx_fifo.vhd | 2 +-
.../ip_core/axis_data_fifo/axis_data_fifo.xci | 19 +-
.../src/sim/tb_scalp_aurora_phy_rx_fifo.vhd | 6 +-
ips/hw/scalp_axi4lite/component.xml | 46 +-
.../scalp_axi4lite/src/hdl/scalp_axi4lite.vhd | 53 +-
.../src/hdl/scalp_axi4lite_rd_chan.vhd | 2 +-
.../src/hdl/scalp_axi4lite_wr_chan.vhd | 2 +-
.../src/sim/tb_scalp_axi4lite.vhd | 6 +-
.../xgui/scalp_axi4lite_v1_1.tcl | 145 ++
.../xgui/scalp_axi4lite_v1_2.tcl | 145 ++
.../src/hdl/scalp_design_aurora_clk.vhd | 34 +
.../scalp_aurora_clk/scalp_aurora_clk.xci | 18 +-
.../src/sim/tb_scalp_design_aurora_clk.vhd | 6 +-
.../src/hdl/scalp_design_debug.vhd | 34 +
.../vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci | 18 +-
.../src/sim/tb_scalp_design_debug.vhd | 6 +-
.../src/hdl/scalp_packet_fifo_wrapper.vhd | 2 +-
.../src/sim/tb_scalp_packet_fifo_wrapper.vhd | 6 +-
.../scalp_router/src/hdl/scalp_axis_to_sp.vhd | 109 +-
ips/hw/scalp_router/src/hdl/scalp_misc.vhd | 2 +-
ips/hw/scalp_router/src/hdl/scalp_router.vhd | 54 +-
.../scalp_router/src/hdl/scalp_sp_to_axis.vhd | 27 +-
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../.scripts/clean_prj_scalp_aurora_phy.sh | 6 +-
.../.scripts/create_prj_scalp_aurora_phy.sh | 6 +-
.../.scripts/create_prj_scalp_aurora_phy.tcl | 45 +-
.../.scripts/open_prj_scalp_aurora_phy.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../src/ipi_tcl/scalp_aurora_phy_ipi.tcl} | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../clean_prj_scalp_aurora_phy_rx_fifo.sh | 6 +-
.../create_prj_scalp_aurora_phy_rx_fifo.sh | 6 +-
.../create_prj_scalp_aurora_phy_rx_fifo.tcl | 14 +-
.../open_prj_scalp_aurora_phy_rx_fifo.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../ipi_tcl/scalp_aurora_phy_rx_fifo_ipi.tcl} | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../.scripts/clean_prj_scalp_axi4lite.sh | 6 +-
.../.scripts/create_prj_scalp_axi4lite.sh | 6 +-
.../.scripts/create_prj_scalp_axi4lite.tcl | 14 +-
.../lin64/.scripts/open_prj_scalp_axi4lite.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../src/ipi_tcl/scalp_axi4lite_ipi.tcl} | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../clean_prj_scalp_design_aurora_clk.sh | 6 +-
.../create_prj_scalp_design_aurora_clk.sh | 6 +-
.../create_prj_scalp_design_aurora_clk.tcl | 15 +-
.../open_prj_scalp_design_aurora_clk.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../ipi_tcl/scalp_design_aurora_clk_ipi.tcl} | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../.scripts/clean_prj_scalp_design_debug.sh | 6 +-
.../.scripts/create_prj_scalp_design_debug.sh | 6 +-
.../create_prj_scalp_design_debug.tcl | 19 +-
.../.scripts/open_prj_scalp_design_debug.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../src/ipi_tcl/scalp_design_debug_ipi.tcl | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../clean_prj_scalp_packet_fifo_wrapper.sh | 6 +-
.../create_prj_scalp_packet_fifo_wrapper.sh | 6 +-
.../create_prj_scalp_packet_fifo_wrapper.tcl | 24 +-
.../open_prj_scalp_packet_fifo_wrapper.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../ipi_tcl/scalp_packet_fifo_wrapper_ipi.tcl | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../lin64/.scripts/clean_prj_scalp_router.sh | 6 +-
.../lin64/.scripts/create_prj_scalp_router.sh | 6 +-
.../.scripts/create_prj_scalp_router.tcl | 14 +-
.../lin64/.scripts/open_prj_scalp_router.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../2020.2/src/ipi_tcl/scalp_router_ipi.tcl | 0
.../aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd | 2 +-
.../src/sim/tb_aurora_drp_pkg.vhd | 6 +-
.../src/hdl/aurora_status_pkg.vhd | 22 +-
.../src/sim/tb_aurora_status_pkg.vhd | 6 +-
packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd | 2 +-
packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd | 6 +-
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../.scripts/clean_prj_aurora_drp_pkg.sh | 6 +-
.../.scripts/create_prj_aurora_drp_pkg.sh | 6 +-
.../.scripts/create_prj_aurora_drp_pkg.tcl | 21 +-
.../lin64/.scripts/open_prj_aurora_drp_pkg.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../2020.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../.scripts/clean_prj_aurora_status_pkg.sh | 6 +-
.../.scripts/create_prj_aurora_status_pkg.sh | 6 +-
.../.scripts/create_prj_aurora_status_pkg.tcl | 21 +-
.../.scripts/open_prj_aurora_status_pkg.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../src/ipi_tcl/aurora_status_pkg_ipi.tcl | 0
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../lin64/.scripts/clean_prj_axi4_pkg.sh | 6 +-
.../lin64/.scripts/create_prj_axi4_pkg.sh | 6 +-
.../lin64/.scripts/create_prj_axi4_pkg.tcl | 21 +-
.../lin64/.scripts/open_prj_axi4_pkg.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../2020.2/src/ipi_tcl/axi4_pkg_ipi.tcl | 0
.../src/hdl/scalp_zynqps_wrapper.vhd | 2 +-
.../scalp_zynqps/src/sim/tb_scalp_zynqps.vhd | 6 +-
.../lin64/.scripts/.prompt_colors.tcl | 6 +-
.../lin64/.scripts/clean_prj_scalp_zynqps.sh | 6 +-
.../lin64/.scripts/create_prj_scalp_zynqps.sh | 6 +-
.../.scripts/create_prj_scalp_zynqps.tcl | 57 +-
.../lin64/.scripts/open_prj_scalp_zynqps.sh | 6 +-
.../lin64/.scripts/utils.tcl | 6 +-
.../{2019.2 => 2020.2}/lin64/setup.sh | 6 +-
.../src/ipi_tcl/scalp_zynqps_ipi.tcl | 68 +-
tools/config/aurora_drp_pkg.json | 4 +-
tools/config/aurora_status_pkg.json | 4 +-
tools/config/axi4_pkg.json | 4 +-
tools/config/scalp_aurora_phy.json | 11 +-
tools/config/scalp_aurora_phy_rx_fifo.json | 4 +-
tools/config/scalp_axi4lite.json | 4 +-
tools/config/scalp_design_aurora_clk.json | 4 +-
tools/config/scalp_design_debug.json | 4 +-
tools/config/scalp_firmware.json | 4 +-
tools/config/scalp_packet_fifo_wrapper.json | 4 +-
tools/config/scalp_router.json | 4 +-
tools/config/scalp_zynqps.json | 4 +-
tools/vivado_prj_creator | 2 +-
170 files changed, 3640 insertions(+), 2781 deletions(-)
delete mode 100644 designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
delete mode 100644 designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
delete mode 100644 designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_firmware.sh (88%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_firmware.sh (86%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_firmware.tcl (93%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/export_hw_scalp_firmware.sh (86%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/export_hw_scalp_firmware.tcl (90%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/gen_bitstream_scalp_firmware.sh (88%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/gen_bitstream_scalp_firmware.tcl (92%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/gen_sw_apps_scalp_firmware.sh (90%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl (94%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/load_bitstream_scalp_firmware.sh (86%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/load_bitstream_scalp_firmware.tcl (93%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/load_sw_app_scalp_firmware.sh (86%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/load_sw_app_scalp_firmware.tcl (92%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_firmware.sh (85%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename ips/vivado/scalp_aurora_phy/2019.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl => designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc (100%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/src/constrs/ibert_constraints.xdc (100%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/src/constrs/scalp_firmware.xdc (99%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/src/constrs/timing_constraints.xdc (99%)
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/src/hdl/reset_delay_gen.vhd (98%)
create mode 100644 designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
create mode 100644 designs/vivado/scalp_firmware/2020.2/src/ipi_tcl/scalp_firmware_ipi.tcl
rename designs/vivado/scalp_firmware/{2019.2 => 2020.2}/src/sim/tb_scalp_firmware.vhd (87%)
create mode 100644 ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_1.tcl
create mode 100644 ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_2.tcl
create mode 100644 ips/hw/scalp_design_aurora_clk/src/hdl/scalp_design_aurora_clk.vhd
create mode 100644 ips/hw/scalp_design_debug/src/hdl/scalp_design_debug.vhd
rename ips/vivado/scalp_aurora_phy/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename ips/vivado/scalp_aurora_phy/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_aurora_phy.sh (88%)
rename ips/vivado/scalp_aurora_phy/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_aurora_phy.sh (86%)
rename ips/vivado/scalp_aurora_phy/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_aurora_phy.tcl (77%)
rename ips/vivado/scalp_aurora_phy/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_aurora_phy.sh (85%)
rename ips/vivado/scalp_aurora_phy/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename ips/vivado/scalp_aurora_phy/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename ips/vivado/{scalp_design_aurora_clk/2019.2/src/ipi_tcl/scalp_design_aurora_clk_ipi.tcl => scalp_aurora_phy/2020.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl} (100%)
rename ips/vivado/scalp_aurora_phy_rx_fifo/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename ips/vivado/scalp_aurora_phy_rx_fifo/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh (89%)
rename ips/vivado/scalp_aurora_phy_rx_fifo/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh (86%)
rename ips/vivado/scalp_aurora_phy_rx_fifo/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl (94%)
rename ips/vivado/scalp_aurora_phy_rx_fifo/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh (86%)
rename ips/vivado/scalp_aurora_phy_rx_fifo/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename ips/vivado/scalp_aurora_phy_rx_fifo/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename ips/vivado/{scalp_design_debug/2019.2/src/ipi_tcl/scalp_design_debug_ipi.tcl => scalp_aurora_phy_rx_fifo/2020.2/src/ipi_tcl/scalp_aurora_phy_rx_fifo_ipi.tcl} (100%)
rename ips/vivado/scalp_axi4lite/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename ips/vivado/scalp_axi4lite/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_axi4lite.sh (88%)
rename ips/vivado/scalp_axi4lite/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_axi4lite.sh (86%)
rename ips/vivado/scalp_axi4lite/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_axi4lite.tcl (95%)
rename ips/vivado/scalp_axi4lite/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_axi4lite.sh (85%)
rename ips/vivado/scalp_axi4lite/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename ips/vivado/scalp_axi4lite/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename ips/vivado/{scalp_packet_fifo_wrapper/2019.2/src/ipi_tcl/scalp_packet_fifo_wrapper_ipi.tcl => scalp_axi4lite/2020.2/src/ipi_tcl/scalp_axi4lite_ipi.tcl} (100%)
rename ips/vivado/scalp_design_aurora_clk/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename ips/vivado/scalp_design_aurora_clk/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_design_aurora_clk.sh (89%)
rename ips/vivado/scalp_design_aurora_clk/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_design_aurora_clk.sh (86%)
rename ips/vivado/scalp_design_aurora_clk/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_design_aurora_clk.tcl (92%)
rename ips/vivado/scalp_design_aurora_clk/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_design_aurora_clk.sh (86%)
rename ips/vivado/scalp_design_aurora_clk/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename ips/vivado/scalp_design_aurora_clk/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename ips/vivado/{scalp_router/2019.2/src/ipi_tcl/scalp_router_ipi.tcl => scalp_design_aurora_clk/2020.2/src/ipi_tcl/scalp_design_aurora_clk_ipi.tcl} (100%)
rename ips/vivado/scalp_design_debug/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename ips/vivado/scalp_design_debug/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_design_debug.sh (89%)
rename ips/vivado/scalp_design_debug/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_design_debug.sh (86%)
rename ips/vivado/scalp_design_debug/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_design_debug.tcl (90%)
rename ips/vivado/scalp_design_debug/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_design_debug.sh (86%)
rename ips/vivado/scalp_design_debug/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename ips/vivado/scalp_design_debug/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename packages/vivado/aurora_drp_pkg/2019.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl => ips/vivado/scalp_design_debug/2020.2/src/ipi_tcl/scalp_design_debug_ipi.tcl (100%)
rename ips/vivado/scalp_packet_fifo_wrapper/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename ips/vivado/scalp_packet_fifo_wrapper/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_packet_fifo_wrapper.sh (89%)
rename ips/vivado/scalp_packet_fifo_wrapper/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.sh (86%)
rename ips/vivado/scalp_packet_fifo_wrapper/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.tcl (86%)
rename ips/vivado/scalp_packet_fifo_wrapper/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_packet_fifo_wrapper.sh (86%)
rename ips/vivado/scalp_packet_fifo_wrapper/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename ips/vivado/scalp_packet_fifo_wrapper/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename packages/vivado/aurora_status_pkg/2019.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl => ips/vivado/scalp_packet_fifo_wrapper/2020.2/src/ipi_tcl/scalp_packet_fifo_wrapper_ipi.tcl (100%)
rename ips/vivado/scalp_router/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename ips/vivado/scalp_router/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_router.sh (88%)
rename ips/vivado/scalp_router/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_router.sh (86%)
rename ips/vivado/scalp_router/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_router.tcl (96%)
rename ips/vivado/scalp_router/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_router.sh (85%)
rename ips/vivado/scalp_router/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename ips/vivado/scalp_router/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename packages/vivado/axi4_pkg/2019.2/src/ipi_tcl/axi4_pkg_ipi.tcl => ips/vivado/scalp_router/2020.2/src/ipi_tcl/scalp_router_ipi.tcl (100%)
rename packages/vivado/aurora_drp_pkg/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename packages/vivado/aurora_drp_pkg/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_aurora_drp_pkg.sh (88%)
rename packages/vivado/aurora_drp_pkg/{2019.2 => 2020.2}/lin64/.scripts/create_prj_aurora_drp_pkg.sh (86%)
rename packages/vivado/aurora_drp_pkg/{2019.2 => 2020.2}/lin64/.scripts/create_prj_aurora_drp_pkg.tcl (90%)
rename packages/vivado/aurora_drp_pkg/{2019.2 => 2020.2}/lin64/.scripts/open_prj_aurora_drp_pkg.sh (85%)
rename packages/vivado/aurora_drp_pkg/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename packages/vivado/aurora_drp_pkg/{2019.2 => 2020.2}/lin64/setup.sh (91%)
create mode 100644 packages/vivado/aurora_drp_pkg/2020.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl
rename packages/vivado/aurora_status_pkg/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename packages/vivado/aurora_status_pkg/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_aurora_status_pkg.sh (89%)
rename packages/vivado/aurora_status_pkg/{2019.2 => 2020.2}/lin64/.scripts/create_prj_aurora_status_pkg.sh (86%)
rename packages/vivado/aurora_status_pkg/{2019.2 => 2020.2}/lin64/.scripts/create_prj_aurora_status_pkg.tcl (90%)
rename packages/vivado/aurora_status_pkg/{2019.2 => 2020.2}/lin64/.scripts/open_prj_aurora_status_pkg.sh (85%)
rename packages/vivado/aurora_status_pkg/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename packages/vivado/aurora_status_pkg/{2019.2 => 2020.2}/lin64/setup.sh (91%)
create mode 100644 packages/vivado/aurora_status_pkg/2020.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl
rename packages/vivado/axi4_pkg/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename packages/vivado/axi4_pkg/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_axi4_pkg.sh (88%)
rename packages/vivado/axi4_pkg/{2019.2 => 2020.2}/lin64/.scripts/create_prj_axi4_pkg.sh (86%)
rename packages/vivado/axi4_pkg/{2019.2 => 2020.2}/lin64/.scripts/create_prj_axi4_pkg.tcl (90%)
rename packages/vivado/axi4_pkg/{2019.2 => 2020.2}/lin64/.scripts/open_prj_axi4_pkg.sh (85%)
rename packages/vivado/axi4_pkg/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename packages/vivado/axi4_pkg/{2019.2 => 2020.2}/lin64/setup.sh (90%)
create mode 100644 packages/vivado/axi4_pkg/2020.2/src/ipi_tcl/axi4_pkg_ipi.tcl
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/lin64/.scripts/.prompt_colors.tcl (89%)
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/lin64/.scripts/clean_prj_scalp_zynqps.sh (88%)
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_zynqps.sh (86%)
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/lin64/.scripts/create_prj_scalp_zynqps.tcl (67%)
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/lin64/.scripts/open_prj_scalp_zynqps.sh (85%)
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/lin64/.scripts/utils.tcl (94%)
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/lin64/setup.sh (91%)
rename soc/vivado/scalp_zynqps/{2019.2 => 2020.2}/src/ipi_tcl/scalp_zynqps_ipi.tcl (89%)
diff --git a/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
deleted file mode 100644
index e727a29..0000000
--- a/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
+++ /dev/null
@@ -1,254 +0,0 @@
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 4 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {SouthWritePhyStatexDP[0]} {SouthWritePhyStatexDP[1]} {SouthWritePhyStatexDP[2]} {SouthWritePhyStatexDP[3]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 2 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {SouthReadPhyStatexDP[0]} {SouthReadPhyStatexDP[1]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 32 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {SouthRXM2SxD[DataxD][31]} {SouthRXM2SxD[DataxD][30]} {SouthRXM2SxD[DataxD][29]} {SouthRXM2SxD[DataxD][28]} {SouthRXM2SxD[DataxD][27]} {SouthRXM2SxD[DataxD][26]} {SouthRXM2SxD[DataxD][25]} {SouthRXM2SxD[DataxD][24]} {SouthRXM2SxD[DataxD][23]} {SouthRXM2SxD[DataxD][22]} {SouthRXM2SxD[DataxD][21]} {SouthRXM2SxD[DataxD][20]} {SouthRXM2SxD[DataxD][19]} {SouthRXM2SxD[DataxD][18]} {SouthRXM2SxD[DataxD][17]} {SouthRXM2SxD[DataxD][16]} {SouthRXM2SxD[DataxD][15]} {SouthRXM2SxD[DataxD][14]} {SouthRXM2SxD[DataxD][13]} {SouthRXM2SxD[DataxD][12]} {SouthRXM2SxD[DataxD][11]} {SouthRXM2SxD[DataxD][10]} {SouthRXM2SxD[DataxD][9]} {SouthRXM2SxD[DataxD][8]} {SouthRXM2SxD[DataxD][7]} {SouthRXM2SxD[DataxD][6]} {SouthRXM2SxD[DataxD][5]} {SouthRXM2SxD[DataxD][4]} {SouthRXM2SxD[DataxD][3]} {SouthRXM2SxD[DataxD][2]} {SouthRXM2SxD[DataxD][1]} {SouthRXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 4 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {NorthWritePhyStatexDP[0]} {NorthWritePhyStatexDP[1]} {NorthWritePhyStatexDP[2]} {NorthWritePhyStatexDP[3]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 2 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {NorthReadPhyStatexDP[0]} {NorthReadPhyStatexDP[1]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 32 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {NorthRXM2SxD[DataxD][31]} {NorthRXM2SxD[DataxD][30]} {NorthRXM2SxD[DataxD][29]} {NorthRXM2SxD[DataxD][28]} {NorthRXM2SxD[DataxD][27]} {NorthRXM2SxD[DataxD][26]} {NorthRXM2SxD[DataxD][25]} {NorthRXM2SxD[DataxD][24]} {NorthRXM2SxD[DataxD][23]} {NorthRXM2SxD[DataxD][22]} {NorthRXM2SxD[DataxD][21]} {NorthRXM2SxD[DataxD][20]} {NorthRXM2SxD[DataxD][19]} {NorthRXM2SxD[DataxD][18]} {NorthRXM2SxD[DataxD][17]} {NorthRXM2SxD[DataxD][16]} {NorthRXM2SxD[DataxD][15]} {NorthRXM2SxD[DataxD][14]} {NorthRXM2SxD[DataxD][13]} {NorthRXM2SxD[DataxD][12]} {NorthRXM2SxD[DataxD][11]} {NorthRXM2SxD[DataxD][10]} {NorthRXM2SxD[DataxD][9]} {NorthRXM2SxD[DataxD][8]} {NorthRXM2SxD[DataxD][7]} {NorthRXM2SxD[DataxD][6]} {NorthRXM2SxD[DataxD][5]} {NorthRXM2SxD[DataxD][4]} {NorthRXM2SxD[DataxD][3]} {NorthRXM2SxD[DataxD][2]} {NorthRXM2SxD[DataxD][1]} {NorthRXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-set_property port_width 4 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-set_property port_width 32 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-set_property port_width 4 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-set_property port_width 32 [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-set_property port_width 2 [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXFifoResetDoneStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXFifoResetDoneStatexDP[1]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-set_property port_width 3 [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthNFCStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthNFCStatexDP[1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthNFCStatexDP[2]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-set_property port_width 4 [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-set_property port_width 32 [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-set_property port_width 4 [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-set_property port_width 32 [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-set_property port_width 2 [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXFifoResetDoneStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXFifoResetDoneStatexDP[1]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-set_property port_width 3 [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthNFCStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthNFCStatexDP[1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthNFCStatexDP[2]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-set_property port_width 1 [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthProgEmptyxSP]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-set_property port_width 1 [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthProgFullxSP]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-set_property port_width 1 [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {NorthRXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-set_property port_width 1 [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-set_property port_width 1 [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-set_property port_width 1 [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {NorthRXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-set_property port_width 1 [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list {NorthRXS2MxD[ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-set_property port_width 1 [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-set_property port_width 1 [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-set_property port_width 1 [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-set_property port_width 1 [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCS2MxD[ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXS2MxD[ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[EastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[NorthxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-set_property port_width 1 [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[SouthxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[WestxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-set_property port_width 1 [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[EastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
-set_property port_width 1 [get_debug_ports u_ila_0/probe36]
-connect_debug_port u_ila_0/probe36 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[NorthxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
-set_property port_width 1 [get_debug_ports u_ila_0/probe37]
-connect_debug_port u_ila_0/probe37 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[SouthxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
-set_property port_width 1 [get_debug_ports u_ila_0/probe38]
-connect_debug_port u_ila_0/probe38 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[WestxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
-set_property port_width 1 [get_debug_ports u_ila_0/probe39]
-connect_debug_port u_ila_0/probe39 [get_nets [list {RXResetxR[BackPressureResetxR][EastxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
-set_property port_width 1 [get_debug_ports u_ila_0/probe40]
-connect_debug_port u_ila_0/probe40 [get_nets [list {RXResetxR[BackPressureResetxR][NorthxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
-set_property port_width 1 [get_debug_ports u_ila_0/probe41]
-connect_debug_port u_ila_0/probe41 [get_nets [list {RXResetxR[BackPressureResetxR][SouthxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
-set_property port_width 1 [get_debug_ports u_ila_0/probe42]
-connect_debug_port u_ila_0/probe42 [get_nets [list {RXResetxR[BackPressureResetxR][WestxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
-set_property port_width 1 [get_debug_ports u_ila_0/probe43]
-connect_debug_port u_ila_0/probe43 [get_nets [list {RXResetxR[FifoResetxR][EastxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
-set_property port_width 1 [get_debug_ports u_ila_0/probe44]
-connect_debug_port u_ila_0/probe44 [get_nets [list {RXResetxR[FifoResetxR][NorthxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
-set_property port_width 1 [get_debug_ports u_ila_0/probe45]
-connect_debug_port u_ila_0/probe45 [get_nets [list {RXResetxR[FifoResetxR][SouthxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
-set_property port_width 1 [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list {RXResetxR[FifoResetxR][WestxR]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
-set_property port_width 1 [get_debug_ports u_ila_0/probe47]
-connect_debug_port u_ila_0/probe47 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthProgEmptyxSP]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
-set_property port_width 1 [get_debug_ports u_ila_0/probe48]
-connect_debug_port u_ila_0/probe48 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthProgFullxSP]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
-set_property port_width 1 [get_debug_ports u_ila_0/probe49]
-connect_debug_port u_ila_0/probe49 [get_nets [list {SouthRXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
-set_property port_width 1 [get_debug_ports u_ila_0/probe50]
-connect_debug_port u_ila_0/probe50 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
-set_property port_width 1 [get_debug_ports u_ila_0/probe51]
-connect_debug_port u_ila_0/probe51 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
-set_property port_width 1 [get_debug_ports u_ila_0/probe52]
-connect_debug_port u_ila_0/probe52 [get_nets [list {SouthRXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
-set_property port_width 1 [get_debug_ports u_ila_0/probe53]
-connect_debug_port u_ila_0/probe53 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
-set_property port_width 1 [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list {SouthRXS2MxD[ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
-set_property port_width 1 [get_debug_ports u_ila_0/probe55]
-connect_debug_port u_ila_0/probe55 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
-set_property port_width 1 [get_debug_ports u_ila_0/probe56]
-connect_debug_port u_ila_0/probe56 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
-set_property port_width 1 [get_debug_ports u_ila_0/probe57]
-connect_debug_port u_ila_0/probe57 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
-set_property port_width 1 [get_debug_ports u_ila_0/probe58]
-connect_debug_port u_ila_0/probe58 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCS2mxD[ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
-set_property port_width 1 [get_debug_ports u_ila_0/probe59]
-connect_debug_port u_ila_0/probe59 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXS2MxD[ReadyxS]}]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
deleted file mode 100644
index 546fa84..0000000
--- a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
+++ /dev/null
@@ -1,1871 +0,0 @@
-----------------------------------------------------------------------------------
--- _ _
--- | |_ ___ _ __(_)__ _
--- | ' \/ -_) '_ \ / _` |
--- |_||_\___| .__/_\__,_|
--- |_|
---
-----------------------------------------------------------------------------------
---
--- Company: hepia
--- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
---
--- Module Name: scalp_firmware - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
--- Description: scalp_firmware
---
--- Last update: 2020-11-26
---
----------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
--- Aurora packages
-use work.aurora_status_pkg.all;
-use work.aurora_drp_pkg.all;
--- Axi4 packages
-use work.axi4_pkg.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity scalp_firmware is
-
- generic (
- C_USE_IBERT : boolean := false;
- C_DEBUG_MODE : boolean := false;
- C_RX_FIFO_MODE : boolean := true);
-
- port (
- -----------------------------------------------------------------------
- -- Names defined and not described in the constraint file.
- -----------------------------------------------------------------------
- -- Zynq FIXED_IO
- PSClkxCIO : inout std_logic;
- PSSRstxRNIO : inout std_logic;
- PSPorxSNIO : inout std_logic;
- -- DDR interface
- DDRClkNxCIO : inout std_logic;
- DDRClkPxCIO : inout std_logic;
- DDRDRstxRNIO : inout std_logic;
- DDRCasNxSIO : inout std_logic;
- DDRCkexSIO : inout std_logic;
- DDRCsNxSIO : inout std_logic;
- DDROdtxSIO : inout std_logic;
- DDRRasNxSIO : inout std_logic;
- DDRWexSNIO : inout std_logic;
- DDRBankAddrxDIO : inout std_logic_vector(2 downto 0);
- DDRAddrxDIO : inout std_logic_vector(14 downto 0);
- DDRVrNxSIO : inout std_logic;
- DDRVrPxSIO : inout std_logic;
- DDRDmxDIO : inout std_logic_vector(3 downto 0);
- DDRDqxDIO : inout std_logic_vector(31 downto 0);
- DDRDqsNxDIO : inout std_logic_vector(3 downto 0);
- DDRDqsPxDIO : inout std_logic_vector(3 downto 0);
- -- MIO Interface
- MIOxDIO : inout std_logic_vector(53 downto 0);
- -----------------------------------------------------------------------
- -- USB signals
- UsbVbusPwrFaultxSI : in std_logic;
- -- PLL interface
- Pll2V5ClkuWirexCO : out std_logic; -- Clock (from SPI1_SCLK)
- Pll2V5DatauWirexSO : out std_logic; -- Data (from SPI1_MOSI)
- Pll2V5LEuWirexSO : out std_logic; -- Latch enable (from SPI1_SS)
- Pll2V5GOExSO : out std_logic; -- Global Output Enable
- Pll2V5LDxSI : in std_logic; -- Lock Detect
- Pll2V5SyncxSO : out std_logic; -- Sync
- Pll2V5ClkIn0LOSxSI : in std_logic; -- FPGA clock Loss of Sync
- Pll2V5ClkIn1LOSxSI : in std_logic; -- External oscillator Loss of Sync
- -- GTP interfaces
- -- Clocks
- GTPRefClk0PxCI : in std_logic;
- GTPRefClk0NxCI : in std_logic;
- GTPRefClk1PxCI : in std_logic;
- GTPRefClk1NxCI : in std_logic;
- -- North
- GTPFromNorthPxSI : in std_logic;
- GTPFromNorthNxSI : in std_logic;
- GTPToNorthPxSO : out std_logic;
- GTPToNorthNxSO : out std_logic;
- -- East
- GTPFromEastPxSI : in std_logic;
- GTPFromEastNxSI : in std_logic;
- GTPToEastPxSO : out std_logic;
- GTPToEastNxSO : out std_logic;
- -- South
- GTPFromSouthPxSI : in std_logic;
- GTPFromSouthNxSI : in std_logic;
- GTPToSouthPxSO : out std_logic;
- GTPToSouthNxSO : out std_logic;
- -- West
- GTPFromWestPxSI : in std_logic;
- GTPFromWestNxSI : in std_logic;
- GTPToWestPxSO : out std_logic;
- GTPToWestNxSO : out std_logic;
- -- LVDS links towards edge connectors
- -- North
- -- LVDS2V5North0PxSIO : inout std_logic;
- -- LVDS2V5North0NxSIO : inout std_logic;
- -- LVDS2V5North1PxSIO : inout std_logic;
- -- LVDS2V5North1NxSIO : inout std_logic;
- -- LVDS2V5North2PxSIO : inout std_logic;
- -- LVDS2V5North2NxSIO : inout std_logic;
- -- LVDS2V5North3PxSIO : inout std_logic;
- -- LVDS2V5North3NxSIO : inout std_logic;
- -- LVDS2V5North4PxSIO : inout std_logic;
- -- LVDS2V5North4NxSIO : inout std_logic;
- -- LVDS2V5North5PxSIO : inout std_logic;
- -- LVDS2V5North5NxSIO : inout std_logic;
- -- LVDS2V5North6PxSIO : inout std_logic;
- -- LVDS2V5North6NxSIO : inout std_logic;
- -- LVDS2V5North7PxSIO : inout std_logic;
- -- LVDS2V5North7NxSIO : inout std_logic;
- -- South
- -- LVDS2V5South0PxSIO : inout std_logic;
- -- LVDS2V5South0NxSIO : inout std_logic;
- -- LVDS2V5South1PxSIO : inout std_logic;
- -- LVDS2V5South1NxSIO : inout std_logic;
- -- LVDS2V5South2PxSIO : inout std_logic;
- -- LVDS2V5South2NxSIO : inout std_logic;
- -- LVDS2V5South3PxSIO : inout std_logic;
- -- LVDS2V5South3NxSIO : inout std_logic;
- -- LVDS2V5South4PxSIO : inout std_logic;
- -- LVDS2V5South4NxSIO : inout std_logic;
- -- LVDS2V5South5PxSIO : inout std_logic;
- -- LVDS2V5South5NxSIO : inout std_logic;
- -- LVDS2V5South6PxSIO : inout std_logic;
- -- LVDS2V5South6NxSIO : inout std_logic;
- -- LVDS2V5South7PxSIO : inout std_logic;
- -- LVDS2V5South7NxSIO : inout std_logic;
- -- East
- -- LVDS2V5East0PxSIO : inout std_logic;
- -- LVDS2V5East0NxSIO : inout std_logic;
- -- LVDS2V5East1PxSIO : inout std_logic;
- -- LVDS2V5East1NxSIO : inout std_logic;
- -- LVDS2V5East2PxSIO : inout std_logic;
- -- LVDS2V5East2NxSIO : inout std_logic;
- -- LVDS2V5East3PxSIO : inout std_logic;
- -- LVDS2V5East3NxSIO : inout std_logic;
- -- LVDS2V5East4PxSIO : inout std_logic;
- -- LVDS2V5East4NxSIO : inout std_logic;
- -- LVDS2V5East5PxSIO : inout std_logic;
- -- LVDS2V5East5NxSIO : inout std_logic;
- -- LVDS2V5East6PxSIO : inout std_logic;
- -- LVDS2V5East6NxSIO : inout std_logic;
- -- LVDS2V5East7PxSIO : inout std_logic;
- -- LVDS2V5East7NxSIO : inout std_logic;
- -- West
- -- LVDS2V5West0PxSIO : inout std_logic;
- -- LVDS2V5West0NxSIO : inout std_logic;
- -- LVDS2V5West1PxSIO : inout std_logic;
- -- LVDS2V5West1NxSIO : inout std_logic;
- -- LVDS2V5West2PxSIO : inout std_logic;
- -- LVDS2V5West2NxSIO : inout std_logic;
- -- LVDS2V5West3PxSIO : inout std_logic;
- -- LVDS2V5West3NxSIO : inout std_logic;
- -- LVDS2V5West4PxSIO : inout std_logic;
- -- LVDS2V5West4NxSIO : inout std_logic;
- -- LVDS2V5West5PxSIO : inout std_logic;
- -- LVDS2V5West5NxSIO : inout std_logic;
- -- LVDS2V5West6PxSIO : inout std_logic;
- -- LVDS2V5West6NxSIO : inout std_logic;
- -- LVDS2V5West7PxSIO : inout std_logic;
- -- LVDS2V5West7NxSIO : inout std_logic;
- -- LVDS links towards top-bottom connectors
- -- Top
- -- LVDS2V5Top0PxSIO : inout std_logic;
- -- LVDS2V5Top0NxSIO : inout std_logic;
- -- LVDS2V5Top1PxSIO : inout std_logic;
- -- LVDS2V5Top1NxSIO : inout std_logic;
- -- LVDS2V5Top2PxSIO : inout std_logic;
- -- LVDS2V5Top2NxSIO : inout std_logic;
- -- LVDS2V5Top3PxSIO : inout std_logic;
- -- LVDS2V5Top3NxSIO : inout std_logic;
- -- LVDS2V5Top4PxSIO : inout std_logic;
- -- LVDS2V5Top4NxSIO : inout std_logic;
- -- LVDS2V5Top5PxSIO : inout std_logic;
- -- LVDS2V5Top5NxSIO : inout std_logic;
- -- LVDS2V5Top6PxSIO : inout std_logic;
- -- LVDS2V5Top6NxSIO : inout std_logic;
- -- LVDS2V5Top7PxSIO : inout std_logic;
- -- LVDS2V5Top7NxSIO : inout std_logic;
- -- Bottom
- -- LVDS2V5Bottom0PxSIO : inout std_logic;
- -- LVDS2V5Bottom0NxSIO : inout std_logic;
- -- LVDS2V5Bottom1PxSIO : inout std_logic;
- -- LVDS2V5Bottom1NxSIO : inout std_logic;
- -- LVDS2V5Bottom2PxSIO : inout std_logic;
- -- LVDS2V5Bottom2NxSIO : inout std_logic;
- -- LVDS2V5Bottom3PxSIO : inout std_logic;
- -- LVDS2V5Bottom3NxSIO : inout std_logic;
- -- LVDS2V5Bottom4PxSIO : inout std_logic;
- -- LVDS2V5Bottom4NxSIO : inout std_logic;
- -- LVDS2V5Bottom5PxSIO : inout std_logic;
- -- LVDS2V5Bottom5NxSIO : inout std_logic;
- -- LVDS2V5Bottom6PxSIO : inout std_logic;
- -- LVDS2V5Bottom6NxSIO : inout std_logic;
- -- LVDS2V5Bottom7PxSIO : inout std_logic;
- -- LVDS2V5Bottom7NxSIO : inout std_logic;
- -- RGB LEDs
- Led12V5RxSO : out std_logic;
- Led12V5GxSO : out std_logic;
- Led12V5BxSO : out std_logic;
- Led22V5RxSO : out std_logic;
- Led22V5GxSO : out std_logic;
- Led22V5BxSO : out std_logic;
- -- Self reset (connected to PS_SRSTB)
- SelfRstxRNO : out std_logic);
- -- Clocks from PLLs (connected to MRCC pins)
- -- Local
- -- PLLClk2V5LocalPxCI : in std_logic;
- -- PLLClk2V5LocalNxCI : in std_logic;
- -- -- North
- -- PLLClk2V5NorthPxCI : in std_logic;
- -- PLLClk2V5NorthNxCI : in std_logic;
- -- -- South
- -- PLLClk2V5SouthPxCI : in std_logic;
- -- PLLClk2V5SouthNxCI : in std_logic;
- -- -- Top
- -- PLLClk2V5TopxCI : in std_logic; -- Single-ended
- -- -- Bottom
- -- PLLClk2V5BottomxCI : in std_logic; -- Single-ended
- -- -- Clocks to/from neighbours
- -- -- North
- -- Clk2V5NorthPxCI : in std_logic;
- -- Clk2V5NorthNxCI : in std_logic;
- -- Clk2V5NorthPxCO : out std_logic;
- -- Clk2V5NorthNxCO : out std_logic;
- -- -- South
- -- Clk2V5SouthPxCI : in std_logic;
- -- Clk2V5SouthNxCI : in std_logic;
- -- Clk2V5SouthPxCO : out std_logic;
- -- Clk2V5SouthNxCO : out std_logic;
- -- -- East
- -- Clk2V5EastPxCI : in std_logic;
- -- Clk2V5EastNxCI : in std_logic;
- -- Clk2V5EastPxCO : out std_logic;
- -- Clk2V5EastNxCO : out std_logic;
- -- -- West
- -- Clk2V5WestPxCI : in std_logic;
- -- Clk2V5WestNxCI : in std_logic;
- -- Clk2V5WestPxCO : out std_logic;
- -- Clk2V5WestNxCO : out std_logic;
- -- -- Top
- -- Clk2V5TopPxCI : in std_logic;
- -- Clk2V5TopNxCI : in std_logic;
- -- Clk2V5TopPxCO : out std_logic;
- -- Clk2V5TopNxCO : out std_logic;
- -- -- Bottom
- -- Clk2V5BottomPxCI : in std_logic;
- -- Clk2V5BottomNxCI : in std_logic;
- -- Clk2V5BottomPxCO : out std_logic;
- -- Clk2V5BottomNxCO : out std_logic;
- -- -- Recovery
- -- Clk2V5RecoveryPxCO : out std_logic;
- -- Clk2V5RecoveryNxCO : out std_logic);
-
-end scalp_firmware;
-
-
-architecture arch of scalp_firmware is
-
- -- Constantes
- -- constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
- constant C_AXI_ADDR_SIZE : integer range 0 to 32 := 12;
-
- component scalp_aurora_phy is
- generic (
- C_DEBUG_MODE : boolean;
- C_RX_FIFO_MODE : boolean);
- port (
- GTRefClkxCI : in t_gt_ref_slave_clk;
- AuroraClkxCI : in t_aurora_slave_clk;
- AuroraClkxCO : out t_aurora_master_clk;
- AuroraResetxRI : in t_aurora_slave_reset;
- AuroraResetxRO : out t_aurora_master_link_reset;
- RXResetxRI : in t_rx_reset;
- RXFifoResetDonexDO : out t_rx_fifo_reset_done;
- GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
- GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
- GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
- GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
- GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
- GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
- GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
- GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
- NorthRXM2SxDO : out t_axi4m2s;
- NorthRXS2MxDI : in t_axi4s2m;
- NorthTXM2SxDI : in t_axi4m2s;
- NorthTXS2MxDO : out t_axi4s2m;
- EastRXM2SxDO : out t_axi4m2s;
- EastRXS2MxDI : in t_axi4s2m;
- EastTXM2SxDI : in t_axi4m2s;
- EastTXS2MxDO : out t_axi4s2m;
- SouthRXM2SxDO : out t_axi4m2s;
- SouthRXS2MxDI : in t_axi4s2m;
- SouthTXM2SxDI : in t_axi4m2s;
- SouthTXS2MxDO : out t_axi4s2m;
- WestRXM2SxDO : out t_axi4m2s;
- WestRXS2MxDI : in t_axi4s2m;
- WestTXM2SxDI : in t_axi4m2s;
- WestTXS2MxDO : out t_axi4s2m;
- NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
- WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
- WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
- NorthRXNFCM2SxDO : out t_axi4nfcm2s;
- NorthTXNFCM2SxDI : in t_axi4nfcm2s;
- NorthTXNFCS2MxDO : out t_axi4nfcs2m;
- EastRXNFCM2SxDO : out t_axi4nfcm2s;
- EastTXNFCM2SxDI : in t_axi4nfcm2s;
- EastTXNFCS2MxDO : out t_axi4nfcs2m;
- SouthRXNFCM2SxDO : out t_axi4nfcm2s;
- SouthTXNFCM2SxDI : in t_axi4nfcm2s;
- SouthTXNFCS2mxDO : out t_axi4nfcs2m;
- WestRXNFCM2SxDO : out t_axi4nfcm2s;
- WestTXNFCM2SxDI : in t_axi4nfcm2s;
- WestTXNFCS2MxDO : out t_axi4nfcs2m;
- AuroraCtrlxDI : in t_aurora_control;
- AuroraStatusxDO : out t_aurora_status;
- AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
- AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0);
- NorthRXFifoStatusxDO : out t_axi4fifo_status;
- EastRXFifoStatusxDO : out t_axi4fifo_status;
- SouthRXFifoStatusxDO : out t_axi4fifo_status;
- WestRXFifoStatusxDO : out t_axi4fifo_status;
- AxisFifoErrorxDO : out t_axi4fifo_error);
- end component scalp_aurora_phy;
-
- -- Signals
- -- Clocks
- -- Processing system clock
- signal PSSysClkxC : std_logic := '0';
- -- GTP Clocks
- -- signal GTPRefClk0xC : std_logic := '0';
- -- signal GTPRefClk1xC : std_logic := '0';
- signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
- signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
- -- Resets
- -- Processing system reset
- signal PSSysResetxR : std_logic := '0';
- -- Scalp Aurora Phy
- signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
- signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
- signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
- signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
- signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
- signal RXResetxR : t_rx_reset := C_NO_RX_RESET;
- signal RXFifoResetDonexD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
- signal RXFifoResetDoneDelayedxD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
- signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
- signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
- signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
- signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
- signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
- signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
- signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
- signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
- signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
- signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
- signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
- signal NorthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal EastRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal SouthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal WestRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal AxisFifoErrorxD : t_axi4fifo_error := C_NO_AXI4_FIFO_ERROR;
- -- Scalp Axi Lite interface and IRQ
- signal InterruptxS : std_ulogic := '0';
- signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RdValidxS : std_ulogic := '0';
- signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WrValidxS : std_ulogic := '0';
- -- Zynq Reg Bank
- -- type t_status_send_word is (E_IDLE, E_SEND);
-
- -- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- --
- -- signal NorthNativeSlavexD : t_native_fifo_slave;
- -- signal NorthNativeMasterxD : t_native_fifo_master;
- -- signal EastNativeSlavexD : t_native_fifo_slave;
- -- signal EastNativeMasterxD : t_native_fifo_master;
- -- signal SouthNativeSlavexD : t_native_fifo_slave;
- -- signal SouthNativeMasterxD : t_native_fifo_master;
- -- signal WestNativeSlavexD : t_native_fifo_slave;
- -- signal WestNativeMasterxD : t_native_fifo_master;
- --
- -- signal InterruptRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal InterruptRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- North
- -- signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- East
- -- signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- South
- -- signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- West
- -- signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- Debug
- -- signal CntRstxR : std_ulogic := '0';
- signal ClkEnxS : std_ulogic := '0';
- signal NorthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal NorthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- signal EastDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal EastDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- signal SouthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal SouthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- signal WestDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal WestDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- --
- signal DebugCounterResetxR : t_if_common_reset := C_NO_IF_COMMON_RESET;
- signal DebugRXFifoResetxR : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
- signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-
- -- Attributes
- attribute mark_debug : string;
- attribute keep : string;
- -- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
- -- North
- attribute mark_debug of NorthRXM2SxD : signal is "true";
- attribute keep of NorthRXM2SxD : signal is "true";
- attribute mark_debug of NorthRXS2MxD : signal is "true";
- attribute keep of NorthRXS2MxD : signal is "true";
- -- East
- -- attribute keep of EastRXM2SxD : signal is "true";
- -- attribute keep of EastRXM2SxD : signal is "true";
- -- attribute keep of EastRXS2MxD : signal is "true";
- -- attribute keep of EastRXS2MxD : signal is "true";
- -- South
- attribute mark_debug of SouthRXM2SxD : signal is "true";
- attribute keep of SouthRXM2SxD : signal is "true";
- attribute mark_debug of SouthRXS2MxD : signal is "true";
- attribute keep of SouthRXS2MxD : signal is "true";
- -- West
- -- attribute keep of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXS2MxD : signal is "true";
- -- attribute keep of WestRXS2MxD : signal is "true";
-
-begin
-
- ProcessingSystemxB : block is
- begin -- block ProcessingSystemxB
-
- ZynqxI : entity work.scalp_zynqps_wrapper
- port map (
- -- Processor interface
- FIXED_IO_ps_clk => PSClkxCIO,
- FIXED_IO_ps_porb => PSPorxSNIO,
- FIXED_IO_ps_srstb => PSSRstxRNIO,
- FclkClk0xCO => PSSysClkxC,
- FclkReset0xRO => PSSysResetxR,
- -- DDR interface
- DDR_addr => DDRAddrxDIO,
- DDR_ba => DDRBankAddrxDIO,
- DDR_cas_n => DDRCasNxSIO,
- DDR_ck_n => DDRClkNxCIO,
- DDR_ck_p => DDRClkPxCIO,
- DDR_cke => DDRCkexSIO,
- DDR_cs_n => DDRCsNxSIO,
- DDR_dm => DDRDmxDIO,
- DDR_dq => DDRDqxDIO,
- DDR_dqs_n => DDRDqsNxDIO,
- DDR_dqs_p => DDRDqsPxDIO,
- DDR_odt => DDROdtxSIO,
- DDR_ras_n => DDRRasNxSIO,
- DDR_reset_n => DDRDRstxRNIO,
- DDR_we_n => DDRWexSNIO,
- FIXED_IO_ddr_vrn => DDRVrNxSIO,
- FIXED_IO_ddr_vrp => DDRVrPxSIO,
- -- USB interface
- Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
- -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
- -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
- Spi1MOSIxSO => Pll2V5DatauWirexSO,
- Spi1SSxSO => Pll2V5LEuWirexSO,
- Spi1SclkxCO => Pll2V5ClkuWirexCO,
- -- MIO
- FIXED_IO_mio => MIOxDIO,
- -- Scalp Axi Lite interface and IRQ
- InterruptxSI => InterruptxS,
- RdAddrxDO => RdAddrxD,
- RdDataxDI => RdDataxD,
- RdValidxSO => RdValidxS,
- WrAddrxDO => WrAddrxD,
- WrDataxDO => WrDataxD,
- WrValidxSO => WrValidxS);
-
- end block ProcessingSystemxB;
-
- ProgrammableLogicxB : block is
- begin -- block ProgrammableLogicxB
-
- InputClocksxB : block is
- begin -- block InputClocksxB
-
- GTPRefClk0PxAS : GTRefClk0DiffxC.ClkPxC <= GTPRefClk0PxCI;
- GTPRefClk0NxAS : GTRefClk0DiffxC.ClkNxC <= GTPRefClk0NxCI;
- -- GTPRefClk1PxAS : GTRefClk0DiffxC.ClkPxC <= GTPRefClk1PxCI;
- -- GTPRefClk1NxAS : GTRefClk0DiffxC.ClkNxC <= GTPRefClk1NxCI;
-
- -- GTP Clocks buffers
- IBufDSGTPRefClk0xI : IBUFDS_GTE2
- port map (
- I => GTRefClk0DiffxC.ClkPxC,
- IB => GTRefClk0DiffxC.ClkNxC,
- CEB => '0',
- O => GTRefClk0xC.GTRefClkxC,
- ODIV2 => open);
-
- -- IBufDSGTPRefClk1xI : IBUFDS_GTE2
- -- port map (
- -- I => GTRefClk0DiffxC.ClkPxC,
- -- IB => GTRefClk0DiffxC.ClkNxC,
- -- CEB => '0',
- -- O => GTRefClk1xCGTRefClkxC,
- -- ODIV2 => open);
-
- end block InputClocksxB;
-
- PllClocksxB : block is
-
- constant C_AURORA_RST_DLY_TICKS : integer := 25;
- constant C_GT_RST_DLY_TICKS : integer := 625;
-
- signal PllLockedxS : std_ulogic := '0';
-
- begin -- block PllClocksxB
-
- ScalpAuroraPllxI : entity work.scalp_aurora_clk
- port map (
- -- Clock out ports
- InitClkxCO => AuroraClkSlavexC.InitClkxC,
- DrpClkxCO => AuroraClkSlavexC.DrpClkxC,
- -- Status and control signals
- reset => PSSysResetxR,
- PllLockedxSO => PllLockedxS,
- -- Clock in ports
- PSSysClkxCI => PSSysClkxC);
-
- AuroraRstDlyxI : entity work.reset_delay_gen
- generic map (
- C_TICKS => C_AURORA_RST_DLY_TICKS)
- port map (
- ClkxCI => AuroraClkSlavexC.InitClkxC,
- PllLockedxSI => PllLockedxS,
- ResetxRI => PSSysResetxR,
- ResetDelayedxRO => AuroraResetSlavexR.ResetxR);
-
- GTRstDlyxI : entity work.reset_delay_gen
- generic map (
- C_TICKS => C_GT_RST_DLY_TICKS)
- port map (
- ClkxCI => AuroraClkSlavexC.InitClkxC,
- PllLockedxSI => PllLockedxS,
- ResetxRI => PSSysResetxR,
- ResetDelayedxRO => AuroraResetSlavexR.GTResetxR);
-
- end block PllClocksxB;
-
- GTPhyxB : block is
-
- constant C_RX_FIFO_RST_DONE_DLY_TICKS : integer := 100;
-
- begin -- block GTPhyxB
-
- -- GTP
- GTPFromNorthPxAS : GTPFromNorthxD.RXPxD(0) <= GTPFromNorthPxSI;
- GTPFromNorthNxAS : GTPFromNorthxD.RXNxD(0) <= GTPFromNorthNxSI;
- GTPToNorthPxAS : GTPToNorthPxSO <= GTPToNorthxD.TXPxD(0);
- GTPToNorthNxAS : GTPToNorthNxSO <= GTPToNorthxD.TXNxD(0);
- GTPFromEastPxAS : GTPFromEastxD.RXPxD(0) <= GTPFromEastPxSI;
- GTPFromEastNxAS : GTPFromEastxD.RXNxD(0) <= GTPFromEastNxSI;
- GTPToEastPxAS : GTPToEastPxSO <= GTPToEastxD.TXPxD(0);
- GTPToEastNxAS : GTPToEastNxSO <= GTPToEastxD.TXNxD(0);
- GTPFromSouthPxAS : GTPFromSouthxD.RXPxD(0) <= GTPFromSouthPxSI;
- GTPFromSouthNxAS : GTPFromSouthxD.RXNxD(0) <= GTPFromSouthNxSI;
- GTPToSouthPxAS : GTPToSouthPxSO <= GTPToSouthxD.TXPxD(0);
- GTPToSouthNxAS : GTPToSouthNxSO <= GTPToSouthxD.TXNxD(0);
- GTPFromWestPxAS : GTPFromWestxD.RXPxD(0) <= GTPFromWestPxSI;
- GTPFromWestNxAS : GTPFromWestxD.RXNxD(0) <= GTPFromWestNxSI;
- GTPToWestPxAS : GTPToWestPxSO <= GTPToWestxD.TXPxD(0);
- GTPToWestNxAS : GTPToWestNxSO <= GTPToWestxD.TXNxD(0);
-
- CtrlxB : block is
- begin -- block CtrlxB
-
- PowerDownxAS : AuroraCtrlxD.PowerDownxS <= '0';
- LoopbackxAS : AuroraCtrlxD.LoopbackxD <= (others => '0');
-
- end block CtrlxB;
-
- ScalpAuroraPhyxI : entity work.scalp_aurora_phy
- generic map (
- C_DEBUG_MODE => C_DEBUG_MODE,
- C_RX_FIFO_MODE => C_RX_FIFO_MODE,
- C_RX_FIFO_RST_DONE_DLY_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
- port map (
- -- Clocks
- -- GTP Ref Clocks
- GTRefClkxCI => GTRefClk0xC,
- -- Aurora System and GTP Clocks
- AuroraClkxCI => AuroraClkSlavexC,
- AuroraClkxCO => AuroraClkMasterxC,
- -- Reset
- -- Aurora Reset
- AuroraResetxRI => AuroraResetSlavexR,
- AuroraResetxRO => AuroraResetMasterLinkxR,
- -- RX Fifo and Back Pressure Reset
- RXResetxRI => RXResetxR,
- RXFifoResetDonexDO => RXFifoResetDonexD,
- RXFifoResetDoneDelayedxDO => RXFifoResetDoneDelayedxD,
- -- Back Pressure Reset
- -- GTP Serial IO
- -- North
- GTPFromNorthxDI => GTPFromNorthxD,
- GTPToNorthxDO => GTPToNorthxD,
- -- East
- GTPFromEastxDI => GTPFromEastxD,
- GTPToEastxDO => GTPToEastxD,
- -- South
- GTPFromSouthxDI => GTPFromSouthxD,
- GTPToSouthxDO => GTPToSouthxD,
- -- West
- GTPFromWestxDI => GTPFromWestxD,
- GTPToWestxDO => GTPToWestxD,
- -- Axi4 Framing Interface
- -- North
- NorthRXM2SxDO => NorthRXM2SxD,
- NorthRXS2MxDI => NorthRXS2MxD,
- NorthTXM2SxDI => NorthTXM2SxD,
- NorthTXS2MxDO => NorthTXS2MxD,
- -- East
- EastRXM2SxDO => EastRXM2SxD,
- EastRXS2MxDI => EastRXS2MxD,
- EastTXM2SxDI => EastTXM2SxD,
- EastTXS2MxDO => EastTXS2MxD,
- -- South
- SouthRXM2SxDO => SouthRXM2SxD,
- SouthRXS2MxDI => SouthRXS2MxD,
- SouthTXM2SxDI => SouthTXM2SxD,
- SouthTXS2MxDO => SouthTXS2MxD,
- -- West
- WestRXM2SxDO => WestRXM2SxD,
- WestRXS2MxDI => WestRXS2MxD,
- WestTXM2SxDI => WestTXM2SxD,
- WestTXS2MxDO => WestTXS2MxD,
- -- Axi4 Framing UFC Interface
- -- North
- NorthRXUFCM2SxDO => NorthRXUFCM2SxD,
- NorthTXUFCM2SxDI => NorthTXUFCM2SxD,
- NorthTXUFCS2MxDO => NorthTXUFCS2MxD,
- -- East
- EastRXUFCM2SxDO => EastRXUFCM2SxD,
- EastTXUFCM2SxDI => EastTXUFCM2SxD,
- EastTXUFCS2MxDO => EastTXUFCS2MxD,
- -- South
- SouthRXUFCM2SxDO => SouthRXUFCM2SxD,
- SouthTXUFCM2SxDI => SouthTXUFCM2SxD,
- SouthTXUFCS2MxDO => SouthTXUFCS2MxD,
- -- West
- WestRXUFCM2SxDO => WestRXUFCM2SxD,
- WestTXUFCM2SxDI => WestTXUFCM2SxD,
- WestTXUFCS2MxDO => WestTXUFCS2MxD,
- -- Axi4 Framing NFC Interface
- -- The NFC interface is not available when the
- -- constant C_RX_FIFO_MODE is set to TRUE.
- -- North
- NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
- NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
- NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
- -- East
- EastRXNFCM2SxDO => EastRXNFCM2SxD,
- EastTXNFCM2SxDI => EastTXNFCM2SxD,
- EastTXNFCS2MxDO => EastTXNFCS2MxD,
- -- South
- SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
- SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
- SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
- -- West
- WestRXNFCM2SxDO => WestRXNFCM2SxD,
- WestTXNFCM2SxDI => WestTXNFCM2SxD,
- WestTXNFCS2MxDO => WestTXNFCS2MxD,
- -- Aurora Ctrl + Status
- AuroraCtrlxDI => AuroraCtrlxD,
- AuroraStatusxDO => AuroraStatusxD,
- -- DRP Port
- AuroraDRPM2SxDI => AuroraDRPM2SxD,
- AuroraDRPS2MxDO => AuroraDRPS2MxD,
- -- RX Fifo Status
- -- North
- NorthRXFifoStatusxDO => NorthRXFifoStatusxD,
- -- East
- EastRXFifoStatusxDO => EastRXFifoStatusxD,
- -- South
- SouthRXFifoStatusxDO => SouthRXFifoStatusxD,
- -- West
- WestRXFifoStatusxDO => WestRXFifoStatusxD,
- -- Axis Fifo Error
- AxisFifoErrorxDO => AxisFifoErrorxD);
-
- end block GTPhyxB;
-
- -- ZynqRegBankxB : block is
- -- begin -- block ZynqRegBankxB
-
-
- -- RegBankxB : block is
- -- begin -- block RegBankxB
-
- -- WriteRegPortxP : process (EastCtrlRegPortxDP,
- -- EastWrDataRegPortxDP,
- -- NorthCtrlRegPortxDP,
- -- NorthWrDataRegPortxDP,
- -- SouthCtrlRegPortxDP,
- -- SouthWrDataRegPortxDP,
- -- WestCtrlRegPortxDP,
- -- WestWrDataRegPortxDP, WrAddrxD,
- -- WrDataxD, WrValidxS) is
- -- begin -- process WriteRegPortxP
- -- -- North
- -- NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP;
- -- NorthWrDataRegPortxDN <= NorthWrDataRegPortxDP;
- -- -- East
- -- EastCtrlRegPortxDN <= EastCtrlRegPortxDP;
- -- EastWrDataRegPortxDN <= EastWrDataRegPortxDP;
- -- -- South
- -- SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP;
- -- SouthWrDataRegPortxDN <= SouthWrDataRegPortxDP;
- -- -- West
- -- WestCtrlRegPortxDN <= WestCtrlRegPortxDP;
- -- WestWrDataRegPortxDN <= WestWrDataRegPortxDP;
-
- -- if WrValidxS = '1' then
- -- case WrAddrxD is
- -- -- Ctrl
- -- -- North
- -- when x"000" => NorthCtrlRegPortxDN <= WrDataxD;
- -- when x"004" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP or WrDataxD;
- -- when x"008" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP and not WrDataxD;
- -- -- East
- -- when x"00c" => EastCtrlRegPortxDN <= WrDataxD;
- -- when x"010" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP or WrDataxD;
- -- when x"014" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP and not WrDataxD;
- -- -- South
- -- when x"018" => SouthCtrlRegPortxDN <= WrDataxD;
- -- when x"01c" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP or WrDataxD;
- -- when x"020" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP and not WrDataxD;
- -- -- East
- -- when x"024" => WestCtrlRegPortxDN <= WrDataxD;
- -- when x"028" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP or WrDataxD;
- -- when x"02c" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP and not WrDataxD;
- -- -- Data
- -- -- North
- -- when x"030" => NorthWrDataRegPortxDN <= WrDataxD;
- -- -- East
- -- when x"034" => EastWrDataRegPortxDN <= WrDataxD;
- -- -- South
- -- when x"038" => SouthWrDataRegPortxDN <= WrDataxD;
- -- -- West
- -- when x"03c" => WestWrDataRegPortxDN <= WrDataxD;
- -- when others => null;
- -- end case;
- -- end if;
- -- end process WriteRegPortxP;
-
- -- ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
- -- begin -- process ReadRegPortxP
- -- if PSSysResetxR = '1' then
- -- RdDataxD <= (others => '0');
- -- elsif rising_edge(PSSysClkxC) then
- -- RdDataxD <= (others => '0');
-
- -- if RdValidxS = '1' then
- -- case RdAddrxD is
- -- when x"000" => RdDataxD <= NorthCtrlRegPortxDP;
- -- when x"00C" => RdDataxD <= EastCtrlRegPortxDP;
- -- when x"018" => RdDataxD <= SouthCtrlRegPortxDP;
- -- when x"024" => RdDataxD <= WestCtrlRegPortxDP;
- -- when x"030" => RdDataxD <= NorthWrDataRegPortxDP;
- -- when x"034" => RdDataxD <= EastWrDataRegPortxDP;
- -- when x"038" => RdDataxD <= SouthWrDataRegPortxDP;
- -- when x"03c" => RdDataxD <= WestWrDataRegPortxDP;
- -- when x"040" => RdDataxD <= NorthStatusRegPortxDP;
- -- when x"044" => RdDataxD <= EastStatusRegPortxDP;
- -- when x"048" => RdDataxD <= SouthStatusRegPortxDP;
- -- when x"04c" => RdDataxD <= WestStatusRegPortxDP;
- -- when others => RdDataxD <= (others => '0');
- -- end case;
- -- end if;
- -- end if;
- -- end process ReadRegPortxP;
-
- -- RegBankxP : process (PSSysClkxC, PSSysResetxR) is
- -- begin -- process RegBankxP
- -- if PSSysResetxR = '1' then
- -- -- North
- -- NorthStatusRegPortxDP <= (others => '0');
- -- NorthCtrlRegPortxDP <= (others => '0');
- -- NorthWrDataRegPortxDP <= (others => '0');
- -- -- East
- -- EastStatusRegPortxDP <= (others => '0');
- -- EastCtrlRegPortxDP <= (others => '0');
- -- EastWrDataRegPortxDP <= (others => '0');
- -- -- South
- -- SouthStatusRegPortxDP <= (others => '0');
- -- SouthCtrlRegPortxDP <= (others => '0');
- -- SouthWrDataRegPortxDP <= (others => '0');
- -- -- West
- -- WestStatusRegPortxDP <= (others => '0');
- -- WestCtrlRegPortxDP <= (others => '0');
- -- WestWrDataRegPortxDP <= (others => '0');
- -- elsif rising_edge(PSSysClkxC) then
- -- -- North
- -- NorthStatusRegPortxDP <= NorthStatusRegPortxDN;
- -- NorthCtrlRegPortxDP <= NorthCtrlRegPortxDN;
- -- NorthWrDataRegPortxDP <= NorthWrDataRegPortxDN;
- -- -- East
- -- EastStatusRegPortxDP <= EastStatusRegPortxDN;
- -- EastCtrlRegPortxDP <= EastCtrlRegPortxDN;
- -- EastWrDataRegPortxDP <= EastWrDataRegPortxDN;
- -- -- South
- -- SouthStatusRegPortxDP <= SouthStatusRegPortxDN;
- -- SouthCtrlRegPortxDP <= SouthCtrlRegPortxDN;
- -- SouthWrDataRegPortxDP <= SouthWrDataRegPortxDN;
- -- -- West
- -- WestStatusRegPortxDP <= WestStatusRegPortxDN;
- -- WestCtrlRegPortxDP <= WestCtrlRegPortxDN;
- -- WestWrDataRegPortxDP <= WestWrDataRegPortxDN;
- -- end if;
- -- end process RegBankxP;
-
- -- end block RegBankxB;
-
- -- TxFifoxB : block is
- -- begin -- block TxFifoxB
-
- -- NorthWrDataxAS : NorthNativeSlavexD.DataxD <= NorthWrDataRegPortxDP;
- -- EastWrDataxAS : EastNativeSlavexD.DataxD <= EastWrDataRegPortxDP;
- -- SouthWrDataxAS : SouthNativeSlavexD.DataxD <= SouthWrDataRegPortxDN;
- -- WestWrDataRegxAS : WestNativeSlavexD.DataxD <= WestWrDataRegPortxDN;
- -- NorthWrEnxAS : NorthNativeSlavexD.WrEnxS <= NorthCtrlRegPortxDP(0);
- -- EastWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
- -- SouthWrEnxAS : SouthNativeSlavexD.WrEnxS <= SouthCtrlRegPortxDP(0);
- -- WestWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
- -- NorthStatusRegPortxAS : NorthStatusRegPortxDN <= (0 => NorthNativeMasterxD.FullxS,
- -- 1 => NorthNativeMasterxD.EmptyxS,
- -- 2 => NorthNativeMasterxD.AlmostFullxS,
- -- 3 => NorthNativeMasterxD.AlmostEmptyxS,
- -- 4 => NorthNativeMasterxD.WrRstBusyxS,
- -- 5 => NorthNativeMasterxD.RdRstBusyxS,
- -- others => '0');
- -- EastStatusRegPortxAS : EastStatusRegPortxDN <= (0 => EastNativeMasterxD.FullxS,
- -- 1 => EastNativeMasterxD.EmptyxS,
- -- 2 => EastNativeMasterxD.AlmostFullxS,
- -- 3 => EastNativeMasterxD.AlmostEmptyxS,
- -- 4 => EastNativeMasterxD.WrRstBusyxS,
- -- 5 => EastNativeMasterxD.RdRstBusyxS,
- -- others => '0');
- -- SouthStatusRegPortxAS : SouthStatusRegPortxDN <= (0 => SouthNativeMasterxD.FullxS,
- -- 1 => SouthNativeMasterxD.EmptyxS,
- -- 2 => SouthNativeMasterxD.AlmostFullxS,
- -- 3 => SouthNativeMasterxD.AlmostEmptyxS,
- -- 4 => SouthNativeMasterxD.WrRstBusyxS,
- -- 5 => SouthNativeMasterxD.RdRstBusyxS,
- -- others => '0');
- -- WestStatusRegPortxAS : WestStatusRegPortxDN <= (0 => WestNativeMasterxD.FullxS,
- -- 1 => WestNativeMasterxD.EmptyxS,
- -- 2 => WestNativeMasterxD.AlmostFullxS,
- -- 3 => WestNativeMasterxD.AlmostEmptyxS,
- -- 4 => WestNativeMasterxD.WrRstBusyxS,
- -- 5 => WestNativeMasterxD.RdRstBusyxS,
- -- others => '0');
-
- -- UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
- -- AuroraClkMasterxC.UserClkxC) is
- -- begin -- process UpdateRegxP
- -- if not AuroraClkMasterxC.PllNotLockedxS then
- -- NorthStatusSendWordxDP <= E_IDLE;
- -- EastStatusSendWordxDP <= E_IDLE;
- -- SouthStatusSendWordxDP <= E_IDLE;
- -- WestStatusSendWordxDP <= E_IDLE;
- -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- -- NorthStatusSendWordxDP <= NorthStatusSendWordxDN;
- -- EastStatusSendWordxDP <= EastStatusSendWordxDN;
- -- SouthStatusSendWordxDP <= SouthStatusSendWordxDN;
- -- WestStatusSendWordxDP <= WestStatusSendWordxDN;
- -- end if;
- -- end process UpdateRegxP;
-
- -- NorthSendWordxP : process (NorthNativeMasterxD.DataxD,
- -- NorthNativeMasterxD.EmptyxS,
- -- NorthStatusSendWordxDP,
- -- NorthTXS2MxD.ReadyxS) is
- -- begin -- process NorthSendWordxP
- -- NorthTXM2SxD.DataxD <= (others => '0');
- -- NorthTXM2SxD.KeepxD <= (others => '1');
- -- NorthTXM2SxD.LastxS <= '0';
- -- NorthTXM2SxD.ValidxS <= '0';
- -- NorthNativeSlavexD.RdEnxS <= '0';
- -- NorthStatusSendWordxDN <= NorthStatusSendWordxDP;
-
- -- case NorthStatusSendWordxDP is
- -- when E_IDLE =>
-
- -- if (NorthNativeMasterxD.EmptyxS = '0') and
- -- (NorthTXS2MxD.ReadyxS = '1') then
- -- NorthTXM2SxD.DataxD <= NorthNativeMasterxD.DataxD;
- -- NorthTXM2SxD.LastxS <= '1';
- -- NorthTXM2SxD.ValidxS <= '1';
- -- NorthNativeSlavexD.RdEnxS <= '1';
- -- NorthStatusSendWordxDN <= E_SEND;
- -- end if;
-
- -- when E_SEND =>
- -- NorthStatusSendWordxDN <= E_IDLE;
-
- -- when others => null;
- -- end case;
- -- end process NorthSendWordxP;
-
- -- EastSendWordxP : process (EastNativeMasterxD.DataxD,
- -- EastNativeMasterxD.EmptyxS,
- -- EastStatusSendWordxDP,
- -- EastTXS2MxD.ReadyxS) is
- -- begin -- process EastSendWordxP
- -- EastTXM2SxD.DataxD <= (others => '0');
- -- EastTXM2SxD.KeepxD <= (others => '1');
- -- EastTXM2SxD.LastxS <= '0';
- -- EastTXM2SxD.ValidxS <= '0';
- -- EastNativeSlavexD.RdEnxS <= '0';
- -- EastStatusSendWordxDN <= EastStatusSendWordxDP;
-
- -- case EastStatusSendWordxDP is
- -- when E_IDLE =>
-
- -- if (EastNativeMasterxD.EmptyxS = '0') and
- -- (EastTXS2MxD.ReadyxS = '1') then
- -- EastTXM2SxD.DataxD <= EastNativeMasterxD.DataxD;
- -- EastTXM2SxD.LastxS <= '1';
- -- EastTXM2SxD.ValidxS <= '1';
- -- EastNativeSlavexD.RdEnxS <= '1';
- -- EastStatusSendWordxDN <= E_SEND;
- -- end if;
-
- -- when E_SEND =>
- -- EastStatusSendWordxDN <= E_IDLE;
-
- -- when others => null;
- -- end case;
- -- end process EastSendWordxP;
-
- -- SouthSendWordxP : process (SouthNativeMasterxD.DataxD,
- -- SouthNativeMasterxD.EmptyxS,
- -- SouthStatusSendWordxDP,
- -- SouthTXS2MxD.ReadyxS) is
- -- begin -- process SouthSendWordxP
- -- SouthTXM2SxD.DataxD <= (others => '0');
- -- SouthTXM2SxD.KeepxD <= (others => '1');
- -- SouthTXM2SxD.LastxS <= '0';
- -- SouthTXM2SxD.ValidxS <= '0';
- -- SouthNativeSlavexD.RdEnxS <= '0';
- -- SouthStatusSendWordxDN <= SouthStatusSendWordxDP;
-
- -- case SouthStatusSendWordxDP is
- -- when E_IDLE =>
-
- -- if (SouthNativeMasterxD.EmptyxS = '0') and
- -- (SouthTXS2MxD.ReadyxS = '1') then
- -- SouthTXM2SxD.DataxD <= SouthNativeMasterxD.DataxD;
- -- SouthTXM2SxD.LastxS <= '1';
- -- SouthTXM2SxD.ValidxS <= '1';
- -- SouthNativeSlavexD.RdEnxS <= '1';
- -- SouthStatusSendWordxDN <= E_SEND;
- -- end if;
-
- -- when E_SEND =>
- -- SouthStatusSendWordxDN <= E_IDLE;
-
- -- when others => null;
- -- end case;
- -- end process SouthSendWordxP;
-
- -- WestSendWordxP : process (WestNativeMasterxD.DataxD,
- -- WestNativeMasterxD.EmptyxS,
- -- WestStatusSendWordxDP,
- -- WestTXS2MxD.ReadyxS) is
- -- begin -- process WestSendWordxP
- -- WestTXM2SxD.DataxD <= (others => '0');
- -- WestTXM2SxD.KeepxD <= (others => '1');
- -- WestTXM2SxD.LastxS <= '0';
- -- WestTXM2SxD.ValidxS <= '0';
- -- WestNativeSlavexD.RdEnxS <= '0';
- -- WestStatusSendWordxDN <= WestStatusSendWordxDP;
-
- -- case WestStatusSendWordxDP is
- -- when E_IDLE =>
-
- -- if (WestNativeMasterxD.EmptyxS = '0') and
- -- (WestTXS2MxD.ReadyxS = '1') then
- -- WestTXM2SxD.DataxD <= WestNativeMasterxD.DataxD;
- -- WestTXM2SxD.LastxS <= '1';
- -- WestTXM2SxD.ValidxS <= '1';
- -- WestNativeSlavexD.RdEnxS <= '1';
- -- WestStatusSendWordxDN <= E_SEND;
- -- end if;
-
- -- when E_SEND =>
- -- WestStatusSendWordxDN <= E_IDLE;
-
- -- when others => null;
- -- end case;
- -- end process WestSendWordxP;
-
- -- NorthFifoxI : entity work.scalp_packet_fifo_wrapper
- -- port map (
- -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- -- WrClkxCI => PSSysClkxC,
- -- ResetxRI => PSSysResetxR,
- -- NativeSlavexDI => NorthNativeSlavexD,
- -- NativeMasterxDO => NorthNativeMasterxD);
-
- -- EastFifoxI : entity work.scalp_packet_fifo_wrapper
- -- port map (
- -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- -- WrClkxCI => PSSysClkxC,
- -- ResetxRI => PSSysResetxR,
- -- NativeSlavexDI => EastNativeSlavexD,
- -- NativeMasterxDO => EastNativeMasterxD);
-
- -- SouthFifoxI : entity work.scalp_packet_fifo_wrapper
- -- port map (
- -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- -- WrClkxCI => PSSysClkxC,
- -- ResetxRI => PSSysResetxR,
- -- NativeSlavexDI => SouthNativeSlavexD,
- -- NativeMasterxDO => SouthNativeMasterxD);
-
- -- WestFifoxI : entity work.scalp_packet_fifo_wrapper
- -- port map (
- -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- -- WrClkxCI => PSSysClkxC,
- -- ResetxRI => PSSysResetxR,
- -- NativeSlavexDI => WestNativeSlavexD,
- -- NativeMasterxDO => WestNativeMasterxD);
-
- -- end block TxFifoxB;
-
- -- end block ZynqRegBankxB;
-
- DebugxB : block is
-
- -- RX Fifo reset 196 cycles
- constant C_RX_FIFO_RST_DLY_TICKS : integer := 200;
-
- type t_read_phy_states is (E_READ_PHY_IDLE, E_READ_PHY_S0, E_READ_PHY_S1, E_READ_PHY_S2);
- type t_write_phy_states is (E_WRITE_PHY_IDLE, E_WRITE_PHY_W0, E_WRITE_PHY_W1,
- E_WRITE_PHY_W2, E_WRITE_PHY_W3, E_WRITE_PHY_W4,
- E_WRITE_PHY_W5, E_WRITE_PHY_W6, E_WRITE_PHY_W7);
-
- -- North
- signal NorthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
- signal NorthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
- signal NorthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
- signal NorthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
- -- East
- signal EastReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
- signal EastReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
- signal EastWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
- signal EastWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
- -- South
- signal SouthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
- signal SouthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
- signal SouthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
- signal SouthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
- -- West
- signal WestReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
- signal WestReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
- signal WestWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
- signal WestWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
-
- attribute mark_debug : string;
- attribute keep : string;
- --
- attribute mark_debug of NorthWritePhyStatexDP : signal is "true";
- attribute keep of NorthWritePhyStatexDP : signal is "true";
- -- attribute mark_debug of EastWritePhyStatexDP : signal is "true";
- -- attribute keep of EastWritePhyStatexDP : signal is "true";
- attribute mark_debug of SouthWritePhyStatexDP : signal is "true";
- attribute keep of SouthWritePhyStatexDP : signal is "true";
- -- attribute mark_debug of WestWritePhyStatexDP : signal is "true";
- -- attribute keep of WestWritePhyStatexDP : signal is "true";
- attribute mark_debug of NorthReadPhyStatexDP : signal is "true";
- attribute keep of NorthReadPhyStatexDP : signal is "true";
- -- attribute mark_debug of EastReadPhyStatexDP : signal is "true";
- -- attribute keep of EastReadPhyStatexDP : signal is "true";
- attribute mark_debug of SouthReadPhyStatexDP : signal is "true";
- attribute keep of SouthReadPhyStatexDP : signal is "true";
- -- attribute mark_debug of WestReadPhyStatexDP : signal is "true";
- -- attribute keep of WestReadPhyStatexDP : signal is "true";
-
- begin -- block DebugxB
-
- -- RX Fifo reset 196 cycles
- -- Clock and Resets
- -- RX Fifo
- NorthFifoResetxAS : RXResetxR.FifoResetxR.NorthxR <=
- '1' when
- (DebugRXFifoResetxR.NorthxR = '1') or
- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(0) = '0') else
- '0';
- EastFifoResetxAS : RXResetxR.FifoResetxR.EastxR <=
- '1' when
- (DebugRXFifoResetxR.EastxR = '1') or
- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(1) = '0') else
- '0';
- SouthFifoResetxAS : RXResetxR.FifoResetxR.SouthxR <=
- '1' when
- (DebugRXFifoResetxR.SouthxR = '1') or
- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(2) = '0') else
- '0';
- WestFifoResetxAS : RXResetxR.FifoResetxR.WestxR <=
- '1' when
- (DebugRXFifoResetxR.WestxR = '1') or
- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(3) = '0') else
- '0';
- -- Back pressure
- NorthBackPressureResetxAS : RXResetxR.BackPressureResetxR.NorthxR <=
- '1' when
- (DebugBackPressureResetxR.NorthxR = '1') or
- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
- (RXFifoResetDonexD.NorthxS = '0') or
- (RXFifoResetDoneDelayedxD.NorthxS = '0') or
- (AuroraStatusxD.ChannelUpxD(0) = '0') else
- '0';
- EastBackPressureResetxAS : RXResetxR.BackPressureResetxR.EastxR <=
- '1' when
- (DebugBackPressureResetxR.EastxR = '1') or
- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
- (RXFifoResetDonexD.EastxS = '0') or
- (RXFifoResetDoneDelayedxD.EastxS = '0') or
- (AuroraStatusxD.ChannelUpxD(1) = '0') else
- '0';
- SouthBackPressureResetxAS : RXResetxR.BackPressureResetxR.SouthxR <=
- '1' when
- (DebugBackPressureResetxR.SouthxR = '1') or
- (RXFifoResetDonexD.SouthxS = '0') or
- (RXFifoResetDoneDelayedxD.SouthxS = '0') or
- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(2) = '0') else
- '0';
- WestBackPressureResetxAS : RXResetxR.BackPressureResetxR.WestxR <=
- '1' when
- (DebugBackPressureResetxR.WestxR = '1') or
- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
- (RXFifoResetDonexD.WestxS = '0') or
- (RXFifoResetDoneDelayedxD.WestxS = '0') or
- (AuroraStatusxD.ChannelUpxD(3) = '0') else
- '0';
-
- NorthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
- AuroraStatusxD.ChannelUpxD(0),
- AuroraStatusxD.LaneUpxD(0)(0),
- DebugCounterResetxR.NorthxR,
- RXFifoResetDoneDelayedxD.NorthxS,
- RXFifoResetDonexD.NorthxS) is
- begin -- process NorthUpdateRegxP
- if (DebugCounterResetxR.NorthxR = '1') or
- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(0) = '0') or
- (RXFifoResetDonexD.NorthxS = '0') or
- (RXFifoResetDoneDelayedxD.NorthxS = '0') then
- NorthReadPhyStatexDP <= E_READ_PHY_IDLE;
- NorthWritePhyStatexDP <= E_WRITE_PHY_IDLE;
- NorthDataCounterxDP <= (others => '0');
- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- NorthReadPhyStatexDP <= NorthReadPhyStatexDN;
- NorthWritePhyStatexDP <= NorthWritePhyStatexDN;
- NorthDataCounterxDP <= NorthDataCounterxDN;
- end if;
- end process NorthUpdateRegxP;
-
- EastUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
- AuroraStatusxD.ChannelUpxD(1),
- AuroraStatusxD.LaneUpxD(1)(0),
- DebugCounterResetxR.EastxR,
- RXFifoResetDoneDelayedxD.EastxS,
- RXFifoResetDonexD.EastxS) is
- begin -- process EastUpdateRegxP
- if (DebugCounterResetxR.EastxR = '1') or
- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(1) = '0') or
- (RXFifoResetDonexD.EastxS = '0') or
- (RXFifoResetDoneDelayedxD.EastxS = '0') then
- EastReadPhyStatexDP <= E_READ_PHY_IDLE;
- EastWritePhyStatexDP <= E_WRITE_PHY_IDLE;
- EastDataCounterxDP <= (others => '0');
- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- EastReadPhyStatexDP <= EastReadPhyStatexDN;
- EastWritePhyStatexDP <= EastWritePhyStatexDN;
- EastDataCounterxDP <= EastDataCounterxDN;
- end if;
- end process EastUpdateRegxP;
-
- SouthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
- AuroraStatusxD.ChannelUpxD(2),
- AuroraStatusxD.LaneUpxD(2)(0),
- DebugCounterResetxR.SouthxR,
- RXFifoResetDoneDelayedxD.SouthxS,
- RXFifoResetDonexD.SouthxS) is
- begin -- process SouthUpdateRegxP
- if (DebugCounterResetxR.SouthxR = '1') or
- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(2) = '0') or
- (RXFifoResetDonexD.SouthxS = '0') or
- (RXFifoResetDoneDelayedxD.SouthxS = '0') then
- SouthReadPhyStatexDP <= E_READ_PHY_IDLE;
- SouthWritePhyStatexDP <= E_WRITE_PHY_IDLE;
- SouthDataCounterxDP <= (others => '0');
- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- SouthReadPhyStatexDP <= SouthReadPhyStatexDN;
- SouthWritePhyStatexDP <= SouthWritePhyStatexDN;
- SouthDataCounterxDP <= SouthDataCounterxDN;
- end if;
- end process SouthUpdateRegxP;
-
- WestUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
- AuroraStatusxD.ChannelUpxD(3),
- AuroraStatusxD.LaneUpxD(3)(0),
- DebugCounterResetxR.WestxR,
- RXFifoResetDoneDelayedxD.WestxS,
- RXFifoResetDonexD.WestxS) is
- begin -- process WestUpdateRegxP
- if (DebugCounterResetxR.WestxR = '1') or
- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
- (AuroraStatusxD.ChannelUpxD(3) = '0') or
- (RXFifoResetDonexD.WestxS = '0') or
- (RXFifoResetDoneDelayedxD.WestxS = '0') then
- WestReadPhyStatexDP <= E_READ_PHY_IDLE;
- WestWritePhyStatexDP <= E_WRITE_PHY_IDLE;
- WestDataCounterxDP <= (others => '0');
- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- WestReadPhyStatexDP <= WestReadPhyStatexDN;
- WestWritePhyStatexDP <= WestWritePhyStatexDN;
- WestDataCounterxDP <= WestDataCounterxDN;
- end if;
- end process WestUpdateRegxP;
-
- VioUserResetsxI : entity work.vio_user_resets
- port map (
- clk => AuroraClkMasterxC.UserClkxC,
- probe_out0(0) => DebugCounterResetxR.NorthxR,
- probe_out1(0) => DebugCounterResetxR.EastxR,
- probe_out2(0) => DebugCounterResetxR.SouthxR,
- probe_out3(0) => DebugCounterResetxR.WestxR,
- probe_out4(0) => DebugBackPressureResetxR.NorthxR,
- probe_out5(0) => DebugBackPressureResetxR.EastxR,
- probe_out6(0) => DebugBackPressureResetxR.SouthxR,
- probe_out7(0) => DebugBackPressureResetxR.WestxR,
- probe_out8(0) => DebugRXFifoResetxR.NorthxR,
- probe_out9(0) => DebugRXFifoResetxR.EastxR,
- probe_out10(0) => DebugRXFifoResetxR.SouthxR,
- probe_out11(0) => DebugRXFifoResetxR.WestxR);
-
- VioStatusxI : entity work.vio_status
- port map (
- clk => AuroraClkMasterxC.UserClkxC,
- -- North
- probe_in0(0) => AuroraStatusxD.HardErrxD(0),
- probe_in1(0) => AuroraStatusxD.SoftErrxD(0),
- probe_in2(0) => AuroraStatusxD.FrameErrxD(0),
- probe_in3 => AuroraStatusxD.LaneUpxD(0),
- probe_in4(0) => AuroraStatusxD.ChannelUpxD(0),
- probe_in5(0) => AuroraStatusxD.RXResetDoneOutxD(0),
- probe_in6(0) => AuroraStatusxD.TXResetDoneOutxD(0),
- -- East
- probe_in7(0) => AuroraStatusxD.HardErrxD(1),
- probe_in8(0) => AuroraStatusxD.SoftErrxD(1),
- probe_in9(0) => AuroraStatusxD.FrameErrxD(1),
- probe_in10 => AuroraStatusxD.LaneUpxD(1),
- probe_in11(0) => AuroraStatusxD.ChannelUpxD(1),
- probe_in12(0) => AuroraStatusxD.RXResetDoneOutxD(1),
- probe_in13(0) => AuroraStatusxD.TXResetDoneOutxD(1),
- -- South
- probe_in14(0) => AuroraStatusxD.HardErrxD(2),
- probe_in15(0) => AuroraStatusxD.SoftErrxD(2),
- probe_in16(0) => AuroraStatusxD.FrameErrxD(2),
- probe_in17 => AuroraStatusxD.LaneUpxD(2),
- probe_in18(0) => AuroraStatusxD.ChannelUpxD(2),
- probe_in19(0) => AuroraStatusxD.RXResetDoneOutxD(2),
- probe_in20(0) => AuroraStatusxD.TXResetDoneOutxD(2),
- -- West
- probe_in21(0) => AuroraStatusxD.HardErrxD(3),
- probe_in22(0) => AuroraStatusxD.SoftErrxD(3),
- probe_in23(0) => AuroraStatusxD.FrameErrxD(3),
- probe_in24 => AuroraStatusxD.LaneUpxD(3),
- probe_in25(0) => AuroraStatusxD.ChannelUpxD(3),
- probe_in26(0) => AuroraStatusxD.RXResetDoneOutxD(3),
- probe_in27(0) => AuroraStatusxD.TXResetDoneOutxD(3));
-
- NorthWriteTXPhyxP : process (NorthDataCounterxDP,
- NorthTXS2MxD.ReadyxS,
- NorthWritePhyStatexDP) is
- begin -- process NorthWriteTXPhyxP
- -- Default values
- NorthWritePhyStatexDN <= NorthWritePhyStatexDP;
- NorthDataCounterxDN <= NorthDataCounterxDP;
- NorthTXM2SxD.DataxD <= (others => '0');
- NorthTXM2SxD.KeepxD <= (others => '1');
- NorthTXM2SxD.ValidxS <= '0';
- NorthTXM2SxD.LastxS <= '0';
-
- case NorthWritePhyStatexDP is
- when E_WRITE_PHY_IDLE =>
- NorthWritePhyStatexDN <= E_WRITE_PHY_W0;
-
- when E_WRITE_PHY_W0 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W1;
- end if;
-
- when E_WRITE_PHY_W1 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W2;
- end if;
-
- when E_WRITE_PHY_W2 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W3;
- end if;
-
- when E_WRITE_PHY_W3 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W4;
- end if;
-
- when E_WRITE_PHY_W4 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W5;
- end if;
-
- when E_WRITE_PHY_W5 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W6;
- end if;
- when E_WRITE_PHY_W6 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W7;
- end if;
-
- when E_WRITE_PHY_W7 =>
- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
- NorthTXM2SxD.ValidxS <= '1';
- NorthTXM2SxD.LastxS <= '1';
-
- if NorthTXS2MxD.ReadyxS = '1' then
- NorthWritePhyStatexDN <= E_WRITE_PHY_W0;
- NorthDataCounterxDN <= NorthDataCounterxDP + 1;
- end if;
-
- when others => null;
- end case;
-
- end process NorthWriteTXPhyxP;
-
- EastWriteTXPhyxP : process (EastDataCounterxDP,
- EastTXS2MxD.ReadyxS,
- EastWritePhyStatexDP) is
- begin -- process EastWriteTXPhyxP
- -- Default values
- EastWritePhyStatexDN <= EastWritePhyStatexDP;
- EastDataCounterxDN <= EastDataCounterxDP;
- EastTXM2SxD.DataxD <= (others => '0');
- EastTXM2SxD.KeepxD <= (others => '1');
- EastTXM2SxD.ValidxS <= '0';
- EastTXM2SxD.LastxS <= '0';
-
- case EastWritePhyStatexDP is
- when E_WRITE_PHY_IDLE =>
- EastWritePhyStatexDN <= E_WRITE_PHY_W0;
-
- when E_WRITE_PHY_W0 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W1;
- end if;
-
- when E_WRITE_PHY_W1 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W2;
- end if;
-
- when E_WRITE_PHY_W2 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W3;
- end if;
-
- when E_WRITE_PHY_W3 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W4;
- end if;
-
- when E_WRITE_PHY_W4 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W5;
- end if;
-
- when E_WRITE_PHY_W5 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W6;
- end if;
-
- when E_WRITE_PHY_W6 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W7;
- end if;
-
- when E_WRITE_PHY_W7 =>
- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
- EastTXM2SxD.ValidxS <= '1';
- EastTXM2SxD.LastxS <= '1';
-
- if EastTXS2MxD.ReadyxS = '1' then
- EastWritePhyStatexDN <= E_WRITE_PHY_W0;
- EastDataCounterxDN <= EastDataCounterxDP + 1;
- end if;
-
- when others => null;
- end case;
-
- end process EastWriteTXPhyxP;
-
- SouthWriteTXPhyxP : process (SouthDataCounterxDP,
- SouthTXS2MxD.ReadyxS,
- SouthWritePhyStatexDP) is
- begin -- process SouthWriteTXPhyxP
- -- Default values
- SouthWritePhyStatexDN <= SouthWritePhyStatexDP;
- SouthDataCounterxDN <= SouthDataCounterxDP;
- SouthTXM2SxD.DataxD <= (others => '0');
- SouthTXM2SxD.KeepxD <= (others => '1');
- SouthTXM2SxD.ValidxS <= '0';
- SouthTXM2SxD.LastxS <= '0';
-
- case SouthWritePhyStatexDP is
- when E_WRITE_PHY_IDLE =>
- SouthWritePhyStatexDN <= E_WRITE_PHY_W0;
-
- when E_WRITE_PHY_W0 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W1;
- end if;
-
- when E_WRITE_PHY_W1 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W2;
- end if;
-
- when E_WRITE_PHY_W2 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W3;
- end if;
-
- when E_WRITE_PHY_W3 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W4;
- end if;
-
- when E_WRITE_PHY_W4 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W5;
- end if;
-
- when E_WRITE_PHY_W5 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W6;
- end if;
-
- when E_WRITE_PHY_W6 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W7;
- end if;
-
- when E_WRITE_PHY_W7 =>
- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
- SouthTXM2SxD.ValidxS <= '1';
- SouthTXM2SxD.LastxS <= '1';
-
- if SouthTXS2MxD.ReadyxS = '1' then
- SouthWritePhyStatexDN <= E_WRITE_PHY_W0;
- SouthDataCounterxDN <= SouthDataCounterxDP + 1;
- end if;
-
- when others => null;
- end case;
-
- end process SouthWriteTXPhyxP;
-
- WestWriteTXPhyxP : process (WestDataCounterxDP,
- WestTXS2MxD.ReadyxS,
- WestWritePhyStatexDP) is
- begin -- process WestWriteTXPhyxP
- -- Default values
- WestWritePhyStatexDN <= WestWritePhyStatexDP;
- WestDataCounterxDN <= WestDataCounterxDP;
- WestTXM2SxD.DataxD <= (others => '0');
- WestTXM2SxD.KeepxD <= (others => '1');
- WestTXM2SxD.ValidxS <= '0';
- WestTXM2SxD.LastxS <= '0';
-
- case WestWritePhyStatexDP is
- when E_WRITE_PHY_IDLE =>
- WestWritePhyStatexDN <= E_WRITE_PHY_W0;
-
- when E_WRITE_PHY_W0 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W1;
- end if;
-
- when E_WRITE_PHY_W1 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W2;
- end if;
-
- when E_WRITE_PHY_W2 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W3;
- end if;
-
- when E_WRITE_PHY_W3 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W4;
- end if;
-
- when E_WRITE_PHY_W4 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W5;
- end if;
-
- when E_WRITE_PHY_W5 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W6;
- end if;
-
- when E_WRITE_PHY_W6 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W7;
- end if;
-
- when E_WRITE_PHY_W7 =>
- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
- WestTXM2SxD.ValidxS <= '1';
- WestTXM2SxD.LastxS <= '1';
-
- if WestTXS2MxD.ReadyxS = '1' then
- WestWritePhyStatexDN <= E_WRITE_PHY_W0;
- WestDataCounterxDN <= WestDataCounterxDP + 1;
- end if;
-
- when others => null;
- end case;
-
- end process WestWriteTXPhyxP;
-
- NorthReadRXPhyxP : process (NorthRXFifoStatusxD.ProgEmptyxS,
- NorthRXFifoStatusxD.ProgFullxS,
- NorthRXM2SxD.ValidxS,
- NorthReadPhyStatexDP) is
- begin -- process NorthReadRXPhyxP
- -- Default value
- NorthReadPhyStatexDN <= NorthReadPhyStatexDP;
- NorthRXS2MxD.ReadyxS <= '0';
-
- case NorthReadPhyStatexDP is
- when E_READ_PHY_IDLE =>
- if (NorthRXFifoStatusxD.ProgFullxS = '1') and
- (NorthRXFifoStatusxD.ProgEmptyxS = '0') then
- NorthReadPhyStatexDN <= E_READ_PHY_S0;
- end if;
-
- when E_READ_PHY_S0 =>
- if NorthRXM2SxD.ValidxS = '1' then
- NorthRXS2MxD.ReadyxS <= '1';
- end if;
-
- if (NorthRXFifoStatusxD.ProgFullxS = '0') and
- (NorthRXFifoStatusxD.ProgEmptyxS = '1') then
- NorthReadPhyStatexDN <= E_READ_PHY_IDLE;
- end if;
-
- when others => null;
- end case;
- end process NorthReadRXPhyxP;
-
- EastReadRXPhyxP : process (EastRXFifoStatusxD.ProgEmptyxS,
- EastRXFifoStatusxD.ProgFullxS,
- EastRXM2SxD.ValidxS,
- EastReadPhyStatexDP) is
- begin -- process EastReadRXPhyxP
- -- Default value
- EastReadPhyStatexDN <= EastReadPhyStatexDP;
- EastRXS2MxD.ReadyxS <= '0';
-
- case EastReadPhyStatexDP is
- when E_READ_PHY_IDLE =>
- if (EastRXFifoStatusxD.ProgFullxS = '1') and
- (EastRXFifoStatusxD.ProgEmptyxS = '0') then
- EastReadPhyStatexDN <= E_READ_PHY_S0;
- end if;
-
- when E_READ_PHY_S0 =>
- if EastRXM2SxD.ValidxS = '1' then
- EastRXS2MxD.ReadyxS <= '1';
- end if;
-
- if (EastRXFifoStatusxD.ProgFullxS = '0') and
- (EastRXFifoStatusxD.ProgEmptyxS = '1') then
- EastReadPhyStatexDN <= E_READ_PHY_IDLE;
- end if;
-
- when others => null;
- end case;
- end process EastReadRXPhyxP;
-
- SouthReadRXPhyxP : process (SouthRXFifoStatusxD.ProgEmptyxS,
- SouthRXFifoStatusxD.ProgFullxS,
- SouthRXM2SxD.ValidxS,
- SouthReadPhyStatexDP) is
- begin -- process SouthReadRXPhyxP
- -- Default value
- SouthReadPhyStatexDN <= SouthReadPhyStatexDP;
- SouthRXS2MxD.ReadyxS <= '0';
-
- case SouthReadPhyStatexDP is
- when E_READ_PHY_IDLE =>
- if (SouthRXFifoStatusxD.ProgFullxS = '1') and
- (SouthRXFifoStatusxD.ProgEmptyxS = '0') then
- SouthReadPhyStatexDN <= E_READ_PHY_S0;
- end if;
-
- when E_READ_PHY_S0 =>
- if SouthRXM2SxD.ValidxS = '1' then
- SouthRXS2MxD.ReadyxS <= '1';
- end if;
-
- if (SouthRXFifoStatusxD.ProgFullxS = '0') and
- (SouthRXFifoStatusxD.ProgEmptyxS = '1') then
- SouthReadPhyStatexDN <= E_READ_PHY_IDLE;
- end if;
-
- when others => null;
- end case;
- end process SouthReadRXPhyxP;
-
- WestReadRXPhyxP : process (WestRXFifoStatusxD.ProgEmptyxS,
- WestRXFifoStatusxD.ProgFullxS,
- WestRXM2SxD.ValidxS,
- WestReadPhyStatexDP) is
- begin -- process WestReadRXPhyxP
- -- Default value
- WestReadPhyStatexDN <= WestReadPhyStatexDP;
- WestRXS2MxD.ReadyxS <= '0';
-
- case WestReadPhyStatexDP is
- when E_READ_PHY_IDLE =>
- if (WestRXFifoStatusxD.ProgFullxS = '1') and
- (WestRXFifoStatusxD.ProgEmptyxS = '0') then
- WestReadPhyStatexDN <= E_READ_PHY_S0;
- end if;
-
- when E_READ_PHY_S0 =>
- if WestRXM2SxD.ValidxS = '1' then
- WestRXS2MxD.ReadyxS <= '1';
- end if;
-
- if (WestRXFifoStatusxD.ProgFullxS = '0') and
- (WestRXFifoStatusxD.ProgEmptyxS = '1') then
- WestReadPhyStatexDN <= E_READ_PHY_IDLE;
- end if;
-
- when others => null;
- end case;
- end process WestReadRXPhyxP;
-
- end block DebugxB;
-
- end block ProgrammableLogicxB;
-
-end arch;
diff --git a/designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl b/designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
deleted file mode 100644
index 61be405..0000000
--- a/designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl
+++ /dev/null
@@ -1 +0,0 @@
-source "../../../../../../soc/vivado/scalp_zynqps/2019.2/src/ipi_tcl/scalp_zynqps_ipi.tcl"
\ No newline at end of file
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
index 4aaabb9..8697967 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh
similarity index 88%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh
index 1a425ca..22ffc62 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh
similarity index 86%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh
index 8113284..7d37d3d 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl
similarity index 93%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl
index 9e98aaa..11299db 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware'
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-set_property board_part "hepia-cores.ch:scalp_node:part0:0.1" [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -73,28 +73,28 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
# add IPs source file
- set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
+ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
- set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
- set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
- set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
@@ -113,7 +113,6 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -122,8 +121,7 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
-
+
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh
similarity index 86%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh
index 310b7a1..ceae6a7 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Export the hardware design to SDK
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl
similarity index 90%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl
index 0cdd692..f207949 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Export the hardware design to SDK
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
similarity index 88%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
index 2dc8574..0d72b87 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Generate bitstream file
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
similarity index 92%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
index ce35000..fd267b2 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script used to generate bitstream file
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
similarity index 90%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
index d108356..ae94310 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Generate software application
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
similarity index 94%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
index bf1e395..bcb280b 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script used to generate software application
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
similarity index 86%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
index aa50fc6..2fec043 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Load bitstream file
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
similarity index 93%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
index 7915434..02728f2 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script used to load FPGA bitstream
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
similarity index 86%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
index b12c803..33fb86a 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Load software application
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
similarity index 92%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
index d74f2a7..86f5271 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script used to load software application
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh
similarity index 85%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh
index 634e06b..c5cc591 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
rename to designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl
index 2e7d215..c9dfdfb 100644
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh b/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh
similarity index 91%
rename from designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
rename to designs/vivado/scalp_firmware/2020.2/lin64/setup.sh
index 24068a6..6f157f0 100755
--- a/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-11-30 09:39:40
+# Last update: 2021-01-15 09:27:32
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl b/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc
similarity index 100%
rename from ips/vivado/scalp_aurora_phy/2019.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl
rename to designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc
diff --git a/designs/vivado/scalp_firmware/2019.2/src/constrs/ibert_constraints.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/ibert_constraints.xdc
similarity index 100%
rename from designs/vivado/scalp_firmware/2019.2/src/constrs/ibert_constraints.xdc
rename to designs/vivado/scalp_firmware/2020.2/src/constrs/ibert_constraints.xdc
diff --git a/designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
similarity index 99%
rename from designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc
rename to designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
index 78b9ac5..b1a1c83 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc
+++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
@@ -248,3 +248,5 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
+
diff --git a/designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
similarity index 99%
rename from designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc
rename to designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
index 8891914..9f07492 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -28,3 +28,5 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+
+
diff --git a/designs/vivado/scalp_firmware/2019.2/src/hdl/reset_delay_gen.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/reset_delay_gen.vhd
similarity index 98%
rename from designs/vivado/scalp_firmware/2019.2/src/hdl/reset_delay_gen.vhd
rename to designs/vivado/scalp_firmware/2020.2/src/hdl/reset_delay_gen.vhd
index c1d104f..573ada5 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/hdl/reset_delay_gen.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/reset_delay_gen.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: reset_delay_gen - behavioral
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: Reset Delay Generator
--
-- Last update: 2020-10-12
diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
new file mode 100644
index 0000000..01d1e1e
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -0,0 +1,2222 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: scalp_firmware - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_firmware
+--
+-- Last update: 2021-01-11
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+-- Aurora packages
+use work.aurora_status_pkg.all;
+use work.aurora_drp_pkg.all;
+-- Axi4 packages
+use work.axi4_pkg.all;
+-- Scalp
+use work.scalp_misc.all;
+use work.scalp_utility.all;
+--use work.scalp_sim_packets.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity scalp_firmware is
+
+ generic (
+ C_USE_IBERT : boolean := false;
+ C_DEBUG_MODE : boolean := false;
+ C_RX_FIFO_MODE : boolean := true;
+ C_SCALP_NUMBER_OF_INTERFACE : integer range 0 to 255 := 7;
+ C_SCALP_SCHEDULER_STRATEGY : string := "RR");
+
+ port (
+ -----------------------------------------------------------------------
+ -- Names defined and not described in the constraint file.
+ -----------------------------------------------------------------------
+ -- Zynq FIXED_IO
+ PSClkxCIO : inout std_logic;
+ PSSRstxRNIO : inout std_logic;
+ PSPorxSNIO : inout std_logic;
+ -- DDR interface
+ DDRClkNxCIO : inout std_logic;
+ DDRClkPxCIO : inout std_logic;
+ DDRDRstxRNIO : inout std_logic;
+ DDRCasNxSIO : inout std_logic;
+ DDRCkexSIO : inout std_logic;
+ DDRCsNxSIO : inout std_logic;
+ DDROdtxSIO : inout std_logic;
+ DDRRasNxSIO : inout std_logic;
+ DDRWexSNIO : inout std_logic;
+ DDRBankAddrxDIO : inout std_logic_vector(2 downto 0);
+ DDRAddrxDIO : inout std_logic_vector(14 downto 0);
+ DDRVrNxSIO : inout std_logic;
+ DDRVrPxSIO : inout std_logic;
+ DDRDmxDIO : inout std_logic_vector(3 downto 0);
+ DDRDqxDIO : inout std_logic_vector(31 downto 0);
+ DDRDqsNxDIO : inout std_logic_vector(3 downto 0);
+ DDRDqsPxDIO : inout std_logic_vector(3 downto 0);
+ -- MIO Interface
+ MIOxDIO : inout std_logic_vector(53 downto 0);
+ -----------------------------------------------------------------------
+ -- USB signals
+ UsbVbusPwrFaultxSI : in std_logic;
+ -- PLL interface
+ Pll2V5ClkuWirexCO : out std_logic; -- Clock (from SPI1_SCLK)
+ Pll2V5DatauWirexSO : out std_logic; -- Data (from SPI1_MOSI)
+ Pll2V5LEuWirexSO : out std_logic; -- Latch enable (from SPI1_SS)
+ Pll2V5GOExSO : out std_logic; -- Global Output Enable
+ Pll2V5LDxSI : in std_logic; -- Lock Detect
+ Pll2V5SyncxSO : out std_logic; -- Sync
+ Pll2V5ClkIn0LOSxSI : in std_logic; -- FPGA clock Loss of Sync
+ Pll2V5ClkIn1LOSxSI : in std_logic; -- External oscillator Loss of Sync
+ -- GTP interfaces
+ -- Clocks
+ GTPRefClk0PxCI : in std_logic;
+ GTPRefClk0NxCI : in std_logic;
+ GTPRefClk1PxCI : in std_logic;
+ GTPRefClk1NxCI : in std_logic;
+ -- North
+ GTPFromNorthPxSI : in std_logic;
+ GTPFromNorthNxSI : in std_logic;
+ GTPToNorthPxSO : out std_logic;
+ GTPToNorthNxSO : out std_logic;
+ -- East
+ GTPFromEastPxSI : in std_logic;
+ GTPFromEastNxSI : in std_logic;
+ GTPToEastPxSO : out std_logic;
+ GTPToEastNxSO : out std_logic;
+ -- South
+ GTPFromSouthPxSI : in std_logic;
+ GTPFromSouthNxSI : in std_logic;
+ GTPToSouthPxSO : out std_logic;
+ GTPToSouthNxSO : out std_logic;
+ -- West
+ GTPFromWestPxSI : in std_logic;
+ GTPFromWestNxSI : in std_logic;
+ GTPToWestPxSO : out std_logic;
+ GTPToWestNxSO : out std_logic;
+ -- LVDS links towards edge connectors
+ -- North
+ -- LVDS2V5North0PxSIO : inout std_logic;
+ -- LVDS2V5North0NxSIO : inout std_logic;
+ -- LVDS2V5North1PxSIO : inout std_logic;
+ -- LVDS2V5North1NxSIO : inout std_logic;
+ -- LVDS2V5North2PxSIO : inout std_logic;
+ -- LVDS2V5North2NxSIO : inout std_logic;
+ -- LVDS2V5North3PxSIO : inout std_logic;
+ -- LVDS2V5North3NxSIO : inout std_logic;
+ -- LVDS2V5North4PxSIO : inout std_logic;
+ -- LVDS2V5North4NxSIO : inout std_logic;
+ -- LVDS2V5North5PxSIO : inout std_logic;
+ -- LVDS2V5North5NxSIO : inout std_logic;
+ -- LVDS2V5North6PxSIO : inout std_logic;
+ -- LVDS2V5North6NxSIO : inout std_logic;
+ -- LVDS2V5North7PxSIO : inout std_logic;
+ -- LVDS2V5North7NxSIO : inout std_logic;
+ -- South
+ -- LVDS2V5South0PxSIO : inout std_logic;
+ -- LVDS2V5South0NxSIO : inout std_logic;
+ -- LVDS2V5South1PxSIO : inout std_logic;
+ -- LVDS2V5South1NxSIO : inout std_logic;
+ -- LVDS2V5South2PxSIO : inout std_logic;
+ -- LVDS2V5South2NxSIO : inout std_logic;
+ -- LVDS2V5South3PxSIO : inout std_logic;
+ -- LVDS2V5South3NxSIO : inout std_logic;
+ -- LVDS2V5South4PxSIO : inout std_logic;
+ -- LVDS2V5South4NxSIO : inout std_logic;
+ -- LVDS2V5South5PxSIO : inout std_logic;
+ -- LVDS2V5South5NxSIO : inout std_logic;
+ -- LVDS2V5South6PxSIO : inout std_logic;
+ -- LVDS2V5South6NxSIO : inout std_logic;
+ -- LVDS2V5South7PxSIO : inout std_logic;
+ -- LVDS2V5South7NxSIO : inout std_logic;
+ -- East
+ -- LVDS2V5East0PxSIO : inout std_logic;
+ -- LVDS2V5East0NxSIO : inout std_logic;
+ -- LVDS2V5East1PxSIO : inout std_logic;
+ -- LVDS2V5East1NxSIO : inout std_logic;
+ -- LVDS2V5East2PxSIO : inout std_logic;
+ -- LVDS2V5East2NxSIO : inout std_logic;
+ -- LVDS2V5East3PxSIO : inout std_logic;
+ -- LVDS2V5East3NxSIO : inout std_logic;
+ -- LVDS2V5East4PxSIO : inout std_logic;
+ -- LVDS2V5East4NxSIO : inout std_logic;
+ -- LVDS2V5East5PxSIO : inout std_logic;
+ -- LVDS2V5East5NxSIO : inout std_logic;
+ -- LVDS2V5East6PxSIO : inout std_logic;
+ -- LVDS2V5East6NxSIO : inout std_logic;
+ -- LVDS2V5East7PxSIO : inout std_logic;
+ -- LVDS2V5East7NxSIO : inout std_logic;
+ -- West
+ -- LVDS2V5West0PxSIO : inout std_logic;
+ -- LVDS2V5West0NxSIO : inout std_logic;
+ -- LVDS2V5West1PxSIO : inout std_logic;
+ -- LVDS2V5West1NxSIO : inout std_logic;
+ -- LVDS2V5West2PxSIO : inout std_logic;
+ -- LVDS2V5West2NxSIO : inout std_logic;
+ -- LVDS2V5West3PxSIO : inout std_logic;
+ -- LVDS2V5West3NxSIO : inout std_logic;
+ -- LVDS2V5West4PxSIO : inout std_logic;
+ -- LVDS2V5West4NxSIO : inout std_logic;
+ -- LVDS2V5West5PxSIO : inout std_logic;
+ -- LVDS2V5West5NxSIO : inout std_logic;
+ -- LVDS2V5West6PxSIO : inout std_logic;
+ -- LVDS2V5West6NxSIO : inout std_logic;
+ -- LVDS2V5West7PxSIO : inout std_logic;
+ -- LVDS2V5West7NxSIO : inout std_logic;
+ -- LVDS links towards top-bottom connectors
+ -- Top
+ -- LVDS2V5Top0PxSIO : inout std_logic;
+ -- LVDS2V5Top0NxSIO : inout std_logic;
+ -- LVDS2V5Top1PxSIO : inout std_logic;
+ -- LVDS2V5Top1NxSIO : inout std_logic;
+ -- LVDS2V5Top2PxSIO : inout std_logic;
+ -- LVDS2V5Top2NxSIO : inout std_logic;
+ -- LVDS2V5Top3PxSIO : inout std_logic;
+ -- LVDS2V5Top3NxSIO : inout std_logic;
+ -- LVDS2V5Top4PxSIO : inout std_logic;
+ -- LVDS2V5Top4NxSIO : inout std_logic;
+ -- LVDS2V5Top5PxSIO : inout std_logic;
+ -- LVDS2V5Top5NxSIO : inout std_logic;
+ -- LVDS2V5Top6PxSIO : inout std_logic;
+ -- LVDS2V5Top6NxSIO : inout std_logic;
+ -- LVDS2V5Top7PxSIO : inout std_logic;
+ -- LVDS2V5Top7NxSIO : inout std_logic;
+ -- Bottom
+ -- LVDS2V5Bottom0PxSIO : inout std_logic;
+ -- LVDS2V5Bottom0NxSIO : inout std_logic;
+ -- LVDS2V5Bottom1PxSIO : inout std_logic;
+ -- LVDS2V5Bottom1NxSIO : inout std_logic;
+ -- LVDS2V5Bottom2PxSIO : inout std_logic;
+ -- LVDS2V5Bottom2NxSIO : inout std_logic;
+ -- LVDS2V5Bottom3PxSIO : inout std_logic;
+ -- LVDS2V5Bottom3NxSIO : inout std_logic;
+ -- LVDS2V5Bottom4PxSIO : inout std_logic;
+ -- LVDS2V5Bottom4NxSIO : inout std_logic;
+ -- LVDS2V5Bottom5PxSIO : inout std_logic;
+ -- LVDS2V5Bottom5NxSIO : inout std_logic;
+ -- LVDS2V5Bottom6PxSIO : inout std_logic;
+ -- LVDS2V5Bottom6NxSIO : inout std_logic;
+ -- LVDS2V5Bottom7PxSIO : inout std_logic;
+ -- LVDS2V5Bottom7NxSIO : inout std_logic;
+ -- RGB LEDs
+ Led12V5RxSO : out std_logic;
+ Led12V5GxSO : out std_logic;
+ Led12V5BxSO : out std_logic;
+ Led22V5RxSO : out std_logic;
+ Led22V5GxSO : out std_logic;
+ Led22V5BxSO : out std_logic;
+ -- Self reset (connected to PS_SRSTB)
+ SelfRstxRNO : out std_logic);
+ -- Clocks from PLLs (connected to MRCC pins)
+ -- Local
+ -- PLLClk2V5LocalPxCI : in std_logic;
+ -- PLLClk2V5LocalNxCI : in std_logic;
+ -- -- North
+ -- PLLClk2V5NorthPxCI : in std_logic;
+ -- PLLClk2V5NorthNxCI : in std_logic;
+ -- -- South
+ -- PLLClk2V5SouthPxCI : in std_logic;
+ -- PLLClk2V5SouthNxCI : in std_logic;
+ -- -- Top
+ -- PLLClk2V5TopxCI : in std_logic; -- Single-ended
+ -- -- Bottom
+ -- PLLClk2V5BottomxCI : in std_logic; -- Single-ended
+ -- -- Clocks to/from neighbours
+ -- -- North
+ -- Clk2V5NorthPxCI : in std_logic;
+ -- Clk2V5NorthNxCI : in std_logic;
+ -- Clk2V5NorthPxCO : out std_logic;
+ -- Clk2V5NorthNxCO : out std_logic;
+ -- -- South
+ -- Clk2V5SouthPxCI : in std_logic;
+ -- Clk2V5SouthNxCI : in std_logic;
+ -- Clk2V5SouthPxCO : out std_logic;
+ -- Clk2V5SouthNxCO : out std_logic;
+ -- -- East
+ -- Clk2V5EastPxCI : in std_logic;
+ -- Clk2V5EastNxCI : in std_logic;
+ -- Clk2V5EastPxCO : out std_logic;
+ -- Clk2V5EastNxCO : out std_logic;
+ -- -- West
+ -- Clk2V5WestPxCI : in std_logic;
+ -- Clk2V5WestNxCI : in std_logic;
+ -- Clk2V5WestPxCO : out std_logic;
+ -- Clk2V5WestNxCO : out std_logic;
+ -- -- Top
+ -- Clk2V5TopPxCI : in std_logic;
+ -- Clk2V5TopNxCI : in std_logic;
+ -- Clk2V5TopPxCO : out std_logic;
+ -- Clk2V5TopNxCO : out std_logic;
+ -- -- Bottom
+ -- Clk2V5BottomPxCI : in std_logic;
+ -- Clk2V5BottomNxCI : in std_logic;
+ -- Clk2V5BottomPxCO : out std_logic;
+ -- Clk2V5BottomNxCO : out std_logic;
+ -- -- Recovery
+ -- Clk2V5RecoveryPxCO : out std_logic;
+ -- Clk2V5RecoveryNxCO : out std_logic);
+
+end scalp_firmware;
+
+
+architecture arch of scalp_firmware is
+
+ -- Constantes
+ -- constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
+ constant C_AXI_ADDR_SIZE : integer range 0 to 32 := 12;
+
+ component scalp_aurora_phy is
+ generic (
+ C_DEBUG_MODE : boolean;
+ C_RX_FIFO_MODE : boolean);
+ port (
+ GTRefClkxCI : in t_gt_ref_slave_clk;
+ AuroraClkxCI : in t_aurora_slave_clk;
+ AuroraClkxCO : out t_aurora_master_clk;
+ AuroraResetxRI : in t_aurora_slave_reset;
+ AuroraResetxRO : out t_aurora_master_link_reset;
+ RXResetxRI : in t_rx_reset;
+ RXFifoResetDonexDO : out t_rx_fifo_reset_done;
+ GTPFromNorthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToNorthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromEastxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToEastxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromSouthxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToSouthxDO : out t_aurora_gtp_diff_io_tx;
+ GTPFromWestxDI : in t_aurora_gtp_diff_io_rx;
+ GTPToWestxDO : out t_aurora_gtp_diff_io_tx;
+ NorthRXM2SxDO : out t_axi4m2s;
+ NorthRXS2MxDI : in t_axi4s2m;
+ NorthTXM2SxDI : in t_axi4m2s;
+ NorthTXS2MxDO : out t_axi4s2m;
+ EastRXM2SxDO : out t_axi4m2s;
+ EastRXS2MxDI : in t_axi4s2m;
+ EastTXM2SxDI : in t_axi4m2s;
+ EastTXS2MxDO : out t_axi4s2m;
+ SouthRXM2SxDO : out t_axi4m2s;
+ SouthRXS2MxDI : in t_axi4s2m;
+ SouthTXM2SxDI : in t_axi4m2s;
+ SouthTXS2MxDO : out t_axi4s2m;
+ WestRXM2SxDO : out t_axi4m2s;
+ WestRXS2MxDI : in t_axi4s2m;
+ WestTXM2SxDI : in t_axi4m2s;
+ WestTXS2MxDO : out t_axi4s2m;
+ NorthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ NorthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ NorthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ EastRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ EastTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ EastTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ SouthRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ SouthTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ SouthTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
+ WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
+ WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
+ NorthRXNFCM2SxDO : out t_axi4nfcm2s;
+ NorthTXNFCM2SxDI : in t_axi4nfcm2s;
+ NorthTXNFCS2MxDO : out t_axi4nfcs2m;
+ EastRXNFCM2SxDO : out t_axi4nfcm2s;
+ EastTXNFCM2SxDI : in t_axi4nfcm2s;
+ EastTXNFCS2MxDO : out t_axi4nfcs2m;
+ SouthRXNFCM2SxDO : out t_axi4nfcm2s;
+ SouthTXNFCM2SxDI : in t_axi4nfcm2s;
+ SouthTXNFCS2mxDO : out t_axi4nfcs2m;
+ WestRXNFCM2SxDO : out t_axi4nfcm2s;
+ WestTXNFCM2SxDI : in t_axi4nfcm2s;
+ WestTXNFCS2MxDO : out t_axi4nfcs2m;
+ AuroraCtrlxDI : in t_aurora_control;
+ AuroraStatusxDO : out t_aurora_status;
+ AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
+ AuroraDRPS2MxDO : out t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0);
+ NorthRXFifoStatusxDO : out t_axi4fifo_status;
+ EastRXFifoStatusxDO : out t_axi4fifo_status;
+ SouthRXFifoStatusxDO : out t_axi4fifo_status;
+ WestRXFifoStatusxDO : out t_axi4fifo_status;
+ AxisFifoErrorxDO : out t_axi4fifo_error);
+ end component scalp_aurora_phy;
+
+ -- Signals
+ -- Clocks
+ -- Processing system clock
+ signal PSSysClkxC : std_logic := '0';
+ -- GTP Clocks
+ -- signal GTPRefClk0xC : std_logic := '0';
+ -- signal GTPRefClk1xC : std_logic := '0';
+ signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
+ -- Resets
+ -- Processing system reset
+ signal PSSysResetxR : std_logic := '0';
+ -- Scalp Aurora Phy
+ signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
+ signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
+ signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
+ signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
+ signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
+ signal RXResetxR : t_rx_reset := C_NO_RX_RESET;
+ signal RXFifoResetDonexD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal RXFifoResetDoneDelayedxD : t_rx_fifo_reset_done := C_NO_RX_FIFO_RESET_DONE;
+ signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
+ signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
+ signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
+ signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
+ signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
+ signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
+ signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
+ signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
+ signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
+ signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
+ signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
+ signal NorthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal EastRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal SouthRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal WestRXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
+ signal AxisFifoErrorxD : t_axi4fifo_error := C_NO_AXI4_FIFO_ERROR;
+ -- Scalp Router
+ signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ -- signal ScalpRouterReadyxD : t_scalp_router_ready := C_NO_SCALP_ROUTER_READY;
+ -- Scalp Axi Lite interface and IRQ
+ signal InterruptxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
+ -- Zynq Reg Bank
+ -- type t_status_send_word is (E_IDLE, E_SEND);
+
+ -- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
+ -- signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
+ -- --
+ -- signal NorthNativeSlavexD : t_native_fifo_slave;
+ -- signal NorthNativeMasterxD : t_native_fifo_master;
+ -- signal EastNativeSlavexD : t_native_fifo_slave;
+ -- signal EastNativeMasterxD : t_native_fifo_master;
+ -- signal SouthNativeSlavexD : t_native_fifo_slave;
+ -- signal SouthNativeMasterxD : t_native_fifo_master;
+ -- signal WestNativeSlavexD : t_native_fifo_slave;
+ -- signal WestNativeMasterxD : t_native_fifo_master;
+ --
+ -- signal InterruptRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal InterruptRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- North
+ -- signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- East
+ -- signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- South
+ -- signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- West
+ -- signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- Debug
+ -- signal CntRstxR : std_ulogic := '0';
+ signal ClkEnxS : std_ulogic := '0';
+ signal NorthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal NorthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal EastDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal EastDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal SouthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal SouthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ signal WestDataCounterxDN : unsigned(31 downto 0) := (others => '0');
+ signal WestDataCounterxDP : unsigned(31 downto 0) := (others => '0');
+ --
+ signal DebugCounterResetxR : t_if_common_reset := C_NO_IF_COMMON_RESET;
+ signal DebugRXFifoResetxR : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
+ signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ -- Clocks
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
+ -- North
+ -- East
+ -- attribute mark_debug of EastRXM2SxD : signal is "true";
+ -- attribute keep of EastRXM2SxD : signal is "true";
+ -- attribute mark_debug of EastRXS2MxD : signal is "true";
+ -- attribute keep of EastRXS2MxD : signal is "true";
+ -- attribute mark_debug of EastTXM2SxD : signal is "true";
+ -- attribute keep of EastTXM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXS2MxD : signal is "true";
+ -- attribute keep of EastTXS2MxD : signal is "true";
+ -- South
+ -- West
+ -- attribute mark_debug of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute mark_debug of WestRXS2MxD : signal is "true";
+ -- attribute keep of WestRXS2MxD : signal is "true";
+ -- attribute mark_debug of WestTXM2SxD : signal is "true";
+ -- attribute keep of WestTXM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXS2MxD : signal is "true";
+ -- attribute keep of WestTXS2MxD : signal is "true";
+ -- attribute mark_debug of ScalpRouterReadyxD : signal is "true";
+ -- attribute keep of ScalpRouterReadyxD : signal is "true";
+ -- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
+ -- attribute keep of RXAxism2sVectorxD : signal is "true";
+ -- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of RXAxiss2mVectorxD : signal is "true";
+ -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
+ -- attribute keep of TXAxism2sVectorxD : signal is "true";
+ -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of TXAxiss2mVectorxD : signal is "true";
+
+begin
+
+ ProcessingSystemxB : block is
+ begin -- block ProcessingSystemxB
+
+ ZynqxI : entity work.scalp_zynqps_wrapper
+ port map (
+ -- Processor interface
+ FIXED_IO_ps_clk => PSClkxCIO,
+ FIXED_IO_ps_porb => PSPorxSNIO,
+ FIXED_IO_ps_srstb => PSSRstxRNIO,
+ FclkClk0xCO => PSSysClkxC,
+ FclkReset0xRO => PSSysResetxR,
+ -- DDR interface
+ DDR_addr => DDRAddrxDIO,
+ DDR_ba => DDRBankAddrxDIO,
+ DDR_cas_n => DDRCasNxSIO,
+ DDR_ck_n => DDRClkNxCIO,
+ DDR_ck_p => DDRClkPxCIO,
+ DDR_cke => DDRCkexSIO,
+ DDR_cs_n => DDRCsNxSIO,
+ DDR_dm => DDRDmxDIO,
+ DDR_dq => DDRDqxDIO,
+ DDR_dqs_n => DDRDqsNxDIO,
+ DDR_dqs_p => DDRDqsPxDIO,
+ DDR_odt => DDROdtxSIO,
+ DDR_ras_n => DDRRasNxSIO,
+ DDR_reset_n => DDRDRstxRNIO,
+ DDR_we_n => DDRWexSNIO,
+ FIXED_IO_ddr_vrn => DDRVrNxSIO,
+ FIXED_IO_ddr_vrp => DDRVrPxSIO,
+ -- USB interface
+ Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
+ -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+ -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+ Spi1MOSIxSO => Pll2V5DatauWirexSO,
+ Spi1SSxSO => Pll2V5LEuWirexSO,
+ Spi1SclkxCO => Pll2V5ClkuWirexCO,
+ -- MIO
+ FIXED_IO_mio => MIOxDIO,
+ -- Scalp Axi Lite interface and IRQ
+ InterruptxSI => InterruptxS,
+ RdAddrxDO => RdAddrxD,
+ RdDataxDI => RdDataxD,
+ RdValidxSO => RdValidxS,
+ WrAddrxDO => WrAddrxD,
+ WrDataxDO => WrDataxD,
+ WrValidxSO => WrValidxS);
+
+ end block ProcessingSystemxB;
+
+ ProgrammableLogicxB : block is
+ begin -- block ProgrammableLogicxB
+
+ InputClocksxB : block is
+ begin -- block InputClocksxB
+
+ GTPRefClk0PxAS : GTRefClk0DiffxC.ClkPxC <= GTPRefClk0PxCI;
+ GTPRefClk0NxAS : GTRefClk0DiffxC.ClkNxC <= GTPRefClk0NxCI;
+ -- GTPRefClk1PxAS : GTRefClk0DiffxC.ClkPxC <= GTPRefClk1PxCI;
+ -- GTPRefClk1NxAS : GTRefClk0DiffxC.ClkNxC <= GTPRefClk1NxCI;
+
+ -- GTP Clocks buffers
+ IBufDSGTPRefClk0xI : IBUFDS_GTE2
+ port map (
+ I => GTRefClk0DiffxC.ClkPxC,
+ IB => GTRefClk0DiffxC.ClkNxC,
+ CEB => '0',
+ O => GTRefClk0xC.GTRefClkxC,
+ ODIV2 => open);
+
+ -- IBufDSGTPRefClk1xI : IBUFDS_GTE2
+ -- port map (
+ -- I => GTRefClk0DiffxC.ClkPxC,
+ -- IB => GTRefClk0DiffxC.ClkNxC,
+ -- CEB => '0',
+ -- O => GTRefClk1xCGTRefClkxC,
+ -- ODIV2 => open);
+
+ end block InputClocksxB;
+
+ PllClocksxB : block is
+
+ constant C_AURORA_RST_DLY_TICKS : integer := 25;
+ constant C_GT_RST_DLY_TICKS : integer := 625;
+
+ signal PllLockedxS : std_ulogic := '0';
+
+ begin -- block PllClocksxB
+
+ ScalpAuroraPllxI : entity work.scalp_aurora_clk
+ port map (
+ -- Clock out ports
+ InitClkxCO => AuroraClkSlavexC.InitClkxC,
+ DrpClkxCO => AuroraClkSlavexC.DrpClkxC,
+ -- Status and control signals
+ reset => PSSysResetxR,
+ PllLockedxSO => PllLockedxS,
+ -- Clock in ports
+ PSSysClkxCI => PSSysClkxC);
+
+ AuroraRstDlyxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_AURORA_RST_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkSlavexC.InitClkxC,
+ PllLockedxSI => PllLockedxS,
+ ResetxRI => PSSysResetxR,
+ ResetDelayedxRO => AuroraResetSlavexR.ResetxR);
+
+ GTRstDlyxI : entity work.reset_delay_gen
+ generic map (
+ C_TICKS => C_GT_RST_DLY_TICKS)
+ port map (
+ ClkxCI => AuroraClkSlavexC.InitClkxC,
+ PllLockedxSI => PllLockedxS,
+ ResetxRI => PSSysResetxR,
+ ResetDelayedxRO => AuroraResetSlavexR.GTResetxR);
+
+ end block PllClocksxB;
+
+ GTPhyxB : block is
+
+ constant C_RX_FIFO_RST_DONE_DLY_TICKS : integer := 100;
+
+ begin -- block GTPhyxB
+
+ -- GTP
+ GTPFromNorthPxAS : GTPFromNorthxD.RXPxD(0) <= GTPFromNorthPxSI;
+ GTPFromNorthNxAS : GTPFromNorthxD.RXNxD(0) <= GTPFromNorthNxSI;
+ GTPToNorthPxAS : GTPToNorthPxSO <= GTPToNorthxD.TXPxD(0);
+ GTPToNorthNxAS : GTPToNorthNxSO <= GTPToNorthxD.TXNxD(0);
+ GTPFromEastPxAS : GTPFromEastxD.RXPxD(0) <= GTPFromEastPxSI;
+ GTPFromEastNxAS : GTPFromEastxD.RXNxD(0) <= GTPFromEastNxSI;
+ GTPToEastPxAS : GTPToEastPxSO <= GTPToEastxD.TXPxD(0);
+ GTPToEastNxAS : GTPToEastNxSO <= GTPToEastxD.TXNxD(0);
+ GTPFromSouthPxAS : GTPFromSouthxD.RXPxD(0) <= GTPFromSouthPxSI;
+ GTPFromSouthNxAS : GTPFromSouthxD.RXNxD(0) <= GTPFromSouthNxSI;
+ GTPToSouthPxAS : GTPToSouthPxSO <= GTPToSouthxD.TXPxD(0);
+ GTPToSouthNxAS : GTPToSouthNxSO <= GTPToSouthxD.TXNxD(0);
+ GTPFromWestPxAS : GTPFromWestxD.RXPxD(0) <= GTPFromWestPxSI;
+ GTPFromWestNxAS : GTPFromWestxD.RXNxD(0) <= GTPFromWestNxSI;
+ GTPToWestPxAS : GTPToWestPxSO <= GTPToWestxD.TXPxD(0);
+ GTPToWestNxAS : GTPToWestNxSO <= GTPToWestxD.TXNxD(0);
+
+ CtrlxB : block is
+ begin -- block CtrlxB
+
+ PowerDownxAS : AuroraCtrlxD.PowerDownxS <= '0';
+ LoopbackxAS : AuroraCtrlxD.LoopbackxD <= (others => '0');
+
+ end block CtrlxB;
+
+ ScalpAuroraPhyxI : entity work.scalp_aurora_phy
+ generic map (
+ C_DEBUG_MODE => C_DEBUG_MODE,
+ C_RX_FIFO_MODE => C_RX_FIFO_MODE,
+ C_RX_FIFO_RST_DONE_DLY_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
+ port map (
+ -- Clocks
+ -- GTP Ref Clocks
+ GTRefClkxCI => GTRefClk0xC,
+ -- Aurora System and GTP Clocks
+ AuroraClkxCI => AuroraClkSlavexC,
+ AuroraClkxCO => AuroraClkMasterxC,
+ -- Reset
+ -- Aurora Reset
+ AuroraResetxRI => AuroraResetSlavexR,
+ AuroraResetxRO => AuroraResetMasterLinkxR,
+ -- RX Fifo and Back Pressure Reset
+ RXResetxRI => RXResetxR,
+ RXFifoResetDonexDO => RXFifoResetDonexD,
+ RXFifoResetDoneDelayedxDO => RXFifoResetDoneDelayedxD,
+ -- Back Pressure Reset
+ -- GTP Serial IO
+ -- North
+ GTPFromNorthxDI => GTPFromNorthxD,
+ GTPToNorthxDO => GTPToNorthxD,
+ -- East
+ GTPFromEastxDI => GTPFromEastxD,
+ GTPToEastxDO => GTPToEastxD,
+ -- South
+ GTPFromSouthxDI => GTPFromSouthxD,
+ GTPToSouthxDO => GTPToSouthxD,
+ -- West
+ GTPFromWestxDI => GTPFromWestxD,
+ GTPToWestxDO => GTPToWestxD,
+ -- Axi4 Framing Interface
+ -- North
+ NorthRXM2SxDO => NorthRXM2SxD,
+ NorthRXS2MxDI => NorthRXS2MxD,
+ NorthTXM2SxDI => NorthTXM2SxD,
+ NorthTXS2MxDO => NorthTXS2MxD,
+ -- East
+ EastRXM2SxDO => EastRXM2SxD,
+ EastRXS2MxDI => EastRXS2MxD,
+ EastTXM2SxDI => EastTXM2SxD,
+ EastTXS2MxDO => EastTXS2MxD,
+ -- South
+ SouthRXM2SxDO => SouthRXM2SxD,
+ SouthRXS2MxDI => SouthRXS2MxD,
+ SouthTXM2SxDI => SouthTXM2SxD,
+ SouthTXS2MxDO => SouthTXS2MxD,
+ -- West
+ WestRXM2SxDO => WestRXM2SxD,
+ WestRXS2MxDI => WestRXS2MxD,
+ WestTXM2SxDI => WestTXM2SxD,
+ WestTXS2MxDO => WestTXS2MxD,
+ -- Axi4 Framing UFC Interface
+ -- North
+ NorthRXUFCM2SxDO => NorthRXUFCM2SxD,
+ NorthTXUFCM2SxDI => NorthTXUFCM2SxD,
+ NorthTXUFCS2MxDO => NorthTXUFCS2MxD,
+ -- East
+ EastRXUFCM2SxDO => EastRXUFCM2SxD,
+ EastTXUFCM2SxDI => EastTXUFCM2SxD,
+ EastTXUFCS2MxDO => EastTXUFCS2MxD,
+ -- South
+ SouthRXUFCM2SxDO => SouthRXUFCM2SxD,
+ SouthTXUFCM2SxDI => SouthTXUFCM2SxD,
+ SouthTXUFCS2MxDO => SouthTXUFCS2MxD,
+ -- West
+ WestRXUFCM2SxDO => WestRXUFCM2SxD,
+ WestTXUFCM2SxDI => WestTXUFCM2SxD,
+ WestTXUFCS2MxDO => WestTXUFCS2MxD,
+ -- Axi4 Framing NFC Interface
+ -- The NFC interface is not available when the
+ -- constant C_RX_FIFO_MODE is set to TRUE.
+ -- North
+ NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
+ NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
+ NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
+ -- East
+ EastRXNFCM2SxDO => EastRXNFCM2SxD,
+ EastTXNFCM2SxDI => EastTXNFCM2SxD,
+ EastTXNFCS2MxDO => EastTXNFCS2MxD,
+ -- South
+ SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
+ SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
+ SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
+ -- West
+ WestRXNFCM2SxDO => WestRXNFCM2SxD,
+ WestTXNFCM2SxDI => WestTXNFCM2SxD,
+ WestTXNFCS2MxDO => WestTXNFCS2MxD,
+ -- Aurora Ctrl + Status
+ AuroraCtrlxDI => AuroraCtrlxD,
+ AuroraStatusxDO => AuroraStatusxD,
+ -- DRP Port
+ AuroraDRPM2SxDI => AuroraDRPM2SxD,
+ AuroraDRPS2MxDO => AuroraDRPS2MxD,
+ -- RX Fifo Status
+ -- North
+ NorthRXFifoStatusxDO => NorthRXFifoStatusxD,
+ -- East
+ EastRXFifoStatusxDO => EastRXFifoStatusxD,
+ -- South
+ SouthRXFifoStatusxDO => SouthRXFifoStatusxD,
+ -- West
+ WestRXFifoStatusxDO => WestRXFifoStatusxD,
+ -- Axis Fifo Error
+ AxisFifoErrorxDO => AxisFifoErrorxD);
+
+ end block GTPhyxB;
+
+ NetworkLayerxB : block is
+
+ constant C_SCALP_PACKET_PAYLOAD_SIZE : integer range 1 to C_SCALP_PACKET_LENGTH_RANGE_VALUE := 8;
+ constant C_SCALP_RANDOM_READY : boolean := false;
+ ---------------------------------------------------------------------------
+ -- Scalp Packets
+ ---------------------------------------------------------------------------
+
+ constant C_SCALP_PACKET_NET_ADDR_110 : t_scalp_netaddr
+ := (XxD => 1, YxD => 1, ZxD => 0);
+ constant C_SCALP_PACKET_NET_ADDR_210 : t_scalp_netaddr
+ := (XxD => 2, YxD => 1, ZxD => 0);
+ ---------------------------------------------------------------------------
+ -- Scalp Packet Headers
+ ---------------------------------------------------------------------------
+ constant C_SP_HEADER_NULL : t_scalp_packet_header := C_NO_SCALP_PACKET_HEADER;
+ constant C_SP_HEADER_110_TO_210 : t_scalp_packet_header
+ := (DstAddrxD => C_SCALP_PACKET_NET_ADDR_210,
+ SrcAddrxD => C_SCALP_PACKET_NET_ADDR_110,
+ TypexD => 1,
+ LengthxD => C_SCALP_PACKET_PAYLOAD_SIZE);
+ ---------------------------------------------------------------------------
+ -- Scalp Packet Payloads
+ ---------------------------------------------------------------------------
+ constant C_SP_PAYLOAD_NULL : t_scalp_packet_payload(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))
+ := (0 => C_NO_SCALP_PACKET_WORD,
+ 1 => C_NO_SCALP_PACKET_WORD,
+ 2 => C_NO_SCALP_PACKET_WORD,
+ 3 => C_NO_SCALP_PACKET_WORD,
+ 4 => C_NO_SCALP_PACKET_WORD,
+ 5 => C_NO_SCALP_PACKET_WORD,
+ 6 => C_NO_SCALP_PACKET_WORD,
+ 7 => C_NO_SCALP_PACKET_WORD);
+ constant C_SP_PAYLOAD_0 : t_scalp_packet_payload(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))
+ := (0 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0abbccdd#, (C_BYTE_SIZE * 4))),
+ IdxD => 0),
+ 1 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0bccddee#, (C_BYTE_SIZE * 4))),
+ IdxD => 1),
+ 2 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0cddeeff#, (C_BYTE_SIZE * 4))),
+ IdxD => 2),
+ 3 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0deeff11#, (C_BYTE_SIZE * 4))),
+ IdxD => 3),
+ 4 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0eff1122#, (C_BYTE_SIZE * 4))),
+ IdxD => 4),
+ 5 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#0f112233#, (C_BYTE_SIZE * 4))),
+ IdxD => 5),
+ 6 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#01223344#, (C_BYTE_SIZE * 4))),
+ IdxD => 6),
+ 7 =>
+ (WordxD => std_ulogic_vector(to_unsigned(16#02334455#, (C_BYTE_SIZE * 4))),
+ IdxD => 7));
+
+ type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
+
+ signal ScalpRouterResetxRNA : std_ulogic := '0';
+ -- Scalp Packets
+ -- From South 101
+ ---------------------------------------------------------------------------
+ ---------------------------------------------------------------------------
+ signal ScalpPacketLocalxD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
+ (SpHeaderxD => C_SP_HEADER_NULL,
+ SpPayloadxD => C_SP_PAYLOAD_NULL);
+ signal ScalpPacketValidLocalxS : std_ulogic := '0';
+ signal ScalpPacketSelectLocalxD : integer := 0;
+ ---------------------------------------------------------------------------
+ -- Packet 0
+ signal ScalpPacket0xD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
+ (SpHeaderxD => C_SP_HEADER_110_TO_210,
+ SpPayloadxD => C_SP_PAYLOAD_0);
+ signal ScalpPacketValid12xS : std_ulogic := '0';
+ --
+ signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
+ signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
+ signal VioWrSpValidxS : std_ulogic := '0';
+
+ -- attribute mark_debug of ScalpRouterResetxRNA : signal is "true";
+ -- attribute keep of ScalpRouterResetxRNA : signal is "true";
+ -- attribute mark_debug of ScalpPacket0xD : signal is "true";
+ -- attribute keep of ScalpPacket0xD : signal is "true";
+ -- attribute mark_debug of WrSPStatexDP : signal is "true";
+ -- attribute keep of WrSPStatexDP : signal is "true";
+ -- attribute mark_debug of WrSPStatexDN : signal is "true";
+ -- attribute keep of WrSPStatexDN : signal is "true";
+ -- attribute mark_debug of VioWrSpValidxS : signal is "true";
+ -- attribute keep of VioWrSpValidxS : signal is "true";
+ -- attribute mark_debug of ScalpPacketLocalxD : signal is "true";
+ -- attribute keep of ScalpPacketLocalxD : signal is "true";
+ -- attribute mark_debug of ScalpPacketValidLocalxS : signal is "true";
+ -- attribute keep of ScalpPacketValidLocalxS : signal is "true";
+
+ begin -- block NetworkLayerxB
+
+ ResetxB : block is
+
+ constant C_CDC_TYPE : integer range 0 to 2 := 1;
+ constant C_RESET_STATE : integer range 0 to 1 := 0;
+ constant C_SINGLE_BIT : integer range 0 to 1 := 1;
+ constant C_FLOP_INPUT : integer range 0 to 1 := 1;
+ constant C_VECTOR_WIDTH : integer range 0 to 32 := 2;
+ constant C_MTBF_STAGES : integer range 0 to 6 := 5;
+
+ signal PrimaryResetxRN : std_ulogic := '0';
+ signal SecondaryResetxRN : std_ulogic := '0';
+ signal PSSysResetSyncxR : std_ulogic := '0';
+
+ begin -- block ResetxB
+
+ PrimaryResetxAS : PrimaryResetxRN <= not PSSysResetxR;
+ SecondaryResetxAS : SecondaryResetxRN <= not AuroraClkMasterxC.PllNotLockedxS;
+
+ CDCSyncResetxB : entity work.cdc_sync
+ generic map (
+ C_CDC_TYPE => C_CDC_TYPE,
+ C_RESET_STATE => C_RESET_STATE,
+ C_SINGLE_BIT => C_SINGLE_BIT,
+ C_FLOP_INPUT => C_FLOP_INPUT,
+ C_VECTOR_WIDTH => C_VECTOR_WIDTH,
+ C_MTBF_STAGES => C_MTBF_STAGES)
+ port map (
+ PrimaryClkxCAI => PSSysClkxC,
+ PrimaryResetxRNI => PrimaryResetxRN,
+ PrimaryxSI => PSSysResetxR,
+ PrimaryxDI => (others => '0'),
+ PrimaryAckxSO => open,
+ SecondaryClkxCAI => AuroraClkMasterxC.UserClkxC,
+ SecondaryResetxRNI => SecondaryResetxRN,
+ SecondaryxSO => PSSysResetSyncxR,
+ SecondaryxDO => open);
+
+ ScalpRouterResetxAS : ScalpRouterResetxRNA <= (not PSSysResetSyncxR) and
+ (not AuroraClkMasterxC.PllNotLockedxS);
+ -- RX Fifo reset 196 cycles
+ -- Clock and Resets
+ -- RX Fifo
+ NorthFifoResetxAS : RXResetxR.FifoResetxR.NorthxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ '0';
+ EastFifoResetxAS : RXResetxR.FifoResetxR.EastxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ '0';
+ SouthFifoResetxAS : RXResetxR.FifoResetxR.SouthxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ '0';
+ WestFifoResetxAS : RXResetxR.FifoResetxR.WestxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ '0';
+ -- Back pressure
+ NorthBackPressureResetxAS : RXResetxR.BackPressureResetxR.NorthxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ (RXFifoResetDonexD.NorthxS = '0') or
+ (RXFifoResetDoneDelayedxD.NorthxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ '0';
+ EastBackPressureResetxAS : RXResetxR.BackPressureResetxR.EastxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ (RXFifoResetDonexD.EastxS = '0') or
+ (RXFifoResetDoneDelayedxD.EastxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ '0';
+ SouthBackPressureResetxAS : RXResetxR.BackPressureResetxR.SouthxR <=
+ '1' when
+ (RXFifoResetDonexD.SouthxS = '0') or
+ (RXFifoResetDoneDelayedxD.SouthxS = '0') or
+ (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ '0';
+ WestBackPressureResetxAS : RXResetxR.BackPressureResetxR.WestxR <=
+ '1' when
+ (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ (RXFifoResetDonexD.WestxS = '0') or
+ (RXFifoResetDoneDelayedxD.WestxS = '0') or
+ (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ '0';
+
+ end block ResetxB;
+
+ -- ScalpRouterReadyxB : block is
+ -- begin -- block ScalpRouterReadyxB
+
+ -- ScalpRouterReadyNorthxAS : ScalpRouterReadyxD.NorthxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.NorthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.NorthxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ -- '1';
+ -- ScalpRouterReadyEastxAS : ScalpRouterReadyxD.EastxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.EastxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.EastxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ -- '1';
+ -- ScalpRouterReadySouthxAS : ScalpRouterReadyxD.SouthxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.SouthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.SouthxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ -- '1';
+ -- ScalpRouterReadyWestxAS : ScalpRouterReadyxD.WestxS <=
+ -- '0' when
+ -- (RXFifoResetDonexD.WestxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.WestxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ -- '1';
+ -- ScalpRouterReadyTopxAS : ScalpRouterReadyxD.TopxS <= '0';
+ -- ScalpRouterReadyBottomxAS : ScalpRouterReadyxD.BottomxS <= '0';
+ -- ScalpRouterReadyLocalxAS : ScalpRouterReadyxD.LocalxS <= (not PSSysResetxR) and
+ -- (not AuroraClkMasterxC.PllNotLockedxS);
+
+ -- end block ScalpRouterReadyxB;
+
+ NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
+ EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID);
+ SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID);
+ WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID);
+ NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD;
+ EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
+ SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
+ WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
+ NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
+ EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
+ SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
+ WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD;
+ NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID);
+ EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID);
+ SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
+ WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
+ -- Local Router Net Addr
+ LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_110;
+ -- Local Ready
+ -- RXAxiss2mVectorxD(C_LOCAL_IF_ID) <=
+
+ WrSpValidxI : entity work.vio_axi_cnt_ctrl
+ port map (
+ clk => AuroraClkMasterxC.UserClkxC,
+ probe_out0(0) => VioWrSpValidxS);
+
+ ScalpSP2AxisLocalxI : entity work.scalp_sp_to_axis
+ generic map (
+ C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE)
+ port map (
+ SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ SysRstxRNAI => ScalpRouterResetxRNA,
+ ScalpPacketxDI => ScalpPacket0xD,
+ ScalpPacketValidxSI => ScalpPacketValid12xS,
+ ScalpAxism2sxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID),
+ ScalpAxiss2mxDI => RXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ ScalpRdyxSO => open);
+
+ ScalpRouterxI : entity work.scalp_router
+ generic map (
+ C_SCALP_NUMBER_OF_INTERFACE => C_SCALP_NUMBER_OF_INTERFACE,
+ C_SCALP_SCHEDULER_STRATEGY => C_SCALP_SCHEDULER_STRATEGY)
+ port map (
+ SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ SysRstxRNAI => ScalpRouterResetxRNA,
+ LocNetAddrxDI => LocNetAddrxD,
+ RXAxism2sVectorxDI => RXAxism2sVectorxD,
+ RXAxiss2mVectorxDO => RXAxiss2mVectorxD,
+ TXAxism2sVectorxDO => TXAxism2sVectorxD,
+ TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
+ QoSVectorxDI => QoSVectorxD);
+
+ ScalpAxis2SPxI : entity work.scalp_axis_to_sp
+ generic map (
+ C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
+ C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY)
+ port map (
+ SysClkxCI => AuroraClkMasterxC.UserClkxC,
+ SysRstxRNAI => ScalpRouterResetxRNA,
+ ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
+ ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ ScalpPacketxDO => ScalpPacketLocalxD,
+ ScalpPacketValidxSO => ScalpPacketValidLocalxS);
+
+ WritePacketxB : block is
+ begin -- block WritePacketxB
+
+ UpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ ScalpRouterResetxRNA) is
+ begin -- process UpdateRegxP
+ if ScalpRouterResetxRNA = '0' then
+ WrSPStatexDP <= E_WR_SP_IDLE;
+ elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ WrSPStatexDP <= WrSPStatexDN;
+ end if;
+ end process UpdateRegxP;
+
+ SpValidxP : process (VioWrSpValidxS, WrSPStatexDP) is
+ begin -- process SpValidxP
+ -- Default values
+ WrSPStatexDN <= WrSPStatexDP;
+ ScalpPacketValid12xS <= '0';
+
+ case WrSPStatexDP is
+ when E_WR_SP_IDLE =>
+ if VioWrSpValidxS = '1' then
+ ScalpPacketValid12xS <= '1';
+ WrSPStatexDN <= E_WR_SP_VALID;
+ end if;
+ when E_WR_SP_VALID =>
+ ScalpPacketValid12xS <= '0';
+ WrSPStatexDN <= E_WR_SP_WAIT;
+ when E_WR_SP_WAIT =>
+ if VioWrSpValidxS = '0' then
+ WrSPStatexDN <= E_WR_SP_IDLE;
+ end if;
+ when others => null;
+ end case;
+ end process SpValidxP;
+
+ end block WritePacketxB;
+
+ end block NetworkLayerxB;
+
+ ZynqRegBankxB : block is
+ begin -- block ZynqRegBankxB
+
+ RegBankxB : block is
+ begin -- block RegBankxB
+
+ WriteRegPortxP : process (NorthCtrlRegPortxDP, WrAddrxD,
+ WrDataxD, WrValidxS) is
+ begin -- process WriteRegPortxP
+ -- North
+ NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP;
+ -- NorthWrDataRegPortxDN <= NorthWrDataRegPortxDP;
+ -- -- East
+ -- EastCtrlRegPortxDN <= EastCtrlRegPortxDP;
+ -- EastWrDataRegPortxDN <= EastWrDataRegPortxDP;
+ -- -- South
+ -- SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP;
+ -- SouthWrDataRegPortxDN <= SouthWrDataRegPortxDP;
+ -- -- West
+ -- WestCtrlRegPortxDN <= WestCtrlRegPortxDP;
+ -- WestWrDataRegPortxDN <= WestWrDataRegPortxDP;
+
+ if WrValidxS = '1' then
+ case WrAddrxD is
+ -- Ctrl
+ -- North
+ when x"000" => NorthCtrlRegPortxDN <= WrDataxD;
+ when x"004" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP or WrDataxD;
+ when x"008" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP and not WrDataxD;
+ -- East
+ -- when x"00c" => EastCtrlRegPortxDN <= WrDataxD;
+ -- when x"010" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP or WrDataxD;
+ -- when x"014" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP and not WrDataxD;
+ -- -- South
+ -- when x"018" => SouthCtrlRegPortxDN <= WrDataxD;
+ -- when x"01c" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP or WrDataxD;
+ -- when x"020" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP and not WrDataxD;
+ -- -- East
+ -- when x"024" => WestCtrlRegPortxDN <= WrDataxD;
+ -- when x"028" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP or WrDataxD;
+ -- when x"02c" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP and not WrDataxD;
+ -- -- Data
+ -- -- North
+ -- when x"030" => NorthWrDataRegPortxDN <= WrDataxD;
+ -- -- East
+ -- when x"034" => EastWrDataRegPortxDN <= WrDataxD;
+ -- -- South
+ -- when x"038" => SouthWrDataRegPortxDN <= WrDataxD;
+ -- -- West
+ -- when x"03c" => WestWrDataRegPortxDN <= WrDataxD;
+ when others => null;
+ end case;
+ end if;
+ end process WriteRegPortxP;
+
+ ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
+ begin -- process ReadRegPortxP
+ if PSSysResetxR = '1' then
+ RdDataxD <= (others => '0');
+ elsif rising_edge(PSSysClkxC) then
+ RdDataxD <= (others => '0');
+
+ if RdValidxS = '1' then
+ case RdAddrxD is
+ when x"000" => RdDataxD <= NorthCtrlRegPortxDP;
+ -- when x"00C" => RdDataxD <= EastCtrlRegPortxDP;
+ -- when x"018" => RdDataxD <= SouthCtrlRegPortxDP;
+ -- when x"024" => RdDataxD <= WestCtrlRegPortxDP;
+ -- when x"030" => RdDataxD <= NorthWrDataRegPortxDP;
+ -- when x"034" => RdDataxD <= EastWrDataRegPortxDP;
+ -- when x"038" => RdDataxD <= SouthWrDataRegPortxDP;
+ -- when x"03c" => RdDataxD <= WestWrDataRegPortxDP;
+ -- when x"040" => RdDataxD <= NorthStatusRegPortxDP;
+ -- when x"044" => RdDataxD <= EastStatusRegPortxDP;
+ -- when x"048" => RdDataxD <= SouthStatusRegPortxDP;
+ -- when x"04c" => RdDataxD <= WestStatusRegPortxDP;
+ when others => RdDataxD <= x"aabbccdd";
+ end case;
+ end if;
+ end if;
+ end process ReadRegPortxP;
+
+ RegBankxP : process (PSSysClkxC, PSSysResetxR) is
+ begin -- process RegBankxP
+ if PSSysResetxR = '1' then
+ -- North
+ -- NorthStatusRegPortxDP <= (others => '0');
+ NorthCtrlRegPortxDP <= (others => '0');
+ -- NorthWrDataRegPortxDP <= (others => '0');
+ -- East
+ -- EastStatusRegPortxDP <= (others => '0');
+ -- EastCtrlRegPortxDP <= (others => '0');
+ -- EastWrDataRegPortxDP <= (others => '0');
+ -- -- South
+ -- SouthStatusRegPortxDP <= (others => '0');
+ -- SouthCtrlRegPortxDP <= (others => '0');
+ -- SouthWrDataRegPortxDP <= (others => '0');
+ -- -- West
+ -- WestStatusRegPortxDP <= (others => '0');
+ -- WestCtrlRegPortxDP <= (others => '0');
+ -- WestWrDataRegPortxDP <= (others => '0');
+ elsif rising_edge(PSSysClkxC) then
+ -- North
+ -- NorthStatusRegPortxDP <= NorthStatusRegPortxDN;
+ NorthCtrlRegPortxDP <= NorthCtrlRegPortxDN;
+ -- NorthWrDataRegPortxDP <= NorthWrDataRegPortxDN;
+ -- -- East
+ -- EastStatusRegPortxDP <= EastStatusRegPortxDN;
+ -- EastCtrlRegPortxDP <= EastCtrlRegPortxDN;
+ -- EastWrDataRegPortxDP <= EastWrDataRegPortxDN;
+ -- -- South
+ -- SouthStatusRegPortxDP <= SouthStatusRegPortxDN;
+ -- SouthCtrlRegPortxDP <= SouthCtrlRegPortxDN;
+ -- SouthWrDataRegPortxDP <= SouthWrDataRegPortxDN;
+ -- -- West
+ -- WestStatusRegPortxDP <= WestStatusRegPortxDN;
+ -- WestCtrlRegPortxDP <= WestCtrlRegPortxDN;
+ -- WestWrDataRegPortxDP <= WestWrDataRegPortxDN;
+ end if;
+ end process RegBankxP;
+
+ end block RegBankxB;
+
+ -- TxFifoxB : block is
+ -- begin -- block TxFifoxB
+
+ -- NorthWrDataxAS : NorthNativeSlavexD.DataxD <= NorthWrDataRegPortxDP;
+ -- EastWrDataxAS : EastNativeSlavexD.DataxD <= EastWrDataRegPortxDP;
+ -- SouthWrDataxAS : SouthNativeSlavexD.DataxD <= SouthWrDataRegPortxDN;
+ -- WestWrDataRegxAS : WestNativeSlavexD.DataxD <= WestWrDataRegPortxDN;
+ -- NorthWrEnxAS : NorthNativeSlavexD.WrEnxS <= NorthCtrlRegPortxDP(0);
+ -- EastWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
+ -- SouthWrEnxAS : SouthNativeSlavexD.WrEnxS <= SouthCtrlRegPortxDP(0);
+ -- WestWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
+ -- NorthStatusRegPortxAS : NorthStatusRegPortxDN <= (0 => NorthNativeMasterxD.FullxS,
+ -- 1 => NorthNativeMasterxD.EmptyxS,
+ -- 2 => NorthNativeMasterxD.AlmostFullxS,
+ -- 3 => NorthNativeMasterxD.AlmostEmptyxS,
+ -- 4 => NorthNativeMasterxD.WrRstBusyxS,
+ -- 5 => NorthNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+ -- EastStatusRegPortxAS : EastStatusRegPortxDN <= (0 => EastNativeMasterxD.FullxS,
+ -- 1 => EastNativeMasterxD.EmptyxS,
+ -- 2 => EastNativeMasterxD.AlmostFullxS,
+ -- 3 => EastNativeMasterxD.AlmostEmptyxS,
+ -- 4 => EastNativeMasterxD.WrRstBusyxS,
+ -- 5 => EastNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+ -- SouthStatusRegPortxAS : SouthStatusRegPortxDN <= (0 => SouthNativeMasterxD.FullxS,
+ -- 1 => SouthNativeMasterxD.EmptyxS,
+ -- 2 => SouthNativeMasterxD.AlmostFullxS,
+ -- 3 => SouthNativeMasterxD.AlmostEmptyxS,
+ -- 4 => SouthNativeMasterxD.WrRstBusyxS,
+ -- 5 => SouthNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+ -- WestStatusRegPortxAS : WestStatusRegPortxDN <= (0 => WestNativeMasterxD.FullxS,
+ -- 1 => WestNativeMasterxD.EmptyxS,
+ -- 2 => WestNativeMasterxD.AlmostFullxS,
+ -- 3 => WestNativeMasterxD.AlmostEmptyxS,
+ -- 4 => WestNativeMasterxD.WrRstBusyxS,
+ -- 5 => WestNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+
+ -- UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
+ -- AuroraClkMasterxC.UserClkxC) is
+ -- begin -- process UpdateRegxP
+ -- if not AuroraClkMasterxC.PllNotLockedxS then
+ -- NorthStatusSendWordxDP <= E_IDLE;
+ -- EastStatusSendWordxDP <= E_IDLE;
+ -- SouthStatusSendWordxDP <= E_IDLE;
+ -- WestStatusSendWordxDP <= E_IDLE;
+ -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- NorthStatusSendWordxDP <= NorthStatusSendWordxDN;
+ -- EastStatusSendWordxDP <= EastStatusSendWordxDN;
+ -- SouthStatusSendWordxDP <= SouthStatusSendWordxDN;
+ -- WestStatusSendWordxDP <= WestStatusSendWordxDN;
+ -- end if;
+ -- end process UpdateRegxP;
+
+ -- NorthSendWordxP : process (NorthNativeMasterxD.DataxD,
+ -- NorthNativeMasterxD.EmptyxS,
+ -- NorthStatusSendWordxDP,
+ -- NorthTXS2MxD.ReadyxS) is
+ -- begin -- process NorthSendWordxP
+ -- NorthTXM2SxD.DataxD <= (others => '0');
+ -- NorthTXM2SxD.KeepxD <= (others => '1');
+ -- NorthTXM2SxD.LastxS <= '0';
+ -- NorthTXM2SxD.ValidxS <= '0';
+ -- NorthNativeSlavexD.RdEnxS <= '0';
+ -- NorthStatusSendWordxDN <= NorthStatusSendWordxDP;
+
+ -- case NorthStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (NorthNativeMasterxD.EmptyxS = '0') and
+ -- (NorthTXS2MxD.ReadyxS = '1') then
+ -- NorthTXM2SxD.DataxD <= NorthNativeMasterxD.DataxD;
+ -- NorthTXM2SxD.LastxS <= '1';
+ -- NorthTXM2SxD.ValidxS <= '1';
+ -- NorthNativeSlavexD.RdEnxS <= '1';
+ -- NorthStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- NorthStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process NorthSendWordxP;
+
+ -- EastSendWordxP : process (EastNativeMasterxD.DataxD,
+ -- EastNativeMasterxD.EmptyxS,
+ -- EastStatusSendWordxDP,
+ -- EastTXS2MxD.ReadyxS) is
+ -- begin -- process EastSendWordxP
+ -- EastTXM2SxD.DataxD <= (others => '0');
+ -- EastTXM2SxD.KeepxD <= (others => '1');
+ -- EastTXM2SxD.LastxS <= '0';
+ -- EastTXM2SxD.ValidxS <= '0';
+ -- EastNativeSlavexD.RdEnxS <= '0';
+ -- EastStatusSendWordxDN <= EastStatusSendWordxDP;
+
+ -- case EastStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (EastNativeMasterxD.EmptyxS = '0') and
+ -- (EastTXS2MxD.ReadyxS = '1') then
+ -- EastTXM2SxD.DataxD <= EastNativeMasterxD.DataxD;
+ -- EastTXM2SxD.LastxS <= '1';
+ -- EastTXM2SxD.ValidxS <= '1';
+ -- EastNativeSlavexD.RdEnxS <= '1';
+ -- EastStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- EastStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process EastSendWordxP;
+
+ -- SouthSendWordxP : process (SouthNativeMasterxD.DataxD,
+ -- SouthNativeMasterxD.EmptyxS,
+ -- SouthStatusSendWordxDP,
+ -- SouthTXS2MxD.ReadyxS) is
+ -- begin -- process SouthSendWordxP
+ -- SouthTXM2SxD.DataxD <= (others => '0');
+ -- SouthTXM2SxD.KeepxD <= (others => '1');
+ -- SouthTXM2SxD.LastxS <= '0';
+ -- SouthTXM2SxD.ValidxS <= '0';
+ -- SouthNativeSlavexD.RdEnxS <= '0';
+ -- SouthStatusSendWordxDN <= SouthStatusSendWordxDP;
+
+ -- case SouthStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (SouthNativeMasterxD.EmptyxS = '0') and
+ -- (SouthTXS2MxD.ReadyxS = '1') then
+ -- SouthTXM2SxD.DataxD <= SouthNativeMasterxD.DataxD;
+ -- SouthTXM2SxD.LastxS <= '1';
+ -- SouthTXM2SxD.ValidxS <= '1';
+ -- SouthNativeSlavexD.RdEnxS <= '1';
+ -- SouthStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- SouthStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process SouthSendWordxP;
+
+ -- WestSendWordxP : process (WestNativeMasterxD.DataxD,
+ -- WestNativeMasterxD.EmptyxS,
+ -- WestStatusSendWordxDP,
+ -- WestTXS2MxD.ReadyxS) is
+ -- begin -- process WestSendWordxP
+ -- WestTXM2SxD.DataxD <= (others => '0');
+ -- WestTXM2SxD.KeepxD <= (others => '1');
+ -- WestTXM2SxD.LastxS <= '0';
+ -- WestTXM2SxD.ValidxS <= '0';
+ -- WestNativeSlavexD.RdEnxS <= '0';
+ -- WestStatusSendWordxDN <= WestStatusSendWordxDP;
+
+ -- case WestStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (WestNativeMasterxD.EmptyxS = '0') and
+ -- (WestTXS2MxD.ReadyxS = '1') then
+ -- WestTXM2SxD.DataxD <= WestNativeMasterxD.DataxD;
+ -- WestTXM2SxD.LastxS <= '1';
+ -- WestTXM2SxD.ValidxS <= '1';
+ -- WestNativeSlavexD.RdEnxS <= '1';
+ -- WestStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- WestStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process WestSendWordxP;
+
+ -- NorthFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => NorthNativeSlavexD,
+ -- NativeMasterxDO => NorthNativeMasterxD);
+
+ -- EastFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => EastNativeSlavexD,
+ -- NativeMasterxDO => EastNativeMasterxD);
+
+ -- SouthFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => SouthNativeSlavexD,
+ -- NativeMasterxDO => SouthNativeMasterxD);
+
+ -- WestFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => WestNativeSlavexD,
+ -- NativeMasterxDO => WestNativeMasterxD);
+
+ -- end block TxFifoxB;
+
+ end block ZynqRegBankxB;
+
+ -- DebugxB : block is
+
+ -- -- RX Fifo reset 196 cycles
+ -- constant C_RX_FIFO_RST_DLY_TICKS : integer := 200;
+
+ -- type t_read_phy_states is (E_READ_PHY_IDLE, E_READ_PHY_S0, E_READ_PHY_S1, E_READ_PHY_S2);
+ -- type t_write_phy_states is (E_WRITE_PHY_IDLE, E_WRITE_PHY_W0, E_WRITE_PHY_W1,
+ -- E_WRITE_PHY_W2, E_WRITE_PHY_W3, E_WRITE_PHY_W4,
+ -- E_WRITE_PHY_W5, E_WRITE_PHY_W6, E_WRITE_PHY_W7);
+
+ -- -- North
+ -- signal NorthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal NorthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal NorthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- signal NorthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- -- East
+ -- signal EastReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal EastReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal EastWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- signal EastWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- -- South
+ -- signal SouthReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal SouthReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal SouthWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- signal SouthWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- -- West
+ -- signal WestReadPhyStatexDN : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal WestReadPhyStatexDP : t_read_phy_states := E_READ_PHY_IDLE;
+ -- signal WestWritePhyStatexDN : t_write_phy_states := E_WRITE_PHY_IDLE;
+ -- signal WestWritePhyStatexDP : t_write_phy_states := E_WRITE_PHY_IDLE;
+
+ -- attribute mark_debug : string;
+ -- attribute keep : string;
+ -- --
+ -- attribute mark_debug of NorthWritePhyStatexDP : signal is "true";
+ -- attribute keep of NorthWritePhyStatexDP : signal is "true";
+ -- -- attribute mark_debug of EastWritePhyStatexDP : signal is "true";
+ -- -- attribute keep of EastWritePhyStatexDP : signal is "true";
+ -- attribute mark_debug of SouthWritePhyStatexDP : signal is "true";
+ -- attribute keep of SouthWritePhyStatexDP : signal is "true";
+ -- -- attribute mark_debug of WestWritePhyStatexDP : signal is "true";
+ -- -- attribute keep of WestWritePhyStatexDP : signal is "true";
+ -- attribute mark_debug of NorthReadPhyStatexDP : signal is "true";
+ -- attribute keep of NorthReadPhyStatexDP : signal is "true";
+ -- -- attribute mark_debug of EastReadPhyStatexDP : signal is "true";
+ -- -- attribute keep of EastReadPhyStatexDP : signal is "true";
+ -- attribute mark_debug of SouthReadPhyStatexDP : signal is "true";
+ -- attribute keep of SouthReadPhyStatexDP : signal is "true";
+ -- -- attribute mark_debug of WestReadPhyStatexDP : signal is "true";
+ -- -- attribute keep of WestReadPhyStatexDP : signal is "true";
+
+ -- begin -- block DebugxB
+
+ -- -- RX Fifo reset 196 cycles
+ -- -- Clock and Resets
+ -- -- RX Fifo
+ -- NorthFifoResetxAS : RXResetxR.FifoResetxR.NorthxR <=
+ -- '1' when
+ -- (DebugRXFifoResetxR.NorthxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ -- '0';
+ -- EastFifoResetxAS : RXResetxR.FifoResetxR.EastxR <=
+ -- '1' when
+ -- (DebugRXFifoResetxR.EastxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ -- '0';
+ -- SouthFifoResetxAS : RXResetxR.FifoResetxR.SouthxR <=
+ -- '1' when
+ -- (DebugRXFifoResetxR.SouthxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ -- '0';
+ -- WestFifoResetxAS : RXResetxR.FifoResetxR.WestxR <=
+ -- '1' when
+ -- (DebugRXFifoResetxR.WestxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ -- '0';
+ -- -- Back pressure
+ -- NorthBackPressureResetxAS : RXResetxR.BackPressureResetxR.NorthxR <=
+ -- '1' when
+ -- (DebugBackPressureResetxR.NorthxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ -- (RXFifoResetDonexD.NorthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.NorthxS = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(0) = '0') else
+ -- '0';
+ -- EastBackPressureResetxAS : RXResetxR.BackPressureResetxR.EastxR <=
+ -- '1' when
+ -- (DebugBackPressureResetxR.EastxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ -- (RXFifoResetDonexD.EastxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.EastxS = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(1) = '0') else
+ -- '0';
+ -- SouthBackPressureResetxAS : RXResetxR.BackPressureResetxR.SouthxR <=
+ -- '1' when
+ -- (DebugBackPressureResetxR.SouthxR = '1') or
+ -- (RXFifoResetDonexD.SouthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.SouthxS = '0') or
+ -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(2) = '0') else
+ -- '0';
+ -- WestBackPressureResetxAS : RXResetxR.BackPressureResetxR.WestxR <=
+ -- '1' when
+ -- (DebugBackPressureResetxR.WestxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ -- (RXFifoResetDonexD.WestxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.WestxS = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(3) = '0') else
+ -- '0';
+
+ -- NorthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ -- AuroraStatusxD.ChannelUpxD(0),
+ -- AuroraStatusxD.LaneUpxD(0)(0),
+ -- DebugCounterResetxR.NorthxR,
+ -- RXFifoResetDoneDelayedxD.NorthxS,
+ -- RXFifoResetDonexD.NorthxS) is
+ -- begin -- process NorthUpdateRegxP
+ -- if (DebugCounterResetxR.NorthxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(0) = '0') or
+ -- (RXFifoResetDonexD.NorthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.NorthxS = '0') then
+ -- NorthReadPhyStatexDP <= E_READ_PHY_IDLE;
+ -- NorthWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ -- NorthDataCounterxDP <= (others => '0');
+ -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- NorthReadPhyStatexDP <= NorthReadPhyStatexDN;
+ -- NorthWritePhyStatexDP <= NorthWritePhyStatexDN;
+ -- NorthDataCounterxDP <= NorthDataCounterxDN;
+ -- end if;
+ -- end process NorthUpdateRegxP;
+
+ -- EastUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ -- AuroraStatusxD.ChannelUpxD(1),
+ -- AuroraStatusxD.LaneUpxD(1)(0),
+ -- DebugCounterResetxR.EastxR,
+ -- RXFifoResetDoneDelayedxD.EastxS,
+ -- RXFifoResetDonexD.EastxS) is
+ -- begin -- process EastUpdateRegxP
+ -- if (DebugCounterResetxR.EastxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(1) = '0') or
+ -- (RXFifoResetDonexD.EastxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.EastxS = '0') then
+ -- EastReadPhyStatexDP <= E_READ_PHY_IDLE;
+ -- EastWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ -- EastDataCounterxDP <= (others => '0');
+ -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- EastReadPhyStatexDP <= EastReadPhyStatexDN;
+ -- EastWritePhyStatexDP <= EastWritePhyStatexDN;
+ -- EastDataCounterxDP <= EastDataCounterxDN;
+ -- end if;
+ -- end process EastUpdateRegxP;
+
+ -- SouthUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ -- AuroraStatusxD.ChannelUpxD(2),
+ -- AuroraStatusxD.LaneUpxD(2)(0),
+ -- DebugCounterResetxR.SouthxR,
+ -- RXFifoResetDoneDelayedxD.SouthxS,
+ -- RXFifoResetDonexD.SouthxS) is
+ -- begin -- process SouthUpdateRegxP
+ -- if (DebugCounterResetxR.SouthxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(2) = '0') or
+ -- (RXFifoResetDonexD.SouthxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.SouthxS = '0') then
+ -- SouthReadPhyStatexDP <= E_READ_PHY_IDLE;
+ -- SouthWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ -- SouthDataCounterxDP <= (others => '0');
+ -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- SouthReadPhyStatexDP <= SouthReadPhyStatexDN;
+ -- SouthWritePhyStatexDP <= SouthWritePhyStatexDN;
+ -- SouthDataCounterxDP <= SouthDataCounterxDN;
+ -- end if;
+ -- end process SouthUpdateRegxP;
+
+ -- WestUpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ -- AuroraStatusxD.ChannelUpxD(3),
+ -- AuroraStatusxD.LaneUpxD(3)(0),
+ -- DebugCounterResetxR.WestxR,
+ -- RXFifoResetDoneDelayedxD.WestxS,
+ -- RXFifoResetDonexD.WestxS) is
+ -- begin -- process WestUpdateRegxP
+ -- if (DebugCounterResetxR.WestxR = '1') or
+ -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
+ -- (AuroraStatusxD.ChannelUpxD(3) = '0') or
+ -- (RXFifoResetDonexD.WestxS = '0') or
+ -- (RXFifoResetDoneDelayedxD.WestxS = '0') then
+ -- WestReadPhyStatexDP <= E_READ_PHY_IDLE;
+ -- WestWritePhyStatexDP <= E_WRITE_PHY_IDLE;
+ -- WestDataCounterxDP <= (others => '0');
+ -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- WestReadPhyStatexDP <= WestReadPhyStatexDN;
+ -- WestWritePhyStatexDP <= WestWritePhyStatexDN;
+ -- WestDataCounterxDP <= WestDataCounterxDN;
+ -- end if;
+ -- end process WestUpdateRegxP;
+
+ -- VioUserResetsxI : entity work.vio_user_resets
+ -- port map (
+ -- clk => AuroraClkMasterxC.UserClkxC,
+ -- probe_out0(0) => DebugCounterResetxR.NorthxR,
+ -- probe_out1(0) => DebugCounterResetxR.EastxR,
+ -- probe_out2(0) => DebugCounterResetxR.SouthxR,
+ -- probe_out3(0) => DebugCounterResetxR.WestxR,
+ -- probe_out4(0) => DebugBackPressureResetxR.NorthxR,
+ -- probe_out5(0) => DebugBackPressureResetxR.EastxR,
+ -- probe_out6(0) => DebugBackPressureResetxR.SouthxR,
+ -- probe_out7(0) => DebugBackPressureResetxR.WestxR,
+ -- probe_out8(0) => DebugRXFifoResetxR.NorthxR,
+ -- probe_out9(0) => DebugRXFifoResetxR.EastxR,
+ -- probe_out10(0) => DebugRXFifoResetxR.SouthxR,
+ -- probe_out11(0) => DebugRXFifoResetxR.WestxR);
+
+ -- VioStatusxI : entity work.vio_status
+ -- port map (
+ -- clk => AuroraClkMasterxC.UserClkxC,
+ -- -- North
+ -- probe_in0(0) => AuroraStatusxD.HardErrxD(0),
+ -- probe_in1(0) => AuroraStatusxD.SoftErrxD(0),
+ -- probe_in2(0) => AuroraStatusxD.FrameErrxD(0),
+ -- probe_in3 => AuroraStatusxD.LaneUpxD(0),
+ -- probe_in4(0) => AuroraStatusxD.ChannelUpxD(0),
+ -- probe_in5(0) => AuroraStatusxD.RXResetDoneOutxD(0),
+ -- probe_in6(0) => AuroraStatusxD.TXResetDoneOutxD(0),
+ -- -- East
+ -- probe_in7(0) => AuroraStatusxD.HardErrxD(1),
+ -- probe_in8(0) => AuroraStatusxD.SoftErrxD(1),
+ -- probe_in9(0) => AuroraStatusxD.FrameErrxD(1),
+ -- probe_in10 => AuroraStatusxD.LaneUpxD(1),
+ -- probe_in11(0) => AuroraStatusxD.ChannelUpxD(1),
+ -- probe_in12(0) => AuroraStatusxD.RXResetDoneOutxD(1),
+ -- probe_in13(0) => AuroraStatusxD.TXResetDoneOutxD(1),
+ -- -- South
+ -- probe_in14(0) => AuroraStatusxD.HardErrxD(2),
+ -- probe_in15(0) => AuroraStatusxD.SoftErrxD(2),
+ -- probe_in16(0) => AuroraStatusxD.FrameErrxD(2),
+ -- probe_in17 => AuroraStatusxD.LaneUpxD(2),
+ -- probe_in18(0) => AuroraStatusxD.ChannelUpxD(2),
+ -- probe_in19(0) => AuroraStatusxD.RXResetDoneOutxD(2),
+ -- probe_in20(0) => AuroraStatusxD.TXResetDoneOutxD(2),
+ -- -- West
+ -- probe_in21(0) => AuroraStatusxD.HardErrxD(3),
+ -- probe_in22(0) => AuroraStatusxD.SoftErrxD(3),
+ -- probe_in23(0) => AuroraStatusxD.FrameErrxD(3),
+ -- probe_in24 => AuroraStatusxD.LaneUpxD(3),
+ -- probe_in25(0) => AuroraStatusxD.ChannelUpxD(3),
+ -- probe_in26(0) => AuroraStatusxD.RXResetDoneOutxD(3),
+ -- probe_in27(0) => AuroraStatusxD.TXResetDoneOutxD(3));
+
+ -- NorthWriteTXPhyxP : process (NorthDataCounterxDP,
+ -- NorthTXS2MxD.ReadyxS,
+ -- NorthWritePhyStatexDP) is
+ -- begin -- process NorthWriteTXPhyxP
+ -- -- Default values
+ -- NorthWritePhyStatexDN <= NorthWritePhyStatexDP;
+ -- NorthDataCounterxDN <= NorthDataCounterxDP;
+ -- NorthTXM2SxD.DataxD <= (others => '0');
+ -- NorthTXM2SxD.KeepxD <= (others => '1');
+ -- NorthTXM2SxD.ValidxS <= '0';
+ -- NorthTXM2SxD.LastxS <= '0';
+
+ -- case NorthWritePhyStatexDP is
+ -- when E_WRITE_PHY_IDLE =>
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ -- when E_WRITE_PHY_W0 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W1;
+ -- end if;
+
+ -- when E_WRITE_PHY_W1 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W2;
+ -- end if;
+
+ -- when E_WRITE_PHY_W2 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W3;
+ -- end if;
+
+ -- when E_WRITE_PHY_W3 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W4;
+ -- end if;
+
+ -- when E_WRITE_PHY_W4 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W5;
+ -- end if;
+
+ -- when E_WRITE_PHY_W5 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W6;
+ -- end if;
+ -- when E_WRITE_PHY_W6 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W7;
+ -- end if;
+
+ -- when E_WRITE_PHY_W7 =>
+ -- NorthTXM2SxD.DataxD <= std_logic_vector(NorthDataCounterxDP);
+ -- NorthTXM2SxD.ValidxS <= '1';
+ -- NorthTXM2SxD.LastxS <= '1';
+
+ -- if NorthTXS2MxD.ReadyxS = '1' then
+ -- NorthWritePhyStatexDN <= E_WRITE_PHY_W0;
+ -- NorthDataCounterxDN <= NorthDataCounterxDP + 1;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+
+ -- end process NorthWriteTXPhyxP;
+
+ -- EastWriteTXPhyxP : process (EastDataCounterxDP,
+ -- EastTXS2MxD.ReadyxS,
+ -- EastWritePhyStatexDP) is
+ -- begin -- process EastWriteTXPhyxP
+ -- -- Default values
+ -- EastWritePhyStatexDN <= EastWritePhyStatexDP;
+ -- EastDataCounterxDN <= EastDataCounterxDP;
+ -- EastTXM2SxD.DataxD <= (others => '0');
+ -- EastTXM2SxD.KeepxD <= (others => '1');
+ -- EastTXM2SxD.ValidxS <= '0';
+ -- EastTXM2SxD.LastxS <= '0';
+
+ -- case EastWritePhyStatexDP is
+ -- when E_WRITE_PHY_IDLE =>
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ -- when E_WRITE_PHY_W0 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W1;
+ -- end if;
+
+ -- when E_WRITE_PHY_W1 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W2;
+ -- end if;
+
+ -- when E_WRITE_PHY_W2 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W3;
+ -- end if;
+
+ -- when E_WRITE_PHY_W3 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W4;
+ -- end if;
+
+ -- when E_WRITE_PHY_W4 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W5;
+ -- end if;
+
+ -- when E_WRITE_PHY_W5 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W6;
+ -- end if;
+
+ -- when E_WRITE_PHY_W6 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W7;
+ -- end if;
+
+ -- when E_WRITE_PHY_W7 =>
+ -- EastTXM2SxD.DataxD <= std_logic_vector(EastDataCounterxDP);
+ -- EastTXM2SxD.ValidxS <= '1';
+ -- EastTXM2SxD.LastxS <= '1';
+
+ -- if EastTXS2MxD.ReadyxS = '1' then
+ -- EastWritePhyStatexDN <= E_WRITE_PHY_W0;
+ -- EastDataCounterxDN <= EastDataCounterxDP + 1;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+
+ -- end process EastWriteTXPhyxP;
+
+ -- SouthWriteTXPhyxP : process (SouthDataCounterxDP,
+ -- SouthTXS2MxD.ReadyxS,
+ -- SouthWritePhyStatexDP) is
+ -- begin -- process SouthWriteTXPhyxP
+ -- -- Default values
+ -- SouthWritePhyStatexDN <= SouthWritePhyStatexDP;
+ -- SouthDataCounterxDN <= SouthDataCounterxDP;
+ -- SouthTXM2SxD.DataxD <= (others => '0');
+ -- SouthTXM2SxD.KeepxD <= (others => '1');
+ -- SouthTXM2SxD.ValidxS <= '0';
+ -- SouthTXM2SxD.LastxS <= '0';
+
+ -- case SouthWritePhyStatexDP is
+ -- when E_WRITE_PHY_IDLE =>
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ -- when E_WRITE_PHY_W0 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W1;
+ -- end if;
+
+ -- when E_WRITE_PHY_W1 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W2;
+ -- end if;
+
+ -- when E_WRITE_PHY_W2 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W3;
+ -- end if;
+
+ -- when E_WRITE_PHY_W3 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W4;
+ -- end if;
+
+ -- when E_WRITE_PHY_W4 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W5;
+ -- end if;
+
+ -- when E_WRITE_PHY_W5 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W6;
+ -- end if;
+
+ -- when E_WRITE_PHY_W6 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W7;
+ -- end if;
+
+ -- when E_WRITE_PHY_W7 =>
+ -- SouthTXM2SxD.DataxD <= std_logic_vector(SouthDataCounterxDP);
+ -- SouthTXM2SxD.ValidxS <= '1';
+ -- SouthTXM2SxD.LastxS <= '1';
+
+ -- if SouthTXS2MxD.ReadyxS = '1' then
+ -- SouthWritePhyStatexDN <= E_WRITE_PHY_W0;
+ -- SouthDataCounterxDN <= SouthDataCounterxDP + 1;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+
+ -- end process SouthWriteTXPhyxP;
+
+ -- WestWriteTXPhyxP : process (WestDataCounterxDP,
+ -- WestTXS2MxD.ReadyxS,
+ -- WestWritePhyStatexDP) is
+ -- begin -- process WestWriteTXPhyxP
+ -- -- Default values
+ -- WestWritePhyStatexDN <= WestWritePhyStatexDP;
+ -- WestDataCounterxDN <= WestDataCounterxDP;
+ -- WestTXM2SxD.DataxD <= (others => '0');
+ -- WestTXM2SxD.KeepxD <= (others => '1');
+ -- WestTXM2SxD.ValidxS <= '0';
+ -- WestTXM2SxD.LastxS <= '0';
+
+ -- case WestWritePhyStatexDP is
+ -- when E_WRITE_PHY_IDLE =>
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W0;
+
+ -- when E_WRITE_PHY_W0 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W1;
+ -- end if;
+
+ -- when E_WRITE_PHY_W1 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W2;
+ -- end if;
+
+ -- when E_WRITE_PHY_W2 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W3;
+ -- end if;
+
+ -- when E_WRITE_PHY_W3 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W4;
+ -- end if;
+
+ -- when E_WRITE_PHY_W4 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W5;
+ -- end if;
+
+ -- when E_WRITE_PHY_W5 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W6;
+ -- end if;
+
+ -- when E_WRITE_PHY_W6 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W7;
+ -- end if;
+
+ -- when E_WRITE_PHY_W7 =>
+ -- WestTXM2SxD.DataxD <= std_logic_vector(WestDataCounterxDP);
+ -- WestTXM2SxD.ValidxS <= '1';
+ -- WestTXM2SxD.LastxS <= '1';
+
+ -- if WestTXS2MxD.ReadyxS = '1' then
+ -- WestWritePhyStatexDN <= E_WRITE_PHY_W0;
+ -- WestDataCounterxDN <= WestDataCounterxDP + 1;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+
+ -- end process WestWriteTXPhyxP;
+
+ -- NorthReadRXPhyxP : process (NorthRXFifoStatusxD.ProgEmptyxS,
+ -- NorthRXFifoStatusxD.ProgFullxS,
+ -- NorthRXM2SxD.ValidxS,
+ -- NorthReadPhyStatexDP) is
+ -- begin -- process NorthReadRXPhyxP
+ -- -- Default value
+ -- NorthReadPhyStatexDN <= NorthReadPhyStatexDP;
+ -- NorthRXS2MxD.ReadyxS <= '0';
+
+ -- case NorthReadPhyStatexDP is
+ -- when E_READ_PHY_IDLE =>
+ -- if (NorthRXFifoStatusxD.ProgFullxS = '1') and
+ -- (NorthRXFifoStatusxD.ProgEmptyxS = '0') then
+ -- NorthReadPhyStatexDN <= E_READ_PHY_S0;
+ -- end if;
+
+ -- when E_READ_PHY_S0 =>
+ -- if NorthRXM2SxD.ValidxS = '1' then
+ -- NorthRXS2MxD.ReadyxS <= '1';
+ -- end if;
+
+ -- if (NorthRXFifoStatusxD.ProgFullxS = '0') and
+ -- (NorthRXFifoStatusxD.ProgEmptyxS = '1') then
+ -- NorthReadPhyStatexDN <= E_READ_PHY_IDLE;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+ -- end process NorthReadRXPhyxP;
+
+ -- EastReadRXPhyxP : process (EastRXFifoStatusxD.ProgEmptyxS,
+ -- EastRXFifoStatusxD.ProgFullxS,
+ -- EastRXM2SxD.ValidxS,
+ -- EastReadPhyStatexDP) is
+ -- begin -- process EastReadRXPhyxP
+ -- -- Default value
+ -- EastReadPhyStatexDN <= EastReadPhyStatexDP;
+ -- EastRXS2MxD.ReadyxS <= '0';
+
+ -- case EastReadPhyStatexDP is
+ -- when E_READ_PHY_IDLE =>
+ -- if (EastRXFifoStatusxD.ProgFullxS = '1') and
+ -- (EastRXFifoStatusxD.ProgEmptyxS = '0') then
+ -- EastReadPhyStatexDN <= E_READ_PHY_S0;
+ -- end if;
+
+ -- when E_READ_PHY_S0 =>
+ -- if EastRXM2SxD.ValidxS = '1' then
+ -- EastRXS2MxD.ReadyxS <= '1';
+ -- end if;
+
+ -- if (EastRXFifoStatusxD.ProgFullxS = '0') and
+ -- (EastRXFifoStatusxD.ProgEmptyxS = '1') then
+ -- EastReadPhyStatexDN <= E_READ_PHY_IDLE;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+ -- end process EastReadRXPhyxP;
+
+ -- SouthReadRXPhyxP : process (SouthRXFifoStatusxD.ProgEmptyxS,
+ -- SouthRXFifoStatusxD.ProgFullxS,
+ -- SouthRXM2SxD.ValidxS,
+ -- SouthReadPhyStatexDP) is
+ -- begin -- process SouthReadRXPhyxP
+ -- -- Default value
+ -- SouthReadPhyStatexDN <= SouthReadPhyStatexDP;
+ -- SouthRXS2MxD.ReadyxS <= '0';
+
+ -- case SouthReadPhyStatexDP is
+ -- when E_READ_PHY_IDLE =>
+ -- if (SouthRXFifoStatusxD.ProgFullxS = '1') and
+ -- (SouthRXFifoStatusxD.ProgEmptyxS = '0') then
+ -- SouthReadPhyStatexDN <= E_READ_PHY_S0;
+ -- end if;
+
+ -- when E_READ_PHY_S0 =>
+ -- if SouthRXM2SxD.ValidxS = '1' then
+ -- SouthRXS2MxD.ReadyxS <= '1';
+ -- end if;
+
+ -- if (SouthRXFifoStatusxD.ProgFullxS = '0') and
+ -- (SouthRXFifoStatusxD.ProgEmptyxS = '1') then
+ -- SouthReadPhyStatexDN <= E_READ_PHY_IDLE;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+ -- end process SouthReadRXPhyxP;
+
+ -- WestReadRXPhyxP : process (WestRXFifoStatusxD.ProgEmptyxS,
+ -- WestRXFifoStatusxD.ProgFullxS,
+ -- WestRXM2SxD.ValidxS,
+ -- WestReadPhyStatexDP) is
+ -- begin -- process WestReadRXPhyxP
+ -- -- Default value
+ -- WestReadPhyStatexDN <= WestReadPhyStatexDP;
+ -- WestRXS2MxD.ReadyxS <= '0';
+
+ -- case WestReadPhyStatexDP is
+ -- when E_READ_PHY_IDLE =>
+ -- if (WestRXFifoStatusxD.ProgFullxS = '1') and
+ -- (WestRXFifoStatusxD.ProgEmptyxS = '0') then
+ -- WestReadPhyStatexDN <= E_READ_PHY_S0;
+ -- end if;
+
+ -- when E_READ_PHY_S0 =>
+ -- if WestRXM2SxD.ValidxS = '1' then
+ -- WestRXS2MxD.ReadyxS <= '1';
+ -- end if;
+
+ -- if (WestRXFifoStatusxD.ProgFullxS = '0') and
+ -- (WestRXFifoStatusxD.ProgEmptyxS = '1') then
+ -- WestReadPhyStatexDN <= E_READ_PHY_IDLE;
+ -- end if;
+
+ -- when others => null;
+ -- end case;
+ -- end process WestReadRXPhyxP;
+
+ -- end block DebugxB;
+
+ end block ProgrammableLogicxB;
+
+end arch;
diff --git a/designs/vivado/scalp_firmware/2020.2/src/ipi_tcl/scalp_firmware_ipi.tcl b/designs/vivado/scalp_firmware/2020.2/src/ipi_tcl/scalp_firmware_ipi.tcl
new file mode 100644
index 0000000..e168716
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/ipi_tcl/scalp_firmware_ipi.tcl
@@ -0,0 +1 @@
+source "../../../../../../soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl"
\ No newline at end of file
diff --git a/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd
similarity index 87%
rename from designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
rename to designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd
index bbaed25..f763f92 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: tb_scalp_firmware - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_firmware
--
--- Last update: 2020-11-25 14:35:23
+-- Last update: 2021-01-15 09:27:32
--
---------------------------------------------------------------------------------
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/cdc_sync.vhd b/ips/hw/scalp_aurora_phy/src/hdl/cdc_sync.vhd
index 80b0490..ac4cd81 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/cdc_sync.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/cdc_sync.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: cdc_sync - behavioral
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: CDC Sync module
--
-- Last update: 2020-09-28
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/clock_module.vhd b/ips/hw/scalp_aurora_phy/src/hdl/clock_module.vhd
index ed6b79b..876e1c1 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/clock_module.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/clock_module.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: clock_module - rtl
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: Aurora clock module
--
-- Last update: 2020-09-28
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/gt_common.vhd b/ips/hw/scalp_aurora_phy/src/hdl/gt_common.vhd
index 6b1e628..5da6ae2 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/gt_common.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/gt_common.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: gt_common - rtl
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: Aurora GTP common
--
-- Last update: 2020-09-28
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/reset_logic.vhd b/ips/hw/scalp_aurora_phy/src/hdl/reset_logic.vhd
index 5936daf..b8d049f 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/reset_logic.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/reset_logic.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: reset_logic - rtl
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: Aurora reset logic module
--
-- Last update: 2020-09-28
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
index 30a18dd..04fd55c 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
@@ -12,10 +12,10 @@
--
-- Module Name: scalp_aurora_phy - arch
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: scalp_aurora_phy
--
--- Last update: 2020-11-25
+-- Last update: 2021-01-11
--
---------------------------------------------------------------------------------
@@ -223,33 +223,33 @@ architecture arch of scalp_aurora_phy is
signal WestFifoTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- attribute mark_debug of RXFifoResetDonexD : signal is "true";
- attribute keep of RXFifoResetDonexD : signal is "true";
- attribute mark_debug of RXFifoResetDoneDelayedxD : signal is "true";
- attribute keep of RXFifoResetDoneDelayedxD : signal is "true";
+ -- attribute mark_debug of RXFifoResetDonexD : signal is "true";
+ -- attribute keep of RXFifoResetDonexD : signal is "true";
+ -- attribute mark_debug of RXFifoResetDoneDelayedxD : signal is "true";
+ -- attribute keep of RXFifoResetDoneDelayedxD : signal is "true";
-- North
- attribute mark_debug of NorthTXM2SxD : signal is "true";
- attribute keep of NorthTXM2SxD : signal is "true";
- attribute mark_debug of NorthTXS2MxD : signal is "true";
- attribute keep of NorthTXS2MxD : signal is "true";
- attribute mark_debug of NorthRXM2SxD : signal is "true";
- attribute keep of NorthRXM2SxD : signal is "true";
- attribute mark_debug of NorthTXNFCM2SxD : signal is "true";
- attribute keep of NorthTXNFCM2SxD : signal is "true";
- attribute mark_debug of NorthTXNFCS2MxD : signal is "true";
- attribute keep of NorthTXNFCS2MxD : signal is "true";
- attribute mark_debug of NorthRXNFCM2SxD : signal is "true";
- attribute keep of NorthRXNFCM2SxD : signal is "true";
+ -- attribute mark_debug of NorthTXM2SxD : signal is "true";
+ -- attribute keep of NorthTXM2SxD : signal is "true";
+ -- attribute mark_debug of NorthTXS2MxD : signal is "true";
+ -- attribute keep of NorthTXS2MxD : signal is "true";
+ -- attribute mark_debug of NorthRXM2SxD : signal is "true";
+ -- attribute keep of NorthRXM2SxD : signal is "true";
+ -- attribute mark_debug of NorthTXNFCM2SxD : signal is "true";
+ -- attribute keep of NorthTXNFCM2SxD : signal is "true";
+ -- attribute mark_debug of NorthTXNFCS2MxD : signal is "true";
+ -- attribute keep of NorthTXNFCS2MxD : signal is "true";
+ -- attribute mark_debug of NorthRXNFCM2SxD : signal is "true";
+ -- attribute keep of NorthRXNFCM2SxD : signal is "true";
-- East
- -- attribute mark_debug of EastTXM2SxD : signal is "true";
- -- attribute keep of EastTXM2SxD : signal is "true";
- -- attribute mark_debug of EastTXS2MxD : signal is "true";
- -- attribute keep of EastTXS2MxD : signal is "true";
- -- attribute mark_debug of EastRXM2SxD : signal is "true";
- -- attribute keep of EastRXM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXM2SxD : signal is "true";
+ -- attribute keep of EastTXM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXS2MxD : signal is "true";
+ -- attribute keep of EastTXS2MxD : signal is "true";
+ -- attribute mark_debug of EastRXM2SxD : signal is "true";
+ -- attribute keep of EastRXM2SxD : signal is "true";
-- attribute mark_debug of EastTXNFCM2SxD : signal is "true";
-- attribute keep of EastTXNFCM2SxD : signal is "true";
-- attribute mark_debug of EastTXNFCS2MxD : signal is "true";
@@ -257,25 +257,25 @@ architecture arch of scalp_aurora_phy is
-- attribute mark_debug of EastRXNFCM2SxD : signal is "true";
-- attribute keep of EastRXNFCM2SxD : signal is "true";
-- South
- attribute mark_debug of SouthTXM2SxD : signal is "true";
- attribute keep of SouthTXM2SxD : signal is "true";
- attribute mark_debug of SouthTXS2MxD : signal is "true";
- attribute keep of SouthTXS2MxD : signal is "true";
- attribute mark_debug of SouthRXM2SxD : signal is "true";
- attribute keep of SouthRXM2SxD : signal is "true";
- attribute mark_debug of SouthTXNFCM2SxD : signal is "true";
- attribute keep of SouthTXNFCM2SxD : signal is "true";
- attribute mark_debug of SouthTXNFCS2MxD : signal is "true";
- attribute keep of SouthTXNFCS2MxD : signal is "true";
- attribute mark_debug of SouthRXNFCM2SxD : signal is "true";
- attribute keep of SouthRXNFCM2SxD : signal is "true";
+ -- attribute mark_debug of SouthTXM2SxD : signal is "true";
+ -- attribute keep of SouthTXM2SxD : signal is "true";
+ -- attribute mark_debug of SouthTXS2MxD : signal is "true";
+ -- attribute keep of SouthTXS2MxD : signal is "true";
+ -- attribute mark_debug of SouthRXM2SxD : signal is "true";
+ -- attribute keep of SouthRXM2SxD : signal is "true";
+ -- attribute mark_debug of SouthTXNFCM2SxD : signal is "true";
+ -- attribute keep of SouthTXNFCM2SxD : signal is "true";
+ -- attribute mark_debug of SouthTXNFCS2MxD : signal is "true";
+ -- attribute keep of SouthTXNFCS2MxD : signal is "true";
+ -- attribute mark_debug of SouthRXNFCM2SxD : signal is "true";
+ -- attribute keep of SouthRXNFCM2SxD : signal is "true";
-- West
- -- attribute mark_debug of WestTXM2SxD : signal is "true";
- -- attribute keep of WestTXM2SxD : signal is "true";
- -- attribute mark_debug of WestTXS2MxD : signal is "true";
- -- attribute keep of WestTXS2MxD : signal is "true";
- -- attribute mark_debug of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXM2SxD : signal is "true";
+ -- attribute keep of WestTXM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXS2MxD : signal is "true";
+ -- attribute keep of WestTXS2MxD : signal is "true";
+ -- attribute mark_debug of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
-- attribute mark_debug of WestTXNFCM2SxD : signal is "true";
-- attribute keep of WestTXNFCM2SxD : signal is "true";
-- attribute mark_debug of WestTXNFCS2MxD : signal is "true";
@@ -646,15 +646,15 @@ begin
signal AuroraPllLockedxS : std_ulogic := '0';
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
- attribute mark_debug of NorthRXFifoResetDoneStatexDP : signal is "true";
- attribute keep of NorthRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute mark_debug of NorthRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute keep of NorthRXFifoResetDoneStatexDP : signal is "true";
-- attribute mark_debug of EastRXFifoResetDoneStatexDP : signal is "true";
-- attribute keep of EastRXFifoResetDoneStatexDP : signal is "true";
- attribute mark_debug of SouthRXFifoResetDoneStatexDP : signal is "true";
- attribute keep of SouthRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute mark_debug of SouthRXFifoResetDoneStatexDP : signal is "true";
+ -- attribute keep of SouthRXFifoResetDoneStatexDP : signal is "true";
-- attribute mark_debug of WestRXFifoResetDoneStatexDP : signal is "true";
-- attribute keep of WestRXFifoResetDoneStatexDP : signal is "true";
@@ -907,15 +907,15 @@ begin
signal AxisFifoErrorxDP : t_axi4fifo_error := C_NO_AXI4_FIFO_ERROR;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- North
- attribute mark_debug of NorthNFCStatexDP : signal is "true";
- attribute keep of NorthNFCStatexDP : signal is "true";
- attribute mark_debug of NorthProgFullxSP : signal is "true";
- attribute keep of NorthProgFullxSP : signal is "true";
- attribute mark_debug of NorthProgEmptyxSP : signal is "true";
- attribute keep of NorthProgEmptyxSP : signal is "true";
+ -- attribute mark_debug of NorthNFCStatexDP : signal is "true";
+ -- attribute keep of NorthNFCStatexDP : signal is "true";
+ -- attribute mark_debug of NorthProgFullxSP : signal is "true";
+ -- attribute keep of NorthProgFullxSP : signal is "true";
+ -- attribute mark_debug of NorthProgEmptyxSP : signal is "true";
+ -- attribute keep of NorthProgEmptyxSP : signal is "true";
-- East
-- attribute mark_debug of EastNFCStatexDP : signal is "true";
-- attribute keep of EastNFCStatexDP : signal is "true";
@@ -924,12 +924,12 @@ begin
-- attribute mark_debug of EastProgEmptyxSP : signal is "true";
-- attribute keep of EastProgEmptyxSP : signal is "true";
-- South
- attribute mark_debug of SouthNFCStatexDP : signal is "true";
- attribute keep of SouthNFCStatexDP : signal is "true";
- attribute mark_debug of SouthProgFullxSP : signal is "true";
- attribute keep of SouthProgFullxSP : signal is "true";
- attribute mark_debug of SouthProgEmptyxSP : signal is "true";
- attribute keep of SouthProgEmptyxSP : signal is "true";
+ -- attribute mark_debug of SouthNFCStatexDP : signal is "true";
+ -- attribute keep of SouthNFCStatexDP : signal is "true";
+ -- attribute mark_debug of SouthProgFullxSP : signal is "true";
+ -- attribute keep of SouthProgFullxSP : signal is "true";
+ -- attribute mark_debug of SouthProgEmptyxSP : signal is "true";
+ -- attribute keep of SouthProgEmptyxSP : signal is "true";
-- West
-- attribute mark_debug of WestNFCStatexDP : signal is "true";
-- attribute keep of WestNFCStatexDP : signal is "true";
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy_wrapper.vhd b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy_wrapper.vhd
index 7fb810a..b529824 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy_wrapper.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy_wrapper.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: scalp_aurora_phy_wrapper - arch
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: scalp_aurora_phy_wrapper
--
-- Last update: 2020-11-10
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
index 631b220..cb8b351 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
@@ -12,6 +12,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT0_QPLLRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -22,28 +23,33 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -51,10 +57,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
@@ -92,12 +100,14 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -105,6 +115,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -136,10 +147,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXI_TX.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXI_RX.CLK_DOMAIN"/>
@@ -277,7 +290,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_7series">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">scalp_node</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.isv7gth">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.port7dmonitorout">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_coupling">AC</spirit:configurableElementValue>
@@ -377,7 +390,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
@@ -390,12 +403,12 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
@@ -411,7 +424,6 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDEST_WIDTH" xilinx:valueSource="constant"/>
@@ -463,6 +475,39 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Flow_Mode" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SupportLevel" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"s_axi_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"31"},"s_axi_tx_tkeep":{"direction":"in","physical_left":"0","physical_right":"3"},"s_axi_tx_tlast":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axi_nfc_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_nfc_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"3"},"s_axi_nfc_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axi_ufc_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_ufc_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"2"},"s_axi_ufc_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_rx_tdata":{"direction":"out","physical_left":"0","physical_right":"31"},"m_axi_rx_tkee
+p":{"direction":"out","physical_left":"0","physical_right":"3"},"m_axi_rx_tlast":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_ufc_rx_tdata":{"direction":"out","physical_left":"0","physical_right":"31"},"m_axi_ufc_rx_tkeep":{"direction":"out","physical_left":"0","physical_right":"3"},"m_axi_ufc_rx_tlast":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_ufc_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"hard_err":{"direction":"out","physical_left":"0","physical_right":"0"},"soft_err":{"direction":"out","physical_left":"0","physical_right":"0"},"frame_err":{"direction":"out","physical_left":"0","physical_right":"0"},"channel_up":{"direction":"out","physical_left":"0","physical_right":"0"},"lane_up":{"direction":"out","physical_left":"0","physical_right":"0"},"txp":{"direction":"out","physical_left":"0","physical_right":"0"},"txn":{"direction":
+"out","physical_left":"0","physical_right":"0"},"reset":{"direction":"in","physical_left":"0","physical_right":"0"},"gt_reset":{"direction":"in","physical_left":"0","physical_right":"0"},"loopback":{"direction":"in","physical_left":"2","physical_right":"0"},"rxp":{"direction":"in","physical_left":"0","physical_right":"0"},"rxn":{"direction":"in","physical_left":"0","physical_right":"0"},"drpclk_in":{"direction":"in","physical_left":"0","physical_right":"0"},"drpaddr_in":{"direction":"in","physical_left":"8","physical_right":"0"},"drpen_in":{"direction":"in","physical_left":"0","physical_right":"0"},"drpdi_in":{"direction":"in","physical_left":"15","physical_right":"0"},"drprdy_out":{"direction":"out","physical_left":"0","physical_right":"0"},"drpdo_out":{"direction":"out","physical_left":"15","physical_right":"0"},"drpwe_in":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axi_nfc_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_nfc_rx_tdata
+":{"direction":"out","physical_left":"0","physical_right":"3"},"power_down":{"direction":"in","physical_left":"0","physical_right":"0"},"tx_lock":{"direction":"out","physical_left":"0","physical_right":"0"},"tx_resetdone_out":{"direction":"out","physical_left":"0","physical_right":"0"},"rx_resetdone_out":{"direction":"out","physical_left":"0","physical_right":"0"},"link_reset_out":{"direction":"out","physical_left":"0","physical_right":"0"},"gt_common_reset_out":{"direction":"out","physical_left":"0","physical_right":"0"},"gt0_pll0outclk_in":{"direction":"in","physical_left":"0","physical_right":"0"},"gt0_pll1outclk_in":{"direction":"in","physical_left":"0","physical_right":"0"},"gt0_pll0outrefclk_in":{"direction":"in","physical_left":"0","physical_right":"0"},"gt0_pll1outrefclk_in":{"direction":"in","physical_left":"0","physical_right":"0"},"gt0_pll0refclklost_in":{"direction":"in","physical_left":"0","physical_right":"0"},"quad1_common_lock_in":{"direction":"in","physical_left":"0",
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+p","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RX_RESETDONE_OUT":{"physical_name":"rx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"SOFT_ERR":{"physical_name":"soft_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_LOCK":{"physical_name":"tx_lock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_RESETDONE_OUT":{"physical_name":"tx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CORE_CONTROL":{"vlnv":"xilinx.com:display_aurora:core_control_in:1.0","abstraction_type":"xilinx.com:display_aurora:core_control_in_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"LOOPBACK":{"physical_name":"loopback","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0"},"PLL_NOT_LOCKED":{"physical_name":"pll_not_locked","physical_left":"0","physical_right":"0","logi
+cal_left":"0","logical_right":"0"},"Power_down":{"physical_name":"power_down","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_TX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX_rtl:1.0","mode":"master","parameters":{},"port_maps":{"TXN":{"physical_name":"txn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TXP":{"physical_name":"txp","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_RX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"RXN":{"physical_name":"rxn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RXP":{"physical_name":"rxp","physical_left":"0","physical_right":"0","logica
+l_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
index 7222490..d112a38 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
@@ -12,6 +12,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT0_QPLLRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -22,28 +23,33 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -51,10 +57,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
@@ -92,12 +100,14 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -105,6 +115,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -136,10 +147,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXI_TX.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXI_RX.CLK_DOMAIN"/>
@@ -277,7 +290,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_7series">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">scalp_node</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.isv7gth">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.port7dmonitorout">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_coupling">AC</spirit:configurableElementValue>
@@ -377,7 +390,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
@@ -390,12 +403,12 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
@@ -411,7 +424,6 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDEST_WIDTH" xilinx:valueSource="constant"/>
@@ -463,6 +475,39 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Flow_Mode" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SupportLevel" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"s_axi_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"31"},"s_axi_tx_tkeep":{"direction":"in","physical_left":"0","physical_right":"3"},"s_axi_tx_tlast":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axi_nfc_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_nfc_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"3"},"s_axi_nfc_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axi_ufc_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_ufc_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"2"},"s_axi_ufc_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_rx_tdata":{"direction":"out","physical_left":"0","physical_right":"31"},"m_axi_rx_tkee
+p":{"direction":"out","physical_left":"0","physical_right":"3"},"m_axi_rx_tlast":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_ufc_rx_tdata":{"direction":"out","physical_left":"0","physical_right":"31"},"m_axi_ufc_rx_tkeep":{"direction":"out","physical_left":"0","physical_right":"3"},"m_axi_ufc_rx_tlast":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_ufc_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"hard_err":{"direction":"out","physical_left":"0","physical_right":"0"},"soft_err":{"direction":"out","physical_left":"0","physical_right":"0"},"frame_err":{"direction":"out","physical_left":"0","physical_right":"0"},"channel_up":{"direction":"out","physical_left":"0","physical_right":"0"},"lane_up":{"direction":"out","physical_left":"0","physical_right":"0"},"txp":{"direction":"out","physical_left":"0","physical_right":"0"},"txn":{"direction":
+"out","physical_left":"0","physical_right":"0"},"reset":{"direction":"in","physical_left":"0","physical_right":"0"},"gt_reset":{"direction":"in","physical_left":"0","physical_right":"0"},"loopback":{"direction":"in","physical_left":"2","physical_right":"0"},"rxp":{"direction":"in","physical_left":"0","physical_right":"0"},"rxn":{"direction":"in","physical_left":"0","physical_right":"0"},"drpclk_in":{"direction":"in","physical_left":"0","physical_right":"0"},"drpaddr_in":{"direction":"in","physical_left":"8","physical_right":"0"},"drpen_in":{"direction":"in","physical_left":"0","physical_right":"0"},"drpdi_in":{"direction":"in","physical_left":"15","physical_right":"0"},"drprdy_out":{"direction":"out","physical_left":"0","physical_right":"0"},"drpdo_out":{"direction":"out","physical_left":"15","physical_right":"0"},"drpwe_in":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axi_nfc_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_nfc_rx_tdata
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+physical_right":"0","logical_left":"15","logical_right":"0"},"DO":{"physical_name":"drpdo_out","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0"},"DRDY":{"physical_name":"drprdy_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"DWE":{"physical_name":"drpwe_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CORE_STATUS":{"vlnv":"xilinx.com:display_aurora:core_status_out:1.0","abstraction_type":"xilinx.com:display_aurora:core_status_out_rtl:1.0","mode":"master","parameters":{},"port_maps":{"CHANNEL_UP":{"physical_name":"channel_up","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"FRAME_ERR":{"physical_name":"frame_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"HARD_ERR":{"physical_name":"hard_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"LANE_UP":{"physical_name":"lane_u
+p","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RX_RESETDONE_OUT":{"physical_name":"rx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"SOFT_ERR":{"physical_name":"soft_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_LOCK":{"physical_name":"tx_lock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_RESETDONE_OUT":{"physical_name":"tx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CORE_CONTROL":{"vlnv":"xilinx.com:display_aurora:core_control_in:1.0","abstraction_type":"xilinx.com:display_aurora:core_control_in_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"LOOPBACK":{"physical_name":"loopback","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0"},"PLL_NOT_LOCKED":{"physical_name":"pll_not_locked","physical_left":"0","physical_right":"0","logi
+cal_left":"0","logical_right":"0"},"Power_down":{"physical_name":"power_down","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_TX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX_rtl:1.0","mode":"master","parameters":{},"port_maps":{"TXN":{"physical_name":"txn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TXP":{"physical_name":"txp","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_RX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"RXN":{"physical_name":"rxn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RXP":{"physical_name":"rxp","physical_left":"0","physical_right":"0","logica
+l_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
index 00a1133..5d4c0db 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
@@ -12,6 +12,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT0_QPLLRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -22,28 +23,33 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -51,10 +57,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
@@ -92,12 +100,14 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -105,6 +115,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -136,10 +147,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXI_TX.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXI_RX.CLK_DOMAIN"/>
@@ -277,7 +290,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_7series">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">scalp_node</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.isv7gth">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.port7dmonitorout">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_coupling">AC</spirit:configurableElementValue>
@@ -377,7 +390,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
@@ -390,12 +403,12 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
@@ -411,7 +424,6 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDEST_WIDTH" xilinx:valueSource="constant"/>
@@ -463,6 +475,39 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Flow_Mode" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SupportLevel" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"s_axi_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"31"},"s_axi_tx_tkeep":{"direction":"in","physical_left":"0","physical_right":"3"},"s_axi_tx_tlast":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axi_nfc_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_nfc_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"3"},"s_axi_nfc_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axi_ufc_tx_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axi_ufc_tx_tdata":{"direction":"in","physical_left":"0","physical_right":"2"},"s_axi_ufc_tx_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_rx_tdata":{"direction":"out","physical_left":"0","physical_right":"31"},"m_axi_rx_tkee
+p":{"direction":"out","physical_left":"0","physical_right":"3"},"m_axi_rx_tlast":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_ufc_rx_tdata":{"direction":"out","physical_left":"0","physical_right":"31"},"m_axi_ufc_rx_tkeep":{"direction":"out","physical_left":"0","physical_right":"3"},"m_axi_ufc_rx_tlast":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axi_ufc_rx_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"hard_err":{"direction":"out","physical_left":"0","physical_right":"0"},"soft_err":{"direction":"out","physical_left":"0","physical_right":"0"},"frame_err":{"direction":"out","physical_left":"0","physical_right":"0"},"channel_up":{"direction":"out","physical_left":"0","physical_right":"0"},"lane_up":{"direction":"out","physical_left":"0","physical_right":"0"},"txp":{"direction":"out","physical_left":"0","physical_right":"0"},"txn":{"direction":
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+alue":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"init_clk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT0_DRP_IF":{"vlnv":"xilinx.com:interface:drp:1.0","abstraction_type":"xilinx.com:interface:drp_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"DADDR":{"physical_name":"drpaddr_in","physical_left":"8","physical_right":"0","logical_left":"8","logical_right":"0"},"DEN":{"physical_name":"drpen_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"DI":{"physical_name":"drpdi_in","physical_left":"15","
+physical_right":"0","logical_left":"15","logical_right":"0"},"DO":{"physical_name":"drpdo_out","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0"},"DRDY":{"physical_name":"drprdy_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"DWE":{"physical_name":"drpwe_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CORE_STATUS":{"vlnv":"xilinx.com:display_aurora:core_status_out:1.0","abstraction_type":"xilinx.com:display_aurora:core_status_out_rtl:1.0","mode":"master","parameters":{},"port_maps":{"CHANNEL_UP":{"physical_name":"channel_up","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"FRAME_ERR":{"physical_name":"frame_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"HARD_ERR":{"physical_name":"hard_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"LANE_UP":{"physical_name":"lane_u
+p","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RX_RESETDONE_OUT":{"physical_name":"rx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"SOFT_ERR":{"physical_name":"soft_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_LOCK":{"physical_name":"tx_lock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_RESETDONE_OUT":{"physical_name":"tx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CORE_CONTROL":{"vlnv":"xilinx.com:display_aurora:core_control_in:1.0","abstraction_type":"xilinx.com:display_aurora:core_control_in_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"LOOPBACK":{"physical_name":"loopback","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0"},"PLL_NOT_LOCKED":{"physical_name":"pll_not_locked","physical_left":"0","physical_right":"0","logi
+cal_left":"0","logical_right":"0"},"Power_down":{"physical_name":"power_down","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_TX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX_rtl:1.0","mode":"master","parameters":{},"port_maps":{"TXN":{"physical_name":"txn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TXP":{"physical_name":"txp","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_RX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"RXN":{"physical_name":"rxn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RXP":{"physical_name":"rxp","physical_left":"0","physical_right":"0","logica
+l_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
diff --git a/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci b/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
index 99ec90d..16af9a1 100644
--- a/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
+++ b/ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
@@ -12,6 +12,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRPCLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT0_QPLLRESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -22,28 +23,33 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK1_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK2_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -51,10 +57,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.CLK_DOMAIN"/>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INIT_DIFF_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
@@ -92,12 +100,14 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYNC_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYS_RESET_OUT.INSERT_VIP">0</spirit:configurableElementValue>
@@ -105,6 +115,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_OUT_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue>
@@ -136,10 +147,12 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UFC_S_AXI_TX.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_CLK_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.USER_DATA_M_AXI_RX.CLK_DOMAIN"/>
@@ -277,7 +290,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ins_loss_nyq">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_7series">true</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">scalp_node</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.isv7gth">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.port7dmonitorout">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.rx_coupling">AC</spirit:configurableElementValue>
@@ -377,7 +390,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
@@ -390,12 +403,12 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
@@ -411,7 +424,6 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_M_AXI_RX.TUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TKEEP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TLAST" xilinx:valueSource="constant"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TREADY" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.HAS_TSTRB" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.NFC_S_AXI_TX.TDEST_WIDTH" xilinx:valueSource="constant"/>
@@ -463,6 +475,39 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Flow_Mode" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SupportLevel" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
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+user"}]},"port_maps":{"CLK":{"physical_name":"gt_refclk1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"gt_drp_clk_in":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"GT0_DRP_IF:GT1_DRP_IF:GT2_DRP_IF:GT3_DRP_IF:GT4_DRP_IF:GT5_DRP_IF:GT6_DRP_IF:GT7_DRP_IF:GT8_DRP_IF:GT9_DRP_IF:GT10_DRP_IF:GT11_DRP_IF:GT12_DRP_IF:GT13_DRP_IF:GT14_DRP_IF:GT15_DRP_IF"},{"value_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"res
+olve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"drpclk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"drpclk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"GT0_DRP:GT1_DRP:GT2_DRP:GT3_DRP:GT4_DRP:GT5_DRP:GT6_DRP:GT7_DRP:GT8_DRP:GT9_DRP:GT10_DRP:GT11_DRP:GT12_DRP:GT13_DRP:GT14_DRP:GT15_DRP"},{"value_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"v
+alue":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"init_clk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT0_DRP_IF":{"vlnv":"xilinx.com:interface:drp:1.0","abstraction_type":"xilinx.com:interface:drp_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"DADDR":{"physical_name":"drpaddr_in","physical_left":"8","physical_right":"0","logical_left":"8","logical_right":"0"},"DEN":{"physical_name":"drpen_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"DI":{"physical_name":"drpdi_in","physical_left":"15","
+physical_right":"0","logical_left":"15","logical_right":"0"},"DO":{"physical_name":"drpdo_out","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0"},"DRDY":{"physical_name":"drprdy_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"DWE":{"physical_name":"drpwe_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CORE_STATUS":{"vlnv":"xilinx.com:display_aurora:core_status_out:1.0","abstraction_type":"xilinx.com:display_aurora:core_status_out_rtl:1.0","mode":"master","parameters":{},"port_maps":{"CHANNEL_UP":{"physical_name":"channel_up","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"FRAME_ERR":{"physical_name":"frame_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"HARD_ERR":{"physical_name":"hard_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"LANE_UP":{"physical_name":"lane_u
+p","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RX_RESETDONE_OUT":{"physical_name":"rx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"SOFT_ERR":{"physical_name":"soft_err","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_LOCK":{"physical_name":"tx_lock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TX_RESETDONE_OUT":{"physical_name":"tx_resetdone_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"CORE_CONTROL":{"vlnv":"xilinx.com:display_aurora:core_control_in:1.0","abstraction_type":"xilinx.com:display_aurora:core_control_in_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"LOOPBACK":{"physical_name":"loopback","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0"},"PLL_NOT_LOCKED":{"physical_name":"pll_not_locked","physical_left":"0","physical_right":"0","logi
+cal_left":"0","logical_right":"0"},"Power_down":{"physical_name":"power_down","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_TX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_TX_rtl:1.0","mode":"master","parameters":{},"port_maps":{"TXN":{"physical_name":"txn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TXP":{"physical_name":"txp","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"GT_SERIAL_RX":{"vlnv":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX:1.0","abstraction_type":"xilinx.com:display_aurora:GT_Serial_Transceiver_Pins_RX_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"RXN":{"physical_name":"rxn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"RXP":{"physical_name":"rxp","physical_left":"0","physical_right":"0","logica
+l_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
diff --git a/ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd b/ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd
index 92adcb5..d6a251a 100644
--- a/ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd
+++ b/ips/hw/scalp_aurora_phy/src/sim/tb_scalp_aurora_phy.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_aurora_phy - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_aurora_phy
--
--- Last update: 2020-09-28 09:02:33
+-- Last update: 2021-01-15 09:08:10
--
---------------------------------------------------------------------------------
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
index a02841e..e2920c9 100644
--- a/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: scalp_aurora_phy_rx_fifo - arch
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: scalp_aurora_phy_rx_fifo
--
-- Last update: 2020-11-18
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci b/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
index 5888e06..b74e7ea 100644
--- a/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
@@ -26,6 +26,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
@@ -45,6 +46,7 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_RSTIF.INSERT_VIP">0</spirit:configurableElementValue>
@@ -91,7 +93,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
@@ -104,12 +106,12 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
@@ -135,6 +137,17 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROG_FULL_THRESH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"s_axis_aresetn":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axis_aclk":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axis_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axis_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axis_tdata":{"direction":"in","physical_left":"31","physical_right":"0"},"s_axis_tkeep":{"direction":"in","physical_left":"3","physical_right":"0"},"s_axis_tlast":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axis_aclk":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axis_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axis_tready":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axis_tdata":{"direction":"out","physical_left":"31","physical_right":"0"},"m_axis_tkeep":{"direction":"out","physical_left":"3","physical_right":"0"},"m_axis_tlast":{"direction":"out","physical_left":"0","physical_
+right":"0"},"axis_wr_data_count":{"direction":"out","physical_left":"31","physical_right":"0"},"axis_rd_data_count":{"direction":"out","physical_left":"31","physical_right":"0"},"prog_empty":{"direction":"out","physical_left":"0","physical_right":"0"},"prog_full":{"direction":"out","physical_left":"0","physical_right":"0"}},"interfaces":{"S_AXIS":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"slave","parameters":{"TDATA_NUM_BYTES":[{"value":"4"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"TDEST_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"TID_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"TUSER_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TREADY":[{"value":"1"},{"value_src":"default"},{"value_permission":"user"},{"r
+esolve_type":"generated"}],"HAS_TSTRB":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TKEEP":[{"value":"1"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TLAST":[{"value":"1"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"LAYERED_METADATA":[{"value":"undef"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"TDATA":{"physical_name":"s_axis_tdata","physical_left":"31","physical_right":"
+0","logical_left":"31","logical_right":"0"},"TKEEP":{"physical_name":"s_axis_tkeep","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0"},"TLAST":{"physical_name":"s_axis_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TREADY":{"physical_name":"s_axis_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TVALID":{"physical_name":"s_axis_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"M_AXIS":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"master","parameters":{"TDATA_NUM_BYTES":[{"value":"4"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"TDEST_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"TID_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}]
+,"TUSER_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TREADY":[{"value":"1"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TSTRB":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TKEEP":[{"value":"1"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TLAST":[{"value":"1"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"LAYERED_METADATA":[{"value":"undef"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"IN
+SERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"TDATA":{"physical_name":"m_axis_tdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0"},"TKEEP":{"physical_name":"m_axis_tkeep","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0"},"TLAST":{"physical_name":"m_axis_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TREADY":{"physical_name":"m_axis_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TVALID":{"physical_name":"m_axis_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"S_RSTIF":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"POLARITY":[{"value":"ACTIVE_LOW"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":
+"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"RST":{"physical_name":"s_axis_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"S_CLKIF":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"S_AXIS"},{"value_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"
+},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"s_axis_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"M_CLKIF":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"M_AXIS"},{"value_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""
+},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"m_axis_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/sim/tb_scalp_aurora_phy_rx_fifo.vhd b/ips/hw/scalp_aurora_phy_rx_fifo/src/sim/tb_scalp_aurora_phy_rx_fifo.vhd
index d5c8fc6..dd8c069 100644
--- a/ips/hw/scalp_aurora_phy_rx_fifo/src/sim/tb_scalp_aurora_phy_rx_fifo.vhd
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/sim/tb_scalp_aurora_phy_rx_fifo.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_aurora_phy_rx_fifo - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_aurora_phy_rx_fifo
--
--- Last update: 2020-11-07 08:30:46
+-- Last update: 2021-01-15 08:48:31
--
---------------------------------------------------------------------------------
diff --git a/ips/hw/scalp_axi4lite/component.xml b/ips/hw/scalp_axi4lite/component.xml
index dc75ae1..5b01f61 100644
--- a/ips/hw/scalp_axi4lite/component.xml
+++ b/ips/hw/scalp_axi4lite/component.xml
@@ -3,7 +3,7 @@
<spirit:vendor>hepia.hesge.ch</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>scalp_axi4lite</spirit:name>
- <spirit:version>1.0</spirit:version>
+ <spirit:version>1.2</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>InterruptxSI</spirit:name>
@@ -276,7 +276,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>53aa3a87</spirit:value>
+ <spirit:value>01369ae3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -292,7 +292,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>53aa3a87</spirit:value>
+ <spirit:value>01369ae3</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -770,7 +770,7 @@
<spirit:file>
<spirit:name>src/hdl/scalp_axi4lite.vhd</spirit:name>
<spirit:userFileType>vhdlSource-2008</spirit:userFileType>
- <spirit:userFileType>CHECKSUM_d16a227c</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_61969ead</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -791,14 +791,14 @@
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>xgui/scalp_axi4lite_v1_0.tcl</spirit:name>
+ <spirit:name>xgui/scalp_axi4lite_v1_2.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_e83bd4c5</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
- <spirit:description>scalp_axi4lite_v1_0</spirit:description>
+ <spirit:description>scalp_axi4lite_v1_2</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_AXI4_ARADDR_SIZE</spirit:name>
@@ -874,11 +874,11 @@
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>scalp_axi4lite_v1_0</xilinx:displayName>
+ <xilinx:displayName>scalp_axi4lite_v1_2</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:vendorDisplayName>Hepia</xilinx:vendorDisplayName>
- <xilinx:coreRevision>3</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2020-11-08T08:07:27Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>5</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2021-01-14T10:34:15Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@661d7be7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3770d293_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
@@ -913,13 +913,37 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@4ec6e2b5_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5f71c732_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ea4c95a_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@70272d0c_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5fa291f1_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a07fa9f_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11690020_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@aebca06_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5edf9aac_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@76659ea0_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@51f6c6a4_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@73612d84_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@225dd10f_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1b66f08f_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@21eda8cb_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@724118a_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@64479442_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@14bd97a_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@44c35679_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7967c609_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4468364e_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5fed8f55_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@74255795_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2b370660_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@657e9787_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@ccc16e7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6053c4e4_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_axi4lite</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
- <xilinx:xilinxVersion>2019.2</xilinx:xilinxVersion>
+ <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b913313a"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="5bb05b05"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4322a235"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="01c45ba3"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="302dc023"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="2709f17e"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="cedefa4e"/>
diff --git a/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite.vhd b/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite.vhd
index f74e046..c9d9c41 100644
--- a/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite.vhd
+++ b/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite.vhd
@@ -12,10 +12,10 @@
--
-- Module Name: scalp_axi4lite - arch
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: scalp_axi4lite
--
--- Last update: 2020-11-08
+-- Last update: 2021-01-11
--
---------------------------------------------------------------------------------
@@ -141,6 +141,31 @@ architecture arch of scalp_axi4lite is
ValidxSO : out std_logic);
end component scalp_axi4lite_rd_chan;
+ -- Signals
+ signal WrDataxD : std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrAddrxD : std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_logic := '0';
+ signal RdDataxD : std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdAddrxD : std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_logic := '0';
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ attribute mark_debug of WrDataxD : signal is "true";
+ attribute keep of WrDataxD : signal is "true";
+ attribute mark_debug of WrAddrxD : signal is "true";
+ attribute keep of WrAddrxD : signal is "true";
+ attribute mark_debug of WrValidxS : signal is "true";
+ attribute keep of WrValidxS : signal is "true";
+ attribute mark_debug of RdDataxD : signal is "true";
+ attribute keep of RdDataxD : signal is "true";
+ attribute mark_debug of RdAddrxD : signal is "true";
+ attribute keep of RdAddrxD : signal is "true";
+ attribute mark_debug of RdValidxS : signal is "true";
+ attribute keep of RdValidxS : signal is "true";
+
begin -- architecture rtl
-- Asynchronous statements
@@ -157,6 +182,18 @@ begin -- architecture rtl
assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
report "AWADDR and ADDR vectors must be the same" severity failure;
+ EntityIOxB : block is
+ begin -- block EntityIOxB
+
+ WrDataxAS : WrDataxDO <= WrDataxD;
+ WrAddrxAS : WrAddrxDO <= WrAddrxD;
+ WrValidxAS : WrValidxSO <= WrValidxS;
+ RdDataxAS : RdDataxD <= RdDataxDI;
+ RdAddrxAS : RdAddrxDO <= RdAddrxD;
+ RdValidxAS : RdValidxSO <= RdValidxS;
+
+ end block EntityIOxB;
+
InterruptxB : block is
begin -- block InterruptxB
@@ -195,9 +232,9 @@ begin -- architecture rtl
SAxiBValidxSO => SAxiBValidxSO,
SAxiBReadyxSI => SAxiBReadyxSI,
-- Signal for Writing in a Register Bank
- DataxDO => WrDataxDO,
- AddrxDO => WrAddrxDO,
- ValidxSO => WrValidxSO);
+ DataxDO => WrDataxD,
+ AddrxDO => WrAddrxD,
+ ValidxSO => WrValidxS);
ScalpAxi4LiteRdChanxI : entity work.scalp_axi4lite_rd_chan
generic map (
@@ -220,9 +257,9 @@ begin -- architecture rtl
SAxiRValidxSO => SAxiRValidxSO,
SAxiRReadyxSI => SAxiRReadyxSI,
-- Signal for Reading in a Register Bank
- DataxDI => RdDataxDI,
- AddrxDO => RdAddrxDO,
- ValidxSO => RdValidxSO);
+ DataxDI => RdDataxD,
+ AddrxDO => RdAddrxD,
+ ValidxSO => RdValidxS);
end block ScalpAxi4LitexB;
diff --git a/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_rd_chan.vhd b/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_rd_chan.vhd
index 4026e86..2cc01a5 100644
--- a/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_rd_chan.vhd
+++ b/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_rd_chan.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: scalp_axi4lite_rd_chan - behavioural
-- Target Device: All
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: AXI4 Lite Read Channel Slave Side
--
-- Last update: 2020-11-08
diff --git a/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_wr_chan.vhd b/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_wr_chan.vhd
index 4f0a870..11b8323 100644
--- a/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_wr_chan.vhd
+++ b/ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_wr_chan.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: scalp_axi4lite_wr_chan - behavioural
-- Target Device: All
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: AXI4 Lite Write Channel Slave Side
--
-- Last update: 2020-11-08
diff --git a/ips/hw/scalp_axi4lite/src/sim/tb_scalp_axi4lite.vhd b/ips/hw/scalp_axi4lite/src/sim/tb_scalp_axi4lite.vhd
index 5a61f73..2b9cf88 100644
--- a/ips/hw/scalp_axi4lite/src/sim/tb_scalp_axi4lite.vhd
+++ b/ips/hw/scalp_axi4lite/src/sim/tb_scalp_axi4lite.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_axi4lite - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_axi4lite
--
--- Last update: 2020-11-08 07:53:10
+-- Last update: 2021-01-14 11:26:35
--
---------------------------------------------------------------------------------
diff --git a/ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_1.tcl b/ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_1.tcl
new file mode 100644
index 0000000..f9f3a79
--- /dev/null
+++ b/ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_1.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
diff --git a/ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_2.tcl b/ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_2.tcl
new file mode 100644
index 0000000..f9f3a79
--- /dev/null
+++ b/ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_2.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
diff --git a/ips/hw/scalp_design_aurora_clk/src/hdl/scalp_design_aurora_clk.vhd b/ips/hw/scalp_design_aurora_clk/src/hdl/scalp_design_aurora_clk.vhd
new file mode 100644
index 0000000..ed50183
--- /dev/null
+++ b/ips/hw/scalp_design_aurora_clk/src/hdl/scalp_design_aurora_clk.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_design_aurora_clk - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_design_aurora_clk
+--
+-- Last update: 2021-01-15 08:32:18
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scalp_design_aurora_clk is
+end scalp_design_aurora_clk;
+
+
+architecture arch of scalp_design_aurora_clk is
+
+begin
+
+end arch;
diff --git a/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci b/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
index 6a3f451..d55a593 100644
--- a/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
+++ b/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
@@ -21,18 +21,21 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT2.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
@@ -41,12 +44,14 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:configurableElementValue>
@@ -652,7 +657,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
@@ -665,12 +670,12 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
@@ -713,6 +718,13 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMARY_PORT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"reset":{"direction":"in","physical_left":"0","physical_right":"0"},"PSSysClkxCI":{"direction":"in","physical_left":"0","physical_right":"0"},"InitClkxCO":{"direction":"out","physical_left":"0","physical_right":"0"},"DrpClkxCO":{"direction":"out","physical_left":"0","physical_right":"0"},"PllLockedxSO":{"direction":"out","physical_left":"0","physical_right":"0"}},"interfaces":{"reset":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"POLARITY":[{"value":"ACTIVE_HIGH"},{"value_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"BOARD.ASSOCIATED_PARAM":[{"value":"RESET_BOARD_INTERFACE"},{"value_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"RST":{"physical_name":"reset","physical_left":"0","physical_right":"0","logical_left
+":"0","logical_right":"0"}}},"clock_CLK_IN1":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_BUSIF":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}],"BOARD.ASSOCIATED_PARAM":[{"value":"CLK_IN1_BOARD
+_INTERFACE"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"immediate"}]},"port_maps":{"CLK_IN1":{"physical_name":"PSSysClkxCI","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"clock_CLK_OUT1":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_BUSIF":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"valu
+e_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK_OUT1":{"physical_name":"InitClkxCO","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"clock_CLK_OUT2":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_BUSIF":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"
+ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK_OUT2":{"physical_name":"DrpClkxCO","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
diff --git a/ips/hw/scalp_design_aurora_clk/src/sim/tb_scalp_design_aurora_clk.vhd b/ips/hw/scalp_design_aurora_clk/src/sim/tb_scalp_design_aurora_clk.vhd
index 5534336..4210c33 100644
--- a/ips/hw/scalp_design_aurora_clk/src/sim/tb_scalp_design_aurora_clk.vhd
+++ b/ips/hw/scalp_design_aurora_clk/src/sim/tb_scalp_design_aurora_clk.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_design_aurora_clk - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_design_aurora_clk
--
--- Last update: 2020-10-13 12:46:49
+-- Last update: 2021-01-15 08:32:18
--
---------------------------------------------------------------------------------
diff --git a/ips/hw/scalp_design_debug/src/hdl/scalp_design_debug.vhd b/ips/hw/scalp_design_debug/src/hdl/scalp_design_debug.vhd
new file mode 100644
index 0000000..06add09
--- /dev/null
+++ b/ips/hw/scalp_design_debug/src/hdl/scalp_design_debug.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_design_debug - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_design_debug
+--
+-- Last update: 2021-01-15 08:39:29
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scalp_design_debug is
+end scalp_design_debug;
+
+
+architecture arch of scalp_design_debug is
+
+begin
+
+end arch;
diff --git a/ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci b/ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
index 3661301..92b2b4a 100644
--- a/ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
+++ b/ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
@@ -13,15 +13,16 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_IN">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_OUT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">12</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
@@ -793,7 +794,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_axi_cnt_ctrl</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
@@ -811,18 +812,23 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_IN" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_IN3_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_IN6_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_IN9_WIDTH" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"clk":{"direction":"in","physical_left":"0","physical_right":"0"},"probe_out0":{"direction":"out","physical_left":"0","physical_right":"0"}},"interfaces":{"signal_clock":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_BUSIF":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_V
+IP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
diff --git a/ips/hw/scalp_design_debug/src/sim/tb_scalp_design_debug.vhd b/ips/hw/scalp_design_debug/src/sim/tb_scalp_design_debug.vhd
index 27fe043..c133834 100644
--- a/ips/hw/scalp_design_debug/src/sim/tb_scalp_design_debug.vhd
+++ b/ips/hw/scalp_design_debug/src/sim/tb_scalp_design_debug.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_design_debug - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_design_debug
--
--- Last update: 2020-10-13 12:39:40
+-- Last update: 2021-01-15 08:39:29
--
---------------------------------------------------------------------------------
diff --git a/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd b/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd
index db22a70..3a96d0e 100644
--- a/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd
+++ b/ips/hw/scalp_packet_fifo_wrapper/src/hdl/scalp_packet_fifo_wrapper.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: scalp_packet_fifo_wrapper - arch
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: scalp_packet_fifo_wrapper
--
-- Last update: 2020-11-08
diff --git a/ips/hw/scalp_packet_fifo_wrapper/src/sim/tb_scalp_packet_fifo_wrapper.vhd b/ips/hw/scalp_packet_fifo_wrapper/src/sim/tb_scalp_packet_fifo_wrapper.vhd
index 3bc1884..3508f49 100644
--- a/ips/hw/scalp_packet_fifo_wrapper/src/sim/tb_scalp_packet_fifo_wrapper.vhd
+++ b/ips/hw/scalp_packet_fifo_wrapper/src/sim/tb_scalp_packet_fifo_wrapper.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_packet_fifo_wrapper - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_packet_fifo_wrapper
--
--- Last update: 2020-11-08 10:31:02
+-- Last update: 2021-01-15 08:44:59
--
---------------------------------------------------------------------------------
diff --git a/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd b/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
index 005d0a2..45e2f64 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: AXI Stream to Scalp Packet converter.
--
--- Last update: 2020-11-30
+-- Last update: 2020-12-22
--
---------------------------------------------------------------------------------
library ieee;
@@ -123,63 +123,72 @@ begin -- architecture behavioral
ScalpAxiss2mxAS : ScalpAxiss2mxDO <= ScalpAxiss2mxD;
end block EntityIOxB;
- RandomReadyxP : process is
- variable SeedB1xD : integer := 999;
- variable SeedB2xD : integer := 999;
- variable MinCyclesxD : integer := 1;
- variable MaxCyclesxD : integer := 3;
- variable WaitingCyclesxD : integer := 0;
- variable MinValRealxD : real := 0.0;
- variable MaxValReadxD : real := 1.0;
- variable RandomValuexD : real := 0.0;
- variable ThresholdxD : real := 0.3;
- variable RandxD : real := 0.0;
+ RandomReadyxG : if C_SCALP_RANDOM_READY = true generate
- -- Random Integer Value
- impure function scalp_rand_int (
- MinValxD : integer;
- MaxValxD : integer)
- return integer is
- variable RandxD : real;
- begin -- function scalp_rand_int
- uniform(SeedB1xD, SeedB2xD, RandxD);
- return integer(round(RandxD * real(MaxValxD - MinValxD + 1) + real(MinValxD) - 0.5));
- end function scalp_rand_int;
+ RandomReadyxP : process is
+ variable SeedB1xD : integer := 999;
+ variable SeedB2xD : integer := 999;
+ variable MinCyclesxD : integer := 1;
+ variable MaxCyclesxD : integer := 3;
+ variable WaitingCyclesxD : integer := 0;
+ variable MinValRealxD : real := 0.0;
+ variable MaxValReadxD : real := 1.0;
+ variable RandomValuexD : real := 0.0;
+ variable ThresholdxD : real := 0.3;
+ variable RandxD : real := 0.0;
- -- Random Real Value
- impure function scalp_rand_real (
- MinValxD : real;
- MaxValxD : real)
- return real is
- variable RandxD : real;
- begin -- function scalp_rand_real
- uniform(SeedB1xD, SeedB2xD, RandxD);
- return RandxD * (MaxValxD - MinValxD) + MinValxD;
- end function scalp_rand_real;
+ -- Random Integer Value
+ impure function scalp_rand_int (
+ MinValxD : integer;
+ MaxValxD : integer)
+ return integer is
+ variable RandxD : real;
+ begin -- function scalp_rand_int
+ uniform(SeedB1xD, SeedB2xD, RandxD);
+ return integer(round(RandxD * real(MaxValxD - MinValxD + 1) + real(MinValxD) - 0.5));
+ end function scalp_rand_int;
- begin -- process RandomReadyxP
- -- Axis ReadyxS Default Value
- ScalpAxiss2mxD.ReadyxS <= '1';
- ReadyxS <= '1';
+ -- Random Real Value
+ impure function scalp_rand_real (
+ MinValxD : real;
+ MaxValxD : real)
+ return real is
+ variable RandxD : real;
+ begin -- function scalp_rand_real
+ uniform(SeedB1xD, SeedB2xD, RandxD);
+ return RandxD * (MaxValxD - MinValxD) + MinValxD;
+ end function scalp_rand_real;
- if C_SCALP_RANDOM_READY = true then
- RandomValuexD := scalp_rand_real(MinValRealxD, MaxValReadxD);
+ begin -- process RandomReadyxP
+ -- Axis ReadyxS Default Value
+ ScalpAxiss2mxD.ReadyxS <= '1';
+ ReadyxS <= '1';
- if RandomValuexD < ThresholdxD then
- ScalpAxiss2mxD.ReadyxS <= '0';
- ReadyxS <= '0';
- else
- ScalpAxiss2mxD.ReadyxS <= '1';
- ReadyxS <= '1';
+ if C_SCALP_RANDOM_READY = true then
+ RandomValuexD := scalp_rand_real(MinValRealxD, MaxValReadxD);
+
+ if RandomValuexD < ThresholdxD then
+ ScalpAxiss2mxD.ReadyxS <= '0';
+ ReadyxS <= '0';
+ else
+ ScalpAxiss2mxD.ReadyxS <= '1';
+ ReadyxS <= '1';
+ end if;
end if;
- end if;
- WaitingCyclesxD := scalp_rand_int(MinCyclesxD, MaxCyclesxD);
+ WaitingCyclesxD := scalp_rand_int(MinCyclesxD, MaxCyclesxD);
+
+ for i in 0 to (WaitingCyclesxD - 1) loop
+ wait until rising_edge(SysClkxCI);
+ end loop; -- i
+ end process RandomReadyxP;
+
+ elsif C_SCALP_RANDOM_READY = false generate
+
+ ScalpAxiss2mReadyxAS : ScalpAxiss2mxD.ReadyxS <= '1';
+ ReadyxAS : ReadyxS <= '1';
- for i in 0 to (WaitingCyclesxD - 1) loop
- wait until rising_edge(SysClkxCI);
- end loop; -- i
- end process RandomReadyxP;
+ end generate RandomReadyxG;
StateMachineUpdateRegxP : process (SysClkxCI, SysRstxRNAI) is
begin -- process StateMachineUpdateRegxP
diff --git a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
index 282bb64..5150dc1 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2018.2
-- Description: Scalp Miscellanous
--
--- Last update: 2020-11-30
+-- Last update: 2020-12-07
--
---------------------------------------------------------------------------------
library ieee;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router.vhd b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
index 9f02514..65a192e 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router (NoC).
--
--- Last update: 2020-11-30
+-- Last update: 2020-12-21
--
---------------------------------------------------------------------------------
library ieee;
@@ -117,19 +117,19 @@ architecture rtl of scalp_router is
-- Signals
-- Scalp Router
-- Local Router Network Address
- signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
+ signal LocNetAddrxD : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
-- Axi4 Stream Interfaces
- signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
- signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
- signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal RXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal RXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
+ signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
+ signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
-- Scalp QoS Vectors
- signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
+ signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
-- Axi4 Stream Cross-Links with Neighborhood
- signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
- signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal RXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal RXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
+ signal TXAxi4m2sLinksxD : t_axi4m2s_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_M2S));
+ signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => C_NO_AXI4_S2M));
---------------------------------------------------------------------------
-- For Simulation With Vivado Only
-- Axi4 Stream Cross-Links with Neighborhood
@@ -139,11 +139,35 @@ architecture rtl of scalp_router is
-- signal TXAxi4s2mLinksxD : t_axi4s2m_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_SIM_AXISS2M_VECTOR);
---------------------------------------------------------------------------
-- Scalp Booking Vectors
- signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsInxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal BookingVectorsOutxD : t_scalp_booking_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
-- Scalp Scheduler Ack Vectors
- signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
- signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsInxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ signal SchedulerAckVectorsOutxD : t_scalp_scheduler_ack_vector_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0)((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0) := (others => (others => '0'));
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of LocNetAddrxD : signal is "true";
+ -- attribute keep of LocNetAddrxD : signal is "true";
+ -- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
+ -- attribute keep of RXAxism2sVectorxD : signal is "true";
+ -- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of RXAxiss2mVectorxD : signal is "true";
+ -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
+ -- attribute keep of TXAxism2sVectorxD : signal is "true";
+ -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+ -- attribute keep of TXAxiss2mVectorxD : signal is "true";
+ -- attribute mark_debug of QoSVectorxD : signal is "true";
+ -- attribute keep of QoSVectorxD : signal is "true";
+ -- attribute mark_debug of BookingVectorsInxD : signal is "true";
+ -- attribute keep of BookingVectorsInxD : signal is "true";
+ -- attribute mark_debug of BookingVectorsOutxD : signal is "true";
+ -- attribute keep of BookingVectorsOutxD : signal is "true";
+ -- attribute mark_debug of SchedulerAckVectorsInxD : signal is "true";
+ -- attribute keep of SchedulerAckVectorsInxD : signal is "true";
+ -- attribute mark_debug of SchedulerAckVectorsOutxD : signal is "true";
+ -- attribute keep of SchedulerAckVectorsOutxD : signal is "true";
begin -- architecture rtl
diff --git a/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd b/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd
index 7363468..4f0d7b3 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_sp_to_axis.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Packet to AXI Stream converter.
--
--- Last update: 2020-11-30
+-- Last update: 2021-01-11
--
---------------------------------------------------------------------------------
library ieee;
@@ -112,6 +112,31 @@ architecture behavioral of scalp_sp_to_axis is
-- Others
signal ScalpRdyxS : std_ulogic := '0';
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of ScalpAxism2sxD : signal is "true";
+ -- attribute keep of ScalpAxism2sxD : signal is "true";
+ -- attribute mark_debug of ScalpAxiss2mxD : signal is "true";
+ -- attribute keep of ScalpAxiss2mxD : signal is "true";
+ -- attribute mark_debug of ScalpPacketStatexDP : signal is "true";
+ -- attribute keep of ScalpPacketStatexDP : signal is "true";
+ -- attribute mark_debug of ScalpPacketStatexDN : signal is "true";
+ -- attribute keep of ScalpPacketStatexDN : signal is "true";
+ -- attribute mark_debug of ScalpPacketCntxDP : signal is "true";
+ -- attribute keep of ScalpPacketCntxDP : signal is "true";
+ -- attribute mark_debug of ScalpPacketValidxS : signal is "true";
+ -- attribute keep of ScalpPacketValidxS : signal is "true";
+ -- attribute mark_debug of ScalpPacketxD : signal is "true";
+ -- attribute keep of ScalpPacketxD : signal is "true";
+ -- attribute mark_debug of DataxDP : signal is "true";
+ -- attribute keep of DataxDP : signal is "true";
+ -- attribute mark_debug of DataxDN : signal is "true";
+ -- attribute keep of DataxDN : signal is "true";
+ -- attribute mark_debug of ScalpRdyxS : signal is "true";
+ -- attribute keep of ScalpRdyxS : signal is "true";
+
begin -- architecture behavioral
EntityIOxB : block is
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/.prompt_colors.tcl
index dff4d5a..034497e 100644
--- a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-09-28 09:02:33
+# Last update: 2021-01-15 09:08:10
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
similarity index 88%
rename from ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
rename to ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
index 60d5f1d..f328ff8 100755
--- a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
+++ b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/clean_prj_scalp_aurora_phy.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-09-28 09:02:33
+# Last update: 2021-01-15 09:08:10
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
similarity index 86%
rename from ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
rename to ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
index 99846ad..14dc0bb 100755
--- a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
+++ b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-28 09:02:33
+# Last update: 2021-01-15 09:08:10
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
similarity index 77%
rename from ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
rename to ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
index fe0b514..182c757 100644
--- a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
+++ b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_aurora_phy'
#
-# Last update: 2020-09-28 09:02:33
+# Last update: 2021-01-15 09:08:10
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -66,10 +66,8 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
- #add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file
-
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -78,11 +76,10 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
- read_ip $comp_src_dir/ip_core/north_channel/north_channel.xci
- read_ip $comp_src_dir/ip_core/south_channel/south_channel.xci
- read_ip $comp_src_dir/ip_core/west_channel/west_channel.xci
- read_ip $comp_src_dir/ip_core/east_channel/east_channel.xci
+ read_ip $comp_src_dir/ip_core/north_channel/north_channel.xci
+read_ip $comp_src_dir/ip_core/south_channel/south_channel.xci
+read_ip $comp_src_dir/ip_core/west_channel/west_channel.xci
+read_ip $comp_src_dir/ip_core/east_channel/east_channel.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
@@ -136,7 +133,6 @@ foreach j $vhdl_sim_file_list {
print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
@@ -158,29 +154,6 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
- set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
- add_files -norecurse $vhdl_pkg_file_list
- foreach j $vhdl_pkg_file_list {
- set_property file_type {VHDL 2008} [get_files $j]
- print_status "VHDL 2008 mode configured for the file $j" "OK"
- set_property is_enabled true [get_files $j]
- }
- set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
- add_files -norecurse $vhdl_pkg_file_list
- foreach j $vhdl_pkg_file_list {
- set_property file_type {VHDL 2008} [get_files $j]
- print_status "VHDL 2008 mode configured for the file $j" "OK"
- set_property is_enabled true [get_files $j]
- }
- set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
- add_files -norecurse $vhdl_pkg_file_list
- foreach j $vhdl_pkg_file_list {
- set_property file_type {VHDL 2008} [get_files $j]
- print_status "VHDL 2008 mode configured for the file $j" "OK"
- set_property is_enabled true [get_files $j]
- }
-}
print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK"
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
similarity index 85%
rename from ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
rename to ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
index 9b40ac5..98b0a71 100755
--- a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
+++ b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/open_prj_scalp_aurora_phy.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-28 09:02:33
+# Last update: 2021-01-15 09:08:10
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/utils.tcl
rename to ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/utils.tcl
index 43a6191..f0dfbb9 100644
--- a/ips/vivado/scalp_aurora_phy/2019.2/lin64/.scripts/utils.tcl
+++ b/ips/vivado/scalp_aurora_phy/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-09-28 09:02:33
+# Last update: 2021-01-15 09:08:10
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy/2019.2/lin64/setup.sh b/ips/vivado/scalp_aurora_phy/2020.2/lin64/setup.sh
similarity index 91%
rename from ips/vivado/scalp_aurora_phy/2019.2/lin64/setup.sh
rename to ips/vivado/scalp_aurora_phy/2020.2/lin64/setup.sh
index bb46716..6266bea 100755
--- a/ips/vivado/scalp_aurora_phy/2019.2/lin64/setup.sh
+++ b/ips/vivado/scalp_aurora_phy/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-09-28 09:02:33
+# Last update: 2021-01-15 09:08:10
#
##################################################################################
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/src/ipi_tcl/scalp_design_aurora_clk_ipi.tcl b/ips/vivado/scalp_aurora_phy/2020.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl
similarity index 100%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/src/ipi_tcl/scalp_design_aurora_clk_ipi.tcl
rename to ips/vivado/scalp_aurora_phy/2020.2/src/ipi_tcl/scalp_aurora_phy_ipi.tcl
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/.prompt_colors.tcl
index cc7b6c6..f693cac 100644
--- a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-11-07 08:30:46
+# Last update: 2021-01-15 08:48:31
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh
similarity index 89%
rename from ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh
index 291a1d5..dc9da5a 100755
--- a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-11-07 08:30:46
+# Last update: 2021-01-15 08:48:31
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh
similarity index 86%
rename from ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh
index 17e5639..d01e067 100755
--- a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-07 08:30:46
+# Last update: 2021-01-15 08:48:31
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl
similarity index 94%
rename from ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl
index c3eb878..27905d1 100644
--- a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_aurora_phy_rx_fifo'
#
-# Last update: 2020-11-07 08:30:46
+# Last update: 2021-01-15 08:48:31
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -67,8 +67,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
# add IPs source file
-
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -77,8 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
- read_ip $comp_src_dir/ip_core/axis_data_fifo/axis_data_fifo.xci
+ read_ip $comp_src_dir/ip_core/axis_data_fifo/axis_data_fifo.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh
similarity index 86%
rename from ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh
index a1a7840..84f6319 100755
--- a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-07 08:30:46
+# Last update: 2021-01-15 08:48:31
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/utils.tcl
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/utils.tcl
index 6a82a59..23cb46e 100644
--- a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/utils.tcl
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-11-07 08:30:46
+# Last update: 2021-01-15 08:48:31
#
##################################################################################
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/setup.sh b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/setup.sh
similarity index 91%
rename from ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/setup.sh
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/setup.sh
index d0c15e0..3b93426 100755
--- a/ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/setup.sh
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-11-07 08:30:46
+# Last update: 2021-01-15 08:48:31
#
##################################################################################
diff --git a/ips/vivado/scalp_design_debug/2019.2/src/ipi_tcl/scalp_design_debug_ipi.tcl b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/src/ipi_tcl/scalp_aurora_phy_rx_fifo_ipi.tcl
similarity index 100%
rename from ips/vivado/scalp_design_debug/2019.2/src/ipi_tcl/scalp_design_debug_ipi.tcl
rename to ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/src/ipi_tcl/scalp_aurora_phy_rx_fifo_ipi.tcl
diff --git a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/.prompt_colors.tcl
index 31e5e7a..9ff3819 100644
--- a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-11-08 07:53:10
+# Last update: 2021-01-14 11:26:35
#
##################################################################################
diff --git a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh
similarity index 88%
rename from ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh
rename to ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh
index 54e8688..22578ca 100755
--- a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh
+++ b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-11-08 07:53:10
+# Last update: 2021-01-14 11:26:35
#
##################################################################################
diff --git a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.sh b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/create_prj_scalp_axi4lite.sh
similarity index 86%
rename from ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.sh
rename to ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/create_prj_scalp_axi4lite.sh
index fa8771e..80706d6 100755
--- a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.sh
+++ b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/create_prj_scalp_axi4lite.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-08 07:53:10
+# Last update: 2021-01-14 11:26:35
#
##################################################################################
diff --git a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl
similarity index 95%
rename from ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl
rename to ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl
index 8e711e5..2c82cfa 100644
--- a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl
+++ b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_axi4lite'
#
-# Last update: 2020-11-08 07:53:10
+# Last update: 2021-01-14 11:26:35
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -67,8 +67,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
# add IPs source file
-
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -77,8 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
-
+
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
diff --git a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/open_prj_scalp_axi4lite.sh b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/open_prj_scalp_axi4lite.sh
similarity index 85%
rename from ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/open_prj_scalp_axi4lite.sh
rename to ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/open_prj_scalp_axi4lite.sh
index 89d4f93..0eae140 100755
--- a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/open_prj_scalp_axi4lite.sh
+++ b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/open_prj_scalp_axi4lite.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-08 07:53:10
+# Last update: 2021-01-14 11:26:35
#
##################################################################################
diff --git a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/utils.tcl
rename to ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/utils.tcl
index 2d0fe9d..d18f562 100644
--- a/ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/utils.tcl
+++ b/ips/vivado/scalp_axi4lite/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-11-08 07:53:10
+# Last update: 2021-01-14 11:26:35
#
##################################################################################
diff --git a/ips/vivado/scalp_axi4lite/2019.2/lin64/setup.sh b/ips/vivado/scalp_axi4lite/2020.2/lin64/setup.sh
similarity index 91%
rename from ips/vivado/scalp_axi4lite/2019.2/lin64/setup.sh
rename to ips/vivado/scalp_axi4lite/2020.2/lin64/setup.sh
index 0575831..32946e0 100755
--- a/ips/vivado/scalp_axi4lite/2019.2/lin64/setup.sh
+++ b/ips/vivado/scalp_axi4lite/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-11-08 07:53:10
+# Last update: 2021-01-14 11:26:35
#
##################################################################################
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/src/ipi_tcl/scalp_packet_fifo_wrapper_ipi.tcl b/ips/vivado/scalp_axi4lite/2020.2/src/ipi_tcl/scalp_axi4lite_ipi.tcl
similarity index 100%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/src/ipi_tcl/scalp_packet_fifo_wrapper_ipi.tcl
rename to ips/vivado/scalp_axi4lite/2020.2/src/ipi_tcl/scalp_axi4lite_ipi.tcl
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/.prompt_colors.tcl
index e98c7ec..aa12107 100644
--- a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_aurora_clk
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-10-13 12:46:49
+# Last update: 2021-01-15 08:32:18
#
##################################################################################
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/clean_prj_scalp_design_aurora_clk.sh b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/clean_prj_scalp_design_aurora_clk.sh
similarity index 89%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/clean_prj_scalp_design_aurora_clk.sh
rename to ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/clean_prj_scalp_design_aurora_clk.sh
index 80cb689..c7c2b1c 100755
--- a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/clean_prj_scalp_design_aurora_clk.sh
+++ b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/clean_prj_scalp_design_aurora_clk.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_aurora_clk
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-10-13 12:46:49
+# Last update: 2021-01-15 08:32:18
#
##################################################################################
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.sh b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.sh
similarity index 86%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.sh
rename to ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.sh
index 0694401..1562878 100755
--- a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.sh
+++ b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_aurora_clk
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-10-13 12:46:49
+# Last update: 2021-01-15 08:32:18
#
##################################################################################
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.tcl b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.tcl
similarity index 92%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.tcl
rename to ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.tcl
index 08479a8..5ecacc6 100644
--- a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.tcl
+++ b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/create_prj_scalp_design_aurora_clk.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_aurora_clk
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_design_aurora_clk'
#
-# Last update: 2020-10-13 12:46:49
+# Last update: 2021-01-15 08:32:18
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -66,10 +66,8 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
- #add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file
-
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -78,8 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
- read_ip $comp_src_dir/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
+ read_ip $comp_src_dir/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/open_prj_scalp_design_aurora_clk.sh b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/open_prj_scalp_design_aurora_clk.sh
similarity index 86%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/open_prj_scalp_design_aurora_clk.sh
rename to ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/open_prj_scalp_design_aurora_clk.sh
index b0dd339..f86d9e3 100755
--- a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/open_prj_scalp_design_aurora_clk.sh
+++ b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/open_prj_scalp_design_aurora_clk.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_aurora_clk
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-10-13 12:46:49
+# Last update: 2021-01-15 08:32:18
#
##################################################################################
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/utils.tcl
rename to ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/utils.tcl
index 932a8d0..6a9c44f 100644
--- a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/.scripts/utils.tcl
+++ b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_aurora_clk
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-10-13 12:46:49
+# Last update: 2021-01-15 08:32:18
#
##################################################################################
diff --git a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/setup.sh b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/setup.sh
similarity index 91%
rename from ips/vivado/scalp_design_aurora_clk/2019.2/lin64/setup.sh
rename to ips/vivado/scalp_design_aurora_clk/2020.2/lin64/setup.sh
index c43620f..f7d8eee 100755
--- a/ips/vivado/scalp_design_aurora_clk/2019.2/lin64/setup.sh
+++ b/ips/vivado/scalp_design_aurora_clk/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_aurora_clk
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-10-13 12:46:49
+# Last update: 2021-01-15 08:32:18
#
##################################################################################
diff --git a/ips/vivado/scalp_router/2019.2/src/ipi_tcl/scalp_router_ipi.tcl b/ips/vivado/scalp_design_aurora_clk/2020.2/src/ipi_tcl/scalp_design_aurora_clk_ipi.tcl
similarity index 100%
rename from ips/vivado/scalp_router/2019.2/src/ipi_tcl/scalp_router_ipi.tcl
rename to ips/vivado/scalp_design_aurora_clk/2020.2/src/ipi_tcl/scalp_design_aurora_clk_ipi.tcl
diff --git a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/.prompt_colors.tcl
index f32777c..afe6219 100644
--- a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_debug
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-10-13 12:39:40
+# Last update: 2021-01-15 08:39:29
#
##################################################################################
diff --git a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/clean_prj_scalp_design_debug.sh b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/clean_prj_scalp_design_debug.sh
similarity index 89%
rename from ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/clean_prj_scalp_design_debug.sh
rename to ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/clean_prj_scalp_design_debug.sh
index 643a5ba..c7efacf 100755
--- a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/clean_prj_scalp_design_debug.sh
+++ b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/clean_prj_scalp_design_debug.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_debug
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-10-13 12:39:40
+# Last update: 2021-01-15 08:39:29
#
##################################################################################
diff --git a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/create_prj_scalp_design_debug.sh b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/create_prj_scalp_design_debug.sh
similarity index 86%
rename from ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/create_prj_scalp_design_debug.sh
rename to ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/create_prj_scalp_design_debug.sh
index 1d0123c..f3ec18b 100755
--- a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/create_prj_scalp_design_debug.sh
+++ b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/create_prj_scalp_design_debug.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_debug
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-10-13 12:39:40
+# Last update: 2021-01-15 08:39:29
#
##################################################################################
diff --git a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/create_prj_scalp_design_debug.tcl b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/create_prj_scalp_design_debug.tcl
similarity index 90%
rename from ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/create_prj_scalp_design_debug.tcl
rename to ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/create_prj_scalp_design_debug.tcl
index 4adaba6..031b139 100644
--- a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/create_prj_scalp_design_debug.tcl
+++ b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/create_prj_scalp_design_debug.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_debug
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_design_debug'
#
-# Last update: 2020-10-13 12:39:40
+# Last update: 2021-01-15 08:39:29
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -66,10 +66,8 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
- #add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file
-
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -78,10 +76,9 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
- read_ip $comp_src_dir/ip_core/vio_status/vio_status.xci
- read_ip $comp_src_dir/ip_core/data_counter/data_counter.xci
- read_ip $comp_src_dir/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
+ read_ip $comp_src_dir/ip_core/vio_status/vio_status.xci
+read_ip $comp_src_dir/ip_core/data_counter/data_counter.xci
+read_ip $comp_src_dir/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
diff --git a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/open_prj_scalp_design_debug.sh b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/open_prj_scalp_design_debug.sh
similarity index 86%
rename from ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/open_prj_scalp_design_debug.sh
rename to ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/open_prj_scalp_design_debug.sh
index ba3fdfe..47f48be 100755
--- a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/open_prj_scalp_design_debug.sh
+++ b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/open_prj_scalp_design_debug.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_debug
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-10-13 12:39:40
+# Last update: 2021-01-15 08:39:29
#
##################################################################################
diff --git a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/utils.tcl
rename to ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/utils.tcl
index 15b4368..4bc17a2 100644
--- a/ips/vivado/scalp_design_debug/2019.2/lin64/.scripts/utils.tcl
+++ b/ips/vivado/scalp_design_debug/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_debug
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-10-13 12:39:40
+# Last update: 2021-01-15 08:39:29
#
##################################################################################
diff --git a/ips/vivado/scalp_design_debug/2019.2/lin64/setup.sh b/ips/vivado/scalp_design_debug/2020.2/lin64/setup.sh
similarity index 91%
rename from ips/vivado/scalp_design_debug/2019.2/lin64/setup.sh
rename to ips/vivado/scalp_design_debug/2020.2/lin64/setup.sh
index e8c209f..e5d4664 100755
--- a/ips/vivado/scalp_design_debug/2019.2/lin64/setup.sh
+++ b/ips/vivado/scalp_design_debug/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_design_debug
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-10-13 12:39:40
+# Last update: 2021-01-15 08:39:29
#
##################################################################################
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl b/ips/vivado/scalp_design_debug/2020.2/src/ipi_tcl/scalp_design_debug_ipi.tcl
similarity index 100%
rename from packages/vivado/aurora_drp_pkg/2019.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl
rename to ips/vivado/scalp_design_debug/2020.2/src/ipi_tcl/scalp_design_debug_ipi.tcl
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/.prompt_colors.tcl
index 1110ac3..84b1b02 100644
--- a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_packet_fifo_wrapper
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-11-08 10:31:02
+# Last update: 2021-01-15 08:44:59
#
##################################################################################
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/clean_prj_scalp_packet_fifo_wrapper.sh b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/clean_prj_scalp_packet_fifo_wrapper.sh
similarity index 89%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/clean_prj_scalp_packet_fifo_wrapper.sh
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/clean_prj_scalp_packet_fifo_wrapper.sh
index 98d008f..5716787 100755
--- a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/clean_prj_scalp_packet_fifo_wrapper.sh
+++ b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/clean_prj_scalp_packet_fifo_wrapper.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_packet_fifo_wrapper
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-11-08 10:31:02
+# Last update: 2021-01-15 08:44:59
#
##################################################################################
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.sh b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.sh
similarity index 86%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.sh
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.sh
index ef3d7b3..6d49e61 100755
--- a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.sh
+++ b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_packet_fifo_wrapper
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-08 10:31:02
+# Last update: 2021-01-15 08:44:59
#
##################################################################################
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.tcl b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.tcl
similarity index 86%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.tcl
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.tcl
index 61d1bc6..ad8b6af 100644
--- a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.tcl
+++ b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/create_prj_scalp_packet_fifo_wrapper.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_packet_fifo_wrapper
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_packet_fifo_wrapper'
#
-# Last update: 2020-11-08 10:31:02
+# Last update: 2021-01-15 08:44:59
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -67,8 +67,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
# add IPs source file
-
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -77,8 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
- read_ip $comp_src_dir/ip_core/scalp_packet_fifo/scalp_packet_fifo.xci
+ read_ip $comp_src_dir/ip_core/scalp_packet_fifo/scalp_packet_fifo.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
@@ -132,7 +130,15 @@ foreach j $vhdl_sim_file_list {
print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources
-
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ }
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
# Add SoC wrapper sources files
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/open_prj_scalp_packet_fifo_wrapper.sh b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/open_prj_scalp_packet_fifo_wrapper.sh
similarity index 86%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/open_prj_scalp_packet_fifo_wrapper.sh
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/open_prj_scalp_packet_fifo_wrapper.sh
index c420d9e..5149fec 100755
--- a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/open_prj_scalp_packet_fifo_wrapper.sh
+++ b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/open_prj_scalp_packet_fifo_wrapper.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_packet_fifo_wrapper
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-08 10:31:02
+# Last update: 2021-01-15 08:44:59
#
##################################################################################
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/utils.tcl
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/utils.tcl
index 3330ab2..18f00ed 100644
--- a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/.scripts/utils.tcl
+++ b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_packet_fifo_wrapper
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-11-08 10:31:02
+# Last update: 2021-01-15 08:44:59
#
##################################################################################
diff --git a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/setup.sh b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/setup.sh
similarity index 91%
rename from ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/setup.sh
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/setup.sh
index bcc0345..097f3b3 100755
--- a/ips/vivado/scalp_packet_fifo_wrapper/2019.2/lin64/setup.sh
+++ b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_packet_fifo_wrapper
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-11-08 10:31:02
+# Last update: 2021-01-15 08:44:59
#
##################################################################################
diff --git a/packages/vivado/aurora_status_pkg/2019.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl b/ips/vivado/scalp_packet_fifo_wrapper/2020.2/src/ipi_tcl/scalp_packet_fifo_wrapper_ipi.tcl
similarity index 100%
rename from packages/vivado/aurora_status_pkg/2019.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl
rename to ips/vivado/scalp_packet_fifo_wrapper/2020.2/src/ipi_tcl/scalp_packet_fifo_wrapper_ipi.tcl
diff --git a/ips/vivado/scalp_router/2019.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_router/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from ips/vivado/scalp_router/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to ips/vivado/scalp_router/2020.2/lin64/.scripts/.prompt_colors.tcl
index 767df68..5edc7a7 100644
--- a/ips/vivado/scalp_router/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/ips/vivado/scalp_router/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_router
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-11-30 08:31:15
+# Last update: 2021-01-15 09:21:48
#
##################################################################################
diff --git a/ips/vivado/scalp_router/2019.2/lin64/.scripts/clean_prj_scalp_router.sh b/ips/vivado/scalp_router/2020.2/lin64/.scripts/clean_prj_scalp_router.sh
similarity index 88%
rename from ips/vivado/scalp_router/2019.2/lin64/.scripts/clean_prj_scalp_router.sh
rename to ips/vivado/scalp_router/2020.2/lin64/.scripts/clean_prj_scalp_router.sh
index e407363..7fd9873 100755
--- a/ips/vivado/scalp_router/2019.2/lin64/.scripts/clean_prj_scalp_router.sh
+++ b/ips/vivado/scalp_router/2020.2/lin64/.scripts/clean_prj_scalp_router.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_router
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-11-30 08:31:15
+# Last update: 2021-01-15 09:21:48
#
##################################################################################
diff --git a/ips/vivado/scalp_router/2019.2/lin64/.scripts/create_prj_scalp_router.sh b/ips/vivado/scalp_router/2020.2/lin64/.scripts/create_prj_scalp_router.sh
similarity index 86%
rename from ips/vivado/scalp_router/2019.2/lin64/.scripts/create_prj_scalp_router.sh
rename to ips/vivado/scalp_router/2020.2/lin64/.scripts/create_prj_scalp_router.sh
index 123e6cd..19d6e8b 100755
--- a/ips/vivado/scalp_router/2019.2/lin64/.scripts/create_prj_scalp_router.sh
+++ b/ips/vivado/scalp_router/2020.2/lin64/.scripts/create_prj_scalp_router.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_router
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-30 08:31:15
+# Last update: 2021-01-15 09:21:48
#
##################################################################################
diff --git a/ips/vivado/scalp_router/2019.2/lin64/.scripts/create_prj_scalp_router.tcl b/ips/vivado/scalp_router/2020.2/lin64/.scripts/create_prj_scalp_router.tcl
similarity index 96%
rename from ips/vivado/scalp_router/2019.2/lin64/.scripts/create_prj_scalp_router.tcl
rename to ips/vivado/scalp_router/2020.2/lin64/.scripts/create_prj_scalp_router.tcl
index 9cea07d..c78e67e 100644
--- a/ips/vivado/scalp_router/2019.2/lin64/.scripts/create_prj_scalp_router.tcl
+++ b/ips/vivado/scalp_router/2020.2/lin64/.scripts/create_prj_scalp_router.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_router
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_router'
#
-# Last update: 2020-11-30 08:31:15
+# Last update: 2021-01-15 09:21:48
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -67,8 +67,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
# add IPs source file
-
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -77,8 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
-
+
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
diff --git a/ips/vivado/scalp_router/2019.2/lin64/.scripts/open_prj_scalp_router.sh b/ips/vivado/scalp_router/2020.2/lin64/.scripts/open_prj_scalp_router.sh
similarity index 85%
rename from ips/vivado/scalp_router/2019.2/lin64/.scripts/open_prj_scalp_router.sh
rename to ips/vivado/scalp_router/2020.2/lin64/.scripts/open_prj_scalp_router.sh
index deac5a2..4c23006 100755
--- a/ips/vivado/scalp_router/2019.2/lin64/.scripts/open_prj_scalp_router.sh
+++ b/ips/vivado/scalp_router/2020.2/lin64/.scripts/open_prj_scalp_router.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_router
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-11-30 08:31:15
+# Last update: 2021-01-15 09:21:48
#
##################################################################################
diff --git a/ips/vivado/scalp_router/2019.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_router/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from ips/vivado/scalp_router/2019.2/lin64/.scripts/utils.tcl
rename to ips/vivado/scalp_router/2020.2/lin64/.scripts/utils.tcl
index 2d6ab42..f06a3c8 100644
--- a/ips/vivado/scalp_router/2019.2/lin64/.scripts/utils.tcl
+++ b/ips/vivado/scalp_router/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_router
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-11-30 08:31:15
+# Last update: 2021-01-15 09:21:48
#
##################################################################################
diff --git a/ips/vivado/scalp_router/2019.2/lin64/setup.sh b/ips/vivado/scalp_router/2020.2/lin64/setup.sh
similarity index 91%
rename from ips/vivado/scalp_router/2019.2/lin64/setup.sh
rename to ips/vivado/scalp_router/2020.2/lin64/setup.sh
index fd872bf..abe1cdf 100755
--- a/ips/vivado/scalp_router/2019.2/lin64/setup.sh
+++ b/ips/vivado/scalp_router/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_router
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-11-30 08:31:15
+# Last update: 2021-01-15 09:21:48
#
##################################################################################
diff --git a/packages/vivado/axi4_pkg/2019.2/src/ipi_tcl/axi4_pkg_ipi.tcl b/ips/vivado/scalp_router/2020.2/src/ipi_tcl/scalp_router_ipi.tcl
similarity index 100%
rename from packages/vivado/axi4_pkg/2019.2/src/ipi_tcl/axi4_pkg_ipi.tcl
rename to ips/vivado/scalp_router/2020.2/src/ipi_tcl/scalp_router_ipi.tcl
diff --git a/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd b/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
index 7793741..3d03e1e 100644
--- a/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
+++ b/packages/hw/aurora_drp_pkg/src/hdl/aurora_drp_pkg.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: aurora_drp_pkg
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: DRP interface control signals for the Aurora phy.
--
-- Last update: 2020-10-12
diff --git a/packages/hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd b/packages/hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd
index d292767..3eaf60c 100644
--- a/packages/hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd
+++ b/packages/hw/aurora_drp_pkg/src/sim/tb_aurora_drp_pkg.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: tb_aurora_drp_pkg - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for package aurora_drp_pkg
--
--- Last update: 2020-09-21 10:54:03
+-- Last update: 2021-01-14 11:09:52
--
---------------------------------------------------------------------------------
diff --git a/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
index d2a4046..c5e35b0 100644
--- a/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
+++ b/packages/hw/aurora_status_pkg/src/hdl/aurora_status_pkg.vhd
@@ -12,10 +12,10 @@
--
-- Module Name: aurora_status_pkg
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: Control and status signals for the Aurora phy.
--
--- Last update: 2020-11-25
+-- Last update: 2020-12-07
--
---------------------------------------------------------------------------------
@@ -290,6 +290,24 @@ package aurora_status_pkg is
type t_rx_fifo_reset_done_states is (E_RESET, E_WAIT_DONE, E_IS_DONE);
+ type t_scalp_router_ready is record
+ NorthxS : std_ulogic;
+ EastxS : std_ulogic;
+ SouthxS : std_ulogic;
+ WestxS : std_ulogic;
+ TopxS : std_ulogic;
+ BottomxS : std_ulogic;
+ LocalxS : std_ulogic;
+ end record t_scalp_router_ready;
+
+ constant C_NO_SCALP_ROUTER_READY : t_scalp_router_ready := (NorthxS => '0',
+ EastxS => '0',
+ SouthxS => '0',
+ WestxS => '0',
+ TopxS => '0',
+ BottomxS => '0',
+ LocalxS => '0');
+
-- Functions
function std_bool (exp_in : in boolean) return std_ulogic;
diff --git a/packages/hw/aurora_status_pkg/src/sim/tb_aurora_status_pkg.vhd b/packages/hw/aurora_status_pkg/src/sim/tb_aurora_status_pkg.vhd
index bc56293..afb8cbb 100644
--- a/packages/hw/aurora_status_pkg/src/sim/tb_aurora_status_pkg.vhd
+++ b/packages/hw/aurora_status_pkg/src/sim/tb_aurora_status_pkg.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: tb_aurora_status_pkg - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for package aurora_status_pkg
--
--- Last update: 2020-09-21 10:57:55
+-- Last update: 2021-01-14 11:10:01
--
---------------------------------------------------------------------------------
diff --git a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
index 5f8cca7..792aad9 100644
--- a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
+++ b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: axi4_pkg
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: AXI4 format bus signals.
--
-- Last update: 2020-11-25
diff --git a/packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd b/packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd
index 10ef166..6db0bf7 100644
--- a/packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd
+++ b/packages/hw/axi4_pkg/src/sim/tb_axi4_pkg.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: tb_axi4_pkg - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for package axi4_pkg
--
--- Last update: 2020-09-21 10:58:57
+-- Last update: 2021-01-14 11:10:09
--
---------------------------------------------------------------------------------
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
index 08a5516..7ebc14d 100644
--- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_drp_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-09-21 10:54:03
+# Last update: 2021-01-14 11:09:52
#
##################################################################################
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh
similarity index 88%
rename from packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh
rename to packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh
index 55c73e8..fc4bbd9 100755
--- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh
+++ b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/clean_prj_aurora_drp_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_drp_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-09-21 10:54:03
+# Last update: 2021-01-14 11:09:52
#
##################################################################################
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh
similarity index 86%
rename from packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh
rename to packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh
index eb2b8a8..536bbd0 100755
--- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh
+++ b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/create_prj_aurora_drp_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_drp_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-21 10:54:03
+# Last update: 2021-01-14 11:09:52
#
##################################################################################
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl
similarity index 90%
rename from packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl
rename to packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl
index e850aed..beb2a0f 100644
--- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl
+++ b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/create_prj_aurora_drp_pkg.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_drp_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'aurora_drp_pkg'
#
-# Last update: 2020-09-21 10:54:03
+# Last update: 2021-01-14 11:09:52
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -61,11 +61,13 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
- add_files -norecurse $hdl_src_file_list
+ add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
# add IPs source file
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -74,7 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
@@ -86,6 +88,11 @@ foreach j $vhdl_src_file_list {
}
print_status "VHDL 2008 mode configured for project sources" "OK"
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh
similarity index 85%
rename from packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh
rename to packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh
index e253c86..0328a87 100755
--- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh
+++ b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/open_prj_aurora_drp_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_drp_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-21 10:54:03
+# Last update: 2021-01-14 11:09:52
#
##################################################################################
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/utils.tcl b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/utils.tcl
rename to packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/utils.tcl
index 9d58086..d74779e 100644
--- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/.scripts/utils.tcl
+++ b/packages/vivado/aurora_drp_pkg/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_drp_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-09-21 10:54:03
+# Last update: 2021-01-14 11:09:52
#
##################################################################################
diff --git a/packages/vivado/aurora_drp_pkg/2019.2/lin64/setup.sh b/packages/vivado/aurora_drp_pkg/2020.2/lin64/setup.sh
similarity index 91%
rename from packages/vivado/aurora_drp_pkg/2019.2/lin64/setup.sh
rename to packages/vivado/aurora_drp_pkg/2020.2/lin64/setup.sh
index 376e6a0..f83873a 100755
--- a/packages/vivado/aurora_drp_pkg/2019.2/lin64/setup.sh
+++ b/packages/vivado/aurora_drp_pkg/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_drp_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-09-21 10:54:03
+# Last update: 2021-01-14 11:09:52
#
##################################################################################
diff --git a/packages/vivado/aurora_drp_pkg/2020.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl b/packages/vivado/aurora_drp_pkg/2020.2/src/ipi_tcl/aurora_drp_pkg_ipi.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
index 88f94eb..5fe2b1a 100644
--- a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-09-21 10:57:55
+# Last update: 2021-01-14 11:10:01
#
##################################################################################
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh
similarity index 89%
rename from packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh
rename to packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh
index 1b2cde1..57f0a83 100755
--- a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh
+++ b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/clean_prj_aurora_status_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-09-21 10:57:55
+# Last update: 2021-01-14 11:10:01
#
##################################################################################
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.sh b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/create_prj_aurora_status_pkg.sh
similarity index 86%
rename from packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.sh
rename to packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/create_prj_aurora_status_pkg.sh
index b5daffb..7ef0594 100755
--- a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.sh
+++ b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/create_prj_aurora_status_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-21 10:57:55
+# Last update: 2021-01-14 11:10:01
#
##################################################################################
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl
similarity index 90%
rename from packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl
rename to packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl
index e04df11..91affd1 100644
--- a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl
+++ b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/create_prj_aurora_status_pkg.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'aurora_status_pkg'
#
-# Last update: 2020-09-21 10:57:55
+# Last update: 2021-01-14 11:10:01
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -61,11 +61,13 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
- add_files -norecurse $hdl_src_file_list
+ add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
# add IPs source file
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -74,7 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
@@ -86,6 +88,11 @@ foreach j $vhdl_src_file_list {
}
print_status "VHDL 2008 mode configured for project sources" "OK"
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/open_prj_aurora_status_pkg.sh b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/open_prj_aurora_status_pkg.sh
similarity index 85%
rename from packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/open_prj_aurora_status_pkg.sh
rename to packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/open_prj_aurora_status_pkg.sh
index 6b75e75..d12e542 100755
--- a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/open_prj_aurora_status_pkg.sh
+++ b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/open_prj_aurora_status_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-21 10:57:55
+# Last update: 2021-01-14 11:10:01
#
##################################################################################
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/utils.tcl b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/utils.tcl
rename to packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/utils.tcl
index cdb1be0..4904e12 100644
--- a/packages/vivado/aurora_status_pkg/2019.2/lin64/.scripts/utils.tcl
+++ b/packages/vivado/aurora_status_pkg/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-09-21 10:57:55
+# Last update: 2021-01-14 11:10:01
#
##################################################################################
diff --git a/packages/vivado/aurora_status_pkg/2019.2/lin64/setup.sh b/packages/vivado/aurora_status_pkg/2020.2/lin64/setup.sh
similarity index 91%
rename from packages/vivado/aurora_status_pkg/2019.2/lin64/setup.sh
rename to packages/vivado/aurora_status_pkg/2020.2/lin64/setup.sh
index 35e8175..14fb0a3 100755
--- a/packages/vivado/aurora_status_pkg/2019.2/lin64/setup.sh
+++ b/packages/vivado/aurora_status_pkg/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-09-21 10:57:55
+# Last update: 2021-01-14 11:10:01
#
##################################################################################
diff --git a/packages/vivado/aurora_status_pkg/2020.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl b/packages/vivado/aurora_status_pkg/2020.2/src/ipi_tcl/aurora_status_pkg_ipi.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from packages/vivado/axi4_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to packages/vivado/axi4_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
index 908374b..730aea1 100644
--- a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-09-21 10:58:57
+# Last update: 2021-01-14 11:10:09
#
##################################################################################
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/clean_prj_axi4_pkg.sh b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/clean_prj_axi4_pkg.sh
similarity index 88%
rename from packages/vivado/axi4_pkg/2019.2/lin64/.scripts/clean_prj_axi4_pkg.sh
rename to packages/vivado/axi4_pkg/2020.2/lin64/.scripts/clean_prj_axi4_pkg.sh
index c53b314..d45e03a 100755
--- a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/clean_prj_axi4_pkg.sh
+++ b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/clean_prj_axi4_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-09-21 10:58:57
+# Last update: 2021-01-14 11:10:09
#
##################################################################################
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.sh b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/create_prj_axi4_pkg.sh
similarity index 86%
rename from packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.sh
rename to packages/vivado/axi4_pkg/2020.2/lin64/.scripts/create_prj_axi4_pkg.sh
index 010a8a8..ac0e5de 100755
--- a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.sh
+++ b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/create_prj_axi4_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-21 10:58:57
+# Last update: 2021-01-14 11:10:09
#
##################################################################################
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.tcl b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/create_prj_axi4_pkg.tcl
similarity index 90%
rename from packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.tcl
rename to packages/vivado/axi4_pkg/2020.2/lin64/.scripts/create_prj_axi4_pkg.tcl
index 3f3e315..e26cced 100644
--- a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/create_prj_axi4_pkg.tcl
+++ b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/create_prj_axi4_pkg.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'axi4_pkg'
#
-# Last update: 2020-09-21 10:58:57
+# Last update: 2021-01-14 11:10:09
#
##################################################################################
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -61,11 +61,13 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
- add_files -norecurse $hdl_src_file_list
+ add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
# add IPs source file
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
@@ -74,7 +76,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
@@ -86,6 +88,11 @@ foreach j $vhdl_src_file_list {
}
print_status "VHDL 2008 mode configured for project sources" "OK"
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/open_prj_axi4_pkg.sh b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/open_prj_axi4_pkg.sh
similarity index 85%
rename from packages/vivado/axi4_pkg/2019.2/lin64/.scripts/open_prj_axi4_pkg.sh
rename to packages/vivado/axi4_pkg/2020.2/lin64/.scripts/open_prj_axi4_pkg.sh
index 19d51ed..a1a441e 100755
--- a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/open_prj_axi4_pkg.sh
+++ b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/open_prj_axi4_pkg.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-21 10:58:57
+# Last update: 2021-01-14 11:10:09
#
##################################################################################
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/utils.tcl b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from packages/vivado/axi4_pkg/2019.2/lin64/.scripts/utils.tcl
rename to packages/vivado/axi4_pkg/2020.2/lin64/.scripts/utils.tcl
index 3ab94a5..4e33f98 100644
--- a/packages/vivado/axi4_pkg/2019.2/lin64/.scripts/utils.tcl
+++ b/packages/vivado/axi4_pkg/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-09-21 10:58:57
+# Last update: 2021-01-14 11:10:09
#
##################################################################################
diff --git a/packages/vivado/axi4_pkg/2019.2/lin64/setup.sh b/packages/vivado/axi4_pkg/2020.2/lin64/setup.sh
similarity index 90%
rename from packages/vivado/axi4_pkg/2019.2/lin64/setup.sh
rename to packages/vivado/axi4_pkg/2020.2/lin64/setup.sh
index 6ad920b..02e84a6 100755
--- a/packages/vivado/axi4_pkg/2019.2/lin64/setup.sh
+++ b/packages/vivado/axi4_pkg/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-09-21 10:58:57
+# Last update: 2021-01-14 11:10:09
#
##################################################################################
diff --git a/packages/vivado/axi4_pkg/2020.2/src/ipi_tcl/axi4_pkg_ipi.tcl b/packages/vivado/axi4_pkg/2020.2/src/ipi_tcl/axi4_pkg_ipi.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
index 670afb9..d0d7351 100644
--- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
@@ -12,7 +12,7 @@
--
-- Module Name: scalp_zynqps_wrapper - arch
-- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
-- Last update: 2020-11-08
diff --git a/soc/hw/scalp_zynqps/src/sim/tb_scalp_zynqps.vhd b/soc/hw/scalp_zynqps/src/sim/tb_scalp_zynqps.vhd
index aba8d8e..4291ea3 100644
--- a/soc/hw/scalp_zynqps/src/sim/tb_scalp_zynqps.vhd
+++ b/soc/hw/scalp_zynqps/src/sim/tb_scalp_zynqps.vhd
@@ -11,11 +11,11 @@
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: tb_scalp_zynqps - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
-- Description: Testbench for scalp_zynqps
--
--- Last update: 2020-09-07 11:18:55
+-- Last update: 2021-01-14 11:15:26
--
---------------------------------------------------------------------------------
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/.prompt_colors.tcl b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/.prompt_colors.tcl
similarity index 89%
rename from soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/.prompt_colors.tcl
rename to soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/.prompt_colors.tcl
index 57411e7..ac2e987 100644
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/.prompt_colors.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Console color print utility
#
-# Last update: 2020-09-07 11:18:55
+# Last update: 2021-01-14 11:15:26
#
##################################################################################
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/clean_prj_scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/clean_prj_scalp_zynqps.sh
similarity index 88%
rename from soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/clean_prj_scalp_zynqps.sh
rename to soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/clean_prj_scalp_zynqps.sh
index 38e7dfd..1ecc87f 100755
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/clean_prj_scalp_zynqps.sh
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/clean_prj_scalp_zynqps.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Cleanup project directory
#
-# Last update: 2020-09-07 11:18:55
+# Last update: 2021-01-14 11:15:26
#
##################################################################################
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/create_prj_scalp_zynqps.sh
similarity index 86%
rename from soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.sh
rename to soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/create_prj_scalp_zynqps.sh
index 5484e07..2e67794 100755
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.sh
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/create_prj_scalp_zynqps.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-07 11:18:55
+# Last update: 2021-01-14 11:15:26
#
##################################################################################
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.tcl b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/create_prj_scalp_zynqps.tcl
similarity index 67%
rename from soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.tcl
rename to soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/create_prj_scalp_zynqps.tcl
index 5057ecf..0b14a8c 100644
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/create_prj_scalp_zynqps.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_zynqps'
#
-# Last update: 2020-09-07 11:18:55
+# Last update: 2021-01-14 11:15:26
#
##################################################################################
@@ -24,6 +24,8 @@ source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_zynqps"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
# Set project type
set PRJ_TYPE "COMP_PRJ_TYPE"
@@ -36,11 +38,13 @@ set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../soc/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
@@ -54,28 +58,41 @@ update_ip_catalog
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources
- set hdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+ set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
- set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
- add_files -norecurse $hdl_src_file_list
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+ add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
# add IPs source file
- #read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
- set hdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+ set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
- set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
+ set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
- #read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for project sources" "OK"
+
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
@@ -94,17 +111,29 @@ update_compile_order -fileset sources_1
# Add testbench sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
- set hdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+ set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $src_dir/sim *.v]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
- set hdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+ set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
}
-set hdl_sim_file_list [list {*}$hdl_sim_file_list {*}$verilog_sim_file_list]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL} [get_files $j]
+ print_status "VHDL mode configured for the file $j" "OK"
+}
+print_status "VHDL mode configured for testbench sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/open_prj_scalp_zynqps.sh b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/open_prj_scalp_zynqps.sh
similarity index 85%
rename from soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/open_prj_scalp_zynqps.sh
rename to soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/open_prj_scalp_zynqps.sh
index a9d16a1..c769485 100755
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/open_prj_scalp_zynqps.sh
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/open_prj_scalp_zynqps.sh
@@ -13,11 +13,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Create Vivado project
#
-# Last update: 2020-09-07 11:18:55
+# Last update: 2021-01-14 11:15:26
#
##################################################################################
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/utils.tcl b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/utils.tcl
similarity index 94%
rename from soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/utils.tcl
rename to soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/utils.tcl
index 987591f..b871c60 100644
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/.scripts/utils.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/utils.tcl
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: Project management utilities
#
-# Last update: 2020-09-07 11:18:55
+# Last update: 2021-01-14 11:15:26
#
##################################################################################
diff --git a/soc/vivado/scalp_zynqps/2019.2/lin64/setup.sh b/soc/vivado/scalp_zynqps/2020.2/lin64/setup.sh
similarity index 91%
rename from soc/vivado/scalp_zynqps/2019.2/lin64/setup.sh
rename to soc/vivado/scalp_zynqps/2020.2/lin64/setup.sh
index 47d3c27..f35884d 100755
--- a/soc/vivado/scalp_zynqps/2019.2/lin64/setup.sh
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/setup.sh
@@ -11,11 +11,11 @@
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
-# Target Device: SCALP xc7z015clg485-2
-# Tool version: 2019.2
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
-# Last update: 2020-09-07 11:18:55
+# Last update: 2021-01-14 11:15:26
#
##################################################################################
diff --git a/soc/vivado/scalp_zynqps/2019.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
similarity index 89%
rename from soc/vivado/scalp_zynqps/2019.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
rename to soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index c57dbea..b539535 100644
--- a/soc/vivado/scalp_zynqps/2019.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
-set scripts_vivado_version 2019.2
+set scripts_vivado_version 2020.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
- catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
return 1
}
@@ -44,6 +44,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z015clg485-2
+ set_property BOARD_PART hepia-cores.ch:scalp_node:part0:0.1 [current_project]
}
@@ -70,9 +71,9 @@ if { $run_remote_bd_flow == 1 } {
# Check if remote design exists on disk
if { [file exists $str_bd_filepath ] == 1 } {
- catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
- common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
- common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+ catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
+ common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
+ common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
return 1
}
@@ -80,9 +81,9 @@ if { $run_remote_bd_flow == 1 } {
# Check if design exists in memory
set list_existing_designs [get_bd_designs -quiet $design_name]
if { $list_existing_designs ne "" } {
- catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
- common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+ common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
return 1
}
@@ -90,11 +91,11 @@ if { $run_remote_bd_flow == 1 } {
# Check if design exists on disk within project
set list_existing_designs [get_files -quiet */${design_name}.bd]
if { $list_existing_designs ne "" } {
- catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location:
+ catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
$list_existing_designs"}
- catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
- common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+ common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
return 1
}
@@ -106,7 +107,7 @@ if { $run_remote_bd_flow == 1 } {
# Create regular design
if { [catch {create_bd_design $design_name} errmsg] } {
- common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable <design_name>."
+ common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
return 1
}
@@ -125,13 +126,13 @@ xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
-hepia.hesge.ch:user:scalp_axi4lite:1.0\
+hepia.hesge.ch:user:scalp_axi4lite:1.2\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
"
set list_ips_missing ""
- common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
@@ -141,14 +142,14 @@ xilinx.com:ip:vio:3.0\
}
if { $list_ips_missing ne "" } {
- catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
- common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
@@ -172,14 +173,14 @@ proc create_root_design { parentCell } {
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
- catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
- catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
@@ -549,7 +550,36 @@ proc create_root_design { parentCell } {
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_9_PULLUP {enabled} \
CONFIG.PCW_MIO_9_SLEW {slow} \
- CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SPI 0#SPI 0#SPI 0#GPIO#GPIO#SPI 0#UART 0#UART 0#UART 1#UART 1#I2C 0#I2C 0#CAN 1#CAN 1} \
+ CONFIG.PCW_MIO_TREE_PERIPHERALS { \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#Enet 0#USB \
+ 0#GPIO#GPIO#SPI 0#UART \
+ 0#I2C 0#CAN \
+ 0#SPI 0#SPI \
+ 0#UART 0#UART \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 0#USB 0#SPI \
+ 1#CAN 1 \
+ 1#SD 1#Enet \
+ 1#SD 1#Enet \
+ 1#SD 1#Enet \
+ 1#UART 1#I2C \
+ Flash#GPIO#GPIO#SD 1#SD \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ Flash#Quad SPI \
+ GPIO#Quad SPI \
+ } \
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#cd#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#sclk#miso#ss[0]#gpio[43]#gpio[44]#mosi#rx#tx#tx#rx#scl#sda#tx#rx} \
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
@@ -650,7 +680,7 @@ proc create_root_design { parentCell } {
set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
# Create instance: scalp_axi4lite_0, and set properties
- set scalp_axi4lite_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_axi4lite:1.0 scalp_axi4lite_0 ]
+ set scalp_axi4lite_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_axi4lite:1.2 scalp_axi4lite_0 ]
# Create instance: util_vector_logic_0, and set properties
set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
diff --git a/tools/config/aurora_drp_pkg.json b/tools/config/aurora_drp_pkg.json
index ea5bc7f..2027e0f 100644
--- a/tools/config/aurora_drp_pkg.json
+++ b/tools/config/aurora_drp_pkg.json
@@ -7,12 +7,12 @@
"name": "aurora_drp_pkg",
"type": "COMP_PRJ_TYPE",
"category": "PACKAGES",
- "vivado_version": "2019.2",
+ "vivado_version": "2020.2",
"target_language": "VHDL",
"vhdl_version": "VHDL 2008"
},
"hardware": {
"part_name": "xc7z015clg485-2",
- "board_name": "SCALP"
+ "board_name": "hepia-cores.ch:scalp_node:part0:0.1"
}
}
diff --git a/tools/config/aurora_status_pkg.json b/tools/config/aurora_status_pkg.json
index 1686a85..514ebc2 100644
--- a/tools/config/aurora_status_pkg.json
+++ b/tools/config/aurora_status_pkg.json
@@ -7,12 +7,12 @@
"name": "aurora_status_pkg",
"type": "COMP_PRJ_TYPE",
"category": "PACKAGES",
- "vivado_version": "2019.2",
+ "vivado_version": "2020.2",
"target_language": "VHDL",
"vhdl_version": "VHDL 2008"
},
"hardware": {
"part_name": "xc7z015clg485-2",
- "board_name": "SCALP"
+ "board_name": "hepia-cores.ch:scalp_node:part0:0.1"
}
}
diff --git a/tools/config/axi4_pkg.json b/tools/config/axi4_pkg.json
index 497e541..04953ca 100644
--- a/tools/config/axi4_pkg.json
+++ b/tools/config/axi4_pkg.json
@@ -7,12 +7,12 @@
"name": "axi4_pkg",
"type": "COMP_PRJ_TYPE",
"category": "PACKAGES",
- "vivado_version": "2019.2",
+ "vivado_version": "2020.2",
"target_language": "VHDL",
"vhdl_version": "VHDL 2008"
},
"hardware": {
"part_name": "xc7z015clg485-2",
- "board_name": "SCALP"
+ "board_name": "hepia-cores.ch:scalp_node:part0:0.1"
}
}
diff --git a/tools/config/scalp_aurora_phy.json b/tools/config/scalp_aurora_phy.json
index ec66ad7..47c30b2 100644
--- a/tools/config/scalp_aurora_phy.json
+++ b/tools/config/scalp_aurora_phy.json
@@ -7,13 +7,13 @@
"name" : "scalp_aurora_phy",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"components" : {
"packages" : {
@@ -31,6 +31,13 @@
"south_channel" : "enable",
"west_channel" : "enable"
}
+ },
+ "scalp_aurora_phy_rx_fifo" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "axis_data_fifo" : "enable"
+ }
}
}
}
diff --git a/tools/config/scalp_aurora_phy_rx_fifo.json b/tools/config/scalp_aurora_phy_rx_fifo.json
index 5766126..93151c7 100644
--- a/tools/config/scalp_aurora_phy_rx_fifo.json
+++ b/tools/config/scalp_aurora_phy_rx_fifo.json
@@ -7,13 +7,13 @@
"name" : "scalp_aurora_phy_rx_fifo",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"components" : {
"packages" : {
diff --git a/tools/config/scalp_axi4lite.json b/tools/config/scalp_axi4lite.json
index 0d1c171..ff73890 100644
--- a/tools/config/scalp_axi4lite.json
+++ b/tools/config/scalp_axi4lite.json
@@ -7,13 +7,13 @@
"name" : "scalp_axi4lite",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"components" : {
"packages" : {
diff --git a/tools/config/scalp_design_aurora_clk.json b/tools/config/scalp_design_aurora_clk.json
index bbab62e..d88b716 100644
--- a/tools/config/scalp_design_aurora_clk.json
+++ b/tools/config/scalp_design_aurora_clk.json
@@ -7,13 +7,13 @@
"name" : "scalp_design_aurora_clk",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"components" : {
"ips" : {
diff --git a/tools/config/scalp_design_debug.json b/tools/config/scalp_design_debug.json
index 513efe7..dcec751 100644
--- a/tools/config/scalp_design_debug.json
+++ b/tools/config/scalp_design_debug.json
@@ -7,13 +7,13 @@
"name" : "scalp_design_debug",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"components" : {
"ips" : {
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
index 6d21c65..807278c 100644
--- a/tools/config/scalp_firmware.json
+++ b/tools/config/scalp_firmware.json
@@ -7,13 +7,13 @@
"name" : "scalp_firmware",
"type" : "DESIGN_PRJ_TYPE",
"category" : "DESIGNS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"constraints" : {
"scalp_firmware" : "enable",
diff --git a/tools/config/scalp_packet_fifo_wrapper.json b/tools/config/scalp_packet_fifo_wrapper.json
index 01437c7..87fd0e8 100644
--- a/tools/config/scalp_packet_fifo_wrapper.json
+++ b/tools/config/scalp_packet_fifo_wrapper.json
@@ -7,13 +7,13 @@
"name" : "scalp_packet_fifo_wrapper",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"components" : {
"packages" : {
diff --git a/tools/config/scalp_router.json b/tools/config/scalp_router.json
index 03301dd..aba7fc0 100644
--- a/tools/config/scalp_router.json
+++ b/tools/config/scalp_router.json
@@ -7,13 +7,13 @@
"name" : "scalp_router",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
},
"components" : {
"packages" : {
diff --git a/tools/config/scalp_zynqps.json b/tools/config/scalp_zynqps.json
index 8194915..50198b4 100644
--- a/tools/config/scalp_zynqps.json
+++ b/tools/config/scalp_zynqps.json
@@ -7,11 +7,11 @@
"name" : "scalp_zynqps",
"type" : "COMP_PRJ_TYPE",
"category" : "SOC",
- "vivado_version" : "2019.2",
+ "vivado_version" : "2020.2",
"target_language" : "VHDL"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
- "board_name" : "SCALP"
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
}
}
diff --git a/tools/vivado_prj_creator b/tools/vivado_prj_creator
index 1c381ff..14d2222 160000
--- a/tools/vivado_prj_creator
+++ b/tools/vivado_prj_creator
@@ -1 +1 @@
-Subproject commit 1c381ffde12e4710be3767e02223806e9c28b789
+Subproject commit 14d2222cde0a7162b79d24f1bb0631795438af48
--
GitLab