diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index 7090d02a9d1d3fc844622366d92f66373faf7a36..fca63d4bf1a4b8995c5b784cadfb49e42abcae03 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
--- Last update: 2021-05-17
+-- Last update: 2021-05-18
--
---------------------------------------------------------------------------------
@@ -517,14 +517,14 @@ architecture arch of scalp_firmware is
signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
-- attribute mark_debug of WestRXM2SxD : signal is "true";
-- attribute keep of WestRXM2SxD : signal is "true";
@@ -889,19 +889,21 @@ begin
signal ScalpPacket0xD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
(SpHeaderxD => C_SP_HEADER_110_TO_210,
SpPayloadxD => C_SP_PAYLOAD_0);
- signal ScalpPacketValid12xS : std_ulogic := '0';
+ signal ScalpPacketValid12xS : std_ulogic := '0';
--
- signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE_0;
- signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE_0;
- signal VioWrSpValidxS : std_ulogic := '0';
+ signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE_0;
+ signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE_0;
+ signal VioWrSpValidxS : std_ulogic := '0';
--
- signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
- signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
+ signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
+ signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
-- Scalp Packet
- -- attribute mark_debug of ScalpPacket0xD : signal is "true";
- -- attribute keep of ScalpPacket0xD : signal is "true";
- -- attribute mark_debug of ScalpPacketValid12xS : signal is "true";
- -- attribute keep of ScalpPacketValid12xS : signal is "true";
+ attribute mark_debug of ScalpPacket0xD : signal is "true";
+ attribute keep of ScalpPacket0xD : signal is "true";
+ attribute mark_debug of ScalpPacketValid12xS : signal is "true";
+ attribute keep of ScalpPacketValid12xS : signal is "true";
+ attribute mark_debug of ScalpPacketLocalxD : signal is "true";
+ attribute keep of ScalpPacketLocalxD : signal is "true";
-- VIO
-- attribute mark_debug of VioWrSpValidxS : signal is "true";
-- attribute keep of VioWrSpValidxS : signal is "true";
@@ -1075,35 +1077,6 @@ begin
SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
-
-
-
-
- -- RXLinkLayerRegxP: process (AuroraClkMasterxC.UserClkxC,
- -- ScalpRouterResetxRNA) is
- -- begin -- process RXLinkLayerRegxP
- -- if ScalpRouterResetxRNA = '0' then
- -- RXSideLLxDP <= E_SCALP_RX_LINK_LAYER_IDLE;
- -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- -- RXSideLLxDP <= RXSideLLxDN;
- -- end if;
- -- end process RXLinkLayerRegxP;
-
- -- RXLinkLayerxP: process is
- -- begin -- process RXLinkLayerxP
- -- RXSideLLxDN <= RXSideLLxDP;
-
- -- case RXSideLLxDP is
- -- when E_SCALP_RX_LINK_LAYER_IDLE => ;
- -- when E_SCALP_RX_LINK_LAYER_WAIT_ON_LAST => ;
- -- when E_SCALP_RX_LINK_LAYER_WAIT => ;
- -- when others => null;
- -- end case;
- -- end process RXLinkLayerxP;
-
-
-
-
WrSpValidxI : entity work.vio_axi_cnt_ctrl
port map (
clk => AuroraClkMasterxC.UserClkxC,
diff --git a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
index a3969799e176ef549323176b5a625ff32e65c4d6..86b97ed0f5f0e020109d5741636fb3428bc3bc82 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
@@ -64,22 +64,22 @@ architecture behavioral of scalp_fifo_double_register is
attribute mark_debug : string;
attribute keep : string;
--
- attribute mark_debug of Axism2s0xD : signal is "true";
- attribute keep of Axism2s0xD : signal is "true";
- attribute mark_debug of Axism2s1xDP : signal is "true";
- attribute keep of Axism2s1xDP : signal is "true";
- attribute mark_debug of Axism2s1xDN : signal is "true";
- attribute keep of Axism2s1xDN : signal is "true";
- attribute mark_debug of Axism2s2xDP : signal is "true";
- attribute keep of Axism2s2xDP : signal is "true";
- attribute mark_debug of Axism2s2xDN : signal is "true";
- attribute keep of Axism2s2xDN : signal is "true";
- attribute mark_debug of Axism2s3xD : signal is "true";
- attribute keep of Axism2s3xD : signal is "true";
- attribute mark_debug of Axiss2m1xDN : signal is "true";
- attribute keep of Axiss2m1xDN : signal is "true";
- attribute mark_debug of Axiss2m1xDP : signal is "true";
- attribute keep of Axiss2m1xDP : signal is "true";
+ -- attribute mark_debug of Axism2s0xD : signal is "true";
+ -- attribute keep of Axism2s0xD : signal is "true";
+ -- attribute mark_debug of Axism2s1xDP : signal is "true";
+ -- attribute keep of Axism2s1xDP : signal is "true";
+ -- attribute mark_debug of Axism2s1xDN : signal is "true";
+ -- attribute keep of Axism2s1xDN : signal is "true";
+ -- attribute mark_debug of Axism2s2xDP : signal is "true";
+ -- attribute keep of Axism2s2xDP : signal is "true";
+ -- attribute mark_debug of Axism2s2xDN : signal is "true";
+ -- attribute keep of Axism2s2xDN : signal is "true";
+ -- attribute mark_debug of Axism2s3xD : signal is "true";
+ -- attribute keep of Axism2s3xD : signal is "true";
+ -- attribute mark_debug of Axiss2m1xDN : signal is "true";
+ -- attribute keep of Axiss2m1xDN : signal is "true";
+ -- attribute mark_debug of Axiss2m1xDP : signal is "true";
+ -- attribute keep of Axiss2m1xDP : signal is "true";
begin -- architecture behavioral
diff --git a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
index 8b8123b6ab09bc6bbd70ea8b6232889fbed4f3f0..1010ea98cd14edf89c444d2af8b7c72508973a0a 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2018.2
-- Description: Scalp Miscellanous
--
--- Last update: 2021-05-12
+-- Last update: 2021-05-18
--
---------------------------------------------------------------------------------
library ieee;
@@ -60,9 +60,7 @@ package scalp_misc is
-- Scalp Tx Side States
type t_scalp_tx_side_states is (E_SCALP_TX_IDLE,
- E_SCALP_TX_WAIT_BOOKING_VECTOR,
- E_SCALP_TX_POP_N_PUSH,
- E_SCALP_TX_WAIT_ACK);
+ E_SCALP_TX_POP_N_PUSH);
-- Scalp Rx Side States
type t_scalp_rx_side_states is (E_SCALP_RX_IDLE,
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
index 3adedb236bf89ca5d12cb52022b47475f8c65e01..40da0be4ede265a016972156ff74999b3e907a8c 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Interface.
--
--- Last update: 2021-05-12
+-- Last update: 2021-05-18
--
---------------------------------------------------------------------------------
library ieee;
@@ -93,8 +93,8 @@ architecture rtl of scalp_router_interface is
SysRstxRNAI : in std_ulogic;
DstRouterNetAddrxDO : out t_scalp_netaddr;
RouterNetAddrValidxSO : out std_ulogic;
- BookingVectorValidxSI : in std_ulogic;
- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
+ -- BookingVectorValidxSI : in std_ulogic;
+ -- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
RXAxi4M2SLinkxDI : in t_axi4m2s;
RXAxi4S2MLinkxDO : out t_axi4s2m;
TXAxi4M2SLinkxDO : out t_axi4m2s;
@@ -261,8 +261,8 @@ begin -- architecture rtl
SysRstxRNAI => SysRstxRNAI,
DstRouterNetAddrxDO => DstRouterNetAddrxD,
RouterNetAddrValidxSO => RouterNetAddrValidxS,
- BookingVectorValidxSI => BookingVectorValidxS,
- SchedulerAckxDI => SchedulerAckxD,
+ -- BookingVectorValidxSI => BookingVectorValidxS,
+ -- SchedulerAckxDI => SchedulerAckxD,
RXAxi4M2SLinkxDI => RXAxi4m2sIfxD,
RXAxi4S2MLinkxDO => RXAxi4s2mIfxD,
TXAxi4M2SLinkxDO => TXAxi4M2SLinkxD,
diff --git a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
index cee0bbab45ba4a14d758f6c943872a2942f56874..ed739ec929a803a33dda31fb137e1c7bb77b5a9e 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp TX side state machine.
--
--- Last update: 2021-05-11
+-- Last update: 2021-05-18
--
---------------------------------------------------------------------------------
library ieee;
@@ -45,9 +45,9 @@ entity scalp_tx_side is
DstRouterNetAddrxDO : out t_scalp_netaddr;
RouterNetAddrValidxSO : out std_ulogic;
-- Indicates when the booking vector is valid.
- BookingVectorValidxSI : in std_ulogic;
+ -- BookingVectorValidxSI : in std_ulogic;
-- Scheduler Acknowledgement Vector
- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
+ -- SchedulerAckxDI : in std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
-- Axi4 Stream
-- Input side
RXAxi4M2SLinkxDI : in t_axi4m2s;
@@ -77,8 +77,7 @@ architecture behavioral of scalp_tx_side is
signal DstRouterNetAddrxDN : t_scalp_netaddr := C_3D_MIN_SCALP_NETADDR;
signal RouterNetAddrValidxSP : std_ulogic := '0';
signal RouterNetAddrValidxSN : std_ulogic := '0';
- signal BookingVectorValidxS : std_ulogic := '0';
- signal SchedulerAckxD : std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0) := (others => '0');
+ -- signal SchedulerAckxD : std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0) := (others => '0');
signal RXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
signal RXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
signal TXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
@@ -88,39 +87,37 @@ architecture behavioral of scalp_tx_side is
signal TXSideStatexDN : t_scalp_tx_side_states := E_SCALP_TX_IDLE;
-- Others
signal ReadyInxD : t_axi4s2m := C_NO_AXI4_S2M;
- signal EnPopNPushxS : std_ulogic := '0';
+ signal EnPopxS : std_ulogic := '0';
attribute mark_debug : string;
attribute keep : string;
--
- -- attribute mark_debug of DstRouterNetAddrxDP : signal is "true";
- -- attribute keep of DstRouterNetAddrxDP : signal is "true";
- -- attribute mark_debug of DstRouterNetAddrxDN : signal is "true";
- -- attribute keep of DstRouterNetAddrxDN : signal is "true";
- -- attribute mark_debug of RouterNetAddrValidxSP : signal is "true";
- -- attribute keep of RouterNetAddrValidxSP : signal is "true";
- -- attribute mark_debug of RouterNetAddrValidxSN : signal is "true";
- -- attribute keep of RouterNetAddrValidxSN : signal is "true";
- -- attribute mark_debug of BookingVectorValidxS : signal is "true";
- -- attribute keep of BookingVectorValidxS : signal is "true";
+ attribute mark_debug of TXAxi4M2SLinkxD : signal is "true";
+ attribute keep of TXAxi4M2SLinkxD : signal is "true";
+ attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
+ attribute keep of TXAxi4S2MLinkxD : signal is "true";
+ attribute mark_debug of ReadyInxD : signal is "true";
+ attribute keep of ReadyInxD : signal is "true";
+ attribute mark_debug of TXSideStatexDN : signal is "true";
+ attribute keep of TXSideStatexDN : signal is "true";
+ attribute mark_debug of TXSideStatexDP : signal is "true";
+ attribute keep of TXSideStatexDP : signal is "true";
+ attribute mark_debug of RXAxi4M2SLinkxD : signal is "true";
+ attribute keep of RXAxi4M2SLinkxD : signal is "true";
+ attribute mark_debug of RXAxi4S2MLinkxD : signal is "true";
+ attribute keep of RXAxi4S2MLinkxD : signal is "true";
+ attribute mark_debug of DstRouterNetAddrxDN : signal is "true";
+ attribute keep of DstRouterNetAddrxDN : signal is "true";
+ attribute mark_debug of DstRouterNetAddrxDP : signal is "true";
+ attribute keep of DstRouterNetAddrxDP : signal is "true";
+ attribute mark_debug of RouterNetAddrValidxSN : signal is "true";
+ attribute keep of RouterNetAddrValidxSN : signal is "true";
+ attribute mark_debug of RouterNetAddrValidxSP : signal is "true";
+ attribute keep of RouterNetAddrValidxSP : signal is "true";
+ attribute mark_debug of EnPopxS : signal is "true";
+ attribute keep of EnPopxS : signal is "true";
-- attribute mark_debug of SchedulerAckxD : signal is "true";
-- attribute keep of SchedulerAckxD : signal is "true";
- -- attribute mark_debug of RXAxi4M2SLinkxD : signal is "true";
- -- attribute keep of RXAxi4M2SLinkxD : signal is "true";
- -- attribute mark_debug of RXAxi4S2MLinkxD : signal is "true";
- -- attribute keep of RXAxi4S2MLinkxD : signal is "true";
- -- attribute mark_debug of TXAxi4M2SLinkxD : signal is "true";
- -- attribute keep of TXAxi4M2SLinkxD : signal is "true";
- -- attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
- -- attribute keep of TXAxi4S2MLinkxD : signal is "true";
- -- attribute mark_debug of TXSideStatexDP : signal is "true";
- -- attribute keep of TXSideStatexDP : signal is "true";
- -- attribute mark_debug of TXSideStatexDN : signal is "true";
- -- attribute keep of TXSideStatexDN : signal is "true";
- -- attribute mark_debug of ReadyInxD : signal is "true";
- -- attribute keep of ReadyInxD : signal is "true";
- -- attribute mark_debug of EnPopNPushxS : signal is "true";
- -- attribute keep of EnPopNPushxS : signal is "true";
begin -- architecture behavioral
@@ -129,18 +126,21 @@ begin -- architecture behavioral
EntityIOxB : block is
begin -- block EntityIOxB
DstRouterNetAddrxAS : DstRouterNetAddrxDO <= DstRouterNetAddrxDP;
- SchedulerAckxAS : SchedulerAckxD <= SchedulerAckxDI;
+ RouterNetAddrValidxAS : RouterNetAddrValidxSO <= RouterNetAddrValidxSP;
+ -- SchedulerAckxAS : SchedulerAckxD <= SchedulerAckxDI;
+ -- Ext. Side
RXAxi4M2SLinkxAS : RXAxi4M2SLinkxD <= RXAxi4M2SLinkxDI;
RXAxi4S2MLinkxAS : RXAxi4S2MLinkxDO <= RXAxi4S2MLinkxD;
TXAxi4M2SLinkxAS : TXAxi4M2SLinkxDO <= TXAxi4M2SLinkxD;
TXAxi4S2MLinkxAS : TXAxi4S2MLinkxD <= TXAxi4S2MLinkxDI;
- RouterNetAddrValidxAS : RouterNetAddrValidxSO <= RouterNetAddrValidxSP;
- BookingVectorValidxAS : BookingVectorValidxS <= BookingVectorValidxSI;
+
+ -- BookingVectorValidxAS : BookingVectorValidxS <= BookingVectorValidxSI;
end block EntityIOxB;
AsyncStatementsxB : block is
begin -- block AsyncStatementsxB
- ReadyInxAS : ReadyInxD <= TXAxi4S2MLinkxD when EnPopNPushxS = '1' else C_NO_AXI4_S2M;
+ ReadyInxAS : ReadyInxD <= C_ON_AXI4_S2M when EnPopxS = '1' else
+ C_NO_AXI4_S2M;
end block AsyncStatementsxB;
-- Synchronous Statements
@@ -170,49 +170,40 @@ begin -- architecture behavioral
end if;
end process UpdateRegxP;
- TXSideStateMachinexP : process (BookingVectorValidxS, DstRouterNetAddrxDP,
- RXAxi4M2SLinkxD.DataxD,
- RXAxi4M2SLinkxD.ValidxS,
- TXAxi4M2SLinkxD.LastxS, TXSideStatexDP) is
+ TXSideStateMachinexP : process (TXAxi4M2SLinkxD.DataxD,
+ TXAxi4M2SLinkxD.LastxS,
+ TXAxi4M2SLinkxD.ValidxS,
+ TXAxi4S2MLinkxD.ReadyxS, TXSideStatexDP) is
begin -- process TXSideStateMachinexP
-- Default values
TXSideStatexDN <= TXSideStatexDP;
- DstRouterNetAddrxDN <= DstRouterNetAddrxDP;
+ DstRouterNetAddrxDN <= C_3D_MIN_SCALP_NETADDR;
RouterNetAddrValidxSN <= '0';
- EnPopNPushxS <= '0';
+ EnPopxS <= '0';
case TXSideStatexDP is
when E_SCALP_TX_IDLE =>
- -- Si un paquet scalp est présent, on lit le premier mot
- -- pour en extraire l'adresse de destination.
- if RXAxi4M2SLinkxD.ValidxS = '1' then
- DstRouterNetAddrxDN <= scalp_peek_addr_ul(RXAxi4M2SLinkxD.DataxD);
- RouterNetAddrValidxSN <= '1';
- TXSideStatexDN <= E_SCALP_TX_WAIT_BOOKING_VECTOR;
- end if;
+ EnPopxS <= '1';
- when E_SCALP_TX_WAIT_BOOKING_VECTOR =>
- if BookingVectorValidxS = '1' then
- EnPopNPushxS <= '1';
- TXSideStatexDN <= E_SCALP_TX_POP_N_PUSH;
+ if TXAxi4M2SLinkxD.ValidxS = '1' then
+ EnPopxS <= '0';
+ DstRouterNetAddrxDN <= scalp_peek_addr_ul(TXAxi4M2SLinkxD.DataxD);
+ RouterNetAddrValidxSN <= '1';
+ TXSideStatexDN <= E_SCALP_TX_POP_N_PUSH;
end if;
when E_SCALP_TX_POP_N_PUSH =>
- EnPopNPushxS <= '1';
- if TXAxi4M2SLinkxD.LastxS = '1' then
- -- EnPopNPushxS <= '0'; --
- -- TXSideStatexDN <= E_SCALP_TX_WAIT_ACK;
- TXSideStatexDN <= E_SCALP_TX_IDLE;
+ if TXAxi4S2MLinkxD.ReadyxS = '1' then
+ EnPopxS <= '1';
+ if TXAxi4M2SLinkxD.LastxS = '1' then
+ TXSideStatexDN <= E_SCALP_TX_IDLE;
+ end if;
end if;
- -- when E_SCALP_TX_WAIT_ACK =>
- -- if SchedulerAckxD(0) = '1' then
- -- TXSideStatexDN <= E_SCALP_TX_IDLE;
- -- end if;
-
when others => null;
end case;
+
end process TXSideStateMachinexP;
end architecture behavioral;
diff --git a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
index d82274af6bdf878e7f2cf3bc1aea23eea18f71ea..df2a4bd94c0cd87f7cffcacc02f91b331f14a7c6 100644
--- a/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
+++ b/packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
@@ -63,6 +63,7 @@ package axi4_pkg is
StrbxD => (others => '0'),
UserxD => (others => '0'));
constant C_NO_AXI4_S2M : t_axi4s2m := (ReadyxS => '0');
+ constant C_ON_AXI4_S2M : t_axi4s2m := (ReadyxS => '1');
-- Non-Generic Vector of AXI4 Framing Bus
---------------------------------------------------------------------------