From 9bb095f9d12dd62ff538ec01d8b60c4cbc664678 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Fri, 10 Sep 2021 10:09:38 +0200
Subject: [PATCH] Update scalp_router_firmware
---
.../2020.2/src/constrs/scalp_firmware.xdc | 2 +
.../2020.2/src/constrs/timing_constraints.xdc | 2 +
.../2020.2/src/hdl/scalp_router_firmware.vhd | 237 ++----------------
3 files changed, 31 insertions(+), 210 deletions(-)
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
index ade029a..744874f 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
@@ -255,3 +255,5 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
+
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
index ffd69f8..6e693f5 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -35,3 +35,5 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+
+
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
index 539cbd5..4551a32 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_router_firmware
--
--- Last update: 2021-06-29
+-- Last update: 2021-09-07
--
---------------------------------------------------------------------------------
@@ -43,6 +43,7 @@ entity scalp_router_firmware is
C_USE_IBERT : boolean := false;
C_DEBUG_MODE : boolean := false;
C_RX_FIFO_MODE : boolean := true;
+ C_RX_FIFO_CTRL_TLAST : boolean := true;
C_SCALP_NUMBER_OF_INTERFACE : integer range 0 to 255 := 7;
C_SCALP_SCHEDULER_STRATEGY : string := "RR");
@@ -285,8 +286,10 @@ architecture arch of scalp_router_firmware is
component scalp_aurora_phy is
generic (
- C_DEBUG_MODE : boolean;
- C_RX_FIFO_MODE : boolean);
+ C_DEBUG_MODE : boolean;
+ C_RX_FIFO_MODE : boolean;
+ C_RX_FIFO_RST_DONE_DLY_TICKS : integer;
+ C_RX_FIFO_CTRL_TLAST : boolean);
port (
GTRefClkxCI : in t_gt_ref_slave_clk;
AuroraClkxCI : in t_aurora_slave_clk;
@@ -553,61 +556,21 @@ architecture arch of scalp_router_firmware is
signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
- attribute mark_debug of LocNetAddrxD : signal is "true";
- attribute keep of LocNetAddrxD : signal is "true";
- -- attribute mark_debug of RXFifoRdDataStatexD : signal is "true";
- -- attribute keep of RXFifoRdDataStatexD : signal is "true";
- attribute mark_debug of TXFifoWrDataStatexD : signal is "true";
- attribute keep of TXFifoWrDataStatexD : signal is "true";
- attribute mark_debug of ScalpPacketWriteDataxD : signal is "true";
- attribute keep of ScalpPacketWriteDataxD : signal is "true";
- attribute mark_debug of ScalpPacketReadDataxD : signal is "true";
- attribute keep of ScalpPacketReadDataxD : signal is "true";
- attribute mark_debug of ScalpPacketCtrlxD : signal is "true";
- attribute keep of ScalpPacketCtrlxD : signal is "true";
- attribute mark_debug of ScalpPacketStatusxD : signal is "true";
- attribute keep of ScalpPacketStatusxD : signal is "true";
- -- attribute mark_debug of RXRdDataCntxD : signal is "true";
- -- attribute keep of RXRdDataCntxD : signal is "true";
- -- attribute mark_debug of RXWrDataCntxD : signal is "true";
- -- attribute keep of RXWrDataCntxD : signal is "true";
- -- attribute mark_debug of TXRdDataCntxD : signal is "true";
- -- attribute keep of TXRdDataCntxD : signal is "true";
- -- attribute mark_debug of TXWrDataCntxD : signal is "true";
- -- attribute keep of TXWrDataCntxD : signal is "true";
- attribute mark_debug of LocNetAddrVectxD : signal is "true";
- attribute keep of LocNetAddrVectxD : signal is "true";
- -- attribute mark_debug of EastTXM2SxD : signal is "true";
- -- attribute keep of EastTXS2MxD : signal is "true";
- -- attribute mark_debug of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
- -- attribute mark_debug of WestRXS2MxD : signal is "true";
- -- attribute keep of WestRXS2MxD : signal is "true";
- attribute mark_debug of TXFifoRXM2SxD : signal is "true";
- attribute keep of TXFifoRXM2SxD : signal is "true";
- attribute mark_debug of TXFifoRXS2MxS : signal is "true";
- attribute keep of TXFifoRXS2MxS : signal is "true";
- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
- attribute keep of RXAxism2sVectorxD : signal is "true";
- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
- attribute keep of RXAxiss2mVectorxD : signal is "true";
- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
- attribute keep of TXAxism2sVectorxD : signal is "true";
- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
- attribute keep of TXAxiss2mVectorxD : signal is "true";
- attribute mark_debug of TXFifoWrDataStateNextxD : signal is "true";
- attribute keep of TXFifoWrDataStateNextxD : signal is "true";
- attribute mark_debug of ScalpRouterResetxRNA : signal is "true";
- attribute keep of ScalpRouterResetxRNA : signal is "true";
+ attribute mark_debug of EastTXM2SxD : signal is "true";
+ attribute keep of EastTXM2SxD : signal is "true";
+ attribute mark_debug of EastTXS2MxD : signal is "true";
+ attribute keep of EastTXS2MxD : signal is "true";
+ attribute mark_debug of LocNetAddrxD : signal is "true";
+ attribute keep of LocNetAddrxD : signal is "true";
begin
@@ -772,7 +735,8 @@ begin
generic map (
C_DEBUG_MODE => C_DEBUG_MODE,
C_RX_FIFO_MODE => C_RX_FIFO_MODE,
- C_RX_FIFO_RST_DONE_DLY_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS)
+ C_RX_FIFO_RST_DONE_DLY_TICKS => C_RX_FIFO_RST_DONE_DLY_TICKS,
+ C_RX_FIFO_CTRL_TLAST => C_RX_FIFO_CTRL_TLAST)
port map (
-- Clocks
-- GTP Ref Clocks
@@ -1061,84 +1025,12 @@ begin
end block ResetxB;
- -- ScalpRouterReadyxB : block is
- -- begin -- block ScalpRouterReadyxB
-
- -- ScalpRouterReadyNorthxAS : ScalpRouterReadyxD.NorthxS <=
- -- '0' when
- -- (RXFifoResetDonexD.NorthxS = '0') or
- -- (RXFifoResetDoneDelayedxD.NorthxS = '0') or
- -- (AuroraStatusxD.LaneUpxD(0)(0) = '0') or
- -- (AuroraStatusxD.ChannelUpxD(0) = '0') else
- -- '1';
- -- ScalpRouterReadyEastxAS : ScalpRouterReadyxD.EastxS <=
- -- '0' when
- -- (RXFifoResetDonexD.EastxS = '0') or
- -- (RXFifoResetDoneDelayedxD.EastxS = '0') or
- -- (AuroraStatusxD.LaneUpxD(1)(0) = '0') or
- -- (AuroraStatusxD.ChannelUpxD(1) = '0') else
- -- '1';
- -- ScalpRouterReadySouthxAS : ScalpRouterReadyxD.SouthxS <=
- -- '0' when
- -- (RXFifoResetDonexD.SouthxS = '0') or
- -- (RXFifoResetDoneDelayedxD.SouthxS = '0') or
- -- (AuroraStatusxD.LaneUpxD(2)(0) = '0') or
- -- (AuroraStatusxD.ChannelUpxD(2) = '0') else
- -- '1';
- -- ScalpRouterReadyWestxAS : ScalpRouterReadyxD.WestxS <=
- -- '0' when
- -- (RXFifoResetDonexD.WestxS = '0') or
- -- (RXFifoResetDoneDelayedxD.WestxS = '0') or
- -- (AuroraStatusxD.LaneUpxD(3)(0) = '0') or
- -- (AuroraStatusxD.ChannelUpxD(3) = '0') else
- -- '1';
- -- ScalpRouterReadyTopxAS : ScalpRouterReadyxD.TopxS <= '0';
- -- ScalpRouterReadyBottomxAS : ScalpRouterReadyxD.BottomxS <= '0';
- -- ScalpRouterReadyLocalxAS : ScalpRouterReadyxD.LocalxS <= (not PSSysResetxR) and
- -- (not AuroraClkMasterxC.PllNotLockedxS);
-
- -- end block ScalpRouterReadyxB;
-
-- Local Router Net Addr
-- LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_210;
LocNetAddrXxAS : LocNetAddrxD.XxD <= to_integer(unsigned(LocNetAddrVectxD(7 downto 0)));
LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocNetAddrVectxD(15 downto 8)));
LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocNetAddrVectxD(23 downto 16)));
- -- LocNetAddrFFxG : for i in 0 to 7 generate
-
- -- XxI : FDCE
- -- generic map (
- -- INIT => '0')
- -- port map (
- -- Q => LocNetAddrVectxDP(i),
- -- C => AuroraClkMasterxC.UserClkxC,
- -- CE => '1',
- -- CLR => '0',
- -- D => LocNetAddrVectxDN(i));
-
- -- YxI : FDCE
- -- generic map (
- -- INIT => '0')
- -- port map (
- -- Q => LocNetAddrVectxDP(i + 8),
- -- C => AuroraClkMasterxC.UserClkxC,
- -- CE => '1',
- -- CLR => '0',
- -- D => LocNetAddrVectxDN(i + 8));
-
- -- ZxI : FDCE
- -- generic map (
- -- INIT => '0')
- -- port map (
- -- Q => LocNetAddrVectxDP(i + 16),
- -- C => AuroraClkMasterxC.UserClkxC,
- -- CE => '1',
- -- CLR => '0',
- -- D => LocNetAddrVectxDN(i + 16));
-
- -- end generate LocNetAddrFFxG;
-
-- TX Side
NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID);
@@ -1148,6 +1040,7 @@ begin
EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
+
-- RX Side
NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
@@ -1158,6 +1051,7 @@ begin
SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
+
WrSpValidxI : entity work.vio_axi_cnt_ctrl
port map (
clk => AuroraClkMasterxC.UserClkxC,
@@ -1258,6 +1152,8 @@ begin
-- TX Fifo
ScalpAxisFifoWrapperTXxI : entity work.scalp_axis_fifo_wrapper
+ generic map (
+ C_CTRL_TLAST => true)
port map (
ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC,
ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC,
@@ -1327,6 +1223,8 @@ begin
-- RX Fifo
ScalpAxisFifoWrapperRXxI : entity work.scalp_axis_fifo_wrapper
+ generic map (
+ C_CTRL_TLAST => true)
port map (
ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC,
ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC,
@@ -1351,87 +1249,6 @@ begin
TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
QoSVectorxDI => QoSVectorxD);
- -- ScalpSP2AxisLocalxI : entity work.scalp_sp_to_axis
- -- generic map (
- -- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE)
- -- port map (
- -- SysClkxCI => AuroraClkMasterxC.UserClkxC,
- -- SysRstxRNAI => ScalpRouterResetxRNA,
- -- ScalpPacketxDI => ScalpPacket0xD,
- -- ScalpPacketValidxSI => ScalpPacketValid12xS,
- -- ScalpAxism2sxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID),
- -- ScalpAxiss2mxDI => RXAxiss2mVectorxD(C_LOCAL_IF_ID),
- -- ScalpRdyxSO => open);
-
- -- ScalpAxis2SPxI : entity work.scalp_axis_to_sp
- -- generic map (
- -- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
- -- C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY)
- -- port map (
- -- SysClkxCI => AuroraClkMasterxC.UserClkxC,
- -- SysRstxRNAI => ScalpRouterResetxRNA,
- -- ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
- -- ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
- -- ScalpPacketxDO => ScalpPacketLocalxD,
- -- ScalpPacketValidxSO => ScalpPacketValidLocalxS);
-
- -- WritePacketxB : block is
- -- begin -- block WritePacketxB
-
- -- UpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
- -- ScalpRouterResetxRNA) is
- -- begin -- process UpdateRegxP
- -- if ScalpRouterResetxRNA = '0' then
- -- WrSPStatexDP <= E_WR_SP_IDLE;
- -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- -- WrSPStatexDP <= WrSPStatexDN;
- -- end if;
- -- end process UpdateRegxP;
-
- -- SpValidxP : process (RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS,
- -- VioWrSpValidxS, WrSPStatexDP) is
- -- begin -- process SpValidxP
- -- -- Default values
- -- WrSPStatexDN <= WrSPStatexDP;
- -- ScalpPacketValid12xS <= '0';
-
- -- case WrSPStatexDP is
- -- when E_WR_SP_IDLE =>
- -- if VioWrSpValidxS = '1' then
- -- ScalpPacketValid12xS <= '1';
- -- WrSPStatexDN <= E_WR_SP_VALID_0;
- -- end if;
-
- -- when E_WR_SP_VALID_0 =>
- -- ScalpPacketValid12xS <= '0';
- -- WrSPStatexDN <= E_WR_SP_LAST_0;
-
- -- when E_WR_SP_LAST_0 =>
- -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
- -- WrSPStatexDN <= E_WR_SP_LAST_1;
- -- end if;
-
- -- when E_WR_SP_LAST_1 =>
- -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then
- -- ScalpPacketValid12xS <= '1';
- -- WrSPStatexDN <= E_WR_SP_VALID_1;
- -- end if;
-
- -- when E_WR_SP_VALID_1 =>
- -- ScalpPacketValid12xS <= '0';
- -- WrSPStatexDN <= E_WR_SP_WAIT;
-
- -- when E_WR_SP_WAIT =>
- -- if VioWrSpValidxS = '0' then
- -- WrSPStatexDN <= E_WR_SP_IDLE;
- -- end if;
-
- -- when others => null;
- -- end case;
- -- end process SpValidxP;
-
- -- end block WritePacketxB;
-
end block NetworkLayerxB;
end block ProgrammableLogicxB;
--
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