diff --git a/.gitignore b/.gitignore index fe87c3325fd1adf4c1a7ee2d21984f7f773b70f3..4fe44703299aba856047252b00d945b62af3eb92 100644 --- a/.gitignore +++ b/.gitignore @@ -95,6 +95,69 @@ ################ # Vivado folders ################ -designs/vivado/scalp_firmware/2019.2/lin64/scalp_firmware/ -designs/vivado/scalp_firmware/2019.2/lin64/.scripts/scalp_zynqps/ -tools/vivado_prj_creator \ No newline at end of file +designs/vivado/scalp_firmware/2020.2/lin64/.scripts/scalp_zynqps/ +designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/ +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.dcp +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.vhd +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xdc +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xml +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/ +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_clocks.xdc +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_core.vhd +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_ooc.xdc +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_sim_netlist.v +ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel_stub.v +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.dcp +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.vhd +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xdc +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xml +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel/ +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_clocks.xdc +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_core.vhd +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_ooc.xdc +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_sim_netlist.v +ips/hw/scalp_aurora_phy/src/ip_core/north_channel/north_channel_stub.v +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.dcp +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.vhd +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xdc +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xml +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel/ +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel_clocks.xdc +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel_core.vhd +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel_ooc.xdc +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel_sim_netlist.v +ips/hw/scalp_aurora_phy/src/ip_core/south_channel/south_channel_stub.v +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.dcp +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.vhd +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xdc +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xml +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel/ +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel_clocks.xdc +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel_core.vhd +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel_ooc.xdc +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel_sim_netlist.v +ips/hw/scalp_aurora_phy/src/ip_core/west_channel/west_channel_stub.v +ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.dcp +ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xml +ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo_ooc.xdc +ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo_sim_netlist.v +ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo_stub.v +ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/hdl/ +ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/synth/ +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.dcp +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.v +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xdc +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xml +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk_board.xdc +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk_clk_wiz.v +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk_ooc.xdc +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk_sim_netlist.v +ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk_stub.v +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/hdl/ +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/synth/ +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.dcp +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xdc +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xml +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl_ooc.xdc +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl_sim_netlist.v +ips/hw/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl_stub.v \ No newline at end of file