diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index fca63d4bf1a4b8995c5b784cadfb49e42abcae03..ede28d1e651443d916d3d4e1d3c567a6d8bdc90d 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
--- Last update: 2021-05-18
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
@@ -526,10 +526,10 @@ architecture arch of scalp_firmware is
attribute keep of AuroraClkSlavexC : signal is "true";
attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
- -- attribute mark_debug of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
- -- attribute mark_debug of WestRXS2MxD : signal is "true";
- -- attribute keep of WestRXS2MxD : signal is "true";
+ attribute mark_debug of WestRXM2SxD : signal is "true";
+ attribute keep of WestRXM2SxD : signal is "true";
+ attribute mark_debug of WestRXS2MxD : signal is "true";
+ attribute keep of WestRXS2MxD : signal is "true";
-- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
-- attribute keep of RXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
@@ -872,7 +872,7 @@ begin
-- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
- type t_write_sp_states is (E_WR_SP_IDLE_0, E_WR_SP_VALID_0, E_WR_SP_WAIT_0, E_WR_SP_IDLE_1, E_WR_LAST_1, E_WR_SP_VALID_1, E_WR_SP_WAIT_1);
+ type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID_0, E_WR_SP_UNVALID_0, E_WR_SP_VALID_1, E_WR_SP_WAIT);
signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Scalp Packets
@@ -891,19 +891,19 @@ begin
SpPayloadxD => C_SP_PAYLOAD_0);
signal ScalpPacketValid12xS : std_ulogic := '0';
--
- signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE_0;
- signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE_0;
+ signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
+ signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
signal VioWrSpValidxS : std_ulogic := '0';
--
signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
-- Scalp Packet
- attribute mark_debug of ScalpPacket0xD : signal is "true";
- attribute keep of ScalpPacket0xD : signal is "true";
+ -- attribute mark_debug of ScalpPacket0xD : signal is "true";
+ -- attribute keep of ScalpPacket0xD : signal is "true";
attribute mark_debug of ScalpPacketValid12xS : signal is "true";
attribute keep of ScalpPacketValid12xS : signal is "true";
- attribute mark_debug of ScalpPacketLocalxD : signal is "true";
- attribute keep of ScalpPacketLocalxD : signal is "true";
+ -- attribute mark_debug of ScalpPacketLocalxD : signal is "true";
+ -- attribute keep of ScalpPacketLocalxD : signal is "true";
-- VIO
-- attribute mark_debug of VioWrSpValidxS : signal is "true";
-- attribute keep of VioWrSpValidxS : signal is "true";
@@ -1127,7 +1127,7 @@ begin
ScalpRouterResetxRNA) is
begin -- process UpdateRegxP
if ScalpRouterResetxRNA = '0' then
- WrSPStatexDP <= E_WR_SP_IDLE_0;
+ WrSPStatexDP <= E_WR_SP_IDLE;
elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
WrSPStatexDP <= WrSPStatexDN;
end if;
@@ -1140,35 +1140,47 @@ begin
ScalpPacketValid12xS <= '0';
case WrSPStatexDP is
- when E_WR_SP_IDLE_0 =>
+ when E_WR_SP_IDLE =>
if VioWrSpValidxS = '1' then
ScalpPacketValid12xS <= '1';
WrSPStatexDN <= E_WR_SP_VALID_0;
end if;
when E_WR_SP_VALID_0 =>
ScalpPacketValid12xS <= '0';
- WrSPStatexDN <= E_WR_SP_WAIT_0;
- when E_WR_SP_WAIT_0 =>
- WrSPStatexDN <= E_WR_SP_IDLE_1;
+ WrSPStatexDN <= E_WR_SP_UNVALID_0;
- when E_WR_SP_IDLE_1 =>
- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
- WrSPStatexDN <= E_WR_LAST_1;
- end if;
-
- when E_WR_LAST_1 =>
- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then
- ScalpPacketValid12xS <= '1';
- WrSPStatexDN <= E_WR_SP_VALID_1;
- end if;
+ when E_WR_SP_UNVALID_0 =>
+ ScalpPacketValid12xS <= '1';
+ WrSPStatexDN <= E_WR_SP_VALID_1;
when E_WR_SP_VALID_1 =>
ScalpPacketValid12xS <= '0';
- WrSPStatexDN <= E_WR_SP_WAIT_1;
-
- when E_WR_SP_WAIT_1 =>
+ WrSPStatexDN <= E_WR_SP_WAIT;
+
+ -- when E_WR_SP_WAIT_0 =>
+ -- WrSPStatexDN <= E_WR_SP_IDLE_1;
+
+ -- when E_WR_SP_IDLE_1 =>
+ -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
+ -- WrSPStatexDN <= E_WR_LAST_1;
+ -- ScalpPacketValid12xS <= '1';
+ -- end if;
+
+ -- when E_WR_LAST_1 =>
+ -- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then
+ -- -- ScalpPacketValid12xS <= '1';
+ -- ScalpPacketValid12xS <= '0';
+ -- -- WrSPStatexDN <= E_WR_SP_VALID_1;
+ -- WrSPStatexDN <= E_WR_SP_WAIT_1;
+ -- end if;
+
+ -- -- when E_WR_SP_VALID_1 =>
+ -- -- ScalpPacketValid12xS <= '0';
+ -- -- WrSPStatexDN <= E_WR_SP_WAIT_1;
+
+ when E_WR_SP_WAIT =>
if VioWrSpValidxS = '0' then
- WrSPStatexDN <= E_WR_SP_IDLE_0;
+ WrSPStatexDN <= E_WR_SP_IDLE;
end if;
-- if VioWrSpValidxS = '0' then
-- WrSPStatexDN <= E_WR_SP_IDLE;
diff --git a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
index 04fd55cd020cbd4ec8bc64263f1a83a6f577f9d8..064050f5d1fe6e9caa502f61a08e354bb65ba172 100644
--- a/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
+++ b/ips/hw/scalp_aurora_phy/src/hdl/scalp_aurora_phy.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_aurora_phy
--
--- Last update: 2021-01-11
+-- Last update: 2021-05-19
--
---------------------------------------------------------------------------------
@@ -274,8 +274,8 @@ architecture arch of scalp_aurora_phy is
-- attribute keep of WestTXM2SxD : signal is "true";
-- attribute mark_debug of WestTXS2MxD : signal is "true";
-- attribute keep of WestTXS2MxD : signal is "true";
- -- attribute mark_debug of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
+ attribute mark_debug of WestRXM2SxD : signal is "true";
+ attribute keep of WestRXM2SxD : signal is "true";
-- attribute mark_debug of WestTXNFCM2SxD : signal is "true";
-- attribute keep of WestTXNFCM2SxD : signal is "true";
-- attribute mark_debug of WestTXNFCS2MxD : signal is "true";