diff --git a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
index 7f6d7347688a0b178bece5eb880d044e9629e2d6..8fc403b192c0dd1aefae80f0ad8226103df27c44 100644
--- a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
+++ b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
@@ -304,6 +304,8 @@ architecture arch of scalp_mipi is
     signal GPIO0IxD          : std_logic_vector(31 downto 0)                      := (others => '0');
     signal GPIO0OxD          : std_logic_vector(31 downto 0)                      := (others => '0');
     signal GPIO0TxD          : std_logic_vector(31 downto 0)                      := (others => '0');
+    signal Csi2RstnxS        : std_logic                                          := '0';
+    signal DmaRstnxS         : std_logic                                          := '0';
     -- Camera MIPI signals
     signal MipiClockHsNxC : std_logic                                             := '0';
     signal MipiClockHsPxC : std_logic                                             := '0';
@@ -411,7 +413,9 @@ begin
                 MipiDataHsN      => MipiDataHsNxD,
                 MipiDataHsP      => MipiDataHsPxD,
                 MipiDataLpN      => MipiDataLpNxD,
-                MipiDataLpP      => MipiDataLpPxD
+                MipiDataLpP      => MipiDataLpPxD,
+                Csi2Rstn         => Csi2RstnxS,
+                DmaRstn          => DmaRstnxS
             );
 
     end block ProcessingSystemxB;
@@ -434,17 +438,29 @@ begin
             I2c1SdaIxS  <= LVDS2V5Bottom5PxSIO;
 --            LVDS2V5Bottom5PxSIO <= GPIO0OxD(2) when GPIO0TxD(2)='0' else 'Z';
 --            GPIO0IxD(2)  <= LVDS2V5Bottom5PxSIO;
+
             -- Camera I2C SCL tri-state buffer
             LVDS2V5Bottom5NxSIO <= I2c1SclOxS when I2c1SclTxS='0' else 'Z';
             I2c1SclIxS  <= LVDS2V5Bottom5NxSIO;
 --            LVDS2V5Bottom5NxSIO <= GPIO0OxD(3) when GPIO0TxD(3)='0' else 'Z';
 --            GPIO0IxD(3)  <= LVDS2V5Bottom5NxSIO;
+
+            -- DMA nReset tri-state buffer (GPIO0_0)
+            DmaRstnxS <=  GPIO0OxD(0) when  GPIO0TxD(0)='0' else 'Z';
+            GPIO0IxD(0)  <= DmaRstnxS;
+            
+            -- CSI2 nReset tri-state buffer (GPIO0_1)
+            Csi2RstnxS <=  GPIO0OxD(1) when  GPIO0TxD(1)='0' else 'Z';
+            GPIO0IxD(1)  <= Csi2RstnxS;
+            
             -- Camera PWUP tri-state buffer (GPIO0_4)
             LVDS2V5Bottom6NxSIO <=  GPIO0OxD(4) when  GPIO0TxD(4)='0' else 'Z';
             GPIO0IxD(4)  <= LVDS2V5Bottom6NxSIO;
+            
             -- Camera GPIO tri-state buffer (GPIO0_5)
             LVDS2V5Bottom6PxSIO <=  GPIO0OxD(5) when  GPIO0TxD(5)='0' else 'Z';
             GPIO0IxD(5)  <= LVDS2V5Bottom6PxSIO;
+            
             -- MIPI signal assignement
             MipiPhyClockHsNxAS : MipiClockHsNxC   <= Clk2V5BottomNxCI;
             MipiPhyClockHsPxAS : MipiClockHsPxC   <= Clk2V5BottomPxCI;
diff --git a/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
index 87d84c4235fc15ef6700c576737409ea3766245f..aec32d0d3650f606ea1a8b097e8e37193e5a2fbc 100644
--- a/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
@@ -87,7 +87,9 @@ entity scalp_mipi_zynqps_wrapper is
         MipiDataHsN         : in    std_logic_vector (1 downto 0);
         MipiDataHsP         : in    std_logic_vector (1 downto 0);
         MipiDataLpN         : in    std_logic_vector (1 downto 0);
-        MipiDataLpP         : in    std_logic_vector (1 downto 0)
+        MipiDataLpP         : in    std_logic_vector (1 downto 0);
+        Csi2Rstn            : in    std_logic;
+        DmaRstn             : in    std_logic
 );
 
 end scalp_mipi_zynqps_wrapper;
@@ -149,7 +151,9 @@ begin
             MIPI_data_hs_n      => MipiDataHsN,
             MIPI_data_hs_p      => MipiDataHsP,
             MIPI_data_lp_n      => MipiDataLpN,
-            MIPI_data_lp_p      => MipiDataLpP
+            MIPI_data_lp_p      => MipiDataLpP,
+            Csi2Rstn            => Csi2Rstn,
+            DmaRstn             => DmaRstn
             );
 
 end arch;
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
index 07839b7084a54ccc947a04968b0dad4796bbba4f..a933bf4c64153f49c84a4bdc9c86daaf757d1120 100644
--- a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
@@ -122,6 +122,8 @@ set bCheckIPsPassed 1
 set bCheckIPs 1
 if { $bCheckIPs == 1 } {
    set list_check_ips "\ 
+xilinx.com:ip:axi_data_fifo:2.1\
+xilinx.com:ip:axi_intc:4.1\
 xilinx.com:ip:axis_subset_converter:1.1\
 xilinx.com:ip:clk_wiz:6.0\
 xilinx.com:ip:xlconstant:1.1\
@@ -210,6 +212,8 @@ proc create_root_design { parentCell } {
 
 
   # Create ports
+  set Csi2Rstn [ create_bd_port -dir I -type rst Csi2Rstn ]
+  set DmaRstn [ create_bd_port -dir I -type rst DmaRstn ]
   set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
   set_property -dict [ list \
    CONFIG.FREQ_HZ {125000000} \
@@ -228,6 +232,20 @@ proc create_root_design { parentCell } {
   set WrDataxDO [ create_bd_port -dir O -from 31 -to 0 WrDataxDO ]
   set WrValidxSO [ create_bd_port -dir O WrValidxSO ]
 
+  # Create instance: axi_data_fifo_0, and set properties
+  set axi_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_data_fifo:2.1 axi_data_fifo_0 ]
+  set_property -dict [ list \
+   CONFIG.DATA_WIDTH {64} \
+   CONFIG.READ_FIFO_DELAY {1} \
+   CONFIG.READ_FIFO_DEPTH {512} \
+ ] $axi_data_fifo_0
+
+  # Create instance: axi_intc_0, and set properties
+  set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
+  set_property -dict [ list \
+   CONFIG.C_IRQ_CONNECTION {1} \
+ ] $axi_intc_0
+
   # Create instance: axi_mem_intercon, and set properties
   set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
   set_property -dict [ list \
@@ -241,7 +259,7 @@ proc create_root_design { parentCell } {
    CONFIG.M_HAS_TLAST {1} \
    CONFIG.M_HAS_TREADY {1} \
    CONFIG.M_HAS_TSTRB {1} \
-   CONFIG.M_TDATA_NUM_BYTES {6} \
+   CONFIG.M_TDATA_NUM_BYTES {3} \
    CONFIG.M_TDEST_WIDTH {1} \
    CONFIG.M_TID_WIDTH {1} \
    CONFIG.M_TUSER_WIDTH {1} \
@@ -249,11 +267,11 @@ proc create_root_design { parentCell } {
    CONFIG.S_TDATA_NUM_BYTES {2} \
    CONFIG.S_TDEST_WIDTH {10} \
    CONFIG.S_TUSER_WIDTH {1} \
-   CONFIG.TDATA_REMAP {32'b00000000000000000000000000000000,tdata[15:0]} \
+   CONFIG.TDATA_REMAP {8'b00000000,tdata[15:0]} \
    CONFIG.TDEST_REMAP {tdest[0:0]} \
-   CONFIG.TKEEP_REMAP {6'b111111} \
+   CONFIG.TKEEP_REMAP {3'b111} \
    CONFIG.TLAST_REMAP {tlast[0]} \
-   CONFIG.TSTRB_REMAP {6'b111111} \
+   CONFIG.TSTRB_REMAP {3'b111} \
    CONFIG.TUSER_REMAP {tuser[0:0]} \
  ] $axis_subset_converter_0
 
@@ -290,7 +308,7 @@ proc create_root_design { parentCell } {
   # Create instance: irq_xlconcat, and set properties
   set irq_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 irq_xlconcat ]
   set_property -dict [ list \
-   CONFIG.NUM_PORTS {1} \
+   CONFIG.NUM_PORTS {3} \
  ] $irq_xlconcat
 
   # Create instance: mipi_csi2_rx_subsyst_0, and set properties
@@ -299,6 +317,8 @@ proc create_root_design { parentCell } {
    CONFIG.CMN_NUM_LANES {2} \
    CONFIG.CMN_PXL_FORMAT {YUV422_8bit} \
    CONFIG.C_DPHY_LANES {2} \
+   CONFIG.C_EXDES_BOARD {ZCU102} \
+   CONFIG.DPY_EN_REG_IF {false} \
  ] $mipi_csi2_rx_subsyst_0
 
   # Create instance: processing_system7_0, and set properties
@@ -713,6 +733,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {11} \
    CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
    CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \
+   CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
    CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
    CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
    CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
@@ -751,15 +772,15 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_USB_RESET_ENABLE {1} \
    CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
    CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
-   CONFIG.PCW_USE_S_AXI_GP0 {1} \
-   CONFIG.PCW_USE_S_AXI_HP0 {0} \
+   CONFIG.PCW_USE_S_AXI_GP0 {0} \
+   CONFIG.PCW_USE_S_AXI_HP0 {1} \
    CONFIG.PCW_USE_S_AXI_HP3 {0} \
  ] $processing_system7_0
 
   # Create instance: ps7_0_axi_periph, and set properties
   set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
   set_property -dict [ list \
-   CONFIG.NUM_MI {4} \
+   CONFIG.NUM_MI {5} \
    CONFIG.NUM_SI {2} \
  ] $ps7_0_axi_periph
 
@@ -807,8 +828,8 @@ proc create_root_design { parentCell } {
   set v_frmbuf_wr_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_frmbuf_wr:2.2 v_frmbuf_wr_0 ]
   set_property -dict [ list \
    CONFIG.AXIMM_ADDR_WIDTH {32} \
-   CONFIG.AXIMM_DATA_WIDTH {128} \
-   CONFIG.C_M_AXI_MM_VIDEO_DATA_WIDTH {128} \
+   CONFIG.AXIMM_DATA_WIDTH {64} \
+   CONFIG.C_M_AXI_MM_VIDEO_DATA_WIDTH {64} \
    CONFIG.HAS_BGR8 {1} \
    CONFIG.HAS_RGB8 {0} \
    CONFIG.HAS_UYVY8 {1} \
@@ -817,7 +838,7 @@ proc create_root_design { parentCell } {
    CONFIG.MAX_COLS {640} \
    CONFIG.MAX_NR_PLANES {1} \
    CONFIG.MAX_ROWS {480} \
-   CONFIG.SAMPLES_PER_CLOCK {2} \
+   CONFIG.SAMPLES_PER_CLOCK {1} \
  ] $v_frmbuf_wr_0
 
   # Create instance: vio_0, and set properties
@@ -829,7 +850,8 @@ proc create_root_design { parentCell } {
 
   # Create interface connections
   connect_bd_intf_net -intf_net MIPI_1 [get_bd_intf_ports MIPI] [get_bd_intf_pins mipi_csi2_rx_subsyst_0/mipi_phy_if]
-  connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_GP0]
+  connect_bd_intf_net -intf_net axi_data_fifo_0_M_AXI [get_bd_intf_pins axi_data_fifo_0/M_AXI] [get_bd_intf_pins axi_mem_intercon/S00_AXI]
+  connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
   connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins axis_subset_converter_0/M_AXIS] [get_bd_intf_pins v_frmbuf_wr_0/s_axis_video]
   connect_bd_intf_net -intf_net mipi_csi2_rx_subsyst_0_video_out [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins mipi_csi2_rx_subsyst_0/video_out]
 connect_bd_intf_net -intf_net [get_bd_intf_nets mipi_csi2_rx_subsyst_0_video_out] [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_2_AXIS]
@@ -847,21 +869,26 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins mipi_csi2_rx_subsyst_0/csirxss_s_axi] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins v_frmbuf_wr_0/s_axi_CTRL]
-  connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
+  connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins ps7_0_axi_periph/M04_AXI]
+  connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_data_fifo_0/S_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
 
   # Create port connections
+  connect_bd_net -net Csi2Rstn_1 [get_bd_ports Csi2Rstn] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aresetn]
+  connect_bd_net -net DmaRstn_1 [get_bd_ports DmaRstn] [get_bd_pins axi_data_fifo_0/aresetn] [get_bd_pins axis_subset_converter_0/aresetn]
   connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
   connect_bd_net -net RdDataxDI_0_1 [get_bd_ports RdDataxDI] [get_bd_pins scalp_axi4lite_0/RdDataxDI]
   connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
+  connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins processing_system7_0/IRQ_F2P]
   connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mipi_csi2_rx_subsyst_0/dphy_clk_200M]
   connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
-  connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
-  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins ps7_0_axi_periph/S01_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins vio_0/clk]
+  connect_bd_net -net irq_xlconcat_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins irq_xlconcat/dout]
+  connect_bd_net -net mipi_csi2_rx_subsyst_0_csirxss_csi_irq [get_bd_pins irq_xlconcat/In1] [get_bd_pins mipi_csi2_rx_subsyst_0/csirxss_csi_irq]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins ps7_0_axi_periph/S01_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins vio_0/clk]
   connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
   connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
   connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
   connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
-  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axis_subset_converter_0/aresetn] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins ps7_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
+  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins ps7_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
   connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO]
   connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
   connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
@@ -871,20 +898,19 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
   connect_bd_net -net scalp_safe_firmware_0_RgbLedsCtrlPortxDO [get_bd_ports RgbLedsCtrlPortxDO] [get_bd_pins scalp_safe_firmware_0/RgbLedsCtrlPortxDO]
   connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
   connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
+  connect_bd_net -net v_frmbuf_wr_0_interrupt [get_bd_pins irq_xlconcat/In2] [get_bd_pins v_frmbuf_wr_0/interrupt]
   connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
 
   # Create address segments
+  assign_bd_address -offset 0x41800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
   assign_bd_address -offset 0x43C20000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg] -force
   assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr] -force
   assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
   assign_bd_address -offset 0x43C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs v_frmbuf_wr_0/s_axi_CTRL/Reg] -force
-  assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM] -force
-  assign_bd_address -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR] -force
+  assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
 
   # Exclude Address Segments
   exclude_bd_addr_seg -offset 0x43C20000 -range 0x00001000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg]
-  exclude_bd_addr_seg -offset 0xE0000000 -range 0x00400000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_IOP]
-  exclude_bd_addr_seg -offset 0x40000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0]
   exclude_bd_addr_seg -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr]
   exclude_bd_addr_seg -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr]