diff --git a/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd b/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
index 4b596e8c6bd5c1edc0780ad1d07726e34f482f6d..1c4f13e6907d2ec7ea0f0ae997cea7a8677ded63 100644
--- a/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
+++ b/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: scalp_firmware
 --
--- Last update: 2021-01-18
+-- Last update: 2021-03-12
 --
 ---------------------------------------------------------------------------------
 
@@ -291,6 +291,14 @@ architecture arch of scalp_safe_firmware is
     -- Zynq Reg Bank
     signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
     signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    -- RGB Leds
+    signal Led12V5RxS     : std_ulogic                                         := '0';
+    signal Led12V5GxS     : std_ulogic                                         := '0';
+    signal Led12V5BxS     : std_ulogic                                         := '0';
+    signal Led22V5RxS     : std_ulogic                                         := '0';
+    signal Led22V5GxS     : std_ulogic                                         := '0';
+    signal Led22V5BxS     : std_ulogic                                         := '0';
+
 
     -- Attributes
     attribute mark_debug         : string;
@@ -352,6 +360,19 @@ begin
     ProgrammableLogicxB : block is
     begin  -- block ProgrammableLogicxB        
 
+        EntityIOxB : block is
+        begin
+
+            Led12V5RxAS : Led12V5RxSO <= Led12V5RxS;
+            Led12V5GxAS : Led12V5GxSO <= Led12V5GxS;
+            Led12V5BxAS : Led12V5BxSO <= Led12V5BxS;
+            Led22V5RxAS : Led22V5RxSO <= Led22V5RxS;
+            Led22V5GxAS : Led22V5GxSO <= Led22V5GxS;
+            Led22V5BxAS : Led22V5BxSO <= Led22V5BxS;
+
+        end block EntityIOxB;
+
+
         ZynqRegBankxB : block is
         begin  -- block ZynqRegBankxB
 
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..604d0ee15afbcdbc01bc6975319d9dd134a37836
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,37 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# Text attributes
+set RESET [exec tput sgr0]
+set BOLD [exec tput bold]
+set ITALIC [exec tput sitm]
+set BLINK [exec tput blink]
+set HIGHL [exec tput smso]
+
+# Text colors
+set RED [exec tput setaf 1]
+set GREEN [exec tput setaf 2]
+set YELLOW [exec tput setaf 3]
+set BLUE [exec tput setaf 4]
+set MAGENTA [exec tput setaf 5]
+set CYAN [exec tput setaf 6]
+set WHITE [exec tput setaf 7]
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/clean_prj_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/clean_prj_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c98f844cdfb4bb339c44c102b4653ebc64d600a8
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/clean_prj_scalp_user_firmware.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_user_firmware/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7ad236ba8f03a8bfbf2507be97a3c2da6af02a04
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_user_firmware.tcl -notrace
+echo "> Done"
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..87a9fa740f281953eada3e78d31bbccb51bf8c73
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.tcl
@@ -0,0 +1,166 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_user_firmware'
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "DESIGN_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	# add HDL sources
+	set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list    
+	# add the constraints file (XDC)
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
+add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
+	set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_user_firmware.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/scalp_user_firmware.xdc]
+
+	# add IPs source file
+  
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	# components sources are stored in an external directory
+	# add the project component
+	set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list
+	# add IPs source file
+  
+	# add IP-XACT source file
+	#add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+foreach j $vhdl_src_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
+# Set packages libraries if any
+#set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+foreach j $vhdl_sim_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
+# Add packages sources
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
+
+# Add SoC wrapper sources files
+	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
+	add_files -norecurse $vhdl_soc_file_list
+	foreach j $vhdl_soc_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+print_status "Add SoC wrapper sources" "OK"
+print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..86885daba4bb66b61e5e70d58fdca400534b86ef
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.sh
@@ -0,0 +1,29 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to SDK
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Export the hardware design to SDK"
+
+vivado -nojournal -nolog -mode tcl -source ./export_hw_scalp_user_firmware.tcl -notrace
+
+echo "> Done"
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..154ab245aa9ccb612f14d0ec56c9a8e249c1fbf0
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.tcl
@@ -0,0 +1,42 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to SDK
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+
+# Initialize workspace directories name
+set prj_name "scalp_user_firmware"
+set impl_dir "${PRJ_DIR}/${prj_name}/${prj_name}.runs/impl_1/"
+set export_dir "${PRJ_DIR}/${prj_name}/${prj_name}.sdk"
+print_status "Initialize workspace directories name" "OK"
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
+print_status "Open project $prj_name" "OK"
+
+# export the hardware
+file mkdir $export_dir
+file copy -force $impl_dir/$prj_name.sysdef $export_dir/$prj_name.hdf
+print_status "Export hardware to SDK" "OK"
+
+exit
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e6c52718d85b46fb0405f06cbf06825176cfc49f
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate bitstream file
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+PRJ_DIR=..
+
+echo "> Generate bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./gen_bitstream_scalp_user_firmware.tcl -notrace
+
+echo "> Copy bitstream file in current directory..."
+mkdir -p ${PRJ_DIR}/bitstream/
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.runs/impl_1/scalp_user_firmware.bit ${PRJ_DIR}/bitstream/scalp_user_firmware.bit
+
+echo "> Done"
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ca9de4e3f07e7223b047f6c8c7f4c8986a9dc49c
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.tcl
@@ -0,0 +1,56 @@
+#!/usr/bin/tcl
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to generate bitstream file
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
+update_compile_order -fileset sources_1
+print_status "Open project $prj_name" "OK"
+
+# Run synthesis
+print_status "Run synthesis" "IN_PROGRESS"
+launch_runs synth_1
+wait_on_run synth_1
+print_status "Run synthesis" "OK"
+
+# Run implementation
+print_status "Run implementation" "IN_PROGRESS"
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+wait_on_run impl_1
+print_status "Run implementation" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time on the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..18ddcb4af897ede46e23355603a01e9b893648dd
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.sh
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+PRJ_DIR=..
+
+echo "> Generate software applications..."
+xsdk -batch -source ./gen_sw_apps_scalp_user_firmware.tcl -notrace
+
+echo "> Copy application file in current directory..."
+mkdir -p ${PRJ_DIR}/app/
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.sdk/scalp_user_firmware_app/Debug/scalp_user_firmware_app.elf ${PRJ_DIR}/app/scalp_user_firmware_app.elf
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.sdk/scalp_user_firmware_hw_platform_0/system.hdf ${PRJ_DIR}/app/scalp_user_firmware.hdf
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.sdk/scalp_user_firmware_hw_platform_0/ps7_init.tcl ${PRJ_DIR}/app/ps7_init.tcl
+
+echo "> Done"
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8e0532bbb1d9700b5bb929cd7885d5e1acb65dcd
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.tcl
@@ -0,0 +1,74 @@
+#!/usr/bin/tcl
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to generate software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+
+set workspace_dir "${PRJ_DIR}/$prj_name/$prj_name.sdk/"
+set hw_spec_file "$prj_name.hdf"
+
+set hw_platform_name "${prj_name}_hw_platform_0"
+set proc_name "ps7_cortexa9_0"
+set os_name "freertos823_xilinx"
+
+set bsp_name "${prj_name}_bsp"
+set app_name "${prj_name}_app"
+
+# Set the SDK workspace
+setws $workspace_dir
+print_status "Set workspace directory" "OK"
+
+# Create the hardware project
+sdk createhw -name $hw_platform_name -hwspec $workspace_dir/$hw_spec_file
+print_status "Create hardware project" "OK"
+
+# Create the FreeRTOS BSP
+sdk createbsp -name $bsp_name -hwproject $hw_platform_name -proc $proc_name -os $os_name
+print_status "Create FreeRTOS BSP project" "OK"
+
+# Create the empty application
+sdk createapp -name $app_name -hwproject $hw_platform_name -proc $proc_name -lang C -app {Empty Application} -os $os_name -bsp $bsp_name
+print_status "Create Empty Application project" "OK"
+
+# Import source files
+sdk importsources -name $app_name -path ${PRJ_DIR}/../src/sw/ -linker-script
+print_status "Import project source files" "OK"
+
+# Set the include directories
+configapp -app $app_name include-path "${PRJ_DIR}/../src/inc/"
+configapp -app $app_name include-path "${PRJ_DIR}/../src/lib/"
+configapp -app $app_name include-path "${PRJ_DIR}/../src/mod/"
+print_status "Set includes directories" "OK"
+
+# Build the projects
+print_status "Build BSP project" "IN_PROGRESS"
+sdk projects -build -type bsp -name $bsp_name
+print_status "Build BSP project" "OK"
+
+print_status "Build application project" "IN_PROGRESS"
+sdk projects -build -type app -name $app_name
+print_status "Build application project" "OK"
+
+exit
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..507a22205771b8aa9a0f72f0379f48415222bb02
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Load bitstream file
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Load bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./load_bitstream_scalp_user_firmware.tcl -notrace
+echo "> Done"
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..53a39bccecb5f1eda56e7db49c660f638da887ea
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.tcl
@@ -0,0 +1,61 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to load FPGA bitstream
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+
+# Open the hardware manager and connect to the hardware server
+open_hw
+print_status "Open hardware manager" "OK"
+connect_hw_server -url localhost:3121
+print_status "Connect to hardware server" "OK"
+
+# Get the hardware target and open it
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
+open_hw_target
+print_status "Open hardware target" "OK"
+
+# Display targets list
+set index -1
+set targets [lindex [get_hw_devices]]
+puts "Found target(s):"
+foreach target $targets {
+  incr index
+  puts "$index : $target"
+}
+puts "Which target do you want to program?"
+set sel_target [read stdin 1]
+
+# Set the program file
+set_property PROGRAM.FILE ${PRJ_DIR}/bitstream/$prj_name.bit [lindex [get_hw_devices] $sel_target]
+current_hw_device [lindex [get_hw_devices] $sel_target]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] $sel_target]
+print_status "Set program file" "OK"
+
+# Program the device
+print_status "Program device" "IN_PROGRESS"
+program_hw_device [lindex [get_hw_devices] $sel_target]
+print_status "Program device" "OK"
+
+exit
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e2ecfb264d907bda5d9417395ed11786cf3a14a0
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Load software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Load software application..."
+xsdk -batch -source ./load_sw_app_scalp_user_firmware.tcl -notrace
+echo "> Done"
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..20750edc666573349ed585c67fec98a85c874eb2
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.tcl
@@ -0,0 +1,64 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to load software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+set hw_platform_name "${prj_name}_hw_platform_0"
+set app_name "${prj_name}_app"
+
+# Connect to the hardware server
+connect -url tcp:127.0.0.1:3121
+print_status "Connect to hardware server" "OK"
+
+# Connect to the processor
+targets 2
+print_status "Connect to ARM Cortex-A9 MPCore #0" "OK"
+
+# Load the hardware design
+loadhw -hw ${PRJ_DIR}/app/$prj_name.hdf
+print_status "Load hardware design" "OK"
+
+# Reset the processor
+rst -processor
+print_status "Reset ARM Cortex-A9 MPCore #0" "OK"
+
+# Initialize the MPSoC
+source ${PRJ_DIR}/app/ps7_init.tcl
+ps7_init
+ps7_post_config
+print_status "Initialize PS7" "OK"
+
+# Load the application
+dow ${PRJ_DIR}/app/$app_name.elf
+print_status "Load software application" "OK"
+
+# Run the application
+con
+print_status "Run software application" "OK"
+
+# Disconnect from the target
+disconnect
+print_status "Disconnect from hardware server" "OK"
+
+exit
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/open_prj_scalp_user_firmware.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/open_prj_scalp_user_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..85747c6b9f81f57ef7b005eb04d4a0365884d101
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/open_prj_scalp_user_firmware.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_user_firmware/scalp_user_firmware.xpr
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3416a9d59911eb94783345198d8d1c3083137e35
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+    # Fix the directory name, this ensures the directory name is in the
+    # native format for the platform and contains a final directory seperator
+    set basedir [string trimright [file join [file normalize $basedir] { }]]
+    set fileList {}
+
+    # Look in the current directory for matching files, -type {f r}
+    # means ony readable normal files are looked at, -nocomplain stops
+    # an error being thrown if the returned list is empty
+    foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+        lappend fileList $fileName
+    }
+
+    # Now look for any sub direcories in the current directory
+    foreach dirName [glob -nocomplain -type {d  r} -path $basedir *] {
+        # Recusively call the routine on the sub directory and append any
+        # new files to the results
+        set subDirList [findFiles $dirName $pattern]
+        if { [llength $subDirList] > 0 } {
+            foreach subDirFile $subDirList {
+                lappend fileList $subDirFile
+            }
+        }
+    }
+    return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+    set MAX_STR_LENGTH 70
+    source .prompt_colors.tcl
+    puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/lin64/setup.sh b/designs/vivado/scalp_user_firmware/2020.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..54a8bd6f5d400eb149dbb7eff930668b87560d14
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/lin64/setup.sh
@@ -0,0 +1,30 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_user_firmware.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_user_firmware.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_user_firmware.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_user_firmware.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_user_firmware.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_user_firmware.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_scalp_user_firmware.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_user_firmware.sh && cd ..'
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/ibert_constraints.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/ibert_constraints.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..602b523f941544701ea24e62603c5fb40558d97e
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/ibert_constraints.xdc
@@ -0,0 +1,382 @@
+# Taken from IBERT example design
+
+##
+## Icon Constraints
+##
+create_clock -name J_CLK -period 30 [get_pins -of_objects [get_cells gen_ibert.ibert_inst/inst/bscan_inst/SERIES7_BSCAN.bscan_inst] -filter {name =~ *DRCK}]
+set_clock_groups -group [get_clocks J_CLK] -asynchronous
+##
+## System clock Divider paramter values
+##
+set_property CLKFBOUT_MULT_F 8.000 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property DIVCLK_DIVIDE 1 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property CLKIN1_PERIOD 8.0 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+set_property CLKOUT0_DIVIDE_F 10.000 [get_cells gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM]
+##
+## Refclk constraints
+##
+set_clock_groups -group [get_clocks GTP_REF_CLK_* -include_generated_clocks] -asynchronous
+#
+#
+#
+##
+## TX/RX out clock constraints
+##
+# GT X0Y0
+create_clock -name Q0_RXCLK0 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[0].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK0] -asynchronous
+create_clock -name  Q0_TX0 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[0].u_ch/u_gtpe2_channel/TXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_TX0] -asynchronous
+# GT X0Y1
+create_clock -name Q0_RXCLK1 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[1].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK1] -asynchronous
+# GT X0Y2
+create_clock -name Q0_RXCLK2 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[2].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK2] -asynchronous
+# GT X0Y3
+create_clock -name Q0_RXCLK3 -period 2.56 [get_pins {gen_ibert.ibert_inst/inst/QUAD[0].u_q/CH[3].u_ch/u_gtpe2_channel/RXOUTCLK}]
+set_clock_groups -group [get_clocks Q0_RXCLK3] -asynchronous
+##
+## Timing constraint
+##
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins gen_ibert.ibert_inst/inst/SYSCLK_DIVIDER.U_GT_MMCM/CLKIN1]
+##
+## GTPE2 Channel and Common Loc constraints
+##
+set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[0].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[1].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[2].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_CHANNEL_X0Y3 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[3].u_ch/u_gtpe2_channel]
+set_property LOC GTPE2_COMMON_X0Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+##
+## BUFH Loc constraints for TX/RX userclks
+##
+set_property LOC BUFHCE_X1Y0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/local_txusr.u_txusr]
+set_property LOC BUFHCE_X1Y1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr0]
+set_property LOC BUFHCE_X1Y2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr1]
+set_property LOC BUFHCE_X1Y3 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr2]
+set_property LOC BUFHCE_X1Y4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_clocking/rx_ind.u_rxusr3]
+##
+## MGT reference clock BUFFERS location constraints
+##
+
+
+set_property LOC IBUFDS_GTE2_X0Y0 [get_cells i_clocks.ibufds_GTP_REF_CLK_0]
+set_property LOC IBUFDS_GTE2_X0Y1 [get_cells i_clocks.ibufds_GTP_REF_CLK_1]
+
+##
+## Attribute values for GTPE2 Channel and Common instances
+##
+##
+##remove ASYNC_REG property
+##
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_310/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_30E/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_312/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_314/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+
+set_property ASYNC_REG false [get_cells {gen_ibert.ibert_inst/inst/QUAD[*].u_q/CH[*].u_ch/U_CHANNEL_REGS/reg_306/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[*]}]
+
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdb_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg]
+
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg]
+set_property ASYNC_REG false [get_cells gen_ibert.ibert_inst/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdb_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg]
+
+##
+## Attribute Values for QUAD[0] - Channel
+##
+ ##------Comma Detection and Alignment---------
+set_property ALIGN_COMMA_DOUBLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_COMMA_ENABLE 10'b0001111111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_COMMA_WORD 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_MCOMMA_DET "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_MCOMMA_VALUE 10'b1010000011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_PCOMMA_DET "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ALIGN_PCOMMA_VALUE 10'b0101111100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_MCOMMA_DETECT "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_PCOMMA_DETECT "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DEC_VALID_COMMA_ONLY "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property DMONITOR_CFG 24'h000A00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##--------------Channel Bonding--------------
+set_property CBCC_DATA_SOURCE_SEL "DECODED" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_KEEP_ALIGN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_MAX_SKEW 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_LEN 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_1 10'b0101111100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_1_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_1 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CHAN_BOND_SEQ_2_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Clock Correction------------
+set_property CLK_COR_KEEP_IDLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_MAX_LAT 9.0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_MIN_LAT 7.0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_PRECEDENCE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_CORRECT_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_REPEAT_WAIT 0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_LEN 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_1 10'b0100011100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_1_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_1 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_2 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_3 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_4 10'b0100000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CLK_COR_SEQ_2_USE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Channel PLL----------------------
+set_property RXOUT_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXOUT_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------Eyescan--------------
+set_property ES_CONTROL 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_ERRDET_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_EYE_SCAN_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_HORZ_OFFSET 12'h002 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_PMA_CFG 10'b0000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_PRESCALE 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_QUALIFIER 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_QUAL_MASK 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_SDATA_MASK 80'h00000000000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ES_VERT_OFFSET 9'b010000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_DESKEW_SEQ_ENABLE 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_LANE_DESKEW_CFG 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property FTS_LANE_DESKEW_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property GEARBOX_MODE 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property OUTREFCLK_SEL_INV 2'b11 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PCS_PCIE_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PCS_RSVD_ATTR 48'h000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV 32'h00000333 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV2 32'h00002040 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV3 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV4 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV5 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV6 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV7 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_BIAS_CFG 16'b0000111100110011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_PREDRIVER_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------Rx Elastic Buffer and Phase alignment-------------
+set_property RXBUF_ADDR_MODE "FAST" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EIDLE_HI_CNT 4'b1000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EIDLE_LO_CNT 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_BUFFER_CFG 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_CB_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_COMMAALIGN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_EIDLE "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_RESET_ON_RATE_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUFRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_OVFLW 61 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_OVRD "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXBUF_THRESH_UNDFLW 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_CFG 16'h0010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_LCFG 9'h020 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXDLY_TAP_CFG 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------RX driver, OOB signalling, Coupling and Eq., CDR------------
+set_property RXCDR_CFG 83'h0001107FE206021041010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDRFREQRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_FR_RESET_ON_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_HOLD_DURING_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_LOCK_CFG 6'b001001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDR_PH_RESET_ON_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXCDRPHRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOOB_CFG 7'b0000110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------RX Interface-------------------------
+set_property RX_DATA_WIDTH 16 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CLK25_DIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CM_SEL 2'b11 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CM_TRIM 4'b1010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DDI_SEL 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DEBUG_CFG 12'b000000000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##------------RX Decision Feedback Equalizer(DFE)-------------
+set_property RX_DEFER_RESET_BUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_OS_CFG 13'b0000010000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_DISPERR_SEQ_MATCH "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------RX Gearbox---------------------------
+set_property RXGEARBOX_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXISCANRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG  14'b00001111110000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG2 5'b01010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HF_CFG3 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_HOLD_DURING_EIDLE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_INCM_CFG 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_IPCM_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_LF_CFG  18'b000000001111110000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_LF_CFG2 5'b01010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_OSINT_CFG 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPCSRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPH_CFG 24'hC00002 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPHDLY_CFG 24'h084000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPH_MONITOR_SEL 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPMARESET_TIME 5'b00011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------PRBS Detection-----------------------
+set_property RXPRBS_ERR_LOOPBACK 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_SIG_VALID_DLY 10 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSLIDE_AUTO_WAIT 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSLIDE_MODE "off" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_XCLK_SEL "RXREC" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------RX Attributes for PCI Express/SATA/SAS----------
+set_property PD_TRANS_TIME_FROM_P2 12'h03c [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PD_TRANS_TIME_NONE_P2 8'h3c [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PD_TRANS_TIME_TO_P2 8'h64 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SAS_MAX_COM 64 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SAS_MIN_COM 36 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_BURST_SEQ_LEN 4'b1111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_BURST_VAL 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_PLL_CFG VCO_3000MHZ [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_EIDLE_VAL 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_BURST 8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_INIT 21 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MAX_WAKE 7 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_BURST 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_INIT 12 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SATA_MIN_WAKE 4 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property SHOW_REALIGN_COMMA "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TERM_RCAL_CFG 15'b100001000010000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TERM_RCAL_OVRD 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TRANS_TIME_RATE 8'h0E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TST_RSV 32'h00000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##------------TX Buffering and Phase Alignment----------------
+set_property TXBUF_EN "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXBUF_RESET_ON_RATE_CHANGE "TRUE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------TX Interface-------------------------
+set_property TX_DATA_WIDTH 16 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DEEMPH0 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DEEMPH1 6'b000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_CFG 16'h0010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_LCFG 9'h020 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXDLY_TAP_CFG 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_CLK25_DIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##--------------TX Driver and OOB Signalling------------------
+set_property TX_EIDLE_ASSERT_DELAY 3'b110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_EIDLE_DEASSERT_DELAY 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_LOOPBACK_DRIVE_HIZ "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MAINCURSOR_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_DRIVE_MODE "DIRECT" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##-----------------------TX Gearbox---------------------------
+set_property TXGEARBOX_EN "FALSE" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##----------------TX Attributes for PCI Express---------------
+set_property TX_MARGIN_FULL_0 7'b1001110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_1 7'b1001001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_2 7'b1000101 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_3 7'b1000010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_FULL_4 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_0 7'b1000110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_1 7'b1000100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_2 7'b1000010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_3 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_MARGIN_LOW_4 7'b1000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPCSRESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPH_CFG 16'h0400 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPHDLY_CFG 24'h084000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPH_MONITOR_SEL 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPMARESET_TIME 5'b00001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_RXDETECT_CFG 14'h1832 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_RXDETECT_REF 3'b100 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_XCLK_SEL "TXOUT" [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property UCODEER_CLR 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+ ##---------------- JTAG Attributes ---------------
+set_property ACJTAG_DEBUG_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ACJTAG_MODE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ACJTAG_RESET 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property ADAPT_CFG0 20'h00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPMRESET_TIME 7'b0001111 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_BIAS_STARTUP_DISABLE 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CFG 4'b0110 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CFG1 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_CM_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_GC_CFG 9'b101110010 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXLPM_GC_CFG2 3'b001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG 43'h49000040E80 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG2 7'b0100000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG3 7'b0100000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG4 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG5 2'h0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property CFOK_CFG6 4'b0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- EYESCAN ---------------
+set_property ES_CLK_PHASE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_RSV5 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- RX Phase Interpolator ---------------
+set_property RXPI_CFG0 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPI_CFG1 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXPI_CFG2 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- TX Phase Interpolator ---------------
+set_property TXPI_CFG0 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG1 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG2 2'b00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG3 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG4 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_CFG5 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_GREY_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_INVSTROBE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_PPMCLK_SEL TXUSRCLK2 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_PPM_CFG 8'h00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXPI_SYNFREQ_PPM 3'b000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property USE_PCS_CLK_PHASE_SEL 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- LOOPBACK ---------------
+set_property LOOPBACK_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- OOB Signalling ---------------
+set_property RXOOB_CLK_CFG PMA [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOSCALRESET_TIME 5'b00011 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXOSCALRESET_TIMEOUT 5'b00000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXOOB_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##---------------- PMA Attributes ---------------
+set_property CLK_COMMON_SWING 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RX_CLKMUX_EN 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TX_CLKMUX_EN 1'b1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property PMA_LOOPBACK_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##---------------- RX SYNC ---------------
+set_property RXSYNC_MULTILANE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSYNC_OVRD 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property RXSYNC_SKIP_DA 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+ ##---------------- TX SYNC ---------------
+set_property TXSYNC_MULTILANE 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXSYNC_OVRD 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+set_property TXSYNC_SKIP_DA 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/CH[*].u_ch/u_gtpe2_channel]
+
+##
+## Attribute Values for QUAD[0] - Common
+##
+set_property BIAS_CFG 64'h0000000000050001 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property COMMON_CFG 32'h00000000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_CFG 27'h01F0319 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_CFG 27'h01F0319 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_DMON_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_DMON_CFG 1'b0 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL_CLKOUT_CFG 8'h00 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_INIT_CFG 24'h00001E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_INIT_CFG 24'h00001E [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_LOCK_CFG 9'h1E8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_LOCK_CFG 9'h1E8 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_FBDIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_FBDIV 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_FBDIV_45 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_FBDIV_45 5 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL0_REFCLK_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property PLL1_REFCLK_DIV 1 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property RSVD_ATTR0 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
+set_property RSVD_ATTR1 16'h0000 [get_cells gen_ibert.ibert_inst/inst/QUAD[0].u_q*/u_common/u_gtpe2_common]
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..dcd34d94609d8c00b9c6db15e06d95b2eca5ebe9
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
@@ -0,0 +1,252 @@
+############################################################################
+# Programmable Logic placement constraints                                 #
+############################################################################
+
+##### USB interface (bank 13) #####
+# USB_VBUS_PWRFAULT_i
+set_property PACKAGE_PIN AA19 [get_ports UsbVbusPwrFaultxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports UsbVbusPwrFaultxSI]
+
+##### PLL interface (banks 35 and 34) #####
+# PLL_2V5_CLKuWire_o
+set_property PACKAGE_PIN G8 [get_ports Pll2V5ClkuWirexCO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkuWirexCO]
+# PLL_2V5_DATAuWire_o
+set_property PACKAGE_PIN G7 [get_ports Pll2V5DatauWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5DatauWirexSO]
+# PLL_2V5_LEuWire_o
+set_property PACKAGE_PIN G6 [get_ports Pll2V5LEuWirexSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LEuWirexSO]
+# PLL_2V5_GOE_o
+set_property PACKAGE_PIN F6 [get_ports Pll2V5GOExSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5GOExSO]
+# PLL_2V5_LD_i
+set_property PACKAGE_PIN H6 [get_ports Pll2V5LDxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LDxSI]
+# PLL_2V5_SYNC_n_o
+set_property PACKAGE_PIN H5 [get_ports Pll2V5SyncxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5SyncxSO]
+# PLL_2V5_CLKIN0_LOS_i (bank 34)
+set_property PACKAGE_PIN J3 [get_ports Pll2V5ClkIn0LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn0LOSxSI]
+# PLL_2V5_CLKIN1_LOS_i (bank 34)
+set_property PACKAGE_PIN K2 [get_ports Pll2V5ClkIn1LOSxSI]
+set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
+
+##### GTP interfaces (bank 112) #####
+#set_property PACKAGE_PIN U9 [get_ports GTPRefClk0PxCI]
+#set_property PACKAGE_PIN V9 [get_ports GTPRefClk0NxCI]
+#set_property PACKAGE_PIN "U5" [get_ports "GTPRefClk1PxCI"]
+#set_property PACKAGE_PIN "V5" [get_ports "GTPRefClk1NxCI"]
+#set_property PACKAGE_PIN Y8 [get_ports GTPFromNorthNxSI]
+#set_property PACKAGE_PIN W8 [get_ports GTPFromNorthPxSI]
+#set_property PACKAGE_PIN Y4 [get_ports GTPToNorthNxSO]
+#set_property PACKAGE_PIN W4 [get_ports GTPToNorthPxSO]
+#set_property PACKAGE_PIN AB7 [get_ports GTPFromSouthNxSI]
+#set_property PACKAGE_PIN AA7 [get_ports GTPFromSouthPxSI]
+#set_property PACKAGE_PIN AB3 [get_ports GTPToSouthNxSO]
+#set_property PACKAGE_PIN AA3 [get_ports GTPToSouthPxSO]
+#set_property PACKAGE_PIN AB9 [get_ports GTPFromEastNxSI]
+#set_property PACKAGE_PIN AA9 [get_ports GTPFromEastPxSI]
+#set_property PACKAGE_PIN AB5 [get_ports GTPToEastNxSO]
+#set_property PACKAGE_PIN AA5 [get_ports GTPToEastPxSO]
+#set_property PACKAGE_PIN Y6 [get_ports GTPFromWestNxSI]
+#set_property PACKAGE_PIN W6 [get_ports GTPFromWestPxSI]
+#set_property PACKAGE_PIN Y2 [get_ports GTPToWestNxSO]
+#set_property PACKAGE_PIN W2 [get_ports GTPToWestPxSO]
+
+##### LVDS links towards edge connectors #####
+# North (bank 35)
+#set_property PACKAGE_PIN "E8"   [get_ports "LVDS2V5North7PxSIO"]
+#set_property PACKAGE_PIN "D8"   [get_ports "LVDS2V5North7NxSIO"]
+#set_property PACKAGE_PIN "D7"   [get_ports "LVDS2V5North6PxSIO"]
+#set_property PACKAGE_PIN "D6"   [get_ports "LVDS2V5North6NxSIO"]
+#set_property PACKAGE_PIN "C8"   [get_ports "LVDS2V5North5PxSIO"]
+#set_property PACKAGE_PIN "B8"   [get_ports "LVDS2V5North5NxSIO"]
+#set_property PACKAGE_PIN "B7"   [get_ports "LVDS2V5North4PxSIO"]
+#set_property PACKAGE_PIN "B6"   [get_ports "LVDS2V5North4NxSIO"]
+#set_property PACKAGE_PIN "A7"   [get_ports "LVDS2V5North3PxSIO"]
+#set_property PACKAGE_PIN "A6"   [get_ports "LVDS2V5North3NxSIO"]
+#set_property PACKAGE_PIN "A5"   [get_ports "LVDS2V5North2PxSIO"]
+#set_property PACKAGE_PIN "A4"   [get_ports "LVDS2V5North2NxSIO"]
+#set_property PACKAGE_PIN "B2"   [get_ports "LVDS2V5North1PxSIO"]
+#set_property PACKAGE_PIN "B1"   [get_ports "LVDS2V5North1NxSIO"]
+#set_property PACKAGE_PIN "A2"   [get_ports "LVDS2V5North0PxSIO"]
+#set_property PACKAGE_PIN "A1"   [get_ports "LVDS2V5North0NxSIO"]
+# South (bank 13)
+#set_property PACKAGE_PIN "V15"  [get_ports "LVDS2V5South7PxSIO"]
+#set_property PACKAGE_PIN "W15"  [get_ports "LVDS2V5South7NxSIO"]
+#set_property PACKAGE_PIN "AB13" [get_ports "LVDS2V5South6PxSIO"]
+#set_property PACKAGE_PIN "AB14" [get_ports "LVDS2V5South6NxSIO"]
+#set_property PACKAGE_PIN "V13"  [get_ports "LVDS2V5South5PxSIO"]
+#set_property PACKAGE_PIN "V14"  [get_ports "LVDS2V5South5NxSIO"]
+#set_property PACKAGE_PIN "Y12"  [get_ports "LVDS2V5South4PxSIO"]
+#set_property PACKAGE_PIN "Y13"  [get_ports "LVDS2V5South4NxSIO"]
+#set_property PACKAGE_PIN "AA12" [get_ports "LVDS2V5South3PxSIO"]
+#set_property PACKAGE_PIN "AB12" [get_ports "LVDS2V5South3NxSIO"]
+#set_property PACKAGE_PIN "W12"  [get_ports "LVDS2V5South2PxSIO"]
+#set_property PACKAGE_PIN "W13"  [get_ports "LVDS2V5South2NxSIO"]
+#set_property PACKAGE_PIN "AA11" [get_ports "LVDS2V5South1PxSIO"]
+#set_property PACKAGE_PIN "AB11" [get_ports "LVDS2V5South1NxSIO"]
+#set_property PACKAGE_PIN "V11"  [get_ports "LVDS2V5South0PxSIO"]
+#set_property PACKAGE_PIN "W11"  [get_ports "LVDS2V5South0NxSIO"]
+# East (bank 13)
+#set_property PACKAGE_PIN "V16"  [get_ports "LVDS2V5East7PxSIO"]
+#set_property PACKAGE_PIN "W16"  [get_ports "LVDS2V5East7NxSIO"]
+#set_property PACKAGE_PIN "W17"  [get_ports "LVDS2V5East6PxSIO"]
+#set_property PACKAGE_PIN "Y17"  [get_ports "LVDS2V5East6NxSIO"]
+#set_property PACKAGE_PIN "U13"  [get_ports "LVDS2V5East5PxSIO"]
+#set_property PACKAGE_PIN "U14"  [get_ports "LVDS2V5East5NxSIO"]
+#set_property PACKAGE_PIN "V18"  [get_ports "LVDS2V5East4PxSIO"]
+#set_property PACKAGE_PIN "W18"  [get_ports "LVDS2V5East4NxSIO"]
+#set_property PACKAGE_PIN "U11"  [get_ports "LVDS2V5East3PxSIO"]
+#set_property PACKAGE_PIN "U12"  [get_ports "LVDS2V5East3NxSIO"]
+#set_property PACKAGE_PIN "U19"  [get_ports "LVDS2V5East2PxSIO"]
+#set_property PACKAGE_PIN "V19"  [get_ports "LVDS2V5East2NxSIO"]
+#set_property PACKAGE_PIN "R17"  [get_ports "LVDS2V5East1PxSIO"]
+#set_property PACKAGE_PIN "T17"  [get_ports "LVDS2V5East1NxSIO"]
+#set_property PACKAGE_PIN "U17"  [get_ports "LVDS2V5East0PxSIO"]
+#set_property PACKAGE_PIN "U18"  [get_ports "LVDS2V5East0NxSIO"]
+# West (bank 35)
+#set_property PACKAGE_PIN "H4"   [get_ports "LVDS2V5West7PxSIO"]
+#set_property PACKAGE_PIN "H3"   [get_ports "LVDS2V5West7NxSIO"]
+#set_property PACKAGE_PIN "H1"   [get_ports "LVDS2V5West6PxSIO"]
+#set_property PACKAGE_PIN "G1"   [get_ports "LVDS2V5West6NxSIO"]
+#set_property PACKAGE_PIN "G3"   [get_ports "LVDS2V5West5PxSIO"]
+#set_property PACKAGE_PIN "G2"   [get_ports "LVDS2V5West5NxSIO"]
+#set_property PACKAGE_PIN "F2"   [get_ports "LVDS2V5West4PxSIO"]
+#set_property PACKAGE_PIN "F1"   [get_ports "LVDS2V5West4NxSIO"]
+#set_property PACKAGE_PIN "G4"   [get_ports "LVDS2V5West3PxSIO"]
+#set_property PACKAGE_PIN "F4"   [get_ports "LVDS2V5West3NxSIO"]
+#set_property PACKAGE_PIN "E2"   [get_ports "LVDS2V5West2PxSIO"]
+#set_property PACKAGE_PIN "D2"   [get_ports "LVDS2V5West2NxSIO"]
+#set_property PACKAGE_PIN "E4"   [get_ports "LVDS2V5West1PxSIO"]
+#set_property PACKAGE_PIN "E3"   [get_ports "LVDS2V5West1NxSIO"]
+#set_property PACKAGE_PIN "D1"   [get_ports "LVDS2V5West0PxSIO"]
+#set_property PACKAGE_PIN "C1"   [get_ports "LVDS2V5West0NxSIO"]
+
+##### LVDS links towards top-bottom connectors #####
+# Top (bank 34)
+#set_property PACKAGE_PIN "J8"   [get_ports "LVDS2V5Top7PxSIO"]
+#set_property PACKAGE_PIN "K8"   [get_ports "LVDS2V5Top7NxSIO"]
+#set_property PACKAGE_PIN "K7"   [get_ports "LVDS2V5Top6PxSIO"]
+#set_property PACKAGE_PIN "L7"   [get_ports "LVDS2V5Top6NxSIO"]
+#set_property PACKAGE_PIN "N8"   [get_ports "LVDS2V5Top5PxSIO"]
+#set_property PACKAGE_PIN "P8"   [get_ports "LVDS2V5Top5NxSIO"]
+#set_property PACKAGE_PIN "M8"   [get_ports "LVDS2V5Top4PxSIO"]
+#set_property PACKAGE_PIN "M7"   [get_ports "LVDS2V5Top4NxSIO"]
+#set_property PACKAGE_PIN "L6"   [get_ports "LVDS2V5Top3PxSIO"]
+#set_property PACKAGE_PIN "M6"   [get_ports "LVDS2V5Top3NxSIO"]
+#set_property PACKAGE_PIN "J7"   [get_ports "LVDS2V5Top2PxSIO"]
+#set_property PACKAGE_PIN "J6"   [get_ports "LVDS2V5Top2NxSIO"]
+#set_property PACKAGE_PIN "J5"   [get_ports "LVDS2V5Top1PxSIO"]
+#set_property PACKAGE_PIN "K5"   [get_ports "LVDS2V5Top1NxSIO"]
+#set_property PACKAGE_PIN "J2"   [get_ports "LVDS2V5Top0PxSIO"]
+#set_property PACKAGE_PIN "J1"   [get_ports "LVDS2V5Top0NxSIO"]
+# Bottom (bank 34)
+#set_property PACKAGE_PIN "N6"   [get_ports "LVDS2V5Bottom7PxSIO"]
+#set_property PACKAGE_PIN "N5"   [get_ports "LVDS2V5Bottom7NxSIO"]
+#set_property PACKAGE_PIN "P6"   [get_ports "LVDS2V5Bottom6PxSIO"]
+#set_property PACKAGE_PIN "P5"   [get_ports "LVDS2V5Bottom6NxSIO"]
+#set_property PACKAGE_PIN "R5"   [get_ports "LVDS2V5Bottom5PxSIO"]
+#set_property PACKAGE_PIN "R4"   [get_ports "LVDS2V5Bottom5NxSIO"]
+#set_property PACKAGE_PIN "R3"   [get_ports "LVDS2V5Bottom4PxSIO"]
+#set_property PACKAGE_PIN "R2"   [get_ports "LVDS2V5Bottom4NxSIO"]
+#set_property PACKAGE_PIN "P3"   [get_ports "LVDS2V5Bottom3PxSIO"]
+#set_property PACKAGE_PIN "P2"   [get_ports "LVDS2V5Bottom3NxSIO"]
+#set_property PACKAGE_PIN "N1"   [get_ports "LVDS2V5Bottom2PxSIO"]
+#set_property PACKAGE_PIN "P1"   [get_ports "LVDS2V5Bottom2NxSIO"]
+#set_property PACKAGE_PIN "N4"   [get_ports "LVDS2V5Bottom1PxSIO"]
+#set_property PACKAGE_PIN "N3"   [get_ports "LVDS2V5Bottom1NxSIO"]
+#set_property PACKAGE_PIN "M2"   [get_ports "LVDS2V5Bottom0PxSIO"]
+#set_property PACKAGE_PIN "M1"   [get_ports "LVDS2V5Bottom0NxSIO"]
+
+##### RGB LEDs (banks 34 and 13) #####
+# LED1_2V5_R_o (bank 34)
+set_property PACKAGE_PIN L2 [get_ports Led12V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5RxSO]
+# LED1_2V5_G_o (bank 34)
+set_property PACKAGE_PIN L1 [get_ports Led12V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5GxSO]
+# LED1_2V5_B_o (bank 34)
+set_property PACKAGE_PIN R8 [get_ports Led12V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led12V5BxSO]
+# LED2_2V5_R_o (bank 13)
+set_property PACKAGE_PIN T16 [get_ports Led22V5RxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5RxSO]
+# LED2_2V5_G_o (bank 13)
+set_property PACKAGE_PIN U16 [get_ports Led22V5GxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5GxSO]
+# LED2_2V5_B_o (bank 13)
+set_property PACKAGE_PIN AA20 [get_ports Led22V5BxSO]
+set_property IOSTANDARD LVCMOS25 [get_ports Led22V5BxSO]
+
+##### Self reset (bank 34) #####
+set_property PACKAGE_PIN H8 [get_ports SelfRstxRNO]
+set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
+
+##### Clock dedicated pins (Multi-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "D5"   [get_ports "PLLClk2V5LocalPxCI"]
+#set_property PACKAGE_PIN "C4"   [get_ports "PLLClk2V5LocalNxCI"]
+#set_property PACKAGE_PIN "B4"   [get_ports "PLLClk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "B3"   [get_ports "PLLClk2V5NorthNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "T2"   [get_ports "PLLClk2V5TopxCI"]
+#set_property PACKAGE_PIN "L5"   [get_ports "PLLClk2V5BottomxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "Y14"  [get_ports "PLLClk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "Y15"  [get_ports "PLLClk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "Y18"  [get_ports "Clk2V5RecoveryPxCO"]
+#set_property PACKAGE_PIN "Y19"  [get_ports "Clk2V5RecoveryNxCO"]
+
+##### Clock dedicated pins (Single-region) #####
+# Bank 35
+#set_property PACKAGE_PIN "C6"   [get_ports "Clk2V5NorthPxCI"]
+#set_property PACKAGE_PIN "C5"   [get_ports "Clk2V5NorthNxCI"]
+#set_property PACKAGE_PIN "D3"   [get_ports "Clk2V5WestPxCI"]
+#set_property PACKAGE_PIN "C3"   [get_ports "Clk2V5WestNxCI"]
+# Bank 34
+#set_property PACKAGE_PIN "K4"   [get_ports "Clk2V5TopPxCI"]
+#set_property PACKAGE_PIN "K3"   [get_ports "Clk2V5TopNxCI"]
+#set_property PACKAGE_PIN "U2"   [get_ports "Clk2V5BottomPxCI"]
+#set_property PACKAGE_PIN "U1"   [get_ports "Clk2V5BottomNxCI"]
+# Bank 13
+#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
+#set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
+#set_property PACKAGE_PIN "AA16" [get_ports "Clk2V5EastPxCI"]
+#set_property PACKAGE_PIN "AA17" [get_ports "Clk2V5EastNxCI"]
+
+##### Clock outputs #####
+## Bank 35
+#set_property PACKAGE_PIN "F7"   [get_ports "Clk2V5NorthPxCO"]
+#set_property PACKAGE_PIN "E7"   [get_ports "Clk2V5NorthNxCO"]
+#set_property PACKAGE_PIN "F5"   [get_ports "Clk2V5WestPxCO"]
+#set_property PACKAGE_PIN "E5"   [get_ports "Clk2V5WestNxCO"]
+# Bank 34
+#set_property PACKAGE_PIN "P7"   [get_ports "Clk2V5TopPxCO"]
+#set_property PACKAGE_PIN "R7"   [get_ports "Clk2V5TopNxCO"]
+#set_property PACKAGE_PIN "M4"   [get_ports "Clk2V5BottomPxCO"]
+#set_property PACKAGE_PIN "M3"   [get_ports "Clk2V5BottomNxCO"]
+# Bank 13
+#set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
+#set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
+#set_property PACKAGE_PIN "AB21" [get_ports "Clk2V5EastPxCO"]
+#set_property PACKAGE_PIN "AB22" [get_ports "Clk2V5EastNxCO"]
+
+############################################################################
+# Other constraints                                                        #
+############################################################################
+
+##### Operating conditions (for XPE report) #####
+# Extended grade (as for -2 speed grade) and maximum consumption estimation
+set_operating_conditions -grade extended -process maximum
+# 4'' by 4'' PCB, no heatsink, no air flow
+set_operating_conditions -airflow 0 -heatsink none -board small
+
+
+
+
+
+
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..3a458f2af5014e25fd7a09250af52e68a786475c
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -0,0 +1,32 @@
+############################################################################
+# Timing constraints                                                       #
+############################################################################
+
+##### PS_CLK (125 MHz) #####
+create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
+
+##### GTP reference clocks (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk1xC]
+
+##### Clocks from PLLs (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Local}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Bottom}]
+
+##### Clocks from neighbours (125 MHz) #####
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_North}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_South}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_East}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_West}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Top}]
+#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Bottom}]
+
+
+
+
+
+
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/hdl/scalp_user_firmware.vhd b/designs/vivado/scalp_user_firmware/2020.2/src/hdl/scalp_user_firmware.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..753b96c9a33de0ca7668bbf5627eadbe9e40e32d
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/hdl/scalp_user_firmware.vhd
@@ -0,0 +1,429 @@
+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: scalp_user_firmware - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_user_firmware
+--
+-- Last update: 2021-03-17
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+-- Axi4 packages
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity scalp_user_firmware is
+
+    generic (
+        C_USE_IBERT  : boolean := false;
+        C_DEBUG_MODE : boolean := false);
+
+    port (
+        -----------------------------------------------------------------------
+        -- Names defined and not described in the constraint file.
+        -----------------------------------------------------------------------
+        -- Zynq FIXED_IO
+        PSClkxCIO          : inout std_logic;
+        PSSRstxRNIO        : inout std_logic;
+        PSPorxSNIO         : inout std_logic;
+        -- DDR interface
+        DDRClkNxCIO        : inout std_logic;
+        DDRClkPxCIO        : inout std_logic;
+        DDRDRstxRNIO       : inout std_logic;
+        DDRCasNxSIO        : inout std_logic;
+        DDRCkexSIO         : inout std_logic;
+        DDRCsNxSIO         : inout std_logic;
+        DDROdtxSIO         : inout std_logic;
+        DDRRasNxSIO        : inout std_logic;
+        DDRWexSNIO         : inout std_logic;
+        DDRBankAddrxDIO    : inout std_logic_vector(2 downto 0);
+        DDRAddrxDIO        : inout std_logic_vector(14 downto 0);
+        DDRVrNxSIO         : inout std_logic;
+        DDRVrPxSIO         : inout std_logic;
+        DDRDmxDIO          : inout std_logic_vector(3 downto 0);
+        DDRDqxDIO          : inout std_logic_vector(31 downto 0);
+        DDRDqsNxDIO        : inout std_logic_vector(3 downto 0);
+        DDRDqsPxDIO        : inout std_logic_vector(3 downto 0);
+        -- MIO Interface
+        MIOxDIO            : inout std_logic_vector(53 downto 0);
+        -----------------------------------------------------------------------
+        -- USB signals
+        UsbVbusPwrFaultxSI : in    std_logic;
+        -- PLL interface
+        Pll2V5ClkuWirexCO  : out   std_logic;  -- Clock (from SPI1_SCLK)
+        Pll2V5DatauWirexSO : out   std_logic;  -- Data (from SPI1_MOSI)
+        Pll2V5LEuWirexSO   : out   std_logic;  -- Latch enable (from SPI1_SS)
+        Pll2V5GOExSO       : out   std_logic;  -- Global Output Enable
+        Pll2V5LDxSI        : in    std_logic;  -- Lock Detect
+        Pll2V5SyncxSO      : out   std_logic;  -- Sync
+        Pll2V5ClkIn0LOSxSI : in    std_logic;  -- FPGA clock Loss of Sync
+        Pll2V5ClkIn1LOSxSI : in    std_logic;  -- External oscillator Loss of Sync
+        -- GTP interfaces
+        -- Clocks
+        -- GTPRefClk0PxCI     : in    std_logic;
+        -- GTPRefClk0NxCI     : in    std_logic;
+        -- GTPRefClk1PxCI     : in    std_logic;
+        -- GTPRefClk1NxCI     : in    std_logic;
+        -- North
+        -- GTPFromNorthPxSI   : in    std_logic;
+        -- GTPFromNorthNxSI   : in    std_logic;
+        -- GTPToNorthPxSO     : out   std_logic;
+        -- GTPToNorthNxSO     : out   std_logic;
+        -- East
+        -- GTPFromEastPxSI    : in    std_logic;
+        -- GTPFromEastNxSI    : in    std_logic;
+        -- GTPToEastPxSO      : out   std_logic;
+        -- GTPToEastNxSO      : out   std_logic;
+        -- South
+        -- GTPFromSouthPxSI   : in    std_logic;
+        -- GTPFromSouthNxSI   : in    std_logic;
+        -- GTPToSouthPxSO     : out   std_logic;
+        -- GTPToSouthNxSO     : out   std_logic;
+        -- West
+        -- GTPFromWestPxSI    : in    std_logic;
+        -- GTPFromWestNxSI    : in    std_logic;
+        -- GTPToWestPxSO      : out   std_logic;
+        -- GTPToWestNxSO      : out   std_logic;
+        -- LVDS links towards edge connectors
+        -- North
+        -- LVDS2V5North0PxSIO  : inout std_logic;
+        -- LVDS2V5North0NxSIO  : inout std_logic;
+        -- LVDS2V5North1PxSIO  : inout std_logic;
+        -- LVDS2V5North1NxSIO  : inout std_logic;
+        -- LVDS2V5North2PxSIO  : inout std_logic;
+        -- LVDS2V5North2NxSIO  : inout std_logic;
+        -- LVDS2V5North3PxSIO  : inout std_logic;
+        -- LVDS2V5North3NxSIO  : inout std_logic;
+        -- LVDS2V5North4PxSIO  : inout std_logic;
+        -- LVDS2V5North4NxSIO  : inout std_logic;
+        -- LVDS2V5North5PxSIO  : inout std_logic;
+        -- LVDS2V5North5NxSIO  : inout std_logic;
+        -- LVDS2V5North6PxSIO  : inout std_logic;
+        -- LVDS2V5North6NxSIO  : inout std_logic;
+        -- LVDS2V5North7PxSIO  : inout std_logic;
+        -- LVDS2V5North7NxSIO  : inout std_logic;
+        -- South
+        -- LVDS2V5South0PxSIO  : inout std_logic;
+        -- LVDS2V5South0NxSIO  : inout std_logic;
+        -- LVDS2V5South1PxSIO  : inout std_logic;
+        -- LVDS2V5South1NxSIO  : inout std_logic;
+        -- LVDS2V5South2PxSIO  : inout std_logic;
+        -- LVDS2V5South2NxSIO  : inout std_logic;
+        -- LVDS2V5South3PxSIO  : inout std_logic;
+        -- LVDS2V5South3NxSIO  : inout std_logic;
+        -- LVDS2V5South4PxSIO  : inout std_logic;
+        -- LVDS2V5South4NxSIO  : inout std_logic;
+        -- LVDS2V5South5PxSIO  : inout std_logic;
+        -- LVDS2V5South5NxSIO  : inout std_logic;
+        -- LVDS2V5South6PxSIO  : inout std_logic;
+        -- LVDS2V5South6NxSIO  : inout std_logic;
+        -- LVDS2V5South7PxSIO  : inout std_logic;
+        -- LVDS2V5South7NxSIO  : inout std_logic;
+        -- East
+        -- LVDS2V5East0PxSIO   : inout std_logic;
+        -- LVDS2V5East0NxSIO   : inout std_logic;
+        -- LVDS2V5East1PxSIO   : inout std_logic;
+        -- LVDS2V5East1NxSIO   : inout std_logic;
+        -- LVDS2V5East2PxSIO   : inout std_logic;
+        -- LVDS2V5East2NxSIO   : inout std_logic;
+        -- LVDS2V5East3PxSIO   : inout std_logic;
+        -- LVDS2V5East3NxSIO   : inout std_logic;
+        -- LVDS2V5East4PxSIO   : inout std_logic;
+        -- LVDS2V5East4NxSIO   : inout std_logic;
+        -- LVDS2V5East5PxSIO   : inout std_logic;
+        -- LVDS2V5East5NxSIO   : inout std_logic;
+        -- LVDS2V5East6PxSIO   : inout std_logic;
+        -- LVDS2V5East6NxSIO   : inout std_logic;
+        -- LVDS2V5East7PxSIO   : inout std_logic;
+        -- LVDS2V5East7NxSIO   : inout std_logic;
+        -- West
+        -- LVDS2V5West0PxSIO   : inout std_logic;
+        -- LVDS2V5West0NxSIO   : inout std_logic;
+        -- LVDS2V5West1PxSIO   : inout std_logic;
+        -- LVDS2V5West1NxSIO   : inout std_logic;
+        -- LVDS2V5West2PxSIO   : inout std_logic;
+        -- LVDS2V5West2NxSIO   : inout std_logic;
+        -- LVDS2V5West3PxSIO   : inout std_logic;
+        -- LVDS2V5West3NxSIO   : inout std_logic;
+        -- LVDS2V5West4PxSIO   : inout std_logic;
+        -- LVDS2V5West4NxSIO   : inout std_logic;
+        -- LVDS2V5West5PxSIO   : inout std_logic;
+        -- LVDS2V5West5NxSIO   : inout std_logic;
+        -- LVDS2V5West6PxSIO   : inout std_logic;
+        -- LVDS2V5West6NxSIO   : inout std_logic;
+        -- LVDS2V5West7PxSIO   : inout std_logic;
+        -- LVDS2V5West7NxSIO   : inout std_logic;
+        -- LVDS links towards top-bottom connectors
+        -- Top
+        -- LVDS2V5Top0PxSIO    : inout std_logic;
+        -- LVDS2V5Top0NxSIO    : inout std_logic;
+        -- LVDS2V5Top1PxSIO    : inout std_logic;
+        -- LVDS2V5Top1NxSIO    : inout std_logic;
+        -- LVDS2V5Top2PxSIO    : inout std_logic;
+        -- LVDS2V5Top2NxSIO    : inout std_logic;
+        -- LVDS2V5Top3PxSIO    : inout std_logic;
+        -- LVDS2V5Top3NxSIO    : inout std_logic;
+        -- LVDS2V5Top4PxSIO    : inout std_logic;
+        -- LVDS2V5Top4NxSIO    : inout std_logic;
+        -- LVDS2V5Top5PxSIO    : inout std_logic;
+        -- LVDS2V5Top5NxSIO    : inout std_logic;
+        -- LVDS2V5Top6PxSIO    : inout std_logic;
+        -- LVDS2V5Top6NxSIO    : inout std_logic;
+        -- LVDS2V5Top7PxSIO    : inout std_logic;
+        -- LVDS2V5Top7NxSIO    : inout std_logic;
+        -- Bottom
+        -- LVDS2V5Bottom0PxSIO : inout std_logic;
+        -- LVDS2V5Bottom0NxSIO : inout std_logic;
+        -- LVDS2V5Bottom1PxSIO : inout std_logic;
+        -- LVDS2V5Bottom1NxSIO : inout std_logic;
+        -- LVDS2V5Bottom2PxSIO : inout std_logic;
+        -- LVDS2V5Bottom2NxSIO : inout std_logic;
+        -- LVDS2V5Bottom3PxSIO : inout std_logic;
+        -- LVDS2V5Bottom3NxSIO : inout std_logic;
+        -- LVDS2V5Bottom4PxSIO : inout std_logic;
+        -- LVDS2V5Bottom4NxSIO : inout std_logic;
+        -- LVDS2V5Bottom5PxSIO : inout std_logic;
+        -- LVDS2V5Bottom5NxSIO : inout std_logic;
+        -- LVDS2V5Bottom6PxSIO : inout std_logic;
+        -- LVDS2V5Bottom6NxSIO : inout std_logic;
+        -- LVDS2V5Bottom7PxSIO : inout std_logic;
+        -- LVDS2V5Bottom7NxSIO : inout std_logic;
+        -- RGB LEDs
+        Led12V5RxSO        : out   std_logic;
+        Led12V5GxSO        : out   std_logic;
+        Led12V5BxSO        : out   std_logic;
+        Led22V5RxSO        : out   std_logic;
+        Led22V5GxSO        : out   std_logic;
+        Led22V5BxSO        : out   std_logic;
+        -- Self reset (connected to PS_SRSTB)
+        SelfRstxRNO        : out   std_logic);
+    -- Clocks from PLLs (connected to MRCC pins)
+    -- Local
+    -- PLLClk2V5LocalPxCI  : in    std_logic;
+    -- PLLClk2V5LocalNxCI  : in    std_logic;
+    -- -- North
+    -- PLLClk2V5NorthPxCI  : in    std_logic;
+    -- PLLClk2V5NorthNxCI  : in    std_logic;
+    -- -- South
+    -- PLLClk2V5SouthPxCI  : in    std_logic;
+    -- PLLClk2V5SouthNxCI  : in    std_logic;
+    -- -- Top
+    -- PLLClk2V5TopxCI     : in    std_logic;  -- Single-ended
+    -- -- Bottom
+    -- PLLClk2V5BottomxCI  : in    std_logic;  -- Single-ended
+    -- -- Clocks to/from neighbours
+    -- -- North
+    -- Clk2V5NorthPxCI     : in    std_logic;
+    -- Clk2V5NorthNxCI     : in    std_logic;
+    -- Clk2V5NorthPxCO     : out   std_logic;
+    -- Clk2V5NorthNxCO     : out   std_logic;
+    -- -- South
+    -- Clk2V5SouthPxCI     : in    std_logic;
+    -- Clk2V5SouthNxCI     : in    std_logic;
+    -- Clk2V5SouthPxCO     : out   std_logic;
+    -- Clk2V5SouthNxCO     : out   std_logic;
+    -- -- East
+    -- Clk2V5EastPxCI      : in    std_logic;
+    -- Clk2V5EastNxCI      : in    std_logic;
+    -- Clk2V5EastPxCO      : out   std_logic;
+    -- Clk2V5EastNxCO      : out   std_logic;
+    -- -- West
+    -- Clk2V5WestPxCI      : in    std_logic;
+    -- Clk2V5WestNxCI      : in    std_logic;
+    -- Clk2V5WestPxCO      : out   std_logic;
+    -- Clk2V5WestNxCO      : out   std_logic;
+    -- -- Top
+    -- Clk2V5TopPxCI       : in    std_logic;
+    -- Clk2V5TopNxCI       : in    std_logic;
+    -- Clk2V5TopPxCO       : out   std_logic;
+    -- Clk2V5TopNxCO       : out   std_logic;
+    -- -- Bottom
+    -- Clk2V5BottomPxCI    : in    std_logic;
+    -- Clk2V5BottomNxCI    : in    std_logic;
+    -- Clk2V5BottomPxCO    : out   std_logic;
+    -- Clk2V5BottomNxCO    : out   std_logic;
+    -- -- Recovery
+    -- Clk2V5RecoveryPxCO  : out   std_logic;
+    -- Clk2V5RecoveryNxCO  : out   std_logic);
+
+end scalp_user_firmware;
+
+architecture arch of scalp_user_firmware is
+
+    -- Constantes
+    -- constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
+    constant C_AXI_ADDR_SIZE : integer range 0 to 32 := 12;
+
+    -- Signals
+    -- Clocks
+    -- Processing system clock
+    signal PSSysClkxC     : std_logic                                          := '0';
+    -- Resets
+    -- Processing system reset
+    signal PSSysResetxR   : std_logic                                          := '0';
+    -- Scalp Axi Lite interface and IRQ
+    signal InterruptxS    : std_ulogic                                         := '0';
+    signal RdAddrxD       : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0)  := (others => '0');
+    signal RdDataxD       : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    signal RdValidxS      : std_ulogic                                         := '0';
+    signal WrAddrxD       : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0)  := (others => '0');
+    signal WrDataxD       : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    signal WrValidxS      : std_ulogic                                         := '0';
+    -- Zynq Reg Bank
+    signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    -- RGB Leds
+    signal Led12V5RxS     : std_ulogic                                         := '0';
+    signal Led12V5GxS     : std_ulogic                                         := '0';
+    signal Led12V5BxS     : std_ulogic                                         := '0';
+    signal Led22V5RxS     : std_ulogic                                         := '0';
+    signal Led22V5GxS     : std_ulogic                                         := '0';
+    signal Led22V5BxS     : std_ulogic                                         := '0';
+
+
+    -- Attributes
+    attribute mark_debug         : string;
+    attribute keep               : string;
+    -- Clocks
+    attribute keep of PSSysClkxC : signal is "true";
+
+begin
+
+    ProcessingSystemxB : block is
+    begin  -- block ProcessingSystemxB
+
+        ZynqxI : entity work.scalp_zynqps_wrapper
+            port map (
+                -- Processor interface
+                FIXED_IO_ps_clk     => PSClkxCIO,
+                FIXED_IO_ps_porb    => PSPorxSNIO,
+                FIXED_IO_ps_srstb   => PSSRstxRNIO,
+                FclkClk0xCO         => PSSysClkxC,
+                FclkReset0xRO       => PSSysResetxR,
+                -- DDR interface
+                DDR_addr            => DDRAddrxDIO,
+                DDR_ba              => DDRBankAddrxDIO,
+                DDR_cas_n           => DDRCasNxSIO,
+                DDR_ck_n            => DDRClkNxCIO,
+                DDR_ck_p            => DDRClkPxCIO,
+                DDR_cke             => DDRCkexSIO,
+                DDR_cs_n            => DDRCsNxSIO,
+                DDR_dm              => DDRDmxDIO,
+                DDR_dq              => DDRDqxDIO,
+                DDR_dqs_n           => DDRDqsNxDIO,
+                DDR_dqs_p           => DDRDqsPxDIO,
+                DDR_odt             => DDROdtxSIO,
+                DDR_ras_n           => DDRRasNxSIO,
+                DDR_reset_n         => DDRDRstxRNIO,
+                DDR_we_n            => DDRWexSNIO,
+                FIXED_IO_ddr_vrn    => DDRVrNxSIO,
+                FIXED_IO_ddr_vrp    => DDRVrPxSIO,
+                -- USB interface
+                Usb0VBusPwrFaultxSI => UsbVbusPwrFaultxSI,
+                -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
+                -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
+                Spi1MOSIxSO         => Pll2V5DatauWirexSO,
+                Spi1SSxSO           => Pll2V5LEuWirexSO,
+                Spi1SclkxCO         => Pll2V5ClkuWirexCO,
+                -- MIO
+                FIXED_IO_mio        => MIOxDIO,
+                -- Scalp Axi Lite interface and IRQ
+                InterruptxSI        => InterruptxS,
+                RdAddrxDO           => RdAddrxD,
+                RdDataxDI           => RdDataxD,
+                RdValidxSO          => RdValidxS,
+                WrAddrxDO           => WrAddrxD,
+                WrDataxDO           => WrDataxD,
+                WrValidxSO          => WrValidxS);
+
+    end block ProcessingSystemxB;
+
+    ProgrammableLogicxB : block is
+    begin  -- block ProgrammableLogicxB        
+
+        EntityIOxB : block is
+        begin
+
+            Led12V5RxAS : Led12V5RxSO <= Led12V5RxS;
+            Led12V5GxAS : Led12V5GxSO <= Led12V5GxS;
+            Led12V5BxAS : Led12V5BxSO <= Led12V5BxS;
+            Led22V5RxAS : Led22V5RxSO <= Led22V5RxS;
+            Led22V5GxAS : Led22V5GxSO <= Led22V5GxS;
+            Led22V5BxAS : Led22V5BxSO <= Led22V5BxS;
+
+        end block EntityIOxB;
+
+
+        ZynqRegBankxB : block is
+        begin  -- block ZynqRegBankxB
+
+            RegBankxB : block is
+            begin  -- block RegBankxB
+
+                WriteRegPortxP : process (CtrlRegPortxDP, WrAddrxD, WrDataxD,
+                                          WrValidxS) is
+                begin  -- process WriteRegPortxP
+                    CtrlRegPortxDN <= CtrlRegPortxDP;
+
+                    if WrValidxS = '1' then
+                        case WrAddrxD is
+                            -- Ctrl
+                            -- North
+                            when x"000" => CtrlRegPortxDN <= WrDataxD;
+                            when x"004" => CtrlRegPortxDN <= CtrlRegPortxDP or WrDataxD;
+                            when x"008" => CtrlRegPortxDN <= CtrlRegPortxDP and not WrDataxD;
+                            when others => null;
+                        end case;
+                    end if;
+                end process WriteRegPortxP;
+
+                ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
+                begin  -- process ReadRegPortxP
+                    if PSSysResetxR = '1' then
+                        RdDataxD <= (others => '0');
+                    elsif rising_edge(PSSysClkxC) then
+                        RdDataxD <= (others => '0');
+
+                        if RdValidxS = '1' then
+                            case RdAddrxD is
+                                when x"000" => RdDataxD <= CtrlRegPortxDP;
+                                when others => RdDataxD <= x"aabbccdd";
+                            end case;
+                        end if;
+                    end if;
+                end process ReadRegPortxP;
+
+                RegBankxP : process (PSSysClkxC, PSSysResetxR) is
+                begin  -- process RegBankxP
+                    if PSSysResetxR = '1' then
+                        CtrlRegPortxDP <= (others => '0');
+                    elsif rising_edge(PSSysClkxC) then
+                        CtrlRegPortxDP <= CtrlRegPortxDN;
+                    end if;
+                end process RegBankxP;
+
+            end block RegBankxB;
+
+        end block ZynqRegBankxB;
+
+    end block ProgrammableLogicxB;
+
+end arch;
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/ipi_tcl/scalp_user_firmware_ipi.tcl b/designs/vivado/scalp_user_firmware/2020.2/src/ipi_tcl/scalp_user_firmware_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e1687165c745d65accba46f0e86ebf5af5a3d442
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/ipi_tcl/scalp_user_firmware_ipi.tcl
@@ -0,0 +1 @@
+source "../../../../../../soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl"
\ No newline at end of file
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/sim/tb_scalp_user_firmware.vhd b/designs/vivado/scalp_user_firmware/2020.2/src/sim/tb_scalp_user_firmware.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3ceca05d0fa7a578e1587771932cac14e6b851de
--- /dev/null
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/sim/tb_scalp_user_firmware.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: tb_scalp_user_firmware - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_user_firmware
+--
+-- Last update: 2021-03-17 07:44:47
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_user_firmware is
+end tb_scalp_user_firmware;
+
+
+architecture behavioral of tb_scalp_user_firmware is
+
+begin
+
+end behavioral;
diff --git a/tools/config/scalp_user_firmware.json b/tools/config/scalp_user_firmware.json
new file mode 100644
index 0000000000000000000000000000000000000000..0fbecfd0268a94a2a3b9f2262a06745c61ca7f05
--- /dev/null
+++ b/tools/config/scalp_user_firmware.json
@@ -0,0 +1,32 @@
+{
+    "author" : {
+        "name"  : "Joachim Schmidt",
+        "email" : "<joachim.schmidt@hesge.ch>"
+    },
+    "project" : {
+        "name"            : "scalp_user_firmware",
+        "type"            : "DESIGN_PRJ_TYPE",
+        "category"        : "DESIGNS",
+        "vivado_version"  : "2020.2",
+        "target_language" : "VHDL",
+        "vhdl_version"    : "VHDL 2008"
+    },
+    "hardware" : {
+        "part_name"  : "xc7z015clg485-2",
+        "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+    },
+    "constraints" : {
+        "scalp_user_firmware" : "enable",
+        "ibert_constraints"   : "disable",
+        "debug"               : "enable",
+        "timing_constraints"  : "enable"
+    },   
+    "components" : {
+        "packages" : {
+            "axi4_pkg"          : "enable"
+        },
+        "soc" : {
+            "scalp_zynqps" : "enable"
+        }
+    }
+}