diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index fea8251cab004a136f6e3606176b1d36f568d35f..cfb395dbaf27700b1fd0df50f4000184b8a21d2d 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
--- Last update: 2021-05-05
+-- Last update: 2021-05-06
--
---------------------------------------------------------------------------------
@@ -535,38 +535,38 @@ architecture arch of scalp_firmware is
attribute mark_debug of TXAxism2sVectorxD : signal is "true";
attribute keep of TXAxism2sVectorxD : signal is "true";
-- Scalp Aurora PHY Ready -> TX Side
- attribute mark_debug of NorthTXM2SxD : signal is "true";
- attribute keep of NorthTXM2SxD : signal is "true";
- attribute mark_debug of NorthTXS2MxD : signal is "true";
- attribute keep of NorthTXS2MxD : signal is "true";
- attribute mark_debug of EastTXM2SxD : signal is "true";
- attribute keep of EastTXM2SxD : signal is "true";
- attribute mark_debug of EastTXS2MxD : signal is "true";
- attribute keep of EastTXS2MxD : signal is "true";
- attribute mark_debug of SouthTXM2SxD : signal is "true";
- attribute keep of SouthTXM2SxD : signal is "true";
- attribute mark_debug of SouthTXS2MxD : signal is "true";
- attribute keep of SouthTXS2MxD : signal is "true";
- attribute mark_debug of WestTXM2SxD : signal is "true";
- attribute keep of WestTXM2SxD : signal is "true";
- attribute mark_debug of WestTXS2MxD : signal is "true";
- attribute keep of WestTXS2MxD : signal is "true";
- attribute mark_debug of NorthRXM2SxD : signal is "true";
- attribute keep of NorthRXM2SxD : signal is "true";
- attribute mark_debug of NorthRXS2MxD : signal is "true";
- attribute keep of NorthRXS2MxD : signal is "true";
- attribute mark_debug of EastRXM2SxD : signal is "true";
- attribute keep of EastRXM2SxD : signal is "true";
- attribute mark_debug of EastRXS2MxD : signal is "true";
- attribute keep of EastRXS2MxD : signal is "true";
- attribute mark_debug of SouthRXM2SxD : signal is "true";
- attribute keep of SouthRXM2SxD : signal is "true";
- attribute mark_debug of SouthRXS2MxD : signal is "true";
- attribute keep of SouthRXS2MxD : signal is "true";
- attribute mark_debug of WestRXM2SxD : signal is "true";
- attribute keep of WestRXM2SxD : signal is "true";
- attribute mark_debug of WestRXS2MxD : signal is "true";
- attribute keep of WestRXS2MxD : signal is "true";
+ -- attribute mark_debug of NorthTXM2SxD : signal is "true";
+ -- attribute keep of NorthTXM2SxD : signal is "true";
+ -- attribute mark_debug of NorthTXS2MxD : signal is "true";
+ -- attribute keep of NorthTXS2MxD : signal is "true";
+ -- attribute mark_debug of EastTXM2SxD : signal is "true";
+ -- attribute keep of EastTXM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXS2MxD : signal is "true";
+ -- attribute keep of EastTXS2MxD : signal is "true";
+ -- attribute mark_debug of SouthTXM2SxD : signal is "true";
+ -- attribute keep of SouthTXM2SxD : signal is "true";
+ -- attribute mark_debug of SouthTXS2MxD : signal is "true";
+ -- attribute keep of SouthTXS2MxD : signal is "true";
+ -- attribute mark_debug of WestTXM2SxD : signal is "true";
+ -- attribute keep of WestTXM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXS2MxD : signal is "true";
+ -- attribute keep of WestTXS2MxD : signal is "true";
+ -- attribute mark_debug of NorthRXM2SxD : signal is "true";
+ -- attribute keep of NorthRXM2SxD : signal is "true";
+ -- attribute mark_debug of NorthRXS2MxD : signal is "true";
+ -- attribute keep of NorthRXS2MxD : signal is "true";
+ -- attribute mark_debug of EastRXM2SxD : signal is "true";
+ -- attribute keep of EastRXM2SxD : signal is "true";
+ -- attribute mark_debug of EastRXS2MxD : signal is "true";
+ -- attribute keep of EastRXS2MxD : signal is "true";
+ -- attribute mark_debug of SouthRXM2SxD : signal is "true";
+ -- attribute keep of SouthRXM2SxD : signal is "true";
+ -- attribute mark_debug of SouthRXS2MxD : signal is "true";
+ -- attribute keep of SouthRXS2MxD : signal is "true";
+ -- attribute mark_debug of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute mark_debug of WestRXS2MxD : signal is "true";
+ -- attribute keep of WestRXS2MxD : signal is "true";
begin
@@ -891,7 +891,9 @@ begin
(WordxD => std_ulogic_vector(to_unsigned(16#02334455#, (C_BYTE_SIZE * 4))),
IdxD => 7));
- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
+ -- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
+
+ type t_write_sp_states is (E_WR_SP_IDLE_0, E_WR_SP_VALID_0, E_WR_SP_WAIT_0, E_WR_SP_IDLE_1, E_WR_SP_VALID_1, E_WR_SP_WAIT_1);
signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Scalp Packets
@@ -914,8 +916,8 @@ begin
signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
signal VioWrSpValidxS : std_ulogic := '0';
-- Scalp Packet
- attribute mark_debug of ScalpPacket0xD : signal is "true";
- attribute keep of ScalpPacket0xD : signal is "true";
+ -- attribute mark_debug of ScalpPacket0xD : signal is "true";
+ -- attribute keep of ScalpPacket0xD : signal is "true";
attribute mark_debug of ScalpPacketValid12xS : signal is "true";
attribute keep of ScalpPacketValid12xS : signal is "true";
-- VIO
@@ -1141,7 +1143,7 @@ begin
ScalpRouterResetxRNA) is
begin -- process UpdateRegxP
if ScalpRouterResetxRNA = '0' then
- WrSPStatexDP <= E_WR_SP_IDLE;
+ WrSPStatexDP <= E_WR_SP_IDLE_0;
elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
WrSPStatexDP <= WrSPStatexDN;
end if;
@@ -1154,18 +1156,32 @@ begin
ScalpPacketValid12xS <= '0';
case WrSPStatexDP is
- when E_WR_SP_IDLE =>
+ when E_WR_SP_IDLE_0 =>
if VioWrSpValidxS = '1' then
ScalpPacketValid12xS <= '1';
- WrSPStatexDN <= E_WR_SP_VALID;
+ WrSPStatexDN <= E_WR_SP_VALID_0;
end if;
- when E_WR_SP_VALID =>
+ when E_WR_SP_VALID_0 =>
ScalpPacketValid12xS <= '0';
- WrSPStatexDN <= E_WR_SP_WAIT;
- when E_WR_SP_WAIT =>
+ WrSPStatexDN <= E_WR_SP_WAIT_0;
+ when E_WR_SP_WAIT_0 =>
+ WrSPStatexDN <= E_WR_SP_IDLE_1;
+
+ when E_WR_SP_IDLE_1 =>
+ ScalpPacketValid12xS <= '1';
+ WrSPStatexDN <= E_WR_SP_VALID_1;
+
+ when E_WR_SP_VALID_1 =>
+ ScalpPacketValid12xS <= '0';
+ WrSPStatexDN <= E_WR_SP_WAIT_1;
+
+ when E_WR_SP_WAIT_1 =>
if VioWrSpValidxS = '0' then
- WrSPStatexDN <= E_WR_SP_IDLE;
+ WrSPStatexDN <= E_WR_SP_IDLE_0;
end if;
+ -- if VioWrSpValidxS = '0' then
+ -- WrSPStatexDN <= E_WR_SP_IDLE;
+ -- end if;
when others => null;
end case;
end process SpValidxP;