diff --git a/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
index c9dc22b422aa3a597aa2a81c629da3ee5a86d8a1..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
+++ b/designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc
@@ -1,65 +0,0 @@
-
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPyhxI/ClkRstxB.AuroraClockModulexI/AuroraClkxCO[InitClkxC]}]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 4 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {AuroraResetMasterLinkxR[LinkResetxR][0]} {AuroraResetMasterLinkxR[LinkResetxR][1]} {AuroraResetMasterLinkxR[LinkResetxR][2]} {AuroraResetMasterLinkxR[LinkResetxR][3]}]]
-create_debug_core u_ila_1 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
-set_property port_width 1 [get_debug_ports u_ila_1/clk]
-connect_debug_port u_ila_1/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPyhxI/ClkRstxB.AuroraClockModulexI/CLK]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
-set_property port_width 4 [get_debug_ports u_ila_1/probe0]
-connect_debug_port u_ila_1/probe0 [get_nets [list {AuroraResetMasterLinkxR[SystemResetxR][0]} {AuroraResetMasterLinkxR[SystemResetxR][1]} {AuroraResetMasterLinkxR[SystemResetxR][2]} {AuroraResetMasterLinkxR[SystemResetxR][3]}]]
-create_debug_core u_ila_2 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
-set_property port_width 1 [get_debug_ports u_ila_2/clk]
-connect_debug_port u_ila_2/clk [get_nets [list ProgrammableLogicxB.PllClocksxB.ScalpAuroraPllxI/inst/InitClkxCO]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
-set_property port_width 1 [get_debug_ports u_ila_2/probe0]
-connect_debug_port u_ila_2/probe0 [get_nets [list {AuroraResetSlavexR[GTResetxR]}]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
-set_property port_width 1 [get_debug_ports u_ila_2/probe1]
-connect_debug_port u_ila_2/probe1 [get_nets [list {AuroraResetSlavexR[ResetxR]}]]
-create_debug_core u_ila_3 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_3]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_3]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_3]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_3]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_3]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3]
-set_property port_width 1 [get_debug_ports u_ila_3/clk]
-connect_debug_port u_ila_3/clk [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe0]
-set_property port_width 1 [get_debug_ports u_ila_3/probe0]
-connect_debug_port u_ila_3/probe0 [get_nets [list PSSysResetxR]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc
index cb0705da09c971d18cb46e653b1e0c1a557ba25b..9466d9aa08d4562d30bfd5d7a6b221000071e19a 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc
+++ b/designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc
@@ -246,3 +246,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
diff --git a/designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc
index 3ed9c079b9fae2f8d360c69c0c787e9fe5110903..4960acac7ff88f27f9e599140c4a946845d1cfc0 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc
@@ -26,3 +26,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+
diff --git a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
index e49a1019180576010563b2b90c6ea286e4c5ed49..e9010e62cb1c62babee9310df8877b965680a849 100644
--- a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: scalp_firmware
--
--- Last update: 2020-11-08
+-- Last update: 2020-11-10
--
---------------------------------------------------------------------------------
@@ -429,71 +429,187 @@ architecture arch of scalp_firmware is
-- Zynq Reg Bank
type t_status_send_word is (E_IDLE, E_SEND);
- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
- signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
- signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
- signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
+ signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
+ signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
+ signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
+ signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
--
- signal NorthNativeSlavexD : t_native_fifo_slave;
- signal NorthNativeMasterxD : t_native_fifo_master;
- signal EastNativeSlavexD : t_native_fifo_slave;
- signal EastNativeMasterxD : t_native_fifo_master;
- signal SouthNativeSlavexD : t_native_fifo_slave;
- signal SouthNativeMasterxD : t_native_fifo_master;
- signal WestNativeSlavexD : t_native_fifo_slave;
- signal WestNativeMasterxD : t_native_fifo_master;
+ signal NorthNativeSlavexD : t_native_fifo_slave;
+ signal NorthNativeMasterxD : t_native_fifo_master;
+ signal EastNativeSlavexD : t_native_fifo_slave;
+ signal EastNativeMasterxD : t_native_fifo_master;
+ signal SouthNativeSlavexD : t_native_fifo_slave;
+ signal SouthNativeMasterxD : t_native_fifo_master;
+ signal WestNativeSlavexD : t_native_fifo_slave;
+ signal WestNativeMasterxD : t_native_fifo_master;
--
-- signal InterruptRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- signal InterruptRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- North
- signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- East
- signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- South
- signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- West
- signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ -- Debug
+ -- signal CntRstxR : std_ulogic := '0';
+ signal ClkEnxS : std_ulogic := '0';
+ signal DataCounterxD : std_ulogic_vector(31 downto 0) := (others => '0');
+ --
+ signal DebugCounterResetxR : std_ulogic := '0';
+ signal DebugRXFifoResetxR : std_ulogic := '0';
+ signal DebugBackPressureResetxR : std_ulogic := '0';
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
-- Resets
- attribute mark_debug of PSSysResetxR : signal is "true";
- attribute keep of PSSysResetxR : signal is "true";
- attribute mark_debug of AuroraResetSlavexR : signal is "true";
- attribute keep of AuroraResetSlavexR : signal is "true";
- attribute mark_debug of AuroraResetMasterLinkxR : signal is "true";
- attribute keep of AuroraResetMasterLinkxR : signal is "true";
+ -- attribute mark_debug of PSSysResetxR : signal is "true";
+ -- attribute keep of PSSysResetxR : signal is "true";
+ -- attribute mark_debug of AuroraResetSlavexR : signal is "true";
+ -- attribute keep of AuroraResetSlavexR : signal is "true";
+ -- attribute mark_debug of AuroraResetMasterLinkxR : signal is "true";
+ -- attribute keep of AuroraResetMasterLinkxR : signal is "true";
+ -- Aurora
+ attribute mark_debug of NorthFifoStatusxD : signal is "true";
+ attribute keep of NorthFifoStatusxD : signal is "true";
+ attribute mark_debug of EastFifoStatusxD : signal is "true";
+ attribute keep of EastFifoStatusxD : signal is "true";
+ attribute mark_debug of SouthFifoStatusxD : signal is "true";
+ attribute keep of SouthFifoStatusxD : signal is "true";
+ attribute mark_debug of WestFifoStatusxD : signal is "true";
+ attribute keep of WestFifoStatusxD : signal is "true";
+ -- attribute mark_debug of NorthRXM2SxD : signal is "true";
+ -- attribute keep of NorthRXM2SxD : signal is "true";
+ -- attribute mark_debug of NorthRXFromFifoS2MxD : signal is "true";
+ -- attribute keep of NorthRXFromFifoS2MxD : signal is "true";
+ -- attribute mark_debug of NorthRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute keep of NorthRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute mark_debug of NorthRXfromPhyTXfromFifoS2MxD : signal is "true";
+ -- attribute keep of NorthRXfromPhyTXfromFifoS2MxD : signal is "true";
+ -- attribute mark_debug of EastFifoStatusxD : signal is "true";
+ -- attribute keep of EastFifoStatusxD : signal is "true";
+ -- attribute mark_debug of EastRXM2SxD : signal is "true";
+ -- attribute keep of EastRXM2SxD : signal is "true";
+ -- attribute mark_debug of EastRXFromFifoS2MxD : signal is "true";
+ -- attribute keep of EastRXFromFifoS2MxD : signal is "true";
+ -- attribute mark_debug of EastRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute keep of EastRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute mark_debug of EastRXfromPhyTXfromFifoS2MxD : signal is "true";
+ -- attribute keep of EastRXfromPhyTXfromFifoS2MxD : signal is "true";
+ -- attribute mark_debug of SouthFifoStatusxD : signal is "true";
+ -- attribute keep of SouthFifoStatusxD : signal is "true";
+ -- attribute mark_debug of SouthRXM2SxD : signal is "true";
+ -- attribute keep of SouthRXM2SxD : signal is "true";
+ -- attribute mark_debug of SouthRXFromFifoS2MxD : signal is "true";
+ -- attribute keep of SouthRXFromFifoS2MxD : signal is "true";
+ -- attribute mark_debug of SouthRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute keep of SouthRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute mark_debug of SouthRXfromPhyTXfromFifoS2MxD : signal is "true";
+ -- attribute keep of SouthRXfromPhyTXfromFifoS2MxD : signal is "true";
+ -- attribute mark_debug of WestFifoStatusxD : signal is "true";
+ -- attribute keep of WestFifoStatusxD : signal is "true";
+ -- attribute mark_debug of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute mark_debug of WestRXFromFifoS2MxD : signal is "true";
+ -- attribute keep of WestRXFromFifoS2MxD : signal is "true";
+ -- attribute mark_debug of WestRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute keep of WestRXfromPhyTXfromFifoM2SxD : signal is "true";
+ -- attribute mark_debug of WestRXfromPhyTXfromFifoS2MxD : signal is "true";
+ -- attribute keep of WestRXfromPhyTXfromFifoS2MxD : signal is "true";
+ --
+ attribute mark_debug of NorthRXM2SxD : signal is "true";
+ attribute keep of NorthRXM2SxD : signal is "true";
+ attribute mark_debug of NorthTXM2SxD : signal is "true";
+ attribute keep of NorthTXM2SxD : signal is "true";
+ attribute mark_debug of NorthTXS2MxD : signal is "true";
+ attribute keep of NorthTXS2MxD : signal is "true";
+ attribute mark_debug of EastRXM2SxD : signal is "true";
+ attribute keep of EastRXM2SxD : signal is "true";
+ attribute mark_debug of EastTXM2SxD : signal is "true";
+ attribute keep of EastTXM2SxD : signal is "true";
+ attribute mark_debug of EastTXS2MxD : signal is "true";
+ attribute keep of EastTXS2MxD : signal is "true";
+ attribute mark_debug of SouthRXM2SxD : signal is "true";
+ attribute keep of SouthRXM2SxD : signal is "true";
+ attribute mark_debug of SouthTXM2SxD : signal is "true";
+ attribute keep of SouthTXM2SxD : signal is "true";
+ attribute mark_debug of SouthTXS2MxD : signal is "true";
+ attribute keep of SouthTXS2MxD : signal is "true";
+ attribute mark_debug of WestRXM2SxD : signal is "true";
+ attribute keep of WestRXM2SxD : signal is "true";
+ attribute mark_debug of WestTXM2SxD : signal is "true";
+ attribute keep of WestTXM2SxD : signal is "true";
+ attribute mark_debug of WestTXS2MxD : signal is "true";
+ attribute keep of WestTXS2MxD : signal is "true";
+ attribute mark_debug of NorthRXNFCM2SxD : signal is "true";
+ attribute keep of NorthRXNFCM2SxD : signal is "true";
+ attribute mark_debug of NorthTXNFCM2SxD : signal is "true";
+ attribute keep of NorthTXNFCM2SxD : signal is "true";
+ attribute mark_debug of NorthTXNFCS2MxD : signal is "true";
+ attribute keep of NorthTXNFCS2MxD : signal is "true";
+ attribute mark_debug of EastRXNFCM2SxD : signal is "true";
+ attribute keep of EastRXNFCM2SxD : signal is "true";
+ attribute mark_debug of EastTXNFCM2SxD : signal is "true";
+ attribute keep of EastTXNFCM2SxD : signal is "true";
+ attribute mark_debug of EastTXNFCS2MxD : signal is "true";
+ attribute keep of EastTXNFCS2MxD : signal is "true";
+ attribute mark_debug of SouthRXNFCM2SxD : signal is "true";
+ attribute keep of SouthRXNFCM2SxD : signal is "true";
+ attribute mark_debug of SouthTXNFCM2SxD : signal is "true";
+ attribute keep of SouthTXNFCM2SxD : signal is "true";
+ attribute mark_debug of SouthTXNFCS2mxD : signal is "true";
+ attribute keep of SouthTXNFCS2mxD : signal is "true";
+ attribute mark_debug of WestRXNFCM2SxD : signal is "true";
+ attribute keep of WestRXNFCM2SxD : signal is "true";
+ attribute mark_debug of WestTXNFCM2SxD : signal is "true";
+ attribute keep of WestTXNFCM2SxD : signal is "true";
+ attribute mark_debug of WestTXNFCS2MxD : signal is "true";
+ attribute keep of WestTXNFCS2MxD : signal is "true";
+ attribute mark_debug of AuroraCtrlxD : signal is "true";
+ attribute keep of AuroraCtrlxD : signal is "true";
+ attribute mark_debug of AuroraStatusxD : signal is "true";
+ attribute keep of AuroraStatusxD : signal is "true";
+ -- attribute mark_debug of NorthTXM2SxD : signal is "true";
+ -- attribute keep of NorthTXM2SxD : signal is "true";
+ -- attribute mark_debug of EastTXM2SxD : signal is "true";
+ -- attribute keep of EastTXM2SxD : signal is "true";
+ -- attribute mark_debug of SouthTXM2SxD : signal is "true";
+ -- attribute keep of SouthTXM2SxD : signal is "true";
+ -- attribute mark_debug of WestTXM2SxD : signal is "true";
+ -- attribute keep of WestTXM2SxD : signal is "true";
begin
@@ -734,7 +850,7 @@ begin
begin -- block RXFifoxB
- RXFifoRstxAS : RXFifoRstxRAN <= not AuroraClkMasterxC.PllNotLockedxS;
+ RXFifoRstxAS : RXFifoRstxRAN <= (not AuroraClkMasterxC.PllNotLockedxS) and (not DebugRXFifoResetxR);
ScalpAuroraPhyRXFifoxI : entity work.scalp_aurora_phy_rx_fifo
port map (
@@ -779,53 +895,91 @@ begin
BackPressurexB : block is
+ signal BackPressureResetxR : std_ulogic := '0';
-- North
- signal NorthProgFullxSN : std_ulogic := '0';
- signal NorthProgFullxSP : std_ulogic := '0';
- signal NorthProgEmptyxSN : std_ulogic := '0';
- signal NorthProgEmptyxSP : std_ulogic := '0';
- signal NorthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal NorthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal NorthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthNFCValidxSN : std_ulogic := '0';
- signal NorthNFCValidxSP : std_ulogic := '0';
+ signal NorthProgFullxSN : std_ulogic := '0';
+ signal NorthProgFullxSP : std_ulogic := '0';
+ signal NorthProgEmptyxSN : std_ulogic := '0';
+ signal NorthProgEmptyxSP : std_ulogic := '0';
+ signal NorthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal NorthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal NorthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal NorthNFCValidxSN : std_ulogic := '0';
+ signal NorthNFCValidxSP : std_ulogic := '0';
-- East
- signal EastProgFullxSN : std_ulogic := '0';
- signal EastProgFullxSP : std_ulogic := '0';
- signal EastProgEmptyxSN : std_ulogic := '0';
- signal EastProgEmptyxSP : std_ulogic := '0';
- signal EastNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal EastNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal EastNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal EastNFCValidxSN : std_ulogic := '0';
- signal EastNFCValidxSP : std_ulogic := '0';
+ signal EastProgFullxSN : std_ulogic := '0';
+ signal EastProgFullxSP : std_ulogic := '0';
+ signal EastProgEmptyxSN : std_ulogic := '0';
+ signal EastProgEmptyxSP : std_ulogic := '0';
+ signal EastNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal EastNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal EastNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal EastNFCValidxSN : std_ulogic := '0';
+ signal EastNFCValidxSP : std_ulogic := '0';
-- South
- signal SouthProgFullxSN : std_ulogic := '0';
- signal SouthProgFullxSP : std_ulogic := '0';
- signal SouthProgEmptyxSN : std_ulogic := '0';
- signal SouthProgEmptyxSP : std_ulogic := '0';
- signal SouthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal SouthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal SouthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal SouthNFCValidxSN : std_ulogic := '0';
- signal SouthNFCValidxSP : std_ulogic := '0';
+ signal SouthProgFullxSN : std_ulogic := '0';
+ signal SouthProgFullxSP : std_ulogic := '0';
+ signal SouthProgEmptyxSN : std_ulogic := '0';
+ signal SouthProgEmptyxSP : std_ulogic := '0';
+ signal SouthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal SouthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal SouthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal SouthNFCValidxSN : std_ulogic := '0';
+ signal SouthNFCValidxSP : std_ulogic := '0';
-- West
- signal WestProgFullxSN : std_ulogic := '0';
- signal WestProgFullxSP : std_ulogic := '0';
- signal WestProgEmptyxSN : std_ulogic := '0';
- signal WestProgEmptyxSP : std_ulogic := '0';
- signal WestNFCStatexDN : t_nfc_states := C_NFC_IDLE;
- signal WestNFCStatexDP : t_nfc_states := C_NFC_IDLE;
- signal WestNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WestNFCValidxSN : std_ulogic := '0';
- signal WestNFCValidxSP : std_ulogic := '0';
+ signal WestProgFullxSN : std_ulogic := '0';
+ signal WestProgFullxSP : std_ulogic := '0';
+ signal WestProgEmptyxSN : std_ulogic := '0';
+ signal WestProgEmptyxSP : std_ulogic := '0';
+ signal WestNFCStatexDN : t_nfc_states := C_NFC_IDLE;
+ signal WestNFCStatexDP : t_nfc_states := C_NFC_IDLE;
+ signal WestNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WestNFCValidxSN : std_ulogic := '0';
+ signal WestNFCValidxSP : std_ulogic := '0';
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ attribute mark_debug of BackPressureResetxR : signal is "true";
+ attribute keep of BackPressureResetxR : signal is "true";
+ --
+ attribute mark_debug of NorthNFCStatexDP : signal is "true";
+ attribute keep of NorthNFCStatexDP : signal is "true";
+ attribute mark_debug of NorthNFCDataxDP : signal is "true";
+ attribute keep of NorthNFCDataxDP : signal is "true";
+ attribute mark_debug of NorthNFCValidxSP : signal is "true";
+ attribute keep of NorthNFCValidxSP : signal is "true";
+ --
+ attribute mark_debug of EastNFCStatexDP : signal is "true";
+ attribute keep of EastNFCStatexDP : signal is "true";
+ attribute mark_debug of EastNFCDataxDP : signal is "true";
+ attribute keep of EastNFCDataxDP : signal is "true";
+ attribute mark_debug of EastNFCValidxSP : signal is "true";
+ attribute keep of EastNFCValidxSP : signal is "true";
+ --
+ attribute mark_debug of SouthNFCStatexDP : signal is "true";
+ attribute keep of SouthNFCStatexDP : signal is "true";
+ attribute mark_debug of SouthNFCDataxDP : signal is "true";
+ attribute keep of SouthNFCDataxDP : signal is "true";
+ attribute mark_debug of SouthNFCValidxSP : signal is "true";
+ attribute keep of SouthNFCValidxSP : signal is "true";
+ --
+ attribute mark_debug of WestNFCStatexDP : signal is "true";
+ attribute keep of WestNFCStatexDP : signal is "true";
+ attribute mark_debug of WestNFCDataxDP : signal is "true";
+ attribute keep of WestNFCDataxDP : signal is "true";
+ attribute mark_debug of WestNFCValidxSP : signal is "true";
+ attribute keep of WestNFCValidxSP : signal is "true";
begin -- block BackPressurexB
+ BackPressureResetxAS : BackPressureResetxR <= AuroraClkMasterxC.PllNotLockedxS or
+ DebugBackPressureResetxR;
-- NFC Data and valid signals
NorthNFCDataxAS : NorthTXNFCM2SxD.DataxD <= NorthNFCDataxDP;
NorthNFCValidxAS : NorthTXNFCM2SxD.ValidxS <= NorthNFCValidxSP;
@@ -838,10 +992,10 @@ begin
WestNFCDataxAS : WestTXNFCM2SxD.DataxD <= WestNFCDataxDP;
WestNFCValidxAS : WestTXNFCM2SxD.ValidxS <= WestNFCValidxSP;
- UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
- AuroraClkMasterxC.UserClkxC) is
+ UpdateRegxP : process (AuroraClkMasterxC.UserClkxC,
+ BackPressureResetxR) is
begin -- process UpdateRegxP
- if not AuroraClkMasterxC.PllNotLockedxS then
+ if BackPressureResetxR = '1' then
NorthProgFullxSP <= '0';
NorthProgEmptyxSP <= '0';
NorthNFCStatexDP <= C_NFC_IDLE;
@@ -890,8 +1044,7 @@ begin
NorthNFCValidxSP, NorthProgEmptyxSN,
NorthProgEmptyxSP, NorthProgFullxSN,
NorthProgFullxSP,
- NorthRXFromFifoS2MxD.ReadyxS,
- NorthTXUFCS2MxD.ReadyxS) is
+ NorthTXNFCS2MxD.ReadyxS) is
begin -- process NorthNFCStatexP
-- Default values
NorthNFCStatexDN <= NorthNFCStatexDP;
@@ -902,29 +1055,29 @@ begin
when C_NFC_IDLE =>
NorthNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
- if (NorthProgFullxSP = '0' and NorthProgFullxSN = '1') or
- (NorthRXFromFifoS2MxD.ReadyxS = '0') then
+ if NorthProgFullxSP = '0' and NorthProgFullxSN = '1' then --or
+ --(NorthRXFromFifoS2MxD.ReadyxS = '0') then
NorthNFCDataxDN <= C_NFC_XOFF;
NorthNFCValidxSN <= '1';
NorthNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
- if (NorthProgEmptyxSP = '0' and NorthProgEmptyxSN = '1') and
- (NorthRXFromFifoS2MxD.ReadyxS = '1') then
+ if NorthProgEmptyxSP = '0' and NorthProgEmptyxSN = '1' then -- and
+ --(NorthRXFromFifoS2MxD.ReadyxS = '1') then
NorthNFCDataxDN <= C_NFC_XON;
NorthNFCValidxSN <= '1';
NorthNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
- if NorthTXUFCS2MxD.ReadyxS = '1' then
+ if NorthTXNFCS2MxD.ReadyxS = '1' then
NorthNFCValidxSN <= '0';
NorthNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
- if NorthTXUFCS2MxD.ReadyxS = '1' then
+ if NorthTXNFCS2MxD.ReadyxS = '1' then
NorthNFCValidxSN <= '0';
NorthNFCStatexDN <= C_NFC_IS_XOFF;
end if;
@@ -938,8 +1091,7 @@ begin
EastNFCValidxSP, EastProgEmptyxSN,
EastProgEmptyxSP, EastProgFullxSN,
EastProgFullxSP,
- EastRXFromFifoS2MxD.ReadyxS,
- EastTXUFCS2MxD.ReadyxS) is
+ EastTXNFCS2MxD.ReadyxS) is
begin -- process EastNFCStatexP
-- Default values
EastNFCStatexDN <= EastNFCStatexDP;
@@ -950,29 +1102,29 @@ begin
when C_NFC_IDLE =>
EastNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
- if (EastProgFullxSP = '0' and EastProgFullxSN = '1') or
- (EastRXFromFifoS2MxD.ReadyxS = '0') then
+ if EastProgFullxSP = '0' and EastProgFullxSN = '1' then --or
+ --(EastRXFromFifoS2MxD.ReadyxS = '0') then
EastNFCDataxDN <= C_NFC_XOFF;
EastNFCValidxSN <= '1';
EastNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
- if (EastProgEmptyxSP = '0' and EastProgEmptyxSN = '1') and
- (EastRXFromFifoS2MxD.ReadyxS = '1') then
+ if EastProgEmptyxSP = '0' and EastProgEmptyxSN = '1' then -- and
+ --(EastRXFromFifoS2MxD.ReadyxS = '1') then
EastNFCDataxDN <= C_NFC_XON;
EastNFCValidxSN <= '1';
EastNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
- if EastTXUFCS2MxD.ReadyxS = '1' then
+ if EastTXNFCS2MxD.ReadyxS = '1' then
EastNFCValidxSN <= '0';
EastNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
- if EastTXUFCS2MxD.ReadyxS = '1' then
+ if EastTXNFCS2MxD.ReadyxS = '1' then
EastNFCValidxSN <= '0';
EastNFCStatexDN <= C_NFC_IS_XOFF;
end if;
@@ -986,8 +1138,7 @@ begin
SouthNFCValidxSP, SouthProgEmptyxSN,
SouthProgEmptyxSP, SouthProgFullxSN,
SouthProgFullxSP,
- SouthRXFromFifoS2MxD.ReadyxS,
- SouthTXUFCS2MxD.ReadyxS) is
+ SouthTXNFCS2MxD.ReadyxS) is
begin -- process SouthNFCStatexP
-- Default values
SouthNFCStatexDN <= SouthNFCStatexDP;
@@ -998,29 +1149,29 @@ begin
when C_NFC_IDLE =>
SouthNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
- if (SouthProgFullxSP = '0' and SouthProgFullxSN = '1') or
- (SouthRXFromFifoS2MxD.ReadyxS = '0') then
+ if SouthProgFullxSP = '0' and SouthProgFullxSN = '1' then -- or
+ --(SouthRXFromFifoS2MxD.ReadyxS = '0') then
SouthNFCDataxDN <= C_NFC_XOFF;
SouthNFCValidxSN <= '1';
SouthNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
- if (SouthProgEmptyxSP = '0' and SouthProgEmptyxSN = '1') and
- (SouthRXFromFifoS2MxD.ReadyxS = '1') then
+ if SouthProgEmptyxSP = '0' and SouthProgEmptyxSN = '1' then -- and
+ --(SouthRXFromFifoS2MxD.ReadyxS = '1') then
SouthNFCDataxDN <= C_NFC_XON;
SouthNFCValidxSN <= '1';
SouthNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
- if SouthTXUFCS2MxD.ReadyxS = '1' then
+ if SouthTXNFCS2MxD.ReadyxS = '1' then
SouthNFCValidxSN <= '0';
SouthNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
- if SouthTXUFCS2MxD.ReadyxS = '1' then
+ if SouthTXNFCS2MxD.ReadyxS = '1' then
SouthNFCValidxSN <= '0';
SouthNFCStatexDN <= C_NFC_IS_XOFF;
end if;
@@ -1034,8 +1185,7 @@ begin
WestNFCValidxSP, WestProgEmptyxSN,
WestProgEmptyxSP, WestProgFullxSN,
WestProgFullxSP,
- WestRXFromFifoS2MxD.ReadyxS,
- WestTXUFCS2MxD.ReadyxS) is
+ WestTXNFCS2MxD.ReadyxS) is
begin -- process WestNFCStatexP
-- Default values
WestNFCStatexDN <= WestNFCStatexDP;
@@ -1046,29 +1196,29 @@ begin
when C_NFC_IDLE =>
WestNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
- if (WestProgFullxSP = '0' and WestProgFullxSN = '1') or
- (WestRXFromFifoS2MxD.ReadyxS = '0') then
+ if WestProgFullxSP = '0' and WestProgFullxSN = '1' then --or
+ --(WestRXFromFifoS2MxD.ReadyxS = '0') then
WestNFCDataxDN <= C_NFC_XOFF;
WestNFCValidxSN <= '1';
WestNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
- if (WestProgEmptyxSP = '0' and WestProgEmptyxSN = '1') and
- (WestRXFromFifoS2MxD.ReadyxS = '1') then
+ if WestProgEmptyxSP = '0' and WestProgEmptyxSN = '1' then -- and
+ --(WestRXFromFifoS2MxD.ReadyxS = '1') then
WestNFCDataxDN <= C_NFC_XON;
WestNFCValidxSN <= '1';
WestNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
- if WestTXUFCS2MxD.ReadyxS = '1' then
+ if WestTXNFCS2MxD.ReadyxS = '1' then
WestNFCValidxSN <= '0';
WestNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
- if WestTXUFCS2MxD.ReadyxS = '1' then
+ if WestTXNFCS2MxD.ReadyxS = '1' then
WestNFCValidxSN <= '0';
WestNFCStatexDN <= C_NFC_IS_XOFF;
end if;
@@ -1082,410 +1232,414 @@ begin
end block GTPhyxB;
- ZynqRegBankxB : block is
- begin -- block ZynqRegBankxB
-
-
- RegBankxB : block is
- begin -- block RegBankxB
-
- WriteRegPortxP : process (EastCtrlRegPortxDP,
- EastWrDataRegPortxDP,
- NorthCtrlRegPortxDP,
- NorthWrDataRegPortxDP,
- SouthCtrlRegPortxDP,
- SouthWrDataRegPortxDP,
- WestCtrlRegPortxDP,
- WestWrDataRegPortxDP, WrAddrxD,
- WrDataxD, WrValidxS) is
- begin -- process WriteRegPortxP
- -- North
- NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP;
- NorthWrDataRegPortxDN <= NorthWrDataRegPortxDP;
- -- East
- EastCtrlRegPortxDN <= EastCtrlRegPortxDP;
- EastWrDataRegPortxDN <= EastWrDataRegPortxDP;
- -- South
- SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP;
- SouthWrDataRegPortxDN <= SouthWrDataRegPortxDP;
- -- West
- WestCtrlRegPortxDN <= WestCtrlRegPortxDP;
- WestWrDataRegPortxDN <= WestWrDataRegPortxDP;
-
- if WrValidxS = '1' then
- case WrAddrxD is
- -- Ctrl
- -- North
- when x"000" => NorthCtrlRegPortxDN <= WrDataxD;
- when x"004" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP or WrDataxD;
- when x"008" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP and not WrDataxD;
- -- East
- when x"00c" => EastCtrlRegPortxDN <= WrDataxD;
- when x"010" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP or WrDataxD;
- when x"014" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP and not WrDataxD;
- -- South
- when x"018" => SouthCtrlRegPortxDN <= WrDataxD;
- when x"01c" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP or WrDataxD;
- when x"020" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP and not WrDataxD;
- -- East
- when x"024" => WestCtrlRegPortxDN <= WrDataxD;
- when x"028" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP or WrDataxD;
- when x"02c" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP and not WrDataxD;
- -- Data
- -- North
- when x"030" => NorthWrDataRegPortxDN <= WrDataxD;
- -- East
- when x"034" => EastWrDataRegPortxDN <= WrDataxD;
- -- South
- when x"038" => SouthWrDataRegPortxDN <= WrDataxD;
- -- West
- when x"03c" => WestWrDataRegPortxDN <= WrDataxD;
- when others => null;
- end case;
- end if;
- end process WriteRegPortxP;
-
- ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
- begin -- process ReadRegPortxP
- if PSSysResetxR = '1' then
- RdDataxD <= (others => '0');
- elsif rising_edge(PSSysClkxC) then
- RdDataxD <= (others => '0');
-
- if RdValidxS = '1' then
- case RdAddrxD is
- when x"000" => RdDataxD <= NorthCtrlRegPortxDP;
- when x"00C" => RdDataxD <= EastCtrlRegPortxDP;
- when x"018" => RdDataxD <= SouthCtrlRegPortxDP;
- when x"024" => RdDataxD <= WestCtrlRegPortxDP;
- when x"030" => RdDataxD <= NorthWrDataRegPortxDP;
- when x"034" => RdDataxD <= EastWrDataRegPortxDP;
- when x"038" => RdDataxD <= SouthWrDataRegPortxDP;
- when x"03c" => RdDataxD <= WestWrDataRegPortxDP;
- when x"040" => RdDataxD <= NorthStatusRegPortxDP;
- when x"044" => RdDataxD <= EastStatusRegPortxDP;
- when x"048" => RdDataxD <= SouthStatusRegPortxDP;
- when x"04c" => RdDataxD <= WestStatusRegPortxDP;
- when others => RdDataxD <= (others => '0');
- end case;
- end if;
- end if;
- end process ReadRegPortxP;
-
- RegBankxP : process (PSSysClkxC, PSSysResetxR) is
- begin -- process RegBankxP
- if PSSysResetxR = '1' then
- -- North
- NorthStatusRegPortxDP <= (others => '0');
- NorthCtrlRegPortxDP <= (others => '0');
- NorthWrDataRegPortxDP <= (others => '0');
- -- East
- EastStatusRegPortxDP <= (others => '0');
- EastCtrlRegPortxDP <= (others => '0');
- EastWrDataRegPortxDP <= (others => '0');
- -- South
- SouthStatusRegPortxDP <= (others => '0');
- SouthCtrlRegPortxDP <= (others => '0');
- SouthWrDataRegPortxDP <= (others => '0');
- -- West
- WestStatusRegPortxDP <= (others => '0');
- WestCtrlRegPortxDP <= (others => '0');
- WestWrDataRegPortxDP <= (others => '0');
- elsif rising_edge(PSSysClkxC) then
- -- North
- NorthStatusRegPortxDP <= NorthStatusRegPortxDN;
- NorthCtrlRegPortxDP <= NorthCtrlRegPortxDN;
- NorthWrDataRegPortxDP <= NorthWrDataRegPortxDN;
- -- East
- EastStatusRegPortxDP <= EastStatusRegPortxDN;
- EastCtrlRegPortxDP <= EastCtrlRegPortxDN;
- EastWrDataRegPortxDP <= EastWrDataRegPortxDN;
- -- South
- SouthStatusRegPortxDP <= SouthStatusRegPortxDN;
- SouthCtrlRegPortxDP <= SouthCtrlRegPortxDN;
- SouthWrDataRegPortxDP <= SouthWrDataRegPortxDN;
- -- West
- WestStatusRegPortxDP <= WestStatusRegPortxDN;
- WestCtrlRegPortxDP <= WestCtrlRegPortxDN;
- WestWrDataRegPortxDP <= WestWrDataRegPortxDN;
- end if;
- end process RegBankxP;
-
- end block RegBankxB;
-
- TxFifoxB : block is
- begin -- block TxFifoxB
-
- NorthWrDataxAS : NorthNativeSlavexD.DataxD <= NorthWrDataRegPortxDP;
- EastWrDataxAS : EastNativeSlavexD.DataxD <= EastWrDataRegPortxDP;
- SouthWrDataxAS : SouthNativeSlavexD.DataxD <= SouthWrDataRegPortxDN;
- WestWrDataRegxAS : WestNativeSlavexD.DataxD <= WestWrDataRegPortxDN;
- NorthWrEnxAS : NorthNativeSlavexD.WrEnxS <= NorthCtrlRegPortxDP(0);
- EastWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
- SouthWrEnxAS : SouthNativeSlavexD.WrEnxS <= SouthCtrlRegPortxDP(0);
- WestWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
- NorthStatusRegPortxAS : NorthStatusRegPortxDN <= (0 => NorthNativeMasterxD.FullxS,
- 1 => NorthNativeMasterxD.EmptyxS,
- 2 => NorthNativeMasterxD.AlmostFullxS,
- 3 => NorthNativeMasterxD.AlmostEmptyxS,
- 4 => NorthNativeMasterxD.WrRstBusyxS,
- 5 => NorthNativeMasterxD.RdRstBusyxS,
- others => '0');
- EastStatusRegPortxAS : EastStatusRegPortxDN <= (0 => EastNativeMasterxD.FullxS,
- 1 => EastNativeMasterxD.EmptyxS,
- 2 => EastNativeMasterxD.AlmostFullxS,
- 3 => EastNativeMasterxD.AlmostEmptyxS,
- 4 => EastNativeMasterxD.WrRstBusyxS,
- 5 => EastNativeMasterxD.RdRstBusyxS,
- others => '0');
- SouthStatusRegPortxAS : SouthStatusRegPortxDN <= (0 => SouthNativeMasterxD.FullxS,
- 1 => SouthNativeMasterxD.EmptyxS,
- 2 => SouthNativeMasterxD.AlmostFullxS,
- 3 => SouthNativeMasterxD.AlmostEmptyxS,
- 4 => SouthNativeMasterxD.WrRstBusyxS,
- 5 => SouthNativeMasterxD.RdRstBusyxS,
- others => '0');
- WestStatusRegPortxAS : WestStatusRegPortxDN <= (0 => WestNativeMasterxD.FullxS,
- 1 => WestNativeMasterxD.EmptyxS,
- 2 => WestNativeMasterxD.AlmostFullxS,
- 3 => WestNativeMasterxD.AlmostEmptyxS,
- 4 => WestNativeMasterxD.WrRstBusyxS,
- 5 => WestNativeMasterxD.RdRstBusyxS,
- others => '0');
-
- UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
- AuroraClkMasterxC.UserClkxC) is
- begin -- process UpdateRegxP
- if not AuroraClkMasterxC.PllNotLockedxS then
- NorthStatusSendWordxDP <= E_IDLE;
- EastStatusSendWordxDP <= E_IDLE;
- SouthStatusSendWordxDP <= E_IDLE;
- WestStatusSendWordxDP <= E_IDLE;
- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
- NorthStatusSendWordxDP <= NorthStatusSendWordxDN;
- EastStatusSendWordxDP <= EastStatusSendWordxDN;
- SouthStatusSendWordxDP <= SouthStatusSendWordxDN;
- WestStatusSendWordxDP <= WestStatusSendWordxDN;
- end if;
- end process UpdateRegxP;
-
- NorthSendWordxP : process (NorthNativeMasterxD.DataxD,
- NorthNativeMasterxD.EmptyxS,
- NorthStatusSendWordxDP,
- NorthTXS2MxD.ReadyxS) is
- begin -- process NorthSendWordxP
- NorthTXM2SxD.DataxD <= (others => '0');
- NorthTXM2SxD.KeepxD <= (others => '1');
- NorthTXM2SxD.LastxS <= '0';
- NorthTXM2SxD.ValidxS <= '0';
- NorthNativeSlavexD.RdEnxS <= '0';
- NorthStatusSendWordxDN <= NorthStatusSendWordxDP;
-
- case NorthStatusSendWordxDP is
- when E_IDLE =>
-
- if (NorthNativeMasterxD.EmptyxS = '0') and
- (NorthTXS2MxD.ReadyxS = '1') then
- NorthTXM2SxD.DataxD <= NorthNativeMasterxD.DataxD;
- NorthTXM2SxD.LastxS <= '1';
- NorthTXM2SxD.ValidxS <= '1';
- NorthNativeSlavexD.RdEnxS <= '1';
- NorthStatusSendWordxDN <= E_SEND;
- end if;
-
- when E_SEND =>
- NorthStatusSendWordxDN <= E_IDLE;
-
- when others => null;
- end case;
- end process NorthSendWordxP;
-
- EastSendWordxP : process (EastNativeMasterxD.DataxD,
- EastNativeMasterxD.EmptyxS,
- EastStatusSendWordxDP,
- EastTXS2MxD.ReadyxS) is
- begin -- process EastSendWordxP
- EastTXM2SxD.DataxD <= (others => '0');
- EastTXM2SxD.KeepxD <= (others => '1');
- EastTXM2SxD.LastxS <= '0';
- EastTXM2SxD.ValidxS <= '0';
- EastNativeSlavexD.RdEnxS <= '0';
- EastStatusSendWordxDN <= EastStatusSendWordxDP;
-
- case EastStatusSendWordxDP is
- when E_IDLE =>
-
- if (EastNativeMasterxD.EmptyxS = '0') and
- (EastTXS2MxD.ReadyxS = '1') then
- EastTXM2SxD.DataxD <= EastNativeMasterxD.DataxD;
- EastTXM2SxD.LastxS <= '1';
- EastTXM2SxD.ValidxS <= '1';
- EastNativeSlavexD.RdEnxS <= '1';
- EastStatusSendWordxDN <= E_SEND;
- end if;
-
- when E_SEND =>
- EastStatusSendWordxDN <= E_IDLE;
-
- when others => null;
- end case;
- end process EastSendWordxP;
-
- SouthSendWordxP : process (SouthNativeMasterxD.DataxD,
- SouthNativeMasterxD.EmptyxS,
- SouthStatusSendWordxDP,
- SouthTXS2MxD.ReadyxS) is
- begin -- process SouthSendWordxP
- SouthTXM2SxD.DataxD <= (others => '0');
- SouthTXM2SxD.KeepxD <= (others => '1');
- SouthTXM2SxD.LastxS <= '0';
- SouthTXM2SxD.ValidxS <= '0';
- SouthNativeSlavexD.RdEnxS <= '0';
- SouthStatusSendWordxDN <= SouthStatusSendWordxDP;
-
- case SouthStatusSendWordxDP is
- when E_IDLE =>
-
- if (SouthNativeMasterxD.EmptyxS = '0') and
- (SouthTXS2MxD.ReadyxS = '1') then
- SouthTXM2SxD.DataxD <= SouthNativeMasterxD.DataxD;
- SouthTXM2SxD.LastxS <= '1';
- SouthTXM2SxD.ValidxS <= '1';
- SouthNativeSlavexD.RdEnxS <= '1';
- SouthStatusSendWordxDN <= E_SEND;
- end if;
-
- when E_SEND =>
- SouthStatusSendWordxDN <= E_IDLE;
-
- when others => null;
- end case;
- end process SouthSendWordxP;
-
- WestSendWordxP : process (WestNativeMasterxD.DataxD,
- WestNativeMasterxD.EmptyxS,
- WestStatusSendWordxDP,
- WestTXS2MxD.ReadyxS) is
- begin -- process WestSendWordxP
- WestTXM2SxD.DataxD <= (others => '0');
- WestTXM2SxD.KeepxD <= (others => '1');
- WestTXM2SxD.LastxS <= '0';
- WestTXM2SxD.ValidxS <= '0';
- WestNativeSlavexD.RdEnxS <= '0';
- WestStatusSendWordxDN <= WestStatusSendWordxDP;
-
- case WestStatusSendWordxDP is
- when E_IDLE =>
-
- if (WestNativeMasterxD.EmptyxS = '0') and
- (WestTXS2MxD.ReadyxS = '1') then
- WestTXM2SxD.DataxD <= WestNativeMasterxD.DataxD;
- WestTXM2SxD.LastxS <= '1';
- WestTXM2SxD.ValidxS <= '1';
- WestNativeSlavexD.RdEnxS <= '1';
- WestStatusSendWordxDN <= E_SEND;
- end if;
-
- when E_SEND =>
- WestStatusSendWordxDN <= E_IDLE;
-
- when others => null;
- end case;
- end process WestSendWordxP;
-
- NorthFifoxI : entity work.scalp_packet_fifo_wrapper
- port map (
- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- WrClkxCI => PSSysClkxC,
- ResetxRI => PSSysResetxR,
- NativeSlavexDI => NorthNativeSlavexD,
- NativeMasterxDO => NorthNativeMasterxD);
-
- EastFifoxI : entity work.scalp_packet_fifo_wrapper
- port map (
- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- WrClkxCI => PSSysClkxC,
- ResetxRI => PSSysResetxR,
- NativeSlavexDI => EastNativeSlavexD,
- NativeMasterxDO => EastNativeMasterxD);
-
- SouthFifoxI : entity work.scalp_packet_fifo_wrapper
- port map (
- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- WrClkxCI => PSSysClkxC,
- ResetxRI => PSSysResetxR,
- NativeSlavexDI => SouthNativeSlavexD,
- NativeMasterxDO => SouthNativeMasterxD);
-
- WestFifoxI : entity work.scalp_packet_fifo_wrapper
- port map (
- RdClkxCI => AuroraClkMasterxC.UserClkxC,
- WrClkxCI => PSSysClkxC,
- ResetxRI => PSSysResetxR,
- NativeSlavexDI => WestNativeSlavexD,
- NativeMasterxDO => WestNativeMasterxD);
-
- end block TxFifoxB;
-
- end block ZynqRegBankxB;
+ -- ZynqRegBankxB : block is
+ -- begin -- block ZynqRegBankxB
+
+
+ -- RegBankxB : block is
+ -- begin -- block RegBankxB
+
+ -- WriteRegPortxP : process (EastCtrlRegPortxDP,
+ -- EastWrDataRegPortxDP,
+ -- NorthCtrlRegPortxDP,
+ -- NorthWrDataRegPortxDP,
+ -- SouthCtrlRegPortxDP,
+ -- SouthWrDataRegPortxDP,
+ -- WestCtrlRegPortxDP,
+ -- WestWrDataRegPortxDP, WrAddrxD,
+ -- WrDataxD, WrValidxS) is
+ -- begin -- process WriteRegPortxP
+ -- -- North
+ -- NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP;
+ -- NorthWrDataRegPortxDN <= NorthWrDataRegPortxDP;
+ -- -- East
+ -- EastCtrlRegPortxDN <= EastCtrlRegPortxDP;
+ -- EastWrDataRegPortxDN <= EastWrDataRegPortxDP;
+ -- -- South
+ -- SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP;
+ -- SouthWrDataRegPortxDN <= SouthWrDataRegPortxDP;
+ -- -- West
+ -- WestCtrlRegPortxDN <= WestCtrlRegPortxDP;
+ -- WestWrDataRegPortxDN <= WestWrDataRegPortxDP;
+
+ -- if WrValidxS = '1' then
+ -- case WrAddrxD is
+ -- -- Ctrl
+ -- -- North
+ -- when x"000" => NorthCtrlRegPortxDN <= WrDataxD;
+ -- when x"004" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP or WrDataxD;
+ -- when x"008" => NorthCtrlRegPortxDN <= NorthCtrlRegPortxDP and not WrDataxD;
+ -- -- East
+ -- when x"00c" => EastCtrlRegPortxDN <= WrDataxD;
+ -- when x"010" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP or WrDataxD;
+ -- when x"014" => EastCtrlRegPortxDN <= EastCtrlRegPortxDP and not WrDataxD;
+ -- -- South
+ -- when x"018" => SouthCtrlRegPortxDN <= WrDataxD;
+ -- when x"01c" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP or WrDataxD;
+ -- when x"020" => SouthCtrlRegPortxDN <= SouthCtrlRegPortxDP and not WrDataxD;
+ -- -- East
+ -- when x"024" => WestCtrlRegPortxDN <= WrDataxD;
+ -- when x"028" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP or WrDataxD;
+ -- when x"02c" => WestCtrlRegPortxDN <= WestCtrlRegPortxDP and not WrDataxD;
+ -- -- Data
+ -- -- North
+ -- when x"030" => NorthWrDataRegPortxDN <= WrDataxD;
+ -- -- East
+ -- when x"034" => EastWrDataRegPortxDN <= WrDataxD;
+ -- -- South
+ -- when x"038" => SouthWrDataRegPortxDN <= WrDataxD;
+ -- -- West
+ -- when x"03c" => WestWrDataRegPortxDN <= WrDataxD;
+ -- when others => null;
+ -- end case;
+ -- end if;
+ -- end process WriteRegPortxP;
+
+ -- ReadRegPortxP : process (PSSysClkxC, PSSysResetxR) is
+ -- begin -- process ReadRegPortxP
+ -- if PSSysResetxR = '1' then
+ -- RdDataxD <= (others => '0');
+ -- elsif rising_edge(PSSysClkxC) then
+ -- RdDataxD <= (others => '0');
+
+ -- if RdValidxS = '1' then
+ -- case RdAddrxD is
+ -- when x"000" => RdDataxD <= NorthCtrlRegPortxDP;
+ -- when x"00C" => RdDataxD <= EastCtrlRegPortxDP;
+ -- when x"018" => RdDataxD <= SouthCtrlRegPortxDP;
+ -- when x"024" => RdDataxD <= WestCtrlRegPortxDP;
+ -- when x"030" => RdDataxD <= NorthWrDataRegPortxDP;
+ -- when x"034" => RdDataxD <= EastWrDataRegPortxDP;
+ -- when x"038" => RdDataxD <= SouthWrDataRegPortxDP;
+ -- when x"03c" => RdDataxD <= WestWrDataRegPortxDP;
+ -- when x"040" => RdDataxD <= NorthStatusRegPortxDP;
+ -- when x"044" => RdDataxD <= EastStatusRegPortxDP;
+ -- when x"048" => RdDataxD <= SouthStatusRegPortxDP;
+ -- when x"04c" => RdDataxD <= WestStatusRegPortxDP;
+ -- when others => RdDataxD <= (others => '0');
+ -- end case;
+ -- end if;
+ -- end if;
+ -- end process ReadRegPortxP;
+
+ -- RegBankxP : process (PSSysClkxC, PSSysResetxR) is
+ -- begin -- process RegBankxP
+ -- if PSSysResetxR = '1' then
+ -- -- North
+ -- NorthStatusRegPortxDP <= (others => '0');
+ -- NorthCtrlRegPortxDP <= (others => '0');
+ -- NorthWrDataRegPortxDP <= (others => '0');
+ -- -- East
+ -- EastStatusRegPortxDP <= (others => '0');
+ -- EastCtrlRegPortxDP <= (others => '0');
+ -- EastWrDataRegPortxDP <= (others => '0');
+ -- -- South
+ -- SouthStatusRegPortxDP <= (others => '0');
+ -- SouthCtrlRegPortxDP <= (others => '0');
+ -- SouthWrDataRegPortxDP <= (others => '0');
+ -- -- West
+ -- WestStatusRegPortxDP <= (others => '0');
+ -- WestCtrlRegPortxDP <= (others => '0');
+ -- WestWrDataRegPortxDP <= (others => '0');
+ -- elsif rising_edge(PSSysClkxC) then
+ -- -- North
+ -- NorthStatusRegPortxDP <= NorthStatusRegPortxDN;
+ -- NorthCtrlRegPortxDP <= NorthCtrlRegPortxDN;
+ -- NorthWrDataRegPortxDP <= NorthWrDataRegPortxDN;
+ -- -- East
+ -- EastStatusRegPortxDP <= EastStatusRegPortxDN;
+ -- EastCtrlRegPortxDP <= EastCtrlRegPortxDN;
+ -- EastWrDataRegPortxDP <= EastWrDataRegPortxDN;
+ -- -- South
+ -- SouthStatusRegPortxDP <= SouthStatusRegPortxDN;
+ -- SouthCtrlRegPortxDP <= SouthCtrlRegPortxDN;
+ -- SouthWrDataRegPortxDP <= SouthWrDataRegPortxDN;
+ -- -- West
+ -- WestStatusRegPortxDP <= WestStatusRegPortxDN;
+ -- WestCtrlRegPortxDP <= WestCtrlRegPortxDN;
+ -- WestWrDataRegPortxDP <= WestWrDataRegPortxDN;
+ -- end if;
+ -- end process RegBankxP;
+
+ -- end block RegBankxB;
+
+ -- TxFifoxB : block is
+ -- begin -- block TxFifoxB
+
+ -- NorthWrDataxAS : NorthNativeSlavexD.DataxD <= NorthWrDataRegPortxDP;
+ -- EastWrDataxAS : EastNativeSlavexD.DataxD <= EastWrDataRegPortxDP;
+ -- SouthWrDataxAS : SouthNativeSlavexD.DataxD <= SouthWrDataRegPortxDN;
+ -- WestWrDataRegxAS : WestNativeSlavexD.DataxD <= WestWrDataRegPortxDN;
+ -- NorthWrEnxAS : NorthNativeSlavexD.WrEnxS <= NorthCtrlRegPortxDP(0);
+ -- EastWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
+ -- SouthWrEnxAS : SouthNativeSlavexD.WrEnxS <= SouthCtrlRegPortxDP(0);
+ -- WestWrEnxAS : EastNativeSlavexD.WrEnxS <= EastCtrlRegPortxDP(0);
+ -- NorthStatusRegPortxAS : NorthStatusRegPortxDN <= (0 => NorthNativeMasterxD.FullxS,
+ -- 1 => NorthNativeMasterxD.EmptyxS,
+ -- 2 => NorthNativeMasterxD.AlmostFullxS,
+ -- 3 => NorthNativeMasterxD.AlmostEmptyxS,
+ -- 4 => NorthNativeMasterxD.WrRstBusyxS,
+ -- 5 => NorthNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+ -- EastStatusRegPortxAS : EastStatusRegPortxDN <= (0 => EastNativeMasterxD.FullxS,
+ -- 1 => EastNativeMasterxD.EmptyxS,
+ -- 2 => EastNativeMasterxD.AlmostFullxS,
+ -- 3 => EastNativeMasterxD.AlmostEmptyxS,
+ -- 4 => EastNativeMasterxD.WrRstBusyxS,
+ -- 5 => EastNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+ -- SouthStatusRegPortxAS : SouthStatusRegPortxDN <= (0 => SouthNativeMasterxD.FullxS,
+ -- 1 => SouthNativeMasterxD.EmptyxS,
+ -- 2 => SouthNativeMasterxD.AlmostFullxS,
+ -- 3 => SouthNativeMasterxD.AlmostEmptyxS,
+ -- 4 => SouthNativeMasterxD.WrRstBusyxS,
+ -- 5 => SouthNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+ -- WestStatusRegPortxAS : WestStatusRegPortxDN <= (0 => WestNativeMasterxD.FullxS,
+ -- 1 => WestNativeMasterxD.EmptyxS,
+ -- 2 => WestNativeMasterxD.AlmostFullxS,
+ -- 3 => WestNativeMasterxD.AlmostEmptyxS,
+ -- 4 => WestNativeMasterxD.WrRstBusyxS,
+ -- 5 => WestNativeMasterxD.RdRstBusyxS,
+ -- others => '0');
+
+ -- UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
+ -- AuroraClkMasterxC.UserClkxC) is
+ -- begin -- process UpdateRegxP
+ -- if not AuroraClkMasterxC.PllNotLockedxS then
+ -- NorthStatusSendWordxDP <= E_IDLE;
+ -- EastStatusSendWordxDP <= E_IDLE;
+ -- SouthStatusSendWordxDP <= E_IDLE;
+ -- WestStatusSendWordxDP <= E_IDLE;
+ -- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
+ -- NorthStatusSendWordxDP <= NorthStatusSendWordxDN;
+ -- EastStatusSendWordxDP <= EastStatusSendWordxDN;
+ -- SouthStatusSendWordxDP <= SouthStatusSendWordxDN;
+ -- WestStatusSendWordxDP <= WestStatusSendWordxDN;
+ -- end if;
+ -- end process UpdateRegxP;
+
+ -- NorthSendWordxP : process (NorthNativeMasterxD.DataxD,
+ -- NorthNativeMasterxD.EmptyxS,
+ -- NorthStatusSendWordxDP,
+ -- NorthTXS2MxD.ReadyxS) is
+ -- begin -- process NorthSendWordxP
+ -- NorthTXM2SxD.DataxD <= (others => '0');
+ -- NorthTXM2SxD.KeepxD <= (others => '1');
+ -- NorthTXM2SxD.LastxS <= '0';
+ -- NorthTXM2SxD.ValidxS <= '0';
+ -- NorthNativeSlavexD.RdEnxS <= '0';
+ -- NorthStatusSendWordxDN <= NorthStatusSendWordxDP;
+
+ -- case NorthStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (NorthNativeMasterxD.EmptyxS = '0') and
+ -- (NorthTXS2MxD.ReadyxS = '1') then
+ -- NorthTXM2SxD.DataxD <= NorthNativeMasterxD.DataxD;
+ -- NorthTXM2SxD.LastxS <= '1';
+ -- NorthTXM2SxD.ValidxS <= '1';
+ -- NorthNativeSlavexD.RdEnxS <= '1';
+ -- NorthStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- NorthStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process NorthSendWordxP;
+
+ -- EastSendWordxP : process (EastNativeMasterxD.DataxD,
+ -- EastNativeMasterxD.EmptyxS,
+ -- EastStatusSendWordxDP,
+ -- EastTXS2MxD.ReadyxS) is
+ -- begin -- process EastSendWordxP
+ -- EastTXM2SxD.DataxD <= (others => '0');
+ -- EastTXM2SxD.KeepxD <= (others => '1');
+ -- EastTXM2SxD.LastxS <= '0';
+ -- EastTXM2SxD.ValidxS <= '0';
+ -- EastNativeSlavexD.RdEnxS <= '0';
+ -- EastStatusSendWordxDN <= EastStatusSendWordxDP;
+
+ -- case EastStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (EastNativeMasterxD.EmptyxS = '0') and
+ -- (EastTXS2MxD.ReadyxS = '1') then
+ -- EastTXM2SxD.DataxD <= EastNativeMasterxD.DataxD;
+ -- EastTXM2SxD.LastxS <= '1';
+ -- EastTXM2SxD.ValidxS <= '1';
+ -- EastNativeSlavexD.RdEnxS <= '1';
+ -- EastStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- EastStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process EastSendWordxP;
+
+ -- SouthSendWordxP : process (SouthNativeMasterxD.DataxD,
+ -- SouthNativeMasterxD.EmptyxS,
+ -- SouthStatusSendWordxDP,
+ -- SouthTXS2MxD.ReadyxS) is
+ -- begin -- process SouthSendWordxP
+ -- SouthTXM2SxD.DataxD <= (others => '0');
+ -- SouthTXM2SxD.KeepxD <= (others => '1');
+ -- SouthTXM2SxD.LastxS <= '0';
+ -- SouthTXM2SxD.ValidxS <= '0';
+ -- SouthNativeSlavexD.RdEnxS <= '0';
+ -- SouthStatusSendWordxDN <= SouthStatusSendWordxDP;
+
+ -- case SouthStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (SouthNativeMasterxD.EmptyxS = '0') and
+ -- (SouthTXS2MxD.ReadyxS = '1') then
+ -- SouthTXM2SxD.DataxD <= SouthNativeMasterxD.DataxD;
+ -- SouthTXM2SxD.LastxS <= '1';
+ -- SouthTXM2SxD.ValidxS <= '1';
+ -- SouthNativeSlavexD.RdEnxS <= '1';
+ -- SouthStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- SouthStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process SouthSendWordxP;
+
+ -- WestSendWordxP : process (WestNativeMasterxD.DataxD,
+ -- WestNativeMasterxD.EmptyxS,
+ -- WestStatusSendWordxDP,
+ -- WestTXS2MxD.ReadyxS) is
+ -- begin -- process WestSendWordxP
+ -- WestTXM2SxD.DataxD <= (others => '0');
+ -- WestTXM2SxD.KeepxD <= (others => '1');
+ -- WestTXM2SxD.LastxS <= '0';
+ -- WestTXM2SxD.ValidxS <= '0';
+ -- WestNativeSlavexD.RdEnxS <= '0';
+ -- WestStatusSendWordxDN <= WestStatusSendWordxDP;
+
+ -- case WestStatusSendWordxDP is
+ -- when E_IDLE =>
+
+ -- if (WestNativeMasterxD.EmptyxS = '0') and
+ -- (WestTXS2MxD.ReadyxS = '1') then
+ -- WestTXM2SxD.DataxD <= WestNativeMasterxD.DataxD;
+ -- WestTXM2SxD.LastxS <= '1';
+ -- WestTXM2SxD.ValidxS <= '1';
+ -- WestNativeSlavexD.RdEnxS <= '1';
+ -- WestStatusSendWordxDN <= E_SEND;
+ -- end if;
+
+ -- when E_SEND =>
+ -- WestStatusSendWordxDN <= E_IDLE;
+
+ -- when others => null;
+ -- end case;
+ -- end process WestSendWordxP;
+
+ -- NorthFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => NorthNativeSlavexD,
+ -- NativeMasterxDO => NorthNativeMasterxD);
+
+ -- EastFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => EastNativeSlavexD,
+ -- NativeMasterxDO => EastNativeMasterxD);
+
+ -- SouthFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => SouthNativeSlavexD,
+ -- NativeMasterxDO => SouthNativeMasterxD);
+
+ -- WestFifoxI : entity work.scalp_packet_fifo_wrapper
+ -- port map (
+ -- RdClkxCI => AuroraClkMasterxC.UserClkxC,
+ -- WrClkxCI => PSSysClkxC,
+ -- ResetxRI => PSSysResetxR,
+ -- NativeSlavexDI => WestNativeSlavexD,
+ -- NativeMasterxDO => WestNativeMasterxD);
+
+ -- end block TxFifoxB;
+
+ -- end block ZynqRegBankxB;
DebugxB : block is
-
- signal CntRstxR : std_ulogic := '0';
- signal ClkEnxS : std_ulogic := '0';
- signal DataCounterxD : std_ulogic_vector(31 downto 0) := (others => '0');
-
begin -- block DebugxB
- -- ClkEnxAS : ClkEnxS <= not AuroraClkMasterxC.PllNotLockedxS;
- -- -- North
- -- NorthTXDataxAS : NorthTXM2SxD.DataxD <= DataCounterxD;
- -- NorthTXKeepxAS : NorthTXM2SxD.KeepxD <= (others => '1');
- -- NorthTXLastxAS : NorthTXM2SxD.LastxS <= '0';
- -- NorthTXValidxAS : NorthTXM2SxD.ValidxS <= not CntRstxR;
- -- -- East
- -- EastTXDataxAS : EastTXM2SxD.DataxD <= DataCounterxD;
- -- EastTXKeepxAS : EastTXM2SxD.KeepxD <= (others => '1');
- -- EastTXLastxAS : EastTXM2SxD.LastxS <= '0';
- -- EastTXValidxAS : EastTXM2SxD.ValidxS <= not CntRstxR;
- -- -- South
- -- SouthTXDataxAS : SouthTXM2SxD.DataxD <= DataCounterxD;
- -- SouthTXKeepxAS : SouthTXM2SxD.KeepxD <= (others => '1');
- -- SouthTXLastxAS : SouthTXM2SxD.LastxS <= '0';
- -- SouthTXValidxAS : SouthTXM2SxD.ValidxS <= not CntRstxR;
- -- -- West
- -- WestTXDataxAS : WestTXM2SxD.DataxD <= DataCounterxD;
- -- WestTXKeepxAS : WestTXM2SxD.KeepxD <= (others => '1');
- -- WestTXLastxAS : WestTXM2SxD.LastxS <= '0';
- -- WestTXValidxAS : WestTXM2SxD.ValidxS <= not CntRstxR;
-
- -- DataCounterxI : entity work.data_counter
- -- port map (
- -- clk => AuroraClkMasterxC.UserClkxC,
- -- ce => ClkEnxS,
- -- sclr => CntRstxR,
- -- q => DataCounterxD);
+ ClkEnxAS : ClkEnxS <= not AuroraClkMasterxC.PllNotLockedxS;
+ -- North
+ NorthTXDataxAS : NorthTXM2SxD.DataxD <= DataCounterxD;
+ NorthTXKeepxAS : NorthTXM2SxD.KeepxD <= (others => '1');
+ NorthTXLastxAS : NorthTXM2SxD.LastxS <= '0';
+ NorthTXValidxAS : NorthTXM2SxD.ValidxS <= not DebugCounterResetxR;
+ -- East
+ EastTXDataxAS : EastTXM2SxD.DataxD <= DataCounterxD;
+ EastTXKeepxAS : EastTXM2SxD.KeepxD <= (others => '1');
+ EastTXLastxAS : EastTXM2SxD.LastxS <= '0';
+ EastTXValidxAS : EastTXM2SxD.ValidxS <= not DebugCounterResetxR;
+ -- South
+ SouthTXDataxAS : SouthTXM2SxD.DataxD <= DataCounterxD;
+ SouthTXKeepxAS : SouthTXM2SxD.KeepxD <= (others => '1');
+ SouthTXLastxAS : SouthTXM2SxD.LastxS <= '0';
+ SouthTXValidxAS : SouthTXM2SxD.ValidxS <= not DebugCounterResetxR;
+ -- West
+ WestTXDataxAS : WestTXM2SxD.DataxD <= DataCounterxD;
+ WestTXKeepxAS : WestTXM2SxD.KeepxD <= (others => '1');
+ WestTXLastxAS : WestTXM2SxD.LastxS <= '0';
+ WestTXValidxAS : WestTXM2SxD.ValidxS <= not DebugCounterResetxR;
+
+ DataCounterxI : entity work.data_counter
+ port map (
+ clk => AuroraClkMasterxC.UserClkxC,
+ ce => ClkEnxS,
+ sclr => DebugCounterResetxR,
+ q => DataCounterxD);
- VioAxiCntCtrlxI : entity work.vio_axi_cnt_ctrl
+ VioUserResetsxI : entity work.vio_user_resets
port map (
clk => AuroraClkMasterxC.UserClkxC,
- -- North
- probe_in0 => NorthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- probe_in1(0) => NorthRXfromPhyTXfromFifoM2SxD.ValidxS,
- probe_in2(0) => NorthTXS2MxD.ReadyxS,
- -- East
- probe_in3 => EastRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- probe_in4(0) => EastRXfromPhyTXfromFifoM2SxD.ValidxS,
- probe_in5(0) => EastTXS2MxD.ReadyxS,
- -- South
- probe_in6 => SouthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- probe_in7(0) => SouthRXfromPhyTXfromFifoM2SxD.ValidxS,
- probe_in8(0) => SouthTXS2MxD.ReadyxS,
- -- West
- probe_in9 => WestRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
- probe_in10(0) => WestRXfromPhyTXfromFifoM2SxD.ValidxS,
- probe_in11(0) => WestTXS2MxD.ReadyxS,
- probe_out0(0) => CntRstxR);
+ probe_out0(0) => DebugCounterResetxR,
+ probe_out1(0) => DebugRXFifoResetxR,
+ probe_out2(0) => DebugBackPressureResetxR,
+ probe_out3 => open,
+ probe_out4 => open);
+
+ -- VioAxiCntCtrlxI : entity work.vio_axi_cnt_ctrl
+ -- port map (
+ -- clk => AuroraClkMasterxC.UserClkxC,
+ -- -- North
+ -- probe_in0 => NorthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ -- probe_in1(0) => NorthRXfromPhyTXfromFifoM2SxD.ValidxS,
+ -- probe_in2(0) => '0', --NorthTXS2MxD.ReadyxS,
+ -- -- East
+ -- probe_in3 => EastRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ -- probe_in4(0) => EastRXfromPhyTXfromFifoM2SxD.ValidxS,
+ -- probe_in5(0) => '0', --EastTXS2MxD.ReadyxS,
+ -- -- South
+ -- probe_in6 => SouthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ -- probe_in7(0) => SouthRXfromPhyTXfromFifoM2SxD.ValidxS,
+ -- probe_in8(0) => '0', --SouthTXS2MxD.ReadyxS,
+ -- -- West
+ -- probe_in9 => WestRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
+ -- probe_in10(0) => WestRXfromPhyTXfromFifoM2SxD.ValidxS,
+ -- probe_in11(0) => '0', --WestTXS2MxD.ReadyxS,
+ -- probe_out0(0) => open); --CntRstxR);
VioStatusxI : entity work.vio_status
port map (