diff --git a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
index c01cf62344cb9e09de1c6f47c7815e402fa2a72d..062069fc27fa1782ec858918d6c28a0df4365e52 100644
--- a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
+++ b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
@@ -429,16 +429,16 @@ begin
             Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
 
             -- Camera I2C SDA tri-state buffer
-            LVDS2V5Bottom5PxSIO <= I2c1SdaOxS when I2c1SdaTxS='1' else 'Z';
+            LVDS2V5Bottom5PxSIO <= I2c1SdaOxS when I2c1SdaTxS='0' else 'Z';
             I2c1SdaIxS  <= LVDS2V5Bottom5PxSIO;
             -- Camera I2C SCL tri-state buffer
-            LVDS2V5Bottom5NxSIO <= I2c1SclOxS when I2c1SclTxS='1' else 'Z';
+            LVDS2V5Bottom5NxSIO <= I2c1SclOxS when I2c1SclTxS='0' else 'Z';
             I2c1SclIxS  <= LVDS2V5Bottom5NxSIO;
             -- Camera PWUP tri-state buffer (GPIO0_4)
-            LVDS2V5Bottom6NxSIO <=  GPIO0OxD(4) when  GPIO0TxD(4)='1' else 'Z';
+            LVDS2V5Bottom6NxSIO <=  GPIO0OxD(4) when  GPIO0TxD(4)='0' else 'Z';
             GPIO0IxD(4)  <= LVDS2V5Bottom6NxSIO;
             -- Camera GPIO tri-state buffer (GPIO0_5)
-            LVDS2V5Bottom6PxSIO <=  GPIO0OxD(5) when  GPIO0TxD(5)='1' else 'Z';
+            LVDS2V5Bottom6PxSIO <=  GPIO0OxD(5) when  GPIO0TxD(5)='0' else 'Z';
             GPIO0IxD(5)  <= LVDS2V5Bottom6PxSIO;
             -- MIPI signal assignement
 --            MipiPhyClockHsNxAS : MipiPhyClockHsNxC   <= Clk2V5BottomNxCI;
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
index b9838174405ce06759bdc2cd4e4f931fd38ca6b9..6a972d434ec2e2af0071fc0554db5d0eaa998639 100644
--- a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
@@ -706,9 +706,11 @@ proc create_root_design { parentCell } {
   set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
   set_property -dict [ list \
    CONFIG.C_MON_TYPE {INTERFACE} \
-   CONFIG.C_NUM_MONITOR_SLOTS {1} \
+   CONFIG.C_NUM_MONITOR_SLOTS {2} \
    CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:gpio_rtl:1.0} \
    CONFIG.C_SLOT_0_TYPE {0} \
+   CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:iic_rtl:1.0} \
+   CONFIG.C_SLOT_1_TYPE {0} \
  ] $system_ila_0
 
   # Create instance: util_vector_logic_0, and set properties
@@ -741,6 +743,8 @@ proc create_root_design { parentCell } {
 connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_GPIO_0] [get_bd_intf_ports GPIO_0] [get_bd_intf_pins system_ila_0/SLOT_0_GPIO]
   set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets processing_system7_0_GPIO_0]
   connect_bd_intf_net -intf_net processing_system7_0_IIC_1 [get_bd_intf_ports I2C1] [get_bd_intf_pins processing_system7_0/IIC_1]
+connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get_bd_intf_ports I2C1] [get_bd_intf_pins system_ila_0/SLOT_1_IIC]
+  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets processing_system7_0_IIC_1]
   connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]