diff --git a/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
index 1e482d7947aa0eab4c9d29e78c3e45bf26b140fa..676ce74db63e4fc82153b92822fb8931c4c948ba 100644
--- a/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
+++ b/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
@@ -258,3 +258,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
diff --git a/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/timing_constraints.xdc
index e5c8cd817933767c76d8e770f2ade2b50b54e629..02494d02b0f1e4dcae2f8f725844e270f3fa1a14 100644
--- a/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_fast_router_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -38,3 +38,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+
diff --git a/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd b/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
index 020fc38ffa0ac43c405925badb5793adf34d19d5..1d9fdbad4c968f7333743588f5d2b5176362b8f9 100644
--- a/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
+++ b/designs/vivado/scalp_fast_router_firmware/2020.2/src/hdl/scalp_fast_router_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_fast_router_firmware
--
--- Last update: 2021-09-20
+-- Last update: 2021-09-29
--
---------------------------------------------------------------------------------
@@ -44,7 +44,8 @@ entity scalp_fast_router_firmware is
C_RX_FIFO_MODE : boolean := true;
C_RX_FIFO_CTRL_TLAST : boolean := true;
C_SCALP_NUMBER_OF_INTERFACE : integer range 0 to 255 := 7;
- C_SCALP_SCHEDULER_STRATEGY : string := "RR");
+ C_SCALP_SCHEDULER_STRATEGY : string := "RR";
+ C_SCALP_DMA_LOOPBACK : boolean := false);
port (
-----------------------------------------------------------------------
@@ -276,7 +277,6 @@ entity scalp_fast_router_firmware is
end scalp_fast_router_firmware;
-
architecture arch of scalp_fast_router_firmware is
-- Constantes
@@ -442,117 +442,20 @@ architecture arch of scalp_fast_router_firmware is
signal TXAxism2sVectorxD : t_axi4m2s_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_M2S);
signal TXAxiss2mVectorxD : t_axi4s2m_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_NO_AXI4_S2M);
signal QoSVectorxD : t_scalp_qos_vector((C_SCALP_NUMBER_OF_INTERFACE - 1) downto 0) := (others => C_SCALP_NO_QOS);
- -- signal ScalpRouterReadyxD : t_scalp_router_ready := C_NO_SCALP_ROUTER_READY;
-- Scalp Axi Lite interface and IRQ
- signal ScalpPacketWriteDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal ScalpPacketReadDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal ScalpPacketCtrlxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal ScalpPacketStatusxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RXRdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RXWrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal TXRdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal TXWrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal LocNetAddrVectxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal TXFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
- signal TXFifoRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal TXFifoRXS2MxS : t_axi4s2m := C_NO_AXI4_S2M;
- signal RXFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
- signal RXFifoTXS2MxS : t_axi4s2m := C_NO_AXI4_S2M;
- signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Zynq Reg Bank
- -- type t_status_send_word is (E_IDLE, E_SEND);
-
- type t_tx_fifo_wr_data_states is (E_WR_IDLE, E_WR_H0, E_WR_H1, E_WR_H2, E_WR_PLD, E_WR_NEXT);
- type t_rx_fifo_rd_data_states is (E_RD_IDLE, E_RD_WORD, E_RD_NEXT);
-
- constant C_WR_VALID : integer range 0 to 255 := 0;
- constant C_WR_LAST : integer range 0 to 255 := 1;
- constant C_WR_READY : integer range 0 to 255 := 2;
- constant C_WR_NEXT : integer range 0 to 255 := 3;
- constant C_RESET_ALL_FIFO : integer range 0 to 255 := 4;
- constant C_WR_H0 : integer range 0 to 255 := 5;
- constant C_WR_H1 : integer range 0 to 255 := 6;
- constant C_WR_H2 : integer range 0 to 255 := 7;
- constant C_WR_PLD : integer range 0 to 255 := 8;
- constant C_WR_NEW_PACKET : integer range 0 to 255 := 9;
- constant C_RD_NEXT : integer range 0 to 255 := 10;
- constant C_RD_NEW_PACKET : integer range 0 to 255 := 11;
- --
- constant C_RD_VALID : integer range 0 to 255 := 0;
- constant C_RD_LAST : integer range 0 to 255 := 1;
- constant C_TX_PROG_FULL : integer range 0 to 255 := 2;
- constant C_RX_PROG_FULL : integer range 0 to 255 := 3;
- constant C_RD_WAIT_NEXT : integer range 0 to 255 := 4;
-
- signal TXFifoWrDataStatexD : t_tx_fifo_wr_data_states := E_WR_IDLE;
- signal TXFifoWrDataStateNextxD : t_tx_fifo_wr_data_states := E_WR_IDLE;
- signal RXFifoRdDataStatexD : t_rx_fifo_rd_data_states := E_RD_IDLE;
- signal RXFifoRdDataStateNextxD : t_rx_fifo_rd_data_states := E_RD_IDLE;
-
- -- signal NorthStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal NorthStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- signal EastStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal EastStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- signal SouthStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal SouthStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- signal WestStatusSendWordxDN : t_status_send_word := E_IDLE;
- -- signal WestStatusSendWordxDP : t_status_send_word := E_IDLE;
- -- --
- -- signal NorthNativeSlavexD : t_native_fifo_slave;
- -- signal NorthNativeMasterxD : t_native_fifo_master;
- -- signal EastNativeSlavexD : t_native_fifo_slave;
- -- signal EastNativeMasterxD : t_native_fifo_master;
- -- signal SouthNativeSlavexD : t_native_fifo_slave;
- -- signal SouthNativeMasterxD : t_native_fifo_master;
- -- signal WestNativeSlavexD : t_native_fifo_slave;
- -- signal WestNativeMasterxD : t_native_fifo_master;
+ signal LocalNetAddrxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RGBLed0xD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RGBLed1xD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal DMARXm2sxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal DMARXs2mxD : t_axi4s2m := C_NO_AXI4_S2M;
+ signal DMATXm2sxD : t_axi4m2s := C_NO_AXI4_M2S;
+ signal DMATXs2mxD : t_axi4s2m := C_NO_AXI4_S2M;
--
- -- signal InterruptRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal InterruptRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- North
- -- signal NorthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal NorthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal NorthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- East
- -- signal EastStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal EastWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- South
- -- signal SouthStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal SouthWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- West
- -- signal WestStatusRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestStatusRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestCtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestCtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestWrDataRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- signal WestWrDataRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- -- Debug
- -- signal CntRstxR : std_ulogic := '0';
- signal ClkEnxS : std_ulogic := '0';
- signal NorthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal NorthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- signal EastDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal EastDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- signal SouthDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal SouthDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- signal WestDataCounterxDN : unsigned(31 downto 0) := (others => '0');
- signal WestDataCounterxDP : unsigned(31 downto 0) := (others => '0');
- --
- signal DebugCounterResetxR : t_if_common_reset := C_NO_IF_COMMON_RESET;
- signal DebugRXFifoResetxR : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
- signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
+ signal ScalpRouterResetxRNA : std_ulogic := '0';
+ signal DebugCounterResetxR : t_if_common_reset := C_NO_IF_COMMON_RESET;
+ signal DebugRXFifoResetxR : t_rx_fifo_reset := C_NO_RX_FIFO_RESET;
+ signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-- Attributes
attribute mark_debug : string;
@@ -564,6 +467,8 @@ architecture arch of scalp_fast_router_firmware is
attribute keep of AuroraClkSlavexC : signal is "true";
attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
+ -- attribute mark_debug of LocNetAddrxD : signal is "true";
+ -- attribute keep of LocNetAddrxD : signal is "true";
begin
@@ -606,7 +511,33 @@ begin
-- MIO
FIXED_IO_mio => MIOxDIO,
UserClkxCI => AuroraClkMasterxC.UserClkxC,
- UserResetxRANI => ScalpRouterResetxRNA);
+ UserResetxRANI => ScalpRouterResetxRNA,
+ -- Scalp Fast Router Registers
+ LocalNetAddrxDO => LocalNetAddrxD,
+ RGBLed0xDO => RGBLed0xD,
+ RGBLed1xDO => RGBLed1xD,
+ -- RX
+ DMARXm2sxDI => DMARXm2sxD,
+ DMARXs2mxDO => DMARXs2mxD,
+ -- TX
+ DMATXm2sxDO => DMATXm2sxD,
+ DMATXs2mxDI => DMATXs2mxD,
+ -- Debug Phy
+ -- West Phy
+ WestRXM2SxDI => WestRXM2SxD,
+ WestRXS2MxDI => WestRXS2MxD,
+ WestTXM2SxDI => WestTXM2SxD,
+ WestTXS2MxDI => WestTXS2MxD,
+ -- East Phy
+ EastRXM2SxDI => EastRXM2SxD,
+ EastRXS2MxDI => EastRXS2MxD,
+ EastTXM2SxDI => EastTXM2SxD,
+ EastTXS2MxDI => EastTXS2MxD,
+ -- Local NoC
+ LocalRXM2SxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
+ LocalRXS2MxDI => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
+ LocalTXM2SxDI => RXAxism2sVectorxD(C_LOCAL_IF_ID),
+ LocalTXS2MxDI => RXAxiss2mVectorxD(C_LOCAL_IF_ID));
end block ProcessingSystemxB;
@@ -1008,9 +939,9 @@ begin
-- Local Router Net Addr
-- LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_210;
- LocNetAddrXxAS : LocNetAddrxD.XxD <= to_integer(unsigned(LocNetAddrVectxD(7 downto 0)));
- LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocNetAddrVectxD(15 downto 8)));
- LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocNetAddrVectxD(23 downto 16)));
+ LocNetAddrXxAS : LocNetAddrxD.XxD <= to_integer(unsigned(LocalNetAddrxD(7 downto 0)));
+ LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocalNetAddrxD(15 downto 8)));
+ LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocalNetAddrxD(23 downto 16)));
-- TX Side
NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
@@ -1032,6 +963,27 @@ begin
SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
+ ScalpDMALoopBackxG : if C_SCALP_DMA_LOOPBACK = true generate
+
+ DMA2DMAm2sxAS : DMARXm2sxD <= DMATXm2sxD;
+ DMA2DMAs2mxAS : DMATXs2mxD <= DMARXs2mxD;
+
+ elsif C_SCALP_DMA_LOOPBACK = false generate
+
+ -- NoC local interface
+ -- RX Side
+ DMA2NoCm2sDataxAS : RXAxism2sVectorxD(C_LOCAL_IF_ID).DataxD <= change_endian_ul(DMATXm2sxD.DataxD);
+ DMA2NoCm2sValidxAS : RXAxism2sVectorxD(C_LOCAL_IF_ID).ValidxS <= DMATXm2sxD.ValidxS;
+ DMA2NoCm2sLastxAS : RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS <= DMATXm2sxD.LastxS;
+ DMA2NoCs2mxAS : DMATXs2mxD <= RXAxiss2mVectorxD(C_LOCAL_IF_ID);
+ -- TX Side
+ NoC2DMAm2sDataxAS : DMARXm2sxD.DataxD <= change_endian_ul(TXAxism2sVectorxD(C_LOCAL_IF_ID).DataxD);
+ NoC2DMAm2sValidxAS : DMARXm2sxD.ValidxS <= TXAxism2sVectorxD(C_LOCAL_IF_ID).ValidxS;
+ NoC2DMAm2sLastxAS : DMARXm2sxD.LastxS <= TXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS;
+ NoC2DMAs2mxAS : TXAxiss2mVectorxD(C_LOCAL_IF_ID) <= DMARXs2mxD;
+
+ end generate ScalpDMALoopBackxG;
+
ScalpRouterxI : entity work.scalp_router
generic map (
C_SCALP_NUMBER_OF_INTERFACE => C_SCALP_NUMBER_OF_INTERFACE,
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/component.xml b/ips/hw/scalp_aurora_phy_rx_fifo/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..63533f076f9eecae3f2bc59dcc0080f4275c381d
--- /dev/null
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/component.xml
@@ -0,0 +1,1891 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>hepia.hesge.ch</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>scalp_aurora_phy_rx_fifo_ip_wrapper</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>RXClkxCI</spirit:name>
+ <spirit:displayName>RXClkxCI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>RXClkxCI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RXCLKXCI.FREQ_HZ"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RXCLKXCI.ASSOCIATED_BUSIF">NorthRXM2SxDI:EastRXM2SxDI:SouthRXM2SxDI:WestRXM2SxDI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RXCLKXCI.ASSOCIATED_RESET">NorthRXRstxRANI:EastRXRstxRANI:SouthRXRstxRANI:WestRXRstxRANI</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>TXClkxCI</spirit:name>
+ <spirit:displayName>TXClkxCI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>TXClkxCI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.TXCLKXCI.FREQ_HZ"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.TXCLKXCI.ASSOCIATED_BUSIF">NorthTXM2SxDO:EastTXM2SxDO:SouthTXM2SxDO:WestTXM2SxDO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.TXCLKXCI.ASSOCIATED_RESET">NorthFifoStatusWrDataCntxDO:NorthFifoStatusRdDataCntxDO:NorthFifoStatusProgEmptyxSO:NorthFifoStatusProgFullxSO:EastFifoStatusWrDataCntxDO:EastFifoStatusRdDataCntxDO:EastFifoStatusProgEmptyxSO:EastFifoStatusProgFullxSO:SouthFifoStatusWrDataCntxDO:SouthFifoStatusRdDataCntxDO:SouthFifoStatusProgEmptyxSO:SouthFifoStatusProgFullxSO:WestFifoStatusWrDataCntxDO:WestFifoStatusProgEmptyxSO:WestFifoStatusProgFullxSO</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>NorthRXRstxRANI</spirit:name>
+ <spirit:displayName>NorthRXRstxRANI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>NorthRXRstxRANI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.NORTHRXRSTXRANI.NUM_READ_OUTSTANDING"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.NORTHRXRSTXRANI.NUM_WRITE_OUTSTANDING"/>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
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+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4f49a9a6_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_aurora_phy_rx_fifo</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5b36310d_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_aurora_phy_rx_fifo</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1ec5a7f3_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_aurora_phy_rx_fifo</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5e821cb7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_aurora_phy_rx_fifo</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@76c448e7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_aurora_phy_rx_fifo</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="9930c364"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="69b7a08f"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="f896e31a"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="bd90c46a"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="c91937a3"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/axi4_pkg.vhd b/ips/hw/scalp_aurora_phy_rx_fifo/src/axi4_pkg.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..8eea268bbb882881c9d7da275dde0bcf48567310
--- /dev/null
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/axi4_pkg.vhd
@@ -0,0 +1,234 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: axi4_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: AXI4 format bus signals.
+--
+-- Last update: 2021-05-21
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package axi4_pkg is
+
+ constant C_AXI4_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_KEEP_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_UFC_RX_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_UFC_TX_DATA_SIZE : integer range 0 to 32 := 3;
+ constant C_AXI4_NFC_DATA_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_DEST_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_STRB_SIZE : integer range 0 to 32 := C_AXI4_KEEP_SIZE; -- Same as Keep
+ constant C_AXI4_USER_SIZE : integer range 0 to 32 := 32;
+
+ -- AXI4 Framing
+ -- Master to Slave
+ type t_axi4m2s is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_DATA_SIZE - 1));
+ KeepxD : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+ LastxS : std_ulogic;
+ ValidxS : std_ulogic;
+ -- Not Necessary
+ IdxS : std_ulogic;
+ DestxD : std_ulogic_vector(0 to (C_AXI4_DEST_SIZE - 1));
+ StrbxD : std_ulogic_vector(0 to (C_AXI4_STRB_SIZE - 1));
+ UserxD : std_ulogic_vector(0 to (C_AXI4_USER_SIZE - 1));
+ end record t_axi4m2s;
+
+ -- Slave to Master
+ type t_axi4s2m is record
+ ReadyxS : std_ulogic;
+ end record t_axi4s2m;
+
+ constant C_NO_AXI4_M2S : t_axi4m2s := (DataxD => (others => '0'),
+ KeepxD => (others => '0'),
+ LastxS => '0',
+ ValidxS => '0',
+ IdxS => '0',
+ DestxD => (others => '0'),
+ StrbxD => (others => '0'),
+ UserxD => (others => '0'));
+ constant C_NO_AXI4_S2M : t_axi4s2m := (ReadyxS => '0');
+ constant C_ON_AXI4_S2M : t_axi4s2m := (ReadyxS => '1');
+
+ type t_axi4_dual_clk is record
+ RXClkxC : std_ulogic;
+ TXClkxC : std_ulogic;
+ end record t_axi4_dual_clk;
+
+ constant C_NO_AXI4_DUAL_CLK : t_axi4_dual_clk := (RXClkxC => '0',
+ TXClkxC => '0');
+
+ type t_axi4_rst is record
+ RstxRAN : std_ulogic;
+ end record t_axi4_rst;
+
+ constant C_NO_AXI4_RST : t_axi4_rst := (RstxRAN => '1');
+
+ -- Non-Generic Vector of AXI4 Framing Bus
+ ---------------------------------------------------------------------------
+ -- constant C_SIM_VIVADO_VECTOR_SIZE : integer := 6;
+ -- type t_axi4m2s_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4m2s;
+ -- type t_axi4s2m_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4s2m;
+
+ -- constant C_NO_SIM_AXISM2S_VECTOR : t_axi4m2s_vector := (others => C_NO_AXI4_M2S);
+ -- constant C_NO_SIM_AXISS2M_VECTOR : t_axi4s2m_vector := (others => C_NO_AXI4_S2M);
+ -- -- Generic Vector of AXI4 Framing Bus Vector
+ -- type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+ -- type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+ ---------------------------------------------------------------------------
+ -- Generic Vector of AXI4 Framing Bus
+ type t_axi4m2s_vector is array (natural range <>) of t_axi4m2s;
+ type t_axi4s2m_vector is array (natural range <>) of t_axi4s2m;
+
+ -- Generic Vector of AXI4 Framing Bus Vector
+ type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+ type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+
+ -- AXI4 UFC
+ -- Master to Slave RX
+ type t_axi4ufcm2s_rx is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_RX_DATA_SIZE - 1));
+ KeepxD : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+ LastxS : std_ulogic;
+ ValidxS : std_ulogic;
+ end record t_axi4ufcm2s_rx;
+
+ -- Master to Slave TX
+ type t_axi4ufcm2s_tx is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_TX_DATA_SIZE - 1));
+ ValidxS : std_ulogic;
+ end record t_axi4ufcm2s_tx;
+
+ -- Slave to Master
+ type t_axi4ufcs2m_tx is record
+ ReadyxS : std_ulogic;
+ end record t_axi4ufcs2m_tx;
+
+ constant C_NO_AXI4_UFC_M2S_RX : t_axi4ufcm2s_rx := (DataxD => (others => '0'),
+ KeepxD => (others => '0'),
+ LastxS => '0',
+ ValidxS => '0');
+ constant C_NO_AXI4_UFC_M2S_TX : t_axi4ufcm2s_tx := (DataxD => (others => '0'),
+ ValidxS => '0');
+ constant C_NO_AXI4_UFC_S2M_TX : t_axi4ufcs2m_tx := (ReadyxS => '0');
+
+ -- AXI4 NFC
+ -- Master to Slave
+ type t_axi4nfcm2s is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_NFC_DATA_SIZE - 1));
+ ValidxS : std_ulogic;
+ end record t_axi4nfcm2s;
+
+ -- Slave to Master
+ type t_axi4nfcs2m is record
+ ReadyxS : std_ulogic;
+ end record t_axi4nfcs2m;
+
+ constant C_NO_AXI4_NFC_M2S : t_axi4nfcm2s := (DataxD => (others => '0'),
+ ValidxS => '0');
+ constant C_NO_AXI4_NFC_S2M : t_axi4nfcs2m := (ReadyxS => '0');
+
+ -- NFC Codes
+ constant C_NFC_XON : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ constant C_NFC_XOFF : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '1');
+
+ type t_nfc_states is (C_NFC_IDLE, C_NFC_IS_XON, C_NFC_IS_XOFF, C_NFC_SEND_XON, C_NFC_SEND_XOFF);
+
+ -- Axis Fifo Status
+ type t_axi4fifo_status is record
+ WrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ ProgEmptyxS : std_ulogic;
+ ProgFullxS : std_ulogic;
+ end record t_axi4fifo_status;
+
+ constant C_NO_AXI4_FIFO_STATUS : t_axi4fifo_status := (WrDataCntxD => (others => '0'),
+ RdDataCntxD => (others => '0'),
+ ProgEmptyxS => '0',
+ ProgFullxS => '0');
+
+ -- Axis Fifo Error Counter
+ type t_axi4fifo_error is record
+ NorthCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ EastCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ SouthCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ WestCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ end record t_axi4fifo_error;
+
+ constant C_NO_AXI4_FIFO_ERROR : t_axi4fifo_error := (NorthCounterxD => (others => '0'),
+ EastCounterxD => (others => '0'),
+ SouthCounterxD => (others => '0'),
+ WestCounterxD => (others => '0'));
+
+ -- Native Fifo for Scalp packets
+ type t_native_fifo_slave is record
+ DataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ WrEnxS : std_ulogic;
+ RdEnxS : std_ulogic;
+ end record t_native_fifo_slave;
+
+ constant C_NO_NATIVE_FIFO_SLAVE : t_native_fifo_slave := (DataxD => (others => '0'),
+ WrEnxS => '0',
+ RdEnxS => '0');
+
+ type t_native_fifo_master is record
+ DataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ FullxS : std_ulogic;
+ EmptyxS : std_ulogic;
+ AlmostFullxS : std_ulogic;
+ AlmostEmptyxS : std_ulogic;
+ WrRstBusyxS : std_ulogic;
+ RdRstBusyxS : std_ulogic;
+ end record t_native_fifo_master;
+
+ constant C_NO_NATIVE_FIFO_MASTER : t_native_fifo_master := (DataxD => (others => '0'),
+ FullxS => '0',
+ EmptyxS => '0',
+ AlmostFullxS => '0',
+ AlmostEmptyxS => '0',
+ WrRstBusyxS => '0',
+ RdRstBusyxS => '0');
+
+ -- AXI4 Functions
+ -- OR reduce from t_axi4s2m_vector
+ function or_reduce_t_axi4s2m_vector (
+ signal VectorxD : t_axi4s2m_vector)
+ return t_axi4s2m;
+
+end package axi4_pkg;
+
+package body axi4_pkg is
+
+ -- AXI4 Functions
+ -- OR reduce from t_axi4s2m_vector
+ function or_reduce_t_axi4s2m_vector (
+ signal VectorxD : t_axi4s2m_vector)
+ return t_axi4s2m is
+ variable ResultxS : t_axi4s2m := C_NO_AXI4_S2M;
+ begin -- function or_reduce_t_axi4s2m_vector
+ for i in VectorxD'range loop
+ ResultxS.ReadyxS := ResultxS.ReadyxS or VectorxD(i).ReadyxS;
+ end loop; -- i
+
+ return ResultxS;
+ end function or_reduce_t_axi4s2m_vector;
+
+end package body axi4_pkg;
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
index 0f2abc9514a2595a5da1bafb20b927c215954c1a..b6e7521e6cf84f2bb148c9a86a51989ed9b1c9ad 100644
--- a/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_aurora_phy_rx_fifo
--
--- Last update: 2021-09-13
+-- Last update: 2021-09-22
--
---------------------------------------------------------------------------------
@@ -32,7 +32,7 @@ entity scalp_aurora_phy_rx_fifo is
C_CTRL_TLAST : boolean := true);
port (
- -- Clocks and Reset
+ -- Clocks and Resets
RXClkxCI : in std_ulogic;
TXClkxCI : in std_ulogic;
RXRstxRANI : in t_rx_fifo_reset;
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo_ip_wrapper.vhd b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo_ip_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..38081c27cf22404b7e6cdaff30de313bafb8d341
--- /dev/null
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo_ip_wrapper.vhd
@@ -0,0 +1,166 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_aurora_phy_rx_fifo - arch
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_aurora_phy_rx_fifo
+--
+-- Last update: 2021-09-22
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+use work.aurora_status_pkg.all;
+
+entity scalp_aurora_phy_rx_fifo_ip_wrapper is
+
+ generic (
+ C_CTRL_TLAST : boolean := true);
+
+ port (
+ -- Clocks and Resets
+ RXClkxCI : in std_ulogic;
+ TXClkxCI : in std_ulogic;
+ --
+ NorthRXRstxRANI : in std_ulogic;
+ EastRXRstxRANI : in std_ulogic;
+ SouthRXRstxRANI : in std_ulogic;
+ WestRXRstxRANI : in std_ulogic;
+ -- AXIS Interfaces and status
+ -- North
+ NorthRXM2SDataxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ NorthRXM2SLastxSI : in std_ulogic;
+ NorthRXM2SValidxSI : in std_ulogic;
+ NorthRXS2MReadyxSO : out std_ulogic;
+ NorthTXM2SDataxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ NorthTXM2SLastxSO : out std_ulogic;
+ NorthTXM2SValidxSO : out std_ulogic;
+ NorthTXS2MReadyxSI : in std_ulogic;
+ NorthFifoStatusWrDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ NorthFifoStatusRdDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ NorthFifoStatusProgEmptyxSO : out std_ulogic;
+ NorthFifoStatusProgFullxSO : out std_ulogic;
+ -- East
+ EastRXM2SDataxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ EastRXM2SLastxSI : in std_ulogic;
+ EastRXM2SValidxSI : in std_ulogic;
+ EastRXS2MReadyxSO : out std_ulogic;
+ EastTXM2SDataxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ EastTXM2SLastxSO : out std_ulogic;
+ EastTXM2SValidxSO : out std_ulogic;
+ EastTXS2MReadyxSI : in std_ulogic;
+ EastFifoStatusWrDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ EastFifoStatusRdDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ EastFifoStatusProgEmptyxSO : out std_ulogic;
+ EastFifoStatusProgFullxSO : out std_ulogic;
+ -- South
+ SouthRXM2SDataxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ SouthRXM2SLastxSI : in std_ulogic;
+ SouthRXM2SValidxSI : in std_ulogic;
+ SouthRXS2MReadyxSO : out std_ulogic;
+ SouthTXM2SDataxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ SouthTXM2SLastxSO : out std_ulogic;
+ SouthTXM2SValidxSO : out std_ulogic;
+ SouthTXS2MReadyxSI : in std_ulogic;
+ SouthFifoStatusWrDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ SouthFifoStatusRdDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ SouthFifoStatusProgEmptyxSO : out std_ulogic;
+ SouthFifoStatusProgFullxSO : out std_ulogic;
+ -- West
+ WestRXM2SDataxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ WestRXM2SLastxSI : in std_ulogic;
+ WestRXM2SValidxSI : in std_ulogic;
+ WestRXS2MReadyxSO : out std_ulogic;
+ WestTXM2SDataxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ WestTXM2SLastxSO : out std_ulogic;
+ WestTXM2SValidxSO : out std_ulogic;
+ WestTXS2MReadyxSI : in std_ulogic;
+ WestFifoStatusWrDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ WestFifoStatusRdDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ WestFifoStatusProgEmptyxSO : out std_ulogic;
+ WestFifoStatusProgFullxSO : out std_ulogic);
+
+end scalp_aurora_phy_rx_fifo_ip_wrapper;
+
+architecture arch of scalp_aurora_phy_rx_fifo_ip_wrapper is
+
+begin
+
+ ScalpAuroraPhyRxFifoxI : entity work.scalp_aurora_phy_rx_fifo
+ generic map (
+ C_CTRL_TLAST => C_CTRL_TLAST)
+ port map (
+ RXClkxCI => RXClkxC,
+ TXClkxCI => TXClkxC,
+ RXRstxRANI.NorthxR => NorthRXRstxRANI,
+ RXRstxRANI.EastxR => EastRXRstxRANI,
+ RXRstxRANI.SouthxR => SouthRXRstxRANI,
+ RXRstxRANI.WestxR => WestRXRstxRANI,
+ -- North
+ NorthRXM2SxDI.DataxD => NorthRXM2SDataxDI,
+ NorthRXM2SxDI.ValidxS => NorthRXM2SValidxSI,
+ NorthRXM2SxDI.LastxS => NorthRXM2SLastxSI,
+ NorthRXS2MxDO.ReadyxS => NorthRXS2MReadyxSO,
+ NorthTXM2SxDO.DataxD => NorthTXM2SDataxDO,
+ NorthTXM2SxDO.ValidxS => NorthTXM2SValidxSO,
+ NorthTXM2SxDO.LastxS => NorthTXM2SLastxSO,
+ NorthTXS2MxDI.ReadyxS => NorthTXS2MReadyxSI,
+ NorthFifoStatusxDO.WrDataCntxD => NorthFifoStatusWrDataCntxDO,
+ NorthFifoStatusxDO.RdDataCntxD => NorthFifoStatusRdDataCntxDO,
+ NorthFifoStatusxDO.ProgEmptyxS => NorthFifoStatusProgEmptyxSO,
+ NorthFifoStatusxDO.ProgFullxS => NorthFifoStatusProgFullxSO,
+ -- East
+ EastRXM2SxDI.DataxD => EastRXM2SDataxDI,
+ EastRXM2SxDI.ValidxS => EastRXM2SValidxSI,
+ EastRXM2SxDI.LastxS => EastRXM2SLastxSI,
+ EastRXS2MxDO.ReadyxS => EastRXS2MReadyxSO,
+ EastTXM2SxDO.DataxD => EastTXM2SDataxDO,
+ EastTXM2SxDO.ValidxS => EastTXM2SValidxSO,
+ EastTXM2SxDO.LastxS => EastTXM2SLastxSO,
+ EastTXS2MxDI.ReadyxS => EastTXS2MReadyxSI,
+ EastFifoStatusxDO.WrDataCntxD => EastFifoStatusWrDataCntxDO,
+ EastFifoStatusxDO.RdDataCntxD => EastFifoStatusRdDataCntxDO,
+ EastFifoStatusxDO.ProgEmptyxS => EastFifoStatusProgEmptyxSO,
+ EastFifoStatusxDO.ProgFullxS => EastFifoStatusProgFullxSO,
+ -- South
+ SouthRXM2SxDI.DataxD => SouthRXM2SDataxDI,
+ SouthRXM2SxDI.ValidxS => SouthRXM2SValidxSI,
+ SouthRXM2SxDI.LastxS => SouthRXM2SLastxSI,
+ SouthRXS2MxDO.ReadyxS => SouthRXS2MReadyxSO,
+ SouthTXM2SxDO.DataxD => SouthTXM2SDataxDO,
+ SouthTXM2SxDO.ValidxS => SouthTXM2SValidxSO,
+ SouthTXM2SxDO.LastxS => SouthTXM2SLastxSO,
+ SouthTXS2MxDI.ReadyxS => SouthTXS2MReadyxSI,
+ SouthFifoStatusxDO.WrDataCntxD => SouthFifoStatusWrDataCntxDO,
+ SouthFifoStatusxDO.RdDataCntxD => SouthFifoStatusRdDataCntxDO,
+ SouthFifoStatusxDO.ProgEmptyxS => SouthFifoStatusProgEmptyxSO,
+ SouthFifoStatusxDO.ProgFullxS => SouthFifoStatusProgFullxSO,
+ -- West
+ WestRXM2SxDI.DataxD => WestRXM2SDataxDI,
+ WestRXM2SxDI.ValidxS => WestRXM2SValidxSI,
+ WestRXM2SxDI.LastxS => WestRXM2SLastxSI,
+ WestRXS2MxDO.ReadyxS => WestRXS2MReadyxSO,
+ WestTXM2SxDO.DataxD => WestTXM2SDataxDO,
+ WestTXM2SxDO.ValidxS => WestTXM2SValidxSO,
+ WestTXM2SxDO.LastxS => WestTXM2SLastxSO,
+ WestTXS2MxDI.ReadyxS => WestTXS2MReadyxSI,
+ WestFifoStatusxDO.WrDataCntxD => WestFifoStatusWrDataCntxDO,
+ WestFifoStatusxDO.RdDataCntxD => WestFifoStatusRdDataCntxDO,
+ WestFifoStatusxDO.ProgEmptyxS => WestFifoStatusProgEmptyxSO,
+ WestFifoStatusxDO.ProgFullxS => WestFifoStatusProgFullxSO);
+
+end arch;
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci b/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
index 6e4b3254493443413d816624c5c48182956d42dd..e82e17ef221a4ebc1dbed0b2274064028bdafcb9 100644
--- a/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
@@ -61,18 +61,18 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_DEPTH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_MEMORY_TYPE">block</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_MODE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_MODE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_ACLK_ASYNC">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH">920</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ADV_FEATURES">826617925</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ADV_FEATURES">825634870</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axis_data_fifo</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_DEPTH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE">block</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MODE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MODE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AEMPTY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AFULL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ECC_ERR_INJECT">0</spirit:configurableElementValue>
@@ -108,11 +108,11 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.gen/sources_1/ip/axis_data_fifo</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../tmp_edit_project.gen/sources_1/ip/axis_data_fifo</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
- <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
diff --git a/ips/hw/scalp_aurora_phy_rx_fifo/xgui/scalp_aurora_phy_rx_fifo_ip_wrapper_v1_0.tcl b/ips/hw/scalp_aurora_phy_rx_fifo/xgui/scalp_aurora_phy_rx_fifo_ip_wrapper_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..84c5be9204760054e3d8425896f4f42d9b63e943
--- /dev/null
+++ b/ips/hw/scalp_aurora_phy_rx_fifo/xgui/scalp_aurora_phy_rx_fifo_ip_wrapper_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_CTRL_TLAST" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_CTRL_TLAST { PARAM_VALUE.C_CTRL_TLAST } {
+ # Procedure called to update C_CTRL_TLAST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_CTRL_TLAST { PARAM_VALUE.C_CTRL_TLAST } {
+ # Procedure called to validate C_CTRL_TLAST
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_CTRL_TLAST { MODELPARAM_VALUE.C_CTRL_TLAST PARAM_VALUE.C_CTRL_TLAST } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_CTRL_TLAST}] ${MODELPARAM_VALUE.C_CTRL_TLAST}
+}
+
diff --git a/ips/hw/scalp_dma_fifo/component.xml b/ips/hw/scalp_dma_fifo/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..8bd360d89a92fbbb4d5bf6c03ff9e401a243d0dc
--- /dev/null
+++ b/ips/hw/scalp_dma_fifo/component.xml
@@ -0,0 +1,699 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>hepia.hesge.ch</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>scalp_dma_fifo</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>RXClkxCI</spirit:name>
+ <spirit:displayName>RXClkxCI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>RXClkxCI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RXCLKXCI.FREQ_HZ"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RXCLKXCI.ASSOCIATED_RESET">RXRstxRANI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RXCLKXCI.ASSOCIATED_BUSIF">DMARXxDI</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>TXClkxCI</spirit:name>
+ <spirit:displayName>TXClkxCI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>TXClkxCI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.TXCLKXCI.FREQ_HZ"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.TXCLKXCI.ASSOCIATED_RESET">RXRstxRANI:WrDataCntxDO:RdDataCntxDO:ProgEmptyxSO:ProgFullxSO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.TXCLKXCI.ASSOCIATED_BUSIF">DMATXxDO</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>RXRstxRANI</spirit:name>
+ <spirit:displayName>RXRstxRANI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>RXRstxRANI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>WrDataCntxDO</spirit:name>
+ <spirit:displayName>WrDataCntxDO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>WrDataCntxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>RdDataCntxDO</spirit:name>
+ <spirit:displayName>RdDataCntxDO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>RdDataCntxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ProgEmptyxSO</spirit:name>
+ <spirit:displayName>ProgEmptyxSO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ProgEmptyxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.PROGEMPTYXSO.NUM_READ_OUTSTANDING"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.PROGEMPTYXSO.NUM_WRITE_OUTSTANDING"/>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ProgFullxSO</spirit:name>
+ <spirit:displayName>ProgFullxSO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ProgFullxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.PROGFULLXSO.NUM_READ_OUTSTANDING"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.PROGFULLXSO.NUM_WRITE_OUTSTANDING"/>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>DMARXxDI</spirit:name>
+ <spirit:displayName>DMARXxDI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMARXDataxDI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TLAST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMARXLastxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMARXValidxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMARXReadyxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>DMATXxDO</spirit:name>
+ <spirit:displayName>DMATXxDO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMATXDataxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TLAST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMATXLastxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMATXValidxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>DMATXReadyxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>VHDL-2008</spirit:language>
+ <spirit:modelName>scalp_dma_fifo</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>dd0fe8c0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>VHDL-2008</spirit:language>
+ <spirit:modelName>scalp_dma_fifo</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_axis_data_fifo_2_0__ref_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>dd0fe8c0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>3e0ee82e</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>RXClkxCI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>TXClkxCI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>RXRstxRANI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>DMARXDataxDI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>DMARXLastxSI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>DMARXValidxSI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
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diff --git a/ips/hw/scalp_dma_fifo/src/axi4_pkg.vhd b/ips/hw/scalp_dma_fifo/src/axi4_pkg.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..8eea268bbb882881c9d7da275dde0bcf48567310
--- /dev/null
+++ b/ips/hw/scalp_dma_fifo/src/axi4_pkg.vhd
@@ -0,0 +1,234 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: axi4_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: AXI4 format bus signals.
+--
+-- Last update: 2021-05-21
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package axi4_pkg is
+
+ constant C_AXI4_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_KEEP_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_UFC_RX_DATA_SIZE : integer range 0 to 32 := 32;
+ constant C_AXI4_UFC_TX_DATA_SIZE : integer range 0 to 32 := 3;
+ constant C_AXI4_NFC_DATA_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_DEST_SIZE : integer range 0 to 32 := 4;
+ constant C_AXI4_STRB_SIZE : integer range 0 to 32 := C_AXI4_KEEP_SIZE; -- Same as Keep
+ constant C_AXI4_USER_SIZE : integer range 0 to 32 := 32;
+
+ -- AXI4 Framing
+ -- Master to Slave
+ type t_axi4m2s is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_DATA_SIZE - 1));
+ KeepxD : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+ LastxS : std_ulogic;
+ ValidxS : std_ulogic;
+ -- Not Necessary
+ IdxS : std_ulogic;
+ DestxD : std_ulogic_vector(0 to (C_AXI4_DEST_SIZE - 1));
+ StrbxD : std_ulogic_vector(0 to (C_AXI4_STRB_SIZE - 1));
+ UserxD : std_ulogic_vector(0 to (C_AXI4_USER_SIZE - 1));
+ end record t_axi4m2s;
+
+ -- Slave to Master
+ type t_axi4s2m is record
+ ReadyxS : std_ulogic;
+ end record t_axi4s2m;
+
+ constant C_NO_AXI4_M2S : t_axi4m2s := (DataxD => (others => '0'),
+ KeepxD => (others => '0'),
+ LastxS => '0',
+ ValidxS => '0',
+ IdxS => '0',
+ DestxD => (others => '0'),
+ StrbxD => (others => '0'),
+ UserxD => (others => '0'));
+ constant C_NO_AXI4_S2M : t_axi4s2m := (ReadyxS => '0');
+ constant C_ON_AXI4_S2M : t_axi4s2m := (ReadyxS => '1');
+
+ type t_axi4_dual_clk is record
+ RXClkxC : std_ulogic;
+ TXClkxC : std_ulogic;
+ end record t_axi4_dual_clk;
+
+ constant C_NO_AXI4_DUAL_CLK : t_axi4_dual_clk := (RXClkxC => '0',
+ TXClkxC => '0');
+
+ type t_axi4_rst is record
+ RstxRAN : std_ulogic;
+ end record t_axi4_rst;
+
+ constant C_NO_AXI4_RST : t_axi4_rst := (RstxRAN => '1');
+
+ -- Non-Generic Vector of AXI4 Framing Bus
+ ---------------------------------------------------------------------------
+ -- constant C_SIM_VIVADO_VECTOR_SIZE : integer := 6;
+ -- type t_axi4m2s_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4m2s;
+ -- type t_axi4s2m_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4s2m;
+
+ -- constant C_NO_SIM_AXISM2S_VECTOR : t_axi4m2s_vector := (others => C_NO_AXI4_M2S);
+ -- constant C_NO_SIM_AXISS2M_VECTOR : t_axi4s2m_vector := (others => C_NO_AXI4_S2M);
+ -- -- Generic Vector of AXI4 Framing Bus Vector
+ -- type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+ -- type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+ ---------------------------------------------------------------------------
+ -- Generic Vector of AXI4 Framing Bus
+ type t_axi4m2s_vector is array (natural range <>) of t_axi4m2s;
+ type t_axi4s2m_vector is array (natural range <>) of t_axi4s2m;
+
+ -- Generic Vector of AXI4 Framing Bus Vector
+ type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+ type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+
+ -- AXI4 UFC
+ -- Master to Slave RX
+ type t_axi4ufcm2s_rx is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_RX_DATA_SIZE - 1));
+ KeepxD : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+ LastxS : std_ulogic;
+ ValidxS : std_ulogic;
+ end record t_axi4ufcm2s_rx;
+
+ -- Master to Slave TX
+ type t_axi4ufcm2s_tx is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_UFC_TX_DATA_SIZE - 1));
+ ValidxS : std_ulogic;
+ end record t_axi4ufcm2s_tx;
+
+ -- Slave to Master
+ type t_axi4ufcs2m_tx is record
+ ReadyxS : std_ulogic;
+ end record t_axi4ufcs2m_tx;
+
+ constant C_NO_AXI4_UFC_M2S_RX : t_axi4ufcm2s_rx := (DataxD => (others => '0'),
+ KeepxD => (others => '0'),
+ LastxS => '0',
+ ValidxS => '0');
+ constant C_NO_AXI4_UFC_M2S_TX : t_axi4ufcm2s_tx := (DataxD => (others => '0'),
+ ValidxS => '0');
+ constant C_NO_AXI4_UFC_S2M_TX : t_axi4ufcs2m_tx := (ReadyxS => '0');
+
+ -- AXI4 NFC
+ -- Master to Slave
+ type t_axi4nfcm2s is record
+ -- Big Endian
+ DataxD : std_ulogic_vector(0 to (C_AXI4_NFC_DATA_SIZE - 1));
+ ValidxS : std_ulogic;
+ end record t_axi4nfcm2s;
+
+ -- Slave to Master
+ type t_axi4nfcs2m is record
+ ReadyxS : std_ulogic;
+ end record t_axi4nfcs2m;
+
+ constant C_NO_AXI4_NFC_M2S : t_axi4nfcm2s := (DataxD => (others => '0'),
+ ValidxS => '0');
+ constant C_NO_AXI4_NFC_S2M : t_axi4nfcs2m := (ReadyxS => '0');
+
+ -- NFC Codes
+ constant C_NFC_XON : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
+ constant C_NFC_XOFF : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '1');
+
+ type t_nfc_states is (C_NFC_IDLE, C_NFC_IS_XON, C_NFC_IS_XOFF, C_NFC_SEND_XON, C_NFC_SEND_XOFF);
+
+ -- Axis Fifo Status
+ type t_axi4fifo_status is record
+ WrDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RdDataCntxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ ProgEmptyxS : std_ulogic;
+ ProgFullxS : std_ulogic;
+ end record t_axi4fifo_status;
+
+ constant C_NO_AXI4_FIFO_STATUS : t_axi4fifo_status := (WrDataCntxD => (others => '0'),
+ RdDataCntxD => (others => '0'),
+ ProgEmptyxS => '0',
+ ProgFullxS => '0');
+
+ -- Axis Fifo Error Counter
+ type t_axi4fifo_error is record
+ NorthCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ EastCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ SouthCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ WestCounterxD : unsigned((C_AXI4_DATA_SIZE - 1) downto 0);
+ end record t_axi4fifo_error;
+
+ constant C_NO_AXI4_FIFO_ERROR : t_axi4fifo_error := (NorthCounterxD => (others => '0'),
+ EastCounterxD => (others => '0'),
+ SouthCounterxD => (others => '0'),
+ WestCounterxD => (others => '0'));
+
+ -- Native Fifo for Scalp packets
+ type t_native_fifo_slave is record
+ DataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ WrEnxS : std_ulogic;
+ RdEnxS : std_ulogic;
+ end record t_native_fifo_slave;
+
+ constant C_NO_NATIVE_FIFO_SLAVE : t_native_fifo_slave := (DataxD => (others => '0'),
+ WrEnxS => '0',
+ RdEnxS => '0');
+
+ type t_native_fifo_master is record
+ DataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ FullxS : std_ulogic;
+ EmptyxS : std_ulogic;
+ AlmostFullxS : std_ulogic;
+ AlmostEmptyxS : std_ulogic;
+ WrRstBusyxS : std_ulogic;
+ RdRstBusyxS : std_ulogic;
+ end record t_native_fifo_master;
+
+ constant C_NO_NATIVE_FIFO_MASTER : t_native_fifo_master := (DataxD => (others => '0'),
+ FullxS => '0',
+ EmptyxS => '0',
+ AlmostFullxS => '0',
+ AlmostEmptyxS => '0',
+ WrRstBusyxS => '0',
+ RdRstBusyxS => '0');
+
+ -- AXI4 Functions
+ -- OR reduce from t_axi4s2m_vector
+ function or_reduce_t_axi4s2m_vector (
+ signal VectorxD : t_axi4s2m_vector)
+ return t_axi4s2m;
+
+end package axi4_pkg;
+
+package body axi4_pkg is
+
+ -- AXI4 Functions
+ -- OR reduce from t_axi4s2m_vector
+ function or_reduce_t_axi4s2m_vector (
+ signal VectorxD : t_axi4s2m_vector)
+ return t_axi4s2m is
+ variable ResultxS : t_axi4s2m := C_NO_AXI4_S2M;
+ begin -- function or_reduce_t_axi4s2m_vector
+ for i in VectorxD'range loop
+ ResultxS.ReadyxS := ResultxS.ReadyxS or VectorxD(i).ReadyxS;
+ end loop; -- i
+
+ return ResultxS;
+ end function or_reduce_t_axi4s2m_vector;
+
+end package body axi4_pkg;
diff --git a/ips/hw/scalp_dma_fifo/src/hdl/scalp_dma_fifo.vhd b/ips/hw/scalp_dma_fifo/src/hdl/scalp_dma_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dab2226fa8c0b58d5b95ad04d5b1a73a5db84915
--- /dev/null
+++ b/ips/hw/scalp_dma_fifo/src/hdl/scalp_dma_fifo.vhd
@@ -0,0 +1,116 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_dma_fifo - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_dma_fifo
+--
+-- Last update: 2021-09-22
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.axi4_pkg.all;
+--use work.aurora_status_pkg.all;
+
+entity scalp_dma_fifo is
+
+ generic (
+ C_CTRL_LAST : boolean := true);
+
+ port (
+ -- Clocks and Resets
+ RXClkxCI : in std_ulogic;
+ TXClkxCI : in std_ulogic;
+ RXRstxRANI : in std_ulogic;
+ -- RX
+ DMARXDataxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMARXLastxSI : in std_ulogic;
+ DMARXValidxSI : in std_ulogic;
+ DMARXReadyxSO : out std_ulogic;
+ -- TX
+ DMATXDataxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMATXLastxSO : out std_ulogic;
+ DMATXValidxSO : out std_ulogic;
+ DMATXReadyxSI : in std_ulogic;
+ -- Status
+ WrDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RdDataCntxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ ProgEmptyxSO : out std_ulogic;
+ ProgFullxSO : out std_ulogic);
+
+end scalp_dma_fifo;
+
+architecture arch of scalp_dma_fifo is
+
+ component axis_data_fifo
+ port (
+ s_axis_aresetn : in std_logic;
+ s_axis_aclk : in std_logic;
+ s_axis_tvalid : in std_logic;
+ s_axis_tready : out std_logic;
+ s_axis_tdata : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ -- s_axis_tkeep : in std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
+ s_axis_tlast : in std_logic;
+ m_axis_aclk : in std_logic;
+ m_axis_tvalid : out std_logic;
+ m_axis_tready : in std_logic;
+ m_axis_tdata : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ -- m_axis_tkeep : out std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
+ m_axis_tlast : out std_logic;
+ axis_wr_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ axis_rd_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ prog_empty : out std_logic;
+ prog_full : out std_logic);
+ end component;
+
+ -- Signals
+ signal DMATXLastxS : std_ulogic := '0';
+
+begin
+
+ CtrlTLastxG : if C_CTRL_LAST = true generate
+
+ DMATXLastCtrlxAS : DMATXLastxSO <= '1' when (DMATXLastxS = '1') and (DMATXValidxSO = '1') else '0';
+
+ elsif C_CTRL_LAST = false generate
+
+ DMATXLastNoCtrlxAS : DMATXLastxSO <= DMATXLastxS;
+
+ end generate CtrlTLastxG;
+
+ AxisDataFifoxI : axis_data_fifo
+ port map (
+ -- Slave side
+ s_axis_aresetn => RXRstxRANI,
+ s_axis_aclk => RXClkxCI,
+ s_axis_tdata => DMARXDataxDI,
+ s_axis_tlast => DMARXLastxSI,
+ s_axis_tvalid => DMARXValidxSI,
+ s_axis_tready => DMARXReadyxSO,
+ -- Master side
+ m_axis_aclk => TXClkxCI,
+ m_axis_tdata => DMATXDataxDO,
+ m_axis_tlast => DMATXLastxS,
+ m_axis_tvalid => DMATXValidxSO,
+ m_axis_tready => DMATXReadyxSI,
+ -- Status
+ axis_wr_data_count => WrDataCntxDO,
+ axis_rd_data_count => RdDataCntxDO,
+ prog_empty => ProgEmptyxSO,
+ prog_full => ProgFullxSO);
+
+end arch;
diff --git a/ips/hw/scalp_dma_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci b/ips/hw/scalp_dma_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
new file mode 100644
index 0000000000000000000000000000000000000000..e82e17ef221a4ebc1dbed0b2274064028bdafcb9
--- /dev/null
+++ b/ips/hw/scalp_dma_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
@@ -0,0 +1,154 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>axis_data_fifo</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_data_fifo" spirit:version="2.0"/>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH">920</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ADV_FEATURES">825634870</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axis_data_fifo</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_DEPTH">1024</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE">block</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MODE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AEMPTY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AFULL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ECC_ERR_INJECT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_EMPTY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_FULL">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_WR_DATA_COUNT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_ACLK_ASYNC">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_EMPTY_THRESH">100</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_FULL_THRESH">920</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">hepia-cores.ch:scalp_node:part0:0.1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../tmp_edit_project.gen/sources_1/ip/axis_data_fifo</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_DEPTH" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_MODE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_PROG_EMPTY" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_PROG_FULL" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_RD_DATA_COUNT" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_WR_DATA_COUNT" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IS_ACLK_ASYNC" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROG_EMPTY_THRESH" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROG_FULL_THRESH" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ <xilinx:boundaryDescriptionInfo>
+ <xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"s_axis_aresetn":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axis_aclk":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axis_tvalid":{"direction":"in","physical_left":"0","physical_right":"0"},"s_axis_tready":{"direction":"out","physical_left":"0","physical_right":"0"},"s_axis_tdata":{"direction":"in","physical_left":"31","physical_right":"0"},"s_axis_tlast":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axis_aclk":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axis_tvalid":{"direction":"out","physical_left":"0","physical_right":"0"},"m_axis_tready":{"direction":"in","physical_left":"0","physical_right":"0"},"m_axis_tdata":{"direction":"out","physical_left":"31","physical_right":"0"},"m_axis_tlast":{"direction":"out","physical_left":"0","physical_right":"0"},"axis_wr_data_count":{"direction":"out","physical_left":"31","physical_right":"0"},"axis_rd_data_count":{"direction":"out","physical_left":
+"31","physical_right":"0"},"prog_empty":{"direction":"out","physical_left":"0","physical_right":"0"},"prog_full":{"direction":"out","physical_left":"0","physical_right":"0"}},"interfaces":{"S_AXIS":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"slave","parameters":{"TDATA_NUM_BYTES":[{"value":"4"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"TDEST_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"TID_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"TUSER_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TREADY":[{"value":"1"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TSTRB":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TKEEP":[{"
+value":"0"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TLAST":[{"value":"1"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"LAYERED_METADATA":[{"value":"undef"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"TDATA":{"physical_name":"s_axis_tdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0"},"TLAST":{"physical_name":"s_axis_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logica
+l_right":"0"},"TREADY":{"physical_name":"s_axis_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TVALID":{"physical_name":"s_axis_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"M_AXIS":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"master","parameters":{"TDATA_NUM_BYTES":[{"value":"4"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"TDEST_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"TID_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"TUSER_WIDTH":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TREADY":[{"value":"1"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TSTRB":[{"value":"0"},{"value_src":"default"}
+,{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TKEEP":[{"value":"0"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"HAS_TLAST":[{"value":"1"},{"value_src":"auto"},{"value_permission":"user"},{"resolve_type":"generated"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"LAYERED_METADATA":[{"value":"undef"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"TDATA":{"physical_name":"m_axis_tdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0"},"TLAST":{"physical_name":"m_axis_
+tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TREADY":{"physical_name":"m_axis_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"},"TVALID":{"physical_name":"m_axis_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"S_RSTIF":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"POLARITY":[{"value":"ACTIVE_LOW"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"RST":{"physical_name":"s_axis_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"S_CLKIF":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"S_AXIS"},{"val
+ue_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"s_axis_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}},"M_CLKIF":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","param
+eters":{"ASSOCIATED_BUSIF":[{"value":"M_AXIS"},{"value_src":"constant"},{"value_permission":"user"},{"resolve_type":"immediate"}],"FREQ_HZ":[{"value":"100000000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}],"FREQ_TOLERANCE_HZ":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"PHASE":[{"value":"0.000"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"CLK_DOMAIN":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"ASSOCIATED_RESET":[{"value":""},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"generated"}],"INSERT_VIP":[{"value":"0"},{"value_src":"default"},{"value_permission":"user"},{"resolve_type":"user"}]},"port_maps":{"CLK":{"physical_name":"m_axis_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0"}}}}}}"/>
+ </xilinx:boundaryDescriptionInfo>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/ips/hw/scalp_dma_fifo/src/sim/tb_scalp_dma_fifo.vhd b/ips/hw/scalp_dma_fifo/src/sim/tb_scalp_dma_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e8b24586cff9e51842f8135eb642d09e9192d825
--- /dev/null
+++ b/ips/hw/scalp_dma_fifo/src/sim/tb_scalp_dma_fifo.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: tb_scalp_dma_fifo - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_dma_fifo
+--
+-- Last update: 2021-09-22 13:32:31
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_dma_fifo is
+end tb_scalp_dma_fifo;
+
+
+architecture behavioral of tb_scalp_dma_fifo is
+
+begin
+
+end behavioral;
diff --git a/ips/hw/scalp_dma_fifo/xgui/scalp_dma_fifo_v1_0.tcl b/ips/hw/scalp_dma_fifo/xgui/scalp_dma_fifo_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ad8a382387ca952df8092205d85d5012812c9f38
--- /dev/null
+++ b/ips/hw/scalp_dma_fifo/xgui/scalp_dma_fifo_v1_0.tcl
@@ -0,0 +1,25 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_CTRL_LAST" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_CTRL_LAST { PARAM_VALUE.C_CTRL_LAST } {
+ # Procedure called to update C_CTRL_LAST when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_CTRL_LAST { PARAM_VALUE.C_CTRL_LAST } {
+ # Procedure called to validate C_CTRL_LAST
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_CTRL_LAST { MODELPARAM_VALUE.C_CTRL_LAST PARAM_VALUE.C_CTRL_LAST } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_CTRL_LAST}] ${MODELPARAM_VALUE.C_CTRL_LAST}
+}
+
diff --git a/ips/hw/scalp_fast_router_registers/component.xml b/ips/hw/scalp_fast_router_registers/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..57836391d464f5f49c88560897fdb88e1eda6691
--- /dev/null
+++ b/ips/hw/scalp_fast_router_registers/component.xml
@@ -0,0 +1,1247 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>hepia.hesge.ch</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>scalp_fast_router_registers</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>SAxiClkxCI</spirit:name>
+ <spirit:displayName>SAxiClkxCI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiClkxCI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.FREQ_HZ">125000000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_RESET">DMAFifoWrDataCntxDO:DMAFifoRrDataCntxDO:LocalNetAddrxDO:RGBLed0xDO:RGBLed1xDO:DMAFifoStatusxDI:DMAFifoWrDataCntxDI:DMAFifoRrDataCntxDI:SAxiRstxRANI:DMAFifoTXWrDataCntxDI:DMAFifoTXRrDataCntxDI:DMAFifoTXStatusxDI:DMAFifoRXWrDataCntxDI:DMAFifoRXRrDataCntxDI:DMAFifoRXStatusxDI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_BUSIF">SAxiLitexDIO</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>SAxiRstxRANI</spirit:name>
+ <spirit:displayName>SAxiRstxRANI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiRstxRANI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>LocalNetAddrxD</spirit:name>
+ <spirit:displayName>LocalNetAddrxD</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>LocalNetAddrxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>RGBLed0xDO</spirit:name>
+ <spirit:displayName>RGBLed0xDO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="data_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>DATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>RGBLed0xDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RGBLED0XDO.NUM_READ_OUTSTANDING"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.RGBLED0XDO.NUM_WRITE_OUTSTANDING"/>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
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+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="3cecaf9e"/>
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+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="d7187a94"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd b/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..02780d8967d64078fe238c13770c37d62dcdd508
--- /dev/null
+++ b/ips/hw/scalp_fast_router_registers/src/hdl/scalp_fast_router_registers.vhd
@@ -0,0 +1,384 @@
+-- THIS IS AN AUTOGENERATED FILE. DO NOT EDIT THIS FILE DIRECTLY.
+-- scalp_regedit v0.1 - 05.2021
+-- Author : Joachim Schmidt <joachim.schmidt@hesge.ch>
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_misc.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity scalp_fast_router_registers is
+
+ generic (
+ C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_RDATA_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2;
+ C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_WDATA_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4;
+ C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2;
+ C_AXI4_ADDR_SIZE : integer range 0 to 32 := 12;
+ C_AXI4_DATA_SIZE : integer range 0 to 32 := 32);
+
+ port (
+ -- Clock and reset
+ SAxiClkxCI : in std_ulogic;
+ SAxiRstxRANI : in std_ulogic;
+ -- AXI4 Lite
+ -- Read Channel
+ -- Read Address Channel
+ SAxiARAddrxDI : in std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
+ SAxiARValidxSI : in std_ulogic;
+ SAxiARReadyxSO : out std_ulogic;
+ -- Read Data Channel
+ SAxiRDataxDO : out std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
+ SAxiRRespxDO : out std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
+ SAxiRValidxSO : out std_ulogic;
+ SAxiRReadyxSI : in std_ulogic;
+ -- Write Channel
+ -- Write Address Channel
+ SAxiAWAddrxDI : in std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
+ SAxiAWValidxSI : in std_ulogic;
+ SAxiAWReadyxSO : out std_ulogic;
+ -- Write Data Channel
+ SAxiWDataxDI : in std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
+ SAxiWStrbxDI : in std_ulogic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
+ SAxiWValidxSI : in std_ulogic;
+ SAxiWReadyxSO : out std_ulogic;
+ -- Write Response Channel
+ SAxiBRespxDO : out std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
+ SAxiBValidxSO : out std_ulogic;
+ SAxiBReadyxSI : in std_ulogic;
+ -- Registers list IO
+ LocalNetAddrxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RGBLed0xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RGBLed1xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMAFifoTXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMAFifoTXRrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMAFifoTXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMAFifoRXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMAFifoRXRrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ DMAFifoRXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
+
+end scalp_fast_router_registers;
+
+architecture behavioral of scalp_fast_router_registers is
+
+ -- Constants
+ constant C_AXI4_RRESP_OKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00";
+ constant C_AXI4_RRESP_EXOKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01";
+ constant C_AXI4_RRESP_SLVERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10";
+ constant C_AXI4_RRESP_DECERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11";
+ constant C_AXI4_BRESP_OKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00";
+ constant C_AXI4_BRESP_EXOKAY : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01";
+ constant C_AXI4_BRESP_SLVERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10";
+ constant C_AXI4_BRESP_DECERR : std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11";
+
+ -- Signals
+ -- Clock and reset
+ signal SAxiClkxC : std_ulogic := '0';
+ signal SAxiRstxRAN : std_ulogic := '0';
+ -- AXI4 Lite
+ signal SAxiARReadyxS : std_ulogic := '0';
+ signal SAxiRValidxS : std_ulogic := '0';
+ signal SAxiBValidxS : std_ulogic := '0';
+ signal SAxiWReadyxS : std_ulogic := '0';
+ signal SAxiAWReadyxS : std_ulogic := '0';
+ signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ -- Signals of access to the register bank
+ signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
+ -- Registers list
+ signal LocalNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal LocalNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed0PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed0PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed1PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RGBLed1PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoTXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal DMAFifoRXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+
+begin
+
+ assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
+ report "RDATA and DATA vectors must be the same" severity failure;
+
+ assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
+ report "ARADDR and ADDR vectors must be the same" severity failure;
+
+ assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
+ report "WDATA and DATA vectors must be the same" severity failure;
+
+ assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
+ report "AWADDR and ADDR vectors must be the same" severity failure;
+
+ EntityIOxB : block is
+ begin -- block EntityIOxB
+
+ -- Clock and reset
+ SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
+ SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
+ -- Read Channel
+ SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
+ SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
+ SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
+ RdValidxAS : RdValidxS <= SAxiARValidxSI;
+ RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
+ SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
+ -- Write Channel
+ SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
+ SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
+ SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
+ SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
+ WrValidxAS : WrValidxS <= SAxiWValidxSI;
+ WrDataxAS : WrDataxD <= SAxiWDataxDI;
+ WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
+ WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
+ SAxiAWValidxSI = '1' else
+ WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
+
+ end block EntityIOxB;
+
+ AXI4LitexB : block is
+ begin -- block AXI4LitexB
+
+ ReadChannelxB : block is
+ begin -- block ReadChannelxB
+
+ ReadAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+
+ variable StateAfterResetxS : boolean := true;
+
+ begin -- process ReadAddrChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiARReadyxS <= '0';
+ StateAfterResetxS := true;
+ elsif rising_edge(SAxiClkxC) then
+ if StateAfterResetxS = true then
+ SAxiARReadyxS <= '1';
+ StateAfterResetxS := false;
+ else
+ SAxiARReadyxS <= SAxiARReadyxS;
+ end if;
+
+ if SAxiARValidxSI = '1' then
+ SAxiARReadyxS <= '0';
+ end if;
+
+ if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then
+ SAxiARReadyxS <= '1';
+ end if;
+ end if;
+ end process ReadAddrChanxP;
+
+ ReadDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process ReadDataChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiRValidxS <= '0';
+ elsif rising_edge(SAxiClkxC) then
+ SAxiRValidxS <= SAxiRValidxS;
+
+ if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then
+ SAxiRValidxS <= '1';
+ end if;
+
+ if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then
+ SAxiRValidxS <= '0';
+ end if;
+ end if;
+ end process ReadDataChanxP;
+
+ end block ReadChannelxB;
+
+ WriteChannelxB : block is
+ begin --block WriteChannelxB
+
+ WrAddrRegxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process WrAddrRegxP
+ if SAxiRstxRAN = '0' then
+ WrAddrxDP <= (others => '0');
+ elsif rising_edge(SAxiClkxC) then
+ WrAddrxDP <= WrAddrxDN;
+ end if;
+ end process WrAddrRegxP;
+
+ WriteAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+
+ variable StateAfterResetxS : boolean := true;
+
+ begin -- process WriteAddrChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiAWReadyxS <= '0';
+ StateAfterResetxS := true;
+ elsif rising_edge(SAxiClkxC) then
+ if StateAfterResetxS = true then
+ SAxiAWReadyxS <= '1';
+ StateAfterResetxS := false;
+ else
+ SAxiAWReadyxS <= SAxiAWReadyxS;
+ end if;
+
+ if SAxiAWValidxSI = '1' then
+ SAxiAWReadyxS <= '0';
+ end if;
+
+ if SAxiWValidxSI = '1' then
+ SAxiAWReadyxS <= '1';
+ end if;
+ end if;
+ end process WriteAddrChanxP;
+
+ WriteDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process WriteDataChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiWReadyxS <= '0';
+ elsif rising_edge(SAxiClkxC) then
+ SAxiWReadyxS <= SAxiWReadyxS;
+
+ if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then
+ SAxiWReadyxS <= '1';
+ end if;
+
+ if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
+ SAxiWReadyxS <= '0';
+ end if;
+ end if;
+ end process WriteDataChanxP;
+
+ WriteRespChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process WriteRespChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiBValidxS <= '0';
+ elsif rising_edge(SAxiClkxC) then
+ SAxiBValidxS <= SAxiBValidxS;
+
+ if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
+ SAxiBValidxS <= '1';
+ end if;
+
+ if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then
+ SAxiBValidxS <= '0';
+ end if;
+ end if;
+ end process WriteRespChanxP;
+
+ end block WriteChannelxB;
+
+ end block AXI4LitexB;
+
+ ScalpFastRouterRegistersxB : block is
+ begin -- block ScalpFastRouterRegistersxB
+
+ WriteRegPortxP : process (DMAFifoRXRrDataCntxDI, DMAFifoRXStatusxDI,
+ DMAFifoRXWrDataCntxDI, DMAFifoTXRrDataCntxDI,
+ DMAFifoTXStatusxDI, DMAFifoTXWrDataCntxDI,
+ LocalNetAddrPortxDP, RGBLed0PortxDP,
+ RGBLed1PortxDP, WrAddrxD, WrDataxD,
+ WrValidxS) is
+ begin -- process WriteRegPortxP
+ LocalNetAddrPortxDN <= LocalNetAddrPortxDP;
+ LocalNetAddrxDO <= LocalNetAddrPortxDP;
+ RGBLed0PortxDN <= RGBLed0PortxDP;
+ RGBLed0xDO <= RGBLed0PortxDP;
+ RGBLed1PortxDN <= RGBLed1PortxDP;
+ RGBLed1xDO <= RGBLed1PortxDP;
+ DMAFifoTXWrDataCntPortxDN <= DMAFifoTXWrDataCntxDI;
+ DMAFifoTXRrDataCntPortxDN <= DMAFifoTXRrDataCntxDI;
+ DMAFifoTXStatusPortxDN <= DMAFifoTXStatusxDI;
+ DMAFifoRXWrDataCntPortxDN <= DMAFifoRXWrDataCntxDI;
+ DMAFifoRXRrDataCntPortxDN <= DMAFifoRXRrDataCntxDI;
+ DMAFifoRXStatusPortxDN <= DMAFifoRXStatusxDI;
+
+ if WrValidxS = '1' then
+ case WrAddrxD is
+ when x"000" => LocalNetAddrPortxDN <= WrDataxD;
+ when x"004" => RGBLed0PortxDN <= WrDataxD;
+ when x"008" => RGBLed1PortxDN <= WrDataxD;
+
+ when others => null;
+ end case;
+ end if;
+ end process WriteRegPortxP;
+
+ ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process ReadRegPortxP
+ if SAxiRstxRAN = '0' then
+ RdDataxD <= (others => '0');
+ elsif rising_edge(SAxiClkxC) then
+ RdDataxD <= RdDataxD;
+
+ if RdValidxS = '1' then
+ case RdAddrxD is
+ when x"000" => RdDataxD <= LocalNetAddrPortxDP;
+ when x"004" => RdDataxD <= RGBLed0PortxDP;
+ when x"008" => RdDataxD <= RGBLed1PortxDP;
+ when x"00C" => RdDataxD <= DMAFifoTXWrDataCntPortxDP;
+ when x"010" => RdDataxD <= DMAFifoTXRrDataCntPortxDP;
+ when x"014" => RdDataxD <= DMAFifoTXStatusPortxDP;
+ when x"018" => RdDataxD <= DMAFifoRXWrDataCntPortxDP;
+ when x"01C" => RdDataxD <= DMAFifoRXRrDataCntPortxDP;
+ when x"020" => RdDataxD <= DMAFifoRXStatusPortxDP;
+
+ when others => RdDataxD <= (others => '0');
+ end case;
+ end if;
+ end if;
+ end process ReadRegPortxP;
+
+ UpdateRegBankxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process UpdateRegBankxP
+ if SAxiRstxRAN = '0' then
+ LocalNetAddrPortxDP <= x"00000000";
+ RGBLed0PortxDP <= x"00000000";
+ RGBLed1PortxDP <= x"00000000";
+ DMAFifoTXWrDataCntPortxDP <= x"00000000";
+ DMAFifoTXRrDataCntPortxDP <= x"00000000";
+ DMAFifoTXStatusPortxDP <= x"00000000";
+ DMAFifoRXWrDataCntPortxDP <= x"00000000";
+ DMAFifoRXRrDataCntPortxDP <= x"00000000";
+ DMAFifoRXStatusPortxDP <= x"00000000";
+
+ elsif rising_edge(SAxiClkxC) then
+ LocalNetAddrPortxDP <= LocalNetAddrPortxDN;
+ RGBLed0PortxDP <= RGBLed0PortxDN;
+ RGBLed1PortxDP <= RGBLed1PortxDN;
+ DMAFifoTXWrDataCntPortxDP <= DMAFifoTXWrDataCntPortxDN;
+ DMAFifoTXRrDataCntPortxDP <= DMAFifoTXRrDataCntPortxDN;
+ DMAFifoTXStatusPortxDP <= DMAFifoTXStatusPortxDN;
+ DMAFifoRXWrDataCntPortxDP <= DMAFifoRXWrDataCntPortxDN;
+ DMAFifoRXRrDataCntPortxDP <= DMAFifoRXRrDataCntPortxDN;
+ DMAFifoRXStatusPortxDP <= DMAFifoRXStatusPortxDN;
+
+ end if;
+ end process UpdateRegBankxP;
+
+ end block ScalpFastRouterRegistersxB;
+
+end behavioral;
diff --git a/ips/hw/scalp_fast_router_registers/src/sim/tb_scalp_fast_router_registers.vhd b/ips/hw/scalp_fast_router_registers/src/sim/tb_scalp_fast_router_registers.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5c7c25df4aedf424339c8205474ce0962e2a849e
--- /dev/null
+++ b/ips/hw/scalp_fast_router_registers/src/sim/tb_scalp_fast_router_registers.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: tb_scalp_fast_router_registers - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_fast_router_registers
+--
+-- Last update: 2021-09-21 08:04:08
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_fast_router_registers is
+end tb_scalp_fast_router_registers;
+
+
+architecture behavioral of tb_scalp_fast_router_registers is
+
+begin
+
+end behavioral;
diff --git a/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_0.tcl b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38
--- /dev/null
+++ b/ips/hw/scalp_fast_router_registers/xgui/scalp_fast_router_registers_v1_0.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.cache/wt/webtalk_pa.xml b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..24d565d9b432be403f659f7c3c4f6c5a8d9e18fc
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.cache/wt/webtalk_pa.xml
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Sep 22 11:21:53 2021">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="26fd8e7542a94eb18312b5f492338211" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AddBusInterfaceHandler" value="32" type="JavaHandler"/>
+<property name="EditProperties" value="1" type="JavaHandler"/>
+<property name="ExitApp" value="2" type="JavaHandler"/>
+<property name="IPPackagerHandler" value="2" type="JavaHandler"/>
+<property name="IPPackagerWizardHandler" value="2" type="JavaHandler"/>
+<property name="SetTopNode" value="1" type="JavaHandler"/>
+<property name="UpdateSourceFiles" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_CANCEL" value="6" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="102" type="GuiHandlerData"/>
+<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
+<property name="EditInterfaceDialog_TABBED_PANE" value="63" type="GuiHandlerData"/>
+<property name="FileGroupFacetTable_REFRESH" value="1" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="9" type="GuiHandlerData"/>
+<property name="IdentificationContentPanel_COMPANY_URL_DISPLAY_NAME" value="1" type="GuiHandlerData"/>
+<property name="IdentificationContentPanel_VENDOR" value="1" type="GuiHandlerData"/>
+<property name="IdentificationContentPanel_VENDOR_DISPLAY_NAME" value="1" type="GuiHandlerData"/>
+<property name="InterfaceConfigurationPanel_DISPLAY_NAME" value="36" type="GuiHandlerData"/>
+<property name="InterfaceConfigurationPanel_MODE" value="10" type="GuiHandlerData"/>
+<property name="InterfaceConfigurationPanel_NAME" value="39" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionChooser_INTERFACE_DEFINITION_CHOOSER" value="32" type="GuiHandlerData"/>
+<property name="InterfaceDefinitionTreeTable_INTERFACES_TREE_TABLE" value="83" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_INTERFACES_LOGICAL_PORTS" value="102" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_IPS_PHYSICAL_PORTS" value="97" type="GuiHandlerData"/>
+<property name="InterfacePortMappingPanel_MAP_PORTS" value="89" type="GuiHandlerData"/>
+<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_EXPORT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FLOW" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_REPORTS" value="12" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TOOLS" value="16" type="GuiHandlerData"/>
+<property name="MainMenuMgr_WINDOW" value="4" type="GuiHandlerData"/>
+<property name="MessageBanner_CHANGES_DETECTED_IN_VIVADO_PROJECT_THAT" value="4" type="GuiHandlerData"/>
+<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="2" type="GuiHandlerData"/>
+<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
+<property name="MsgView_MANAGE_MESSAGE_SUPPRESSION" value="1" type="GuiHandlerData"/>
+<property name="NewIpWizard_IP_DEFINITION_SOURCE_LOCATION" value="1" type="GuiHandlerData"/>
+<property name="NewIpWizard_PACKAGE_YOUR_CURRENT_PROJECT_USE" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_AUTO_UPDATE_HIER" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_EXIT" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_PACKAGER_ADD_BUS_INTERFACE" value="33" type="GuiHandlerData"/>
+<property name="PACommandNames_SET_AS_TOP" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_SRC_REPLACE_FILE" value="1" type="GuiHandlerData"/>
+<property name="PAViews_PACKAGE_IP" value="2" type="GuiHandlerData"/>
+<property name="PackagerStepContentPanel_MESSAGES" value="1" type="GuiHandlerData"/>
+<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="13" type="GuiHandlerData"/>
+<property name="PortAndInterfaceContentPanel_REFRESH" value="3" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_ASSOCIATE_CLOCKS" value="32" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_AUTO_INFER_SINGLE_BIT_INTERFACE" value="2" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_EDIT_INTERFACE" value="9" type="GuiHandlerData"/>
+<property name="PortAndInterfaceFacetTable_PORT_AND_INTERFACE_FACET_TABLE" value="130" type="GuiHandlerData"/>
+<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
+<property name="RDICommands_PROPERTIES" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_PACKAGE_IP" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_RE_PACKAGE_IP" value="1" type="GuiHandlerData"/>
+<property name="SrcMenu_IP_HIERARCHY" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="167" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="141" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.xpr b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.xpr
new file mode 100644
index 0000000000000000000000000000000000000000..88d86167502d57adbecdbf0b541df1ee9c441d26
--- /dev/null
+++ b/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.xpr
@@ -0,0 +1,234 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="54" Path="/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/vivado/scalp_aurora_phy_rx_fifo/2020.2/lin64/scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="26eb93852cae4ddfa906d0ac4042056b"/>
+ <Option Name="Part" Val="xc7z015clg485-2"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirIES" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirIES" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val="hepia-cores.ch:scalp_node:part0:0.1"/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../../../../../../../scalp_firmware"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../../../../../hw"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="DSABoardId" Val="scalp_node"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../../../../../hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../../../../../packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../../../../hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../../../../hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo_ip_wrapper.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../../../../hw/scalp_aurora_phy_rx_fifo/component.xml">
+ <FileInfo SFType="IPXACT"/>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="scalp_aurora_phy_rx_fifo_ip_wrapper"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../../../../../hw/scalp_aurora_phy_rx_fifo/src/sim/tb_scalp_aurora_phy_rx_fifo.vhd">
+ <FileInfo SFType="VHDL2008">
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="scalp_aurora_phy_rx_fifo_ip_wrapper"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="IES">
+ <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="15">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board>
+ <Jumpers/>
+ </Board>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/.gitignore b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..060e20a0b5e3adf3252db77ff21ad79597dcab84
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.gitignore
@@ -0,0 +1,23 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_dma_fifo
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9e041084fcd94caf2e5c0152c9801826a33e59b5
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/clean_prj_scalp_dma_fifo.sh b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/clean_prj_scalp_dma_fifo.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7d8112b80860d7e59e8d29042f600382c3056e21
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/clean_prj_scalp_dma_fifo.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_dma_fifo/ 2> /dev/null
+
+echo "> Done"
+
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/create_prj_scalp_dma_fifo.sh b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/create_prj_scalp_dma_fifo.sh
new file mode 100755
index 0000000000000000000000000000000000000000..71772a31518fd94c5338f0df2df36bae1708b7da
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/create_prj_scalp_dma_fifo.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_dma_fifo.tcl -notrace
+echo "> Done"
+
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/create_prj_scalp_dma_fifo.tcl b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/create_prj_scalp_dma_fifo.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f6192bab8d55aed171ec14da67a7efe6a0a1f382
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/create_prj_scalp_dma_fifo.tcl
@@ -0,0 +1,172 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_dma_fifo'
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_dma_fifo"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set hdl_src_dir "${src_dir}/hdl"
+ set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ set hdl_src_dir "${comp_src_dir}/hdl"
+ set sim_src_dir "${comp_src_dir}/sim"
+}
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+ add_files -norecurse $hdl_src_file_list
+} else {
+ print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
+ # add IPs source files
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # add IPs source files
+ read_ip $comp_src_dir/ip_core/axis_data_fifo/axis_data_fifo.xci
+
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+ add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+ update_compile_order -fileset sim_1
+ print_status "Add simulation sources" "OK"
+} else {
+ print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
+
+# Add packages sources
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ set_property library xil_defaultlib [get_files $j]
+ }
+ set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+ add_files -norecurse $vhdl_pkg_file_list
+ foreach j $vhdl_pkg_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+ set_property is_enabled true [get_files $j]
+ set_property library xil_defaultlib [get_files $j]
+ }
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/open_prj_scalp_dma_fifo.sh b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/open_prj_scalp_dma_fifo.sh
new file mode 100755
index 0000000000000000000000000000000000000000..48aca53c99e4a2e2d4f141916e3fb9ad2474a38f
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/open_prj_scalp_dma_fifo.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_dma_fifo/scalp_dma_fifo.xpr
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..db008d593f6160a608aa253381c7747083a177a4
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/lin64/setup.sh b/ips/vivado/scalp_dma_fifo/2020.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..a25d54b3f9e0ccd55e5b63585ed24afde1619c81
--- /dev/null
+++ b/ips/vivado/scalp_dma_fifo/2020.2/lin64/setup.sh
@@ -0,0 +1,28 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_dma_fifo
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-09-22 13:32:31
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_dma_fifo.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_dma_fifo.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_dma_fifo.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_dma_fifo.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_dma_fifo.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_dma_fifo.sh && cd ..'
diff --git a/ips/vivado/scalp_dma_fifo/2020.2/src/ipi_tcl/scalp_dma_fifo_ipi.tcl b/ips/vivado/scalp_dma_fifo/2020.2/src/ipi_tcl/scalp_dma_fifo_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.gitignore b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..cf1cb247700592d32856e48cbd59130b7cd6a031
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.gitignore
@@ -0,0 +1,23 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_fast_router_registers
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..45f1ff290649b6c1f4adc3ba7a149cd66efa5607
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/clean_prj_scalp_fast_router_registers.sh b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/clean_prj_scalp_fast_router_registers.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7b7dc4602717f0088348a38c50dbeac052b5946f
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/clean_prj_scalp_fast_router_registers.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_fast_router_registers/ 2> /dev/null
+
+echo "> Done"
+
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/create_prj_scalp_fast_router_registers.sh b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/create_prj_scalp_fast_router_registers.sh
new file mode 100755
index 0000000000000000000000000000000000000000..23a9968eff2de5e3feabcd7217a660b151a02bd7
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/create_prj_scalp_fast_router_registers.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_fast_router_registers.tcl -notrace
+echo "> Done"
+
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/create_prj_scalp_fast_router_registers.tcl b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/create_prj_scalp_fast_router_registers.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e0a6df9f09402fb10be48145ca5b024371ca311a
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/create_prj_scalp_fast_router_registers.tcl
@@ -0,0 +1,154 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_fast_router_registers'
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_fast_router_registers"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set hdl_src_dir "${src_dir}/hdl"
+ set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ set hdl_src_dir "${comp_src_dir}/hdl"
+ set sim_src_dir "${comp_src_dir}/sim"
+}
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+ add_files -norecurse $hdl_src_file_list
+} else {
+ print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
+ # add IPs source files
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # add IPs source files
+
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+ add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+ update_compile_order -fileset sim_1
+ print_status "Add simulation sources" "OK"
+} else {
+ print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/open_prj_scalp_fast_router_registers.sh b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/open_prj_scalp_fast_router_registers.sh
new file mode 100755
index 0000000000000000000000000000000000000000..1c45b0f0ec6b495fd26ad0609f541ac367faf856
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/open_prj_scalp_fast_router_registers.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_fast_router_registers/scalp_fast_router_registers.xpr
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..14a6ee90897b4f4f77fa5e18d87d137bfab5ee1e
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/lin64/setup.sh b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7420ddeef1f2ac0d7e72a275919a3090c099b15d
--- /dev/null
+++ b/ips/vivado/scalp_fast_router_registers/2020.2/lin64/setup.sh
@@ -0,0 +1,28 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_fast_router_registers
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-09-21 08:04:08
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_fast_router_registers.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_fast_router_registers.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_fast_router_registers.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_fast_router_registers.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_fast_router_registers.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_fast_router_registers.sh && cd ..'
diff --git a/ips/vivado/scalp_fast_router_registers/2020.2/src/ipi_tcl/scalp_fast_router_registers_ipi.tcl b/ips/vivado/scalp_fast_router_registers/2020.2/src/ipi_tcl/scalp_fast_router_registers_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
index 4cfc93a0e300a6210bee1c2bb35d4367c5525f97..534153e3f4e5f632e8536fa39e947b1625a33880 100644
--- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
--- Last update: 2021-09-20
+-- Last update: 2021-10-04
--
---------------------------------------------------------------------------------
@@ -23,81 +23,160 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
+-- Axi4 packages
+use work.axi4_pkg.all;
+
entity scalp_zynqps_wrapper is
port (
-- Processor interface
- FIXED_IO_ps_clk : inout std_logic;
- FIXED_IO_ps_porb : inout std_logic;
- FIXED_IO_ps_srstb : inout std_logic;
- FclkClk0xCO : out std_logic;
- FclkReset0xRO : out std_logic;
+ FIXED_IO_ps_clk : inout std_ulogic;
+ FIXED_IO_ps_porb : inout std_ulogic;
+ FIXED_IO_ps_srstb : inout std_ulogic;
+ FclkClk0xCO : out std_ulogic;
+ FclkReset0xRO : out std_ulogic;
-- DDR interface
- DDR_addr : inout std_logic_vector (14 downto 0);
- DDR_ba : inout std_logic_vector (2 downto 0);
- DDR_cas_n : inout std_logic;
- DDR_ck_n : inout std_logic;
- DDR_ck_p : inout std_logic;
- DDR_cke : inout std_logic;
- DDR_cs_n : inout std_logic;
- DDR_dm : inout std_logic_vector (3 downto 0);
- DDR_dq : inout std_logic_vector (31 downto 0);
- DDR_dqs_n : inout std_logic_vector (3 downto 0);
- DDR_dqs_p : inout std_logic_vector (3 downto 0);
- DDR_odt : inout std_logic;
- DDR_ras_n : inout std_logic;
- DDR_reset_n : inout std_logic;
- DDR_we_n : inout std_logic;
- FIXED_IO_ddr_vrn : inout std_logic;
- FIXED_IO_ddr_vrp : inout std_logic;
+ DDR_addr : inout std_ulogic_vector (14 downto 0);
+ DDR_ba : inout std_ulogic_vector (2 downto 0);
+ DDR_cas_n : inout std_ulogic;
+ DDR_ck_n : inout std_ulogic;
+ DDR_ck_p : inout std_ulogic;
+ DDR_cke : inout std_ulogic;
+ DDR_cs_n : inout std_ulogic;
+ DDR_dm : inout std_ulogic_vector (3 downto 0);
+ DDR_dq : inout std_ulogic_vector (31 downto 0);
+ DDR_dqs_n : inout std_ulogic_vector (3 downto 0);
+ DDR_dqs_p : inout std_ulogic_vector (3 downto 0);
+ DDR_odt : inout std_ulogic;
+ DDR_ras_n : inout std_ulogic;
+ DDR_reset_n : inout std_ulogic;
+ DDR_we_n : inout std_ulogic;
+ FIXED_IO_ddr_vrn : inout std_ulogic;
+ FIXED_IO_ddr_vrp : inout std_ulogic;
-- USB interface
- Usb0VBusPwrFaultxSI : in std_logic;
+ Usb0VBusPwrFaultxSI : in std_ulogic;
-- SPI1 used as uWire master. Clk, Data and LE signals are outputs
-- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
- Spi1MOSIxSO : out std_logic;
- Spi1SSxSO : out std_logic;
- Spi1SclkxCO : out std_logic;
+ Spi1MOSIxSO : out std_ulogic;
+ Spi1SSxSO : out std_ulogic;
+ Spi1SclkxCO : out std_ulogic;
-- MIO
- FIXED_IO_mio : inout std_logic_vector (53 downto 0);
- UserClkxCI : in std_logic;
- UserResetxRANI : in std_logic);
+ FIXED_IO_mio : inout std_ulogic_vector (53 downto 0);
+ UserClkxCI : in std_ulogic;
+ UserResetxRANI : in std_ulogic;
+ -- Scalp Fast Router Registers
+ LocalNetAddrxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RGBLed0xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ RGBLed1xDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
+ -- RX
+ DMARXm2sxDI : in t_axi4m2s;
+ DMARXs2mxDO : out t_axi4s2m;
+ -- TX
+ DMATXm2sxDO : out t_axi4m2s;
+ DMATXs2mxDI : in t_axi4s2m;
+ -- Debug
+ -- West Phy
+ WestRXM2SxDI : in t_axi4m2s;
+ WestRXS2MxDI : in t_axi4s2m;
+ WestTXM2SxDI : in t_axi4m2s;
+ WestTXS2MxDI : in t_axi4s2m;
+ -- East Phy
+ EastRXM2SxDI : in t_axi4m2s;
+ EastRXS2MxDI : in t_axi4s2m;
+ EastTXM2SxDI : in t_axi4m2s;
+ EastTXS2MxDI : in t_axi4s2m;
+ -- Local NoC
+ LocalRXM2SxDI : in t_axi4m2s;
+ LocalRXS2MxDI : in t_axi4s2m;
+ LocalTXM2SxDI : in t_axi4m2s;
+ LocalTXS2MxDI : in t_axi4s2m);
end scalp_zynqps_wrapper;
architecture arch of scalp_zynqps_wrapper is
+ -- Internal signals
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+
begin
ScalpZynqPSxI : entity work.scalp_zynqps
port map (
- DDR_addr => DDR_addr,
- DDR_ba => DDR_ba,
- DDR_cas_n => DDR_cas_n,
- DDR_ck_n => DDR_ck_n,
- DDR_ck_p => DDR_ck_p,
- DDR_cke => DDR_cke,
- DDR_cs_n => DDR_cs_n,
- DDR_dm => DDR_dm,
- DDR_dq => DDR_dq,
- DDR_dqs_n => DDR_dqs_n,
- DDR_dqs_p => DDR_dqs_p,
- DDR_odt => DDR_odt,
- DDR_ras_n => DDR_ras_n,
- DDR_reset_n => DDR_reset_n,
- DDR_we_n => DDR_we_n,
- FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
- FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
- FIXED_IO_mio => FIXED_IO_mio,
- FIXED_IO_ps_clk => FIXED_IO_ps_clk,
- FIXED_IO_ps_porb => FIXED_IO_ps_porb,
- FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
- FclkClk0xCO => FclkClk0xCO,
- FclkReset0xRO(0) => FclkReset0xRO,
- Spi1MOSIxSO => Spi1MOSIxSO,
- Spi1SSxSO => Spi1SSxSO,
- Spi1SclkxCO => Spi1SclkxCO,
- Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
- UserClkxCI => UserClkxCI,
- UserResetxRANI => UserResetxRANI);
+ DDR_addr => DDR_addr,
+ DDR_ba => DDR_ba,
+ DDR_cas_n => DDR_cas_n,
+ DDR_ck_n => DDR_ck_n,
+ DDR_ck_p => DDR_ck_p,
+ DDR_cke => DDR_cke,
+ DDR_cs_n => DDR_cs_n,
+ DDR_dm => DDR_dm,
+ DDR_dq => DDR_dq,
+ DDR_dqs_n => DDR_dqs_n,
+ DDR_dqs_p => DDR_dqs_p,
+ DDR_odt => DDR_odt,
+ DDR_ras_n => DDR_ras_n,
+ DDR_reset_n => DDR_reset_n,
+ DDR_we_n => DDR_we_n,
+ FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
+ FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
+ FIXED_IO_mio => FIXED_IO_mio,
+ FIXED_IO_ps_clk => FIXED_IO_ps_clk,
+ FIXED_IO_ps_porb => FIXED_IO_ps_porb,
+ FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
+ FclkClk0xCO => FclkClk0xCO,
+ FclkReset0xRO(0) => FclkReset0xRO,
+ Spi1MOSIxSO => Spi1MOSIxSO,
+ Spi1SSxSO => Spi1SSxSO,
+ Spi1SclkxCO => Spi1SclkxCO,
+ Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
+ UserClkxCI => UserClkxCI,
+ UserResetxRANI => UserResetxRANI,
+ LocalNetAddrxDO => LocalNetAddrxDO,
+ RGBLed0xDO => RGBLed0xDO,
+ RGBLed1xDO => RGBLed1xDO,
+ -- AXIS
+ -- DMA
+ DMARXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => DMARXm2sxDI.DataxD,
+ DMARXxDI_tlast => DMARXm2sxDI.LastxS,
+ DMARXxDI_tready => DMARXs2mxDO.ReadyxS,
+ DMARXxDI_tvalid => DMARXm2sxDI.ValidxS,
+ DMATXxDO_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => DMATXm2sxDO.DataxD,
+ DMATXxDO_tlast => DMATXm2sxDO.LastxS,
+ DMATXxDO_tready => DMATXs2mxDI.ReadyxS,
+ DMATXxDO_tvalid => DMATXm2sxDO.ValidxS,
+ -- Debug PHY
+ -- West
+ WestRXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => WestRXM2SxDI.DataxD,
+ WestRXxDI_tlast => WestRXM2SxDI.LastxS,
+ WestRXxDI_tready => WestRXS2MxDI.ReadyxS,
+ WestRXxDI_tvalid => WestRXM2SxDI.ValidxS,
+ WestTXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => WestTXM2SxDI.DataxD,
+ WestTXxDI_tlast => WestTXM2SxDI.LastxS,
+ WestTXxDI_tready => WestTXS2MxDI.ReadyxS,
+ WestTXxDI_tvalid => WestTXM2SxDI.ValidxS,
+ -- East
+ EastRXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => EastRXM2SxDI.DataxD,
+ EastRXxDI_tlast => EastRXM2SxDI.LastxS,
+ EastRXxDI_tready => EastRXS2MxDI.ReadyxS,
+ EastRXxDI_tvalid => EastRXM2SxDI.ValidxS,
+ EastTXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => EastTXM2SxDI.DataxD,
+ EastTXxDI_tlast => EastTXM2SxDI.LastxS,
+ EastTXxDI_tready => EastTXS2MxDI.ReadyxS,
+ EastTXxDI_tvalid => EastTXM2SxDI.ValidxS,
+ -- Local
+ LocalRXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => LocalRXM2SxDI.DataxD,
+ LocalRXxDI_tlast => LocalRXM2SxDI.LastxS,
+ LocalRXxDI_tready => LocalRXS2MxDI.ReadyxS,
+ LocalRXxDI_tvalid => LocalRXM2SxDI.ValidxS,
+ LocalTXxDI_tdata((C_AXI4_DATA_SIZE - 1) downto 0) => LocalTXM2SxDI.DataxD,
+ LocalTXxDI_tlast => LocalTXM2SxDI.LastxS,
+ LocalTXxDI_tready => LocalTXS2MxDI.ReadyxS,
+ LocalTXxDI_tvalid => LocalTXM2SxDI.ValidxS);
end arch;
diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index 497ac7183698d70fe44b03c96101bd325b418092..71852844cb4b629e96b66d13cb5b07b602acc647 100644
--- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -124,10 +124,12 @@ if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_dma:7.1\
-xilinx.com:ip:axis_data_fifo:2.0\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
+hepia.hesge.ch:user:scalp_dma_fifo:1.0\
+hepia.hesge.ch:user:scalp_fast_router_registers:1.0\
+xilinx.com:ip:system_ila:1.1\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
xilinx.com:ip:xlconcat:2.1\
@@ -196,8 +198,57 @@ proc create_root_design { parentCell } {
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
+ set DMARXxDI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMARXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ CONFIG.HAS_TKEEP {0} \
+ CONFIG.HAS_TLAST {1} \
+ CONFIG.HAS_TREADY {1} \
+ CONFIG.HAS_TSTRB {0} \
+ CONFIG.LAYERED_METADATA {undef} \
+ CONFIG.TDATA_NUM_BYTES {4} \
+ CONFIG.TDEST_WIDTH {0} \
+ CONFIG.TID_WIDTH {0} \
+ CONFIG.TUSER_WIDTH {0} \
+ ] $DMARXxDI
+
+ set DMATXxDO [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMATXxDO ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $DMATXxDO
+
+ set EastRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 EastRXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $EastRXxDI
+
+ set EastTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 EastTXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $EastTXxDI
+
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
+ set LocalRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 LocalRXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $LocalRXxDI
+
+ set LocalTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 LocalTXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $LocalTXxDI
+
+ set WestRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 WestRXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $WestRXxDI
+
+ set WestTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 WestTXxDI ]
+ set_property -dict [ list \
+ CONFIG.FREQ_HZ {125000000} \
+ ] $WestTXxDI
+
# Create ports
set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
@@ -205,11 +256,17 @@ proc create_root_design { parentCell } {
CONFIG.FREQ_HZ {125000000} \
] $FclkClk0xCO
set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
+ set LocalNetAddrxDO [ create_bd_port -dir O -from 31 -to 0 -type data LocalNetAddrxDO ]
+ set RGBLed0xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed0xDO ]
+ set RGBLed1xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed1xDO ]
set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
set UserClkxCI [ create_bd_port -dir I -type clk -freq_hz 125000000 UserClkxCI ]
+ set_property -dict [ list \
+ CONFIG.ASSOCIATED_BUSIF {DMATXxDO:DMARXxDI:EastTXxDI:WestRXxDI:WestTXxDI:EastRXxDI:LocalTXxDI:LocalRXxDI} \
+ ] $UserClkxCI
set UserResetxRANI [ create_bd_port -dir I -type rst UserResetxRANI ]
# Create instance: axi_clock_converter_0, and set properties
@@ -221,6 +278,9 @@ proc create_root_design { parentCell } {
# Create instance: axi_clock_converter_2, and set properties
set axi_clock_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_2 ]
+ # Create instance: axi_clock_converter_3, and set properties
+ set axi_clock_converter_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_3 ]
+
# Create instance: axi_dma_0, and set properties
set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
set_property -dict [ list \
@@ -235,21 +295,18 @@ proc create_root_design { parentCell } {
CONFIG.NUM_SI {2} \
] $axi_interconnect_0
- # Create instance: axis_data_fifo_0, and set properties
- set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ # Create instance: gnd_constant_0, and set properties
+ set gnd_constant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_0 ]
set_property -dict [ list \
- CONFIG.ENABLE_ECC {0} \
- CONFIG.FIFO_DEPTH {4096} \
- CONFIG.FIFO_MEMORY_TYPE {block} \
- CONFIG.HAS_RD_DATA_COUNT {1} \
- CONFIG.HAS_WR_DATA_COUNT {1} \
- ] $axis_data_fifo_0
-
- # Create instance: gnd_constant, and set properties
- set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
+ CONFIG.CONST_VAL {0} \
+ ] $gnd_constant_0
+
+ # Create instance: gnd_constant_1, and set properties
+ set gnd_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_1 ]
set_property -dict [ list \
CONFIG.CONST_VAL {0} \
- ] $gnd_constant
+ CONFIG.CONST_WIDTH {30} \
+ ] $gnd_constant_1
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
@@ -698,12 +755,57 @@ proc create_root_design { parentCell } {
# Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \
- CONFIG.NUM_MI {1} \
+ CONFIG.NUM_MI {2} \
] $ps7_0_axi_periph
# Create instance: rst_ps7_0_125M, and set properties
set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
+ # Create instance: scalp_dma_fifo_rx_0, and set properties
+ set scalp_dma_fifo_rx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_rx_0 ]
+
+ # Create instance: scalp_dma_fifo_tx_0, and set properties
+ set scalp_dma_fifo_tx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_tx_0 ]
+
+ # Create instance: scalp_fast_router_registers_0, and set properties
+ set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.0 scalp_fast_router_registers_0 ]
+
+ # Create instance: system_ila_0, and set properties
+ set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
+ set_property -dict [ list \
+ CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
+ CONFIG.C_ADV_TRIGGER {true} \
+ CONFIG.C_BRAM_CNT {3} \
+ CONFIG.C_EN_STRG_QUAL {1} \
+ CONFIG.C_MON_TYPE {MIX} \
+ CONFIG.C_NUM_MONITOR_SLOTS {8} \
+ CONFIG.C_NUM_OF_PROBES {9} \
+ CONFIG.C_PROBE0_MU_CNT {2} \
+ CONFIG.C_PROBE1_MU_CNT {2} \
+ CONFIG.C_PROBE2_MU_CNT {2} \
+ CONFIG.C_PROBE3_MU_CNT {2} \
+ CONFIG.C_PROBE4_MU_CNT {2} \
+ CONFIG.C_PROBE5_MU_CNT {2} \
+ CONFIG.C_PROBE6_MU_CNT {2} \
+ CONFIG.C_PROBE7_MU_CNT {2} \
+ CONFIG.C_PROBE8_MU_CNT {2} \
+ CONFIG.C_SLOT {7} \
+ CONFIG.C_SLOT_0_APC_EN {0} \
+ CONFIG.C_SLOT_0_AXI_DATA_SEL {1} \
+ CONFIG.C_SLOT_0_AXI_TRIG_SEL {1} \
+ CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_1_APC_EN {0} \
+ CONFIG.C_SLOT_1_AXI_DATA_SEL {1} \
+ CONFIG.C_SLOT_1_AXI_TRIG_SEL {1} \
+ CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_6_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ CONFIG.C_SLOT_7_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ ] $system_ila_0
+
# Create instance: util_vector_logic_0, and set properties
set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
set_property -dict [ list \
@@ -729,43 +831,99 @@ proc create_root_design { parentCell } {
# Create instance: xlconcat_0, and set properties
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+ set_property -dict [ list \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.NUM_PORTS {2} \
+ ] $xlconcat_0
+
+ # Create instance: xlconcat_1, and set properties
+ set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
+ set_property -dict [ list \
+ CONFIG.IN2_WIDTH {30} \
+ CONFIG.NUM_PORTS {3} \
+ ] $xlconcat_1
+
+ # Create instance: xlconcat_2, and set properties
+ set xlconcat_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_2 ]
+ set_property -dict [ list \
+ CONFIG.IN2_WIDTH {30} \
+ CONFIG.NUM_PORTS {3} \
+ ] $xlconcat_2
# Create interface connections
+connect_bd_intf_net -intf_net Conn [get_bd_intf_ports EastRXxDI] [get_bd_intf_pins system_ila_0/SLOT_2_AXIS]
+connect_bd_intf_net -intf_net Conn1 [get_bd_intf_ports EastTXxDI] [get_bd_intf_pins system_ila_0/SLOT_3_AXIS]
+connect_bd_intf_net -intf_net Conn2 [get_bd_intf_ports WestRXxDI] [get_bd_intf_pins system_ila_0/SLOT_4_AXIS]
+connect_bd_intf_net -intf_net Conn3 [get_bd_intf_ports WestTXxDI] [get_bd_intf_pins system_ila_0/SLOT_5_AXIS]
+connect_bd_intf_net -intf_net Conn4 [get_bd_intf_ports LocalRXxDI] [get_bd_intf_pins system_ila_0/SLOT_6_AXIS]
+connect_bd_intf_net -intf_net Conn5 [get_bd_intf_ports LocalTXxDI] [get_bd_intf_pins system_ila_0/SLOT_7_AXIS]
+ connect_bd_intf_net -intf_net DMARXxDI_1 [get_bd_intf_ports DMARXxDI] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMARXxDI]
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_dma_0/S_AXI_LITE]
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_2_M_AXI [get_bd_intf_pins axi_clock_converter_2/M_AXI] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
- connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
+ connect_bd_intf_net -intf_net axi_clock_converter_3_M_AXI [get_bd_intf_pins axi_clock_converter_3/M_AXI] [get_bd_intf_pins scalp_fast_router_registers_0/SAxiLitexDIO]
+ connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMARXxDI]
+connect_bd_intf_net -intf_net [get_bd_intf_nets axi_dma_0_M_AXIS_MM2S] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMARXxDI] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets axi_dma_0_M_AXIS_MM2S]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_MM2S]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_clock_converter_2/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_S2MM]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
- connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_clock_converter_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
+ connect_bd_intf_net -intf_net scalp_dma_fifo_rx_0_DMATXxDO [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMATXxDO]
+connect_bd_intf_net -intf_net [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMATXxDO] [get_bd_intf_pins system_ila_0/SLOT_1_AXIS]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO]
+ connect_bd_intf_net -intf_net scalp_dma_fifo_tx_0_DMATXxDO [get_bd_intf_ports DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMATXxDO]
# Create port connections
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
- connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins axi_clock_converter_2/s_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk]
- connect_bd_net -net UserResetxRANI_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins axi_clock_converter_2/s_axi_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn]
+ connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins axi_clock_converter_2/s_axi_aclk] [get_bd_pins axi_clock_converter_3/m_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins scalp_dma_fifo_rx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_rx_0/TXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/TXClkxCI] [get_bd_pins scalp_fast_router_registers_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk]
+ connect_bd_net -net UserResetxRANI_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins axi_clock_converter_2/s_axi_aresetn] [get_bd_pins axi_clock_converter_3/m_axi_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins scalp_dma_fifo_rx_0/RXRstxRANI] [get_bd_pins scalp_dma_fifo_tx_0/RXRstxRANI] [get_bd_pins scalp_fast_router_registers_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn]
connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0]
connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1]
- connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_clock_converter_2/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins vio_0/clk]
+ connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant_0/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_clock_converter_2/m_axi_aclk] [get_bd_pins axi_clock_converter_3/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
- connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_clock_converter_2/m_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_clock_converter_2/m_axi_aresetn] [get_bd_pins axi_clock_converter_3/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn]
+ connect_bd_net -net scalp_dma_fifo_rx_0_ProgEmptyxSO [get_bd_pins scalp_dma_fifo_rx_0/ProgEmptyxSO] [get_bd_pins system_ila_0/probe2] [get_bd_pins xlconcat_2/In0]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_ProgEmptyxSO]
+ connect_bd_net -net scalp_dma_fifo_rx_0_ProgFullxSO [get_bd_pins scalp_dma_fifo_rx_0/ProgFullxSO] [get_bd_pins system_ila_0/probe3] [get_bd_pins xlconcat_2/In1]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_ProgFullxSO]
+ connect_bd_net -net scalp_dma_fifo_rx_0_RdDataCntxDO [get_bd_pins scalp_dma_fifo_rx_0/RdDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXRrDataCntxDI] [get_bd_pins system_ila_0/probe1]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_RdDataCntxDO]
+ connect_bd_net -net scalp_dma_fifo_rx_0_WrDataCntxDO [get_bd_pins scalp_dma_fifo_rx_0/WrDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXWrDataCntxDI] [get_bd_pins system_ila_0/probe0]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_WrDataCntxDO]
+ connect_bd_net -net scalp_dma_fifo_tx_0_ProgEmptyxSO [get_bd_pins scalp_dma_fifo_tx_0/ProgEmptyxSO] [get_bd_pins system_ila_0/probe6] [get_bd_pins xlconcat_1/In0]
+ connect_bd_net -net scalp_dma_fifo_tx_0_ProgFullxSO [get_bd_pins scalp_dma_fifo_tx_0/ProgFullxSO] [get_bd_pins system_ila_0/probe7] [get_bd_pins xlconcat_1/In1]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_ProgFullxSO]
+ connect_bd_net -net scalp_dma_fifo_tx_0_RdDataCntxDO [get_bd_pins scalp_dma_fifo_tx_0/RdDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXRrDataCntxDI] [get_bd_pins system_ila_0/probe5]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_RdDataCntxDO]
+ connect_bd_net -net scalp_dma_fifo_tx_0_WrDataCntxDO [get_bd_pins scalp_dma_fifo_tx_0/WrDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXWrDataCntxDI] [get_bd_pins system_ila_0/probe4]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_WrDataCntxDO]
+ connect_bd_net -net scalp_fast_router_re_0_RGBLed0xDO [get_bd_ports RGBLed0xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed0xDO]
+ connect_bd_net -net scalp_fast_router_re_0_RGBLed1xDO [get_bd_ports RGBLed1xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed1xDO]
+ connect_bd_net -net scalp_fast_router_registers_0_LocalNetAddrxDO [get_bd_ports LocalNetAddrxDO] [get_bd_pins scalp_fast_router_registers_0/LocalNetAddrxDO]
connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
- connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins system_ila_0/probe8] [get_bd_pins xlconcat_0/dout]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets xlconcat_0_dout]
+ connect_bd_net -net xlconcat_1_dout [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXStatusxDI] [get_bd_pins xlconcat_1/dout]
+ connect_bd_net -net xlconcat_2_dout [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXStatusxDI] [get_bd_pins xlconcat_2/dout]
+ connect_bd_net -net xlconstant_0_dout [get_bd_pins gnd_constant_1/dout] [get_bd_pins xlconcat_1/In2] [get_bd_pins xlconcat_2/In2]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
assign_bd_address -offset 0x40400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
+ assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_fast_router_registers_0/SAxiLitexDIO/reg0] -force
# Restore current instance
diff --git a/tools/config/scalp_dma_fifo.json b/tools/config/scalp_dma_fifo.json
new file mode 100644
index 0000000000000000000000000000000000000000..e421fa40fa9ba77beaefdccd3ef86ab7850ebf77
--- /dev/null
+++ b/tools/config/scalp_dma_fifo.json
@@ -0,0 +1,37 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch"
+ },
+ "project" : {
+ "name" : "scalp_dma_fifo",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "IPS",
+ "vivado_version" : "2020.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+ },
+ "components" : {
+ "packages" : {
+ "aurora_status_pkg" : {
+ "enable" : "true"
+ },
+ "axi4_pkg" : {
+ "enable" : "true"
+ }
+ },
+ "ips" : {
+ "scalp_dma_fifo" :
+ {
+ "hdl" : "enable",
+ "xci" : {
+ "axis_data_fifo" : "enable"
+ }
+ }
+ }
+ }
+}
diff --git a/tools/config/scalp_fast_router_registers.json b/tools/config/scalp_fast_router_registers.json
new file mode 100644
index 0000000000000000000000000000000000000000..fb6fdaf61048042855dc0479030d60ebc5052981
--- /dev/null
+++ b/tools/config/scalp_fast_router_registers.json
@@ -0,0 +1,18 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch"
+ },
+ "project" : {
+ "name" : "scalp_fast_router_registers",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "IPS",
+ "vivado_version" : "2020.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+ }
+}
\ No newline at end of file