diff --git a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
index 7828142648d569601bf98a8c26de85d8e6c0fac7..7f6d7347688a0b178bece5eb880d044e9629e2d6 100644
--- a/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
+++ b/designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
@@ -305,14 +305,14 @@ architecture arch of scalp_mipi is
signal GPIO0OxD : std_logic_vector(31 downto 0) := (others => '0');
signal GPIO0TxD : std_logic_vector(31 downto 0) := (others => '0');
-- Camera MIPI signals
--- signal MipiPhyClockHsNxC : std_logic := '0';
--- signal MipiPhyClockHsPxC : std_logic := '0';
--- signal MipiPhyClockLpNxC : std_logic := '0';
--- signal MipiPhyClockLpPxC : std_logic := '0';
--- signal MipiPhyDataHsNxD : std_logic_vector(1 downto 0) := (others => '0');
--- signal MipiPhyDataHsPxD : std_logic_vector(1 downto 0) := (others => '0');
--- signal MipiPhyDataLpNxD : std_logic_vector(1 downto 0) := (others => '0');
--- signal MipiPhyDataLpPxD : std_logic_vector(1 downto 0) := (others => '0');
+ signal MipiClockHsNxC : std_logic := '0';
+ signal MipiClockHsPxC : std_logic := '0';
+ signal MipiClockLpNxC : std_logic := '0';
+ signal MipiClockLpPxC : std_logic := '0';
+ signal MipiDataHsNxD : std_logic_vector(1 downto 0) := (others => '0');
+ signal MipiDataHsPxD : std_logic_vector(1 downto 0) := (others => '0');
+ signal MipiDataLpNxD : std_logic_vector(1 downto 0) := (others => '0');
+ signal MipiDataLpPxD : std_logic_vector(1 downto 0) := (others => '0');
-- Attributes
@@ -402,16 +402,16 @@ begin
-- Zynq GPIO0 interface
GPIO0xDI => GPIO0IxD,
GPIO0xDO => GPIO0OxD,
- GPIO0xDT => GPIO0TxD
+ GPIO0xDT => GPIO0TxD,
-- MIPI interface
--- MipiPhyClockHsN => MipiPhyClockHsNxC,
--- MipiPhyClockHsP => MipiPhyClockHsPxC,
--- MipiPhyClockLpN => MipiPhyClockLpNxC,
--- MipiPhyClockLpP => MipiPhyClockLpPxC,
--- MipiPhyDataHsN => MipiPhyDataHsNxD,
--- MipiPhyDataHsP => MipiPhyDataHsPxD,
--- MipiPhyDataLpN => MipiPhyDataLpNxD,
--- MipiPhyDataLpP => MipiPhyDataLpPxD
+ MipiClockHsN => MipiClockHsNxC,
+ MipiClockHsP => MipiClockHsPxC,
+ MipiClockLpN => MipiClockLpNxC,
+ MipiClockLpP => MipiClockLpPxC,
+ MipiDataHsN => MipiDataHsNxD,
+ MipiDataHsP => MipiDataHsPxD,
+ MipiDataLpN => MipiDataLpNxD,
+ MipiDataLpP => MipiDataLpPxD
);
end block ProcessingSystemxB;
@@ -446,18 +446,18 @@ begin
LVDS2V5Bottom6PxSIO <= GPIO0OxD(5) when GPIO0TxD(5)='0' else 'Z';
GPIO0IxD(5) <= LVDS2V5Bottom6PxSIO;
-- MIPI signal assignement
--- MipiPhyClockHsNxAS : MipiPhyClockHsNxC <= Clk2V5BottomNxCI;
--- MipiPhyClockHsPxAS : MipiPhyClockHsPxC <= Clk2V5BottomPxCI;
--- MipiPhyClockLpNxAS : MipiPhyClockLpNxC <= LVDS2V5Bottom4NxSIO;
--- MipiPhyClockLpPxAS : MipiPhyClockLpPxC <= LVDS2V5Bottom4PxSIO;
--- MipiPhyDataHsN0xAS : MipiPhyDataHsNxD(0) <= LVDS2V5Bottom0NxSIO;
--- MipiPhyDataHsP0xAS : MipiPhyDataHsPxD(0) <= LVDS2V5Bottom0PxSIO;
--- MipiPhyDataLpN0xAS : MipiPhyDataLpNxD(0) <= LVDS2V5Bottom1NxSIO;
--- MipiPhyDataLpP0xAS : MipiPhyDataLpPxD(0) <= LVDS2V5Bottom1PxSIO;
--- MipiPhyDataHsN1xAS : MipiPhyDataHsNxD(1) <= LVDS2V5Bottom2NxSIO;
--- MipiPhyDataHsP1xAS : MipiPhyDataHsPxD(1) <= LVDS2V5Bottom2PxSIO;
--- MipiPhyDataLpN1xAS : MipiPhyDataLpNxD(1) <= LVDS2V5Bottom3NxSIO;
--- MipiPhyDataLpP1xAS : MipiPhyDataLpPxD(1) <= LVDS2V5Bottom3PxSIO;
+ MipiPhyClockHsNxAS : MipiClockHsNxC <= Clk2V5BottomNxCI;
+ MipiPhyClockHsPxAS : MipiClockHsPxC <= Clk2V5BottomPxCI;
+ MipiPhyClockLpNxAS : MipiClockLpNxC <= LVDS2V5Bottom4NxSIO;
+ MipiPhyClockLpPxAS : MipiClockLpPxC <= LVDS2V5Bottom4PxSIO;
+ MipiPhyDataHsN0xAS : MipiDataHsNxD(0) <= LVDS2V5Bottom0NxSIO;
+ MipiPhyDataHsP0xAS : MipiDataHsPxD(0) <= LVDS2V5Bottom0PxSIO;
+ MipiPhyDataLpN0xAS : MipiDataLpNxD(0) <= LVDS2V5Bottom1NxSIO;
+ MipiPhyDataLpP0xAS : MipiDataLpPxD(0) <= LVDS2V5Bottom1PxSIO;
+ MipiPhyDataHsN1xAS : MipiDataHsNxD(1) <= LVDS2V5Bottom2NxSIO;
+ MipiPhyDataHsP1xAS : MipiDataHsPxD(1) <= LVDS2V5Bottom2PxSIO;
+ MipiPhyDataLpN1xAS : MipiDataLpNxD(1) <= LVDS2V5Bottom3NxSIO;
+ MipiPhyDataLpP1xAS : MipiDataLpPxD(1) <= LVDS2V5Bottom3PxSIO;
end block EntityIOxB;
diff --git a/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
index bcb29727bc9407bb73f3f78c56f190fb14a06beb..87d84c4235fc15ef6700c576737409ea3766245f 100644
--- a/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
@@ -78,16 +78,16 @@ entity scalp_mipi_zynqps_wrapper is
-- GPIO0 interface
GPIO0xDI : in std_logic_vector (31 downto 0);
GPIO0xDO : out std_logic_vector (31 downto 0);
- GPIO0xDT : out std_logic_vector (31 downto 0)
+ GPIO0xDT : out std_logic_vector (31 downto 0);
-- MIPI interface
--- MipiPhyClockHsN : in std_logic;
--- MipiPhyClockHsP : in std_logic;
--- MipiPhyClockLpN : in std_logic;
--- MipiPhyClockLpP : in std_logic;
--- MipiPhyDataHsN : in std_logic_vector (1 downto 0);
--- MipiPhyDataHsP : in std_logic_vector (1 downto 0);
--- MipiPhyDataLpN : in std_logic_vector (1 downto 0);
--- MipiPhyDataLpP : in std_logic_vector (1 downto 0)
+ MipiClockHsN : in std_logic;
+ MipiClockHsP : in std_logic;
+ MipiClockLpN : in std_logic;
+ MipiClockLpP : in std_logic;
+ MipiDataHsN : in std_logic_vector (1 downto 0);
+ MipiDataHsP : in std_logic_vector (1 downto 0);
+ MipiDataLpN : in std_logic_vector (1 downto 0);
+ MipiDataLpP : in std_logic_vector (1 downto 0)
);
end scalp_mipi_zynqps_wrapper;
@@ -141,15 +141,15 @@ begin
I2C1_SCL_T => I2c1SclxST,
GPIO_0_TRI_I => GPIO0xDI,
GPIO_0_TRI_O => GPIO0xDO,
- GPIO_0_TRI_T => GPIO0xDT
--- MipiPhyClockHsN => MipiPhyClockHsN,
--- MipiPhyClockHsP => MipiPhyClockHsP,
--- MipiPhyClockLpN => MipiPhyClockLpN,
--- MipiPhyClockLpP => MipiPhyClockLpP,
--- MipiPhyDataHsN => MipiPhyDataHsN,
--- MipiPhyDataHsP => MipiPhyDataHsP,
--- MipiPhyDataLpN => MipiPhyDataLpN,
--- MipiPhyDataLpP => MipiPhyDataLpP
+ GPIO_0_TRI_T => GPIO0xDT,
+ MIPI_clk_hs_n => MipiClockHsN,
+ MIPI_clk_hs_p => MipiClockHsP,
+ MIPI_clk_lp_n => MipiClockLpN,
+ MIPI_clk_lp_p => MipiClockLpP,
+ MIPI_data_hs_n => MipiDataHsN,
+ MIPI_data_hs_p => MipiDataHsP,
+ MIPI_data_lp_n => MipiDataLpN,
+ MIPI_data_lp_p => MipiDataLpP
);
end arch;
diff --git a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
index 6a972d434ec2e2af0071fc0554db5d0eaa998639..07839b7084a54ccc947a04968b0dad4796bbba4f 100644
--- a/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
@@ -122,14 +122,18 @@ set bCheckIPsPassed 1
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
+xilinx.com:ip:axis_subset_converter:1.1\
+xilinx.com:ip:clk_wiz:6.0\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:mipi_csi2_rx_subsystem:5.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
hepia.hesge.ch:user:scalp_axi4lite:1.2\
hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\
xilinx.com:ip:system_ila:1.1\
xilinx.com:ip:util_vector_logic:2.0\
+xilinx.com:ip:v_frmbuf_wr:2.2\
xilinx.com:ip:vio:3.0\
"
@@ -202,6 +206,8 @@ proc create_root_design { parentCell } {
set I2C1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C1 ]
+ set MIPI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:mipi_phy_rtl:1.0 MIPI ]
+
# Create ports
set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
@@ -222,6 +228,59 @@ proc create_root_design { parentCell } {
set WrDataxDO [ create_bd_port -dir O -from 31 -to 0 WrDataxDO ]
set WrValidxSO [ create_bd_port -dir O WrValidxSO ]
+ # Create instance: axi_mem_intercon, and set properties
+ set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {1} \
+ ] $axi_mem_intercon
+
+ # Create instance: axis_subset_converter_0, and set properties
+ set axis_subset_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_0 ]
+ set_property -dict [ list \
+ CONFIG.M_HAS_TKEEP {1} \
+ CONFIG.M_HAS_TLAST {1} \
+ CONFIG.M_HAS_TREADY {1} \
+ CONFIG.M_HAS_TSTRB {1} \
+ CONFIG.M_TDATA_NUM_BYTES {6} \
+ CONFIG.M_TDEST_WIDTH {1} \
+ CONFIG.M_TID_WIDTH {1} \
+ CONFIG.M_TUSER_WIDTH {1} \
+ CONFIG.S_HAS_TLAST {1} \
+ CONFIG.S_TDATA_NUM_BYTES {2} \
+ CONFIG.S_TDEST_WIDTH {10} \
+ CONFIG.S_TUSER_WIDTH {1} \
+ CONFIG.TDATA_REMAP {32'b00000000000000000000000000000000,tdata[15:0]} \
+ CONFIG.TDEST_REMAP {tdest[0:0]} \
+ CONFIG.TKEEP_REMAP {6'b111111} \
+ CONFIG.TLAST_REMAP {tlast[0]} \
+ CONFIG.TSTRB_REMAP {6'b111111} \
+ CONFIG.TUSER_REMAP {tuser[0:0]} \
+ ] $axis_subset_converter_0
+
+ # Create instance: clk_wiz_0, and set properties
+ set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+ set_property -dict [ list \
+ CONFIG.CLKOUT1_DRIVES {BUFG} \
+ CONFIG.CLKOUT1_JITTER {109.241} \
+ CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
+ CONFIG.CLKOUT2_DRIVES {BUFG} \
+ CONFIG.CLKOUT3_DRIVES {BUFG} \
+ CONFIG.CLKOUT4_DRIVES {BUFG} \
+ CONFIG.CLKOUT5_DRIVES {BUFG} \
+ CONFIG.CLKOUT6_DRIVES {BUFG} \
+ CONFIG.CLKOUT7_DRIVES {BUFG} \
+ CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \
+ CONFIG.MMCM_CLKFBOUT_MULT_F {8} \
+ CONFIG.MMCM_CLKOUT0_DIVIDE_F {5} \
+ CONFIG.MMCM_COMPENSATION {BUF_IN} \
+ CONFIG.OVERRIDE_MMCM {true} \
+ CONFIG.PRIMITIVE {PLL} \
+ CONFIG.RESET_PORT {resetn} \
+ CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ CONFIG.USE_LOCKED {false} \
+ ] $clk_wiz_0
+
# Create instance: gnd_constant, and set properties
set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
set_property -dict [ list \
@@ -234,6 +293,14 @@ proc create_root_design { parentCell } {
CONFIG.NUM_PORTS {1} \
] $irq_xlconcat
+ # Create instance: mipi_csi2_rx_subsyst_0, and set properties
+ set mipi_csi2_rx_subsyst_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mipi_csi2_rx_subsystem:5.1 mipi_csi2_rx_subsyst_0 ]
+ set_property -dict [ list \
+ CONFIG.CMN_NUM_LANES {2} \
+ CONFIG.CMN_PXL_FORMAT {YUV422_8bit} \
+ CONFIG.C_DPHY_LANES {2} \
+ ] $mipi_csi2_rx_subsyst_0
+
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
@@ -684,13 +751,16 @@ proc create_root_design { parentCell } {
CONFIG.PCW_USB_RESET_ENABLE {1} \
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
- CONFIG.PCW_USE_S_AXI_GP0 {0} \
+ CONFIG.PCW_USE_S_AXI_GP0 {1} \
+ CONFIG.PCW_USE_S_AXI_HP0 {0} \
+ CONFIG.PCW_USE_S_AXI_HP3 {0} \
] $processing_system7_0
# Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \
- CONFIG.NUM_MI {2} \
+ CONFIG.NUM_MI {4} \
+ CONFIG.NUM_SI {2} \
] $ps7_0_axi_periph
# Create instance: rst_ps7_0_125M, and set properties
@@ -706,11 +776,15 @@ proc create_root_design { parentCell } {
set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
set_property -dict [ list \
CONFIG.C_MON_TYPE {INTERFACE} \
- CONFIG.C_NUM_MONITOR_SLOTS {2} \
+ CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:gpio_rtl:1.0} \
CONFIG.C_SLOT_0_TYPE {0} \
CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:iic_rtl:1.0} \
CONFIG.C_SLOT_1_TYPE {0} \
+ CONFIG.C_SLOT_2_APC_EN {0} \
+ CONFIG.C_SLOT_2_AXI_DATA_SEL {1} \
+ CONFIG.C_SLOT_2_AXI_TRIG_SEL {1} \
+ CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
] $system_ila_0
# Create instance: util_vector_logic_0, and set properties
@@ -729,6 +803,23 @@ proc create_root_design { parentCell } {
CONFIG.LOGO_FILE {data/sym_notgate.png} \
] $util_vector_logic_1
+ # Create instance: v_frmbuf_wr_0, and set properties
+ set v_frmbuf_wr_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_frmbuf_wr:2.2 v_frmbuf_wr_0 ]
+ set_property -dict [ list \
+ CONFIG.AXIMM_ADDR_WIDTH {32} \
+ CONFIG.AXIMM_DATA_WIDTH {128} \
+ CONFIG.C_M_AXI_MM_VIDEO_DATA_WIDTH {128} \
+ CONFIG.HAS_BGR8 {1} \
+ CONFIG.HAS_RGB8 {0} \
+ CONFIG.HAS_UYVY8 {1} \
+ CONFIG.HAS_YUYV8 {0} \
+ CONFIG.HAS_Y_UV8 {0} \
+ CONFIG.MAX_COLS {640} \
+ CONFIG.MAX_NR_PLANES {1} \
+ CONFIG.MAX_ROWS {480} \
+ CONFIG.SAMPLES_PER_CLOCK {2} \
+ ] $v_frmbuf_wr_0
+
# Create instance: vio_0, and set properties
set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ]
set_property -dict [ list \
@@ -737,6 +828,12 @@ proc create_root_design { parentCell } {
] $vio_0
# Create interface connections
+ connect_bd_intf_net -intf_net MIPI_1 [get_bd_intf_ports MIPI] [get_bd_intf_pins mipi_csi2_rx_subsyst_0/mipi_phy_if]
+ connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_mem_intercon/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_GP0]
+ connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins axis_subset_converter_0/M_AXIS] [get_bd_intf_pins v_frmbuf_wr_0/s_axis_video]
+ connect_bd_intf_net -intf_net mipi_csi2_rx_subsyst_0_video_out [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins mipi_csi2_rx_subsyst_0/video_out]
+connect_bd_intf_net -intf_net [get_bd_intf_nets mipi_csi2_rx_subsyst_0_video_out] [get_bd_intf_pins axis_subset_converter_0/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_2_AXIS]
+ set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets mipi_csi2_rx_subsyst_0_video_out]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
@@ -748,19 +845,23 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins mipi_csi2_rx_subsyst_0/csirxss_s_axi] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins v_frmbuf_wr_0/s_axi_CTRL]
+ connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
# Create port connections
connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
connect_bd_net -net RdDataxDI_0_1 [get_bd_ports RdDataxDI] [get_bd_pins scalp_axi4lite_0/RdDataxDI]
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
+ connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mipi_csi2_rx_subsyst_0/dphy_clk_200M]
connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins vio_0/clk]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins ps7_0_axi_periph/S01_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
- connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axis_subset_converter_0/aresetn] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins ps7_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO]
connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
@@ -773,8 +874,19 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
# Create address segments
+ assign_bd_address -offset 0x43C20000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg] -force
assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr] -force
assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
+ assign_bd_address -offset 0x43C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs v_frmbuf_wr_0/s_axi_CTRL/Reg] -force
+ assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM] -force
+ assign_bd_address -offset 0xFC000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR] -force
+
+ # Exclude Address Segments
+ exclude_bd_addr_seg -offset 0x43C20000 -range 0x00001000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg]
+ exclude_bd_addr_seg -offset 0xE0000000 -range 0x00400000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_IOP]
+ exclude_bd_addr_seg -offset 0x40000000 -range 0x02000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_M_AXI_GP0]
+ exclude_bd_addr_seg -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr]
+ exclude_bd_addr_seg -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr]
# Restore current instance