From f32cc0b15a22cd190f1b492d7466858fc3e89647 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Mon, 5 Jul 2021 10:13:49 +0200
Subject: [PATCH] Update scalp_router_firmware for testing.
---
.../2020.2/src/constrs/debug.xdc | 158 ------------
.../2020.2/src/constrs/scalp_firmware.xdc | 1 +
.../2020.2/src/constrs/timing_constraints.xdc | 1 +
.../2020.2/src/hdl/scalp_router_firmware.vhd | 242 +++++++++++-------
ips/hw/scalp_router_regbank/component.xml | 102 +++++++-
.../src/hdl/scalp_router_regbank.vhd | 64 +++--
.../xgui/scalp_router_regbank_v0_4.tcl | 145 +++++++++++
.../xgui/scalp_router_regbank_v0_5.tcl | 145 +++++++++++
.../xgui/scalp_router_regbank_v0_6.tcl | 145 +++++++++++
.../xgui/scalp_router_regbank_v0_7.tcl | 145 +++++++++++
.../xgui/scalp_router_regbank_v0_8.tcl | 145 +++++++++++
.../src/hdl/scalp_zynqps_wrapper.vhd | 6 +-
.../.scripts/scalp_zynqps/scalp_zynqps.bd | 12 +
.../.scripts/scalp_zynqps/scalp_zynqps.bxml | 11 +
.../.scripts/scalp_zynqps/ui/bd_bb8b562f.ui | 12 +
.../scalp_zynqps.cache/wt/webtalk_pa.xml | 51 ++++
.../scalp_zynqps.ip_user_files/README.txt | 1 +
.../lin64/scalp_zynqps/scalp_zynqps.xpr | 212 +++++++++++++++
.../2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl | 44 ++--
19 files changed, 1340 insertions(+), 302 deletions(-)
create mode 100644 ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_4.tcl
create mode 100644 ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_5.tcl
create mode 100644 ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_6.tcl
create mode 100644 ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_7.tcl
create mode 100644 ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_8.tcl
create mode 100644 soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
create mode 100644 soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml
create mode 100644 soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui
create mode 100644 soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml
create mode 100644 soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt
create mode 100644 soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc
index c75ddeb..e69de29 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc
@@ -1,158 +0,0 @@
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 32 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {TXAxism2sVectorxD[1][DataxD][31]} {TXAxism2sVectorxD[1][DataxD][30]} {TXAxism2sVectorxD[1][DataxD][29]} {TXAxism2sVectorxD[1][DataxD][28]} {TXAxism2sVectorxD[1][DataxD][27]} {TXAxism2sVectorxD[1][DataxD][26]} {TXAxism2sVectorxD[1][DataxD][25]} {TXAxism2sVectorxD[1][DataxD][24]} {TXAxism2sVectorxD[1][DataxD][23]} {TXAxism2sVectorxD[1][DataxD][22]} {TXAxism2sVectorxD[1][DataxD][21]} {TXAxism2sVectorxD[1][DataxD][20]} {TXAxism2sVectorxD[1][DataxD][19]} {TXAxism2sVectorxD[1][DataxD][18]} {TXAxism2sVectorxD[1][DataxD][17]} {TXAxism2sVectorxD[1][DataxD][16]} {TXAxism2sVectorxD[1][DataxD][15]} {TXAxism2sVectorxD[1][DataxD][14]} {TXAxism2sVectorxD[1][DataxD][13]} {TXAxism2sVectorxD[1][DataxD][12]} {TXAxism2sVectorxD[1][DataxD][11]} {TXAxism2sVectorxD[1][DataxD][10]} {TXAxism2sVectorxD[1][DataxD][9]} {TXAxism2sVectorxD[1][DataxD][8]} {TXAxism2sVectorxD[1][DataxD][7]} {TXAxism2sVectorxD[1][DataxD][6]} {TXAxism2sVectorxD[1][DataxD][5]} {TXAxism2sVectorxD[1][DataxD][4]} {TXAxism2sVectorxD[1][DataxD][3]} {TXAxism2sVectorxD[1][DataxD][2]} {TXAxism2sVectorxD[1][DataxD][1]} {TXAxism2sVectorxD[1][DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 32 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {TXAxism2sVectorxD[2][DataxD][31]} {TXAxism2sVectorxD[2][DataxD][30]} {TXAxism2sVectorxD[2][DataxD][29]} {TXAxism2sVectorxD[2][DataxD][28]} {TXAxism2sVectorxD[2][DataxD][27]} {TXAxism2sVectorxD[2][DataxD][26]} {TXAxism2sVectorxD[2][DataxD][25]} {TXAxism2sVectorxD[2][DataxD][24]} {TXAxism2sVectorxD[2][DataxD][23]} {TXAxism2sVectorxD[2][DataxD][22]} {TXAxism2sVectorxD[2][DataxD][21]} {TXAxism2sVectorxD[2][DataxD][20]} {TXAxism2sVectorxD[2][DataxD][19]} {TXAxism2sVectorxD[2][DataxD][18]} {TXAxism2sVectorxD[2][DataxD][17]} {TXAxism2sVectorxD[2][DataxD][16]} {TXAxism2sVectorxD[2][DataxD][15]} {TXAxism2sVectorxD[2][DataxD][14]} {TXAxism2sVectorxD[2][DataxD][13]} {TXAxism2sVectorxD[2][DataxD][12]} {TXAxism2sVectorxD[2][DataxD][11]} {TXAxism2sVectorxD[2][DataxD][10]} {TXAxism2sVectorxD[2][DataxD][9]} {TXAxism2sVectorxD[2][DataxD][8]} {TXAxism2sVectorxD[2][DataxD][7]} {TXAxism2sVectorxD[2][DataxD][6]} {TXAxism2sVectorxD[2][DataxD][5]} {TXAxism2sVectorxD[2][DataxD][4]} {TXAxism2sVectorxD[2][DataxD][3]} {TXAxism2sVectorxD[2][DataxD][2]} {TXAxism2sVectorxD[2][DataxD][1]} {TXAxism2sVectorxD[2][DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 32 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {TXAxism2sVectorxD[0][DataxD][31]} {TXAxism2sVectorxD[0][DataxD][30]} {TXAxism2sVectorxD[0][DataxD][29]} {TXAxism2sVectorxD[0][DataxD][28]} {TXAxism2sVectorxD[0][DataxD][27]} {TXAxism2sVectorxD[0][DataxD][26]} {TXAxism2sVectorxD[0][DataxD][25]} {TXAxism2sVectorxD[0][DataxD][24]} {TXAxism2sVectorxD[0][DataxD][23]} {TXAxism2sVectorxD[0][DataxD][22]} {TXAxism2sVectorxD[0][DataxD][21]} {TXAxism2sVectorxD[0][DataxD][20]} {TXAxism2sVectorxD[0][DataxD][19]} {TXAxism2sVectorxD[0][DataxD][18]} {TXAxism2sVectorxD[0][DataxD][17]} {TXAxism2sVectorxD[0][DataxD][16]} {TXAxism2sVectorxD[0][DataxD][15]} {TXAxism2sVectorxD[0][DataxD][14]} {TXAxism2sVectorxD[0][DataxD][13]} {TXAxism2sVectorxD[0][DataxD][12]} {TXAxism2sVectorxD[0][DataxD][11]} {TXAxism2sVectorxD[0][DataxD][10]} {TXAxism2sVectorxD[0][DataxD][9]} {TXAxism2sVectorxD[0][DataxD][8]} {TXAxism2sVectorxD[0][DataxD][7]} {TXAxism2sVectorxD[0][DataxD][6]} {TXAxism2sVectorxD[0][DataxD][5]} {TXAxism2sVectorxD[0][DataxD][4]} {TXAxism2sVectorxD[0][DataxD][3]} {TXAxism2sVectorxD[0][DataxD][2]} {TXAxism2sVectorxD[0][DataxD][1]} {TXAxism2sVectorxD[0][DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {TXAxism2sVectorxD[3][DataxD][31]} {TXAxism2sVectorxD[3][DataxD][30]} {TXAxism2sVectorxD[3][DataxD][29]} {TXAxism2sVectorxD[3][DataxD][28]} {TXAxism2sVectorxD[3][DataxD][27]} {TXAxism2sVectorxD[3][DataxD][26]} {TXAxism2sVectorxD[3][DataxD][25]} {TXAxism2sVectorxD[3][DataxD][24]} {TXAxism2sVectorxD[3][DataxD][23]} {TXAxism2sVectorxD[3][DataxD][22]} {TXAxism2sVectorxD[3][DataxD][21]} {TXAxism2sVectorxD[3][DataxD][20]} {TXAxism2sVectorxD[3][DataxD][19]} {TXAxism2sVectorxD[3][DataxD][18]} {TXAxism2sVectorxD[3][DataxD][17]} {TXAxism2sVectorxD[3][DataxD][16]} {TXAxism2sVectorxD[3][DataxD][15]} {TXAxism2sVectorxD[3][DataxD][14]} {TXAxism2sVectorxD[3][DataxD][13]} {TXAxism2sVectorxD[3][DataxD][12]} {TXAxism2sVectorxD[3][DataxD][11]} {TXAxism2sVectorxD[3][DataxD][10]} {TXAxism2sVectorxD[3][DataxD][9]} {TXAxism2sVectorxD[3][DataxD][8]} {TXAxism2sVectorxD[3][DataxD][7]} {TXAxism2sVectorxD[3][DataxD][6]} {TXAxism2sVectorxD[3][DataxD][5]} {TXAxism2sVectorxD[3][DataxD][4]} {TXAxism2sVectorxD[3][DataxD][3]} {TXAxism2sVectorxD[3][DataxD][2]} {TXAxism2sVectorxD[3][DataxD][1]} {TXAxism2sVectorxD[3][DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 32 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {TXAxism2sVectorxD[4][DataxD][31]} {TXAxism2sVectorxD[4][DataxD][30]} {TXAxism2sVectorxD[4][DataxD][29]} {TXAxism2sVectorxD[4][DataxD][28]} {TXAxism2sVectorxD[4][DataxD][27]} {TXAxism2sVectorxD[4][DataxD][26]} {TXAxism2sVectorxD[4][DataxD][25]} {TXAxism2sVectorxD[4][DataxD][24]} {TXAxism2sVectorxD[4][DataxD][23]} {TXAxism2sVectorxD[4][DataxD][22]} {TXAxism2sVectorxD[4][DataxD][21]} {TXAxism2sVectorxD[4][DataxD][20]} {TXAxism2sVectorxD[4][DataxD][19]} {TXAxism2sVectorxD[4][DataxD][18]} {TXAxism2sVectorxD[4][DataxD][17]} {TXAxism2sVectorxD[4][DataxD][16]} {TXAxism2sVectorxD[4][DataxD][15]} {TXAxism2sVectorxD[4][DataxD][14]} {TXAxism2sVectorxD[4][DataxD][13]} {TXAxism2sVectorxD[4][DataxD][12]} {TXAxism2sVectorxD[4][DataxD][11]} {TXAxism2sVectorxD[4][DataxD][10]} {TXAxism2sVectorxD[4][DataxD][9]} {TXAxism2sVectorxD[4][DataxD][8]} {TXAxism2sVectorxD[4][DataxD][7]} {TXAxism2sVectorxD[4][DataxD][6]} {TXAxism2sVectorxD[4][DataxD][5]} {TXAxism2sVectorxD[4][DataxD][4]} {TXAxism2sVectorxD[4][DataxD][3]} {TXAxism2sVectorxD[4][DataxD][2]} {TXAxism2sVectorxD[4][DataxD][1]} {TXAxism2sVectorxD[4][DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
-set_property port_width 32 [get_debug_ports u_ila_0/probe5]
-connect_debug_port u_ila_0/probe5 [get_nets [list {TXAxism2sVectorxD[5][DataxD][31]} {TXAxism2sVectorxD[5][DataxD][30]} {TXAxism2sVectorxD[5][DataxD][29]} {TXAxism2sVectorxD[5][DataxD][28]} {TXAxism2sVectorxD[5][DataxD][27]} {TXAxism2sVectorxD[5][DataxD][26]} {TXAxism2sVectorxD[5][DataxD][25]} {TXAxism2sVectorxD[5][DataxD][24]} {TXAxism2sVectorxD[5][DataxD][23]} {TXAxism2sVectorxD[5][DataxD][22]} {TXAxism2sVectorxD[5][DataxD][21]} {TXAxism2sVectorxD[5][DataxD][20]} {TXAxism2sVectorxD[5][DataxD][19]} {TXAxism2sVectorxD[5][DataxD][18]} {TXAxism2sVectorxD[5][DataxD][17]} {TXAxism2sVectorxD[5][DataxD][16]} {TXAxism2sVectorxD[5][DataxD][15]} {TXAxism2sVectorxD[5][DataxD][14]} {TXAxism2sVectorxD[5][DataxD][13]} {TXAxism2sVectorxD[5][DataxD][12]} {TXAxism2sVectorxD[5][DataxD][11]} {TXAxism2sVectorxD[5][DataxD][10]} {TXAxism2sVectorxD[5][DataxD][9]} {TXAxism2sVectorxD[5][DataxD][8]} {TXAxism2sVectorxD[5][DataxD][7]} {TXAxism2sVectorxD[5][DataxD][6]} {TXAxism2sVectorxD[5][DataxD][5]} {TXAxism2sVectorxD[5][DataxD][4]} {TXAxism2sVectorxD[5][DataxD][3]} {TXAxism2sVectorxD[5][DataxD][2]} {TXAxism2sVectorxD[5][DataxD][1]} {TXAxism2sVectorxD[5][DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
-set_property port_width 32 [get_debug_ports u_ila_0/probe6]
-connect_debug_port u_ila_0/probe6 [get_nets [list {TXAxism2sVectorxD[6][DataxD][31]} {TXAxism2sVectorxD[6][DataxD][30]} {TXAxism2sVectorxD[6][DataxD][29]} {TXAxism2sVectorxD[6][DataxD][28]} {TXAxism2sVectorxD[6][DataxD][27]} {TXAxism2sVectorxD[6][DataxD][26]} {TXAxism2sVectorxD[6][DataxD][25]} {TXAxism2sVectorxD[6][DataxD][24]} {TXAxism2sVectorxD[6][DataxD][23]} {TXAxism2sVectorxD[6][DataxD][22]} {TXAxism2sVectorxD[6][DataxD][21]} {TXAxism2sVectorxD[6][DataxD][20]} {TXAxism2sVectorxD[6][DataxD][19]} {TXAxism2sVectorxD[6][DataxD][18]} {TXAxism2sVectorxD[6][DataxD][17]} {TXAxism2sVectorxD[6][DataxD][16]} {TXAxism2sVectorxD[6][DataxD][15]} {TXAxism2sVectorxD[6][DataxD][14]} {TXAxism2sVectorxD[6][DataxD][13]} {TXAxism2sVectorxD[6][DataxD][12]} {TXAxism2sVectorxD[6][DataxD][11]} {TXAxism2sVectorxD[6][DataxD][10]} {TXAxism2sVectorxD[6][DataxD][9]} {TXAxism2sVectorxD[6][DataxD][8]} {TXAxism2sVectorxD[6][DataxD][7]} {TXAxism2sVectorxD[6][DataxD][6]} {TXAxism2sVectorxD[6][DataxD][5]} {TXAxism2sVectorxD[6][DataxD][4]} {TXAxism2sVectorxD[6][DataxD][3]} {TXAxism2sVectorxD[6][DataxD][2]} {TXAxism2sVectorxD[6][DataxD][1]} {TXAxism2sVectorxD[6][DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
-set_property port_width 32 [get_debug_ports u_ila_0/probe7]
-connect_debug_port u_ila_0/probe7 [get_nets [list {WestRXM2SxD[DataxD][31]} {WestRXM2SxD[DataxD][30]} {WestRXM2SxD[DataxD][29]} {WestRXM2SxD[DataxD][28]} {WestRXM2SxD[DataxD][27]} {WestRXM2SxD[DataxD][26]} {WestRXM2SxD[DataxD][25]} {WestRXM2SxD[DataxD][24]} {WestRXM2SxD[DataxD][23]} {WestRXM2SxD[DataxD][22]} {WestRXM2SxD[DataxD][21]} {WestRXM2SxD[DataxD][20]} {WestRXM2SxD[DataxD][19]} {WestRXM2SxD[DataxD][18]} {WestRXM2SxD[DataxD][17]} {WestRXM2SxD[DataxD][16]} {WestRXM2SxD[DataxD][15]} {WestRXM2SxD[DataxD][14]} {WestRXM2SxD[DataxD][13]} {WestRXM2SxD[DataxD][12]} {WestRXM2SxD[DataxD][11]} {WestRXM2SxD[DataxD][10]} {WestRXM2SxD[DataxD][9]} {WestRXM2SxD[DataxD][8]} {WestRXM2SxD[DataxD][7]} {WestRXM2SxD[DataxD][6]} {WestRXM2SxD[DataxD][5]} {WestRXM2SxD[DataxD][4]} {WestRXM2SxD[DataxD][3]} {WestRXM2SxD[DataxD][2]} {WestRXM2SxD[DataxD][1]} {WestRXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-set_property port_width 32 [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][0]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
-set_property port_width 1 [get_debug_ports u_ila_0/probe9]
-connect_debug_port u_ila_0/probe9 [get_nets [list ScalpPacketValid12xS]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
-set_property port_width 1 [get_debug_ports u_ila_0/probe10]
-connect_debug_port u_ila_0/probe10 [get_nets [list {TXAxism2sVectorxD[0][LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
-set_property port_width 1 [get_debug_ports u_ila_0/probe11]
-connect_debug_port u_ila_0/probe11 [get_nets [list {TXAxism2sVectorxD[0][ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
-set_property port_width 1 [get_debug_ports u_ila_0/probe12]
-connect_debug_port u_ila_0/probe12 [get_nets [list {TXAxism2sVectorxD[1][LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
-set_property port_width 1 [get_debug_ports u_ila_0/probe13]
-connect_debug_port u_ila_0/probe13 [get_nets [list {TXAxism2sVectorxD[1][ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
-set_property port_width 1 [get_debug_ports u_ila_0/probe14]
-connect_debug_port u_ila_0/probe14 [get_nets [list {TXAxism2sVectorxD[2][LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
-set_property port_width 1 [get_debug_ports u_ila_0/probe15]
-connect_debug_port u_ila_0/probe15 [get_nets [list {TXAxism2sVectorxD[2][ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
-set_property port_width 1 [get_debug_ports u_ila_0/probe16]
-connect_debug_port u_ila_0/probe16 [get_nets [list {TXAxism2sVectorxD[3][LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
-set_property port_width 1 [get_debug_ports u_ila_0/probe17]
-connect_debug_port u_ila_0/probe17 [get_nets [list {TXAxism2sVectorxD[3][ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
-set_property port_width 1 [get_debug_ports u_ila_0/probe18]
-connect_debug_port u_ila_0/probe18 [get_nets [list {TXAxism2sVectorxD[4][LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
-set_property port_width 1 [get_debug_ports u_ila_0/probe19]
-connect_debug_port u_ila_0/probe19 [get_nets [list {TXAxism2sVectorxD[4][ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
-set_property port_width 1 [get_debug_ports u_ila_0/probe20]
-connect_debug_port u_ila_0/probe20 [get_nets [list {TXAxism2sVectorxD[5][LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
-set_property port_width 1 [get_debug_ports u_ila_0/probe21]
-connect_debug_port u_ila_0/probe21 [get_nets [list {TXAxism2sVectorxD[5][ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
-set_property port_width 1 [get_debug_ports u_ila_0/probe22]
-connect_debug_port u_ila_0/probe22 [get_nets [list {TXAxism2sVectorxD[6][LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
-set_property port_width 1 [get_debug_ports u_ila_0/probe23]
-connect_debug_port u_ila_0/probe23 [get_nets [list {TXAxism2sVectorxD[6][ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
-set_property port_width 1 [get_debug_ports u_ila_0/probe24]
-connect_debug_port u_ila_0/probe24 [get_nets [list {TXAxiss2mVectorxD[0][ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
-set_property port_width 1 [get_debug_ports u_ila_0/probe25]
-connect_debug_port u_ila_0/probe25 [get_nets [list {TXAxiss2mVectorxD[1][ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
-set_property port_width 1 [get_debug_ports u_ila_0/probe26]
-connect_debug_port u_ila_0/probe26 [get_nets [list {TXAxiss2mVectorxD[2][ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
-set_property port_width 1 [get_debug_ports u_ila_0/probe27]
-connect_debug_port u_ila_0/probe27 [get_nets [list {TXAxiss2mVectorxD[3][ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
-set_property port_width 1 [get_debug_ports u_ila_0/probe28]
-connect_debug_port u_ila_0/probe28 [get_nets [list {TXAxiss2mVectorxD[4][ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
-set_property port_width 1 [get_debug_ports u_ila_0/probe29]
-connect_debug_port u_ila_0/probe29 [get_nets [list {TXAxiss2mVectorxD[5][ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
-set_property port_width 1 [get_debug_ports u_ila_0/probe30]
-connect_debug_port u_ila_0/probe30 [get_nets [list {TXAxiss2mVectorxD[6][ReadyxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {WestRXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
-set_property port_width 1 [get_debug_ports u_ila_0/probe32]
-connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[LastxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
-set_property port_width 1 [get_debug_ports u_ila_0/probe33]
-connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
-set_property port_width 1 [get_debug_ports u_ila_0/probe34]
-connect_debug_port u_ila_0/probe34 [get_nets [list {WestRXM2SxD[ValidxS]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
-set_property port_width 1 [get_debug_ports u_ila_0/probe35]
-connect_debug_port u_ila_0/probe35 [get_nets [list {WestRXS2MxD[ReadyxS]}]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
index 876688b..ade029a 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
@@ -254,3 +254,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
index c646d10..ffd69f8 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -34,3 +34,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
+
diff --git a/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
index 2dd4c4e..539cbd5 100644
--- a/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
+++ b/designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_router_firmware
--
--- Last update: 2021-06-08
+-- Last update: 2021-06-29
--
---------------------------------------------------------------------------------
@@ -457,6 +457,7 @@ architecture arch of scalp_router_firmware is
signal TXFifoRXS2MxS : t_axi4s2m := C_NO_AXI4_S2M;
signal RXFifoTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal RXFifoTXS2MxS : t_axi4s2m := C_NO_AXI4_S2M;
+ signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Zynq Reg Bank
-- type t_status_send_word is (E_IDLE, E_SEND);
@@ -552,39 +553,61 @@ architecture arch of scalp_router_firmware is
signal DebugBackPressureResetxR : t_rx_back_pressure_reset := C_NO_RX_BACK_PRESSURE_RESET;
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
-- Clocks
- attribute keep of PSSysClkxC : signal is "true";
- attribute keep of GTRefClk0xC : signal is "true";
- attribute keep of GTRefClk1xC : signal is "true";
- attribute keep of AuroraClkSlavexC : signal is "true";
- attribute keep of AuroraClkMasterxC : signal is "true";
+ attribute keep of PSSysClkxC : signal is "true";
+ attribute keep of GTRefClk0xC : signal is "true";
+ attribute keep of GTRefClk1xC : signal is "true";
+ attribute keep of AuroraClkSlavexC : signal is "true";
+ attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
- -- attribute mark_debug of WestRXM2SxD : signal is "true";
- -- attribute keep of WestRXM2SxD : signal is "true";
- -- attribute mark_debug of WestRXS2MxD : signal is "true";
- -- attribute keep of WestRXS2MxD : signal is "true";
- -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
- -- attribute keep of TXAxism2sVectorxD : signal is "true";
- -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
- -- attribute keep of TXAxiss2mVectorxD : signal is "true";
- -- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
- -- attribute keep of RXAxism2sVectorxD : signal is "true";
- -- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
- -- attribute keep of RXAxiss2mVectorxD : signal is "true";
- -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
- -- attribute keep of TXAxism2sVectorxD : signal is "true";
- -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
- -- attribute keep of TXAxiss2mVectorxD : signal is "true";
- -- attribute mark_debug of : signal is "true";
- -- attribute keep of : signal is "true";
- -- attribute mark_debug of : signal is "true";
- -- attribute keep of : signal is "true";
- -- attribute mark_debug of : signal is "true";
- -- attribute keep of : signal is "true";
- -- attribute mark_debug of : signal is "true";
- -- attribute keep of : signal is "true";
+ attribute mark_debug of LocNetAddrxD : signal is "true";
+ attribute keep of LocNetAddrxD : signal is "true";
+ -- attribute mark_debug of RXFifoRdDataStatexD : signal is "true";
+ -- attribute keep of RXFifoRdDataStatexD : signal is "true";
+ attribute mark_debug of TXFifoWrDataStatexD : signal is "true";
+ attribute keep of TXFifoWrDataStatexD : signal is "true";
+ attribute mark_debug of ScalpPacketWriteDataxD : signal is "true";
+ attribute keep of ScalpPacketWriteDataxD : signal is "true";
+ attribute mark_debug of ScalpPacketReadDataxD : signal is "true";
+ attribute keep of ScalpPacketReadDataxD : signal is "true";
+ attribute mark_debug of ScalpPacketCtrlxD : signal is "true";
+ attribute keep of ScalpPacketCtrlxD : signal is "true";
+ attribute mark_debug of ScalpPacketStatusxD : signal is "true";
+ attribute keep of ScalpPacketStatusxD : signal is "true";
+ -- attribute mark_debug of RXRdDataCntxD : signal is "true";
+ -- attribute keep of RXRdDataCntxD : signal is "true";
+ -- attribute mark_debug of RXWrDataCntxD : signal is "true";
+ -- attribute keep of RXWrDataCntxD : signal is "true";
+ -- attribute mark_debug of TXRdDataCntxD : signal is "true";
+ -- attribute keep of TXRdDataCntxD : signal is "true";
+ -- attribute mark_debug of TXWrDataCntxD : signal is "true";
+ -- attribute keep of TXWrDataCntxD : signal is "true";
+ attribute mark_debug of LocNetAddrVectxD : signal is "true";
+ attribute keep of LocNetAddrVectxD : signal is "true";
+ -- attribute mark_debug of EastTXM2SxD : signal is "true";
+ -- attribute keep of EastTXS2MxD : signal is "true";
+ -- attribute mark_debug of WestRXM2SxD : signal is "true";
+ -- attribute keep of WestRXM2SxD : signal is "true";
+ -- attribute mark_debug of WestRXS2MxD : signal is "true";
+ -- attribute keep of WestRXS2MxD : signal is "true";
+ attribute mark_debug of TXFifoRXM2SxD : signal is "true";
+ attribute keep of TXFifoRXM2SxD : signal is "true";
+ attribute mark_debug of TXFifoRXS2MxS : signal is "true";
+ attribute keep of TXFifoRXS2MxS : signal is "true";
+ attribute mark_debug of RXAxism2sVectorxD : signal is "true";
+ attribute keep of RXAxism2sVectorxD : signal is "true";
+ attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
+ attribute keep of RXAxiss2mVectorxD : signal is "true";
+ attribute mark_debug of TXAxism2sVectorxD : signal is "true";
+ attribute keep of TXAxism2sVectorxD : signal is "true";
+ attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+ attribute keep of TXAxiss2mVectorxD : signal is "true";
+ attribute mark_debug of TXFifoWrDataStateNextxD : signal is "true";
+ attribute keep of TXFifoWrDataStateNextxD : signal is "true";
+ attribute mark_debug of ScalpRouterResetxRNA : signal is "true";
+ attribute keep of ScalpRouterResetxRNA : signal is "true";
begin
@@ -626,6 +649,8 @@ begin
Spi1SclkxCO => Pll2V5ClkuWirexCO,
-- MIO
FIXED_IO_mio => MIOxDIO,
+ UserClkxCI => AuroraClkMasterxC.UserClkxC,
+ UserResetxRANI => ScalpRouterResetxRNA,
-- Scalp Axi Lite interface and IRQ
Irq0xDI => (others => '0'),
ScalpPacketWriteDataxDO => ScalpPacketWriteDataxD,
@@ -917,12 +942,11 @@ begin
type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID_0, E_WR_SP_LAST_0, E_WR_SP_LAST_1, E_WR_SP_VALID_1, E_WR_SP_WAIT);
- signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Scalp Packets
-- From South 101
---------------------------------------------------------------------------
---------------------------------------------------------------------------
- signal ScalpPacketLocalxD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
+ signal ScalpPacketLocalxD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
(SpHeaderxD => C_SP_HEADER_NULL,
SpPayloadxD => C_SP_PAYLOAD_NULL);
signal ScalpPacketValidLocalxS : std_ulogic := '0';
@@ -932,38 +956,14 @@ begin
signal ScalpPacket0xD : t_scalp_packet(SpPayloadxD(0 to (C_SCALP_PACKET_PAYLOAD_SIZE - 1))) :=
(SpHeaderxD => C_SP_HEADER_110_TO_210,
SpPayloadxD => C_SP_PAYLOAD_0);
- signal ScalpPacketValid12xS : std_ulogic := '0';
+ signal ScalpPacketValid12xS : std_ulogic := '0';
--
- signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
- signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
- signal VioWrSpValidxS : std_ulogic := '0';
+ signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
+ signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
+ signal VioWrSpValidxS : std_ulogic := '0';
--
- signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
- signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
- -- Scalp Packet
- -- attribute mark_debug of ScalpPacket0xD : signal is "true";
- -- attribute keep of ScalpPacket0xD : signal is "true";
- -- attribute mark_debug of ScalpPacketValid12xS : signal is "true";
- -- attribute keep of ScalpPacketValid12xS : signal is "true";
- -- attribute mark_debug of ScalpPacketLocalxD : signal is "true";
- -- attribute keep of ScalpPacketLocalxD : signal is "true";
- -- VIO
- -- attribute mark_debug of VioWrSpValidxS : signal is "true";
- -- attribute keep of VioWrSpValidxS : signal is "true";
- -- attribute mark_debug of ScalpRouterResetxRNA : signal is "true";
- -- attribute keep of ScalpRouterResetxRNA : signal is "true";
- -- attribute mark_debug of ScalpPacket0xD : signal is "true";
- -- attribute keep of ScalpPacket0xD : signal is "true";
- -- attribute mark_debug of WrSPStatexDP : signal is "true";
- -- attribute keep of WrSPStatexDP : signal is "true";
- -- attribute mark_debug of WrSPStatexDN : signal is "true";
- -- attribute keep of WrSPStatexDN : signal is "true";
- -- attribute mark_debug of VioWrSpValidxS : signal is "true";
- -- attribute keep of VioWrSpValidxS : signal is "true";
- -- attribute mark_debug of ScalpPacketLocalxD : signal is "true";
- -- attribute keep of ScalpPacketLocalxD : signal is "true";
- -- attribute mark_debug of ScalpPacketValidLocalxS : signal is "true";
- -- attribute keep of ScalpPacketValidLocalxS : signal is "true";
+ signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
+ signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
begin -- block NetworkLayerxB
@@ -1101,27 +1101,62 @@ begin
-- Local Router Net Addr
-- LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_210;
- LocNetAddrXxAS : LocNetAddrxD.XxD <= to_integer(unsigned(LocNetAddrVectxD(7 downto 0)));
- LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocNetAddrVectxD(15 downto 8)));
- LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocNetAddrVectxD(23 downto 16)));
+ LocNetAddrXxAS : LocNetAddrxD.XxD <= to_integer(unsigned(LocNetAddrVectxD(7 downto 0)));
+ LocNetAddrYxAS : LocNetAddrxD.YxD <= to_integer(unsigned(LocNetAddrVectxD(15 downto 8)));
+ LocNetAddrZxAS : LocNetAddrxD.ZxD <= to_integer(unsigned(LocNetAddrVectxD(23 downto 16)));
+
+ -- LocNetAddrFFxG : for i in 0 to 7 generate
+
+ -- XxI : FDCE
+ -- generic map (
+ -- INIT => '0')
+ -- port map (
+ -- Q => LocNetAddrVectxDP(i),
+ -- C => AuroraClkMasterxC.UserClkxC,
+ -- CE => '1',
+ -- CLR => '0',
+ -- D => LocNetAddrVectxDN(i));
+
+ -- YxI : FDCE
+ -- generic map (
+ -- INIT => '0')
+ -- port map (
+ -- Q => LocNetAddrVectxDP(i + 8),
+ -- C => AuroraClkMasterxC.UserClkxC,
+ -- CE => '1',
+ -- CLR => '0',
+ -- D => LocNetAddrVectxDN(i + 8));
+
+ -- ZxI : FDCE
+ -- generic map (
+ -- INIT => '0')
+ -- port map (
+ -- Q => LocNetAddrVectxDP(i + 16),
+ -- C => AuroraClkMasterxC.UserClkxC,
+ -- CE => '1',
+ -- CLR => '0',
+ -- D => LocNetAddrVectxDN(i + 16));
+
+ -- end generate LocNetAddrFFxG;
+
-- TX Side
- NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
- EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID);
- SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID);
- WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID);
- NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD;
- EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
- SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
- WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
+ NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
+ EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID);
+ SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID);
+ WestTXM2SxAS : WestTXM2SxD <= TXAxism2sVectorxD(C_WEST_IF_ID);
+ NorthTXS2MxAS : TXAxiss2mVectorxD(C_NORTH_IF_ID) <= NorthTXS2MxD;
+ EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
+ SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
+ WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
-- RX Side
- NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
- EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
- SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
- WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD;
- NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID);
- EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID);
- SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
- WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
+ NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
+ EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
+ SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
+ WestRXM2SxAS : RXAxism2sVectorxD(C_WEST_IF_ID) <= WestRXM2SxD;
+ NorthRXS2MxAS : NorthRXS2MxD <= RXAxiss2mVectorxD(C_NORTH_IF_ID);
+ EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID);
+ SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
+ WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
WrSpValidxI : entity work.vio_axi_cnt_ctrl
port map (
@@ -1141,48 +1176,61 @@ begin
TXFifoWrDataStateNextxD <= E_WR_IDLE;
elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
-- Default Values
- TXFifoRXM2SxD <= C_NO_AXI4_M2S;
+ TXFifoRXM2SxD <= TXFifoRXM2SxD;
TXFifoWrDataStatexD <= TXFifoWrDataStatexD;
TXFifoWrDataStateNextxD <= TXFifoWrDataStateNextxD;
case TXFifoWrDataStatexD is
when E_WR_IDLE =>
+ TXFifoRXM2SxD.DataxD <= (others => '0');
+ TXFifoRXM2SxD.ValidxS <= '0';
+ TXFifoRXM2SxD.LastxS <= '0';
+
if ScalpPacketCtrlxD(C_WR_NEW_PACKET) = '1' then
TXFifoWrDataStatexD <= E_WR_H0;
end if;
when E_WR_H0 =>
+ TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD(31 downto 24) & ScalpPacketWriteDataxD(23 downto 16) &
+ ScalpPacketWriteDataxD(15 downto 8) & ScalpPacketWriteDataxD(7 downto 0));
+ TXFifoRXM2SxD.ValidxS <= '0';
+ TXFifoRXM2SxD.LastxS <= '0';
+
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
- TXFifoRXM2SxD.DataxD <= scalp_sp_h0_to_axis_ul(ScalpPacketWriteDataxD(31 downto 24),
- ScalpPacketWriteDataxD(23 downto 16),
- ScalpPacketWriteDataxD(15 downto 8),
- ScalpPacketWriteDataxD(7 downto 0));
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
TXFifoWrDataStateNextxD <= E_WR_H1;
end if;
when E_WR_H1 =>
+ TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD(31 downto 24) & ScalpPacketWriteDataxD(23 downto 16) &
+ ScalpPacketWriteDataxD(15 downto 8) & "00000000");
+ TXFifoRXM2SxD.ValidxS <= '0';
+ TXFifoRXM2SxD.LastxS <= '0';
+
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
- TXFifoRXM2SxD.DataxD <= scalp_sp_h1_to_axis_ul(ScalpPacketWriteDataxD(31 downto 24),
- ScalpPacketWriteDataxD(23 downto 16),
- ScalpPacketWriteDataxD(15 downto 8));
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
TXFifoWrDataStateNextxD <= E_WR_H2;
end if;
when E_WR_H2 =>
+ TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD(31 downto 16) & "0000000000000000");
+ TXFifoRXM2SxD.ValidxS <= '0';
+ TXFifoRXM2SxD.LastxS <= '0';
+
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
- TXFifoRXM2SxD.DataxD <= scalp_sp_h2_to_axis_ul(ScalpPacketWriteDataxD(31 downto 16));
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
TXFifoWrDataStateNextxD <= E_WR_PLD;
end if;
when E_WR_PLD =>
+ TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD);
+ TXFifoRXM2SxD.ValidxS <= '0';
+ TXFifoRXM2SxD.LastxS <= '0';
+
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
- TXFifoRXM2SxD.DataxD <= scalp_sp_p_to_axis_ul(ScalpPacketWriteDataxD);
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
@@ -1195,6 +1243,10 @@ begin
end if;
when E_WR_NEXT =>
+ TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD);
+ TXFifoRXM2SxD.ValidxS <= '0';
+ TXFifoRXM2SxD.LastxS <= '0';
+
if ScalpPacketCtrlxD(C_WR_NEXT) = '1' and ScalpPacketCtrlxD(C_WR_VALID) = '0' then
TXFifoWrDataStatexD <= TXFifoWrDataStateNextxD;
end if;
@@ -1248,7 +1300,7 @@ begin
when E_RD_WORD =>
if RXFifoTXM2SxD.ValidxS = '1' and ScalpPacketCtrlxD(C_RD_NEXT) = '0' then
RXFifoTXS2MxS.ReadyxS <= '1';
- ScalpPacketReadDataxD <= TXFifoRXM2SxD.DataxD;
+ ScalpPacketReadDataxD <= RXFifoTXM2SxD.DataxD;
ScalpPacketStatusxD(C_RD_VALID) <= '1';
RXFifoRdDataStatexD <= E_RD_NEXT;
RXFifoRdDataStateNextxD <= E_RD_WORD;
@@ -1260,7 +1312,7 @@ begin
end if;
when E_RD_NEXT =>
- ScalpPacketReadDataxD <= TXFifoRXM2SxD.DataxD;
+ ScalpPacketReadDataxD <= RXFifoTXM2SxD.DataxD;
ScalpPacketStatusxD(C_RD_VALID) <= '1';
ScalpPacketStatusxD(C_RD_WAIT_NEXT) <= '1';
diff --git a/ips/hw/scalp_router_regbank/component.xml b/ips/hw/scalp_router_regbank/component.xml
index d61eaf0..b7041e5 100644
--- a/ips/hw/scalp_router_regbank/component.xml
+++ b/ips/hw/scalp_router_regbank/component.xml
@@ -3,7 +3,7 @@
<spirit:vendor>hepia.hesge.ch</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>scalp_router_regbank</spirit:name>
- <spirit:version>0.3</spirit:version>
+ <spirit:version>0.8</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>SAxiClkxCI</spirit:name>
@@ -412,7 +412,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>178324ad</spirit:value>
+ <spirit:value>7a280e8f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -428,7 +428,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>178324ad</spirit:value>
+ <spirit:value>7a280e8f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -931,7 +931,7 @@
<spirit:file>
<spirit:name>src/hdl/scalp_router_regbank.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_178324ad</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_7a280e8f</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -944,14 +944,14 @@
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>xgui/scalp_router_regbank_v0_3.tcl</spirit:name>
+ <spirit:name>xgui/scalp_router_regbank_v0_8.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_94c74469</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
- <spirit:description>scalp_router_regbank_v0_3</spirit:description>
+ <spirit:description>scalp_router_regbank_v0_8</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_AXI4_ARADDR_SIZE</spirit:name>
@@ -1031,11 +1031,11 @@
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>scalp_router_regbank_v0_3</xilinx:displayName>
+ <xilinx:displayName>scalp_router_regbank_v0_8</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:vendorDisplayName>Hepia</xilinx:vendorDisplayName>
- <xilinx:coreRevision>9</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2021-06-01T06:08:58Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>18</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2021-06-28T06:22:25Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@32291851_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@530043c9_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
@@ -1176,13 +1176,93 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@243b0175_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@505dafcd_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@95f3c1d_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4b12cc0b_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@38b6a293_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2fcaf07f_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@125ff332_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@28da8435_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@46cd0da9_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@10abff2c_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
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+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3338410d_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
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+ <xilinx:tag xilinx:name="ui.data.coregen.dd@20820806_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@15227339_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@133e77a3_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@624fea0_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4cd42682_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3379dca9_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@448f48e7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3830a06_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1ee0257b_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2200e2cb_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@753f648d_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2ec75d04_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@12a0bad8_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@375a49d7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7f8c7d1e_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@52defe61_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4f037fc3_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@b0126f5_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="43363bdc"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="210fbbb0"/>
- <xilinx:checksum xilinx:scope="ports" xilinx:value="1730a974"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8fbae063"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="6b6e9195"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d2e1fb7a"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="03a862ce"/>
</xilinx:packagingInfo>
diff --git a/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd b/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd
index 219aeba..b4df94a 100644
--- a/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd
+++ b/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd
@@ -118,6 +118,29 @@ architecture behavioral of scalp_router_regbank is
signal LocNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal LocNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ -- attribute mark_debug of : signal is "true";
+ -- attribute keep of : signal is "true";
+ attribute mark_debug of RdAddrxD : signal is "true";
+ attribute keep of RdAddrxD : signal is "true";
+ attribute mark_debug of RdDataxD : signal is "true";
+ attribute keep of RdDataxD : signal is "true";
+ attribute mark_debug of RdValidxS : signal is "true";
+ attribute keep of RdValidxS : signal is "true";
+ attribute mark_debug of WrAddrxD : signal is "true";
+ attribute keep of WrAddrxD : signal is "true";
+ attribute mark_debug of WrDataxD : signal is "true";
+ attribute keep of WrDataxD : signal is "true";
+ attribute mark_debug of WrValidxS : signal is "true";
+ attribute keep of WrValidxS : signal is "true";
+ attribute mark_debug of LocNetAddrPortxDN : signal is "true";
+ attribute keep of LocNetAddrPortxDN : signal is "true";
+ attribute mark_debug of LocNetAddrPortxDP : signal is "true";
+ attribute keep of LocNetAddrPortxDP : signal is "true";
+
begin
assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
@@ -136,26 +159,28 @@ begin
begin -- block EntityIOxB
-- Clock and reset
- SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
- SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
+ SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
+ SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
-- Read Channel
- SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
- SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
- SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
- RdValidxAS : RdValidxS <= SAxiARValidxSI;
- RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
- SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
+ SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
+ SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
+ SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
+ RdValidxAS : RdValidxS <= SAxiARValidxSI;
+ RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
+ SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
-- Write Channel
- SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
- SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
- SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
- SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
- WrValidxAS : WrValidxS <= SAxiWValidxSI;
- WrDataxAS : WrDataxD <= SAxiWDataxDI;
- WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
- WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
- SAxiAWValidxSI = '1' else
- WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
+ SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
+ SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
+ SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
+ SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
+ WrValidxAS : WrValidxS <= SAxiWValidxSI;
+ WrDataxAS : WrDataxD <= SAxiWDataxDI;
+ WrAddrOutxAS : WrAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0);
+ -- WrAddrOutxAS : WrAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when SAxiAWValidxSI = '1' else WrAddrxDP;
+ -- WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
+ WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when SAxiAWValidxSI = '1' else WrAddrxDP;
+ -- SAxiAWValidxSI = '1' else
+ -- WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
end block EntityIOxB;
@@ -297,14 +322,17 @@ begin
WrValidxS) is
begin -- process WriteRegPortxP
ScalpPacketWriteDataPortxDN <= ScalpPacketWriteDataPortxDP;
+ ScalpPacketWriteDataxDO <= ScalpPacketWriteDataPortxDP;
ScalpPacketReadDataPortxDN <= ScalpPacketReadDataxDI;
ScalpPacketCtrlPortxDN <= ScalpPacketCtrlPortxDP;
+ ScalpPacketCtrlxDO <= ScalpPacketCtrlPortxDP;
ScalpPacketStatusPortxDN <= ScalpPacketStatusxDI;
TXWrDataCntPortxDN <= TXWrDataCntxDI;
TXRdDataCntPortxDN <= TXRdDataCntxDI;
RXWrDataCntPortxDN <= RXWrDataCntxDI;
RXRdDataCntPortxDN <= RXRdDataCntxDI;
LocNetAddrPortxDN <= LocNetAddrPortxDP;
+ LocNetAddrxDO <= LocNetAddrPortxDP;
if WrValidxS = '1' then
case WrAddrxD is
diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_4.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_4.tcl
new file mode 100644
index 0000000..72aafc8
--- /dev/null
+++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_4.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_5.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_5.tcl
new file mode 100644
index 0000000..72aafc8
--- /dev/null
+++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_5.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_6.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_6.tcl
new file mode 100644
index 0000000..72aafc8
--- /dev/null
+++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_6.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_7.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_7.tcl
new file mode 100644
index 0000000..72aafc8
--- /dev/null
+++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_7.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_8.tcl b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_8.tcl
new file mode 100644
index 0000000..72aafc8
--- /dev/null
+++ b/ips/hw/scalp_router_regbank/xgui/scalp_router_regbank_v0_8.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
index 6f21398..61a94df 100644
--- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
--- Last update: 2021-06-01
+-- Last update: 2021-06-22
--
---------------------------------------------------------------------------------
@@ -59,6 +59,8 @@ entity scalp_zynqps_wrapper is
Spi1SclkxCO : out std_logic;
-- MIO
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
+ UserClkxCI : in std_logic;
+ UserResetxRANI : in std_logic;
-- Scalp Axi Lite interface and IRQ
Irq0xDI : in std_logic_vector(0 to 0);
ScalpPacketWriteDataxDO : out std_logic_vector(31 downto 0);
@@ -107,6 +109,8 @@ begin
Spi1SSxSO => Spi1SSxSO,
Spi1SclkxCO => Spi1SclkxCO,
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
+ UserClkxCI => UserClkxCI,
+ UserResetxRANI => UserResetxRANI,
Irq0xDI => Irq0xDI,
ScalpPacketWriteDataxDO => ScalpPacketWriteDataxDO,
ScalpPacketReadDataxDI => ScalpPacketReadDataxDI,
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
new file mode 100644
index 0000000..bd20046
--- /dev/null
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bd
@@ -0,0 +1,12 @@
+{
+ "design": {
+ "design_info": {
+ "boundary_crc": "0x0",
+ "name": "scalp_zynqps",
+ "rev_ctrl_bd_flag": "RevCtrlBdOff",
+ "synth_flow_mode": "Hierarchical",
+ "tool_version": "2020.2"
+ },
+ "design_tree": {}
+ }
+}
\ No newline at end of file
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml
new file mode 100644
index 0000000..55a1a7f
--- /dev/null
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/scalp_zynqps.bxml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root MajorVersion="0" MinorVersion="39">
+ <CompositeFile CompositeFileTopName="scalp_zynqps" CanBeSetAsTop="false" CanDisplayChildGraph="true">
+ <Description>Composite Fileset</Description>
+ <Generation Name="SYNTHESIS" State="STALE" Timestamp="1621502377"/>
+ <Generation Name="IMPLEMENTATION" State="STALE" Timestamp="1621502377"/>
+ <Generation Name="SIMULATION" State="STALE" Timestamp="1621502377"/>
+ <Generation Name="HW_HANDOFF" State="STALE" Timestamp="1621502377"/>
+ <FileCollection Name="SOURCES" Type="SOURCES"/>
+ </CompositeFile>
+</Root>
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui
new file mode 100644
index 0000000..a7ed182
--- /dev/null
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/.scripts/scalp_zynqps/ui/bd_bb8b562f.ui
@@ -0,0 +1,12 @@
+{
+ "ActiveEmotionalView":"Default View",
+ "Default View_ScaleFactor":"1.0",
+ "Default View_TopLeft":"-904,-445",
+ "ExpandedHierarchyInLayout":"",
+ "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
+# -string -flagsOSRD
+levelinfo -pg 1 0 10
+pagesize -pg 1 -db -bbox -sgen 0 0 10 10
+"
+}
+
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000..35a67b6
--- /dev/null
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.cache/wt/webtalk_pa.xml
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Thu May 20 11:21:29 2021">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="d9c1243eb87347ba8472aea5dee0b59a" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="EditDelete" value="1" type="JavaHandler"/>
+<property name="EnablePartialReconfigFlow" value="1" type="JavaHandler"/>
+<property name="ExitApp" value="1" type="JavaHandler"/>
+<property name="RunScript" value="2" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_OK" value="2" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="9" type="GuiHandlerData"/>
+<property name="MainMenuMgr_CHECKPOINT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_EXPORT" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="3" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TOOLS" value="6" type="GuiHandlerData"/>
+<property name="PACommandNames_AUTO_UPDATE_HIER" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_ENABLE_PARTIAL_RECONFIGURATION" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_EXIT" value="2" type="GuiHandlerData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
+<property name="RDICommands_CUSTOM_COMMANDS" value="1" type="GuiHandlerData"/>
+<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
+<property name="RDICommands_RUN_SCRIPT" value="2" type="GuiHandlerData"/>
+<property name="SrcMenu_IP_HIERARCHY" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="103" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="85" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr
new file mode 100644
index 0000000..24f1f2f
--- /dev/null
+++ b/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr
@@ -0,0 +1,212 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="54" Path="/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/soc/vivado/scalp_zynqps/2020.2/lin64/scalp_zynqps/scalp_zynqps.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="0c90be26454f431f93ef1e43b95f0fb5"/>
+ <Option Name="Part" Val="xc7z015clg485-2"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirIES" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirIES" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val="hepia-cores.ch:scalp_node:part0:0.1"/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPRepoPath" Val="$PPRDIR/../../../../../hw"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="DSABoardId" Val="scalp_node"/>
+ <Option Name="WTXSimLaunchSim" Val="0"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="0"/>
+ <Option Name="WTModelSimExportSim" Val="0"/>
+ <Option Name="WTQuestaExportSim" Val="0"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="0"/>
+ <Option Name="WTRivieraExportSim" Val="0"/>
+ <Option Name="WTActivehdlExportSim" Val="0"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../../../../../hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="scalp_zynqps_wrapper"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PPRDIR/../../../../../hw/scalp_zynqps/src/sim/tb_scalp_zynqps.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="scalp_zynqps_wrapper"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="IES">
+ <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="15">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z015clg485-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board>
+ <Jumpers/>
+ </Board>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>
diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index 0f74a82..664b83c 100644
--- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -122,11 +122,12 @@ set bCheckIPsPassed 1
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
+xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
-hepia.hesge.ch:user:scalp_router_regbank:0.3\
+hepia.hesge.ch:user:scalp_router_regbank:0.5\
hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
@@ -219,6 +220,11 @@ proc create_root_design { parentCell } {
set TXRdDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data TXRdDataCntxDI ]
set TXWrDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data TXWrDataCntxDI ]
set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
+ set UserClkxCI [ create_bd_port -dir I -type clk -freq_hz 125000000 UserClkxCI ]
+ set UserResetxRANI [ create_bd_port -dir I -type rst UserResetxRANI ]
+
+ # Create instance: axi_clock_converter_0, and set properties
+ set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: gnd_constant, and set properties
set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
@@ -684,11 +690,8 @@ proc create_root_design { parentCell } {
# Create instance: rst_ps7_0_125M, and set properties
set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
- # Create instance: scalp_router_regbank_1, and set properties
- set scalp_router_regbank_1 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:0.3 scalp_router_regbank_1 ]
- set_property -dict [ list \
- CONFIG.C_AXI4_ADDR_SIZE {8} \
- ] $scalp_router_regbank_1
+ # Create instance: scalp_router_regbank_0, and set properties
+ set scalp_router_regbank_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:0.5 scalp_router_regbank_0 ]
# Create instance: scalp_safe_firmware_0, and set properties
set scalp_safe_firmware_0 [ create_bd_cell -type ip -vlnv hepia.ch:user:scalp_safe_firmware_reg_bank:1.3 scalp_safe_firmware_0 ]
@@ -717,39 +720,42 @@ proc create_root_design { parentCell } {
] $vio_0
# Create interface connections
+ connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins scalp_router_regbank_0/SAxiLitexDIO]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
- connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_router_regbank_1/SAxiLitexDIO]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
# Create port connections
connect_bd_net -net In0_0_1 [get_bd_ports Irq0xDI] [get_bd_pins irq_xlconcat/In0]
- connect_bd_net -net RXRdDataCntxDI_0_1 [get_bd_ports RXRdDataCntxDI] [get_bd_pins scalp_router_regbank_1/RXRdDataCntxDI]
- connect_bd_net -net RXWrDataCntxDI_0_1 [get_bd_ports RXWrDataCntxDI] [get_bd_pins scalp_router_regbank_1/RXWrDataCntxDI]
- connect_bd_net -net ScalpPacketReadDataxDI_1 [get_bd_ports ScalpPacketReadDataxDI] [get_bd_pins scalp_router_regbank_1/ScalpPacketReadDataxDI]
- connect_bd_net -net ScalpPacketStatusxDI_1 [get_bd_ports ScalpPacketStatusxDI] [get_bd_pins scalp_router_regbank_1/ScalpPacketStatusxDI]
- connect_bd_net -net TXRdDataCntxDI_0_1 [get_bd_ports TXRdDataCntxDI] [get_bd_pins scalp_router_regbank_1/TXRdDataCntxDI]
- connect_bd_net -net TXWrDataCntxDI_0_1 [get_bd_ports TXWrDataCntxDI] [get_bd_pins scalp_router_regbank_1/TXWrDataCntxDI]
+ connect_bd_net -net RXRdDataCntxDI_1 [get_bd_ports RXRdDataCntxDI] [get_bd_pins scalp_router_regbank_0/RXRdDataCntxDI]
+ connect_bd_net -net RXWrDataCntxDI_1 [get_bd_ports RXWrDataCntxDI] [get_bd_pins scalp_router_regbank_0/RXWrDataCntxDI]
+ connect_bd_net -net ScalpPacketReadDataxDI_1 [get_bd_ports ScalpPacketReadDataxDI] [get_bd_pins scalp_router_regbank_0/ScalpPacketReadDataxDI]
+ connect_bd_net -net ScalpPacketStatusxDI_1 [get_bd_ports ScalpPacketStatusxDI] [get_bd_pins scalp_router_regbank_0/ScalpPacketStatusxDI]
+ connect_bd_net -net TXRdDataCntxDI_1 [get_bd_ports TXRdDataCntxDI] [get_bd_pins scalp_router_regbank_0/TXRdDataCntxDI]
+ connect_bd_net -net TXWrDataCntxDI_1 [get_bd_ports TXWrDataCntxDI] [get_bd_pins scalp_router_regbank_0/TXWrDataCntxDI]
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
+ connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins scalp_router_regbank_0/SAxiClkxCI]
+ connect_bd_net -net UserResetxRNA_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins scalp_router_regbank_0/SAxiRstxRANI]
connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_router_regbank_1/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins vio_0/clk]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
- connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_router_regbank_1/SAxiRstxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI]
- connect_bd_net -net scalp_router_regbank_1_LocNetAddrxDO [get_bd_ports LocNetAddrxDO] [get_bd_pins scalp_router_regbank_1/LocNetAddrxDO]
- connect_bd_net -net scalp_router_regbank_1_ScalpPacketCtrlxDO [get_bd_ports ScalpPacketCtrlxDO] [get_bd_pins scalp_router_regbank_1/ScalpPacketCtrlxDO]
- connect_bd_net -net scalp_router_regbank_1_ScalpPacketWriteDataxDO [get_bd_ports ScalpPacketWriteDataxDO] [get_bd_pins scalp_router_regbank_1/ScalpPacketWriteDataxDO]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI]
+ connect_bd_net -net scalp_router_regbank_0_LocNetAddrxDO [get_bd_ports LocNetAddrxDO] [get_bd_pins scalp_router_regbank_0/LocNetAddrxDO]
+ connect_bd_net -net scalp_router_regbank_0_ScalpPacketCtrlxDO [get_bd_ports ScalpPacketCtrlxDO] [get_bd_pins scalp_router_regbank_0/ScalpPacketCtrlxDO]
+ connect_bd_net -net scalp_router_regbank_0_ScalpPacketWriteDataxDO [get_bd_ports ScalpPacketWriteDataxDO] [get_bd_pins scalp_router_regbank_0/ScalpPacketWriteDataxDO]
connect_bd_net -net scalp_safe_firmware_0_RgbLedsCtrlPortxDO [get_bd_ports RgbLedsCtrlPortxDO] [get_bd_pins scalp_safe_firmware_0/RgbLedsCtrlPortxDO]
connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
# Create address segments
- assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_router_regbank_1/SAxiLitexDIO/Reg] -force
+ assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_router_regbank_0/SAxiLitexDIO/Reg] -force
assign_bd_address -offset 0x43C10000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
--
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