From f79b72798453a31d1305c92337311dff72d4a785 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Mon, 17 May 2021 10:27:43 +0200
Subject: [PATCH] Update Double Fifo Register

---
 .../scalp_firmware/2020.2/lin64/.gitignore    |   23 +
 .../2020.2/lin64/.scripts/.prompt_colors.tcl  |   38 +-
 .../.scripts/clean_prj_scalp_firmware.sh      |    7 +-
 .../.scripts/create_prj_scalp_firmware.sh     |    2 +-
 .../.scripts/create_prj_scalp_firmware.tcl    |  134 +-
 .../.scripts/export_hw_scalp_firmware.sh      |    4 +-
 .../.scripts/export_hw_scalp_firmware.tcl     |   23 +-
 .../.scripts/gen_bitstream_scalp_firmware.sh  |    2 +-
 .../.scripts/gen_bitstream_scalp_firmware.tcl |    2 +-
 .../.scripts/gen_sw_apps_scalp_firmware.tcl   |   74 -
 .../.scripts/load_bitstream_scalp_firmware.sh |    2 +-
 .../load_bitstream_scalp_firmware.tcl         |    2 +-
 .../.scripts/load_sw_app_scalp_firmware.tcl   |   64 -
 .../lin64/.scripts/open_prj_scalp_firmware.sh |    4 +-
 .../2020.2/lin64/.scripts/utils.tcl           |    2 +-
 .../2020.2/lin64/.scripts/vivado_pid24324.str | 3890 +++++++++++++++++
 .../scalp_firmware/2020.2/lin64/setup.sh      |    4 +-
 .../2020.2/src/constrs/debug.xdc              |  206 +
 .../2020.2/src/constrs/scalp_firmware.xdc     |    1 +
 .../2020.2/src/constrs/timing_constraints.xdc |    1 +
 .../2020.2/src/hdl/scalp_firmware.vhd         |  134 +-
 .../2020.2/src/sim/tb_scalp_firmware.vhd      |    2 +-
 .../2020.2/src/sw/.scripts/.prompt_colors.tcl |   47 +
 .../sw/.scripts/clean_sdk_scalp_firmware.sh}  |   19 +-
 .../.scripts/gen_sw_apps_scalp_firmware.sh}   |    9 +-
 .../.scripts/gen_sw_apps_scalp_firmware.tcl   |  101 +
 .../sw/.scripts/open_sdk_scalp_firmware.sh    |   25 +
 .../2020.2/src/sw/.scripts/utils.tcl          |   62 +
 .../scalp_firmware/2020.2/src/sw/setup.sh     |   27 +
 .../src/inc/scalp_firmware_app.h              |   48 +
 .../src/scalp_firmware_app.c                  |   60 +
 .../2020.2/src/constrs/debug.xdc              |   13 +-
 .../src/constrs/scalp_user_firmware.xdc       |    1 +
 .../2020.2/src/constrs/timing_constraints.xdc |    1 +
 .../scalp_router/src/hdl/scalp_axis_to_sp.vhd |    4 +-
 .../src/hdl/scalp_fifo_double_register.vhd    |   45 +-
 ips/hw/scalp_router/src/hdl/scalp_misc.vhd    |   10 +-
 .../src/hdl/scalp_router_interface.vhd        |   26 +-
 ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd |   53 +-
 ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd |   79 +-
 .../src/hdl/scalp_rx_link_layer.vhd           |   34 +
 .../src/sim/tb_scalp_rx_link_layer.vhd        |   34 +
 .../2020.2/lin64/.gitignore                   |   23 +
 .../2020.2/lin64/.scripts/.prompt_colors.tcl  |   47 +
 .../.scripts/clean_prj_scalp_rx_link_layer.sh |   35 +
 .../create_prj_scalp_rx_link_layer.sh         |   27 +
 .../create_prj_scalp_rx_link_layer.tcl        |  154 +
 .../.scripts/open_prj_scalp_rx_link_layer.sh  |   25 +
 .../2020.2/lin64/.scripts/utils.tcl           |   62 +
 .../scalp_rx_link_layer/2020.2/lin64/setup.sh |   28 +
 .../src/ipi_tcl/scalp_rx_link_layer_ipi.tcl   |    0
 tools/config/scalp_firmware.json              |   17 +-
 tools/config/scalp_rx_link_layer.json         |   18 +
 53 files changed, 5353 insertions(+), 402 deletions(-)
 create mode 100644 designs/vivado/scalp_firmware/2020.2/lin64/.gitignore
 delete mode 100644 designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
 delete mode 100644 designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
 create mode 100644 designs/vivado/scalp_firmware/2020.2/lin64/.scripts/vivado_pid24324.str
 create mode 100644 designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl
 rename designs/vivado/scalp_firmware/2020.2/{lin64/.scripts/gen_sw_apps_scalp_firmware.sh => src/sw/.scripts/clean_sdk_scalp_firmware.sh} (54%)
 rename designs/vivado/scalp_firmware/2020.2/{lin64/.scripts/load_sw_app_scalp_firmware.sh => src/sw/.scripts/gen_sw_apps_scalp_firmware.sh} (79%)
 create mode 100644 designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl
 create mode 100755 designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh
 create mode 100644 designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/utils.tcl
 create mode 100755 designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh
 create mode 100644 designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h
 create mode 100644 designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c
 create mode 100644 ips/hw/scalp_rx_link_layer/src/hdl/scalp_rx_link_layer.vhd
 create mode 100644 ips/hw/scalp_rx_link_layer/src/sim/tb_scalp_rx_link_layer.vhd
 create mode 100644 ips/vivado/scalp_rx_link_layer/2020.2/lin64/.gitignore
 create mode 100644 ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/.prompt_colors.tcl
 create mode 100755 ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/clean_prj_scalp_rx_link_layer.sh
 create mode 100755 ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.sh
 create mode 100644 ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.tcl
 create mode 100755 ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/open_prj_scalp_rx_link_layer.sh
 create mode 100644 ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/utils.tcl
 create mode 100755 ips/vivado/scalp_rx_link_layer/2020.2/lin64/setup.sh
 create mode 100644 ips/vivado/scalp_rx_link_layer/2020.2/src/ipi_tcl/scalp_rx_link_layer_ipi.tcl
 create mode 100644 tools/config/scalp_rx_link_layer.json

diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.gitignore b/designs/vivado/scalp_firmware/2020.2/lin64/.gitignore
new file mode 100644
index 0000000..b843772
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.gitignore
@@ -0,0 +1,23 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-05-17 08:38:48
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_firmware
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
index 8697967..26bb476 100644
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -15,23 +15,33 @@
 # Tool version: 2020.2
 # Description: Console color print utility
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+  set code [catch { set var [exec {*}$cmd] } ]
+  if { $code != 0 } { set var "" }
+
+  return ${var}
+}
+
 # Text attributes
-set RESET [exec tput sgr0]
-set BOLD [exec tput bold]
-set ITALIC [exec tput sitm]
-set BLINK [exec tput blink]
-set HIGHL [exec tput smso]
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
 
 # Text colors
-set RED [exec tput setaf 1]
-set GREEN [exec tput setaf 2]
-set YELLOW [exec tput setaf 3]
-set BLUE [exec tput setaf 4]
-set MAGENTA [exec tput setaf 5]
-set CYAN [exec tput setaf 6]
-set WHITE [exec tput setaf 7]
-
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh
index 22ffc62..72d628d 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Cleanup project directory
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
@@ -31,10 +31,5 @@ rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
 # Remove generated project directory
 rm -rf ${PRJ_DIR}/scalp_firmware/ 2> /dev/null
 
-# Clean app directory
-rm ${PRJ_DIR}/app/*.h 2> /dev/null
-rm ${PRJ_DIR}/app/*.c 2> /dev/null
-rm ${PRJ_DIR}/app/*.html 2> /dev/null
-
 echo "> Done"
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh
index 7d37d3d..7ca8140 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Create Vivado project
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl
index 11299db..c58039e 100644
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: TCL script for re-creating Vivado project 'scalp_firmware'
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
@@ -36,6 +36,7 @@ set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
 # Set the original project directory path for adding/importing sources in the new project
 set src_dir "${PRJ_DIR}/../src"
 set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
 set comp_dir "${ip_dir}/$prj_name"
 set comp_src_dir "${comp_dir}/src"
 set pkg_src_dir "${PKG_DIR}/hw"
@@ -49,60 +50,91 @@ set_property target_language VHDL [current_project]
 print_status "Create project" "OK"
 
 # Map the IP Repository so that custom IP is included
-set_property ip_repo_paths $ip_dir [current_fileset]
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
 update_ip_catalog
 
 #----------------------------------------------------------------
 # Add project sources
 #----------------------------------------------------------------
 
+# Get HDL source files directory
 if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	# add HDL sources
-	set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
-	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
-	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
-	add_files -norecurse $hdl_src_file_list    
-	# add the constraints file (XDC)
-	add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
+    set hdl_src_dir "${src_dir}/hdl"
+    set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+    # components sources are stored in an external directory
+    set hdl_src_dir "${comp_src_dir}/hdl"
+    set sim_src_dir "${comp_src_dir}/sim"
+}    
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+  add_files -norecurse $hdl_src_file_list
+} else {
+  print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {  
+  # add the constraints file (XDC)
+  add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
-add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
 	set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
-add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
-add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
-
-	# add IPs source file
+	
+  # add IPs source files
   set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
 	add_files -norecurse $vhdl_ips_file_list
 	foreach j $vhdl_ips_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_rx_link_layer/src/hdl *.vhd]
+	add_files -norecurse $vhdl_ips_file_list
+	foreach j $vhdl_ips_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
 set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
 	add_files -norecurse $vhdl_ips_file_list
 	foreach j $vhdl_ips_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
 set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
 	add_files -norecurse $vhdl_ips_file_list
 	foreach j $vhdl_ips_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
 set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
 	add_files -norecurse $vhdl_ips_file_list
 	foreach j $vhdl_ips_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
 	read_ip ${ip_dir}/scalp_packet_fifo_wrapper/src/ip_core/scalp_packet_fifo/scalp_packet_fifo.xci
-	read_ip ${ip_dir}/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
@@ -112,32 +144,16 @@ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.v
 	read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
 	read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
 	read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
+	read_ip ${ip_dir}/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
 
 } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
-	# components sources are stored in an external directory
-	# add the project component
-	set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
-	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
-	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
-	add_files -norecurse $hdl_src_file_list
-	# add IPs source file
+  # add IPs source files
   
-	# add IP-XACT source file
-	#add_files -norecurse $comp_dir/component.xml
+  # add IP-XACT source file
+  #add_files -norecurse $comp_dir/component.xml
 }
 print_status "Add project sources" "OK"
 
-foreach j $vhdl_src_file_list {
-    set_property file_type {VHDL 2008} [get_files  $j]
-    print_status "VHDL 2008 mode configured for the file $j" "OK"
-}
-print_status "VHDL 2008 mode configured for project sources" "OK"
-
-#----------------------------------------------------------------
-# Add constraints files
-#----------------------------------------------------------------
-
-
 # Set packages libraries if any
 #set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
 #update_compile_order -fileset sources_1
@@ -154,46 +170,50 @@ print_status "Add IPI design" "OK"
 set_property top $prj_name [current_fileset]
 update_compile_order -fileset sources_1
 
-# Add testbench sources
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
-	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
-	set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
-	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+  add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+  update_compile_order -fileset sim_1
+  print_status "Add simulation sources" "OK"
+} else {
+  print_status "No simulation sources to be added" "WARNING"
 }
-set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
-add_files -fileset sim_1 -norecurse $hdl_sim_file_list
-update_compile_order -fileset sim_1
-print_status "Add testbench sources" "OK"
 
 foreach j $vhdl_sim_file_list {
-    set_property file_type {VHDL 2008} [get_files  $j]
-    print_status "VHDL 2008 mode configured for the file $j" "OK"
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
 }
-print_status "VHDL 2008 mode configured for testbench sources" "OK"
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
 
 # Add packages sources
 	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
 	add_files -norecurse $vhdl_pkg_file_list
 	foreach j $vhdl_pkg_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
+		set_property library xil_defaultlib [get_files $j]
 	}
 	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
 	add_files -norecurse $vhdl_pkg_file_list
 	foreach j $vhdl_pkg_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
+		set_property library xil_defaultlib [get_files $j]
 	}
 	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
 	add_files -norecurse $vhdl_pkg_file_list
 	foreach j $vhdl_pkg_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
+		set_property library xil_defaultlib [get_files $j]
 	}
 print_status "Add packages sources" "OK"
 print_status "VHDL 2008 mode configured for packages sources" "OK"
@@ -202,7 +222,7 @@ print_status "VHDL 2008 mode configured for packages sources" "OK"
 	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
 	add_files -norecurse $vhdl_soc_file_list
 	foreach j $vhdl_soc_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh
index ceae6a7..ddb6537 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh
@@ -17,11 +17,11 @@
 # Tool version: 2020.2
 # Description: Export the hardware design to SDK
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
-echo "> Export the hardware design to SDK"
+echo "> Export the hardware design to Vitis SDK"
 
 vivado -nojournal -nolog -mode tcl -source ./export_hw_scalp_firmware.tcl -notrace
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl
index f207949..5b7b5b5 100644
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl
@@ -13,30 +13,31 @@
 # Project Name: scalp_firmware
 # Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
 # Tool version: 2020.2
-# Description: Export the hardware design to SDK
+# Description: Export the hardware design to Vitis SDK
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
 source utils.tcl
 
+# Project paths
 set PRJ_DIR ".."
+set SRC_DIR "${PRJ_DIR}/../src"
+set EXPORT_DIR "${SRC_DIR}/sw/hw_export"
 
 # Initialize workspace directories name
 set prj_name "scalp_firmware"
-set impl_dir "${PRJ_DIR}/${prj_name}/${prj_name}.runs/impl_1/"
-set export_dir "${PRJ_DIR}/${prj_name}/${prj_name}.sdk"
-print_status "Initialize workspace directories name" "OK"
+# Create the export directory if not present
+file mkdir ${EXPORT_DIR}
+print_status "Initialize workspace directories" "OK"
 
 # Open the project
-open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
+open_project -verbose ${PRJ_DIR}/${prj_name}/${prj_name}.xpr
 print_status "Open project $prj_name" "OK"
 
-# export the hardware
-file mkdir $export_dir
-file copy -force $impl_dir/$prj_name.sysdef $export_dir/$prj_name.hdf
-print_status "Export hardware to SDK" "OK"
+# Export the hardware including the bitstream
+write_hw_platform -fixed -force -include_bit -file ${EXPORT_DIR}/${prj_name}.xsa
+print_status "Export hardware to Vitis SDK" "OK"
 
 exit
-
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
index 0d72b87..45716b4 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Generate bitstream file
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
index fd267b2..045ce64 100644
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: TCL script used to generate bitstream file
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
deleted file mode 100644
index bcb280b..0000000
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
+++ /dev/null
@@ -1,74 +0,0 @@
-#!/usr/bin/tcl
-
-##################################################################################
-#                                 _             _
-#                                | |_  ___ _ __(_)__ _
-#                                | ' \/ -_) '_ \ / _` |
-#                                |_||_\___| .__/_\__,_|
-#                                         |_|
-#
-##################################################################################
-#
-# Company: hepia
-# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
-#
-# Project Name: scalp_firmware
-# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
-# Tool version: 2020.2
-# Description: TCL script used to generate software application
-#
-# Last update: 2021-01-15 09:27:32
-#
-##################################################################################
-
-source utils.tcl
-
-set PRJ_DIR ".."
-set prj_name "scalp_firmware"
-
-set workspace_dir "${PRJ_DIR}/$prj_name/$prj_name.sdk/"
-set hw_spec_file "$prj_name.hdf"
-
-set hw_platform_name "${prj_name}_hw_platform_0"
-set proc_name "ps7_cortexa9_0"
-set os_name "freertos823_xilinx"
-
-set bsp_name "${prj_name}_bsp"
-set app_name "${prj_name}_app"
-
-# Set the SDK workspace
-setws $workspace_dir
-print_status "Set workspace directory" "OK"
-
-# Create the hardware project
-sdk createhw -name $hw_platform_name -hwspec $workspace_dir/$hw_spec_file
-print_status "Create hardware project" "OK"
-
-# Create the FreeRTOS BSP
-sdk createbsp -name $bsp_name -hwproject $hw_platform_name -proc $proc_name -os $os_name
-print_status "Create FreeRTOS BSP project" "OK"
-
-# Create the empty application
-sdk createapp -name $app_name -hwproject $hw_platform_name -proc $proc_name -lang C -app {Empty Application} -os $os_name -bsp $bsp_name
-print_status "Create Empty Application project" "OK"
-
-# Import source files
-sdk importsources -name $app_name -path ${PRJ_DIR}/../src/sw/ -linker-script
-print_status "Import project source files" "OK"
-
-# Set the include directories
-configapp -app $app_name include-path "${PRJ_DIR}/../src/inc/"
-configapp -app $app_name include-path "${PRJ_DIR}/../src/lib/"
-configapp -app $app_name include-path "${PRJ_DIR}/../src/mod/"
-print_status "Set includes directories" "OK"
-
-# Build the projects
-print_status "Build BSP project" "IN_PROGRESS"
-sdk projects -build -type bsp -name $bsp_name
-print_status "Build BSP project" "OK"
-
-print_status "Build application project" "IN_PROGRESS"
-sdk projects -build -type app -name $app_name
-print_status "Build application project" "OK"
-
-exit
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
index 2fec043..dee4aa7 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Load bitstream file
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
index 02728f2..2e1fa2c 100644
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: TCL script used to load FPGA bitstream
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
deleted file mode 100644
index 86f5271..0000000
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
+++ /dev/null
@@ -1,64 +0,0 @@
-##################################################################################
-#                                 _             _
-#                                | |_  ___ _ __(_)__ _
-#                                | ' \/ -_) '_ \ / _` |
-#                                |_||_\___| .__/_\__,_|
-#                                         |_|
-#
-##################################################################################
-#
-# Company: hepia
-# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
-#
-# Project Name: scalp_firmware
-# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
-# Tool version: 2020.2
-# Description: TCL script used to load software application
-#
-# Last update: 2021-01-15 09:27:32
-#
-##################################################################################
-
-source utils.tcl
-
-set PRJ_DIR ".."
-set prj_name "scalp_firmware"
-set hw_platform_name "${prj_name}_hw_platform_0"
-set app_name "${prj_name}_app"
-
-# Connect to the hardware server
-connect -url tcp:127.0.0.1:3121
-print_status "Connect to hardware server" "OK"
-
-# Connect to the processor
-targets 2
-print_status "Connect to ARM Cortex-A9 MPCore #0" "OK"
-
-# Load the hardware design
-loadhw -hw ${PRJ_DIR}/app/$prj_name.hdf
-print_status "Load hardware design" "OK"
-
-# Reset the processor
-rst -processor
-print_status "Reset ARM Cortex-A9 MPCore #0" "OK"
-
-# Initialize the MPSoC
-source ${PRJ_DIR}/app/ps7_init.tcl
-ps7_init
-ps7_post_config
-print_status "Initialize PS7" "OK"
-
-# Load the application
-dow ${PRJ_DIR}/app/$app_name.elf
-print_status "Load software application" "OK"
-
-# Run the application
-con
-print_status "Run software application" "OK"
-
-# Disconnect from the target
-disconnect
-print_status "Disconnect from hardware server" "OK"
-
-exit
-
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh
index c5cc591..89f99c5 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh
@@ -15,9 +15,9 @@
 # Project Name: scalp_firmware
 # Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
 # Tool version: 2020.2
-# Description: Create Vivado project
+# Description: Open Vivado project GUI
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl
index c9dfdfb..494cd78 100644
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: Project management utilities
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/vivado_pid24324.str b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/vivado_pid24324.str
new file mode 100644
index 0000000..c7eaebc
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/vivado_pid24324.str
@@ -0,0 +1,3890 @@
+/*
+
+Xilinx Vivado v2020.2 (64-bit) [Major: 2020, Minor: 2]
+SW Build: 3064766 on Wed Nov 18 09:12:47 MST 2020
+IP Build: 3064653 on Wed Nov 18 14:17:31 MST 2020
+
+Process ID (PID): 24324
+License: Customer
+Mode: GUI Mode
+
+Current time: 	Mon May 17 08:42:34 CEST 2021
+Time zone: 	Central European Standard Time (Europe/Zurich)
+
+OS: PRETTY_NAME="Debian GNU/Linux 10 (buster)"
+OS Version: 5.11.7-debian10-semtech
+OS Architecture: amd64
+Available processors (cores): 6
+
+Display: 0
+Screen size: 2560x1440
+Screen resolution (DPI): 100
+Available screens: 1
+Default font: family=Dialog,name=Dialog,style=plain,size=12
+Scale size: 12
+
+Java version: 	11.0.2 64-bit
+Java home: 	/tools/Xilinx/Vivado/2020.2/tps/lnx64/jre11.0.2
+Java executable location: 	/tools/Xilinx/Vivado/2020.2/tps/lnx64/jre11.0.2/bin/java
+Java initial memory (-Xms): 	128 MB
+Java maximum memory (-Xmx):	 3 GB
+
+
+User name: 	jo
+User home directory: /home/jo
+User working directory: /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/.scripts
+User country: 	CH
+User language: 	fr
+User locale: 	fr_CH
+
+RDI_BASEROOT: /tools/Xilinx/Vivado
+HDI_APPROOT: /tools/Xilinx/Vivado/2020.2
+RDI_DATADIR: /tools/Xilinx/Vivado/2020.2/data
+RDI_BINDIR: /tools/Xilinx/Vivado/2020.2/bin
+
+Vivado preferences file location: /home/jo/.Xilinx/Vivado/2020.2/vivado.xml
+Vivado preferences directory: /home/jo/.Xilinx/Vivado/2020.2/
+Vivado layouts directory: /home/jo/.Xilinx/Vivado/2020.2/data/layouts
+PlanAhead jar file location: 	/tools/Xilinx/Vivado/2020.2/lib/classes/planAhead.jar
+Vivado log file location: 	
+Vivado journal file location: 	
+Engine tmp dir: 	./.Xil/Vivado-24324-semaphore-debian
+
+Xilinx Environment Variables
+----------------------------
+ANDROIDSDK: /home/jo/Android/Sdk/
+ANDROIDSDKTOOLS: /home/jo/Android/Sdk/tools/
+ANDROIDSDKTOOLSBIN: /home/jo/Android/Sdk//home/jo/Android/Sdk/tools/bin/
+VIVADOBINPATH: /tools/Xilinx/Vivado/2020.2/bin/
+VIVADODOCNAVPATH: /tools/Xilinx/DocNav
+VIVADOGCCBINPATH: /tools/Xilinx/Vitis/2020.2/gnu/microblaze/lin/bin/
+VIVADOHLSBINPATH: /tools/Xilinx/Vivado_HLS/2020.2/bin/
+VIVADOHLSPATH: /tools/Xilinx/Vivado_HLS/2020.2/
+VIVADOPATH: /tools/Xilinx/Vivado/2020.2/
+VIVADOSDKBINPATH: /tools/Xilinx/Vitis/2020.2/bin/
+VIVADOSDKPATH: /tools/Xilinx/Vitis/2020.2/
+VIVADOVERSION: 2020.2
+XILINX: /tools/Xilinx/Vivado/2020.2/ids_lite/ISE
+XILINXD_LICENSE_FILE: 7419@10.136.132.94;7419@129.194.185.168;2100@lsn-licence
+XILINXROOTFOLD: /tools
+XILINX_DSP: /tools/Xilinx/Vivado/2020.2/ids_lite/ISE
+XILINX_HLS: /tools/Xilinx/Vitis_HLS/2020.2
+XILINX_PLANAHEAD: /tools/Xilinx/Vivado/2020.2
+XILINX_SDK: /tools/Xilinx/Vitis/2020.2
+XILINX_VITIS: /tools/Xilinx/Vitis/2020.2
+XILINX_VIVADO: /tools/Xilinx/Vivado/2020.2
+XILINX_VIVADO_HLS: /tools/Xilinx/Vivado/2020.2
+
+
+GUI allocated memory:	188 MB
+GUI max memory:		3,072 MB
+Engine allocated memory: 1,489 MB
+
+Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+
+*/
+
+// TclEventType: START_GUI
+// Tcl Message: start_gui 
+// TclEventType: PROJECT_OPEN_DIALOG
+// [GUI Memory]: 109 MB (+111406kb) [00:00:04]
+// [Engine Memory]: 1,476 MB (+1396099kb) [00:00:04]
+// bz (cr):  Open Project : addNotify
+// Opening Vivado Project: ../scalp_firmware/scalp_firmware.xpr. Version: Vivado v2020.2 
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// Tcl Message: open_project ../scalp_firmware/scalp_firmware.xpr 
+// TclEventType: MSGMGR_MOVEMSG
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: FILE_SET_NEW
+// TclEventType: RUN_CURRENT
+// TclEventType: PROJECT_DASHBOARD_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: PROJECT_DASHBOARD_GADGET_NEW
+// TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: LOAD_FEATURE
+// HMemoryUtils.trashcanNow. Engine heap size: 1,501 MB. GUI used memory: 60 MB. Current time: 5/17/21, 8:42:35 AM CEST
+// TclEventType: PROJECT_NEW
+// [GUI Memory]: 120 MB (+5705kb) [00:00:11]
+// WARNING: HEventQueue.dispatchEvent() is taking  1620 ms.
+// Tcl Message: open_project ../scalp_firmware/scalp_firmware.xpr 
+// Tcl Message: Scanning sources... Finished scanning sources 
+// Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw'. 
+// Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.2/data/ip'. 
+// Project name: scalp_firmware; location: /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware; part: xc7z015clg485-2
+// Tcl Message: open_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 7313.250 ; gain = 72.473 ; free physical = 9282 ; free virtual = 21737 
+dismissDialog("Open Project"); // bz
+// [Engine Memory]: 1,555 MB (+5117kb) [00:00:13]
+// Tcl Command: 'rdi::info_commands {device::*}'
+// Tcl Command: 'rdi::info_commands {debug::*}'
+// Tcl Command: 'rdi::info_commands {*}'
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// [GUI Memory]: 140 MB (+14979kb) [00:00:15]
+// [Engine Memory]: 1,634 MB (+1347kb) [00:00:15]
+// Tcl Message: INFO: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'. 
+// Tcl Message: update_compile_order -fileset sources_1 
+// Tcl Message: update_compile_order -fileset sim_1 
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints]", 8); // D
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1]", 9); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, debug.xdc]", 10, false); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, debug.xdc]", 10, false, false, false, false, false, true); // D - Double Click
+// Launch External Editor: 'emacs +0:0 /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc'
+// TclEventType: FILE_SET_CHANGE
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1); // D
+collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, Syntax Error Files]", 1); // D
+// HMemoryUtils.trashcanNow. Engine heap size: 1,700 MB. GUI used memory: 85 MB. Current time: 5/17/21, 8:42:55 AM CEST
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd)]", 2, true); // D - Node
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd)]", 2, true, false, false, false, false, true); // D - Double Click - Node
+// Launch External Editor: 'emacs +280:0 /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd'
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// [Engine Memory]: 1,726 MB (+11133kb) [00:00:43]
+// HMemoryUtils.trashcanNow. Engine heap size: 1,727 MB. GUI used memory: 84 MB. Current time: 5/17/21, 8:43:10 AM CEST
+// Elapsed time: 19 seconds
+selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Libraries", 2); // i
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, xil_defaultlib, Unreferenced]", 31); // D
+collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, xil_defaultlib, Unreferenced]", 31); // D
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // u
+// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
+// f (cr): Launch Runs: addNotify
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// bz (cr):  Starting Design Runs : addNotify
+dismissDialog("Launch Runs"); // f
+// Tcl Message: launch_runs synth_1 -jobs 3 
+// TclEventType: RSB_CHANGE_CURRENT_DIAGRAM
+// TclEventType: RSB_LOCK_CHANGE
+// TclEventType: MSGMGR_REFRESH_MSG
+// Tcl Message: INFO: [BD 41-1662] The design 'scalp_zynqps.bd' is already validated. Therefore parameter propagation will not be re-run. 
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// Tcl Message: VHDL Output written to : /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.vhd VHDL Output written to : /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/scalp_zynqps/sim/scalp_zynqps.vhd VHDL Output written to : /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/scalp_zynqps/hdl/scalp_zynqps_wrapper.vhd 
+// Tcl Message: INFO: [BD 41-1029] Generation completed for the IP Integrator block gnd_constant . INFO: [BD 41-1029] Generation completed for the IP Integrator block irq_xlconcat . 
+// TclEventType: FILE_SET_CHANGE
+// Tcl Message: INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 . 
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RSB_CLOSE_DIAGRAM
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// Tcl Message: INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/xbar . 
+// Tcl Message: INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7_0_axi_periph/s00_couplers/auto_pc . INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_125M . INFO: [BD 41-1029] Generation completed for the IP Integrator block scalp_axi4lite_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block scalp_safe_firmware_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 . INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 . INFO: [BD 41-1029] Generation completed for the IP Integrator block vio_0 . 
+// Tcl Message: Exporting to file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/scalp_zynqps/hw_handoff/scalp_zynqps.hwh Generated Block Design Tcl file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/scalp_zynqps/hw_handoff/scalp_zynqps_bd.tcl Generated Hardware Definition File /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/scalp_zynqps/synth/scalp_zynqps.hwdef 
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_NEW
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_ADD
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: RUN_MODIFY
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_MODIFY
+// HMemoryUtils.trashcanNow. Engine heap size: 1,806 MB. GUI used memory: 88 MB. Current time: 5/17/21, 8:43:50 AM CEST
+// TclEventType: RUN_MODIFY
+// TclEventType: RUN_STATUS_CHANGE
+// Tcl Message: [Mon May 17 08:43:50 2021] Launched synth_1... Run output will be captured here: /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/synth_1/runme.log 
+// Tcl Message: launch_runs: Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 7718.582 ; gain = 187.105 ; free physical = 8144 ; free virtual = 20904 
+// 'k' command handler elapsed time: 25 seconds
+// TclEventType: RUN_STATUS_CHANGE
+// Elapsed time: 24 seconds
+dismissDialog("Starting Design Runs"); // bz
+// [GUI Memory]: 147 MB (+541kb) [00:01:25]
+// TclEventType: RUN_STATUS_CHANGE
+// [Engine Memory]: 1,951 MB (+145700kb) [00:01:27]
+// TclEventType: RUN_STATUS_CHANGE
+// Elapsed time: 72 seconds
+collapseTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, VHDL 2008, xil_defaultlib]", 2); // D
+selectTab(PAResourceEtoH.FileSetView_TABBED_PANE, (HResource) null, "Hierarchy", 0); // i
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd), ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI : scalp_aurora_phy(arch) (scalp_aurora_phy.vhd)]", 6); // D
+// TclEventType: FILE_SET_CHANGE
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd), ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI : scalp_router(rtl) (scalp_router.vhd)]", 16); // D
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd), ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI : scalp_router(rtl) (scalp_router.vhd), ScalpRouterInterfacexG[0].ScalpRouterInterfacexI : scalp_router_interface(rtl) (scalp_router_interface.vhd)]", 17); // D
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// [GUI Memory]: 155 MB (+665kb) [00:03:19]
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// [GUI Memory]: 197 MB (+35011kb) [00:03:49]
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// ag (cr): Synthesis Completed: addNotify
+// HMemoryUtils.trashcanNow. Engine heap size: 1,821 MB. GUI used memory: 108 MB. Current time: 5/17/21, 9:13:50 AM CEST
+// Elapsed time: 1887 seconds
+selectButton(RDIResource.BaseDialog_CANCEL, "Cancel"); // a
+dismissDialog("Synthesis Completed"); // ag
+// Elapsed time: 49 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design]", 15, true); // u - Node
+// Run Command: PAResourceCommand.PACommandNames_GOTO_NETLIST_DESIGN
+// bz (cr):  Open Synthesized Design : addNotify
+// Tcl Message: open_run synth_1 -name synth_1 
+// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7z015clg485-2 
+// HMemoryUtils.trashcanNow. Engine heap size: 1,860 MB. GUI used memory: 108 MB. Current time: 5/17/21, 9:18:20 AM CEST
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_CNS_STALE
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// [Engine Memory]: 2,416 MB (+384987kb) [00:36:03]
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: TIMING_RESULTS_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: FLOORPLAN_MODIFY
+// TclEventType: DESIGN_NEW
+// HMemoryUtils.trashcanNow. Engine heap size: 2,426 MB. GUI used memory: 109 MB. Current time: 5/17/21, 9:18:31 AM CEST
+// TclEventType: DESIGN_NEW
+// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
+// Schematic: addNotify
+// WARNING: HEventQueue.dispatchEvent() is taking  2176 ms.
+// TclEventType: CURR_DESIGN_SET
+// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 7718.582 ; gain = 0.000 ; free physical = 8492 ; free virtual = 21168 
+// Tcl Message: INFO: [Netlist 29-17] Analyzing 307 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization 
+// Tcl Message: INFO: [Chipscope 16-324] Core: ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/vio_0 UUID: 31898c18-405f-5cf9-92b7-4ad14d196966  INFO: [Chipscope 16-324] Core: ProgrammableLogicxB.NetworkLayerxB.WrSpValidxI UUID: f846851f-ed37-59e4-b8a4-3fd8415cd5f8  
+// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xdc:57] 
+// Tcl Message: INFO: [Project 1-1715] 4 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 
+// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8090.301 ; gain = 0.000 ; free physical = 7929 ; free virtual = 20618 
+// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.  
+// Elapsed time: 62 seconds
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
+// ExpRunCommands.openSynthResults elapsed time: 62.4s
+// Tcl Message: open_run: Time (s): cpu = 00:00:29 ; elapsed = 00:01:02 . Memory (MB): peak = 8182.688 ; gain = 464.105 ; free physical = 7827 ; free virtual = 20524 
+// 'dV' command handler elapsed time: 63 seconds
+// WARNING: HEventQueue.dispatchEvent() is taking  1032 ms.
+dismissDialog("Open Synthesized Design"); // bz
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design, Set Up Debug]", 18, false); // u
+// Run Command: PAResourceCommand.PACommandNames_DEBUG_WIZARD
+// N (cr): Set Up Debug: addNotify
+// bz (N):  Filtering Net and Tracing Clock Domain : addNotify
+selectButton("NEXT", "Next >"); // JButton
+dismissDialog("Filtering Net and Tracing Clock Domain"); // bz
+// [GUI Memory]: 214 MB (+8421kb) [00:36:25]
+selectTab((HResource) null, (HResource) null, "Sources", 0); // aK
+expandTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd), ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI : scalp_router(rtl) (scalp_router.vhd), ScalpRouterInterfacexG[0].ScalpRouterInterfacexI : scalp_router_interface(rtl) (scalp_router_interface.vhd), ScalpTXSidexI : scalp_tx_side(behavioral) (scalp_tx_side.vhd)]", 18); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd), ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI : scalp_router(rtl) (scalp_router.vhd), ScalpRouterInterfacexG[0].ScalpRouterInterfacexI : scalp_router_interface(rtl) (scalp_router_interface.vhd), ScalpTXSidexI : scalp_tx_side(behavioral) (scalp_tx_side.vhd), ScalpFifoDoubleRegisterxI : scalp_fifo_double_register(behavioral) (scalp_fifo_double_register.vhd)]", 19, false); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Design Sources, scalp_firmware(arch) (scalp_firmware.vhd), ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI : scalp_router(rtl) (scalp_router.vhd), ScalpRouterInterfacexG[0].ScalpRouterInterfacexI : scalp_router_interface(rtl) (scalp_router_interface.vhd), ScalpTXSidexI : scalp_tx_side(behavioral) (scalp_tx_side.vhd), ScalpFifoDoubleRegisterxI : scalp_fifo_double_register(behavioral) (scalp_fifo_double_register.vhd)]", 19, false, false, false, false, false, true); // D - Double Click
+// Launch External Editor: 'emacs +50:0 /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd'
+// Elapsed time: 18 seconds
+selectButton(RDIResource.AbstractSearchablePanel_SHOW_SEARCH, "Nets to Debug_search"); // x: TRUE
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "DestxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DestxD] (4) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT4 ; Data and Trigger", 3, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DestxD] (4)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "[IdxS"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[IdxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT3 ; Data and Trigger", 15, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[IdxS]", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "KeepxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[1].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[KeepxD] (4) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT3 ; Data and Trigger", 15, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[1].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[KeepxD] (4)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "StrbxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[StrbxD] (4) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT3 ; Data and Trigger", 15, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[StrbxD] (4)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "UserxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[UserxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT1 ; Data and Trigger", 8, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[UserxD] (32)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+// Elapsed time: 12 seconds
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "ScalpTXSidexI"); // OverlayTextField
+selectTreeTableHeader(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "Name", 0); // aq
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; RAMB36E1 ; Data and Trigger", 0, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[2].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 62, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[2].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]", 0, true, true, false, false, false, false); // aq - Shift Key - Node
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[4].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT1 ; Data and Trigger", 21, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[4].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 83, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]", 0, false, true, false, false, false, false); // aq - Shift Key
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "ScalpRXSidexI"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT6 ; Data and Trigger", 0, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 125, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]", 0, false, true, false, false, false, false); // aq - Shift Key
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_axi4lite_0/U0/RdAddrxD (12) ; ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0 ; FDRE ; Data and Trigger", 0, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_axi4lite_0/U0/RdAddrxD (12)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS ; ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0 ; LUT5 ; Data and Trigger", 12, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS", 0, true, true, false, false, false, false); // aq - Shift Key - Node
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+selectButton("NEXT", "Next >"); // JButton
+selectComboBox(PAResourceAtoD.DebugWizard_SAMPLE_OF_DATA_DEPTH, "2048", 1); // e
+selectButton("NEXT", "Next >"); // JButton
+selectButton("FINISH", "Finish"); // JButton
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: DEBUG_CORE_ADD
+// TclEventType: DEBUG_GRAPH_STALE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_core u_ila_0 ila 
+// bz (N):  Set Up Debug : addNotify
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ]] 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe0] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe1] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe2] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe3] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// [GUI Memory]: 234 MB (+9467kb) [00:38:35]
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe4] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe5] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe6] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe7] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe8] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe9] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe10] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe11] 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe12] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe12 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe13] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe13 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe14] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe14 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe15] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe15 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe16] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe16 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe17] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe17 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe18] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe18 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe19] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe19 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe20] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe20 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe21] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe21 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe22] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe22 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe23] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe23 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe24] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe24 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe25] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe25 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe26] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe26 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe27] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe27 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe28] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe28 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe29] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe29 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe30] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe30 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe31] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe31 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe32] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe33] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe34] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe34 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe35] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe35 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe36] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe36 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe37] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe37 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe38] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe38 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe39] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe39 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe40] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe40 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe41] 
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// HMemoryUtils.trashcanNow. Engine heap size: 2,530 MB. GUI used memory: 150 MB. Current time: 5/17/21, 9:21:34 AM CEST
+// Tcl Message: connect_debug_port u_ila_0/probe41 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]} ]] 
+// TclEventType: DEBUG_GRAPH_STALE
+// Elapsed time: 38 seconds
+dismissDialog("Set Up Debug"); // bz
+dismissDialog("Set Up Debug"); // N
+// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
+// A (cr): Out of Date Design: addNotify
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// a (cr): Save Constraints: addNotify
+dismissDialog("Out of Date Design"); // A
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// TclEventType: FILESET_TARGET_UCF_CHANGE
+// TclEventType: FILE_SET_OPTIONS_CHANGE
+// bz (cr):  Save Constraints : addNotify
+// Tcl Message: set_property target_constrs_file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc [current_fileset -constrset] 
+dismissDialog("Save Constraints"); // a
+// TclEventType: DESIGN_STALE
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: DESIGN_SAVE
+// TclEventType: FILESET_TARGET_UCF_CHANGE
+// Tcl Message: save_constraints -force 
+// 'h' command handler elapsed time: 9 seconds
+dismissDialog("Save Constraints"); // bz
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 32, false); // u
+// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
+// A (cr): No Implementation Results Available: addNotify
+selectButton(RDIResource.BaseDialog_YES, "Yes"); // a
+// bz (cr):  Resetting Runs : addNotify
+// cD (cr): Launch Runs: addNotify
+dismissDialog("No Implementation Results Available"); // A
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// TclEventType: FILESET_TARGET_UCF_CHANGE
+dismissDialog("Launch Runs"); // cD
+// bz (cr):  Generate Bitstream : addNotify
+// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 3 
+// Tcl Message: Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. 
+// Tcl Message: Write XDEF Complete: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.05 . Memory (MB): peak = 8182.688 ; gain = 0.000 ; free physical = 7751 ; free virtual = 20471 
+// HMemoryUtils.trashcanNow. Engine heap size: 2,569 MB. GUI used memory: 151 MB. Current time: 5/17/21, 9:21:55 AM CEST
+// TclEventType: RUN_LAUNCH
+// TclEventType: RUN_MODIFY
+// [Engine Memory]: 2,550 MB (+14185kb) [00:39:32]
+// TclEventType: RUN_STATUS_CHANGE
+// Tcl Message: [Mon May 17 09:21:58 2021] Launched impl_1... Run output will be captured here: /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/runme.log 
+dismissDialog("Generate Bitstream"); // bz
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// ag (cr): Bitstream Generation Completed: addNotify
+// Elapsed time: 599 seconds
+selectRadioButton(PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER, "Open Hardware Manager"); // a
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl Command: 'rdi::info_commands get_hw_probes'
+// Tcl Command: 'load_features labtools'
+// TclEventType: LOAD_FEATURE
+// bz (cr):  Open Hardware Manager : addNotify
+// TclEventType: HW_SESSION_OPEN
+// WARNING: HEventQueue.dispatchEvent() is taking  1435 ms.
+// Tcl Message: open_hw_manager 
+dismissDialog("Open Hardware Manager"); // bz
+// Elapsed time: 12 seconds
+selectButton(PAResourceOtoP.ProgramDebugTab_OPEN_TARGET, "Open target"); // h
+selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ak
+// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET
+// Tcl Message: connect_hw_server -allow_non_jtag 
+// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... 
+// bz (cr):  Auto Connect : addNotify
+// TclEventType: HW_SERVER_UPDATE
+// Tcl Message: INFO: [Labtools 27-2221] Launch Output:  ****** Xilinx hw_server v2020.2   **** Build date : Nov 18 2020 at 09:50:49     ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042 INFO: [Labtools 27-3417] Launching cs_server... 
+// TclEventType: HW_SERVER_UPDATE
+// Tcl Message: INFO: [Labtools 27-2221] Launch Output:   ******** Xilinx cs_server v2020.2   ****** Build date   : Nov 03 2020-22:02:56     **** Build number : 2020.2.1604437376       ** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved.    
+// TclEventType: HW_TARGET_CHANGE
+// TclEventType: HW_TARGET_CLOSE
+// Tcl Message: open_hw_target 
+// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210299AFC175 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_ADD
+// TclEventType: HW_TARGET_UPDATE
+// WARNING: HEventQueue.dispatchEvent() is taking  2824 ms.
+// HMemoryUtils.trashcanNow. Engine heap size: 3,874 MB. GUI used memory: 146 MB. Current time: 5/17/21, 9:32:21 AM CEST
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.bit} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: set_property FULL_PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: current_hw_device [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// [Engine Memory]: 3,902 MB (+1283816kb) [00:49:57]
+// WARNING: HEventQueue.dispatchEvent() is taking  3207 ms.
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7z015_1] 0] 
+// Tcl Message: INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s). INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 1 VIO core(s). 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// Elapsed time: 11 seconds
+dismissDialog("Auto Connect"); // bz
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectMenuItem((HResource) null, "xc7z015_1"); // ak
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl Command: 'rdi::info_commands get_hw_probes'
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+// bC (cr): Program Device: addNotify
+selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a
+// bz (cr):  Program Device : addNotify
+// TclEventType: HW_DEVICE_CHANGE
+dismissDialog("Program Device"); // bC
+// Tcl Message: set_property PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: set_property FULL_PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.bit} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_OBJECT_DELETE
+// TclEventType: HW_DEVICE_UPDATE
+// Tcl Message: program_hw_devices [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: DEBUG_PROBE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7z015_1] 0] 
+// Tcl Message: INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s). INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 2 VIO core(s). INFO: [Labtools 27-1889] Uploading output probe values for VIO core [hw_vio_1] INFO: [Labtools 27-1889] Uploading output probe values for VIO core [hw_vio_2] 
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Waveform: addNotify
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Waveform: addNotify
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// HMemoryUtils.trashcanNow. Engine heap size: 3,992 MB. GUI used memory: 163 MB. Current time: 5/17/21, 9:32:33 AM CEST
+// Tcl Message: display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// 'I' command handler elapsed time: 5 seconds
+dismissDialog("Program Device"); // bz
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Waveform: addNotify
+// Waveform: addNotify
+// Waveform: addNotify
+// Elapsed time: 308 seconds
+floatFrame(PAResourceOtoP.PAViews_DASHBOARD, "hw_ila_1"); // az
+// PAResourceOtoP.PAViews_DASHBOARD: hw_ila_1: float view
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,992 MB. GUI used memory: 182 MB. Current time: 5/17/21, 9:37:42 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,992 MB. GUI used memory: 177 MB. Current time: 5/17/21, 9:37:44 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,993 MB. GUI used memory: 178 MB. Current time: 5/17/21, 9:37:45 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,993 MB. GUI used memory: 172 MB. Current time: 5/17/21, 9:37:47 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,993 MB. GUI used memory: 171 MB. Current time: 5/17/21, 9:37:49 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 3,993 MB. GUI used memory: 170 MB. Current time: 5/17/21, 9:37:51 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 14 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[DataxD][0:31]]", 0, true); // a - Node
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][0:31]]", 5, true, true, false, false, false, false); // a - Shift Key - Node
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]]", 15, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]]", 16, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]]", 17, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]]", 18, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]]", 19, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]]", 20, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 21, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]]", 22, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[LastxS]]", 23, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]]", 24, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]]", 25, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]]", 26, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]]", 27, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]]", 29, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]]", 28, false, false, true, false, false, false); // a - Control Key
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][0:31]]", 3, true, false, false, false, true, false); // a - Popup Trigger - Node
+selectMenu("Name"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Radix"); // ah
+selectMenuItem((HResource) null, "New Group"); // ak
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_RENAME_COMMAND
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side]", 21, true); // a - Node
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side]", 0); // a
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[DataxD][0:31]]", 9, true); // a - Node
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]]", 29, false, true, false, false, false, false); // a - Shift Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]]", 29, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Name"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Radix"); // ah
+selectMenuItem((HResource) null, "New Group"); // ak
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_RENAME_COMMAND
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+expandTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side]", 9); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 22 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 13, false); // a
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side]", 22, true); // a - Node
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side]", 22, true); // a - Node
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 10, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectButton(PAResourceItoN.IlaProbeTablePanel_ADD_PROBES, (String) null); // E
+selectButton(PAResourceAtoD.AddIlaProbesPopup_OK, "OK"); // a
+selectTableHeader(PAResourceTtoZ.TriggerSetupPanel_TABLE, "Name", 0); // A
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS] ; ==   ; [B]   ; X ; probe15[0] ; ", 0, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 0, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// Elapsed time: 12 seconds
+setText("[0 - 1023]", "512"); // y
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: set_property CONTROL.TRIGGER_POSITION 512 [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// Elapsed time: 107 seconds
+selectButton(PAResourceEtoH.HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE, "Waveform Viewer_run_trigger"); // E
+// Run Command: PAResourceCommand.PACommandNames_RUN_TRIGGER
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// Tcl Message: INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2021-May-17 09:41:27 
+// Elapsed time: 16 seconds
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS] ; ==   ; [B]   ; B ; probe15[0] ; 1 of 1", 0, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]", 0); // A
+selectButton(PAResourceItoN.IlaProbeTablePanel_REMOVE_SELECTED_PROBE, "IlaProbeTablePanel_remove"); // E
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 11 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]]", 7, false); // a
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]]", 9, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 10, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]]", 14, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]]", 14, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]]", 13, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]]", 17, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]]", 19, false, false, true, false, false, false); // a - Control Key
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]]", 25, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]]", 26, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]]", 27, false, false, true, false, false, false); // a - Control Key
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 22 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]]", 7, false); // a
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]]", 9, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 10, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]]", 13, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]]", 17, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]]", 19, false, false, true, false, false, false); // a - Control Key
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]]", 25, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]]", 26, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]]", 27, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 30, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]]", 33, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]]", 37, false, false, true, false, false, false); // a - Control Key
+selectButton(PAResourceItoN.IlaProbeTablePanel_ADD_PROBES, (String) null); // E
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectButton(PAResourceAtoD.AddIlaProbesPopup_OK, "OK"); // a
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS] ; ==   ; [B]   ; X ; probe12[0] ; ", 0, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 0, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS] ; ==   ; [B]   ; X ; probe14[0] ; ", 1, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 1, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectButton(PAResourceItoN.IlaProbeTablePanel_SET_TRIGGER_CONDITION_TO_GLOBAL, "IlaProbeTablePanel_OPERATOR"); // E
+selectMenuItem(PAResourceItoN.IlaProbeTablePanel_SET_TRIGGER_CONDITION_TO_GLOBAL, "Set Trigger Condition to 'Global OR'"); // Y
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: set_property CONTROL.TRIGGER_CONDITION OR [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS] ; ==   ; [B]   ; X ; probe15[0] ; ", 2, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 2, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS] ; ==   ; [B]   ; X ; probe18[0] ; ", 3, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 3, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS] ; ==   ; [B]   ; X ; probe22[0] ; ", 4, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 4, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS] ; ==   ; [B]   ; X ; probe24[0] ; ", 5, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 5, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS] ; ==   ; [B]   ; X ; probe28[0] ; ", 6, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 6, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS] ; ==   ; [B]   ; X ; probe29[0] ; ", 7, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 7, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS] ; ==   ; [B]   ; X ; probe30[0] ; ", 8, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 8, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS] ; ==   ; [B]   ; X ; probe33[0] ; ", 9, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 9, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS] ; ==   ; [B]   ; X ; probe36[0] ; ", 10, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 10, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS] ; ==   ; [B]   ; X ; probe41[0] ; ", 11, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 11, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectButton(PAResourceEtoH.HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE, "Waveform Viewer_run_trigger"); // E
+// Run Command: PAResourceCommand.PACommandNames_RUN_TRIGGER
+selectButton(PAResourceEtoH.HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE, "Waveform Viewer_run_trigger"); // E
+// Run Command: PAResourceCommand.PACommandNames_RUN_TRIGGER
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 54 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]]", 18, false); // a
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]]", 20, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]]", 21, false, false, true, false, false, false); // a - Control Key
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]]", 35, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]]", 36, false, false, true, false, false, false); // a - Control Key
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]]", 38, false, false, true, false, false, false); // a - Control Key
+selectButton(PAResourceItoN.IlaProbeTablePanel_ADD_PROBE, "IlaProbeTablePanel_new"); // E
+selectButton(PAResourceAtoD.AddIlaProbesPopup_OK, "OK"); // a
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS] ; ==   ; [B]   ; X ; probe23[0] ; ", 12, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 12, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ==   ; [B]   ; X ; probe25[0] ; ", 13, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 13, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS] ; ==   ; [B]   ; X ; probe26[0] ; ", 14, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 14, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ==   ; [B]   ; X ; probe38[0] ; ", 15, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 15, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS] ; ==   ; [B]   ; X ; probe39[0] ; ", 16, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 16, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS] ; ==   ; [B]   ; X ; probe40[0] ; ", 17, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 17, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 4,007 MB. GUI used memory: 173 MB. Current time: 5/17/21, 9:44:35 AM CEST
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: HW_WAVE_ZIP_EXPORT_DONE
+// TclEventType: WAVEFORM_GLASSPANE
+// Tcl Message: display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// Tcl Message: INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2021-May-17 09:44:34 INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data. 
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Elapsed time: 21 seconds
+selectButton(PAResourceEtoH.HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE, "Waveform Viewer_run_trigger"); // E
+// Run Command: PAResourceCommand.PACommandNames_RUN_TRIGGER
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// Tcl Message: INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2021-May-17 09:44:49 
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,007 MB. GUI used memory: 200 MB. Current time: 5/17/21, 9:44:54 AM CEST
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: HW_WAVE_ZIP_EXPORT_DONE
+// TclEventType: WAVEFORM_GLASSPANE
+// Tcl Message: display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// Tcl Message: INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2021-May-17 09:44:53 INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data. 
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,002 MB. GUI used memory: 211 MB. Current time: 5/17/21, 9:44:56 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,002 MB. GUI used memory: 179 MB. Current time: 5/17/21, 9:44:58 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Elapsed time: 22 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]]", 9, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 178 MB. Current time: 5/17/21, 9:45:12 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 10, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 173 MB. Current time: 5/17/21, 9:45:21 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Elapsed time: 46 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectMenuItem((HResource) null, "xc7z015_1"); // ak
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl Command: 'rdi::info_commands get_hw_probes'
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+// bC (cr): Program Device: addNotify
+selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a
+// bz (cr):  Program Device : addNotify
+// TclEventType: HW_DEVICE_CHANGE
+dismissDialog("Program Device"); // bC
+// Tcl Message: set_property PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: set_property FULL_PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.bit} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_OBJECT_DELETE
+// TclEventType: HW_DEVICE_UPDATE
+// Tcl Message: program_hw_devices [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 4,011 MB. GUI used memory: 192 MB. Current time: 5/17/21, 9:46:06 AM CEST
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7z015_1] 0] 
+// Tcl Message: INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s). INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 2 VIO core(s). 
+// 'I' command handler elapsed time: 4 seconds
+dismissDialog("Program Device"); // bz
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectButton(PAResourceEtoH.HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE, "Waveform Viewer_run_trigger"); // E
+// Run Command: PAResourceCommand.PACommandNames_RUN_TRIGGER
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// Tcl Message: INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2021-May-17 09:46:16 
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 4,011 MB. GUI used memory: 207 MB. Current time: 5/17/21, 9:46:24 AM CEST
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: HW_WAVE_ZIP_EXPORT_DONE
+// TclEventType: WAVEFORM_GLASSPANE
+// Tcl Message: display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// Tcl Message: INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2021-May-17 09:46:23 INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data. 
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 179 MB. Current time: 5/17/21, 9:46:31 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Elapsed time: 17 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 540, 480); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 203 MB. Current time: 5/17/21, 9:46:33 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 179 MB. Current time: 5/17/21, 9:46:33 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 182 MB. Current time: 5/17/21, 9:46:34 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 178 MB. Current time: 5/17/21, 9:46:36 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 190 MB. Current time: 5/17/21, 9:46:39 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 177 MB. Current time: 5/17/21, 9:46:39 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xD[DataxD][0:31]]", 18, true); // a - Node
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 174 MB. Current time: 5/17/21, 9:46:41 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 180 MB. Current time: 5/17/21, 9:46:46 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 549, 493); // n
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 179 MB. Current time: 5/17/21, 9:46:48 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 183 MB. Current time: 5/17/21, 9:46:56 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,003 MB. GUI used memory: 182 MB. Current time: 5/17/21, 9:46:58 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Elapsed time: 17 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][0:31]]", 6, true); // a - Node
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// HMemoryUtils.trashcanNow. Engine heap size: 4,020 MB. GUI used memory: 167 MB. Current time: 5/17/21, 9:50:20 AM CEST
+// TclEventType: DG_GRAPH_STALE
+// TclEventType: FILE_SET_CHANGE
+// [Engine Memory]: 4,204 MB (+111995kb) [01:09:23]
+// HMemoryUtils.trashcanNow. Engine heap size: 4,214 MB. GUI used memory: 167 MB. Current time: 5/17/21, 9:51:50 AM CEST
+// Elapsed time: 291 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 573, 493); // nWaveform: addNotify
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 573, 493); // nWaveform: addNotify
+// HMemoryUtils.trashcanNow. Engine heap size: 4,037 MB. GUI used memory: 192 MB. Current time: 5/17/21, 9:51:58 AM CEST
+dockFrame(PAResourceOtoP.PAViews_DASHBOARD, "hw_ila_1"); // az
+// PAResourceOtoP.PAViews_DASHBOARD: hw_ila_1: dock view
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k
+closeTask("Program and Debug", "Hardware Manager", "DesignTask.PROGRAM_DEBUG");
+// A (cr): Confirm Close: addNotify
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// bz (cr):  Close Hardware Manager : addNotify
+// Tcl Message: save_wave_config {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wcfg} 
+// TclEventType: WAVEFORM_MODEL_EVENT
+dismissDialog("Confirm Close"); // A
+// TclEventType: WAVEFORM_CLOSE_WCFG
+// TclEventType: HW_OBJECT_DELETE
+// TclEventType: HW_SERVER_CLOSE
+// TclEventType: HW_SYSMON_DELETE
+closeView(PAResourceOtoP.PAViews_DASHBOARD, "hw_vios"); // i
+closeView(PAResourceOtoP.PAViews_DASHBOARD, "hw_ila_1"); // i
+// Tcl Message: close_hw_manager 
+// TclEventType: HW_SYSMON_DELETE
+// TclEventType: HW_TARGET_CLOSE
+// TclEventType: HW_TARGET_UPDATE
+// TclEventType: DEBUG_PROBE_DELETE
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: HW_SESSION_CLOSE
+// WARNING: HEventQueue.dispatchEvent() is taking  1437 ms.
+dismissDialog("Close Hardware Manager"); // bz
+selectButton(PAResourceTtoZ.TaskBanner_CLOSE, (String) null); // k
+closeTask("Synthesis", "Synthesized Design", "DesignTask.NETLIST_PLANNING");
+// A (cr): Confirm Close: addNotify
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// bz (cr):  Close : addNotify
+dismissDialog("Confirm Close"); // A
+// TclEventType: DESIGN_CLOSE
+// HMemoryUtils.trashcanNow. Engine heap size: 3,990 MB. GUI used memory: 148 MB. Current time: 5/17/21, 9:52:07 AM CEST
+// Engine heap size: 3,990 MB. GUI used memory: 149 MB. Current time: 5/17/21, 9:52:08 AM CEST
+// WARNING: HEventQueue.dispatchEvent() is taking  1735 ms.
+// TclEventType: CURR_DESIGN_SET
+// Tcl Message: close_design 
+// TclEventType: DESIGN_CLOSE
+dismissDialog("Close"); // bz
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, debug.xdc]", 40, false); // D
+selectTree(PAResourceEtoH.FileSetPanel_FILE_SET_PANEL_TREE, "[root, Constraints, constrs_1, debug.xdc]", 40, false, false, false, false, false, true); // D - Double Click
+// Launch External Editor: 'emacs +0:0 /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc'
+// TclEventType: FILE_SET_CHANGE
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // u
+// Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS
+// A (cr): Run Synthesis: addNotify
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// bz (cr):  Resetting Runs : addNotify
+// TclEventType: RUN_MODIFY
+dismissDialog("Run Synthesis"); // A
+// TclEventType: RUN_RESET
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_RESET
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_RESET
+// TclEventType: RUN_MODIFY
+// Tcl Message: reset_run synth_1 
+// f (cr): Launch Runs: addNotify
+// Elapsed time: 36 seconds
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// bz (cr):  Starting Design Runs : addNotify
+dismissDialog("Launch Runs"); // f
+// TclEventType: FILESET_TARGET_UCF_CHANGE
+// TclEventType: RUN_LAUNCH
+// TclEventType: RUN_MODIFY
+// TclEventType: RUN_STATUS_CHANGE
+// 'k' command handler elapsed time: 38 seconds
+dismissDialog("Starting Design Runs"); // bz
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// ag (cr): Synthesis Completed: addNotify
+// Elapsed time: 148 seconds
+selectRadioButton(PAResourceCommand.PACommandNames_GOTO_NETLIST_DESIGN, "Open Synthesized Design"); // a
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// Run Command: PAResourceCommand.PACommandNames_GOTO_NETLIST_DESIGN
+// bz (cr):  Open Synthesized Design : addNotify
+// Tcl Message: open_run synth_1 -name synth_1 
+// Tcl Message: Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7z015clg485-2 
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_CNS_STALE
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: LOC_CONSTRAINT_REMOVE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: PLACEDB_MODIFIY_PRE
+// TclEventType: LOC_CONSTRAINT_ADD
+// TclEventType: SIGNAL_MODIFY
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: POWER_REPORT_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: TIMING_RESULTS_STALE
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: SDC_CONSTRAINT_ADD
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: READ_XDC_FILE_START
+// TclEventType: READ_XDC_FILE_END
+// TclEventType: FLOORPLAN_MODIFY
+// TclEventType: DESIGN_NEW
+// HMemoryUtils.trashcanNow. Engine heap size: 4,030 MB. GUI used memory: 120 MB. Current time: 5/17/21, 9:55:36 AM CEST
+// TclEventType: DESIGN_NEW
+// TclEventType: HFED_INIT_ROUTE_STORAGE_COMPLETED
+// Schematic: addNotify
+// WARNING: HEventQueue.dispatchEvent() is taking  1719 ms.
+// TclEventType: CURR_DESIGN_SET
+// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 9971.891 ; gain = 0.000 ; free physical = 5223 ; free virtual = 18189 
+// Tcl Message: INFO: [Netlist 29-17] Analyzing 307 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.2 INFO: [Project 1-570] Preparing netlist for logic optimization 
+// Tcl Message: INFO: [Chipscope 16-324] Core: ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/vio_0 UUID: 31898c18-405f-5cf9-92b7-4ad14d196966  INFO: [Chipscope 16-324] Core: ProgrammableLogicxB.NetworkLayerxB.WrSpValidxI UUID: f846851f-ed37-59e4-b8a4-3fd8415cd5f8  
+// Tcl Message: INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xdc:57] 
+// Tcl Message: INFO: [Project 1-1715] 4 XPM XDC files have been applied to the design. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 
+// Tcl Message: Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 9971.891 ; gain = 0.000 ; free physical = 5098 ; free virtual = 18063 
+// Tcl Message: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed.  
+// Elapsed time: 11 seconds
+closeView(PAResourceOtoP.PAViews_PROJECT_SUMMARY, "Project Summary"); // v
+// Tcl Message: open_run: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 9971.891 ; gain = 0.000 ; free physical = 5032 ; free virtual = 17996 
+// 'dV' command handler elapsed time: 12 seconds
+// WARNING: HEventQueue.dispatchEvent() is taking  1044 ms.
+dismissDialog("Open Synthesized Design"); // bz
+// Elapsed time: 10 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Open Synthesized Design, Set Up Debug]", 18, false); // u
+// Run Command: PAResourceCommand.PACommandNames_DEBUG_WIZARD
+// N (cr): Set Up Debug: addNotify
+// bz (N):  Filtering Net and Tracing Clock Domain : addNotify
+selectButton("NEXT", "Next >"); // JButton
+dismissDialog("Filtering Net and Tracing Clock Domain"); // bz
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_axi4lite_0/U0/RdAddrxD (12) ; ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0 ; FDRE ; Data and Trigger", 0, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_axi4lite_0/U0/RdAddrxD (12)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS ; ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0 ; LUT5 ; Data and Trigger", 12, "ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS", 0, true, true, false, false, false, false); // aq - Shift Key - Node
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+// WARNING: HEventQueue.dispatchEvent() is taking  1020 ms.
+selectButton((HResource) null, "Nets to Debug_add"); // x: TRUE
+selectButton(RDIResource.AbstractSearchablePanel_SHOW_SEARCH, "Nets to Debug_search"); // x: TRUE
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "UserxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[1].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[UserxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT3 ; Data and Trigger", 15, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[1].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[UserxD] (32)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "[IdxS"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[IdxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT1 ; Data and Trigger", 7, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[IdxS]", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "KeepxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[KeepxD] (4) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT3 ; Data and Trigger", 12, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[KeepxD] (4)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "DestxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DestxD] (4) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT3 ; Data and Trigger", 3, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DestxD] (4)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "StrbxD"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[StrbxD] (4) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 13, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[StrbxD] (4)", 0, true); // aq - Node
+typeControlKey(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, (String) null, 'a'); // aq
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+// Elapsed time: 18 seconds
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "ScalpTXSidexI"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; RAMB36E1 ; Data and Trigger", 0, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[2].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 71, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[2].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]", 0, true, false, true, false, false, false); // aq - Control Key - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; RAMB36E1 ; Data and Trigger", 0, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[2].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 71, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[2].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]", 0, true, true, false, false, false, false); // aq - Shift Key - Node
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[4].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT1 ; Data and Trigger", 24, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[4].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 95, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]", 0, false, true, false, false, false, false); // aq - Shift Key
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+setText("PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE_SEARCH_FIELD", "ScalpRXSidexI"); // OverlayTextField
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32) ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; LUT6 ; Data and Trigger", 0, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[0].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD] (32)", 0, true); // aq - Node
+selectTreeTable(PAResourceAtoD.DebugWizard_CHIPSCOPE_TREE_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS] ; ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ; FDCE ; Data and Trigger", 143, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[5].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]", 0, false, true, false, false, false, false); // aq - Shift Key
+selectButton(PAResourceAtoD.DebugWizard_REMOVE_NETS, "Nets to Debug_remove_nets"); // E
+selectButton("NEXT", "Next >"); // JButton
+selectComboBox(PAResourceAtoD.DebugWizard_SAMPLE_OF_DATA_DEPTH, "2048", 1); // e
+selectButton("NEXT", "Next >"); // JButton
+selectButton("FINISH", "Finish"); // JButton
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: DEBUG_CORE_ADD
+// TclEventType: DEBUG_GRAPH_STALE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_core u_ila_0 ila 
+// bz (N):  Set Up Debug : addNotify
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] 
+// TclEventType: DEBUG_CORE_CONFIG_CHANGE
+// Tcl Message: connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK ]] 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe0] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe1] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe2] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe3] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe4] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe5] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe6] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe7] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe8] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe9] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe10] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe11] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe12] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: set_property port_width 32 [get_debug_ports u_ila_0/probe13] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe14] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe14 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe15] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe15 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe16] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe16 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe17] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe17 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe18] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe18 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe19] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe19 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe20] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe20 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe21] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe21 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe22] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe22 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe23] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe23 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe24] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe24 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe25] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe25 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe26] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe26 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe27] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe27 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe28] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe28 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe29] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe29 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe30] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe30 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe31] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe31 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe32] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe33] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe34] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe34 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe35] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe35 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe36] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe36 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe37] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe37 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe38] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe38 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe39] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe39 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe40] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe40 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe41] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe41 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe42] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe42 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe43] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe43 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe44] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe44 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe45] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe45 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe46] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: connect_debug_port u_ila_0/probe46 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} ]] 
+// TclEventType: NETLIST_UPDATE
+// TclEventType: DEBUG_PORT_ADD
+// TclEventType: NETLIST_UPDATE
+// Tcl Message: create_debug_port u_ila_0 probe 
+// Tcl Message: set_property port_width 1 [get_debug_ports u_ila_0/probe47] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// Tcl Message: set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] 
+// TclEventType: DEBUG_PORT_CONFIG_CHANGE
+// TclEventType: NETLIST_UPDATE
+// HMemoryUtils.trashcanNow. Engine heap size: 4,111 MB. GUI used memory: 158 MB. Current time: 5/17/21, 9:58:25 AM CEST
+// Tcl Message: connect_debug_port u_ila_0/probe47 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} ]] 
+// TclEventType: DEBUG_GRAPH_STALE
+// Elapsed time: 44 seconds
+dismissDialog("Set Up Debug"); // bz
+dismissDialog("Set Up Debug"); // N
+// Run Command: PAResourceCommand.PACommandNames_SAVE_DESIGN
+// A (cr): Out of Date Design: addNotify
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// bz (cr):  Save Constraints : addNotify
+dismissDialog("Out of Date Design"); // A
+// TclEventType: DESIGN_STALE
+// TclEventType: FILE_SET_CHANGE
+// TclEventType: DESIGN_SAVE
+// TclEventType: FILESET_TARGET_UCF_CHANGE
+// Tcl Message: save_constraints 
+selectButton("OptionPane.button", "OK"); // JButton
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Generate Bitstream]", 32, false); // u
+// Run Command: PAResourceCommand.PACommandNames_RUN_BITGEN
+// A (cr): No Implementation Results Available: addNotify
+selectButton(RDIResource.BaseDialog_YES, "Yes"); // a
+// bz (cr):  Resetting Runs : addNotify
+// cD (cr): Launch Runs: addNotify
+dismissDialog("No Implementation Results Available"); // A
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// TclEventType: FILESET_TARGET_UCF_CHANGE
+dismissDialog("Launch Runs"); // cD
+// bz (cr):  Generate Bitstream : addNotify
+// Tcl Message: launch_runs impl_1 -to_step write_bitstream -jobs 3 
+// Tcl Message: Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. 
+// Tcl Message: Write XDEF Complete: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9971.891 ; gain = 0.000 ; free physical = 4977 ; free virtual = 17973 
+// TclEventType: RUN_LAUNCH
+// TclEventType: RUN_MODIFY
+// TclEventType: RUN_STATUS_CHANGE
+// Tcl Message: [Mon May 17 09:58:38 2021] Launched impl_1... Run output will be captured here: /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/runme.log 
+dismissDialog("Generate Bitstream"); // bz
+// TclEventType: RUN_STATUS_CHANGE
+// TclEventType: RUN_STEP_COMPLETED
+// TclEventType: RUN_COMPLETED
+// TclEventType: RUN_STATUS_CHANGE
+// ag (cr): Bitstream Generation Completed: addNotify
+// Elapsed time: 915 seconds
+selectRadioButton(PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER, "Open Hardware Manager"); // a
+selectButton(RDIResource.BaseDialog_OK, "OK"); // a
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl Command: 'rdi::info_commands get_hw_probes'
+// bz (cr):  Open Hardware Manager : addNotify
+// TclEventType: HW_SESSION_OPEN
+// WARNING: HEventQueue.dispatchEvent() is taking  1266 ms.
+// Tcl Message: open_hw_manager 
+dismissDialog("Open Hardware Manager"); // bz
+// Elapsed time: 20 seconds
+selectButton(PAResourceOtoP.ProgramDebugTab_OPEN_TARGET, "Open target"); // h
+selectMenuItem(PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET, "Auto Connect"); // ak
+// Run Command: PAResourceCommand.PACommandNames_AUTO_CONNECT_TARGET
+// bz (cr):  Auto Connect : addNotify
+// Tcl Message: connect_hw_server -allow_non_jtag 
+// Tcl Message: INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121 INFO: [Labtools 27-2222] Launching hw_server... 
+// TclEventType: HW_SERVER_UPDATE
+// Tcl Message: INFO: [Labtools 27-2221] Launch Output:  ****** Xilinx hw_server v2020.2   **** Build date : Nov 18 2020 at 09:50:49     ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042 INFO: [Labtools 27-3417] Launching cs_server... 
+// TclEventType: HW_SERVER_UPDATE
+// Tcl Message: INFO: [Labtools 27-2221] Launch Output:   ******** Xilinx cs_server v2020.2   ****** Build date   : Nov 03 2020-22:02:56     **** Build number : 2020.2.1604437376       ** Copyright 2017-2020 Xilinx, Inc. All Rights Reserved.    
+// TclEventType: HW_TARGET_CHANGE
+// TclEventType: HW_TARGET_CLOSE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_ADD
+// TclEventType: HW_TARGET_UPDATE
+// Tcl Message: open_hw_target 
+// Tcl Message: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210299AFC175 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.bit} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: set_property FULL_PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: current_hw_device [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// WARNING: HEventQueue.dispatchEvent() is taking  2904 ms.
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7z015_1] 0] 
+// Tcl Message: INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s). INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 2 VIO core(s). 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+dismissDialog("Auto Connect"); // bz
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectMenuItem((HResource) null, "xc7z015_1"); // ak
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl Command: 'rdi::info_commands get_hw_probes'
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+// bC (cr): Program Device: addNotify
+selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a
+// bz (cr):  Program Device : addNotify
+// TclEventType: HW_DEVICE_CHANGE
+dismissDialog("Program Device"); // bC
+// Tcl Message: set_property PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: set_property FULL_PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.bit} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_OBJECT_DELETE
+// TclEventType: HW_DEVICE_UPDATE
+// Tcl Message: program_hw_devices [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: DEBUG_PROBE_SET_CHANGE
+// TclEventType: DEBUG_PROBE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7z015_1] 0] 
+// Tcl Message: INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s). INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 2 VIO core(s). 
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_OPEN_WCFG
+// Waveform: addNotify
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// Waveform: addNotify
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// Tcl Message: display_hw_ila_data [ get_hw_ila_data hw_ila_data_1 -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// 'I' command handler elapsed time: 4 seconds
+dismissDialog("Program Device"); // bz
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectTab("PlanAheadTabBaseWorkspace_JideTabbedPane", (HResource) null, "hw_ila_1", 1); // m
+// Waveform: addNotify
+// Waveform: addNotify
+// Waveform: addNotify
+floatFrame(PAResourceOtoP.PAViews_DASHBOARD, "hw_ila_1"); // az
+// PAResourceOtoP.PAViews_DASHBOARD: hw_ila_1: float view
+// HMemoryUtils.trashcanNow. Engine heap size: 4,154 MB. GUI used memory: 217 MB. Current time: 5/17/21, 10:14:43 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS] ; ==   ; [B]   ; B ; probe20[0] ; 1 of 1", 0, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]", 0); // A
+typeControlKey(PAResourceTtoZ.TriggerSetupPanel_TABLE, (String) null, 'a'); // A
+selectButton(PAResourceItoN.IlaProbeTablePanel_REMOVE_SELECTED_PROBE, "IlaProbeTablePanel_remove"); // E
+// [GUI Memory]: 256 MB (+10168kb) [01:32:22]
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bX [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]]", 9, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectButton(PAResourceItoN.IlaProbeTablePanel_ADD_PROBES, (String) null); // E
+selectButton(PAResourceAtoD.AddIlaProbesPopup_OK, "OK"); // a
+selectTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS] ; ==   ; [B]   ; X ; probe33[0] ; ", 0, "X", 3); // A
+editTable(PAResourceTtoZ.TriggerSetupPanel_TABLE, "X", 0, "Value", 3); // A
+// TclEventType: DEBUG_PROBE_CHANGE
+// Tcl Message: set_property TRIGGER_COMPARE_VALUE eq1'bB [get_hw_probes {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+selectButton(PAResourceEtoH.HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE, "Waveform Viewer_run_trigger"); // E
+// Run Command: PAResourceCommand.PACommandNames_RUN_TRIGGER
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// Tcl Message: INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2021-May-17 10:15:12 
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 203 MB. Current time: 5/17/21, 10:15:19 AM CEST
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: HW_WAVE_ZIP_EXPORT_DONE
+// TclEventType: WAVEFORM_GLASSPANE
+// Tcl Message: display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// Tcl Message: INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2021-May-17 10:15:19 INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data. 
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Elapsed time: 12 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 278, 68); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 240 MB. Current time: 5/17/21, 10:15:24 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 197 MB. Current time: 5/17/21, 10:15:25 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 205 MB. Current time: 5/17/21, 10:15:25 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 202 MB. Current time: 5/17/21, 10:15:25 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 201 MB. Current time: 5/17/21, 10:15:25 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 210 MB. Current time: 5/17/21, 10:15:28 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 197 MB. Current time: 5/17/21, 10:15:28 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,162 MB. GUI used memory: 199 MB. Current time: 5/17/21, 10:15:28 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,163 MB. GUI used memory: 199 MB. Current time: 5/17/21, 10:15:29 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,163 MB. GUI used memory: 199 MB. Current time: 5/17/21, 10:15:29 AM CEST
+// Elapsed time: 14 seconds
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false, false, false, false, true, false); // u - Popup Trigger
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false, false, false, false, true, false); // u - Popup Trigger
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false, false, false, false, false, true); // u - Double Click
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 280, 65); // nWaveform: addNotify
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 280, 65); // nWaveform: addNotify
+dockFrame(PAResourceOtoP.PAViews_DASHBOARD, "hw_ila_1"); // az
+// PAResourceOtoP.PAViews_DASHBOARD: hw_ila_1: dock view
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,163 MB. GUI used memory: 176 MB. Current time: 5/17/21, 10:15:51 AM CEST
+selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug, Open Hardware Manager, Program Device]", 34, false); // u
+expandTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Program and Debug]", 6); // u
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+selectMenuItem((HResource) null, "xc7z015_1"); // ak
+// Run Command: PAResourceCommand.PACommandNames_OPEN_HARDWARE_MANAGER
+// Tcl Command: 'rdi::info_commands get_hw_probes'
+// Run Command: PAResourceCommand.PACommandNames_PROGRAM_FPGA
+// bC (cr): Program Device: addNotify
+selectButton(PAResourceOtoP.ProgramFpgaDialog_PROGRAM, "Program"); // a
+// bz (cr):  Program Device : addNotify
+// TclEventType: HW_DEVICE_CHANGE
+dismissDialog("Program Device"); // bC
+// Tcl Message: set_property PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// Tcl Message: set_property FULL_PROBES.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.ltx} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// Tcl Message: set_property PROGRAM.FILE {/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.bit} [get_hw_devices xc7z015_1] 
+// TclEventType: HW_OBJECT_DELETE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,163 MB. GUI used memory: 176 MB. Current time: 5/17/21, 10:15:54 AM CEST
+// Tcl Message: program_hw_devices [get_hw_devices xc7z015_1] 
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_SYSMON_CHANGE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_DEVICE_UPDATE
+// TclEventType: HW_DEVICE_CHANGE
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,163 MB. GUI used memory: 176 MB. Current time: 5/17/21, 10:15:56 AM CEST
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// Tcl Message: INFO: [Labtools 27-3164] End of startup status: HIGH 
+// Tcl Message: refresh_hw_device [lindex [get_hw_devices xc7z015_1] 0] 
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// Tcl Message: INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 1 ILA core(s). INFO: [Labtools 27-2302] Device xc7z015 (JTAG device index = 1) is programmed with a design that has 2 VIO core(s). 
+// TclEventType: HW_DEVICE_PROBES_CHANGE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// HMemoryUtils.trashcanNow. Engine heap size: 4,163 MB. GUI used memory: 176 MB. Current time: 5/17/21, 10:15:56 AM CEST
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: HW_VIO_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: HW_VIO_PROBE_VALUE_CHANGE
+// 'I' command handler elapsed time: 4 seconds
+dismissDialog("Program Device"); // bz
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Elapsed time: 17 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 276, 71); // nWaveform: addNotify
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 276, 71); // nWaveform: addNotify
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 276, 71); // nWaveform: addNotify
+floatFrame(PAResourceOtoP.PAViews_DASHBOARD, "hw_ila_1"); // az
+// PAResourceOtoP.PAViews_DASHBOARD: hw_ila_1: float view
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,159 MB. GUI used memory: 190 MB. Current time: 5/17/21, 10:16:15 AM CEST
+selectButton(RDIResource.WaveformView_ADD, "Waveform Viewer_new"); // E
+selectTree(PAResourceOtoP.ProbesView_PROBES_TREE, "[root, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]]", 19, false); // N
+selectTree(PAResourceOtoP.ProbesView_PROBES_TREE, "[root, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][0:31]]", 15, false); // N
+selectTree(PAResourceOtoP.ProbesView_PROBES_TREE, "[root, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]]", 20, false, true, false, false, false, false); // N - Shift Key
+selectButton(PAResourceAtoD.AddIlaProbesPopup_OK, "OK"); // a
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: DEBUG_PROBE_CHANGE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, Axism2s3xDN[DataxD][0:31]]", 33, true); // a - Node
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, Axism2s3xDP[ValidxS]]", 38, false, true, false, false, false, false); // a - Shift Key
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, Axism2s3xDN[DataxD][0:31]]", 33, true); // a - Node
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// Elapsed time: 10 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axism2s3xDN[ValidxS]]", 13, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Name"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Name"); // ah
+selectMenuItem((HResource) null, "Long"); // Y
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: DEBUG_PROBE_CHANGE
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]]", 13, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Name"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Radix"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenuItem((HResource) null, "Red"); // Y
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectButton(RDIResource.WaveformView_ADD, "Waveform Viewer_new"); // E
+selectTree(PAResourceOtoP.ProbesView_PROBES_TREE, "[root, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][0:31]]", 39, false); // N
+selectTree(PAResourceOtoP.ProbesView_PROBES_TREE, "[root, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]]", 44, false, true, false, false, false, false); // N - Shift Key
+selectButton(PAResourceAtoD.AddIlaProbesPopup_OK, "OK"); // a
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: DEBUG_PROBE_CHANGE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, Axism2s3xDN[DataxD][0:31]]", 33, true); // a - Node
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, Axism2s3xDP[ValidxS]]", 38, false, true, false, false, false, false); // a - Shift Key
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, Axism2s3xDN[DataxD][0:31]]", 33, true); // a - Node
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, Axism2s3xDN[LastxS]]", 31, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Name"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Radix"); // ah
+selectMenu("Radix"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Name"); // ah
+selectMenuItem((HResource) null, "Long"); // Y
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: DEBUG_PROBE_CHANGE
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]]", 32, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Name"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenuItem((HResource) null, "Red"); // Y
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+selectButton(PAResourceEtoH.HardwareIlaWaveformView_RUN_TRIGGER_FOR_THIS_ILA_CORE, "Waveform Viewer_run_trigger"); // E
+// Run Command: PAResourceCommand.PACommandNames_RUN_TRIGGER
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// Tcl Message: INFO: [Labtools 27-1964] The ILA core 'hw_ila_1' trigger was armed at 2021-May-17 10:17:27 
+// TclEventType: HW_ILA_CHANGE
+// Tcl Message: wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}] 
+// TclEventType: HW_ILA_CHANGE
+// TclEventType: WAVEFORM_GLASSPANE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_DELAYED_MODEL_EVENT
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// Tcl Message: display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xc7z015_1] -filter {CELL_NAME=~"u_ila_0"}]] 
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Tcl Message: INFO: [Labtools 27-1966] The ILA core 'hw_ila_1' triggered at 2021-May-17 10:17:36 
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// HMemoryUtils.trashcanNow. Engine heap size: 4,167 MB. GUI used memory: 187 MB. Current time: 5/17/21, 10:17:36 AM CEST
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: HW_WAVE_ZIP_EXPORT_DONE
+// TclEventType: WAVEFORM_GLASSPANE
+// Tcl Message: INFO: [Labtools 27-3304] ILA Waveform data saved to file /home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/designs/vivado/scalp_firmware/2020.2/lin64/scalp_firmware/scalp_firmware.hw/backup/hw_ila_data_1.ila. Use Tcl command 'read_hw_ila_data' or Vivado File->Import->Import ILA Data menu item to import the previously saved data. 
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_MODEL_EVENT
+// Elapsed time: 14 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 269, 119); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,159 MB. GUI used memory: 225 MB. Current time: 5/17/21, 10:17:41 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,159 MB. GUI used memory: 192 MB. Current time: 5/17/21, 10:17:41 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,159 MB. GUI used memory: 192 MB. Current time: 5/17/21, 10:17:41 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,159 MB. GUI used memory: 187 MB. Current time: 5/17/21, 10:17:41 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]]", 9, false); // a
+// HMemoryUtils.trashcanNow. Engine heap size: 4,159 MB. GUI used memory: 187 MB. Current time: 5/17/21, 10:17:46 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]]", 9, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Name"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Name"); // ah
+selectMenuItem((HResource) null, "Short"); // Y
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: DEBUG_PROBE_CHANGE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 183 MB. Current time: 5/17/21, 10:17:52 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 199 MB. Current time: 5/17/21, 10:17:56 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 198 MB. Current time: 5/17/21, 10:17:56 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 188 MB. Current time: 5/17/21, 10:17:57 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Elapsed time: 13 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axiss2m0xD[ReadyxS]]", 11, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 215 MB. Current time: 5/17/21, 10:18:03 AM CEST
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axism2s3xDP[ValidxS]]", 10, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Elapsed time: 10 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axism2s3xDP[DataxD][0:31]]", 8, true, true, false, false, false, false); // a - Shift Key - Node
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axism2s3xDP[LastxS]]", 9, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Radix"); // ah
+selectMenu("Radix"); // ah
+selectMenu("Signal Color"); // ah
+selectMenuItem((HResource) null, "Magenta"); // Y
+// TclEventType: DEBUG_PROBE_CHANGE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 202 MB. Current time: 5/17/21, 10:18:18 AM CEST
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axiss2m1xDP[ReadyxS]]", 12, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, Axism2s3xDP[DataxD][0:31]]", 33, true); // a - Node
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, Axism2s3xDP[ValidxS]]", 35, false, true, false, false, false, false); // a - Shift Key
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 187 MB. Current time: 5/17/21, 10:18:25 AM CEST
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, RX Side, Axism2s3xDP[ValidxS]]", 35, false, false, false, false, true, false); // a - Popup Trigger
+selectMenu("Name"); // ah
+selectMenu("Waveform Style"); // ah
+selectMenu("Signal Color"); // ah
+selectMenu("Radix"); // ah
+selectMenu("Radix"); // ah
+selectMenu("Signal Color"); // ah
+selectMenuItem((HResource) null, "Magenta"); // Y
+// TclEventType: DEBUG_PROBE_CHANGE
+// TclEventType: WAVEFORM_MODEL_EVENT
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_TITLE
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 450, 270); // n
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 551, 287); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 195 MB. Current time: 5/17/21, 10:18:43 AM CEST
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 201 MB. Current time: 5/17/21, 10:19:10 AM CEST
+// Elapsed time: 73 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axiss2m0xD[ReadyxS]]", 11, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Elapsed time: 12 seconds
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 275, 294); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 373, 180); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 214 MB. Current time: 5/17/21, 10:20:12 AM CEST
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 447, 153); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+selectGraphicalView(RDIResource.RDIViews_WAVEFORM_VIEWER, 561, 156); // n
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// TclEventType: WAVEFORM_UPDATE_COMMANDS
+// Elapsed time: 70 seconds
+selectTree(RDIResource.WaveformNameTree_WAVEFORM_NAME_TREE, "[true, TX Side, Axiss2m0xD[ReadyxS]]", 11, false); // a
+// TclEventType: WAVEFORM_UPDATE_WAVEFORM
+// HMemoryUtils.trashcanNow. Engine heap size: 4,160 MB. GUI used memory: 194 MB. Current time: 5/17/21, 10:21:35 AM CEST
+// TclEventType: FILE_SET_CHANGE
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh b/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh
index 6f157f0..53b4b99 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh
+++ b/designs/vivado/scalp_firmware/2020.2/lin64/setup.sh
@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: TCL script creating aliases for Vivado project management scripts
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
@@ -25,6 +25,4 @@ alias clean_project='cd .scripts && ./clean_prj_scalp_firmware.sh && cd ..'
 alias export_hw='cd .scripts && ./export_hw_scalp_firmware.sh && cd ..'
 alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_firmware.sh && cd ..'
 alias load_bitstream='cd .scripts && ./load_bitstream_scalp_firmware.sh && cd ..'
-alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_firmware.sh && cd ..'
-alias load_sw_app='cd .scripts && ./load_sw_app_scalp_firmware.sh && cd ..'
 alias open_gui='cd .scripts && ./open_prj_scalp_firmware.sh && cd ..'
diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc
index e69de29..d6bc42e 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc
+++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/debug.xdc
@@ -0,0 +1,206 @@
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 32 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 32 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 32 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 32 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 32 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 32 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 32 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 32 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 32 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 32 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 32 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 32 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 32 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][31]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][30]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][29]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][28]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][27]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][26]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][25]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][24]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][23]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][22]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][21]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][20]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][19]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][18]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][17]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][16]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][15]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][14]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][13]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][12]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][11]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][10]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][9]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][8]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][7]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][6]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][5]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][4]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][3]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][2]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][1]} {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 1 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 1 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 1 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 1 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 1 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 1 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDN[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s0xD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m0xD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDP[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDN[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[3].ScalpRouterInterfacexI/ScalpTXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s1xDP[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s2xDN[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+set_property port_width 1 [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axism2s3xDP[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDN[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list {ProgrammableLogicxB.NetworkLayerxB.ScalpRouterxI/ScalpRouterInterfacexG[6].ScalpRouterInterfacexI/ScalpRXSidexI/ScalpFifoDoubleRegisterxI/Axiss2m1xDP[ReadyxS]}]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
index 1068ab2..1ab8b93 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
+++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
@@ -251,3 +251,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
 
 
 
+
diff --git a/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
index a0d98af..dcb4ac7 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -31,3 +31,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
 
 
 
+
diff --git a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
index ac32694..7090d02 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: scalp_firmware
 --
--- Last update: 2021-05-10
+-- Last update: 2021-05-17
 --
 ---------------------------------------------------------------------------------
 
@@ -526,47 +526,26 @@ architecture arch of scalp_firmware is
     attribute keep of AuroraClkSlavexC        : signal is "true";
     attribute keep of AuroraClkMasterxC       : signal is "true";
     -- Scalp Router
-    attribute mark_debug of RXAxism2sVectorxD : signal is "true";
-    attribute keep of RXAxism2sVectorxD       : signal is "true";
-    attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
-    attribute keep of RXAxiss2mVectorxD       : signal is "true";
-    attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
-    attribute keep of TXAxiss2mVectorxD       : signal is "true";
-    attribute mark_debug of TXAxism2sVectorxD : signal is "true";
-    attribute keep of TXAxism2sVectorxD       : signal is "true";
-    -- Scalp Aurora PHY Ready -> TX Side
-    -- attribute mark_debug of NorthTXM2SxD      : signal is "true";
-    -- attribute keep of NorthTXM2SxD            : signal is "true";
-    -- attribute mark_debug of NorthTXS2MxD      : signal is "true";
-    -- attribute keep of NorthTXS2MxD            : signal is "true";
-    attribute mark_debug of EastTXM2SxD       : signal is "true";
-    attribute keep of EastTXM2SxD             : signal is "true";
-    attribute mark_debug of EastTXS2MxD       : signal is "true";
-    attribute keep of EastTXS2MxD             : signal is "true";
-    -- attribute mark_debug of SouthTXM2SxD      : signal is "true";
-    -- attribute keep of SouthTXM2SxD            : signal is "true";
-    -- attribute mark_debug of SouthTXS2MxD      : signal is "true";
-    -- attribute keep of SouthTXS2MxD            : signal is "true";
-    -- attribute mark_debug of WestTXM2SxD       : signal is "true";
-    -- attribute keep of WestTXM2SxD             : signal is "true";
-    -- attribute mark_debug of WestTXS2MxD       : signal is "true";
-    -- attribute keep of WestTXS2MxD             : signal is "true";
-    -- attribute mark_debug of NorthRXM2SxD      : signal is "true";
-    -- attribute keep of NorthRXM2SxD            : signal is "true";
-    -- attribute mark_debug of NorthRXS2MxD      : signal is "true";
-    -- attribute keep of NorthRXS2MxD            : signal is "true";
-    -- attribute mark_debug of EastRXM2SxD       : signal is "true";
-    -- attribute keep of EastRXM2SxD             : signal is "true";
-    -- attribute mark_debug of EastRXS2MxD       : signal is "true";
-    -- attribute keep of EastRXS2MxD             : signal is "true";
-    -- attribute mark_debug of SouthRXM2SxD      : signal is "true";
-    -- attribute keep of SouthRXM2SxD            : signal is "true";
-    -- attribute mark_debug of SouthRXS2MxD      : signal is "true";
-    -- attribute keep of SouthRXS2MxD            : signal is "true";
     -- attribute mark_debug of WestRXM2SxD       : signal is "true";
     -- attribute keep of WestRXM2SxD             : signal is "true";
     -- attribute mark_debug of WestRXS2MxD       : signal is "true";
     -- attribute keep of WestRXS2MxD             : signal is "true";
+    -- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
+    -- attribute keep of RXAxism2sVectorxD       : signal is "true";
+    -- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
+    -- attribute keep of RXAxiss2mVectorxD       : signal is "true";
+    -- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
+    -- attribute keep of TXAxism2sVectorxD       : signal is "true";
+    -- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
+    -- attribute keep of TXAxiss2mVectorxD       : signal is "true";
+    -- attribute mark_debug of  : signal is "true";
+    -- attribute keep of        : signal is "true";
+    -- attribute mark_debug of  : signal is "true";
+    -- attribute keep of        : signal is "true";
+    -- attribute mark_debug of  : signal is "true";
+    -- attribute keep of        : signal is "true";
+    -- attribute mark_debug of  : signal is "true";
+    -- attribute keep of        : signal is "true";
 
 begin
 
@@ -915,11 +894,14 @@ begin
             signal WrSPStatexDP                          : t_write_sp_states := E_WR_SP_IDLE_0;
             signal WrSPStatexDN                          : t_write_sp_states := E_WR_SP_IDLE_0;
             signal VioWrSpValidxS                        : std_ulogic        := '0';
+            --
+            signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
+            signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
             -- Scalp Packet
             -- attribute mark_debug of ScalpPacket0xD       : signal is "true";
             -- attribute keep of ScalpPacket0xD             : signal is "true";
-            attribute mark_debug of ScalpPacketValid12xS : signal is "true";
-            attribute keep of ScalpPacketValid12xS       : signal is "true";
+            -- attribute mark_debug of ScalpPacketValid12xS : signal is "true";
+            -- attribute keep of ScalpPacketValid12xS       : signal is "true";
             -- VIO
             -- attribute mark_debug of VioWrSpValidxS       : signal is "true";
             -- attribute keep of VioWrSpValidxS             : signal is "true";
@@ -1072,6 +1054,9 @@ begin
 
             -- end block ScalpRouterReadyxB;
 
+            -- Local Router Net Addr
+            LocNetAddrxAS : LocNetAddrxD                     <= C_SCALP_PACKET_NET_ADDR_210;
+            -- TX Side
             NorthTXM2SxAS : NorthTXM2SxD                     <= TXAxism2sVectorxD(C_NORTH_IF_ID);
             EastTXM2SxAS  : EastTXM2SxD                      <= TXAxism2sVectorxD(C_EAST_IF_ID);
             SouthTXM2SxAS : SouthTXM2SxD                     <= TXAxism2sVectorxD(C_SOUTH_IF_ID);
@@ -1080,6 +1065,7 @@ begin
             EastTXS2MxAS  : TXAxiss2mVectorxD(C_EAST_IF_ID)  <= EastTXS2MxD;
             SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
             WestTXS2MxAS  : TXAxiss2mVectorxD(C_WEST_IF_ID)  <= WestTXS2MxD;
+            -- RX Side
             NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
             EastRXM2SxAS  : RXAxism2sVectorxD(C_EAST_IF_ID)  <= EastRXM2SxD;
             SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
@@ -1088,10 +1074,35 @@ begin
             EastRXS2MxAS  : EastRXS2MxD                      <= RXAxiss2mVectorxD(C_EAST_IF_ID);
             SouthRXS2MxAS : SouthRXS2MxD                     <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
             WestRXS2MxAS  : WestRXS2MxD                      <= RXAxiss2mVectorxD(C_WEST_IF_ID);
-            -- Local Router Net Addr
-            LocNetAddrxAS : LocNetAddrxD                     <= C_SCALP_PACKET_NET_ADDR_110;
-            -- Local Ready
-            -- RXAxiss2mVectorxD(C_LOCAL_IF_ID) <= 
+
+
+
+
+
+            -- RXLinkLayerRegxP: process (AuroraClkMasterxC.UserClkxC,
+            --                            ScalpRouterResetxRNA) is
+            -- begin  -- process RXLinkLayerRegxP
+            --     if ScalpRouterResetxRNA = '0' then
+            --         RXSideLLxDP <= E_SCALP_RX_LINK_LAYER_IDLE;
+            --     elsif rising_edge(AuroraClkMasterxC.UserClkxC) then                    
+            --         RXSideLLxDP <= RXSideLLxDN;
+            --     end if;
+            -- end process RXLinkLayerRegxP;
+
+            -- RXLinkLayerxP: process is
+            -- begin  -- process RXLinkLayerxP
+            --     RXSideLLxDN <= RXSideLLxDP;
+
+            --     case RXSideLLxDP is
+            --         when E_SCALP_RX_LINK_LAYER_IDLE => ;
+            --         when E_SCALP_RX_LINK_LAYER_WAIT_ON_LAST => ;
+            --         when E_SCALP_RX_LINK_LAYER_WAIT => ;
+            --         when others => null;
+            --     end case;
+            -- end process RXLinkLayerxP;
+
+            
+            
 
             WrSpValidxI : entity work.vio_axi_cnt_ctrl
                 port map (
@@ -1124,30 +1135,17 @@ begin
                     TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
                     QoSVectorxDI       => QoSVectorxD);
 
-            ReadLocalxP : process (AuroraClkMasterxC.UserClkxC,
-                                   ScalpRouterResetxRNA) is
-            begin  -- process ReadLocalxP
-                if ScalpRouterResetxRNA = '0' then
-                    TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '0';
-                elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
-                    TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '1';
-                    -- if TXAxism2sVectorxD(C_LOCAL_IF_ID).ValidxS = '1' then
-                    --     TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '1';
-                    -- end if;
-                end if;
-            end process ReadLocalxP;
-
-            -- ScalpAxis2SPxI : entity work.scalp_axis_to_sp
-            --     generic map (
-            --         C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
-            --         C_SCALP_RANDOM_READY        => C_SCALP_RANDOM_READY)
-            --     port map (
-            --         SysClkxCI           => AuroraClkMasterxC.UserClkxC,
-            --         SysRstxRNAI         => ScalpRouterResetxRNA,
-            --         ScalpAxism2sxDI     => TXAxism2sVectorxD(C_LOCAL_IF_ID),
-            --         ScalpAxiss2mxDO     => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
-            --         ScalpPacketxDO      => ScalpPacketLocalxD,
-            --         ScalpPacketValidxSO => ScalpPacketValidLocalxS);
+            ScalpAxis2SPxI : entity work.scalp_axis_to_sp
+                generic map (
+                    C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
+                    C_SCALP_RANDOM_READY        => C_SCALP_RANDOM_READY)
+                port map (
+                    SysClkxCI           => AuroraClkMasterxC.UserClkxC,
+                    SysRstxRNAI         => ScalpRouterResetxRNA,
+                    ScalpAxism2sxDI     => TXAxism2sVectorxD(C_LOCAL_IF_ID),
+                    ScalpAxiss2mxDO     => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
+                    ScalpPacketxDO      => ScalpPacketLocalxD,
+                    ScalpPacketValidxSO => ScalpPacketValidLocalxS);
 
             WritePacketxB : block is
             begin  -- block WritePacketxB
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd b/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd
index f763f92..b8e8839 100644
--- a/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2020.2/src/sim/tb_scalp_firmware.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: Testbench for scalp_firmware
 --
--- Last update: 2021-01-15 09:27:32
+-- Last update: 2021-05-17 08:38:48
 --
 ---------------------------------------------------------------------------------
 
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000..26bb476
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-05-17 08:38:48
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+  set code [catch { set var [exec {*}$cmd] } ]
+  if { $code != 0 } { set var "" }
+
+  return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh
similarity index 54%
rename from designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh
index ae94310..80a7112 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_firmware.sh
@@ -15,22 +15,21 @@
 # Project Name: scalp_firmware
 # Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
 # Tool version: 2020.2
-# Description: Generate software application
+# Description: Cleanup Vitis SDK workspace directory
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
+echo "> Cleanup SDK workspace directory..."
+
 PRJ_DIR=..
 
-echo "> Generate software applications..."
-xsdk -batch -source ./gen_sw_apps_scalp_firmware.tcl -notrace
+# Clean current directory
+rm -rf ./xrc.log/ 2> /dev/null
+rm -rf ./.Xil/ 2> /dev/null
 
-echo "> Copy application file in current directory..."
-mkdir -p ${PRJ_DIR}/app/
-cp ${PRJ_DIR}/scalp_firmware/scalp_firmware.sdk/scalp_firmware_app/Debug/scalp_firmware_app.elf ${PRJ_DIR}/app/scalp_firmware_app.elf
-cp ${PRJ_DIR}/scalp_firmware/scalp_firmware.sdk/scalp_firmware_hw_platform_0/system.hdf ${PRJ_DIR}/app/scalp_firmware.hdf
-cp ${PRJ_DIR}/scalp_firmware/scalp_firmware.sdk/scalp_firmware_hw_platform_0/ps7_init.tcl ${PRJ_DIR}/app/ps7_init.tcl
+# Remove generated workspace directory
+rm -rf ${PRJ_DIR}/vitis_workspace/ 2> /dev/null
 
 echo "> Done"
-
diff --git a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh
similarity index 79%
rename from designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
rename to designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh
index 33fb86a..eb65f07 100755
--- a/designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.sh
@@ -15,13 +15,12 @@
 # Project Name: scalp_firmware
 # Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
 # Tool version: 2020.2
-# Description: Load software application
+# Description: Generate Vitis workspace for software applications
 #
-# Last update: 2021-01-15 09:27:32
+# Last update: 2021-05-17 08:38:48
 #
 ##################################################################################
 
-echo "> Load software application..."
-xsdk -batch -source ./load_sw_app_scalp_firmware.tcl -notrace
+echo "> Generate Vitis workspace software applications"
+xsct gen_sw_apps_scalp_firmware.tcl
 echo "> Done"
-
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl
new file mode 100644
index 0000000..92af1fa
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_firmware.tcl
@@ -0,0 +1,101 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vitis workspace
+#
+# Last update: 2021-05-17 08:38:48
+#
+##################################################################################
+
+#
+# Include files
+#
+source utils.tcl
+
+#
+# Procedures
+#
+# Create source directories and import application source files
+proc import_app_sources {prj_workspace app_name app_src_path} {
+	puts "Import application source file into workspace..."
+
+	# Create workspace application directory
+	set ws_app_src_dir "${prj_workspace}/${app_name}/src"
+	file mkdir "${ws_app_src_dir}"
+	print_status "Create app directory into workspace: ${ws_app_src_dir}" "OK"
+
+	foreach f [glob -nocomplain -directory ${app_src_path} *] {
+		file copy -force $f ${ws_app_src_dir}
+		print_status "Copy $f into ${ws_app_src_dir}" "OK"
+	}
+}
+
+#
+# Generate workspace
+#
+
+# Set variables
+set pwd [pwd]
+
+set prj_workspace "../vitis_workspace"
+
+set prj_platform "scalp_firmware"
+set prj_desc "Zynq platform project"
+set prj_xsa "${pwd}/../hw_export/scalp_firmware.xsa"
+
+# Generate default application for APU0
+# APU0 - Cortex-A9
+set apu_0_prj_proc "ps7_cortexa9_0"
+set apu_0_prj_os "standalone"
+
+set apu_0_domain_name "standalone_apu0_domain"
+
+set apu_0_app_sysprj "scalp_firmware_app_system"
+set apu_0_app_template "Empty Application"
+
+set apu_0_app_name "scalp_firmware_app"
+set apu_0_app_src_dir "${pwd}/../sw_apps/scalp_firmware_app/src"
+
+# Create the workspace
+file mkdir $prj_workspace
+setws $prj_workspace
+
+# Create the platform from the XSA (Xilinx Shell Archive) file
+platform create -name $prj_platform -desc $prj_desc -hw $prj_xsa 
+
+# Create a domain for the APU (Core_0)
+domain create -name ${apu_0_domain_name} -proc ${apu_0_prj_proc} -os ${apu_0_prj_os}
+
+# Setup the APU_0 domain
+domain active ${apu_0_domain_name}
+# Example of how to add libraries to the BSP
+#bsp setlib -name xilfpga
+#bsp setlib -name xilsecure
+
+# Build the platform
+platform active ${prj_platform}
+platform generate
+
+# Build the APU_0 domain
+domain active ${apu_0_domain_name}
+# Create an application for APU Core_0
+app create -name ${apu_0_app_name} -sysproj ${apu_0_app_sysprj} -platform ${prj_platform} -domain ${apu_0_domain_name} -proc ${apu_0_prj_proc} -os ${apu_0_prj_os} -template ${apu_0_app_template} -lang {c}
+# Add application sources
+# Sources are copied into the workspace directory
+import_app_sources ${prj_workspace} ${apu_0_app_name} ${apu_0_app_src_dir}
+# Set includes path
+app config -name ${apu_0_app_name} -add include-path {"${workspace_loc:/${ProjName}/src/inc}"}
+# Build application
+app build ${apu_0_app_name}
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh
new file mode 100755
index 0000000..d4f8666
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/open_sdk_scalp_firmware.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open the Vitis workspace
+#
+# Last update: 2021-05-17 08:38:48
+#
+##################################################################################
+
+echo "> Open Vitis workspace..."
+vitis -workspace ../vitis_workspace
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/utils.tcl b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/utils.tcl
new file mode 100644
index 0000000..6f8668e
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Laurent Gantel <laurent.gantel@hesge.ch>
+#
+# Project Name: t01_demo_platform
+# Target Device: em.avnet.com:zed:part0:1.4 xc7z020clg484-1
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2019-12-09 09:06:01
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+    # Fix the directory name, this ensures the directory name is in the
+    # native format for the platform and contains a final directory seperator
+    set basedir [string trimright [file join [file normalize $basedir] { }]]
+    set fileList {}
+
+    # Look in the current directory for matching files, -type {f r}
+    # means ony readable normal files are looked at, -nocomplain stops
+    # an error being thrown if the returned list is empty
+    foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+        lappend fileList $fileName
+    }
+
+    # Now look for any sub direcories in the current directory
+    foreach dirName [glob -nocomplain -type {d  r} -path $basedir *] {
+        # Recusively call the routine on the sub directory and append any
+        # new files to the results
+        set subDirList [findFiles $dirName $pattern]
+        if { [llength $subDirList] > 0 } {
+            foreach subDirFile $subDirList {
+                lappend fileList $subDirFile
+            }
+        }
+    }
+    return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+    set MAX_STR_LENGTH 70
+    source .prompt_colors.tcl
+    puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh b/designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh
new file mode 100755
index 0000000..26924a8
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/setup.sh
@@ -0,0 +1,27 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vitis workspace management scripts
+#
+# Last update: 2021-05-17 08:38:48
+#
+##################################################################################
+
+# Create aliases
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_firmware.sh && cd ..'
+# TODO: Not supported yet
+#alias load_sw_app='cd .scripts && ./load_sw_app_scalp_firmware.sh && cd ..'
+alias open_sdk='cd .scripts && ./open_sdk_scalp_firmware.sh && cd ..'
+alias clean_sdk='cd .scripts && ./clean_sdk_scalp_firmware.sh && cd ..'
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h
new file mode 100644
index 0000000..d679701
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/inc/scalp_firmware_app.h
@@ -0,0 +1,48 @@
+/*-----------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+-------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- File Name: scalp_firmware_app.h
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Software application
+--
+-- Last update: 2021-05-17 08:38:48
+--
+-----------------------------------------------------------------------------*/
+
+#ifndef SCALP_FIRMWARE_APP_H
+#define SCALP_FIRMWARE_APP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------
+// Constants
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Types
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Functions
+//--------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SCALP_FIRMWARE_APP_H
diff --git a/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c
new file mode 100644
index 0000000..f582ef2
--- /dev/null
+++ b/designs/vivado/scalp_firmware/2020.2/src/sw/sw_apps/scalp_firmware_app/src/scalp_firmware_app.c
@@ -0,0 +1,60 @@
+/*-----------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+-------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- File Name: scalp_firmware_app.c
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Software application
+--
+-- Last update: 2021-05-17 08:38:48
+--
+-----------------------------------------------------------------------------*/
+
+/* Xilinx includes. */
+#include "xil_printf.h"
+#include "xparameters.h"
+
+
+/*----------------------------------------------------------------
+// Constants
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Variables
+//--------------------------------------------------------------*/
+/** @brief Software version */
+const char * APP_VERSION = "0.0.1";
+
+
+/*----------------------------------------------------------------
+// Static Functions
+//--------------------------------------------------------------*/
+
+
+/*----------------------------------------------------------------
+// Functions
+//--------------------------------------------------------------*/
+
+/**
+ * @brief Main entry point
+ */
+int main( void )
+{
+
+	//----------------------------------------------------------------
+  xil_printf( "\r\n-- scalp_firmware app v%s\r\n", APP_VERSION);
+  xil_printf("-- %s - %s\r\n", __DATE__,__TIME__);
+
+  // Endless loop
+	for( ;; );
+}
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc
index c3376ce..9b1ff13 100644
--- a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc
@@ -1,3 +1,4 @@
+
 create_debug_core u_ila_0 ila
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
 set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
@@ -15,19 +16,19 @@ connect_debug_port u_ila_0/probe0 [get_nets [list {ProcessingSystemxB.ZynqxI/Sca
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
 set_property port_width 12 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[11]}]]
+connect_debug_port u_ila_0/probe1 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[11]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 12 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[11]}]]
+set_property port_width 32 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[31]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
 set_property port_width 32 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[31]}]]
+connect_debug_port u_ila_0/probe3 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[31]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
-set_property port_width 32 [get_debug_ports u_ila_0/probe4]
-connect_debug_port u_ila_0/probe4 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[31]}]]
+set_property port_width 12 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[11]}]]
 create_debug_port u_ila_0 probe
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
 set_property port_width 1 [get_debug_ports u_ila_0/probe5]
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
index 1c6f118..bc54518 100644
--- a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
@@ -251,3 +251,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
 
 
 
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
index 4e6bc99..0d3d691 100644
--- a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -31,3 +31,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
 
 
 
+
diff --git a/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd b/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
index 45e2f64..976e7b6 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_axis_to_sp.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.1
 -- Description: AXI Stream to Scalp Packet converter.
 --
--- Last update: 2020-12-22
+-- Last update: 2021-05-10
 --
 ---------------------------------------------------------------------------------
 library ieee;
@@ -78,7 +78,7 @@ entity scalp_axis_to_sp is
 
     generic (
         C_SCALP_PACKET_PAYLOAD_SIZE : integer range 1 to C_SCALP_PACKET_LENGTH_RANGE_VALUE := 8;
-        C_SCALP_RANDOM_READY        : boolean                                              := true);
+        C_SCALP_RANDOM_READY        : boolean                                              := false);
 
     port (
         -- Sys clk and sys nrst
diff --git a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
index e6ecfa7..6c135a1 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.1
 -- Description: Small fifo built with two registers.
 --
--- Last update: 2020-11-30
+-- Last update: 2021-05-17
 --
 ---------------------------------------------------------------------------------
 library ieee;
@@ -56,19 +56,48 @@ architecture behavioral of scalp_fifo_double_register is
     signal Axism2s1xDN : t_axi4m2s := C_NO_AXI4_M2S;
     signal Axism2s2xDP : t_axi4m2s := C_NO_AXI4_M2S;
     signal Axism2s2xDN : t_axi4m2s := C_NO_AXI4_M2S;
-    signal Axism2s3xD  : t_axi4m2s := C_NO_AXI4_M2S;
+    -- signal Axism2s3xD  : t_axi4m2s := C_NO_AXI4_M2S;
+    signal Axism2s3xDN : t_axi4m2s := C_NO_AXI4_M2S;
+    signal Axism2s3xDP : t_axi4m2s := C_NO_AXI4_M2S;
     -- Axis Ready
     signal Axiss2m0xD  : t_axi4s2m := C_NO_AXI4_S2M;
     signal Axiss2m1xDP : t_axi4s2m := C_NO_AXI4_S2M;
     signal Axiss2m1xDN : t_axi4s2m := C_NO_AXI4_S2M;
 
+    -- Attributes
+    attribute mark_debug                : string;
+    attribute keep                      : string;
+    --
+    attribute mark_debug of Axism2s0xD  : signal is "true";
+    attribute keep of Axism2s0xD        : signal is "true";
+    attribute mark_debug of Axism2s1xDP : signal is "true";
+    attribute keep of Axism2s1xDP       : signal is "true";
+    attribute mark_debug of Axism2s1xDN : signal is "true";
+    attribute keep of Axism2s1xDN       : signal is "true";
+    attribute mark_debug of Axism2s2xDP : signal is "true";
+    attribute keep of Axism2s2xDP       : signal is "true";
+    attribute mark_debug of Axism2s2xDN : signal is "true";
+    attribute keep of Axism2s2xDN       : signal is "true";
+    -- attribute mark_debug of Axism2s3xD  : signal is "true";
+    -- attribute keep of Axism2s3xD        : signal is "true";
+    attribute mark_debug of Axism2s3xDN : signal is "true";
+    attribute keep of Axism2s3xDN       : signal is "true";
+    attribute mark_debug of Axism2s3xDP : signal is "true";
+    attribute keep of Axism2s3xDP       : signal is "true";
+    attribute mark_debug of Axiss2m0xD  : signal is "true";
+    attribute keep of Axiss2m0xD        : signal is "true";
+    attribute mark_debug of Axiss2m1xDP : signal is "true";
+    attribute keep of Axiss2m1xDP       : signal is "true";
+    attribute mark_debug of Axiss2m1xDN : signal is "true";
+    attribute keep of Axiss2m1xDN       : signal is "true";
+
 begin  -- architecture behavioral
 
     EntityIOxB : block is
     begin  -- block EntityIOxB
         -- Axis m2s
         Axism2s0FromxAS : Axism2s0xD     <= Axism2sLinkxDI;
-        Axism2s3ToxAS   : Axism2sLinkxDO <= Axism2s3xD;
+        Axism2s3ToxAS   : Axism2sLinkxDO <= Axism2s3xDP;
         -- Axis s2m
         Axiss2m0FromxAS : Axiss2m0xD     <= Axiss2mLinkxDI;
         Axiss2m1FromxAS : Axiss2m1xDN    <= Axiss2m0xD;
@@ -77,10 +106,10 @@ begin  -- architecture behavioral
 
     AsyncStatementsxB : block is
     begin  -- block AsyncStatementsxB        
-        Axism2s3FromxAS : Axism2s3xD <= Axism2s1xDP when
-                                        (Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1') or
-                                        (Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '1') else
-                                        Axism2s2xDP;
+        Axism2s3FromxAS : Axism2s3xDN <= Axism2s1xDP when
+                                         (Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1') or
+                                         (Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '1') else
+                                         Axism2s2xDP;
     end block AsyncStatementsxB;
 
     UpdateRegxP : process (SysClkxCI, SysRstxRNAI) is
@@ -89,6 +118,7 @@ begin  -- architecture behavioral
             -- Axis m2s
             Axism2s1xDP <= C_NO_AXI4_M2S;
             Axism2s2xDP <= C_NO_AXI4_M2S;
+            Axism2s3xDP <= C_NO_AXI4_M2S;
             -- Axis s2m
             Axiss2m1xDP <= C_NO_AXI4_S2M;
         -- Enable Port
@@ -97,6 +127,7 @@ begin  -- architecture behavioral
             -- Axis m2s
             Axism2s1xDP <= Axism2s1xDN;
             Axism2s2xDP <= Axism2s2xDN;
+            Axism2s3xDP <= Axism2s3xDN;
             -- Axis s2m
             Axiss2m1xDP <= Axiss2m1xDN;
         -- Enable Port
diff --git a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
index 5150dc1..8b8123b 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_misc.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2018.2
 -- Description: Scalp Miscellanous
 --
--- Last update: 2020-12-07
+-- Last update: 2021-05-12
 --
 ---------------------------------------------------------------------------------
 library ieee;
@@ -61,7 +61,8 @@ package scalp_misc is
     -- Scalp Tx Side States
     type t_scalp_tx_side_states is (E_SCALP_TX_IDLE,
                                     E_SCALP_TX_WAIT_BOOKING_VECTOR,
-                                    E_SCALP_TX_POP_N_PUSH);
+                                    E_SCALP_TX_POP_N_PUSH,
+                                    E_SCALP_TX_WAIT_ACK);
 
     -- Scalp Rx Side States
     type t_scalp_rx_side_states is (E_SCALP_RX_IDLE,
@@ -79,6 +80,11 @@ package scalp_misc is
                                    E_SP_P,
                                    E_SP_P_LAST);
 
+    -- Scalp RX Link Layer States
+    type t_scalp_rx_link_layer_states is (E_SCALP_RX_LINK_LAYER_IDLE,
+                                          E_SCALP_RX_LINK_LAYER_WAIT_ON_LAST,
+                                          E_SCALP_RX_LINK_LAYER_WAIT);
+
     type t_scalp_netaddr is record
         XxD : integer range 0 to C_SCALP_X_RANGE_VALUE;
         YxD : integer range 0 to C_SCALP_Y_RANGE_VALUE;
diff --git a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
index f6c853d..3adedb2 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_router_interface.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.1
 -- Description: Scalp Router Interface.
 --
--- Last update: 2021-05-04
+-- Last update: 2021-05-12
 --
 ---------------------------------------------------------------------------------
 library ieee;
@@ -94,7 +94,7 @@ architecture rtl of scalp_router_interface is
             DstRouterNetAddrxDO   : out t_scalp_netaddr;
             RouterNetAddrValidxSO : out std_ulogic;
             BookingVectorValidxSI : in  std_ulogic;
-            -- SchedulerAckxDI       : in  std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
+            SchedulerAckxDI       : in  std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
             RXAxi4M2SLinkxDI      : in  t_axi4m2s;
             RXAxi4S2MLinkxDO      : out t_axi4s2m;
             TXAxi4M2SLinkxDO      : out t_axi4m2s;
@@ -217,21 +217,21 @@ architecture rtl of scalp_router_interface is
     signal DTXAxi4S2MLinkxD     : t_axi4s2m                                                           := C_NO_AXI4_S2M;
 
     -- Attributes
-    attribute mark_debug : string;
-    attribute keep       : string;
+    attribute mark_debug                     : string;
+    attribute keep                           : string;
     --
-    -- attribute mark_debug of TXAxi4S2MLinkxD  : signal is "true";
-    -- attribute keep of TXAxi4S2MLinkxD        : signal is "true";
-    -- attribute mark_debug of TXAxi4s2mLinksxD : signal is "true";
-    -- attribute keep of TXAxi4s2mLinksxD       : signal is "true";
-    -- attribute mark_debug of TXAxi4s2mIfxD    : signal is "true";
-    -- attribute keep of TXAxi4s2mIfxD          : signal is "true";
+    -- attribute mark_debug of RXAxi4m2sIfxD    : signal is "true";
+    -- attribute keep of RXAxi4m2sIfxD          : signal is "true";
     -- attribute mark_debug of RXAxi4s2mIfxD    : signal is "true";
     -- attribute keep of RXAxi4s2mIfxD          : signal is "true";
+    -- attribute mark_debug of TXAxi4M2SLinkxD  : signal is "true";
+    -- attribute keep of TXAxi4M2SLinkxD        : signal is "true";
+    -- attribute mark_debug of TXAxi4S2MLinkxD  : signal is "true";
+    -- attribute keep of TXAxi4S2MLinkxD        : signal is "true";    
+    -- attribute mark_debug of TXAxi4m2sLinksxD : signal is "true";
+    -- attribute keep of TXAxi4m2sLinksxD       : signal is "true";
     -- attribute mark_debug of TXAxi4s2mLinksxD : signal is "true";
     -- attribute keep of TXAxi4s2mLinksxD       : signal is "true";
-    -- attribute mark_debug of RXAxi4s2mLinksxD : signal is "true";
-    -- attribute keep of RXAxi4s2mLinksxD       : signal is "true";
 
 begin  -- architecture rtl
 
@@ -262,7 +262,7 @@ begin  -- architecture rtl
             DstRouterNetAddrxDO   => DstRouterNetAddrxD,
             RouterNetAddrValidxSO => RouterNetAddrValidxS,
             BookingVectorValidxSI => BookingVectorValidxS,
-            -- SchedulerAckxDI       => SchedulerAckxD,
+            SchedulerAckxDI       => SchedulerAckxD,
             RXAxi4M2SLinkxDI      => RXAxi4m2sIfxD,
             RXAxi4S2MLinkxDO      => RXAxi4s2mIfxD,
             TXAxi4M2SLinkxDO      => TXAxi4M2SLinkxD,
diff --git a/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
index 9664a43..706c952 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_rx_side.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.1
 -- Description: Scalp RX side state machine.
 --
--- Last update: 2021-05-05
+-- Last update: 2021-05-11
 --
 ---------------------------------------------------------------------------------
 library ieee;
@@ -93,8 +93,8 @@ architecture behavioral of scalp_rx_side is
 
     -- Enity IO Signals
     signal SchedulerAckxD   : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0)                   := (others => '0');
-    signal BookingVectorxDP : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0)                   := (others => '0');
-    signal BookingVectorxDN : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0)                   := (others => '0');
+    -- signal BookingVectorxDP : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0)                   := (others => '0');
+    -- signal BookingVectorxDN : std_ulogic_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0)                   := (others => '0');
     signal TXAxi4M2SLinkxD  : t_axi4m2s                                                                         := C_NO_AXI4_M2S;
     signal TXAxi4S2MLinkxD  : t_axi4s2m                                                                         := C_NO_AXI4_S2M;
     signal RXAxi4M2SLinkxD  : t_axi4m2s_vector((C_SCALP_NEIGHBORS_VECTOR_SIZE - 1) downto 0)                    := (others => C_NO_AXI4_M2S);
@@ -119,8 +119,30 @@ architecture behavioral of scalp_rx_side is
     attribute mark_debug                     : string;
     attribute keep                           : string;
     --
+    -- attribute mark_debug of TXAxi4M2SLinkxD  : signal is "true";
+    -- attribute keep of TXAxi4M2SLinkxD        : signal is "true";
     -- attribute mark_debug of TXAxi4S2MLinkxD  : signal is "true";
     -- attribute keep of TXAxi4S2MLinkxD        : signal is "true";
+    -- attribute mark_debug of RXAxi4M2SLinkxD  : signal is "true";
+    -- attribute keep of RXAxi4M2SLinkxD        : signal is "true";
+    -- attribute mark_debug of RXAxi4S2MLinkxD  : signal is "true";
+    -- attribute keep of RXAxi4S2MLinkxD        : signal is "true";
+    -- attribute mark_debug of BookingVectorxDP : signal is "true";
+    -- attribute keep of BookingVectorxDP       : signal is "true";
+    -- attribute mark_debug of BookingVectorxDN : signal is "true";
+    -- attribute keep of BookingVectorxDN       : signal is "true";
+    -- attribute mark_debug of SchedulerAckxD   : signal is "true";
+    -- attribute keep of SchedulerAckxD         : signal is "true";
+    -- attribute mark_debug of RequestVectorxDP : signal is "true";
+    -- attribute keep of RequestVectorxDP       : signal is "true";
+    -- attribute mark_debug of RequestVectorxDN : signal is "true";
+    -- attribute keep of RequestVectorxDN       : signal is "true";
+    -- attribute mark_debug of ArbitratexS      : signal is "true";
+    -- attribute keep of ArbitratexS            : signal is "true";
+    -- attribute mark_debug of ArbitratedxS     : signal is "true";
+    -- attribute keep of ArbitratedxS           : signal is "true";
+    -- attribute mark_debug of GrantIndexxD     : signal is "true";
+    -- attribute keep of GrantIndexxD           : signal is "true";
     -- attribute mark_debug of RXSideStatexDP   : signal is "true";
     -- attribute keep of RXSideStatexDP         : signal is "true";
     -- attribute mark_debug of RXSideStatexDN   : signal is "true";
@@ -129,22 +151,10 @@ architecture behavioral of scalp_rx_side is
     -- attribute keep of ReadyInxD              : signal is "true";
     -- attribute mark_debug of ReadyOutxD       : signal is "true";
     -- attribute keep of ReadyOutxD             : signal is "true";
-    -- attribute mark_debug of ArbitratexS      : signal is "true";
-    -- attribute keep of ArbitratexS            : signal is "true";
-    -- attribute mark_debug of RequestVectorxDP : signal is "true";
-    -- attribute keep of RequestVectorxDP       : signal is "true";
-    -- attribute mark_debug of ArbitratedxS     : signal is "true";
-    -- attribute keep of ArbitratedxS           : signal is "true";
-    -- attribute mark_debug of GrantIndexxD     : signal is "true";
-    -- attribute keep of GrantIndexxD           : signal is "true";
-    -- attribute mark_debug of RequestVectorxDN : signal is "true";
-    -- attribute keep of RequestVectorxDN       : signal is "true";
-    -- attribute mark_debug of SchedulerAckxD   : signal is "true";
-    -- attribute keep of SchedulerAckxD         : signal is "true";
-    -- attribute mark_debug of RXAxi4S2MLinkxD  : signal is "true";
-    -- attribute keep of RXAxi4S2MLinkxD        : signal is "true";
-    -- attribute mark_debug of RXAxi4M2SLinkxD  : signal is "true";
-    -- attribute keep of RXAxi4M2SLinkxD        : signal is "true";
+    -- attribute mark_debug of EnPopNPushxS     : signal is "true";
+    -- attribute keep of EnPopNPushxS           : signal is "true";
+    -- attribute mark_debug of Axism2sInxD      : signal is "true";
+    -- attribute keep of Axism2sInxD            : signal is "true";
 
 begin  -- architecture behavioral
 
@@ -204,7 +214,7 @@ begin  -- architecture behavioral
             RXSideStatexDP   <= RXSideStatexDN;
             RequestVectorxDP <= RequestVectorxDN;
         end if;
-    end process UpdateRegxP;
+    end process UpdateRegxP;    
 
     RxSideStateMachinexP : process (ArbitratedxS, BookingVectorxDI,
                                     GrantIndexxD, RXAxi4M2SLinkxD,
@@ -243,7 +253,8 @@ begin  -- architecture behavioral
                     EnPopNPushxS                                        <= '1';
 
                     if TXAxi4M2SLinkxD.LastxS = '1' then
-                        RXSideStatexDN <= E_SCALP_RX_ACK;
+                        -- RXAxi4S2MLinkxD <= (others => C_NO_AXI4_S2M); --
+                        RXSideStatexDN  <= E_SCALP_RX_ACK;
                     end if;
 
             when E_SCALP_RX_ACK =>
diff --git a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
index a2a2f37..cee0bba 100644
--- a/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
+++ b/ips/hw/scalp_router/src/hdl/scalp_tx_side.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.1
 -- Description: Scalp TX side state machine.
 --
--- Last update: 2021-05-04
+-- Last update: 2021-05-11
 --
 ---------------------------------------------------------------------------------
 library ieee;
@@ -47,7 +47,7 @@ entity scalp_tx_side is
         -- Indicates when the booking vector is valid.
         BookingVectorValidxSI : in  std_ulogic;
         -- Scheduler Acknowledgement Vector
-        -- SchedulerAckxDI       : in  std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
+        SchedulerAckxDI       : in  std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0);
         -- Axi4 Stream
         -- Input side
         RXAxi4M2SLinkxDI      : in  t_axi4m2s;
@@ -73,32 +73,54 @@ architecture behavioral of scalp_tx_side is
             Axiss2mLinkxDI : in  t_axi4s2m);
     end component scalp_fifo_double_register;
 
-    signal DstRouterNetAddrxDP   : t_scalp_netaddr        := C_3D_MIN_SCALP_NETADDR;
-    signal DstRouterNetAddrxDN   : t_scalp_netaddr        := C_3D_MIN_SCALP_NETADDR;
-    signal RouterNetAddrValidxSP : std_ulogic             := '0';
-    signal RouterNetAddrValidxSN : std_ulogic             := '0';
-    signal BookingVectorValidxS  : std_ulogic             := '0';
-    -- signal SchedulerAckxD        : std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0) := (others => '0');
-    signal RXAxi4M2SLinkxD       : t_axi4m2s              := C_NO_AXI4_M2S;
-    signal RXAxi4S2MLinkxD       : t_axi4s2m              := C_NO_AXI4_S2M;
-    signal TXAxi4M2SLinkxD       : t_axi4m2s              := C_NO_AXI4_M2S;
-    signal TXAxi4S2MLinkxD       : t_axi4s2m              := C_NO_AXI4_S2M;
+    signal DstRouterNetAddrxDP   : t_scalp_netaddr                                                     := C_3D_MIN_SCALP_NETADDR;
+    signal DstRouterNetAddrxDN   : t_scalp_netaddr                                                     := C_3D_MIN_SCALP_NETADDR;
+    signal RouterNetAddrValidxSP : std_ulogic                                                          := '0';
+    signal RouterNetAddrValidxSN : std_ulogic                                                          := '0';
+    signal BookingVectorValidxS  : std_ulogic                                                          := '0';
+    signal SchedulerAckxD        : std_ulogic_vector((C_SCALP_SCHEDULER_ACK_VECTOR_SIZE - 1) downto 0) := (others => '0');
+    signal RXAxi4M2SLinkxD       : t_axi4m2s                                                           := C_NO_AXI4_M2S;
+    signal RXAxi4S2MLinkxD       : t_axi4s2m                                                           := C_NO_AXI4_S2M;
+    signal TXAxi4M2SLinkxD       : t_axi4m2s                                                           := C_NO_AXI4_M2S;
+    signal TXAxi4S2MLinkxD       : t_axi4s2m                                                           := C_NO_AXI4_S2M;
     -- TX Side States
-    signal TXSideStatexDP        : t_scalp_tx_side_states := E_SCALP_TX_IDLE;
-    signal TXSideStatexDN        : t_scalp_tx_side_states := E_SCALP_TX_IDLE;
+    signal TXSideStatexDP        : t_scalp_tx_side_states                                              := E_SCALP_TX_IDLE;
+    signal TXSideStatexDN        : t_scalp_tx_side_states                                              := E_SCALP_TX_IDLE;
     -- Others
-    signal ReadyInxD             : t_axi4s2m              := C_NO_AXI4_S2M;
-    signal EnPopNPushxS          : std_ulogic             := '0';
+    signal ReadyInxD             : t_axi4s2m                                                           := C_NO_AXI4_S2M;
+    signal EnPopNPushxS          : std_ulogic                                                          := '0';
 
-    attribute mark_debug                   : string;
-    attribute keep                         : string;
+    attribute mark_debug                          : string;
+    attribute keep                                : string;
     --
-    -- attribute mark_debug of TXSideStatexDP : signal is "true";
-    -- attribute keep of TXSideStatexDP       : signal is "true";
-    -- attribute mark_debug of TXSideStatexDN : signal is "true";
-    -- attribute keep of TXSideStatexDN       : signal is "true";
-    -- attribute mark_debug of ReadyInxD      : signal is "true";
-    -- attribute keep of ReadyInxD            : signal is "true";
+    -- attribute mark_debug of DstRouterNetAddrxDP   : signal is "true";
+    -- attribute keep of DstRouterNetAddrxDP         : signal is "true";
+    -- attribute mark_debug of DstRouterNetAddrxDN   : signal is "true";
+    -- attribute keep of DstRouterNetAddrxDN         : signal is "true";
+    -- attribute mark_debug of RouterNetAddrValidxSP : signal is "true";
+    -- attribute keep of RouterNetAddrValidxSP       : signal is "true";
+    -- attribute mark_debug of RouterNetAddrValidxSN : signal is "true";
+    -- attribute keep of RouterNetAddrValidxSN       : signal is "true";
+    -- attribute mark_debug of BookingVectorValidxS  : signal is "true";
+    -- attribute keep of BookingVectorValidxS        : signal is "true";
+    -- attribute mark_debug of SchedulerAckxD        : signal is "true";
+    -- attribute keep of SchedulerAckxD              : signal is "true";
+    -- attribute mark_debug of RXAxi4M2SLinkxD       : signal is "true";
+    -- attribute keep of RXAxi4M2SLinkxD             : signal is "true";
+    -- attribute mark_debug of RXAxi4S2MLinkxD       : signal is "true";
+    -- attribute keep of RXAxi4S2MLinkxD             : signal is "true";
+    -- attribute mark_debug of TXAxi4M2SLinkxD       : signal is "true";
+    -- attribute keep of TXAxi4M2SLinkxD             : signal is "true";
+    -- attribute mark_debug of TXAxi4S2MLinkxD       : signal is "true";
+    -- attribute keep of TXAxi4S2MLinkxD             : signal is "true";
+    -- attribute mark_debug of TXSideStatexDP        : signal is "true";
+    -- attribute keep of TXSideStatexDP              : signal is "true";
+    -- attribute mark_debug of TXSideStatexDN        : signal is "true";
+    -- attribute keep of TXSideStatexDN              : signal is "true";
+    -- attribute mark_debug of ReadyInxD             : signal is "true";
+    -- attribute keep of ReadyInxD                   : signal is "true";
+    -- attribute mark_debug of EnPopNPushxS          : signal is "true";
+    -- attribute keep of EnPopNPushxS                : signal is "true";
 
 begin  -- architecture behavioral
 
@@ -107,7 +129,7 @@ begin  -- architecture behavioral
     EntityIOxB : block is
     begin  -- block EntityIOxB
         DstRouterNetAddrxAS   : DstRouterNetAddrxDO   <= DstRouterNetAddrxDP;
-        -- SchedulerAckxAS       : SchedulerAckxD        <= SchedulerAckxDI;
+        SchedulerAckxAS       : SchedulerAckxD        <= SchedulerAckxDI;
         RXAxi4M2SLinkxAS      : RXAxi4M2SLinkxD       <= RXAxi4M2SLinkxDI;
         RXAxi4S2MLinkxAS      : RXAxi4S2MLinkxDO      <= RXAxi4S2MLinkxD;
         TXAxi4M2SLinkxAS      : TXAxi4M2SLinkxDO      <= TXAxi4M2SLinkxD;
@@ -179,9 +201,16 @@ begin  -- architecture behavioral
                     EnPopNPushxS <= '1';
 
                     if TXAxi4M2SLinkxD.LastxS = '1' then
+                        -- EnPopNPushxS   <= '0';  --
+                        -- TXSideStatexDN <= E_SCALP_TX_WAIT_ACK;
                         TXSideStatexDN <= E_SCALP_TX_IDLE;
                     end if;
 
+                    -- when E_SCALP_TX_WAIT_ACK =>
+                    --         if SchedulerAckxD(0) = '1' then
+                    --             TXSideStatexDN <= E_SCALP_TX_IDLE;
+                    --         end if;
+
             when others => null;
         end case;
     end process TXSideStateMachinexP;
diff --git a/ips/hw/scalp_rx_link_layer/src/hdl/scalp_rx_link_layer.vhd b/ips/hw/scalp_rx_link_layer/src/hdl/scalp_rx_link_layer.vhd
new file mode 100644
index 0000000..8198d5f
--- /dev/null
+++ b/ips/hw/scalp_rx_link_layer/src/hdl/scalp_rx_link_layer.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: scalp_rx_link_layer - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_rx_link_layer
+--
+-- Last update: 2021-05-12 12:25:24
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scalp_rx_link_layer is
+end scalp_rx_link_layer;
+
+
+architecture arch of scalp_rx_link_layer is
+
+begin
+
+end arch;
diff --git a/ips/hw/scalp_rx_link_layer/src/sim/tb_scalp_rx_link_layer.vhd b/ips/hw/scalp_rx_link_layer/src/sim/tb_scalp_rx_link_layer.vhd
new file mode 100644
index 0000000..30e0b41
--- /dev/null
+++ b/ips/hw/scalp_rx_link_layer/src/sim/tb_scalp_rx_link_layer.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: tb_scalp_rx_link_layer - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_rx_link_layer
+--
+-- Last update: 2021-05-12 12:25:24
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_rx_link_layer is
+end tb_scalp_rx_link_layer;
+
+
+architecture behavioral of tb_scalp_rx_link_layer is
+
+begin
+
+end behavioral;
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.gitignore b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.gitignore
new file mode 100644
index 0000000..4295900
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.gitignore
@@ -0,0 +1,23 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_rx_link_layer
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000..0106a5a
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+  set code [catch { set var [exec {*}$cmd] } ]
+  if { $code != 0 } { set var "" }
+
+  return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/clean_prj_scalp_rx_link_layer.sh b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/clean_prj_scalp_rx_link_layer.sh
new file mode 100755
index 0000000..c681048
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/clean_prj_scalp_rx_link_layer.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_rx_link_layer/ 2> /dev/null
+
+echo "> Done"
+
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.sh b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.sh
new file mode 100755
index 0000000..0fe8c34
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_rx_link_layer.tcl -notrace
+echo "> Done"
+
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.tcl b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.tcl
new file mode 100644
index 0000000..85365c4
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/create_prj_scalp_rx_link_layer.tcl
@@ -0,0 +1,154 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_rx_link_layer'
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_rx_link_layer"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+    set hdl_src_dir "${src_dir}/hdl"
+    set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+    # components sources are stored in an external directory
+    set hdl_src_dir "${comp_src_dir}/hdl"
+    set sim_src_dir "${comp_src_dir}/sim"
+}    
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+  add_files -norecurse $hdl_src_file_list
+} else {
+  print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {  
+  # add the constraints file (XDC)
+  add_files -fileset constrs_1 -norecurse  $src_dir/constrs/${prj_name}.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
+  # add IPs source files
+  
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+  # add IPs source files
+  
+  # add IP-XACT source file
+  #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+  add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+  update_compile_order -fileset sim_1
+  print_status "Add simulation sources" "OK"
+} else {
+  print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/open_prj_scalp_rx_link_layer.sh b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/open_prj_scalp_rx_link_layer.sh
new file mode 100755
index 0000000..fdcd0fc
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/open_prj_scalp_rx_link_layer.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_rx_link_layer/scalp_rx_link_layer.xpr
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000..673bc2d
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+    # Fix the directory name, this ensures the directory name is in the
+    # native format for the platform and contains a final directory seperator
+    set basedir [string trimright [file join [file normalize $basedir] { }]]
+    set fileList {}
+
+    # Look in the current directory for matching files, -type {f r}
+    # means ony readable normal files are looked at, -nocomplain stops
+    # an error being thrown if the returned list is empty
+    foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+        lappend fileList $fileName
+    }
+
+    # Now look for any sub direcories in the current directory
+    foreach dirName [glob -nocomplain -type {d  r} -path $basedir *] {
+        # Recusively call the routine on the sub directory and append any
+        # new files to the results
+        set subDirList [findFiles $dirName $pattern]
+        if { [llength $subDirList] > 0 } {
+            foreach subDirFile $subDirList {
+                lappend fileList $subDirFile
+            }
+        }
+    }
+    return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+    set MAX_STR_LENGTH 70
+    source .prompt_colors.tcl
+    puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/lin64/setup.sh b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/setup.sh
new file mode 100755
index 0000000..d1833a2
--- /dev/null
+++ b/ips/vivado/scalp_rx_link_layer/2020.2/lin64/setup.sh
@@ -0,0 +1,28 @@
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_rx_link_layer
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-05-12 12:25:24
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_rx_link_layer.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_rx_link_layer.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_rx_link_layer.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_rx_link_layer.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_rx_link_layer.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_rx_link_layer.sh && cd ..'
diff --git a/ips/vivado/scalp_rx_link_layer/2020.2/src/ipi_tcl/scalp_rx_link_layer_ipi.tcl b/ips/vivado/scalp_rx_link_layer/2020.2/src/ipi_tcl/scalp_rx_link_layer_ipi.tcl
new file mode 100644
index 0000000..e69de29
diff --git a/tools/config/scalp_firmware.json b/tools/config/scalp_firmware.json
index 807278c..2f3b4c8 100644
--- a/tools/config/scalp_firmware.json
+++ b/tools/config/scalp_firmware.json
@@ -23,9 +23,15 @@
     },   
     "components" : {
         "packages" : {
-            "aurora_drp_pkg"    : "enable",
-            "aurora_status_pkg" : "enable",
-            "axi4_pkg"          : "enable"
+            "aurora_drp_pkg" : {
+                "enable" : "true"
+            },
+            "aurora_status_pkg" : {
+                "enable" : "true"
+            },
+            "axi4_pkg" : {
+                "enable" : "true"
+            }
         },
         "soc" : {
             "scalp_zynqps" : "enable"
@@ -36,6 +42,11 @@
                 "xci" : {
                 }
             },
+            "scalp_rx_link_layer" : {
+                "hdl" : "enable",
+                "xci" : {
+                }
+            },
             "scalp_aurora_phy" : {
                 "hdl" : "enable",
                 "xci" : {
diff --git a/tools/config/scalp_rx_link_layer.json b/tools/config/scalp_rx_link_layer.json
new file mode 100644
index 0000000..4a33f14
--- /dev/null
+++ b/tools/config/scalp_rx_link_layer.json
@@ -0,0 +1,18 @@
+{
+    "author" : {
+        "name"  : "Joachim Schmidt",
+        "email" : "<joachim.schmidt@hesge.ch"
+    },
+    "project" : {
+        "name"            : "scalp_rx_link_layer",
+        "type"            : "COMP_PRJ_TYPE",
+        "category"        : "IPS",
+        "vivado_version"  : "2020.2",
+        "target_language" : "VHDL",
+        "vhdl_version"    : "VHDL 2008"
+    },
+    "hardware" : {
+        "part_name"  : "xc7z015clg485-2",
+        "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+    }
+}
-- 
GitLab