diff --git a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..b529727ce2e701912a1bc9839815616ae3f4f86f 100644
--- a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc
+++ b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/debug.xdc
@@ -0,0 +1,42 @@
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 12 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 32 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 32 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 12 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdValidxS]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/scalp_safe_firmware.xdc b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/scalp_safe_firmware.xdc
index dcd34d94609d8c00b9c6db15e06d95b2eca5ebe9..1c6f11890dceff8dec33e552c46327b64189a891 100644
--- a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/scalp_safe_firmware.xdc
+++ b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/scalp_safe_firmware.xdc
@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
diff --git a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/timing_constraints.xdc
index 3a458f2af5014e25fd7a09250af52e68a786475c..4e6bc99bf0860f3bb0b41de5d77703375e7c0b6b 100644
--- a/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_safe_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
+
diff --git a/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd b/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
index 1c4f13e6907d2ec7ea0f0ae997cea7a8677ded63..1443b87f34c75e61c4ce95e224722d7c9d0d11ec 100644
--- a/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
+++ b/designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
--- Last update: 2021-03-12
+-- Last update: 2021-03-22
--
---------------------------------------------------------------------------------
@@ -276,29 +276,33 @@ architecture arch of scalp_safe_firmware is
-- Signals
-- Clocks
-- Processing system clock
- signal PSSysClkxC : std_logic := '0';
+ signal PSSysClkxC : std_logic := '0';
-- Resets
-- Processing system reset
- signal PSSysResetxR : std_logic := '0';
+ signal PSSysResetxR : std_logic := '0';
-- Scalp Axi Lite interface and IRQ
- signal InterruptxS : std_ulogic := '0';
- signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RdValidxS : std_ulogic := '0';
- signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WrValidxS : std_ulogic := '0';
+ signal InterruptxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
-- Zynq Reg Bank
- signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- RGB Leds
- signal Led12V5RxS : std_ulogic := '0';
- signal Led12V5GxS : std_ulogic := '0';
- signal Led12V5BxS : std_ulogic := '0';
- signal Led22V5RxS : std_ulogic := '0';
- signal Led22V5GxS : std_ulogic := '0';
- signal Led22V5BxS : std_ulogic := '0';
-
+ signal Led12V5RxS : std_ulogic := '0';
+ signal Led12V5GxS : std_ulogic := '0';
+ signal Led12V5BxS : std_ulogic := '0';
+ signal Led22V5RxS : std_ulogic := '0';
+ signal Led22V5GxS : std_ulogic := '0';
+ signal Led22V5BxS : std_ulogic := '0';
+ -- RgbLeds Ctrl Port
+ signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+
+ -- RGB Leds Enum
+ type t_rgb_leds is (E_LED1_R, E_LED1_G, E_LED1_B, E_LED2_R, E_LED2_G, E_LED2_B);
-- Attributes
attribute mark_debug : string;
@@ -353,7 +357,8 @@ begin
RdValidxSO => RdValidxS,
WrAddrxDO => WrAddrxD,
WrDataxDO => WrDataxD,
- WrValidxSO => WrValidxS);
+ WrValidxSO => WrValidxS,
+ RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD);
end block ProcessingSystemxB;
@@ -363,12 +368,12 @@ begin
EntityIOxB : block is
begin
- Led12V5RxAS : Led12V5RxSO <= Led12V5RxS;
- Led12V5GxAS : Led12V5GxSO <= Led12V5GxS;
- Led12V5BxAS : Led12V5BxSO <= Led12V5BxS;
- Led22V5RxAS : Led22V5RxSO <= Led22V5RxS;
- Led22V5GxAS : Led22V5GxSO <= Led22V5GxS;
- Led22V5BxAS : Led22V5BxSO <= Led22V5BxS;
+ Led12V5RxAS : Led12V5RxSO <= RgbLedsCtrlPortxD(0);
+ Led12V5GxAS : Led12V5GxSO <= RgbLedsCtrlPortxD(1);
+ Led12V5BxAS : Led12V5BxSO <= RgbLedsCtrlPortxD(2);
+ Led22V5RxAS : Led22V5RxSO <= RgbLedsCtrlPortxD(3);
+ Led22V5GxAS : Led22V5GxSO <= RgbLedsCtrlPortxD(4);
+ Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
end block EntityIOxB;
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..c3376ce2522cf4c1ea2cd1b345d8002c9d2994b0 100644
--- a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/debug.xdc
@@ -0,0 +1,42 @@
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 32 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 12 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 12 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[11]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 32 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 32 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[31]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdValidxS]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
index dcd34d94609d8c00b9c6db15e06d95b2eca5ebe9..1c6f11890dceff8dec33e552c46327b64189a891 100644
--- a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/scalp_user_firmware.xdc
@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
index 3a458f2af5014e25fd7a09250af52e68a786475c..4e6bc99bf0860f3bb0b41de5d77703375e7c0b6b 100644
--- a/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/constrs/timing_constraints.xdc
@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
+
diff --git a/designs/vivado/scalp_user_firmware/2020.2/src/hdl/scalp_user_firmware.vhd b/designs/vivado/scalp_user_firmware/2020.2/src/hdl/scalp_user_firmware.vhd
index 753b96c9a33de0ca7668bbf5627eadbe9e40e32d..0d7fe3062c09add697f5fef9e80151a3044ce3b3 100644
--- a/designs/vivado/scalp_user_firmware/2020.2/src/hdl/scalp_user_firmware.vhd
+++ b/designs/vivado/scalp_user_firmware/2020.2/src/hdl/scalp_user_firmware.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_user_firmware
--
--- Last update: 2021-03-17
+-- Last update: 2021-03-24
--
---------------------------------------------------------------------------------
@@ -275,28 +275,23 @@ architecture arch of scalp_user_firmware is
-- Signals
-- Clocks
-- Processing system clock
- signal PSSysClkxC : std_logic := '0';
+ signal PSSysClkxC : std_logic := '0';
-- Resets
-- Processing system reset
- signal PSSysResetxR : std_logic := '0';
+ signal PSSysResetxR : std_logic := '0';
-- Scalp Axi Lite interface and IRQ
- signal InterruptxS : std_ulogic := '0';
- signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RdValidxS : std_ulogic := '0';
- signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WrValidxS : std_ulogic := '0';
+ signal InterruptxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
-- Zynq Reg Bank
- signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- RGB Leds
- signal Led12V5RxS : std_ulogic := '0';
- signal Led12V5GxS : std_ulogic := '0';
- signal Led12V5BxS : std_ulogic := '0';
- signal Led22V5RxS : std_ulogic := '0';
- signal Led22V5GxS : std_ulogic := '0';
- signal Led22V5BxS : std_ulogic := '0';
+ signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- Attributes
@@ -352,7 +347,8 @@ begin
RdValidxSO => RdValidxS,
WrAddrxDO => WrAddrxD,
WrDataxDO => WrDataxD,
- WrValidxSO => WrValidxS);
+ WrValidxSO => WrValidxS,
+ RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD);
end block ProcessingSystemxB;
@@ -362,12 +358,12 @@ begin
EntityIOxB : block is
begin
- Led12V5RxAS : Led12V5RxSO <= Led12V5RxS;
- Led12V5GxAS : Led12V5GxSO <= Led12V5GxS;
- Led12V5BxAS : Led12V5BxSO <= Led12V5BxS;
- Led22V5RxAS : Led22V5RxSO <= Led22V5RxS;
- Led22V5GxAS : Led22V5GxSO <= Led22V5GxS;
- Led22V5BxAS : Led22V5BxSO <= Led22V5BxS;
+ Led12V5RxAS : Led12V5RxSO <= RgbLedsCtrlPortxD(0);
+ Led12V5GxAS : Led12V5GxSO <= RgbLedsCtrlPortxD(1);
+ Led12V5BxAS : Led12V5BxSO <= RgbLedsCtrlPortxD(2);
+ Led22V5RxAS : Led22V5RxSO <= RgbLedsCtrlPortxD(3);
+ Led22V5GxAS : Led22V5GxSO <= RgbLedsCtrlPortxD(4);
+ Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
end block EntityIOxB;
diff --git a/ips/hw/scalp_safe_firmware_reg_bank/component.xml b/ips/hw/scalp_safe_firmware_reg_bank/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..def71d6ec64180c72f8e5a117b71d5406ec78b76
--- /dev/null
+++ b/ips/hw/scalp_safe_firmware_reg_bank/component.xml
@@ -0,0 +1,829 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>hepia.ch</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>scalp_safe_firmware_reg_bank</spirit:name>
+ <spirit:version>1.3</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>SAXILitexDIO</spirit:name>
+ <spirit:displayName>SAXILitexDIO</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="SAXILitexDIO"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiRReadyxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiBValidxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiBReadyxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiAWValidxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiAWReadyxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiWDataxDI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiRRespxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiRValidxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiARAddrxDI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiARReadyxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiAWAddrxDI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiWValidxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiWReadyxSO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiARValidxSI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiWStrbxDI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiBRespxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiRDataxDO</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXILITEXDIO.NUM_READ_OUTSTANDING"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXILITEXDIO.NUM_WRITE_OUTSTANDING"/>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>SAXILiteClkxCI</spirit:name>
+ <spirit:displayName>SAXILiteClkxCI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiClkxCI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXILITECLKXCI.FREQ_HZ"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXILITECLKXCI.ASSOCIATED_BUSIF">SAXILitexDIO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.SAXILITECLKXCI.ASSOCIATED_RESET">SAxiLiteRstxRANI:SAxiRstxRANI</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>SAxiLiteRstxRANI</spirit:name>
+ <spirit:displayName>SAxiLiteRstxRANI</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>SAxiRstxRANI</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:memoryMaps>
+ <spirit:memoryMap>
+ <spirit:name>SAXILitexDIO</spirit:name>
+ <spirit:addressBlock>
+ <spirit:name>SAXILiteAddr</spirit:name>
+ <spirit:displayName>SAXILiteAddr</spirit:displayName>
+ <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+ <spirit:range spirit:format="long">4K</spirit:range>
+ <spirit:width spirit:format="long">0</spirit:width>
+ </spirit:addressBlock>
+ </spirit:memoryMap>
+ </spirit:memoryMaps>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>VHDL-2008</spirit:language>
+ <spirit:modelName>scalp_safe_firmware_reg_bank</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>36589b1c</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>VHDL-2008</spirit:language>
+ <spirit:modelName>scalp_safe_firmware_reg_bank</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>36589b1c</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>94c74469</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>SAxiClkxCI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiRstxRANI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiARAddrxDI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiARValidxSI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiARReadyxSO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiRDataxDO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_RDATA_SIZE')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiRRespxDO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_RRESP_SIZE')) - 1)">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiRValidxSO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiRReadyxSI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiAWAddrxDI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiAWValidxSI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiAWReadyxSO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiWDataxDI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_WDATA_SIZE')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiWStrbxDI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE')) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic_vector</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiWValidxSI</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiWReadyxSO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>std_ulogic</spirit:typeName>
+ <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>SAxiBRespxDO</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_AXI4_BRESP_SIZE')) - 1)">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
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diff --git a/ips/hw/scalp_safe_firmware_reg_bank/src/hdl/scalp_safe_firmware_reg_bank.vhd b/ips/hw/scalp_safe_firmware_reg_bank/src/hdl/scalp_safe_firmware_reg_bank.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8b7da3cbc14cb325904343c8f2fadbf7d0bfd84a
--- /dev/null
+++ b/ips/hw/scalp_safe_firmware_reg_bank/src/hdl/scalp_safe_firmware_reg_bank.vhd
@@ -0,0 +1,330 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_misc.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity scalp_safe_firmware_reg_bank is
+
+ generic (
+ C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_RDATA_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2;
+ C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_WDATA_SIZE : integer range 0 to 32 := 32;
+ C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4;
+ C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2;
+ C_AXI4_ADDR_SIZE : integer range 0 to 32 := 12;
+ C_AXI4_DATA_SIZE : integer range 0 to 32 := 32);
+
+ port (
+ -- Clock and reset
+ SAxiClkxCI : in std_ulogic;
+ SAxiRstxRANI : in std_ulogic;
+ -- AXI4 Lite
+ -- Read Channel
+ -- Read Address Channel
+ SAxiARAddrxDI : in std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
+ SAxiARValidxSI : in std_ulogic;
+ SAxiARReadyxSO : out std_ulogic;
+ -- Read Data Channel
+ SAxiRDataxDO : out std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
+ SAxiRRespxDO : out std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
+ SAxiRValidxSO : out std_ulogic;
+ SAxiRReadyxSI : in std_ulogic;
+ -- Write Channel
+ -- Write Address Channel
+ SAxiAWAddrxDI : in std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
+ SAxiAWValidxSI : in std_ulogic;
+ SAxiAWReadyxSO : out std_ulogic;
+ -- Write Data Channel
+ SAxiWDataxDI : in std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
+ SAxiWStrbxDI : in std_ulogic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
+ SAxiWValidxSI : in std_ulogic;
+ SAxiWReadyxSO : out std_ulogic;
+ -- Write Response Channel
+ SAxiBRespxDO : out std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
+ SAxiBValidxSO : out std_ulogic;
+ SAxiBReadyxSI : in std_ulogic;
+ -- Register Access IO
+ RgbLedsCtrlPortxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
+
+end scalp_safe_firmware_reg_bank;
+
+architecture behavioral of scalp_safe_firmware_reg_bank is
+
+ -- Constants
+ constant C_AXI4_RRESP_OKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00";
+ constant C_AXI4_RRESP_EXOKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01";
+ constant C_AXI4_RRESP_SLVERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10";
+ constant C_AXI4_RRESP_DECERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11";
+ constant C_AXI4_BRESP_OKAY : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00";
+ constant C_AXI4_BRESP_EXOKAY : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01";
+ constant C_AXI4_BRESP_SLVERR : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10";
+ constant C_AXI4_BRESP_DECERR : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11";
+
+ -- Signals
+ -- Clock and reset
+ signal SAxiClkxC : std_ulogic := '0';
+ signal SAxiRstxRAN : std_ulogic := '0';
+ -- AXI4 Lite
+ signal SAxiARReadyxS : std_ulogic := '0';
+ signal SAxiRValidxS : std_ulogic := '0';
+ signal SAxiBValidxS : std_ulogic := '0';
+ signal SAxiWReadyxS : std_ulogic := '0';
+ signal SAxiAWReadyxS : std_ulogic := '0';
+ signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ -- Signals of access to the register bank
+ signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
+ -- Registers list
+ signal RgbLedsCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RgbLedsCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+
+ -- Attributes
+ attribute mark_debug : string;
+ attribute keep : string;
+ --
+ attribute mark_debug of RdAddrxD : signal is "true";
+ attribute keep of RdAddrxD : signal is "true";
+ attribute mark_debug of RdDataxD : signal is "true";
+ attribute keep of RdDataxD : signal is "true";
+ attribute mark_debug of RdValidxS : signal is "true";
+ attribute keep of RdValidxS : signal is "true";
+ attribute mark_debug of WrAddrxD : signal is "true";
+ attribute keep of WrAddrxD : signal is "true";
+ attribute mark_debug of WrDataxD : signal is "true";
+ attribute keep of WrDataxD : signal is "true";
+ attribute mark_debug of WrValidxS : signal is "true";
+ attribute keep of WrValidxS : signal is "true";
+ attribute mark_debug of RgbLedsCtrlPortxDP : signal is "true";
+ attribute keep of RgbLedsCtrlPortxDP : signal is "true";
+
+begin
+
+ assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
+ report "RDATA and DATA vectors must be the same" severity failure;
+
+ assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
+ report "ARADDR and ADDR vectors must be the same" severity failure;
+
+ assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
+ report "WDATA and DATA vectors must be the same" severity failure;
+
+ assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
+ report "AWADDR and ADDR vectors must be the same" severity failure;
+
+ EntityIOxB : block is
+ begin -- block EntityIOxB
+
+ -- Clock and reset
+ SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
+ SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
+ -- Read Channel
+ SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
+ SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
+ SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
+ RdValidxAS : RdValidxS <= SAxiARValidxSI;
+ RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
+ SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
+ -- Write Channel
+ SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
+ SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
+ SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
+ SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
+ WrValidxAS : WrValidxS <= SAxiWValidxSI;
+ WrDataxAS : WrDataxD <= SAxiWDataxDI;
+ WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
+ WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
+ SAxiAWValidxSI = '1' else
+ WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
+ RgbLedsCtrlPortxAS : RgbLedsCtrlPortxDO <= RgbLedsCtrlPortxDP;
+
+ end block EntityIOxB;
+
+ AXI4LitexB : block is
+ begin -- block AXI4LitexB
+
+ ReadChannelxB : block is
+ begin -- block ReadChannelxB
+
+ ReadAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+
+ variable StateAfterResetxS : boolean := true;
+
+ begin -- process ReadAddrChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiARReadyxS <= '0';
+ StateAfterResetxS := true;
+ elsif rising_edge(SAxiClkxC) then
+ if StateAfterResetxS = true then
+ SAxiARReadyxS <= '1';
+ StateAfterResetxS := false;
+ else
+ SAxiARReadyxS <= SAxiARReadyxS;
+ end if;
+
+ if SAxiARValidxSI = '1' then
+ SAxiARReadyxS <= '0';
+ end if;
+
+ if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then
+ SAxiARReadyxS <= '1';
+ end if;
+ end if;
+ end process ReadAddrChanxP;
+
+ ReadDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process ReadDataChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiRValidxS <= '0';
+ elsif rising_edge(SAxiClkxC) then
+ SAxiRValidxS <= SAxiRValidxS;
+
+ if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then
+ SAxiRValidxS <= '1';
+ end if;
+
+ if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then
+ SAxiRValidxS <= '0';
+ end if;
+ end if;
+ end process ReadDataChanxP;
+
+ end block ReadChannelxB;
+
+ WriteChannelxB : block is
+ begin --block WriteChannelxB
+
+ WrAddrRegxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process WrAddrRegxP
+ if SAxiRstxRAN = '0' then
+ WrAddrxDP <= (others => '0');
+ elsif rising_edge(SAxiClkxC) then
+ WrAddrxDP <= WrAddrxDN;
+ end if;
+ end process WrAddrRegxP;
+
+ WriteAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+
+ variable StateAfterResetxS : boolean := true;
+
+ begin -- process WriteAddrChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiAWReadyxS <= '0';
+ StateAfterResetxS := true;
+ elsif rising_edge(SAxiClkxC) then
+ if StateAfterResetxS = true then
+ SAxiAWReadyxS <= '1';
+ StateAfterResetxS := false;
+ else
+ SAxiAWReadyxS <= SAxiAWReadyxS;
+ end if;
+
+ if SAxiAWValidxSI = '1' then
+ SAxiAWReadyxS <= '0';
+ end if;
+
+ if SAxiWValidxSI = '1' then
+ SAxiAWReadyxS <= '1';
+ end if;
+ end if;
+ end process WriteAddrChanxP;
+
+ WriteDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process WriteDataChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiWReadyxS <= '0';
+ elsif rising_edge(SAxiClkxCI) then
+ SAxiWReadyxS <= SAxiWReadyxS;
+
+ if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then
+ SAxiWReadyxS <= '1';
+ end if;
+
+ if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
+ SAxiWReadyxS <= '0';
+ end if;
+ end if;
+ end process WriteDataChanxP;
+
+ WriteRespChanxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process WriteRespChanxP
+ if SAxiRstxRAN = '0' then
+ SAxiBValidxS <= '0';
+ elsif rising_edge(SAxiClkxC) then
+ SAxiBValidxS <= SAxiBValidxS;
+
+ if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
+ SAxiBValidxS <= '1';
+ end if;
+
+ if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then
+ SAxiBValidxS <= '0';
+ end if;
+ end if;
+ end process WriteRespChanxP;
+
+ end block WriteChannelxB;
+
+ end block AXI4LitexB;
+
+ ScalpSafeFirmwareRegBankxB : block is
+ begin -- block ScalpSafeFirmwareRegBankxB
+
+ WriteRegPortxP : process (WrAddrxD, WrDataxD, WrValidxS,
+ RgbLedsCtrlPortxDP) is
+ begin -- process WriteRegPortxP
+ RgbLedsCtrlPortxDN <= RgbLedsCtrlPortxDP;
+
+ if WrValidxS = '1' then
+ case WrAddrxD is
+ when x"000" => RgbLedsCtrlPortxDN <= WrDataxD;
+ when x"004" => RgbLedsCtrlPortxDN <= RgbLedsCtrlPortxDP or WrDataxD;
+ when x"008" => RgbLedsCtrlPortxDN <= RgbLedsCtrlPortxDP and not WrDataxD;
+
+ when others => null;
+ end case;
+ end if;
+ end process WriteRegPortxP;
+
+ ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process ReadRegPortxP
+ if SAxiRstxRAN = '0' then
+ RdDataxD <= (others => '0');
+ elsif rising_edge(SAxiClkxC) then
+ RdDataxD <= (others => '0');
+
+ if RdValidxS = '1' then
+ case RdAddrxD is
+ when x"000" => RdDataxD <= RgbLedsCtrlPortxDP;
+
+ when others => RdDataxD <= (others => '0');
+ end case;
+ end if;
+ end if;
+ end process ReadRegPortxP;
+
+ UpdateRegBankxP : process (SAxiClkxC, SAxiRstxRAN) is
+ begin -- process UpdateRegBankxP
+ if SAxiRstxRAN = '0' then
+ RgbLedsCtrlPortxDP <= x"00000000";
+
+ elsif rising_edge(SAxiClkxC) then
+ RgbLedsCtrlPortxDP <= RgbLedsCtrlPortxDN;
+
+ end if;
+ end process UpdateRegBankxP;
+
+ end block ScalpSafeFirmwareRegBankxB;
+
+end behavioral;
diff --git a/ips/hw/scalp_safe_firmware_reg_bank/src/sim/tb_scalp_safe_firmware_reg_bank.vhd b/ips/hw/scalp_safe_firmware_reg_bank/src/sim/tb_scalp_safe_firmware_reg_bank.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b79826711d2c351d1fa9a8bfef7bdd6b1f4a1d44
--- /dev/null
+++ b/ips/hw/scalp_safe_firmware_reg_bank/src/sim/tb_scalp_safe_firmware_reg_bank.vhd
@@ -0,0 +1,34 @@
+----------------------------------------------------------------------------------
+-- _ _
+-- | |_ ___ _ __(_)__ _
+-- | ' \/ -_) '_ \ / _` |
+-- |_||_\___| .__/_\__,_|
+-- |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+--
+-- Module Name: tb_scalp_safe_firmware_reg_bank - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_safe_firmware_reg_bank
+--
+-- Last update: 2021-03-22 08:20:36
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_safe_firmware_reg_bank is
+end tb_scalp_safe_firmware_reg_bank;
+
+
+architecture behavioral of tb_scalp_safe_firmware_reg_bank is
+
+begin
+
+end behavioral;
diff --git a/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_0.tcl b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38
--- /dev/null
+++ b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_0.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_1.tcl b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38
--- /dev/null
+++ b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_1.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_2.tcl b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_2.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38
--- /dev/null
+++ b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_2.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_3.tcl b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_3.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..72aafc830843c18e0a8d96f97b156397b4081a38
--- /dev/null
+++ b/ips/hw/scalp_safe_firmware_reg_bank/xgui/scalp_safe_firmware_reg_bank_v1_3.tcl
@@ -0,0 +1,145 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to validate C_AXI4_ARADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to validate C_AXI4_AWADDR_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to validate C_AXI4_BRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to validate C_AXI4_DATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to validate C_AXI4_RDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to validate C_AXI4_RRESP_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to validate C_AXI4_WDATA_SIZE
+ return true
+}
+
+proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to validate C_AXI4_WSTRB_SIZE
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
+}
+
+proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
+}
+
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.gitignore b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..91871832b556214a85269ecaf5c11f88b3285b6f
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.gitignore
@@ -0,0 +1,23 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_safe_firmware_reg_bank
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/.prompt_colors.tcl b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/.prompt_colors.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c8b8b9157e0187475ad4c1a377b1678fae443c98
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/.prompt_colors.tcl
@@ -0,0 +1,47 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+ set code [catch { set var [exec {*}$cmd] } ]
+ if { $code != 0 } { set var "" }
+
+ return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/clean_prj_scalp_safe_firmware_reg_bank.sh b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/clean_prj_scalp_safe_firmware_reg_bank.sh
new file mode 100755
index 0000000000000000000000000000000000000000..807998fb56c3377767426eac842eb77295d25175
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/clean_prj_scalp_safe_firmware_reg_bank.sh
@@ -0,0 +1,35 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_safe_firmware_reg_bank/ 2> /dev/null
+
+echo "> Done"
+
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware_reg_bank.sh b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware_reg_bank.sh
new file mode 100755
index 0000000000000000000000000000000000000000..165e9ac095f2b8884d1091d36bf6ba509f7f08d3
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware_reg_bank.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_safe_firmware_reg_bank.tcl -notrace
+echo "> Done"
+
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware_reg_bank.tcl b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware_reg_bank.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ddc8ab91cd485a26b4b6164bdd453fcb7e21e57b
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware_reg_bank.tcl
@@ -0,0 +1,154 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_safe_firmware_reg_bank'
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_safe_firmware_reg_bank"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ set hdl_src_dir "${src_dir}/hdl"
+ set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # components sources are stored in an external directory
+ set hdl_src_dir "${comp_src_dir}/hdl"
+ set sim_src_dir "${comp_src_dir}/sim"
+}
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+ add_files -norecurse $hdl_src_file_list
+} else {
+ print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+ # add the constraints file (XDC)
+ add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
+ set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
+
+ # add IPs source files
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+ # add IPs source files
+
+ # add IP-XACT source file
+ #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+ add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+ update_compile_order -fileset sim_1
+ print_status "Add simulation sources" "OK"
+} else {
+ print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+ set_property file_type {VHDL 2008} [get_files $j]
+ print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
+
+# Add packages sources
+
+
+# Add SoC wrapper sources files
+
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/open_prj_scalp_safe_firmware_reg_bank.sh b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/open_prj_scalp_safe_firmware_reg_bank.sh
new file mode 100755
index 0000000000000000000000000000000000000000..529c212b0949044dd2a27f43a1569ebe421601f6
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/open_prj_scalp_safe_firmware_reg_bank.sh
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_safe_firmware_reg_bank/scalp_safe_firmware_reg_bank.xpr
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/utils.tcl b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/utils.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..82a2569612bb673bac2375c4df13de8dd2505c0c
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/.scripts/utils.tcl
@@ -0,0 +1,62 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+ # Fix the directory name, this ensures the directory name is in the
+ # native format for the platform and contains a final directory seperator
+ set basedir [string trimright [file join [file normalize $basedir] { }]]
+ set fileList {}
+
+ # Look in the current directory for matching files, -type {f r}
+ # means ony readable normal files are looked at, -nocomplain stops
+ # an error being thrown if the returned list is empty
+ foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+ lappend fileList $fileName
+ }
+
+ # Now look for any sub direcories in the current directory
+ foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
+ # Recusively call the routine on the sub directory and append any
+ # new files to the results
+ set subDirList [findFiles $dirName $pattern]
+ if { [llength $subDirList] > 0 } {
+ foreach subDirFile $subDirList {
+ lappend fileList $subDirFile
+ }
+ }
+ }
+ return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+ set MAX_STR_LENGTH 70
+ source .prompt_colors.tcl
+ puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/setup.sh b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/setup.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f59c565299ccd63022cb78e682994fba3acc8c44
--- /dev/null
+++ b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/lin64/setup.sh
@@ -0,0 +1,28 @@
+##################################################################################
+# _ _
+# | |_ ___ _ __(_)__ _
+# | ' \/ -_) '_ \ / _` |
+# |_||_\___| .__/_\__,_|
+# |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
+#
+# Project Name: scalp_safe_firmware_reg_bank
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-03-22 08:20:36
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_safe_firmware_reg_bank.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_safe_firmware_reg_bank.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_safe_firmware_reg_bank.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_safe_firmware_reg_bank.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_safe_firmware_reg_bank.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_safe_firmware_reg_bank.sh && cd ..'
diff --git a/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/src/ipi_tcl/scalp_safe_firmware_reg_bank_ipi.tcl b/ips/vivado/scalp_safe_firmware_reg_bank/2020.2/src/ipi_tcl/scalp_safe_firmware_reg_bank_ipi.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
index d0d7351b9a50d3f247719e2ecf14b703fc9aad5d..ba0f4dbe83261e7c93f84a5b84369eee256acfb4 100644
--- a/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+++ b/soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
--- Last update: 2020-11-08
+-- Last update: 2021-03-22
--
---------------------------------------------------------------------------------
@@ -66,7 +66,8 @@ entity scalp_zynqps_wrapper is
RdValidxSO : out std_logic;
WrAddrxDO : out std_logic_vector (11 downto 0);
WrDataxDO : out std_logic_vector (31 downto 0);
- WrValidxSO : out std_logic);
+ WrValidxSO : out std_logic;
+ RgbLedsCtrlPortxDO : out std_logic_vector (31 downto 0));
end scalp_zynqps_wrapper;
@@ -109,6 +110,7 @@ begin
RdValidxSO => RdValidxSO,
WrAddrxDO => WrAddrxDO,
WrDataxDO => WrDataxDO,
- WrValidxSO => WrValidxSO);
+ WrValidxSO => WrValidxSO,
+ RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO);
end arch;
diff --git a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
index b5395358b3a298bd95ce9bf1c53c87803a4fbdc8..b38d8c4bdeb03260b6f25e9bd293a6229ee787f4 100644
--- a/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+++ b/soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
@@ -127,6 +127,7 @@ xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
hepia.hesge.ch:user:scalp_axi4lite:1.2\
+hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
"
@@ -207,6 +208,7 @@ proc create_root_design { parentCell } {
set RdAddrxDO [ create_bd_port -dir O -from 11 -to 0 RdAddrxDO ]
set RdDataxDI [ create_bd_port -dir I -from 31 -to 0 RdDataxDI ]
set RdValidxSO [ create_bd_port -dir O RdValidxSO ]
+ set RgbLedsCtrlPortxDO [ create_bd_port -dir O -from 31 -to 0 RgbLedsCtrlPortxDO ]
set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
@@ -673,7 +675,7 @@ proc create_root_design { parentCell } {
# Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \
- CONFIG.NUM_MI {1} \
+ CONFIG.NUM_MI {2} \
] $ps7_0_axi_periph
# Create instance: rst_ps7_0_125M, and set properties
@@ -682,6 +684,9 @@ proc create_root_design { parentCell } {
# Create instance: scalp_axi4lite_0, and set properties
set scalp_axi4lite_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_axi4lite:1.2 scalp_axi4lite_0 ]
+ # Create instance: scalp_safe_firmware_0, and set properties
+ set scalp_safe_firmware_0 [ create_bd_cell -type ip -vlnv hepia.ch:user:scalp_safe_firmware_reg_bank:1.3 scalp_safe_firmware_0 ]
+
# Create instance: util_vector_logic_0, and set properties
set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
set_property -dict [ list \
@@ -710,6 +715,7 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO]
+ connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
# Create port connections
connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
@@ -717,24 +723,26 @@ proc create_root_design { parentCell } {
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
- connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins vio_0/clk]
+ connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
- connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI]
+ connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI]
connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO]
connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
connect_bd_net -net scalp_axi4lite_0_WrAddrxDO [get_bd_ports WrAddrxDO] [get_bd_pins scalp_axi4lite_0/WrAddrxDO]
connect_bd_net -net scalp_axi4lite_0_WrDataxDO [get_bd_ports WrDataxDO] [get_bd_pins scalp_axi4lite_0/WrDataxDO]
connect_bd_net -net scalp_axi4lite_0_WrValidxSO [get_bd_ports WrValidxSO] [get_bd_pins scalp_axi4lite_0/WrValidxSO]
+ connect_bd_net -net scalp_safe_firmware_0_RgbLedsCtrlPortxDO [get_bd_ports RgbLedsCtrlPortxDO] [get_bd_pins scalp_safe_firmware_0/RgbLedsCtrlPortxDO]
connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
# Create address segments
assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr] -force
+ assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
# Restore current instance
diff --git a/tools/config/scalp_safe_firmware_reg_bank.json b/tools/config/scalp_safe_firmware_reg_bank.json
new file mode 100644
index 0000000000000000000000000000000000000000..5a26b50bb554447c5e01a97a6c46988878c0aaf5
--- /dev/null
+++ b/tools/config/scalp_safe_firmware_reg_bank.json
@@ -0,0 +1,18 @@
+{
+ "author" : {
+ "name" : "Joachim Schmidt",
+ "email" : "<joachim.schmidt@hesge.ch"
+ },
+ "project" : {
+ "name" : "scalp_safe_firmware_reg_bank",
+ "type" : "COMP_PRJ_TYPE",
+ "category" : "IPS",
+ "vivado_version" : "2020.2",
+ "target_language" : "VHDL",
+ "vhdl_version" : "VHDL 2008"
+ },
+ "hardware" : {
+ "part_name" : "xc7z015clg485-2",
+ "board_name" : "hepia-cores.ch:scalp_node:part0:0.1"
+ }
+}
diff --git a/tools/vivado_prj_creator b/tools/vivado_prj_creator
index 14d2222cde0a7162b79d24f1bb0631795438af48..fa43241310c21f2e6872cb09d6daf0e27e373f72 160000
--- a/tools/vivado_prj_creator
+++ b/tools/vivado_prj_creator
@@ -1 +1 @@
-Subproject commit 14d2222cde0a7162b79d24f1bb0631795438af48
+Subproject commit fa43241310c21f2e6872cb09d6daf0e27e373f72