From fa38ca66145120791db540ecba3377bd8c02d081 Mon Sep 17 00:00:00 2001
From: "joachim.schmidt" <joachim.schmidt@hesge.ch>
Date: Sun, 12 Sep 2021 11:02:35 +0200
Subject: [PATCH] Update scalp_router_regbank
---
ips/hw/scalp_router_regbank/component.xml | 48 ++++-
.../src/hdl/scalp_router_regbank.vhd | 175 +++++++++++-------
2 files changed, 143 insertions(+), 80 deletions(-)
diff --git a/ips/hw/scalp_router_regbank/component.xml b/ips/hw/scalp_router_regbank/component.xml
index b7041e5..46bace0 100644
--- a/ips/hw/scalp_router_regbank/component.xml
+++ b/ips/hw/scalp_router_regbank/component.xml
@@ -3,7 +3,7 @@
<spirit:vendor>hepia.hesge.ch</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>scalp_router_regbank</spirit:name>
- <spirit:version>0.8</spirit:version>
+ <spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>SAxiClkxCI</spirit:name>
@@ -412,7 +412,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>7a280e8f</spirit:value>
+ <spirit:value>16e15106</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -428,7 +428,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
- <spirit:value>7a280e8f</spirit:value>
+ <spirit:value>16e15106</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -931,7 +931,7 @@
<spirit:file>
<spirit:name>src/hdl/scalp_router_regbank.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
- <spirit:userFileType>CHECKSUM_7a280e8f</spirit:userFileType>
+ <spirit:userFileType>CHECKSUM_16e15106</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -944,14 +944,14 @@
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
- <spirit:name>xgui/scalp_router_regbank_v0_8.tcl</spirit:name>
+ <spirit:name>xgui/scalp_router_regbank_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_94c74469</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
- <spirit:description>scalp_router_regbank_v0_8</spirit:description>
+ <spirit:description>scalp_router_regbank_v1_0</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_AXI4_ARADDR_SIZE</spirit:name>
@@ -1031,11 +1031,11 @@
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
- <xilinx:displayName>scalp_router_regbank_v0_8</xilinx:displayName>
+ <xilinx:displayName>scalp_router_regbank_v1_0</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:vendorDisplayName>Hepia</xilinx:vendorDisplayName>
- <xilinx:coreRevision>18</xilinx:coreRevision>
- <xilinx:coreCreationDateTime>2021-06-28T06:22:25Z</xilinx:coreCreationDateTime>
+ <xilinx:coreRevision>22</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2021-09-12T08:42:29Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@32291851_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@530043c9_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
@@ -1256,12 +1256,40 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@52defe61_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4f037fc3_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@b0126f5_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4f0a2041_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@778c2065_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@56084df3_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5526729_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@b1d2941_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7e8dccb0_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6bc81f8d_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23f0989f_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a55ba40_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@f52f706_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@398753e7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6d9eda34_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@42101452_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@53a026d7_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@667e25ed_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@71f35fbc_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@407d044d_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4aa62268_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@ff17e9e_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3459baa2_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@74b073b1_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5e363cb_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@776b34d2_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@78b9123e_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@b62c76_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3fe39027_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@78658331_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27a2c99f_ARCHIVE_LOCATION">/home/jo/Documents/Projets/Hepia/scalp_project/scalp_firmware/ips/hw/scalp_router_regbank</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="43363bdc"/>
- <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8fbae063"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="03649f14"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="6b6e9195"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d2e1fb7a"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="03a862ce"/>
diff --git a/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd b/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd
index b4df94a..68d468f 100644
--- a/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd
+++ b/ips/hw/scalp_router_regbank/src/hdl/scalp_router_regbank.vhd
@@ -81,65 +81,87 @@ architecture behavioral of scalp_router_regbank is
-- Signals
-- Clock and reset
- signal SAxiClkxC : std_ulogic := '0';
- signal SAxiRstxRAN : std_ulogic := '0';
+ signal SAxiClkxC : std_ulogic := '0';
+ signal SAxiRstxRAN : std_ulogic := '0';
-- AXI4 Lite
- signal SAxiARReadyxS : std_ulogic := '0';
- signal SAxiRValidxS : std_ulogic := '0';
- signal SAxiBValidxS : std_ulogic := '0';
- signal SAxiWReadyxS : std_ulogic := '0';
- signal SAxiAWReadyxS : std_ulogic := '0';
- signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal SAxiARReadyxS : std_ulogic := '0';
+ signal SAxiRValidxS : std_ulogic := '0';
+ signal SAxiBValidxS : std_ulogic := '0';
+ signal SAxiWReadyxS : std_ulogic := '0';
+ signal SAxiAWReadyxS : std_ulogic := '0';
+ signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- Signals of access to the register bank
- signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal RdValidxS : std_ulogic := '0';
- signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
- signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
- signal WrValidxS : std_ulogic := '0';
+ signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal RdValidxS : std_ulogic := '0';
+ signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
+ signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+ signal WrValidxS : std_ulogic := '0';
-- Registers list
- signal ScalpPacketWriteDataPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal ScalpPacketWriteDataPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal ScalpPacketReadDataPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal ScalpPacketReadDataPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal ScalpPacketCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal ScalpPacketCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal ScalpPacketStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal ScalpPacketStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal TXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal TXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal TXRdDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal TXRdDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RXRdDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal RXRdDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal LocNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
- signal LocNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketWriteDataPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketWriteDataPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketReadDataPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketReadDataPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal ScalpPacketStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal TXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal TXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal TXRdDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal TXRdDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RXRdDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal RXRdDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal LocNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ signal LocNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
+ -- Debug
+ signal SAxiARAddrInDebugxD : std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0) := (others => '0');
+ signal SAxiARValidInDebugxS : std_ulogic := '0';
+ signal SAxiARReadyOutDebugxS : std_ulogic := '0';
+ signal SAxiRDataOutDebugxD : std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0) := (others => '0');
+ signal SAxiRRespOutDebugxD : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := (others => '0');
+ signal SAxiRValidOutDebugxS : std_ulogic := '0';
+ signal SAxiRReadyInDebugxS : std_ulogic := '0';
-- Attributes
- attribute mark_debug : string;
- attribute keep : string;
+ attribute mark_debug : string;
+ attribute keep : string;
--
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
- attribute mark_debug of RdAddrxD : signal is "true";
- attribute keep of RdAddrxD : signal is "true";
- attribute mark_debug of RdDataxD : signal is "true";
- attribute keep of RdDataxD : signal is "true";
- attribute mark_debug of RdValidxS : signal is "true";
- attribute keep of RdValidxS : signal is "true";
- attribute mark_debug of WrAddrxD : signal is "true";
- attribute keep of WrAddrxD : signal is "true";
- attribute mark_debug of WrDataxD : signal is "true";
- attribute keep of WrDataxD : signal is "true";
- attribute mark_debug of WrValidxS : signal is "true";
- attribute keep of WrValidxS : signal is "true";
- attribute mark_debug of LocNetAddrPortxDN : signal is "true";
- attribute keep of LocNetAddrPortxDN : signal is "true";
- attribute mark_debug of LocNetAddrPortxDP : signal is "true";
- attribute keep of LocNetAddrPortxDP : signal is "true";
+ attribute mark_debug of RdAddrxD : signal is "true";
+ attribute keep of RdAddrxD : signal is "true";
+ attribute mark_debug of RdDataxD : signal is "true";
+ attribute keep of RdDataxD : signal is "true";
+ attribute mark_debug of RdValidxS : signal is "true";
+ attribute keep of RdValidxS : signal is "true";
+ attribute mark_debug of WrAddrxD : signal is "true";
+ attribute keep of WrAddrxD : signal is "true";
+ attribute mark_debug of WrDataxD : signal is "true";
+ attribute keep of WrDataxD : signal is "true";
+ attribute mark_debug of WrValidxS : signal is "true";
+ attribute keep of WrValidxS : signal is "true";
+ attribute mark_debug of LocNetAddrPortxDN : signal is "true";
+ attribute keep of LocNetAddrPortxDN : signal is "true";
+ attribute mark_debug of LocNetAddrPortxDP : signal is "true";
+ attribute keep of LocNetAddrPortxDP : signal is "true";
+ attribute mark_debug of SAxiARAddrInDebugxD : signal is "true";
+ attribute keep of SAxiARAddrInDebugxD : signal is "true";
+ attribute mark_debug of SAxiARValidInDebugxS : signal is "true";
+ attribute keep of SAxiARValidInDebugxS : signal is "true";
+ attribute mark_debug of SAxiARReadyOutDebugxS : signal is "true";
+ attribute keep of SAxiARReadyOutDebugxS : signal is "true";
+ attribute mark_debug of SAxiRDataOutDebugxD : signal is "true";
+ attribute keep of SAxiRDataOutDebugxD : signal is "true";
+ attribute mark_debug of SAxiRRespOutDebugxD : signal is "true";
+ attribute keep of SAxiRRespOutDebugxD : signal is "true";
+ attribute mark_debug of SAxiRValidOutDebugxS : signal is "true";
+ attribute keep of SAxiRValidOutDebugxS : signal is "true";
+ attribute mark_debug of SAxiRReadyInDebugxS : signal is "true";
+ attribute keep of SAxiRReadyInDebugxS : signal is "true";
begin
@@ -155,27 +177,40 @@ begin
assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
report "AWADDR and ADDR vectors must be the same" severity failure;
+ DebugxB : block is
+ begin -- block DebugxB
+
+ SAxiARAddrInDebugxAS : SAxiARAddrInDebugxD <= SAxiARAddrxDI;
+ SAxiARValidInDebugxAS : SAxiARValidInDebugxS <= SAxiARValidxSI;
+ SAxiARReadyOutDebugxAS : SAxiARReadyOutDebugxS <= SAxiARReadyxS;
+ SAxiRDataOutDebugxAS : SAxiRDataOutDebugxD <= RdDataxD;
+ SAxiRRespOutDebugxAS : SAxiRRespOutDebugxD <= C_AXI4_RRESP_OKAY;
+ SAxiRValidOutDebugxAS : SAxiRValidOutDebugxS <= SAxiRValidxS;
+ SAxiRReadyInDebugxAS : SAxiRReadyInDebugxS <= SAxiRReadyxSI;
+
+ end block DebugxB;
+
EntityIOxB : block is
begin -- block EntityIOxB
-- Clock and reset
- SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
- SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
+ SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
+ SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
-- Read Channel
- SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
- SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
- SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
- RdValidxAS : RdValidxS <= SAxiARValidxSI;
- RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
- SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
+ SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
+ SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
+ SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
+ RdValidxAS : RdValidxS <= SAxiARValidxSI;
+ RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
+ SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
-- Write Channel
- SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
- SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
- SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
- SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
- WrValidxAS : WrValidxS <= SAxiWValidxSI;
- WrDataxAS : WrDataxD <= SAxiWDataxDI;
- WrAddrOutxAS : WrAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0);
+ SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
+ SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
+ SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
+ SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
+ WrValidxAS : WrValidxS <= SAxiWValidxSI;
+ WrDataxAS : WrDataxD <= SAxiWDataxDI;
+ WrAddrOutxAS : WrAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0);
-- WrAddrOutxAS : WrAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when SAxiAWValidxSI = '1' else WrAddrxDP;
-- WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when SAxiAWValidxSI = '1' else WrAddrxDP;
@@ -347,12 +382,13 @@ begin
end if;
end process WriteRegPortxP;
- ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is
+ ReadRegPortxP : process (SAxiClkxCI, SAxiRstxRAN) is
begin -- process ReadRegPortxP
if SAxiRstxRAN = '0' then
RdDataxD <= (others => '0');
- elsif rising_edge(SAxiClkxC) then
- RdDataxD <= (others => '0');
+
+ elsif rising_edge(SAxiClkxCI) then
+ RdDataxD <= RdDataxD;
if RdValidxS = '1' then
case RdAddrxD is
@@ -364,7 +400,6 @@ begin
when x"020" => RdDataxD <= RXWrDataCntPortxDP;
when x"024" => RdDataxD <= RXRdDataCntPortxDP;
when x"028" => RdDataxD <= LocNetAddrPortxDP;
-
when others => RdDataxD <= (others => '0');
end case;
end if;
--
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