diff --git a/CPU/CPU.circ b/CPU/CPU.circ
index 3eace0bf82dc16963c995b07d47f2f8bd0eaca98..32be21f9466696f5cd2c4c09f162752270cb4ece 100644
--- a/CPU/CPU.circ
+++ b/CPU/CPU.circ
@@ -1,12 +1,18 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project source="3.7.2" version="1.0">
- This file is intended to be loaded by Logisim-evolution v3.7.2(https://github.com/logisim-evolution/).
+<project source="3.0.0" version="1.0">
+ This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="fanout" val="32"/>
<a name="incoming" val="32"/>
</tool>
+ <tool name="Pin">
+ <a name="appearance" val="NewPins"/>
+ </tool>
+ <tool name="Probe">
+ <a name="appearance" val="NewPins"/>
+ </tool>
<tool name="Tunnel">
<a name="facing" val="east"/>
</tool>
@@ -16,13 +22,54 @@
<a name="facing" val="north"/>
</tool>
</lib>
- <lib desc="#Plexers" name="2"/>
+ <lib desc="#Plexers" name="2">
+ <tool name="Multiplexer">
+ <a name="enable" val="false"/>
+ </tool>
+ <tool name="Demultiplexer">
+ <a name="enable" val="false"/>
+ </tool>
+ </lib>
<lib desc="#Arithmetic" name="3"/>
- <lib desc="#Memory" name="4"/>
+ <lib desc="#Memory" name="4">
+ <tool name="D Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="T Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="J-K Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="S-R Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="Counter">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="Shift Register">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="Random">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="RAM">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="ROM">
+ <a name="contents">addr/data: 8 8
+0
+</a>
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ </lib>
<lib desc="#I/O" name="5"/>
<lib desc="#Base" name="6">
<tool name="Text Tool">
+ <a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
+ <a name="halign" val="center"/>
+ <a name="valign" val="base"/>
</tool>
</lib>
<main name="TOP"/>
@@ -30,6 +77,7 @@
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
+ <a name="tickmain" val="half_period"/>
</options>
<mappings>
<tool lib="6" map="Button2" name="Menu Tool"/>
@@ -40,56 +88,306 @@
<tool lib="6" name="Poke Tool"/>
<tool lib="6" name="Edit Tool"/>
<tool lib="6" name="Text Tool">
+ <a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
+ <a name="halign" val="center"/>
+ <a name="valign" val="base"/>
</tool>
<sep/>
- <tool lib="0" name="Pin"/>
+ <tool lib="0" name="Pin">
+ <a name="appearance" val="NewPins"/>
+ </tool>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
+ <a name="appearance" val="NewPins"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="CPU">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="CPU"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="custom"/>
<a name="circuitnamedboxfixedsize" val="true"/>
- <comp lib="0" loc="(1030,470)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- </comp>
- <comp lib="0" loc="(1090,690)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="OFFSET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="6"/>
- </comp>
- <comp lib="0" loc="(1090,710)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="EN_LOAD"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(1090,730)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="EN_STORE"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
+ <a name="circuitvhdlpath" val=""/>
+ <appear>
+ <rect height="3" stroke="none" width="10" x="50" y="59"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="64">CLK</text>
+ <rect height="3" stroke="none" width="10" x="50" y="79"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="84">RESET</text>
+ <rect height="4" stroke="none" width="10" x="50" y="98"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="104">WB_RAM</text>
+ <rect height="4" stroke="none" width="10" x="260" y="58"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="64">RAM_ADDR</text>
+ <rect height="4" stroke="none" width="10" x="260" y="78"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="84">RAM_DATA_WR</text>
+ <rect height="3" stroke="none" width="10" x="260" y="99"/>
+ <circ-port height="10" pin="1890,1160" width="10" x="265" y="75"/>
+ <circ-port height="10" pin="1890,1130" width="10" x="265" y="55"/>
+ <circ-port height="8" pin="310,80" width="8" x="46" y="96"/>
+ <circ-port height="8" pin="240,60" width="8" x="46" y="76"/>
+ <circ-port height="8" pin="240,40" width="8" x="46" y="56"/>
+ <circ-port height="10" pin="1960,1180" width="10" x="265" y="95"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="104">RAM_EN_WR</text>
+ <rect height="20" stroke="none" width="200" x="60" y="110"/>
+ <rect fill="none" height="80" stroke="#000000" stroke-width="2" width="200" x="60" y="50"/>
+ <text dominant-baseline="alphabetic" fill="#ffffff" font-family="Courier 10 Pitch" font-size="14" font-weight="bold" text-anchor="middle" x="160" y="124">CPU</text>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,50)" stroke-width="0" width="13" x="122" y="63"/>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,180)" stroke-width="0" width="13" x="122" y="73"/>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,310)" stroke-width="0" width="13" x="122" y="83"/>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,440)" stroke-width="0" width="13" x="122" y="93"/>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,570)" stroke-width="0" width="13" x="140" y="63"/>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,700)" stroke-width="0" width="13" x="140" y="73"/>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,830)" stroke-width="0" width="13" x="140" y="93"/>
+ <visible-register height="10" path="/CPU_REG_BANK(990,610)/Register(690,960)" stroke-width="0" width="13" x="140" y="83"/>
+ <visible-register height="10" path="/Register(810,210)" stroke-width="0" width="13" x="130" y="53"/>
+ <circ-anchor facing="east" height="6" width="6" x="267" y="57"/>
+ </appear>
+ <wire from="(2210,230)" to="(2240,230)"/>
+ <wire from="(1610,250)" to="(1610,280)"/>
+ <wire from="(1880,760)" to="(1880,780)"/>
+ <wire from="(970,1280)" to="(1030,1280)"/>
+ <wire from="(310,630)" to="(310,640)"/>
+ <wire from="(730,520)" to="(730,610)"/>
+ <wire from="(1060,1290)" to="(1120,1290)"/>
+ <wire from="(800,1290)" to="(840,1290)"/>
+ <wire from="(270,670)" to="(270,700)"/>
+ <wire from="(810,1000)" to="(830,1000)"/>
+ <wire from="(810,920)" to="(830,920)"/>
+ <wire from="(1650,280)" to="(1910,280)"/>
+ <wire from="(410,680)" to="(430,680)"/>
+ <wire from="(1950,230)" to="(1960,230)"/>
+ <wire from="(680,690)" to="(770,690)"/>
+ <wire from="(1130,570)" to="(1130,630)"/>
+ <wire from="(870,1100)" to="(1030,1100)"/>
+ <wire from="(1670,110)" to="(1680,110)"/>
+ <wire from="(1670,190)" to="(1680,190)"/>
+ <wire from="(1620,1180)" to="(1630,1180)"/>
+ <wire from="(1940,210)" to="(1960,210)"/>
+ <wire from="(1910,280)" to="(2190,280)"/>
+ <wire from="(1680,110)" to="(1700,110)"/>
+ <wire from="(1680,190)" to="(1700,190)"/>
+ <wire from="(1700,690)" to="(1720,690)"/>
+ <wire from="(1820,720)" to="(1850,720)"/>
+ <wire from="(800,280)" to="(810,280)"/>
+ <wire from="(1030,1140)" to="(1050,1140)"/>
+ <wire from="(1860,1160)" to="(1890,1160)"/>
+ <wire from="(980,1190)" to="(1030,1190)"/>
+ <wire from="(870,1480)" to="(920,1480)"/>
+ <wire from="(1870,1050)" to="(1910,1050)"/>
+ <wire from="(2410,250)" to="(2430,250)"/>
+ <wire from="(240,450)" to="(240,460)"/>
+ <wire from="(1940,150)" to="(1940,170)"/>
+ <wire from="(2190,240)" to="(2190,280)"/>
+ <wire from="(1030,1160)" to="(1030,1190)"/>
+ <wire from="(530,750)" to="(570,750)"/>
+ <wire from="(270,430)" to="(270,510)"/>
+ <wire from="(790,1170)" to="(830,1170)"/>
+ <wire from="(1790,1040)" to="(1840,1040)"/>
+ <wire from="(490,700)" to="(490,730)"/>
+ <wire from="(680,250)" to="(680,270)"/>
+ <wire from="(600,630)" to="(770,630)"/>
+ <wire from="(790,1190)" to="(810,1190)"/>
+ <wire from="(2190,280)" to="(2380,280)"/>
+ <wire from="(740,650)" to="(770,650)"/>
+ <wire from="(740,730)" to="(770,730)"/>
+ <wire from="(440,1160)" to="(460,1160)"/>
+ <wire from="(930,120)" to="(960,120)"/>
+ <wire from="(870,940)" to="(900,940)"/>
+ <wire from="(1910,1000)" to="(1910,1050)"/>
+ <wire from="(1800,950)" to="(1800,1130)"/>
+ <wire from="(260,430)" to="(270,430)"/>
+ <wire from="(810,1200)" to="(940,1200)"/>
+ <wire from="(610,210)" to="(680,210)"/>
+ <wire from="(1670,230)" to="(1690,230)"/>
+ <wire from="(1400,670)" to="(1430,670)"/>
+ <wire from="(240,60)" to="(380,60)"/>
+ <wire from="(480,610)" to="(480,670)"/>
+ <wire from="(1610,280)" to="(1650,280)"/>
+ <wire from="(1760,590)" to="(1800,590)"/>
+ <wire from="(580,600)" to="(580,610)"/>
+ <wire from="(540,220)" to="(540,360)"/>
+ <wire from="(430,610)" to="(480,610)"/>
+ <wire from="(440,700)" to="(490,700)"/>
+ <wire from="(2380,240)" to="(2380,280)"/>
+ <wire from="(440,700)" to="(440,710)"/>
+ <wire from="(510,270)" to="(680,270)"/>
+ <wire from="(840,300)" to="(840,330)"/>
+ <wire from="(1210,540)" to="(1210,610)"/>
+ <wire from="(800,1310)" to="(840,1310)"/>
+ <wire from="(870,1300)" to="(910,1300)"/>
+ <wire from="(800,1280)" to="(970,1280)"/>
+ <wire from="(1660,1020)" to="(1660,1150)"/>
+ <wire from="(810,1020)" to="(830,1020)"/>
+ <wire from="(810,940)" to="(830,940)"/>
+ <wire from="(960,1300)" to="(960,1340)"/>
+ <wire from="(250,700)" to="(270,700)"/>
+ <wire from="(1930,150)" to="(1940,150)"/>
+ <wire from="(1950,250)" to="(1960,250)"/>
+ <wire from="(460,670)" to="(480,670)"/>
+ <wire from="(210,420)" to="(230,420)"/>
+ <wire from="(1690,230)" to="(1700,230)"/>
+ <wire from="(1650,1150)" to="(1660,1150)"/>
+ <wire from="(2410,190)" to="(2410,210)"/>
+ <wire from="(1880,970)" to="(1900,970)"/>
+ <wire from="(1940,150)" to="(1960,150)"/>
+ <wire from="(1590,280)" to="(1610,280)"/>
+ <wire from="(1680,210)" to="(1700,210)"/>
+ <wire from="(1680,130)" to="(1700,130)"/>
+ <wire from="(1660,1150)" to="(1680,1150)"/>
+ <wire from="(1700,630)" to="(1720,630)"/>
+ <wire from="(200,550)" to="(340,550)"/>
+ <wire from="(1350,280)" to="(1370,280)"/>
+ <wire from="(1820,740)" to="(1850,740)"/>
+ <wire from="(1030,1160)" to="(1050,1160)"/>
+ <wire from="(560,620)" to="(570,620)"/>
+ <wire from="(910,1300)" to="(960,1300)"/>
+ <wire from="(1310,480)" to="(1310,630)"/>
+ <wire from="(230,610)" to="(290,610)"/>
+ <wire from="(2410,190)" to="(2430,190)"/>
+ <wire from="(360,520)" to="(730,520)"/>
+ <wire from="(1680,70)" to="(1680,90)"/>
+ <wire from="(1680,150)" to="(1680,170)"/>
+ <wire from="(910,1300)" to="(910,1330)"/>
+ <wire from="(2400,190)" to="(2410,190)"/>
+ <wire from="(460,200)" to="(570,200)"/>
+ <wire from="(1790,1060)" to="(1840,1060)"/>
+ <wire from="(1620,1130)" to="(1670,1130)"/>
+ <wire from="(480,670)" to="(770,670)"/>
+ <wire from="(1600,1020)" to="(1660,1020)"/>
+ <wire from="(810,1390)" to="(830,1390)"/>
+ <wire from="(810,1470)" to="(830,1470)"/>
+ <wire from="(970,1280)" to="(970,1320)"/>
+ <wire from="(680,210)" to="(710,210)"/>
+ <wire from="(440,1180)" to="(460,1180)"/>
+ <wire from="(720,240)" to="(810,240)"/>
+ <wire from="(870,240)" to="(900,240)"/>
+ <wire from="(960,1300)" to="(1030,1300)"/>
+ <wire from="(1030,1100)" to="(1030,1140)"/>
+ <wire from="(230,650)" to="(300,650)"/>
+ <wire from="(680,230)" to="(690,230)"/>
+ <wire from="(1930,980)" to="(1960,980)"/>
+ <wire from="(1860,1180)" to="(1960,1180)"/>
+ <wire from="(1760,610)" to="(1800,610)"/>
+ <wire from="(1950,230)" to="(1950,250)"/>
+ <wire from="(340,540)" to="(340,550)"/>
+ <wire from="(540,360)" to="(900,360)"/>
+ <wire from="(740,1270)" to="(780,1270)"/>
+ <wire from="(490,290)" to="(490,310)"/>
+ <wire from="(1060,1330)" to="(1120,1330)"/>
+ <wire from="(1700,610)" to="(1760,610)"/>
+ <wire from="(700,260)" to="(700,280)"/>
+ <wire from="(240,40)" to="(390,40)"/>
+ <wire from="(150,540)" to="(170,540)"/>
+ <wire from="(210,440)" to="(230,440)"/>
+ <wire from="(870,1010)" to="(900,1010)"/>
+ <wire from="(900,240)" to="(930,240)"/>
+ <wire from="(1670,70)" to="(1680,70)"/>
+ <wire from="(1670,150)" to="(1680,150)"/>
+ <wire from="(1690,250)" to="(1700,250)"/>
+ <wire from="(1880,990)" to="(1900,990)"/>
+ <wire from="(1910,700)" to="(1930,700)"/>
+ <wire from="(1940,170)" to="(1960,170)"/>
+ <wire from="(1610,1200)" to="(1630,1200)"/>
+ <wire from="(1680,70)" to="(1700,70)"/>
+ <wire from="(1680,150)" to="(1700,150)"/>
+ <wire from="(1700,650)" to="(1720,650)"/>
+ <wire from="(1720,1140)" to="(1750,1140)"/>
+ <wire from="(950,230)" to="(960,230)"/>
+ <wire from="(600,740)" to="(680,740)"/>
+ <wire from="(1080,1150)" to="(1100,1150)"/>
+ <wire from="(1800,1130)" to="(1890,1130)"/>
+ <wire from="(560,640)" to="(570,640)"/>
+ <wire from="(270,510)" to="(330,510)"/>
+ <wire from="(1030,610)" to="(1210,610)"/>
+ <wire from="(1740,700)" to="(1850,700)"/>
+ <wire from="(2410,210)" to="(2430,210)"/>
+ <wire from="(230,720)" to="(230,730)"/>
+ <wire from="(1940,190)" to="(1940,210)"/>
+ <wire from="(440,690)" to="(440,700)"/>
+ <wire from="(800,1300)" to="(840,1300)"/>
+ <wire from="(990,610)" to="(1030,610)"/>
+ <wire from="(330,660)" to="(430,660)"/>
+ <wire from="(1130,630)" to="(1310,630)"/>
+ <wire from="(680,210)" to="(680,230)"/>
+ <wire from="(810,1090)" to="(830,1090)"/>
+ <wire from="(810,1410)" to="(830,1410)"/>
+ <wire from="(810,1490)" to="(830,1490)"/>
+ <wire from="(810,850)" to="(830,850)"/>
+ <wire from="(960,120)" to="(960,230)"/>
+ <wire from="(560,600)" to="(580,600)"/>
+ <wire from="(440,1120)" to="(460,1120)"/>
+ <wire from="(460,260)" to="(480,260)"/>
+ <wire from="(110,710)" to="(130,710)"/>
+ <wire from="(1910,240)" to="(1910,280)"/>
+ <wire from="(680,690)" to="(680,740)"/>
+ <wire from="(1580,250)" to="(1610,250)"/>
+ <wire from="(680,250)" to="(690,250)"/>
+ <wire from="(1310,630)" to="(1480,630)"/>
+ <wire from="(810,1190)" to="(810,1200)"/>
+ <wire from="(870,1400)" to="(930,1400)"/>
+ <wire from="(1690,230)" to="(1690,250)"/>
+ <wire from="(1650,1150)" to="(1650,1170)"/>
+ <wire from="(1670,990)" to="(1670,1130)"/>
+ <wire from="(530,750)" to="(530,770)"/>
+ <wire from="(1210,610)" to="(1480,610)"/>
+ <wire from="(270,670)" to="(300,670)"/>
+ <wire from="(1670,950)" to="(1800,950)"/>
+ <wire from="(540,220)" to="(570,220)"/>
+ <wire from="(1930,190)" to="(1940,190)"/>
+ <wire from="(150,560)" to="(170,560)"/>
+ <wire from="(870,870)" to="(900,870)"/>
+ <wire from="(1670,1130)" to="(1680,1130)"/>
+ <wire from="(2410,230)" to="(2410,250)"/>
+ <wire from="(1940,190)" to="(1960,190)"/>
+ <wire from="(1450,650)" to="(1480,650)"/>
+ <wire from="(210,710)" to="(220,710)"/>
+ <wire from="(1680,170)" to="(1700,170)"/>
+ <wire from="(1680,90)" to="(1700,90)"/>
+ <wire from="(1700,670)" to="(1720,670)"/>
+ <wire from="(490,730)" to="(570,730)"/>
+ <wire from="(1770,1130)" to="(1800,1130)"/>
+ <wire from="(800,260)" to="(810,260)"/>
+ <wire from="(860,1180)" to="(940,1180)"/>
+ <wire from="(310,80)" to="(380,80)"/>
+ <wire from="(970,1320)" to="(1020,1320)"/>
+ <wire from="(2410,230)" to="(2430,230)"/>
+ <wire from="(1680,110)" to="(1680,130)"/>
+ <wire from="(1680,190)" to="(1680,210)"/>
+ <wire from="(1030,480)" to="(1030,610)"/>
+ <wire from="(1760,590)" to="(1760,610)"/>
+ <wire from="(2400,230)" to="(2410,230)"/>
+ <wire from="(730,610)" to="(770,610)"/>
+ <wire from="(470,740)" to="(570,740)"/>
+ <wire from="(810,1110)" to="(830,1110)"/>
+ <wire from="(810,1190)" to="(830,1190)"/>
+ <wire from="(810,870)" to="(830,870)"/>
+ <wire from="(310,530)" to="(330,530)"/>
+ <wire from="(740,710)" to="(770,710)"/>
+ <wire from="(440,1140)" to="(460,1140)"/>
+ <wire from="(460,280)" to="(480,280)"/>
+ <wire from="(1930,230)" to="(1950,230)"/>
+ <wire from="(1650,240)" to="(1650,280)"/>
+ <wire from="(960,1340)" to="(1030,1340)"/>
+ <wire from="(900,240)" to="(900,360)"/>
+ <wire from="(1650,990)" to="(1670,990)"/>
+ <wire from="(150,690)" to="(220,690)"/>
+ <wire from="(960,230)" to="(970,230)"/>
+ <wire from="(990,630)" to="(1130,630)"/>
<comp lib="0" loc="(110,710)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="16"/>
<a name="label" val="INSTRUCTION"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="16"/>
</comp>
<comp lib="0" loc="(1100,1150)" name="Tunnel">
<a name="label" val="EN_COND_JUMP"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(1100,670)" name="Constant">
- <a name="value" val="0x0"/>
- <a name="width" val="2"/>
- </comp>
<comp lib="0" loc="(1120,1290)" name="Tunnel">
<a name="label" val="EN_BR"/>
<a name="labelfont" val="SansSerif bold 8"/>
@@ -100,45 +398,19 @@
</comp>
<comp lib="0" loc="(1130,570)" name="Tunnel">
<a name="facing" val="south"/>
+ <a name="width" val="8"/>
<a name="label" val="CPU_REG_BANK_OUT_B"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1130,660)" name="Splitter">
- <a name="bit1" val="0"/>
- <a name="bit2" val="1"/>
- <a name="bit3" val="1"/>
- <a name="bit4" val="1"/>
- <a name="bit5" val="1"/>
- <a name="bit6" val="1"/>
- <a name="bit7" val="1"/>
- <a name="facing" val="west"/>
- <a name="incoming" val="8"/>
- <a name="spacing" val="2"/>
- </comp>
- <comp lib="0" loc="(1150,470)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- </comp>
- <comp lib="0" loc="(1160,350)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="PC"/>
- <a name="width" val="7"/>
</comp>
<comp lib="0" loc="(1210,540)" name="Tunnel">
<a name="facing" val="south"/>
+ <a name="width" val="8"/>
<a name="label" val="CPU_REG_BANK_OUT_A"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(130,710)" name="Splitter">
+ <a name="incoming" val="16"/>
<a name="bit1" val="0"/>
- <a name="bit10" val="none"/>
- <a name="bit11" val="none"/>
- <a name="bit12" val="none"/>
- <a name="bit13" val="none"/>
- <a name="bit14" val="none"/>
- <a name="bit15" val="none"/>
<a name="bit2" val="0"/>
<a name="bit3" val="0"/>
<a name="bit4" val="0"/>
@@ -147,240 +419,54 @@
<a name="bit7" val="0"/>
<a name="bit8" val="none"/>
<a name="bit9" val="none"/>
- <a name="incoming" val="16"/>
- </comp>
- <comp lib="0" loc="(1390,320)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="INSTRUCTION"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="16"/>
+ <a name="bit10" val="none"/>
+ <a name="bit11" val="none"/>
+ <a name="bit12" val="none"/>
+ <a name="bit13" val="none"/>
+ <a name="bit14" val="none"/>
+ <a name="bit15" val="none"/>
</comp>
<comp lib="0" loc="(1400,670)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="OP_CODE"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(1400,920)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="EN_INCON_JUMP"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(1400,940)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="EN_COND_JUMP"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(1430,1000)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RES_ALU"/>
+ <a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(1430,670)" name="Splitter">
- <a name="bit1" val="0"/>
- <a name="bit2" val="0"/>
- <a name="bit3" val="1"/>
<a name="incoming" val="4"/>
- </comp>
- <comp lib="0" loc="(1450,1000)" name="Splitter">
- <a name="bit1" val="0"/>
- <a name="bit2" val="0"/>
- <a name="bit3" val="0"/>
- <a name="bit4" val="0"/>
- <a name="bit5" val="none"/>
- <a name="bit6" val="none"/>
- <a name="bit7" val="none"/>
- <a name="facing" val="south"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="8"/>
- </comp>
- <comp lib="0" loc="(1460,310)" name="Splitter">
<a name="bit1" val="0"/>
- <a name="bit10" val="3"/>
- <a name="bit11" val="3"/>
- <a name="bit12" val="4"/>
- <a name="bit13" val="4"/>
- <a name="bit14" val="4"/>
- <a name="bit15" val="4"/>
<a name="bit2" val="0"/>
<a name="bit3" val="1"/>
- <a name="bit4" val="1"/>
- <a name="bit5" val="1"/>
- <a name="bit6" val="2"/>
- <a name="bit7" val="2"/>
- <a name="bit8" val="2"/>
- <a name="bit9" val="3"/>
- <a name="fanout" val="5"/>
- <a name="incoming" val="16"/>
- <a name="spacing" val="4"/>
</comp>
- <comp lib="0" loc="(1470,1040)" name="Tunnel">
+ <comp lib="0" loc="(150,540)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="CPU_REG_BANK_OUT_B"/>
+ <a name="label" val="EN_LOAD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
- <comp lib="0" loc="(1470,1060)" name="Tunnel">
+ <comp lib="0" loc="(150,560)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="EN_STORE"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(1490,850)" name="Constant">
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1490,870)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="INSTR_TO_JUMP"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(150,540)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="EN_LOAD"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(150,560)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="EN_STORE"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(1500,1040)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="RAM_DATA_WR"/>
- <a name="output" val="true"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1510,140)" name="Tunnel">
- <a name="label" val="RESERVED"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(1510,160)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(1510,180)" name="Tunnel">
- <a name="label" val="SOURCE_1"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(1510,200)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(1510,220)" name="Tunnel">
- <a name="label" val="SOURCE_0"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(1510,240)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(1510,260)" name="Tunnel">
- <a name="label" val="RESULT"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(1510,280)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(1510,300)" name="Tunnel">
- <a name="label" val="OP_CODE"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(1510,320)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(1530,1020)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="RAM_ADDR"/>
- <a name="output" val="true"/>
- <a name="width" val="5"/>
- </comp>
- <comp lib="0" loc="(1570,1060)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="RAM_EN_WR"/>
- <a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1570,860)" name="Tunnel">
- <a name="label" val="INC_PC"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1720,310)" name="Splitter">
- <a name="bit1" val="0"/>
- <a name="bit10" val="1"/>
- <a name="bit11" val="1"/>
- <a name="bit12" val="2"/>
- <a name="bit13" val="2"/>
- <a name="bit14" val="2"/>
- <a name="bit15" val="2"/>
- <a name="bit2" val="0"/>
- <a name="bit3" val="0"/>
- <a name="bit4" val="0"/>
- <a name="bit5" val="0"/>
- <a name="bit6" val="0"/>
- <a name="bit7" val="0"/>
- <a name="bit8" val="1"/>
- <a name="bit9" val="1"/>
- <a name="fanout" val="3"/>
- <a name="incoming" val="16"/>
- <a name="spacing" val="4"/>
- </comp>
<comp lib="0" loc="(1740,700)" name="Splitter">
+ <a name="facing" val="west"/>
+ <a name="fanout" val="4"/>
+ <a name="incoming" val="4"/>
<a name="appear" val="right"/>
+ <a name="spacing" val="2"/>
<a name="bit0" val="3"/>
<a name="bit1" val="2"/>
<a name="bit2" val="1"/>
<a name="bit3" val="0"/>
- <a name="facing" val="west"/>
- <a name="fanout" val="4"/>
- <a name="incoming" val="4"/>
- <a name="spacing" val="2"/>
- </comp>
- <comp lib="0" loc="(1770,220)" name="Tunnel">
- <a name="label" val="INSTR_TO_JUMP"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1770,240)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(1770,260)" name="Tunnel">
- <a name="label" val="FLAGS_CONDITION"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(1770,280)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(1770,300)" name="Tunnel">
- <a name="label" val="OP_CODE"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(1770,320)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(1800,590)" name="Probe">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(1800,610)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="RES_ALU"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(1820,720)" name="Tunnel">
<a name="facing" val="east"/>
@@ -398,102 +484,39 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(1930,700)" name="Tunnel">
- <a name="label" val="LAST_FLAGS"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(2000,310)" name="Splitter">
- <a name="bit0" val="none"/>
- <a name="bit1" val="none"/>
- <a name="bit10" val="0"/>
- <a name="bit11" val="0"/>
- <a name="bit12" val="none"/>
- <a name="bit13" val="none"/>
- <a name="bit14" val="none"/>
- <a name="bit15" val="none"/>
- <a name="bit2" val="none"/>
- <a name="bit3" val="none"/>
- <a name="bit4" val="none"/>
- <a name="bit5" val="none"/>
- <a name="bit6" val="none"/>
- <a name="bit7" val="none"/>
- <a name="bit8" val="none"/>
- <a name="bit9" val="0"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="16"/>
- <a name="spacing" val="4"/>
- </comp>
- <comp lib="0" loc="(2050,300)" name="Tunnel">
- <a name="label" val="ADDR_RL"/>
+ <a name="label" val="LAST_FLAGS"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(210,420)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="SOURCE_0"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(210,440)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="ADDR_RL"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(210,710)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="PC_1"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(2190,310)" name="Splitter">
- <a name="bit1" val="0"/>
- <a name="bit10" val="none"/>
- <a name="bit11" val="none"/>
- <a name="bit12" val="none"/>
- <a name="bit13" val="none"/>
- <a name="bit14" val="none"/>
- <a name="bit15" val="none"/>
- <a name="bit2" val="0"/>
- <a name="bit3" val="0"/>
- <a name="bit4" val="0"/>
- <a name="bit5" val="0"/>
- <a name="bit6" val="1"/>
- <a name="bit7" val="1"/>
- <a name="bit8" val="1"/>
- <a name="bit9" val="none"/>
- <a name="incoming" val="16"/>
- <a name="spacing" val="4"/>
- </comp>
- <comp lib="0" loc="(2240,260)" name="Tunnel">
- <a name="label" val="OFFSET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="6"/>
- </comp>
- <comp lib="0" loc="(2240,280)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- </comp>
- <comp lib="0" loc="(2240,300)" name="Tunnel">
- <a name="label" val="ADD_POINTER"/>
+ <a name="label" val="PC_1"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(2240,320)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(230,610)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(230,650)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="RES_ALU"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(230,730)" name="Tunnel">
<a name="facing" val="north"/>
@@ -506,156 +529,87 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(290,610)" name="Splitter">
+ <a name="facing" val="south"/>
+ <a name="incoming" val="4"/>
<a name="bit0" val="1"/>
<a name="bit2" val="1"/>
<a name="bit3" val="0"/>
- <a name="facing" val="south"/>
- <a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(310,530)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD_POINTER"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(370,170)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="CLK"/>
- </comp>
- <comp lib="0" loc="(370,190)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="RESET"/>
</comp>
<comp lib="0" loc="(410,680)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="RAM_OUT"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(440,1120)" name="Constant">
- <a name="value" val="0xb"/>
<a name="width" val="4"/>
+ <a name="value" val="0xb"/>
</comp>
<comp lib="0" loc="(440,1140)" name="Constant">
- <a name="value" val="0xa"/>
<a name="width" val="4"/>
+ <a name="value" val="0xa"/>
</comp>
<comp lib="0" loc="(440,1160)" name="Constant">
- <a name="value" val="0xc"/>
<a name="width" val="4"/>
+ <a name="value" val="0xc"/>
</comp>
<comp lib="0" loc="(440,1180)" name="Constant">
- <a name="value" val="0xd"/>
<a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(440,210)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="WB_RAM"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(440,700)" name="Tunnel">
- <a name="facing" val="north"/>
- <a name="label" val="EN_LOAD"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(450,330)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="INC_PC"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(450,390)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CPU_REG_BANK_OUT_A"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(450,410)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="INSTR_TO_JUMP"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
+ <a name="value" val="0xd"/>
</comp>
<comp lib="0" loc="(460,1120)" name="Tunnel">
+ <a name="width" val="4"/>
<a name="label" val="INSTR_INCOND_JUMP"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(460,1140)" name="Tunnel">
+ <a name="width" val="4"/>
<a name="label" val="INSTR_COND_JUMP"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(460,1160)" name="Tunnel">
+ <a name="width" val="4"/>
<a name="label" val="INSTR_LOAD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(460,1180)" name="Tunnel">
+ <a name="width" val="4"/>
<a name="label" val="INSTR_STORE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
- <comp lib="0" loc="(480,440)" name="Tunnel">
- <a name="facing" val="north"/>
- <a name="label" val="EN_BL"/>
+ <comp lib="0" loc="(560,600)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="EN_STORE"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(510,190)" name="Tunnel">
- <a name="label" val="RESET"/>
+ <comp lib="0" loc="(560,620)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="3"/>
+ <a name="label" val="SOURCE_1"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(510,210)" name="Tunnel">
- <a name="label" val="RAM_OUT"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(520,170)" name="Tunnel">
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(560,600)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="EN_STORE"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(560,620)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="SOURCE_1"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
- </comp>
<comp lib="0" loc="(560,640)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="RESULT"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(690,410)" name="Tunnel">
- <a name="facing" val="north"/>
- <a name="label" val="EN_BL_RL"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(700,340)" name="Tunnel">
- <a name="label" val="PC_1"/>
+ <a name="label" val="RESULT"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(740,1270)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(740,650)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="RESULT"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(740,690)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="WE_REG_BANK"/>
+ <a name="label" val="RESULT"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(740,710)" name="Tunnel">
@@ -669,100 +623,89 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(780,1270)" name="Splitter">
- <a name="appear" val="right"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
+ <a name="appear" val="right"/>
</comp>
<comp lib="0" loc="(790,1170)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="LAST_FLAGS"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(790,1190)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="FLAGS_CONDITION"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(790,390)" name="Constant"/>
- <comp lib="0" loc="(790,410)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
+ <a name="label" val="FLAGS_CONDITION"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(810,1000)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,1020)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="INSTR_INCOND_JUMP"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,1090)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,1110)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="INSTR_COND_JUMP"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,1390)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,1410)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="INSTR_LOAD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,1470)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,1490)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="INSTR_STORE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,850)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,870)" name="Constant">
- <a name="value" val="0x8"/>
<a name="width" val="4"/>
+ <a name="value" val="0x8"/>
</comp>
<comp lib="0" loc="(810,920)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="OP_CODE"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(810,940)" name="Constant">
- <a name="value" val="0x9"/>
<a name="width" val="4"/>
- </comp>
- <comp lib="0" loc="(830,460)" name="Tunnel">
- <a name="facing" val="north"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
+ <a name="value" val="0x9"/>
</comp>
<comp lib="0" loc="(900,1010)" name="Tunnel">
<a name="label" val="EN_INCON_JUMP"/>
@@ -785,188 +728,117 @@
<a name="label" val="EN_STORE"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(920,370)" name="Splitter">
- <a name="bit1" val="0"/>
- <a name="bit2" val="0"/>
- <a name="bit3" val="0"/>
- <a name="bit4" val="0"/>
- <a name="bit5" val="0"/>
- <a name="bit6" val="0"/>
- <a name="bit7" val="none"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="8"/>
- </comp>
<comp lib="0" loc="(930,1400)" name="Tunnel">
<a name="label" val="EN_LOAD"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(960,360)" name="Tunnel">
- <a name="label" val="PC"/>
- <a name="width" val="7"/>
- </comp>
<comp lib="1" loc="(1060,1290)" name="AND Gate">
<a name="size" val="30"/>
</comp>
<comp lib="1" loc="(1060,1330)" name="AND Gate">
- <a name="negate0" val="true"/>
<a name="size" val="30"/>
+ <a name="negate0" val="true"/>
</comp>
<comp lib="1" loc="(1080,1150)" name="AND Gate">
<a name="size" val="30"/>
</comp>
- <comp lib="1" loc="(1140,720)" name="OR Gate">
- <a name="size" val="30"/>
- </comp>
- <comp lib="1" loc="(1480,930)" name="OR Gate">
- <a name="size" val="30"/>
- </comp>
<comp lib="1" loc="(200,550)" name="OR Gate">
<a name="size" val="30"/>
</comp>
<comp lib="1" loc="(860,1180)" name="AND Gate">
- <a name="size" val="30"/>
<a name="width" val="4"/>
+ <a name="size" val="30"/>
</comp>
<comp lib="1" loc="(870,1300)" name="AND Gate">
- <a name="inputs" val="3"/>
<a name="size" val="30"/>
- </comp>
- <comp lib="2" loc="(1220,640)" name="Multiplexer">
- <a name="enable" val="true"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="2" loc="(1540,860)" name="Multiplexer">
- <a name="enable" val="true"/>
- <a name="width" val="8"/>
+ <a name="inputs" val="3"/>
</comp>
<comp lib="2" loc="(250,700)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="width" val="8"/>
</comp>
<comp lib="2" loc="(260,430)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="width" val="3"/>
</comp>
<comp lib="2" loc="(330,660)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="selloc" val="tr"/>
<a name="width" val="8"/>
</comp>
<comp lib="2" loc="(360,520)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="width" val="3"/>
</comp>
<comp lib="2" loc="(460,670)" name="Multiplexer">
- <a name="enable" val="true"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="2" loc="(500,400)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="width" val="8"/>
</comp>
<comp lib="2" loc="(600,630)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="selloc" val="tr"/>
<a name="width" val="3"/>
</comp>
- <comp lib="2" loc="(710,370)" name="Multiplexer">
- <a name="enable" val="true"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="3" loc="(600,340)" name="Adder"/>
<comp lib="3" loc="(870,1010)" name="Comparator">
- <a name="mode" val="unsigned"/>
<a name="width" val="4"/>
+ <a name="mode" val="unsigned"/>
</comp>
<comp lib="3" loc="(870,1100)" name="Comparator">
- <a name="mode" val="unsigned"/>
<a name="width" val="4"/>
+ <a name="mode" val="unsigned"/>
</comp>
<comp lib="3" loc="(870,1400)" name="Comparator">
- <a name="mode" val="unsigned"/>
<a name="width" val="4"/>
+ <a name="mode" val="unsigned"/>
</comp>
<comp lib="3" loc="(870,1480)" name="Comparator">
- <a name="mode" val="unsigned"/>
<a name="width" val="4"/>
+ <a name="mode" val="unsigned"/>
</comp>
<comp lib="3" loc="(870,860)" name="Comparator">
- <a name="mode" val="unsigned"/>
<a name="width" val="4"/>
+ <a name="mode" val="unsigned"/>
</comp>
<comp lib="3" loc="(870,930)" name="Comparator">
- <a name="mode" val="unsigned"/>
<a name="width" val="4"/>
+ <a name="mode" val="unsigned"/>
</comp>
<comp lib="3" loc="(980,1190)" name="Comparator">
- <a name="mode" val="unsigned"/>
<a name="width" val="4"/>
+ <a name="mode" val="unsigned"/>
</comp>
<comp lib="4" loc="(1850,670)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
<a name="width" val="4"/>
</comp>
- <comp lib="4" loc="(800,340)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="6" loc="(1481,115)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="ALU"/>
- </comp>
- <comp lib="6" loc="(1508,824)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="JUMP OF INSTR WHEN JUMPING, JUMP OF 1 ELSEWISE"/>
- </comp>
- <comp lib="6" loc="(1778,193)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="JUMPING"/>
- </comp>
- <comp lib="6" loc="(2236,237)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="LD_ST"/>
- </comp>
- <comp lib="6" loc="(414,438)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="Jump to val if BL"/>
- </comp>
<comp lib="6" loc="(808,1373)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="LOAD INSTRUCTION"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(809,1455)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="STORE INSTRUCTION"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(811,1156)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="MASK TO GET THE ONLY BITS YOU WANT"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(837,1069)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="CONDITIONNAL JUMPING WHEN 10 "/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(847,1251)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="BL - BRANCH AND LINK + BR BRANCH REGISTER "/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(852,905)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="ALU + AFFECTATION CONSTANTE"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(857,981)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="INCONDITIONNAL JUMPING"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(860,828)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="AVOID VALID FLAGS AFTER ANYTHING THAT IS NOT ALU CALCULATIONS "/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(863,810)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="ALU INSTRUCTION ONLY, LOWER THAN 8"/>
- </comp>
- <comp loc="(1400,350)" name="CPU_INSTRUCTION_MEMORY">
- <a name="label" val="CIM_1"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp loc="(1700,610)" name="ALU">
<a name="label" val="ALU1"/>
@@ -974,605 +846,890 @@
<comp loc="(990,610)" name="CPU_REG_BANK">
<a name="label" val="CRB"/>
</comp>
- <wire from="(1030,1100)" to="(1030,1140)"/>
- <wire from="(1030,1140)" to="(1050,1140)"/>
- <wire from="(1030,1160)" to="(1030,1190)"/>
- <wire from="(1030,1160)" to="(1050,1160)"/>
- <wire from="(1030,470)" to="(1030,610)"/>
- <wire from="(1030,610)" to="(1210,610)"/>
- <wire from="(1050,480)" to="(1050,630)"/>
- <wire from="(1050,480)" to="(1150,480)"/>
- <wire from="(1050,630)" to="(1130,630)"/>
- <wire from="(1060,1290)" to="(1120,1290)"/>
- <wire from="(1060,1330)" to="(1120,1330)"/>
- <wire from="(1080,1150)" to="(1100,1150)"/>
- <wire from="(1090,690)" to="(1110,690)"/>
- <wire from="(1090,710)" to="(1110,710)"/>
- <wire from="(1090,730)" to="(1110,730)"/>
- <wire from="(110,710)" to="(130,710)"/>
- <wire from="(1100,670)" to="(1110,670)"/>
- <wire from="(1130,570)" to="(1130,630)"/>
- <wire from="(1130,630)" to="(1190,630)"/>
- <wire from="(1130,650)" to="(1130,660)"/>
- <wire from="(1130,650)" to="(1190,650)"/>
- <wire from="(1140,720)" to="(1200,720)"/>
- <wire from="(1150,470)" to="(1150,480)"/>
- <wire from="(1160,350)" to="(1180,350)"/>
- <wire from="(1200,660)" to="(1200,720)"/>
- <wire from="(1210,540)" to="(1210,610)"/>
- <wire from="(1210,610)" to="(1480,610)"/>
- <wire from="(1220,640)" to="(1270,640)"/>
- <wire from="(1270,630)" to="(1270,640)"/>
- <wire from="(1270,630)" to="(1480,630)"/>
- <wire from="(1390,320)" to="(1420,320)"/>
- <wire from="(1400,350)" to="(1420,350)"/>
- <wire from="(1400,670)" to="(1430,670)"/>
- <wire from="(1400,920)" to="(1450,920)"/>
- <wire from="(1400,940)" to="(1450,940)"/>
- <wire from="(1420,320)" to="(1420,350)"/>
- <wire from="(1420,350)" to="(1460,350)"/>
- <wire from="(1430,1000)" to="(1450,1000)"/>
- <wire from="(1450,650)" to="(1480,650)"/>
- <wire from="(1460,1020)" to="(1530,1020)"/>
- <wire from="(1460,310)" to="(1460,350)"/>
- <wire from="(1460,350)" to="(1720,350)"/>
- <wire from="(1470,1040)" to="(1500,1040)"/>
- <wire from="(1470,1060)" to="(1570,1060)"/>
- <wire from="(1480,140)" to="(1490,140)"/>
- <wire from="(1480,180)" to="(1490,180)"/>
- <wire from="(1480,220)" to="(1490,220)"/>
- <wire from="(1480,260)" to="(1490,260)"/>
- <wire from="(1480,300)" to="(1500,300)"/>
- <wire from="(1480,930)" to="(1520,930)"/>
- <wire from="(1490,140)" to="(1490,160)"/>
- <wire from="(1490,140)" to="(1510,140)"/>
- <wire from="(1490,160)" to="(1510,160)"/>
- <wire from="(1490,180)" to="(1490,200)"/>
- <wire from="(1490,180)" to="(1510,180)"/>
- <wire from="(1490,200)" to="(1510,200)"/>
- <wire from="(1490,220)" to="(1490,240)"/>
- <wire from="(1490,220)" to="(1510,220)"/>
- <wire from="(1490,240)" to="(1510,240)"/>
- <wire from="(1490,260)" to="(1490,280)"/>
- <wire from="(1490,260)" to="(1510,260)"/>
- <wire from="(1490,280)" to="(1510,280)"/>
- <wire from="(1490,850)" to="(1510,850)"/>
- <wire from="(1490,870)" to="(1510,870)"/>
- <wire from="(150,540)" to="(170,540)"/>
- <wire from="(150,560)" to="(170,560)"/>
- <wire from="(150,690)" to="(220,690)"/>
- <wire from="(1500,300)" to="(1500,320)"/>
- <wire from="(1500,300)" to="(1510,300)"/>
- <wire from="(1500,320)" to="(1510,320)"/>
- <wire from="(1520,880)" to="(1520,930)"/>
- <wire from="(1540,860)" to="(1570,860)"/>
- <wire from="(1700,610)" to="(1760,610)"/>
- <wire from="(1700,630)" to="(1720,630)"/>
- <wire from="(1700,650)" to="(1720,650)"/>
- <wire from="(1700,670)" to="(1720,670)"/>
- <wire from="(1700,690)" to="(1720,690)"/>
- <wire from="(1720,310)" to="(1720,350)"/>
- <wire from="(1720,350)" to="(2000,350)"/>
- <wire from="(1740,220)" to="(1750,220)"/>
- <wire from="(1740,260)" to="(1750,260)"/>
- <wire from="(1740,300)" to="(1760,300)"/>
- <wire from="(1740,700)" to="(1850,700)"/>
- <wire from="(1750,220)" to="(1750,240)"/>
- <wire from="(1750,220)" to="(1770,220)"/>
- <wire from="(1750,240)" to="(1770,240)"/>
- <wire from="(1750,260)" to="(1750,280)"/>
- <wire from="(1750,260)" to="(1770,260)"/>
- <wire from="(1750,280)" to="(1770,280)"/>
- <wire from="(1760,300)" to="(1760,320)"/>
- <wire from="(1760,300)" to="(1770,300)"/>
- <wire from="(1760,320)" to="(1770,320)"/>
- <wire from="(1760,590)" to="(1760,610)"/>
- <wire from="(1760,590)" to="(1800,590)"/>
- <wire from="(1760,610)" to="(1800,610)"/>
- <wire from="(1820,720)" to="(1850,720)"/>
- <wire from="(1820,740)" to="(1850,740)"/>
- <wire from="(1880,760)" to="(1880,780)"/>
- <wire from="(1910,700)" to="(1930,700)"/>
- <wire from="(200,550)" to="(340,550)"/>
- <wire from="(2000,310)" to="(2000,350)"/>
- <wire from="(2000,350)" to="(2190,350)"/>
- <wire from="(2020,300)" to="(2050,300)"/>
- <wire from="(210,420)" to="(230,420)"/>
- <wire from="(210,440)" to="(230,440)"/>
- <wire from="(210,710)" to="(220,710)"/>
- <wire from="(2190,310)" to="(2190,350)"/>
- <wire from="(2210,260)" to="(2220,260)"/>
- <wire from="(2210,300)" to="(2220,300)"/>
- <wire from="(2220,260)" to="(2220,280)"/>
- <wire from="(2220,260)" to="(2240,260)"/>
- <wire from="(2220,280)" to="(2240,280)"/>
- <wire from="(2220,300)" to="(2220,320)"/>
- <wire from="(2220,300)" to="(2240,300)"/>
- <wire from="(2220,320)" to="(2240,320)"/>
- <wire from="(230,610)" to="(290,610)"/>
- <wire from="(230,650)" to="(300,650)"/>
- <wire from="(230,720)" to="(230,730)"/>
- <wire from="(240,450)" to="(240,460)"/>
- <wire from="(250,700)" to="(270,700)"/>
- <wire from="(260,430)" to="(270,430)"/>
- <wire from="(270,430)" to="(270,510)"/>
- <wire from="(270,510)" to="(330,510)"/>
- <wire from="(270,670)" to="(270,700)"/>
- <wire from="(270,670)" to="(300,670)"/>
- <wire from="(310,530)" to="(330,530)"/>
- <wire from="(310,630)" to="(310,640)"/>
- <wire from="(330,660)" to="(430,660)"/>
- <wire from="(340,540)" to="(340,550)"/>
- <wire from="(360,520)" to="(730,520)"/>
- <wire from="(370,170)" to="(520,170)"/>
- <wire from="(370,190)" to="(510,190)"/>
- <wire from="(410,680)" to="(430,680)"/>
- <wire from="(440,1120)" to="(460,1120)"/>
- <wire from="(440,1140)" to="(460,1140)"/>
- <wire from="(440,1160)" to="(460,1160)"/>
- <wire from="(440,1180)" to="(460,1180)"/>
- <wire from="(440,210)" to="(510,210)"/>
- <wire from="(440,690)" to="(440,700)"/>
- <wire from="(450,330)" to="(560,330)"/>
- <wire from="(450,390)" to="(470,390)"/>
- <wire from="(450,410)" to="(470,410)"/>
- <wire from="(460,670)" to="(770,670)"/>
- <wire from="(480,420)" to="(480,440)"/>
- <wire from="(500,400)" to="(670,400)"/>
- <wire from="(530,350)" to="(530,490)"/>
- <wire from="(530,350)" to="(560,350)"/>
- <wire from="(530,490)" to="(890,490)"/>
- <wire from="(560,600)" to="(580,600)"/>
- <wire from="(560,620)" to="(570,620)"/>
- <wire from="(560,640)" to="(570,640)"/>
- <wire from="(580,600)" to="(580,610)"/>
- <wire from="(600,340)" to="(670,340)"/>
- <wire from="(600,630)" to="(770,630)"/>
- <wire from="(670,340)" to="(670,360)"/>
- <wire from="(670,340)" to="(700,340)"/>
- <wire from="(670,360)" to="(680,360)"/>
- <wire from="(670,380)" to="(670,400)"/>
- <wire from="(670,380)" to="(680,380)"/>
- <wire from="(690,390)" to="(690,410)"/>
- <wire from="(710,370)" to="(800,370)"/>
- <wire from="(730,520)" to="(730,610)"/>
- <wire from="(730,610)" to="(770,610)"/>
- <wire from="(740,1270)" to="(780,1270)"/>
- <wire from="(740,650)" to="(770,650)"/>
- <wire from="(740,690)" to="(770,690)"/>
- <wire from="(740,710)" to="(770,710)"/>
- <wire from="(740,730)" to="(770,730)"/>
- <wire from="(790,1170)" to="(830,1170)"/>
- <wire from="(790,1190)" to="(810,1190)"/>
- <wire from="(790,390)" to="(800,390)"/>
- <wire from="(790,410)" to="(800,410)"/>
- <wire from="(800,1280)" to="(970,1280)"/>
- <wire from="(800,1290)" to="(840,1290)"/>
- <wire from="(800,1300)" to="(840,1300)"/>
- <wire from="(800,1310)" to="(840,1310)"/>
- <wire from="(810,1000)" to="(830,1000)"/>
- <wire from="(810,1020)" to="(830,1020)"/>
- <wire from="(810,1090)" to="(830,1090)"/>
- <wire from="(810,1110)" to="(830,1110)"/>
- <wire from="(810,1190)" to="(810,1200)"/>
- <wire from="(810,1190)" to="(830,1190)"/>
- <wire from="(810,1200)" to="(940,1200)"/>
- <wire from="(810,1390)" to="(830,1390)"/>
- <wire from="(810,1410)" to="(830,1410)"/>
- <wire from="(810,1470)" to="(830,1470)"/>
- <wire from="(810,1490)" to="(830,1490)"/>
- <wire from="(810,850)" to="(830,850)"/>
- <wire from="(810,870)" to="(830,870)"/>
- <wire from="(810,920)" to="(830,920)"/>
- <wire from="(810,940)" to="(830,940)"/>
- <wire from="(830,430)" to="(830,460)"/>
- <wire from="(860,1180)" to="(940,1180)"/>
- <wire from="(860,370)" to="(890,370)"/>
- <wire from="(870,1010)" to="(900,1010)"/>
- <wire from="(870,1100)" to="(1030,1100)"/>
- <wire from="(870,1300)" to="(910,1300)"/>
- <wire from="(870,1400)" to="(930,1400)"/>
- <wire from="(870,1480)" to="(920,1480)"/>
- <wire from="(870,870)" to="(900,870)"/>
- <wire from="(870,940)" to="(900,940)"/>
- <wire from="(890,370)" to="(890,490)"/>
- <wire from="(890,370)" to="(920,370)"/>
- <wire from="(910,1300)" to="(910,1330)"/>
- <wire from="(910,1300)" to="(960,1300)"/>
- <wire from="(940,360)" to="(960,360)"/>
- <wire from="(960,1300)" to="(1030,1300)"/>
- <wire from="(960,1300)" to="(960,1340)"/>
- <wire from="(960,1340)" to="(1030,1340)"/>
- <wire from="(970,1280)" to="(1030,1280)"/>
- <wire from="(970,1280)" to="(970,1320)"/>
- <wire from="(970,1320)" to="(1020,1320)"/>
- <wire from="(980,1190)" to="(1030,1190)"/>
- <wire from="(990,610)" to="(1030,610)"/>
- <wire from="(990,630)" to="(1050,630)"/>
- </circuit>
- <circuit name="CPU_INSTRUCTION_MEMORY">
- <a name="appearance" val="custom"/>
- <a name="circuit" val="CPU_INSTRUCTION_MEMORY"/>
- <a name="circuitnamedboxfixedsize" val="true"/>
- <a name="simulationFrequency" val="1.0"/>
- <comp lib="0" loc="(1040,780)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="mux1"/>
- <a name="width" val="16"/>
- </comp>
- <comp lib="0" loc="(1040,800)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="mux3"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(240,60)" name="Pin">
+ <a name="label" val="RESET"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(1100,870)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="sel"/>
- <a name="width" val="2"/>
+ <comp lib="0" loc="(380,60)" name="Tunnel">
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(1160,700)" name="Probe">
- <a name="appearance" val="classic"/>
- <a name="radix" val="16"/>
+ <comp lib="0" loc="(240,40)" name="Pin">
+ <a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(1210,790)" name="Pin">
- <a name="appearance" val="classic"/>
- <a name="facing" val="west"/>
- <a name="label" val="INSTRUCTION"/>
- <a name="output" val="true"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(380,80)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="RAM_OUT"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(320,540)" name="Pin">
- <a name="appearance" val="classic"/>
- <a name="label" val="ADDR_INSTR"/>
- <a name="width" val="7"/>
+ <comp lib="0" loc="(390,40)" name="Tunnel">
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(340,540)" name="Splitter">
- <a name="appear" val="center"/>
- <a name="bit1" val="0"/>
- <a name="bit2" val="0"/>
- <a name="bit3" val="0"/>
- <a name="bit4" val="0"/>
- <a name="bit5" val="1"/>
- <a name="bit6" val="1"/>
- <a name="incoming" val="7"/>
+ <comp lib="0" loc="(310,80)" name="Pin">
+ <a name="width" val="8"/>
+ <a name="label" val="WB_RAM"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(370,560)" name="Tunnel">
- <a name="label" val="sel"/>
- <a name="width" val="2"/>
+ <comp lib="3" loc="(610,210)" name="Adder"/>
+ <comp lib="0" loc="(460,260)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="CPU_REG_BANK_OUT_A"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,190)" name="Constant">
- <a name="value" val="0x8010"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(490,310)" name="Tunnel">
+ <a name="facing" val="north"/>
+ <a name="label" val="EN_BL"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,210)" name="Constant">
- <a name="value" val="0x8477"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(460,280)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="INSTR_TO_JUMP"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,230)" name="Constant">
- <a name="value" val="0xa802"/>
- <a name="width" val="16"/>
+ <comp lib="2" loc="(720,240)" name="Multiplexer">
+ <a name="width" val="8"/>
</comp>
- <comp lib="0" loc="(440,250)" name="Constant">
- <a name="value" val="0x8461"/>
- <a name="width" val="16"/>
+ <comp lib="6" loc="(424,308)" name="Text">
+ <a name="text" val="Jump to val if BL"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="0" loc="(440,270)" name="Constant">
- <a name="value" val="0xa802"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(840,330)" name="Tunnel">
+ <a name="facing" val="north"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,290)" name="Constant">
- <a name="value" val="0x8473"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(700,280)" name="Tunnel">
+ <a name="facing" val="north"/>
+ <a name="label" val="EN_BL_RL"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,310)" name="Constant">
- <a name="value" val="0xa802"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(970,230)" name="Tunnel">
+ <a name="width" val="7"/>
+ <a name="label" val="PC"/>
</comp>
- <comp lib="0" loc="(440,330)" name="Constant">
- <a name="value" val="0x8464"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(460,200)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="INC_PC"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,350)" name="Constant">
- <a name="value" val="0xa802"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(710,210)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="PC_1"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,370)" name="Constant">
- <a name="value" val="0xbfee"/>
- <a name="width" val="16"/>
+ <comp lib="4" loc="(810,210)" name="Register"/>
+ <comp lib="0" loc="(800,280)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,390)" name="Constant">
- <a name="value" val="0x8a64"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(800,260)" name="Constant"/>
+ <comp lib="0" loc="(930,240)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="8"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="0"/>
+ <a name="bit4" val="0"/>
+ <a name="bit5" val="0"/>
+ <a name="bit6" val="0"/>
+ <a name="bit7" val="none"/>
</comp>
- <comp lib="0" loc="(440,410)" name="Constant">
- <a name="value" val="0x889c"/>
- <a name="width" val="16"/>
+ <comp lib="2" loc="(510,270)" name="Multiplexer">
+ <a name="width" val="8"/>
</comp>
- <comp lib="0" loc="(440,430)" name="Constant">
- <a name="value" val="0xfe00"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(2240,230)" name="Tunnel">
+ <a name="width" val="3"/>
+ <a name="label" val="ADDR_RL"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,450)" name="Constant">
- <a name="value" val="0x8ace"/>
- <a name="width" val="16"/>
+ <comp lib="6" loc="(1968,123)" name="Text">
+ <a name="text" val="JUMPING"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="0" loc="(440,470)" name="Constant">
- <a name="value" val="0x88ce"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1960,150)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="INSTR_TO_JUMP"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(440,490)" name="Constant">
- <a name="value" val="0xfe00"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1700,250)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(480,200)" name="Constant">
- <a name="value" val="0xc200"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1650,240)" name="Splitter">
+ <a name="fanout" val="5"/>
+ <a name="incoming" val="16"/>
+ <a name="spacing" val="4"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="1"/>
+ <a name="bit4" val="1"/>
+ <a name="bit5" val="1"/>
+ <a name="bit6" val="2"/>
+ <a name="bit7" val="2"/>
+ <a name="bit8" val="2"/>
+ <a name="bit9" val="3"/>
+ <a name="bit10" val="3"/>
+ <a name="bit11" val="3"/>
+ <a name="bit12" val="4"/>
+ <a name="bit13" val="4"/>
+ <a name="bit14" val="4"/>
+ <a name="bit15" val="4"/>
</comp>
- <comp lib="0" loc="(480,220)" name="Constant">
- <a name="value" val="0x1650"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1700,70)" name="Tunnel">
+ <a name="width" val="3"/>
+ <a name="label" val="RESERVED"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(480,240)" name="Constant">
- <a name="value" val="0xee13"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1910,240)" name="Splitter">
+ <a name="fanout" val="3"/>
+ <a name="incoming" val="16"/>
+ <a name="spacing" val="4"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="0"/>
+ <a name="bit4" val="0"/>
+ <a name="bit5" val="0"/>
+ <a name="bit6" val="0"/>
+ <a name="bit7" val="0"/>
+ <a name="bit8" val="1"/>
+ <a name="bit9" val="1"/>
+ <a name="bit10" val="1"/>
+ <a name="bit11" val="1"/>
+ <a name="bit12" val="2"/>
+ <a name="bit13" val="2"/>
+ <a name="bit14" val="2"/>
+ <a name="bit15" val="2"/>
</comp>
- <comp lib="0" loc="(480,260)" name="Constant">
- <a name="value" val="0x1650"/>
- <a name="width" val="16"/>
+ <comp lib="6" loc="(1671,45)" name="Text">
+ <a name="text" val="ALU"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="0" loc="(480,280)" name="Constant">
- <a name="value" val="0xee19"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1700,230)" name="Tunnel">
+ <a name="width" val="4"/>
+ <a name="label" val="OP_CODE"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(480,300)" name="Constant">
- <a name="value" val="0x1650"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1700,170)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(480,320)" name="Constant">
- <a name="value" val="0xee16"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(2430,190)" name="Tunnel">
+ <a name="width" val="6"/>
+ <a name="label" val="OFFSET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="0" loc="(480,340)" name="Constant">
- <a name="value" val="0x1650"/>
- <a name="width" val="16"/>
+ <comp lib="6" loc="(2426,167)" name="Text">
+ <a name="text" val="LD_ST"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="0" loc="(480,360)" name="Constant">
- <a name="value" val="0xee19"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1960,210)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(480,380)" name="Constant">
- <a name="value" val="0x8864"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1960,250)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(480,400)" name="Constant">
- <a name="value" val="0xfe00"/>
- <a name="width" val="16"/>
+ <comp loc="(1590,280)" name="CPU_INSTRUCTION_MEMORY">
+ <a name="label" val="CIM_1"/>
</comp>
- <comp lib="0" loc="(480,420)" name="Constant">
- <a name="value" val="0x8a9c"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(1700,130)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(480,440)" name="Constant">
- <a name="value" val="0x8832"/>
- <a name="width" val="16"/>
+ <comp lib="0" loc="(2380,240)" name="Splitter">
+ <a name="incoming" val="16"/>
+ <a name="spacing" val="4"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="0"/>
+ <a name="bit4" val="0"/>
+ <a name="bit5" val="0"/>
+ <a name="bit6" val="1"/>
+ <a name="bit7" val="1"/>
+ <a name="bit8" val="1"/>
+ <a name="bit9" val="none"/>
+ <a name="bit10" val="none"/>
+ <a name="bit11" val="none"/>
+ <a name="bit12" val="none"/>
+ <a name="bit13" val="none"/>
+ <a name="bit14" val="none"/>
+ <a name="bit15" val="none"/>
+ </comp>
+ <comp lib="0" loc="(2430,250)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1960,170)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(2190,240)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="16"/>
+ <a name="spacing" val="4"/>
+ <a name="bit0" val="none"/>
+ <a name="bit1" val="none"/>
+ <a name="bit2" val="none"/>
+ <a name="bit3" val="none"/>
+ <a name="bit4" val="none"/>
+ <a name="bit5" val="none"/>
+ <a name="bit6" val="none"/>
+ <a name="bit7" val="none"/>
+ <a name="bit8" val="none"/>
+ <a name="bit9" val="0"/>
+ <a name="bit10" val="0"/>
+ <a name="bit11" val="0"/>
+ <a name="bit12" val="none"/>
+ <a name="bit13" val="none"/>
+ <a name="bit14" val="none"/>
+ <a name="bit15" val="none"/>
+ </comp>
+ <comp lib="0" loc="(1960,190)" name="Tunnel">
+ <a name="width" val="4"/>
+ <a name="label" val="FLAGS_CONDITION"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(2430,230)" name="Tunnel">
+ <a name="width" val="3"/>
+ <a name="label" val="ADD_POINTER"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1700,190)" name="Tunnel">
+ <a name="width" val="3"/>
+ <a name="label" val="RESULT"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1960,230)" name="Tunnel">
+ <a name="width" val="4"/>
+ <a name="label" val="OP_CODE"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1700,210)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1700,150)" name="Tunnel">
+ <a name="width" val="3"/>
+ <a name="label" val="SOURCE_0"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1700,110)" name="Tunnel">
+ <a name="width" val="3"/>
+ <a name="label" val="SOURCE_1"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1350,280)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="7"/>
+ <a name="label" val="PC"/>
+ </comp>
+ <comp lib="0" loc="(1700,90)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1580,250)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="INSTRUCTION"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(2430,210)" name="Probe">
+ <a name="facing" val="west"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="2" loc="(1930,980)" name="Multiplexer">
+ <a name="width" val="8"/>
+ </comp>
+ <comp lib="0" loc="(1860,1160)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="CPU_REG_BANK_OUT_B"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1880,990)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="INSTR_TO_JUMP"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1890,1160)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="8"/>
+ <a name="label" val="RAM_DATA_WR"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1960,1180)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="RAM_EN_WR"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1790,1060)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="EN_COND_JUMP"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1860,1180)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="EN_STORE"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1960,980)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="INC_PC"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="1" loc="(1870,1050)" name="OR Gate">
+ <a name="size" val="30"/>
+ </comp>
+ <comp lib="0" loc="(1880,970)" name="Constant">
+ <a name="width" val="8"/>
+ </comp>
+ <comp lib="0" loc="(1790,1040)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="EN_INCON_JUMP"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="6" loc="(1898,944)" name="Text">
+ <a name="text" val="JUMP OF INSTR WHEN JUMPING, JUMP OF 1 ELSEWISE"/>
+ <a name="font" val="SansSerif plain 12"/>
+ </comp>
+ <comp lib="0" loc="(1310,480)" name="Probe">
+ <a name="facing" val="south"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1030,480)" name="Probe">
+ <a name="facing" val="south"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="3" loc="(1720,1140)" name="Adder"/>
+ <comp lib="0" loc="(1610,1200)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="6"/>
+ <a name="label" val="OFFSET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(1620,1180)" name="Constant">
+ <a name="width" val="2"/>
+ <a name="value" val="0x0"/>
+ </comp>
+ <comp lib="0" loc="(1650,1170)" name="Splitter">
+ <a name="facing" val="west"/>
+ <a name="incoming" val="8"/>
+ <a name="spacing" val="2"/>
+ <a name="bit0" val="1"/>
+ <a name="bit2" val="1"/>
+ <a name="bit3" val="1"/>
+ <a name="bit4" val="1"/>
+ <a name="bit5" val="1"/>
+ <a name="bit6" val="0"/>
+ <a name="bit7" val="0"/>
+ </comp>
+ <comp lib="0" loc="(1750,1140)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="8"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="0"/>
+ <a name="bit4" val="0"/>
+ <a name="bit5" val="none"/>
+ <a name="bit6" val="none"/>
+ <a name="bit7" val="none"/>
+ </comp>
+ <comp lib="0" loc="(1890,1130)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="5"/>
+ <a name="label" val="RAM_ADDR"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1650,990)" name="Probe">
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1600,1020)" name="Probe">
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(930,120)" name="Probe">
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,950)" name="Probe">
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1620,1130)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="CPU_REG_BANK_OUT_A"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(430,610)" name="Probe">
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="1" loc="(600,740)" name="OR Gate">
+ <a name="size" val="30"/>
+ <a name="inputs" val="3"/>
+ </comp>
+ <comp lib="0" loc="(440,710)" name="Tunnel">
+ <a name="facing" val="north"/>
+ <a name="label" val="EN_LOAD"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(470,740)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="WE_REG_BANK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(530,770)" name="Tunnel">
+ <a name="facing" val="north"/>
+ <a name="label" val="EN_BL"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ </circuit>
+ <circuit name="CPU_INSTRUCTION_MEMORY">
+ <a name="circuit" val="CPU_INSTRUCTION_MEMORY"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="custom"/>
+ <a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
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+ <wire from="(480,460)" to="(550,460)"/>
+ <wire from="(480,420)" to="(550,420)"/>
+ <wire from="(480,380)" to="(550,380)"/>
+ <comp lib="0" loc="(1040,780)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux1"/>
</comp>
- <comp lib="0" loc="(480,460)" name="Constant">
- <a name="value" val="0xfe00"/>
+ <comp lib="0" loc="(1040,800)" name="Tunnel">
+ <a name="facing" val="east"/>
<a name="width" val="16"/>
+ <a name="label" val="mux3"/>
</comp>
- <comp lib="0" loc="(480,480)" name="Constant">
- <a name="value" val="0x8a32"/>
+ <comp lib="0" loc="(1100,870)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="2"/>
+ <a name="label" val="sel"/>
+ </comp>
+ <comp lib="0" loc="(1160,700)" name="Probe">
+ <a name="radix" val="16"/>
+ </comp>
+ <comp lib="0" loc="(1210,790)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
<a name="width" val="16"/>
+ <a name="label" val="INSTRUCTION"/>
+ </comp>
+ <comp lib="0" loc="(320,540)" name="Pin">
+ <a name="width" val="7"/>
+ <a name="label" val="ADDR_INSTR"/>
+ </comp>
+ <comp lib="0" loc="(340,540)" name="Splitter">
+ <a name="incoming" val="7"/>
+ <a name="appear" val="center"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="0"/>
+ <a name="bit4" val="0"/>
+ <a name="bit5" val="1"/>
+ <a name="bit6" val="1"/>
+ </comp>
+ <comp lib="0" loc="(370,560)" name="Tunnel">
+ <a name="width" val="2"/>
+ <a name="label" val="sel"/>
</comp>
<comp lib="0" loc="(630,350)" name="Tunnel">
- <a name="label" val="mux0"/>
<a name="width" val="16"/>
+ <a name="label" val="mux0"/>
</comp>
<comp lib="0" loc="(630,730)" name="Tunnel">
- <a name="label" val="mux1"/>
<a name="width" val="16"/>
+ <a name="label" val="mux1"/>
</comp>
<comp lib="0" loc="(920,350)" name="Tunnel">
- <a name="label" val="mux2"/>
<a name="width" val="16"/>
+ <a name="label" val="mux2"/>
</comp>
<comp lib="0" loc="(920,730)" name="Tunnel">
- <a name="label" val="mux3"/>
<a name="width" val="16"/>
+ <a name="label" val="mux3"/>
</comp>
<comp lib="0" loc="(990,770)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="mux0"/>
<a name="width" val="16"/>
+ <a name="label" val="mux0"/>
</comp>
<comp lib="0" loc="(990,790)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="mux2"/>
<a name="width" val="16"/>
+ <a name="label" val="mux2"/>
</comp>
<comp lib="2" loc="(1130,790)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="select" val="2"/>
<a name="width" val="16"/>
</comp>
<comp lib="2" loc="(590,350)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="select" val="5"/>
<a name="width" val="16"/>
</comp>
<comp lib="2" loc="(590,730)" name="Multiplexer">
- <a name="enable" val="true"/>
- <a name="select" val="5"/>
<a name="selloc" val="tr"/>
+ <a name="select" val="5"/>
<a name="width" val="16"/>
</comp>
<comp lib="2" loc="(880,350)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="select" val="5"/>
<a name="width" val="16"/>
</comp>
<comp lib="2" loc="(880,730)" name="Multiplexer">
- <a name="enable" val="true"/>
- <a name="select" val="5"/>
<a name="selloc" val="tr"/>
+ <a name="select" val="5"/>
<a name="width" val="16"/>
</comp>
- <wire from="(1040,780)" to="(1090,780)"/>
- <wire from="(1040,800)" to="(1090,800)"/>
- <wire from="(1100,870)" to="(1110,870)"/>
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- <wire from="(1130,790)" to="(1180,790)"/>
- <wire from="(1160,700)" to="(1180,700)"/>
- <wire from="(1180,700)" to="(1180,790)"/>
- <wire from="(1180,790)" to="(1210,790)"/>
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- <wire from="(360,530)" to="(570,530)"/>
- <wire from="(360,540)" to="(360,560)"/>
- <wire from="(360,560)" to="(370,560)"/>
- <wire from="(440,190)" to="(550,190)"/>
- <wire from="(440,210)" to="(550,210)"/>
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- <wire from="(440,270)" to="(550,270)"/>
- <wire from="(440,290)" to="(550,290)"/>
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- <wire from="(440,330)" to="(550,330)"/>
- <wire from="(440,350)" to="(550,350)"/>
- <wire from="(440,370)" to="(550,370)"/>
- <wire from="(440,390)" to="(550,390)"/>
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- <wire from="(440,430)" to="(550,430)"/>
- <wire from="(440,450)" to="(550,450)"/>
- <wire from="(440,470)" to="(550,470)"/>
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- <wire from="(440,610)" to="(550,610)"/>
- <wire from="(440,630)" to="(550,630)"/>
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- <wire from="(440,670)" to="(550,670)"/>
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- <wire from="(440,830)" to="(550,830)"/>
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- <wire from="(440,870)" to="(550,870)"/>
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- <wire from="(480,260)" to="(550,260)"/>
- <wire from="(480,280)" to="(550,280)"/>
- <wire from="(480,300)" to="(550,300)"/>
- <wire from="(480,320)" to="(550,320)"/>
- <wire from="(480,340)" to="(550,340)"/>
- <wire from="(480,360)" to="(550,360)"/>
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- <wire from="(480,400)" to="(550,400)"/>
- <wire from="(480,420)" to="(550,420)"/>
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- <wire from="(480,460)" to="(550,460)"/>
- <wire from="(480,480)" to="(550,480)"/>
- <wire from="(480,500)" to="(550,500)"/>
- <wire from="(480,580)" to="(550,580)"/>
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- <wire from="(480,640)" to="(550,640)"/>
- <wire from="(480,660)" to="(550,660)"/>
- <wire from="(480,680)" to="(550,680)"/>
- <wire from="(480,700)" to="(550,700)"/>
- <wire from="(480,720)" to="(550,720)"/>
- <wire from="(480,740)" to="(550,740)"/>
- <wire from="(480,760)" to="(550,760)"/>
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- <wire from="(480,800)" to="(550,800)"/>
- <wire from="(480,820)" to="(550,820)"/>
- <wire from="(480,840)" to="(550,840)"/>
- <wire from="(480,860)" to="(550,860)"/>
- <wire from="(480,880)" to="(550,880)"/>
- <wire from="(570,510)" to="(570,530)"/>
- <wire from="(570,530)" to="(570,570)"/>
- <wire from="(570,530)" to="(860,530)"/>
- <wire from="(590,350)" to="(630,350)"/>
- <wire from="(590,730)" to="(630,730)"/>
- <wire from="(730,190)" to="(840,190)"/>
- <wire from="(730,210)" to="(840,210)"/>
- <wire from="(730,230)" to="(840,230)"/>
- <wire from="(730,250)" to="(840,250)"/>
- <wire from="(730,270)" to="(840,270)"/>
- <wire from="(730,290)" to="(840,290)"/>
- <wire from="(730,310)" to="(840,310)"/>
- <wire from="(730,330)" to="(840,330)"/>
- <wire from="(730,350)" to="(840,350)"/>
- <wire from="(730,370)" to="(840,370)"/>
- <wire from="(730,390)" to="(840,390)"/>
- <wire from="(730,410)" to="(840,410)"/>
- <wire from="(730,430)" to="(840,430)"/>
- <wire from="(730,450)" to="(840,450)"/>
- <wire from="(730,470)" to="(840,470)"/>
- <wire from="(730,490)" to="(840,490)"/>
- <wire from="(730,570)" to="(840,570)"/>
- <wire from="(730,590)" to="(840,590)"/>
- <wire from="(730,610)" to="(840,610)"/>
- <wire from="(730,630)" to="(840,630)"/>
- <wire from="(730,650)" to="(840,650)"/>
- <wire from="(730,670)" to="(840,670)"/>
- <wire from="(730,690)" to="(840,690)"/>
- <wire from="(730,710)" to="(840,710)"/>
- <wire from="(730,730)" to="(840,730)"/>
- <wire from="(730,750)" to="(840,750)"/>
- <wire from="(730,770)" to="(840,770)"/>
- <wire from="(730,790)" to="(840,790)"/>
- <wire from="(730,810)" to="(840,810)"/>
- <wire from="(730,830)" to="(840,830)"/>
- <wire from="(730,850)" to="(840,850)"/>
- <wire from="(730,870)" to="(840,870)"/>
- <wire from="(770,200)" to="(840,200)"/>
- <wire from="(770,220)" to="(840,220)"/>
- <wire from="(770,240)" to="(840,240)"/>
- <wire from="(770,260)" to="(840,260)"/>
- <wire from="(770,280)" to="(840,280)"/>
- <wire from="(770,300)" to="(840,300)"/>
- <wire from="(770,320)" to="(840,320)"/>
- <wire from="(770,340)" to="(840,340)"/>
- <wire from="(770,360)" to="(840,360)"/>
- <wire from="(770,380)" to="(840,380)"/>
- <wire from="(770,400)" to="(840,400)"/>
- <wire from="(770,420)" to="(840,420)"/>
- <wire from="(770,440)" to="(840,440)"/>
- <wire from="(770,460)" to="(840,460)"/>
- <wire from="(770,480)" to="(840,480)"/>
- <wire from="(770,500)" to="(840,500)"/>
- <wire from="(770,580)" to="(840,580)"/>
- <wire from="(770,600)" to="(840,600)"/>
- <wire from="(770,620)" to="(840,620)"/>
- <wire from="(770,640)" to="(840,640)"/>
- <wire from="(770,660)" to="(840,660)"/>
- <wire from="(770,680)" to="(840,680)"/>
- <wire from="(770,700)" to="(840,700)"/>
- <wire from="(770,720)" to="(840,720)"/>
- <wire from="(770,740)" to="(840,740)"/>
- <wire from="(770,760)" to="(840,760)"/>
- <wire from="(770,780)" to="(840,780)"/>
- <wire from="(770,800)" to="(840,800)"/>
- <wire from="(770,820)" to="(840,820)"/>
- <wire from="(770,840)" to="(840,840)"/>
- <wire from="(770,860)" to="(840,860)"/>
- <wire from="(770,880)" to="(840,880)"/>
- <wire from="(860,510)" to="(860,530)"/>
- <wire from="(860,530)" to="(860,570)"/>
- <wire from="(880,350)" to="(920,350)"/>
- <wire from="(880,730)" to="(920,730)"/>
- <wire from="(990,770)" to="(1090,770)"/>
- <wire from="(990,790)" to="(1090,790)"/>
+ <comp lib="0" loc="(480,300)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee24"/>
+ </comp>
+ <comp lib="0" loc="(440,430)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(480,260)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8461"/>
+ </comp>
+ <comp lib="0" loc="(480,600)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(440,230)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(440,270)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(440,690)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(440,650)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a32"/>
+ </comp>
+ <comp lib="0" loc="(440,310)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8473"/>
+ </comp>
+ <comp lib="0" loc="(480,680)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a00"/>
+ </comp>
+ <comp lib="0" loc="(440,590)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a9c"/>
+ </comp>
+ <comp lib="0" loc="(440,370)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(480,340)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(480,480)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xbfe3"/>
+ </comp>
+ <comp lib="0" loc="(480,360)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8464"/>
+ </comp>
+ <comp lib="0" loc="(440,290)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(440,670)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8800"/>
+ </comp>
+ <comp lib="0" loc="(440,630)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(480,640)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x88ce"/>
+ </comp>
+ <comp lib="0" loc="(480,620)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8ace"/>
+ </comp>
+ <comp lib="0" loc="(440,330)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(440,450)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee2a"/>
+ </comp>
+ <comp lib="0" loc="(480,240)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(440,210)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8477"/>
+ </comp>
+ <comp lib="0" loc="(440,410)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8478"/>
+ </comp>
+ <comp lib="0" loc="(440,390)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(480,280)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(480,320)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(440,470)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xda02"/>
+ </comp>
+ <comp lib="0" loc="(480,440)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(480,460)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xd801"/>
+ </comp>
+ <comp lib="0" loc="(480,200)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xc200"/>
+ </comp>
+ <comp lib="0" loc="(480,400)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee27"/>
+ </comp>
+ <comp lib="0" loc="(480,660)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(440,570)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(440,250)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee1e"/>
+ </comp>
+ <comp lib="0" loc="(440,350)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee21"/>
+ </comp>
+ <comp lib="0" loc="(440,490)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8864"/>
+ </comp>
+ <comp lib="0" loc="(440,190)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8010"/>
+ </comp>
+ <comp lib="0" loc="(480,420)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(440,610)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8832"/>
+ </comp>
+ <comp lib="0" loc="(480,380)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(480,580)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x889c"/>
+ </comp>
+ <comp lib="0" loc="(480,220)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(480,500)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a64"/>
+ </comp>
</circuit>
<circuit name="CPU_REG_BANK">
- <a name="appearance" val="custom"/>
<a name="circuit" val="CPU_REG_BANK"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="custom"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
<appear>
<rect fill="none" height="160" stroke="#000000" stroke-width="2" width="200" x="60" y="50"/>
<rect height="20" stroke="none" width="200" x="60" y="190"/>
@@ -1595,6 +1752,15 @@
<text dominant-baseline="alphabetic" fill="#404040" font-family="Dialog" font-size="12" text-anchor="start" x="65" y="64">ADD_A</text>
<text dominant-baseline="alphabetic" fill="#404040" font-family="Dialog" font-size="12" text-anchor="start" x="65" y="84">ADD_B</text>
<text dominant-baseline="alphabetic" fill="#ffffff" font-family="Dialog" font-size="14" font-weight="bold" text-anchor="middle" x="160" y="204">CPU_REG_BANK</text>
+ <circ-port height="10" pin="1270,400" width="10" x="265" y="55"/>
+ <circ-port height="8" pin="130,230" width="8" x="46" y="176"/>
+ <circ-port height="8" pin="200,150" width="8" x="46" y="116"/>
+ <circ-port height="8" pin="150,130" width="8" x="46" y="96"/>
+ <circ-port height="10" pin="1270,670" width="10" x="265" y="75"/>
+ <circ-port height="8" pin="130,210" width="8" x="46" y="156"/>
+ <circ-port height="8" pin="150,90" width="8" x="46" y="76"/>
+ <circ-port height="8" pin="150,70" width="8" x="46" y="56"/>
+ <circ-port height="8" pin="130,170" width="8" x="46" y="136"/>
<visible-register height="10" path="/Register(690,180)" stroke-width="0" width="13" x="147" y="78"/>
<visible-register height="10" path="/Register(690,310)" stroke-width="0" width="13" x="147" y="88"/>
<visible-register height="10" path="/Register(690,440)" stroke-width="0" width="13" x="147" y="98"/>
@@ -1604,83 +1770,186 @@
<visible-register height="10" path="/Register(690,830)" stroke-width="0" width="13" x="147" y="128"/>
<visible-register height="10" path="/Register(690,960)" stroke-width="0" width="13" x="147" y="138"/>
<circ-anchor facing="east" height="6" width="6" x="267" y="57"/>
- <circ-port height="10" pin="1270,400" width="10" x="265" y="55"/>
- <circ-port height="10" pin="1270,670" width="10" x="265" y="75"/>
- <circ-port height="8" pin="130,170" width="8" x="46" y="136"/>
- <circ-port height="8" pin="130,210" width="8" x="46" y="156"/>
- <circ-port height="8" pin="130,230" width="8" x="46" y="176"/>
- <circ-port height="8" pin="150,130" width="8" x="46" y="96"/>
- <circ-port height="8" pin="150,70" width="8" x="46" y="56"/>
- <circ-port height="8" pin="150,90" width="8" x="46" y="76"/>
- <circ-port height="8" pin="200,150" width="8" x="46" y="116"/>
</appear>
+ <wire from="(720,400)" to="(720,410)"/>
+ <wire from="(720,920)" to="(720,930)"/>
+ <wire from="(670,150)" to="(720,150)"/>
+ <wire from="(670,670)" to="(720,670)"/>
+ <wire from="(1240,470)" to="(1240,560)"/>
+ <wire from="(1250,570)" to="(1250,600)"/>
+ <wire from="(130,170)" to="(230,170)"/>
+ <wire from="(130,210)" to="(230,210)"/>
+ <wire from="(1230,550)" to="(1230,600)"/>
+ <wire from="(540,580)" to="(540,880)"/>
+ <wire from="(670,340)" to="(690,340)"/>
+ <wire from="(670,380)" to="(690,380)"/>
+ <wire from="(670,860)" to="(690,860)"/>
+ <wire from="(670,900)" to="(690,900)"/>
+ <wire from="(1040,560)" to="(1240,560)"/>
+ <wire from="(1050,570)" to="(1250,570)"/>
+ <wire from="(520,540)" to="(550,540)"/>
+ <wire from="(530,590)" to="(530,1010)"/>
+ <wire from="(1220,540)" to="(1220,600)"/>
+ <wire from="(490,610)" to="(500,610)"/>
+ <wire from="(150,130)" to="(230,130)"/>
+ <wire from="(150,90)" to="(230,90)"/>
+ <wire from="(1020,540)" to="(1020,600)"/>
+ <wire from="(1150,450)" to="(1180,450)"/>
+ <wire from="(560,560)" to="(560,620)"/>
+ <wire from="(560,620)" to="(690,620)"/>
+ <wire from="(1020,540)" to="(1220,540)"/>
+ <wire from="(1030,550)" to="(1230,550)"/>
+ <wire from="(1190,470)" to="(1190,510)"/>
+ <wire from="(1240,560)" to="(1240,600)"/>
+ <wire from="(1040,560)" to="(1040,860)"/>
+ <wire from="(550,360)" to="(690,360)"/>
+ <wire from="(550,570)" to="(550,750)"/>
+ <wire from="(520,520)" to="(530,520)"/>
+ <wire from="(720,1050)" to="(720,1060)"/>
+ <wire from="(720,530)" to="(720,540)"/>
+ <wire from="(1200,520)" to="(1200,600)"/>
+ <wire from="(1230,470)" to="(1230,550)"/>
+ <wire from="(670,280)" to="(720,280)"/>
+ <wire from="(670,800)" to="(720,800)"/>
+ <wire from="(1190,510)" to="(1190,600)"/>
+ <wire from="(1180,470)" to="(1180,500)"/>
+ <wire from="(1210,530)" to="(1210,600)"/>
+ <wire from="(1220,670)" to="(1270,670)"/>
+ <wire from="(750,990)" to="(1050,990)"/>
+ <wire from="(200,150)" to="(230,150)"/>
+ <wire from="(540,230)" to="(690,230)"/>
+ <wire from="(1040,210)" to="(1040,510)"/>
+ <wire from="(750,730)" to="(1030,730)"/>
+ <wire from="(540,230)" to="(540,530)"/>
+ <wire from="(670,1030)" to="(690,1030)"/>
+ <wire from="(670,470)" to="(690,470)"/>
+ <wire from="(670,510)" to="(690,510)"/>
+ <wire from="(670,990)" to="(690,990)"/>
+ <wire from="(530,1010)" to="(690,1010)"/>
+ <wire from="(1050,80)" to="(1050,500)"/>
+ <wire from="(1020,470)" to="(1020,530)"/>
+ <wire from="(1150,620)" to="(1180,620)"/>
+ <wire from="(560,490)" to="(560,550)"/>
+ <wire from="(1180,500)" to="(1180,600)"/>
+ <wire from="(1030,340)" to="(1030,520)"/>
+ <wire from="(720,140)" to="(720,150)"/>
+ <wire from="(720,660)" to="(720,670)"/>
+ <wire from="(670,410)" to="(720,410)"/>
+ <wire from="(670,930)" to="(720,930)"/>
+ <wire from="(1220,400)" to="(1220,430)"/>
+ <wire from="(1220,640)" to="(1220,670)"/>
+ <wire from="(500,600)" to="(500,610)"/>
+ <wire from="(520,550)" to="(560,550)"/>
+ <wire from="(1220,470)" to="(1220,540)"/>
+ <wire from="(750,210)" to="(1040,210)"/>
+ <wire from="(1220,400)" to="(1270,400)"/>
+ <wire from="(130,230)" to="(230,230)"/>
+ <wire from="(750,80)" to="(1050,80)"/>
+ <wire from="(540,880)" to="(690,880)"/>
+ <wire from="(750,340)" to="(1030,340)"/>
+ <wire from="(520,530)" to="(540,530)"/>
+ <wire from="(670,120)" to="(690,120)"/>
+ <wire from="(670,600)" to="(690,600)"/>
+ <wire from="(670,640)" to="(690,640)"/>
+ <wire from="(670,80)" to="(690,80)"/>
+ <wire from="(530,100)" to="(690,100)"/>
+ <wire from="(1210,470)" to="(1210,530)"/>
+ <wire from="(150,70)" to="(230,70)"/>
+ <wire from="(1050,570)" to="(1050,990)"/>
+ <wire from="(750,470)" to="(1020,470)"/>
+ <wire from="(1030,550)" to="(1030,730)"/>
+ <wire from="(720,270)" to="(720,280)"/>
+ <wire from="(720,790)" to="(720,800)"/>
+ <wire from="(670,1060)" to="(720,1060)"/>
+ <wire from="(670,540)" to="(720,540)"/>
+ <wire from="(1020,530)" to="(1210,530)"/>
+ <wire from="(520,560)" to="(560,560)"/>
+ <wire from="(750,860)" to="(1040,860)"/>
+ <wire from="(1030,520)" to="(1200,520)"/>
+ <wire from="(1200,470)" to="(1200,520)"/>
+ <wire from="(520,580)" to="(540,580)"/>
+ <wire from="(670,210)" to="(690,210)"/>
+ <wire from="(670,250)" to="(690,250)"/>
+ <wire from="(670,730)" to="(690,730)"/>
+ <wire from="(670,770)" to="(690,770)"/>
+ <wire from="(520,570)" to="(550,570)"/>
+ <wire from="(460,560)" to="(480,560)"/>
+ <wire from="(530,100)" to="(530,520)"/>
+ <wire from="(1050,500)" to="(1180,500)"/>
+ <wire from="(560,490)" to="(690,490)"/>
+ <wire from="(1250,470)" to="(1250,570)"/>
+ <wire from="(750,600)" to="(1020,600)"/>
+ <wire from="(1040,510)" to="(1190,510)"/>
+ <wire from="(550,360)" to="(550,540)"/>
+ <wire from="(550,750)" to="(690,750)"/>
+ <wire from="(520,590)" to="(530,590)"/>
<comp lib="0" loc="(1150,450)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD_A"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(1150,620)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD_B"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(1270,400)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="OUT_A"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="OUT_A"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(1270,670)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="OUT_B"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="OUT_B"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(130,170)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="EN_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(130,210)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(130,230)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="RESET"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(150,130)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="ADD_WR"/>
<a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(150,70)" name="Pin">
+ <a name="label" val="ADD_WR"/>
<a name="appearance" val="NewPins"/>
- <a name="label" val="ADD_A"/>
+ </comp>
+ <comp lib="0" loc="(150,70)" name="Pin">
<a name="width" val="3"/>
+ <a name="label" val="ADD_A"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(150,90)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="ADD_B"/>
<a name="width" val="3"/>
+ <a name="label" val="ADD_B"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(200,150)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="DATA_WR"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(230,130)" name="Tunnel">
+ <a name="width" val="3"/>
<a name="label" val="ADD_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(230,150)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(230,170)" name="Tunnel">
<a name="label" val="EN_WR"/>
@@ -1695,14 +1964,14 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(230,70)" name="Tunnel">
+ <a name="width" val="3"/>
<a name="label" val="ADD_A"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(230,90)" name="Tunnel">
+ <a name="width" val="3"/>
<a name="label" val="ADD_B"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(460,560)" name="Tunnel">
<a name="facing" val="east"/>
@@ -1711,9 +1980,9 @@
</comp>
<comp lib="0" loc="(490,610)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(670,1030)" name="Tunnel">
<a name="facing" val="east"/>
@@ -1737,9 +2006,9 @@
</comp>
<comp lib="0" loc="(670,210)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,250)" name="Tunnel">
<a name="facing" val="east"/>
@@ -1753,273 +2022,196 @@
</comp>
<comp lib="0" loc="(670,340)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(670,380)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,410)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,470)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(670,510)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,540)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,600)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(670,640)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,670)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,730)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(670,770)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,80)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(670,800)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,860)" name="Tunnel">
- <a name="facing" val="east"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
- <comp lib="0" loc="(670,900)" name="Tunnel">
+ <comp lib="0" loc="(670,380)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="CLK"/>
<a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,930)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- </comp>
- <comp lib="0" loc="(670,990)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="2" loc="(1220,430)" name="Multiplexer">
- <a name="facing" val="north"/>
- <a name="select" val="3"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="2" loc="(1220,640)" name="Multiplexer">
- <a name="facing" val="south"/>
- <a name="select" val="3"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="2" loc="(480,560)" name="Demultiplexer">
- <a name="select" val="3"/>
- </comp>
- <comp lib="4" loc="(690,180)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,310)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,440)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,50)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,570)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,700)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,830)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,960)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="6" loc="(1291,630)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="READ B"/>
- </comp>
- <comp lib="6" loc="(1292,456)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="READ A"/>
- </comp>
- <wire from="(1020,470)" to="(1020,530)"/>
- <wire from="(1020,530)" to="(1210,530)"/>
- <wire from="(1020,540)" to="(1020,600)"/>
- <wire from="(1020,540)" to="(1220,540)"/>
- <wire from="(1030,340)" to="(1030,520)"/>
- <wire from="(1030,520)" to="(1200,520)"/>
- <wire from="(1030,550)" to="(1030,730)"/>
- <wire from="(1030,550)" to="(1230,550)"/>
- <wire from="(1040,210)" to="(1040,510)"/>
- <wire from="(1040,510)" to="(1190,510)"/>
- <wire from="(1040,560)" to="(1040,860)"/>
- <wire from="(1040,560)" to="(1240,560)"/>
- <wire from="(1050,500)" to="(1180,500)"/>
- <wire from="(1050,570)" to="(1050,990)"/>
- <wire from="(1050,570)" to="(1250,570)"/>
- <wire from="(1050,80)" to="(1050,500)"/>
- <wire from="(1150,450)" to="(1180,450)"/>
- <wire from="(1150,620)" to="(1180,620)"/>
- <wire from="(1180,470)" to="(1180,500)"/>
- <wire from="(1180,500)" to="(1180,600)"/>
- <wire from="(1190,470)" to="(1190,510)"/>
- <wire from="(1190,510)" to="(1190,600)"/>
- <wire from="(1200,470)" to="(1200,520)"/>
- <wire from="(1200,520)" to="(1200,600)"/>
- <wire from="(1210,470)" to="(1210,530)"/>
- <wire from="(1210,530)" to="(1210,600)"/>
- <wire from="(1220,400)" to="(1220,430)"/>
- <wire from="(1220,400)" to="(1270,400)"/>
- <wire from="(1220,470)" to="(1220,540)"/>
- <wire from="(1220,540)" to="(1220,600)"/>
- <wire from="(1220,640)" to="(1220,670)"/>
- <wire from="(1220,670)" to="(1270,670)"/>
- <wire from="(1230,470)" to="(1230,550)"/>
- <wire from="(1230,550)" to="(1230,600)"/>
- <wire from="(1240,470)" to="(1240,560)"/>
- <wire from="(1240,560)" to="(1240,600)"/>
- <wire from="(1250,470)" to="(1250,570)"/>
- <wire from="(1250,570)" to="(1250,600)"/>
- <wire from="(130,170)" to="(230,170)"/>
- <wire from="(130,210)" to="(230,210)"/>
- <wire from="(130,230)" to="(230,230)"/>
- <wire from="(150,130)" to="(230,130)"/>
- <wire from="(150,70)" to="(230,70)"/>
- <wire from="(150,90)" to="(230,90)"/>
- <wire from="(200,150)" to="(230,150)"/>
- <wire from="(460,560)" to="(480,560)"/>
- <wire from="(490,610)" to="(500,610)"/>
- <wire from="(500,600)" to="(500,610)"/>
- <wire from="(520,520)" to="(530,520)"/>
- <wire from="(520,530)" to="(540,530)"/>
- <wire from="(520,540)" to="(550,540)"/>
- <wire from="(520,550)" to="(560,550)"/>
- <wire from="(520,560)" to="(560,560)"/>
- <wire from="(520,570)" to="(550,570)"/>
- <wire from="(520,580)" to="(540,580)"/>
- <wire from="(520,590)" to="(530,590)"/>
- <wire from="(530,100)" to="(530,520)"/>
- <wire from="(530,100)" to="(690,100)"/>
- <wire from="(530,1010)" to="(690,1010)"/>
- <wire from="(530,590)" to="(530,1010)"/>
- <wire from="(540,230)" to="(540,530)"/>
- <wire from="(540,230)" to="(690,230)"/>
- <wire from="(540,580)" to="(540,880)"/>
- <wire from="(540,880)" to="(690,880)"/>
- <wire from="(550,360)" to="(550,540)"/>
- <wire from="(550,360)" to="(690,360)"/>
- <wire from="(550,570)" to="(550,750)"/>
- <wire from="(550,750)" to="(690,750)"/>
- <wire from="(560,490)" to="(560,550)"/>
- <wire from="(560,490)" to="(690,490)"/>
- <wire from="(560,560)" to="(560,620)"/>
- <wire from="(560,620)" to="(690,620)"/>
- <wire from="(670,1030)" to="(690,1030)"/>
- <wire from="(670,1060)" to="(720,1060)"/>
- <wire from="(670,120)" to="(690,120)"/>
- <wire from="(670,150)" to="(720,150)"/>
- <wire from="(670,210)" to="(690,210)"/>
- <wire from="(670,250)" to="(690,250)"/>
- <wire from="(670,280)" to="(720,280)"/>
- <wire from="(670,340)" to="(690,340)"/>
- <wire from="(670,380)" to="(690,380)"/>
- <wire from="(670,410)" to="(720,410)"/>
- <wire from="(670,470)" to="(690,470)"/>
- <wire from="(670,510)" to="(690,510)"/>
- <wire from="(670,540)" to="(720,540)"/>
- <wire from="(670,600)" to="(690,600)"/>
- <wire from="(670,640)" to="(690,640)"/>
- <wire from="(670,670)" to="(720,670)"/>
- <wire from="(670,730)" to="(690,730)"/>
- <wire from="(670,770)" to="(690,770)"/>
- <wire from="(670,80)" to="(690,80)"/>
- <wire from="(670,800)" to="(720,800)"/>
- <wire from="(670,860)" to="(690,860)"/>
- <wire from="(670,900)" to="(690,900)"/>
- <wire from="(670,930)" to="(720,930)"/>
- <wire from="(670,990)" to="(690,990)"/>
- <wire from="(720,1050)" to="(720,1060)"/>
- <wire from="(720,140)" to="(720,150)"/>
- <wire from="(720,270)" to="(720,280)"/>
- <wire from="(720,400)" to="(720,410)"/>
- <wire from="(720,530)" to="(720,540)"/>
- <wire from="(720,660)" to="(720,670)"/>
- <wire from="(720,790)" to="(720,800)"/>
- <wire from="(720,920)" to="(720,930)"/>
- <wire from="(750,210)" to="(1040,210)"/>
- <wire from="(750,340)" to="(1030,340)"/>
- <wire from="(750,470)" to="(1020,470)"/>
- <wire from="(750,600)" to="(1020,600)"/>
- <wire from="(750,730)" to="(1030,730)"/>
- <wire from="(750,80)" to="(1050,80)"/>
- <wire from="(750,860)" to="(1040,860)"/>
- <wire from="(750,990)" to="(1050,990)"/>
+ </comp>
+ <comp lib="0" loc="(670,410)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,470)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,510)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,540)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,600)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,640)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,670)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,730)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,770)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,80)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,800)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,860)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,900)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,930)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(670,990)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="2" loc="(1220,430)" name="Multiplexer">
+ <a name="facing" val="north"/>
+ <a name="select" val="3"/>
+ <a name="width" val="8"/>
+ </comp>
+ <comp lib="2" loc="(1220,640)" name="Multiplexer">
+ <a name="facing" val="south"/>
+ <a name="select" val="3"/>
+ <a name="width" val="8"/>
+ </comp>
+ <comp lib="2" loc="(480,560)" name="Demultiplexer">
+ <a name="select" val="3"/>
+ </comp>
+ <comp lib="4" loc="(690,180)" name="Register"/>
+ <comp lib="4" loc="(690,310)" name="Register"/>
+ <comp lib="4" loc="(690,440)" name="Register"/>
+ <comp lib="4" loc="(690,50)" name="Register"/>
+ <comp lib="4" loc="(690,570)" name="Register"/>
+ <comp lib="4" loc="(690,700)" name="Register"/>
+ <comp lib="4" loc="(690,830)" name="Register"/>
+ <comp lib="4" loc="(690,960)" name="Register"/>
+ <comp lib="6" loc="(1291,630)" name="Text">
+ <a name="text" val="READ B"/>
+ <a name="font" val="SansSerif plain 12"/>
+ </comp>
+ <comp lib="6" loc="(1292,456)" name="Text">
+ <a name="text" val="READ A"/>
+ <a name="font" val="SansSerif plain 12"/>
+ </comp>
</circuit>
<circuit name="ALU_ADD_SOUS">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="ALU_ADD_SOUS"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(550,280)" to="(550,420)"/>
+ <wire from="(680,430)" to="(730,430)"/>
+ <wire from="(690,480)" to="(740,480)"/>
+ <wire from="(520,340)" to="(570,340)"/>
+ <wire from="(550,280)" to="(600,280)"/>
+ <wire from="(680,310)" to="(870,310)"/>
+ <wire from="(570,340)" to="(570,410)"/>
+ <wire from="(680,490)" to="(740,490)"/>
+ <wire from="(680,310)" to="(680,400)"/>
+ <wire from="(380,330)" to="(380,350)"/>
+ <wire from="(690,420)" to="(730,420)"/>
+ <wire from="(700,410)" to="(740,410)"/>
+ <wire from="(640,360)" to="(870,360)"/>
+ <wire from="(770,420)" to="(810,420)"/>
+ <wire from="(770,480)" to="(810,480)"/>
+ <wire from="(590,420)" to="(690,420)"/>
+ <wire from="(380,330)" to="(490,330)"/>
+ <wire from="(640,330)" to="(640,360)"/>
+ <wire from="(810,420)" to="(810,440)"/>
+ <wire from="(810,460)" to="(810,480)"/>
+ <wire from="(570,430)" to="(680,430)"/>
+ <wire from="(380,350)" to="(420,350)"/>
+ <wire from="(500,230)" to="(500,320)"/>
+ <wire from="(600,280)" to="(600,300)"/>
+ <wire from="(600,320)" to="(600,340)"/>
+ <wire from="(450,350)" to="(490,350)"/>
+ <wire from="(810,440)" to="(830,440)"/>
+ <wire from="(810,460)" to="(830,460)"/>
+ <wire from="(600,300)" to="(620,300)"/>
+ <wire from="(600,320)" to="(620,320)"/>
+ <wire from="(660,310)" to="(680,310)"/>
+ <wire from="(350,350)" to="(380,350)"/>
+ <wire from="(700,470)" to="(730,470)"/>
+ <wire from="(570,340)" to="(600,340)"/>
+ <wire from="(350,230)" to="(500,230)"/>
+ <wire from="(500,230)" to="(640,230)"/>
+ <wire from="(640,230)" to="(640,290)"/>
+ <wire from="(680,430)" to="(680,490)"/>
+ <wire from="(690,420)" to="(690,480)"/>
+ <wire from="(700,410)" to="(700,470)"/>
+ <wire from="(860,450)" to="(870,450)"/>
+ <wire from="(350,280)" to="(550,280)"/>
+ <wire from="(730,420)" to="(740,420)"/>
+ <wire from="(730,430)" to="(740,430)"/>
+ <wire from="(730,470)" to="(740,470)"/>
<comp lib="0" loc="(350,230)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="OP_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(350,280)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="A_in"/>
<a name="width" val="8"/>
+ <a name="label" val="A_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(350,350)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="B_in"/>
<a name="width" val="8"/>
+ <a name="label" val="B_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(550,420)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="8"/>
<a name="appear" val="right"/>
<a name="bit0" val="none"/>
<a name="bit1" val="none"/>
@@ -2029,10 +2221,10 @@
<a name="bit5" val="none"/>
<a name="bit6" val="none"/>
<a name="bit7" val="0"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(570,410)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="8"/>
<a name="appear" val="right"/>
<a name="bit0" val="none"/>
<a name="bit1" val="none"/>
@@ -2042,10 +2234,10 @@
<a name="bit5" val="none"/>
<a name="bit6" val="none"/>
<a name="bit7" val="0"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(680,400)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="8"/>
<a name="appear" val="right"/>
<a name="bit0" val="none"/>
<a name="bit1" val="none"/>
@@ -2055,115 +2247,107 @@
<a name="bit5" val="none"/>
<a name="bit6" val="none"/>
<a name="bit7" val="0"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(870,310)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="R_out"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="R_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(870,360)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="C_out"/>
<a name="output" val="true"/>
+ <a name="label" val="C_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(870,450)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="V_out"/>
<a name="output" val="true"/>
+ <a name="label" val="V_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="1" loc="(450,350)" name="NOT Gate">
<a name="width" val="8"/>
</comp>
<comp lib="1" loc="(770,420)" name="AND Gate">
+ <a name="size" val="30"/>
<a name="inputs" val="3"/>
<a name="negate1" val="true"/>
<a name="negate2" val="true"/>
- <a name="size" val="30"/>
</comp>
<comp lib="1" loc="(770,480)" name="AND Gate">
+ <a name="size" val="30"/>
<a name="inputs" val="3"/>
<a name="negate0" val="true"/>
- <a name="size" val="30"/>
</comp>
<comp lib="1" loc="(860,450)" name="OR Gate">
<a name="size" val="30"/>
</comp>
<comp lib="2" loc="(520,340)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="selloc" val="tr"/>
<a name="width" val="8"/>
</comp>
<comp lib="3" loc="(660,310)" name="Adder"/>
- <wire from="(350,230)" to="(500,230)"/>
- <wire from="(350,280)" to="(550,280)"/>
- <wire from="(350,350)" to="(380,350)"/>
- <wire from="(380,330)" to="(380,350)"/>
- <wire from="(380,330)" to="(490,330)"/>
- <wire from="(380,350)" to="(420,350)"/>
- <wire from="(450,350)" to="(490,350)"/>
- <wire from="(500,230)" to="(500,320)"/>
- <wire from="(500,230)" to="(640,230)"/>
- <wire from="(520,340)" to="(570,340)"/>
- <wire from="(550,280)" to="(550,420)"/>
- <wire from="(550,280)" to="(600,280)"/>
- <wire from="(570,340)" to="(570,410)"/>
- <wire from="(570,340)" to="(600,340)"/>
- <wire from="(570,430)" to="(680,430)"/>
- <wire from="(590,420)" to="(690,420)"/>
- <wire from="(600,280)" to="(600,300)"/>
- <wire from="(600,300)" to="(620,300)"/>
- <wire from="(600,320)" to="(600,340)"/>
- <wire from="(600,320)" to="(620,320)"/>
- <wire from="(640,230)" to="(640,290)"/>
- <wire from="(640,330)" to="(640,360)"/>
- <wire from="(640,360)" to="(870,360)"/>
- <wire from="(660,310)" to="(680,310)"/>
- <wire from="(680,310)" to="(680,400)"/>
- <wire from="(680,310)" to="(870,310)"/>
- <wire from="(680,430)" to="(680,490)"/>
- <wire from="(680,430)" to="(730,430)"/>
- <wire from="(680,490)" to="(740,490)"/>
- <wire from="(690,420)" to="(690,480)"/>
- <wire from="(690,420)" to="(730,420)"/>
- <wire from="(690,480)" to="(740,480)"/>
- <wire from="(700,410)" to="(700,470)"/>
- <wire from="(700,410)" to="(740,410)"/>
- <wire from="(700,470)" to="(730,470)"/>
- <wire from="(730,420)" to="(740,420)"/>
- <wire from="(730,430)" to="(740,430)"/>
- <wire from="(730,470)" to="(740,470)"/>
- <wire from="(770,420)" to="(810,420)"/>
- <wire from="(770,480)" to="(810,480)"/>
- <wire from="(810,420)" to="(810,440)"/>
- <wire from="(810,440)" to="(830,440)"/>
- <wire from="(810,460)" to="(810,480)"/>
- <wire from="(810,460)" to="(830,460)"/>
- <wire from="(860,450)" to="(870,450)"/>
</circuit>
<circuit name="ALU_SHIFT">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="ALU_SHIFT"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(180,370)" to="(180,380)"/>
+ <wire from="(220,340)" to="(220,350)"/>
+ <wire from="(200,340)" to="(200,350)"/>
+ <wire from="(210,340)" to="(210,350)"/>
+ <wire from="(220,240)" to="(220,250)"/>
+ <wire from="(230,240)" to="(230,250)"/>
+ <wire from="(230,340)" to="(230,350)"/>
+ <wire from="(240,240)" to="(240,250)"/>
+ <wire from="(240,340)" to="(240,350)"/>
+ <wire from="(250,240)" to="(250,250)"/>
+ <wire from="(250,340)" to="(250,350)"/>
+ <wire from="(330,240)" to="(330,380)"/>
+ <wire from="(260,240)" to="(260,250)"/>
+ <wire from="(260,340)" to="(260,350)"/>
+ <wire from="(270,240)" to="(270,250)"/>
+ <wire from="(270,340)" to="(270,350)"/>
+ <wire from="(280,240)" to="(280,250)"/>
+ <wire from="(490,190)" to="(490,210)"/>
+ <wire from="(380,190)" to="(490,190)"/>
+ <wire from="(300,320)" to="(300,350)"/>
+ <wire from="(160,220)" to="(190,220)"/>
+ <wire from="(380,190)" to="(380,290)"/>
+ <wire from="(210,300)" to="(370,300)"/>
+ <wire from="(320,220)" to="(480,220)"/>
+ <wire from="(160,190)" to="(380,190)"/>
+ <wire from="(190,220)" to="(190,320)"/>
+ <wire from="(270,350)" to="(300,350)"/>
+ <wire from="(180,380)" to="(330,380)"/>
+ <wire from="(300,270)" to="(320,270)"/>
+ <wire from="(510,230)" to="(530,230)"/>
+ <wire from="(330,240)" to="(480,240)"/>
+ <wire from="(190,220)" to="(200,220)"/>
+ <wire from="(320,220)" to="(320,270)"/>
+ <wire from="(400,310)" to="(530,310)"/>
+ <wire from="(300,320)" to="(370,320)"/>
+ <wire from="(210,240)" to="(210,300)"/>
<comp lib="0" loc="(160,190)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="dir"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(160,220)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="A_in"/>
<a name="width" val="8"/>
+ <a name="label" val="A_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(180,370)" name="Splitter">
- <a name="appear" val="right"/>
<a name="facing" val="north"/>
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
+ <a name="appear" val="right"/>
</comp>
<comp lib="0" loc="(190,320)" name="Splitter">
<a name="facing" val="south"/>
@@ -2187,80 +2371,60 @@
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(530,230)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="R_out"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="R_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(530,310)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="C_out"/>
<a name="output" val="true"/>
+ <a name="label" val="C_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="2" loc="(400,310)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="selloc" val="tr"/>
</comp>
<comp lib="2" loc="(510,230)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="selloc" val="tr"/>
<a name="width" val="8"/>
</comp>
<comp lib="6" loc="(286,127)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="0 - left"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
<comp lib="6" loc="(290,146)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="1 - right"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <wire from="(160,190)" to="(380,190)"/>
- <wire from="(160,220)" to="(190,220)"/>
- <wire from="(180,370)" to="(180,380)"/>
- <wire from="(180,380)" to="(330,380)"/>
- <wire from="(190,220)" to="(190,320)"/>
- <wire from="(190,220)" to="(200,220)"/>
- <wire from="(200,340)" to="(200,350)"/>
- <wire from="(210,240)" to="(210,300)"/>
- <wire from="(210,300)" to="(370,300)"/>
- <wire from="(210,340)" to="(210,350)"/>
+ </circuit>
+ <circuit name="ALU_SHIFT_SIGNED">
+ <a name="circuit" val="ALU_SHIFT_SIGNED"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
+ <a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
<wire from="(220,240)" to="(220,250)"/>
- <wire from="(220,340)" to="(220,350)"/>
<wire from="(230,240)" to="(230,250)"/>
- <wire from="(230,340)" to="(230,350)"/>
<wire from="(240,240)" to="(240,250)"/>
- <wire from="(240,340)" to="(240,350)"/>
<wire from="(250,240)" to="(250,250)"/>
- <wire from="(250,340)" to="(250,350)"/>
+ <wire from="(290,250)" to="(340,250)"/>
+ <wire from="(160,220)" to="(210,220)"/>
<wire from="(260,240)" to="(260,250)"/>
- <wire from="(260,340)" to="(260,350)"/>
<wire from="(270,240)" to="(270,250)"/>
- <wire from="(270,340)" to="(270,350)"/>
- <wire from="(270,350)" to="(300,350)"/>
<wire from="(280,240)" to="(280,250)"/>
- <wire from="(300,270)" to="(320,270)"/>
- <wire from="(300,320)" to="(300,350)"/>
- <wire from="(300,320)" to="(370,320)"/>
- <wire from="(320,220)" to="(320,270)"/>
- <wire from="(320,220)" to="(480,220)"/>
- <wire from="(330,240)" to="(330,380)"/>
- <wire from="(330,240)" to="(480,240)"/>
- <wire from="(380,190)" to="(380,290)"/>
- <wire from="(380,190)" to="(490,190)"/>
- <wire from="(400,310)" to="(530,310)"/>
- <wire from="(490,190)" to="(490,210)"/>
- <wire from="(510,230)" to="(530,230)"/>
- </circuit>
- <circuit name="ALU_SHIFT_SIGNED">
- <a name="appearance" val="logisim_evolution"/>
- <a name="circuit" val="ALU_SHIFT_SIGNED"/>
- <a name="circuitnamedboxfixedsize" val="true"/>
+ <wire from="(290,240)" to="(290,250)"/>
+ <wire from="(340,310)" to="(480,310)"/>
+ <wire from="(210,250)" to="(220,250)"/>
+ <wire from="(340,250)" to="(340,310)"/>
+ <wire from="(290,270)" to="(490,270)"/>
<comp lib="0" loc="(160,220)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="A_in"/>
<a name="width" val="8"/>
+ <a name="label" val="A_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(210,220)" name="Splitter">
<a name="facing" val="south"/>
@@ -2273,319 +2437,324 @@
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(480,310)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="C_out"/>
<a name="output" val="true"/>
+ <a name="label" val="C_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(490,270)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="R_out"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="R_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <wire from="(160,220)" to="(210,220)"/>
- <wire from="(210,250)" to="(220,250)"/>
- <wire from="(220,240)" to="(220,250)"/>
- <wire from="(230,240)" to="(230,250)"/>
- <wire from="(240,240)" to="(240,250)"/>
- <wire from="(250,240)" to="(250,250)"/>
- <wire from="(260,240)" to="(260,250)"/>
- <wire from="(270,240)" to="(270,250)"/>
- <wire from="(280,240)" to="(280,250)"/>
- <wire from="(290,240)" to="(290,250)"/>
- <wire from="(290,250)" to="(340,250)"/>
- <wire from="(290,270)" to="(490,270)"/>
- <wire from="(340,250)" to="(340,310)"/>
- <wire from="(340,310)" to="(480,310)"/>
</circuit>
<circuit name="ALU_AND">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="ALU_AND"/>
- <a name="circuitnamedboxfixedsize" val="true"/>
- <comp lib="0" loc="(180,260)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="A_in"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(180,280)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="B_in"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(350,270)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="R_out"/>
- <a name="output" val="true"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="1" loc="(300,270)" name="AND Gate">
- <a name="size" val="30"/>
- <a name="width" val="8"/>
- </comp>
- <wire from="(180,260)" to="(270,260)"/>
- <wire from="(180,280)" to="(270,280)"/>
- <wire from="(300,270)" to="(350,270)"/>
- </circuit>
- <circuit name="ALU_OR">
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
<a name="appearance" val="logisim_evolution"/>
- <a name="circuit" val="ALU_OR"/>
<a name="circuitnamedboxfixedsize" val="true"/>
- <comp lib="0" loc="(180,260)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="A_in"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(180,280)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="B_in"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(350,270)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="R_out"/>
- <a name="output" val="true"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="1" loc="(300,270)" name="OR Gate">
- <a name="size" val="30"/>
- <a name="width" val="8"/>
- </comp>
+ <a name="circuitvhdlpath" val=""/>
<wire from="(180,260)" to="(270,260)"/>
<wire from="(180,280)" to="(270,280)"/>
<wire from="(300,270)" to="(350,270)"/>
- </circuit>
- <circuit name="ALU_NOT">
- <a name="appearance" val="logisim_evolution"/>
- <a name="circuit" val="ALU_NOT"/>
- <a name="circuitnamedboxfixedsize" val="true"/>
<comp lib="0" loc="(180,260)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="A_in"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(350,260)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="R_out"/>
- <a name="output" val="true"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="1" loc="(300,260)" name="NOT Gate">
- <a name="width" val="8"/>
- </comp>
- <wire from="(180,260)" to="(270,260)"/>
- <wire from="(300,260)" to="(350,260)"/>
- </circuit>
- <circuit name="ALU">
- <a name="appearance" val="logisim_evolution"/>
- <a name="circuit" val="ALU"/>
- <a name="circuitnamedboxfixedsize" val="true"/>
- <a name="simulationFrequency" val="1.0"/>
- <comp lib="0" loc="(110,150)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- <a name="label" val="B_in"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1220,420)" name="Splitter">
- <a name="appear" val="right"/>
- <a name="bit0" val="none"/>
- <a name="bit1" val="none"/>
- <a name="bit2" val="none"/>
- <a name="bit3" val="none"/>
- <a name="bit4" val="none"/>
- <a name="bit5" val="none"/>
- <a name="bit6" val="none"/>
- <a name="bit7" val="0"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="8"/>
- </comp>
- <comp lib="0" loc="(1240,360)" name="Constant">
- <a name="value" val="0x0"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1260,270)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="R"/>
- <a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="A_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(1260,430)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="N"/>
- <a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1260,490)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="C"/>
- <a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1260,560)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="V"/>
- <a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1410,350)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="Z"/>
- <a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(170,150)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- <a name="label" val="OP_in"/>
- <a name="width" val="3"/>
- </comp>
- <comp lib="0" loc="(370,210)" name="Splitter">
- <a name="bit1" val="none"/>
- <a name="bit2" val="none"/>
- <a name="facing" val="south"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="3"/>
- </comp>
- <comp lib="0" loc="(370,310)" name="Splitter">
- <a name="bit1" val="none"/>
- <a name="bit2" val="none"/>
- <a name="facing" val="south"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="3"/>
- </comp>
- <comp lib="0" loc="(50,150)" name="Pin">
+ <comp lib="0" loc="(180,280)" name="Pin">
+ <a name="width" val="8"/>
+ <a name="label" val="B_in"/>
<a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- <a name="label" val="A_in"/>
+ </comp>
+ <comp lib="0" loc="(350,270)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="R_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(960,530)" name="Ground"/>
- <comp lib="2" loc="(1020,490)" name="Multiplexer">
- <a name="select" val="3"/>
- <a name="selloc" val="tr"/>
+ <comp lib="1" loc="(300,270)" name="AND Gate">
+ <a name="width" val="8"/>
+ <a name="size" val="30"/>
</comp>
- <comp lib="2" loc="(990,270)" name="Multiplexer">
- <a name="select" val="3"/>
- <a name="selloc" val="tr"/>
+ </circuit>
+ <circuit name="ALU_OR">
+ <a name="circuit" val="ALU_OR"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
+ <a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(180,260)" to="(270,260)"/>
+ <wire from="(180,280)" to="(270,280)"/>
+ <wire from="(300,270)" to="(350,270)"/>
+ <comp lib="0" loc="(180,260)" name="Pin">
<a name="width" val="8"/>
+ <a name="label" val="A_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="3" loc="(1310,350)" name="Comparator"/>
- <comp loc="(630,230)" name="ALU_ADD_SOUS">
- <a name="label" val="ALU_ADDER"/>
+ <comp lib="0" loc="(180,280)" name="Pin">
+ <a name="width" val="8"/>
+ <a name="label" val="B_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp loc="(630,330)" name="ALU_SHIFT">
- <a name="label" val="ALU_SH"/>
+ <comp lib="0" loc="(350,270)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="8"/>
+ <a name="label" val="R_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp loc="(630,410)" name="ALU_SHIFT_SIGNED">
- <a name="label" val="ALU_SH_SIGNED"/>
+ <comp lib="1" loc="(300,270)" name="OR Gate">
+ <a name="width" val="8"/>
+ <a name="size" val="30"/>
</comp>
- <comp loc="(630,490)" name="ALU_AND">
- <a name="label" val="ALU_ET"/>
+ </circuit>
+ <circuit name="ALU_NOT">
+ <a name="circuit" val="ALU_NOT"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
+ <a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(180,260)" to="(270,260)"/>
+ <wire from="(300,260)" to="(350,260)"/>
+ <comp lib="0" loc="(180,260)" name="Pin">
+ <a name="width" val="8"/>
+ <a name="label" val="A_in"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp loc="(630,570)" name="ALU_OR">
- <a name="label" val="ALU_OU"/>
+ <comp lib="0" loc="(350,260)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="8"/>
+ <a name="label" val="R_out"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp loc="(630,650)" name="ALU_NOT">
- <a name="label" val="ALU_NON"/>
+ <comp lib="1" loc="(300,260)" name="NOT Gate">
+ <a name="width" val="8"/>
</comp>
- <wire from="(1000,170)" to="(1000,450)"/>
- <wire from="(1020,490)" to="(1260,490)"/>
- <wire from="(1030,270)" to="(1030,340)"/>
- <wire from="(1030,270)" to="(1260,270)"/>
- <wire from="(1030,340)" to="(1030,400)"/>
- <wire from="(1030,340)" to="(1270,340)"/>
- <wire from="(1030,400)" to="(1220,400)"/>
- <wire from="(110,150)" to="(110,270)"/>
- <wire from="(110,270)" to="(110,510)"/>
- <wire from="(110,270)" to="(410,270)"/>
- <wire from="(110,510)" to="(110,590)"/>
- <wire from="(110,510)" to="(410,510)"/>
- <wire from="(110,590)" to="(410,590)"/>
+ </circuit>
+ <circuit name="ALU">
+ <a name="circuit" val="ALU"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
+ <a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(660,460)" to="(970,460)"/>
+ <wire from="(830,250)" to="(950,250)"/>
+ <wire from="(960,500)" to="(960,510)"/>
+ <wire from="(830,230)" to="(950,230)"/>
+ <wire from="(940,480)" to="(940,490)"/>
+ <wire from="(960,520)" to="(960,530)"/>
+ <wire from="(970,450)" to="(970,460)"/>
+ <wire from="(970,470)" to="(970,480)"/>
<wire from="(1220,400)" to="(1220,420)"/>
- <wire from="(1240,360)" to="(1270,360)"/>
- <wire from="(1240,430)" to="(1260,430)"/>
+ <wire from="(830,230)" to="(830,240)"/>
+ <wire from="(830,250)" to="(830,260)"/>
+ <wire from="(630,270)" to="(680,270)"/>
<wire from="(1310,350)" to="(1410,350)"/>
+ <wire from="(830,260)" to="(830,330)"/>
+ <wire from="(870,300)" to="(870,650)"/>
<wire from="(170,150)" to="(170,170)"/>
- <wire from="(170,170)" to="(170,210)"/>
- <wire from="(170,170)" to="(970,170)"/>
- <wire from="(170,210)" to="(170,310)"/>
- <wire from="(170,210)" to="(370,210)"/>
- <wire from="(170,310)" to="(370,310)"/>
- <wire from="(380,230)" to="(410,230)"/>
- <wire from="(380,330)" to="(410,330)"/>
- <wire from="(50,150)" to="(50,250)"/>
+ <wire from="(940,490)" to="(980,490)"/>
+ <wire from="(660,250)" to="(660,460)"/>
<wire from="(50,250)" to="(410,250)"/>
- <wire from="(50,250)" to="(50,350)"/>
<wire from="(50,350)" to="(410,350)"/>
- <wire from="(50,350)" to="(50,410)"/>
<wire from="(50,410)" to="(410,410)"/>
- <wire from="(50,410)" to="(50,490)"/>
<wire from="(50,490)" to="(410,490)"/>
- <wire from="(50,490)" to="(50,570)"/>
<wire from="(50,570)" to="(410,570)"/>
- <wire from="(50,570)" to="(50,650)"/>
<wire from="(50,650)" to="(410,650)"/>
- <wire from="(630,230)" to="(830,230)"/>
+ <wire from="(630,650)" to="(870,650)"/>
+ <wire from="(840,270)" to="(950,270)"/>
+ <wire from="(850,280)" to="(850,490)"/>
+ <wire from="(960,510)" to="(980,510)"/>
+ <wire from="(170,170)" to="(170,210)"/>
<wire from="(630,250)" to="(660,250)"/>
- <wire from="(630,270)" to="(680,270)"/>
- <wire from="(630,330)" to="(830,330)"/>
- <wire from="(630,350)" to="(650,350)"/>
- <wire from="(630,410)" to="(840,410)"/>
- <wire from="(630,430)" to="(640,430)"/>
+ <wire from="(860,290)" to="(950,290)"/>
+ <wire from="(970,170)" to="(1000,170)"/>
<wire from="(630,490)" to="(850,490)"/>
- <wire from="(630,570)" to="(860,570)"/>
- <wire from="(630,650)" to="(870,650)"/>
- <wire from="(640,430)" to="(640,480)"/>
- <wire from="(640,480)" to="(940,480)"/>
- <wire from="(650,350)" to="(650,470)"/>
- <wire from="(650,470)" to="(970,470)"/>
- <wire from="(660,250)" to="(660,460)"/>
- <wire from="(660,460)" to="(970,460)"/>
- <wire from="(680,270)" to="(680,560)"/>
+ <wire from="(1240,360)" to="(1270,360)"/>
+ <wire from="(630,230)" to="(830,230)"/>
+ <wire from="(630,330)" to="(830,330)"/>
+ <wire from="(970,170)" to="(970,230)"/>
<wire from="(680,560)" to="(1260,560)"/>
- <wire from="(830,230)" to="(830,240)"/>
- <wire from="(830,230)" to="(950,230)"/>
+ <wire from="(970,450)" to="(980,450)"/>
+ <wire from="(970,470)" to="(980,470)"/>
+ <wire from="(170,210)" to="(370,210)"/>
+ <wire from="(170,310)" to="(370,310)"/>
+ <wire from="(50,350)" to="(50,410)"/>
+ <wire from="(1240,430)" to="(1260,430)"/>
+ <wire from="(630,430)" to="(640,430)"/>
+ <wire from="(840,270)" to="(840,410)"/>
+ <wire from="(960,510)" to="(960,520)"/>
<wire from="(830,240)" to="(950,240)"/>
- <wire from="(830,250)" to="(830,260)"/>
- <wire from="(830,250)" to="(950,250)"/>
- <wire from="(830,260)" to="(830,330)"/>
<wire from="(830,260)" to="(950,260)"/>
- <wire from="(840,270)" to="(840,410)"/>
- <wire from="(840,270)" to="(950,270)"/>
- <wire from="(850,280)" to="(850,490)"/>
+ <wire from="(1030,270)" to="(1030,340)"/>
+ <wire from="(650,470)" to="(970,470)"/>
+ <wire from="(1030,400)" to="(1220,400)"/>
+ <wire from="(50,410)" to="(50,490)"/>
+ <wire from="(50,490)" to="(50,570)"/>
+ <wire from="(110,510)" to="(110,590)"/>
+ <wire from="(50,570)" to="(50,650)"/>
<wire from="(850,280)" to="(950,280)"/>
+ <wire from="(630,570)" to="(860,570)"/>
+ <wire from="(1030,270)" to="(1260,270)"/>
+ <wire from="(110,270)" to="(410,270)"/>
<wire from="(860,290)" to="(860,570)"/>
- <wire from="(860,290)" to="(950,290)"/>
- <wire from="(870,300)" to="(870,650)"/>
- <wire from="(870,300)" to="(950,300)"/>
- <wire from="(940,480)" to="(940,490)"/>
- <wire from="(940,490)" to="(980,490)"/>
- <wire from="(960,500)" to="(960,510)"/>
+ <wire from="(110,510)" to="(410,510)"/>
+ <wire from="(110,590)" to="(410,590)"/>
+ <wire from="(1000,170)" to="(1000,450)"/>
+ <wire from="(990,270)" to="(1030,270)"/>
+ <wire from="(640,480)" to="(940,480)"/>
+ <wire from="(1020,490)" to="(1260,490)"/>
+ <wire from="(1030,340)" to="(1270,340)"/>
<wire from="(960,500)" to="(980,500)"/>
- <wire from="(960,510)" to="(960,520)"/>
- <wire from="(960,510)" to="(980,510)"/>
- <wire from="(960,520)" to="(960,530)"/>
<wire from="(960,520)" to="(980,520)"/>
- <wire from="(970,170)" to="(1000,170)"/>
- <wire from="(970,170)" to="(970,230)"/>
- <wire from="(970,450)" to="(970,460)"/>
- <wire from="(970,450)" to="(980,450)"/>
+ <wire from="(170,170)" to="(970,170)"/>
+ <wire from="(50,150)" to="(50,250)"/>
+ <wire from="(50,250)" to="(50,350)"/>
+ <wire from="(630,350)" to="(650,350)"/>
+ <wire from="(170,210)" to="(170,310)"/>
+ <wire from="(380,230)" to="(410,230)"/>
+ <wire from="(380,330)" to="(410,330)"/>
+ <wire from="(630,410)" to="(840,410)"/>
+ <wire from="(680,270)" to="(680,560)"/>
+ <wire from="(110,270)" to="(110,510)"/>
+ <wire from="(650,350)" to="(650,470)"/>
+ <wire from="(1030,340)" to="(1030,400)"/>
<wire from="(970,460)" to="(980,460)"/>
- <wire from="(970,470)" to="(970,480)"/>
- <wire from="(970,470)" to="(980,470)"/>
<wire from="(970,480)" to="(980,480)"/>
- <wire from="(990,270)" to="(1030,270)"/>
+ <wire from="(110,150)" to="(110,270)"/>
+ <wire from="(640,430)" to="(640,480)"/>
+ <wire from="(870,300)" to="(950,300)"/>
+ <comp lib="0" loc="(110,150)" name="Pin">
+ <a name="facing" val="south"/>
+ <a name="width" val="8"/>
+ <a name="label" val="B_in"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1220,420)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="8"/>
+ <a name="appear" val="right"/>
+ <a name="bit0" val="none"/>
+ <a name="bit1" val="none"/>
+ <a name="bit2" val="none"/>
+ <a name="bit3" val="none"/>
+ <a name="bit4" val="none"/>
+ <a name="bit5" val="none"/>
+ <a name="bit6" val="none"/>
+ <a name="bit7" val="0"/>
+ </comp>
+ <comp lib="0" loc="(1240,360)" name="Constant">
+ <a name="width" val="8"/>
+ <a name="value" val="0x0"/>
+ </comp>
+ <comp lib="0" loc="(1260,270)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="8"/>
+ <a name="label" val="R"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1260,430)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="N"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1260,490)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="C"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1260,560)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="V"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1410,350)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="Z"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(170,150)" name="Pin">
+ <a name="facing" val="south"/>
+ <a name="width" val="3"/>
+ <a name="label" val="OP_in"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(370,210)" name="Splitter">
+ <a name="facing" val="south"/>
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="3"/>
+ <a name="bit1" val="none"/>
+ <a name="bit2" val="none"/>
+ </comp>
+ <comp lib="0" loc="(370,310)" name="Splitter">
+ <a name="facing" val="south"/>
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="3"/>
+ <a name="bit1" val="none"/>
+ <a name="bit2" val="none"/>
+ </comp>
+ <comp lib="0" loc="(50,150)" name="Pin">
+ <a name="facing" val="south"/>
+ <a name="width" val="8"/>
+ <a name="label" val="A_in"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(960,530)" name="Ground"/>
+ <comp lib="2" loc="(1020,490)" name="Multiplexer">
+ <a name="selloc" val="tr"/>
+ <a name="select" val="3"/>
+ </comp>
+ <comp lib="2" loc="(990,270)" name="Multiplexer">
+ <a name="selloc" val="tr"/>
+ <a name="select" val="3"/>
+ <a name="width" val="8"/>
+ </comp>
+ <comp lib="3" loc="(1310,350)" name="Comparator"/>
+ <comp loc="(630,230)" name="ALU_ADD_SOUS">
+ <a name="label" val="ALU_ADDER"/>
+ </comp>
+ <comp loc="(630,330)" name="ALU_SHIFT">
+ <a name="label" val="ALU_SH"/>
+ </comp>
+ <comp loc="(630,410)" name="ALU_SHIFT_SIGNED">
+ <a name="label" val="ALU_SH_SIGNED"/>
+ </comp>
+ <comp loc="(630,490)" name="ALU_AND">
+ <a name="label" val="ALU_ET"/>
+ </comp>
+ <comp loc="(630,570)" name="ALU_OR">
+ <a name="label" val="ALU_OU"/>
+ </comp>
+ <comp loc="(630,650)" name="ALU_NOT">
+ <a name="label" val="ALU_NON"/>
+ </comp>
</circuit>
<circuit name="CPU_RL">
- <a name="appearance" val="custom"/>
<a name="circuit" val="CPU_RL"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="custom"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
<appear>
<rect fill="none" height="79" stroke="#000000" stroke-width="2" width="120" x="60" y="50"/>
<rect height="19" stroke="none" width="120" x="60" y="110"/>
@@ -2598,101 +2767,193 @@
<text dominant-baseline="alphabetic" fill="#404040" font-family="Dialog" font-size="12" text-anchor="start" x="65" y="64">PC</text>
<text dominant-baseline="alphabetic" fill="#404040" font-family="Dialog" font-size="12" text-anchor="start" x="65" y="84">CLK</text>
<text dominant-baseline="alphabetic" fill="#ffffff" font-family="Dialog" font-size="14" font-weight="bold" text-anchor="middle" x="121" y="123">CPU_RL</text>
- <visible-register height="10" path="/Register(760,180)" stroke-width="0" width="6" x="160" y="70"/>
- <circ-anchor facing="east" height="6" width="6" x="187" y="57"/>
<circ-port height="10" pin="870,210" width="10" x="185" y="55"/>
<circ-port height="8" pin="610,200" width="8" x="46" y="56"/>
<circ-port height="8" pin="730,250" width="8" x="46" y="76"/>
<circ-port height="8" pin="790,300" width="8" x="46" y="96"/>
+ <visible-register height="10" path="/Register(760,180)" stroke-width="0" width="6" x="160" y="70"/>
+ <circ-anchor facing="east" height="6" width="6" x="187" y="57"/>
</appear>
+ <wire from="(790,270)" to="(790,300)"/>
+ <wire from="(820,210)" to="(870,210)"/>
+ <wire from="(610,200)" to="(680,200)"/>
+ <wire from="(720,210)" to="(760,210)"/>
+ <wire from="(660,220)" to="(680,220)"/>
+ <wire from="(730,250)" to="(760,250)"/>
+ <wire from="(750,230)" to="(760,230)"/>
<comp lib="0" loc="(610,200)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="PC"/>
<a name="width" val="4"/>
+ <a name="label" val="PC"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(660,220)" name="Constant">
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(730,250)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(750,230)" name="Constant"/>
<comp lib="0" loc="(790,300)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="north"/>
<a name="label" val="RESET"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(870,210)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="REG_L"/>
<a name="output" val="true"/>
<a name="width" val="4"/>
+ <a name="label" val="REG_L"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="3" loc="(720,210)" name="Adder">
<a name="width" val="4"/>
</comp>
<comp lib="4" loc="(760,180)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
<a name="width" val="4"/>
</comp>
- <wire from="(610,200)" to="(680,200)"/>
- <wire from="(660,220)" to="(680,220)"/>
- <wire from="(720,210)" to="(760,210)"/>
- <wire from="(730,250)" to="(760,250)"/>
- <wire from="(750,230)" to="(760,230)"/>
- <wire from="(790,270)" to="(790,300)"/>
- <wire from="(820,210)" to="(870,210)"/>
</circuit>
<circuit name="CPU_RAM8">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="CPU_RAM8"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(720,140)" to="(720,150)"/>
+ <wire from="(720,400)" to="(720,410)"/>
+ <wire from="(720,660)" to="(720,670)"/>
+ <wire from="(720,920)" to="(720,930)"/>
+ <wire from="(670,150)" to="(720,150)"/>
+ <wire from="(670,410)" to="(720,410)"/>
+ <wire from="(670,670)" to="(720,670)"/>
+ <wire from="(670,930)" to="(720,930)"/>
+ <wire from="(1020,540)" to="(1120,540)"/>
+ <wire from="(750,210)" to="(1040,210)"/>
+ <wire from="(460,560)" to="(560,560)"/>
+ <wire from="(180,180)" to="(280,180)"/>
+ <wire from="(180,220)" to="(280,220)"/>
+ <wire from="(180,240)" to="(280,240)"/>
+ <wire from="(750,80)" to="(1050,80)"/>
+ <wire from="(1040,560)" to="(1120,560)"/>
+ <wire from="(460,570)" to="(550,570)"/>
+ <wire from="(540,880)" to="(690,880)"/>
+ <wire from="(1140,580)" to="(1140,630)"/>
+ <wire from="(750,340)" to="(1030,340)"/>
+ <wire from="(540,580)" to="(540,880)"/>
+ <wire from="(670,120)" to="(690,120)"/>
+ <wire from="(670,340)" to="(690,340)"/>
+ <wire from="(670,380)" to="(690,380)"/>
+ <wire from="(670,600)" to="(690,600)"/>
+ <wire from="(670,640)" to="(690,640)"/>
+ <wire from="(670,860)" to="(690,860)"/>
+ <wire from="(670,900)" to="(690,900)"/>
+ <wire from="(530,100)" to="(690,100)"/>
+ <wire from="(1030,520)" to="(1120,520)"/>
+ <wire from="(1050,500)" to="(1120,500)"/>
+ <wire from="(530,590)" to="(530,1010)"/>
+ <wire from="(440,600)" to="(440,640)"/>
+ <wire from="(1020,540)" to="(1020,600)"/>
+ <wire from="(200,120)" to="(280,120)"/>
+ <wire from="(1050,570)" to="(1050,990)"/>
+ <wire from="(560,560)" to="(560,620)"/>
+ <wire from="(560,620)" to="(690,620)"/>
+ <wire from="(460,580)" to="(540,580)"/>
+ <wire from="(750,470)" to="(1020,470)"/>
+ <wire from="(1030,550)" to="(1030,730)"/>
+ <wire from="(1040,560)" to="(1040,860)"/>
+ <wire from="(550,360)" to="(690,360)"/>
+ <wire from="(550,570)" to="(550,750)"/>
+ <wire from="(460,590)" to="(530,590)"/>
+ <wire from="(720,1050)" to="(720,1060)"/>
+ <wire from="(720,270)" to="(720,280)"/>
+ <wire from="(720,530)" to="(720,540)"/>
+ <wire from="(720,790)" to="(720,800)"/>
+ <wire from="(670,1060)" to="(720,1060)"/>
+ <wire from="(670,280)" to="(720,280)"/>
+ <wire from="(670,540)" to="(720,540)"/>
+ <wire from="(670,800)" to="(720,800)"/>
+ <wire from="(1020,530)" to="(1120,530)"/>
+ <wire from="(750,860)" to="(1040,860)"/>
+ <wire from="(580,80)" to="(690,80)"/>
+ <wire from="(460,550)" to="(560,550)"/>
+ <wire from="(750,990)" to="(1050,990)"/>
+ <wire from="(1040,510)" to="(1120,510)"/>
+ <wire from="(250,160)" to="(280,160)"/>
+ <wire from="(460,540)" to="(550,540)"/>
+ <wire from="(540,230)" to="(690,230)"/>
+ <wire from="(1040,210)" to="(1040,510)"/>
+ <wire from="(750,730)" to="(1030,730)"/>
+ <wire from="(540,230)" to="(540,530)"/>
+ <wire from="(670,1030)" to="(690,1030)"/>
+ <wire from="(670,210)" to="(690,210)"/>
+ <wire from="(670,250)" to="(690,250)"/>
+ <wire from="(670,470)" to="(690,470)"/>
+ <wire from="(670,510)" to="(690,510)"/>
+ <wire from="(670,730)" to="(690,730)"/>
+ <wire from="(670,770)" to="(690,770)"/>
+ <wire from="(670,990)" to="(690,990)"/>
+ <wire from="(530,1010)" to="(690,1010)"/>
+ <wire from="(1030,550)" to="(1120,550)"/>
+ <wire from="(1050,570)" to="(1120,570)"/>
+ <wire from="(400,560)" to="(420,560)"/>
+ <wire from="(1050,80)" to="(1050,500)"/>
+ <wire from="(1160,540)" to="(1230,540)"/>
+ <wire from="(530,100)" to="(530,520)"/>
+ <wire from="(1020,470)" to="(1020,530)"/>
+ <wire from="(560,490)" to="(560,550)"/>
+ <wire from="(560,490)" to="(690,490)"/>
+ <wire from="(460,530)" to="(540,530)"/>
+ <wire from="(750,600)" to="(1020,600)"/>
+ <wire from="(1030,340)" to="(1030,520)"/>
+ <wire from="(550,360)" to="(550,540)"/>
+ <wire from="(550,750)" to="(690,750)"/>
+ <wire from="(460,520)" to="(530,520)"/>
<comp lib="0" loc="(1140,630)" name="Tunnel">
<a name="facing" val="north"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD_A"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(1230,540)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="DATA_OUT"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_OUT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(180,180)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="EN_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(180,220)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(180,240)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="RESET"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(200,120)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="ADD_A"/>
<a name="width" val="3"/>
+ <a name="label" val="ADD_A"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(250,160)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="DATA_WR"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(280,120)" name="Tunnel">
+ <a name="width" val="3"/>
<a name="label" val="ADD_A"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(280,160)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(280,180)" name="Tunnel">
<a name="label" val="EN_WR"/>
@@ -2713,15 +2974,15 @@
</comp>
<comp lib="0" loc="(440,640)" name="Tunnel">
<a name="facing" val="north"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD_A"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(580,80)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,1030)" name="Tunnel">
<a name="facing" val="east"/>
@@ -2745,9 +3006,9 @@
</comp>
<comp lib="0" loc="(670,210)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,250)" name="Tunnel">
<a name="facing" val="east"/>
@@ -2761,9 +3022,9 @@
</comp>
<comp lib="0" loc="(670,340)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,380)" name="Tunnel">
<a name="facing" val="east"/>
@@ -2777,9 +3038,9 @@
</comp>
<comp lib="0" loc="(670,470)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,510)" name="Tunnel">
<a name="facing" val="east"/>
@@ -2793,9 +3054,9 @@
</comp>
<comp lib="0" loc="(670,600)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,640)" name="Tunnel">
<a name="facing" val="east"/>
@@ -2809,9 +3070,9 @@
</comp>
<comp lib="0" loc="(670,730)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,770)" name="Tunnel">
<a name="facing" val="east"/>
@@ -2825,9 +3086,9 @@
</comp>
<comp lib="0" loc="(670,860)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(670,900)" name="Tunnel">
<a name="facing" val="east"/>
@@ -2841,184 +3102,111 @@
</comp>
<comp lib="0" loc="(670,990)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="2" loc="(1160,540)" name="Multiplexer">
- <a name="select" val="3"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
</comp>
- <comp lib="2" loc="(420,560)" name="Demultiplexer">
- <a name="select" val="3"/>
- </comp>
- <comp lib="4" loc="(690,180)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,310)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,440)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,50)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,570)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,700)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="4" loc="(690,830)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp lib="2" loc="(1160,540)" name="Multiplexer">
+ <a name="select" val="3"/>
+ <a name="width" val="8"/>
</comp>
- <comp lib="4" loc="(690,960)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp lib="2" loc="(420,560)" name="Demultiplexer">
+ <a name="select" val="3"/>
</comp>
+ <comp lib="4" loc="(690,180)" name="Register"/>
+ <comp lib="4" loc="(690,310)" name="Register"/>
+ <comp lib="4" loc="(690,440)" name="Register"/>
+ <comp lib="4" loc="(690,50)" name="Register"/>
+ <comp lib="4" loc="(690,570)" name="Register"/>
+ <comp lib="4" loc="(690,700)" name="Register"/>
+ <comp lib="4" loc="(690,830)" name="Register"/>
+ <comp lib="4" loc="(690,960)" name="Register"/>
<comp lib="6" loc="(1144,666)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
<a name="text" val="READ A"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <wire from="(1020,470)" to="(1020,530)"/>
- <wire from="(1020,530)" to="(1120,530)"/>
- <wire from="(1020,540)" to="(1020,600)"/>
- <wire from="(1020,540)" to="(1120,540)"/>
- <wire from="(1030,340)" to="(1030,520)"/>
- <wire from="(1030,520)" to="(1120,520)"/>
- <wire from="(1030,550)" to="(1030,730)"/>
- <wire from="(1030,550)" to="(1120,550)"/>
- <wire from="(1040,210)" to="(1040,510)"/>
- <wire from="(1040,510)" to="(1120,510)"/>
- <wire from="(1040,560)" to="(1040,860)"/>
- <wire from="(1040,560)" to="(1120,560)"/>
- <wire from="(1050,500)" to="(1120,500)"/>
- <wire from="(1050,570)" to="(1050,990)"/>
- <wire from="(1050,570)" to="(1120,570)"/>
- <wire from="(1050,80)" to="(1050,500)"/>
- <wire from="(1140,580)" to="(1140,630)"/>
- <wire from="(1160,540)" to="(1230,540)"/>
- <wire from="(180,180)" to="(280,180)"/>
- <wire from="(180,220)" to="(280,220)"/>
- <wire from="(180,240)" to="(280,240)"/>
- <wire from="(200,120)" to="(280,120)"/>
- <wire from="(250,160)" to="(280,160)"/>
- <wire from="(400,560)" to="(420,560)"/>
- <wire from="(440,600)" to="(440,640)"/>
- <wire from="(460,520)" to="(530,520)"/>
- <wire from="(460,530)" to="(540,530)"/>
- <wire from="(460,540)" to="(550,540)"/>
- <wire from="(460,550)" to="(560,550)"/>
- <wire from="(460,560)" to="(560,560)"/>
- <wire from="(460,570)" to="(550,570)"/>
- <wire from="(460,580)" to="(540,580)"/>
- <wire from="(460,590)" to="(530,590)"/>
- <wire from="(530,100)" to="(530,520)"/>
- <wire from="(530,100)" to="(690,100)"/>
- <wire from="(530,1010)" to="(690,1010)"/>
- <wire from="(530,590)" to="(530,1010)"/>
- <wire from="(540,230)" to="(540,530)"/>
- <wire from="(540,230)" to="(690,230)"/>
- <wire from="(540,580)" to="(540,880)"/>
- <wire from="(540,880)" to="(690,880)"/>
- <wire from="(550,360)" to="(550,540)"/>
- <wire from="(550,360)" to="(690,360)"/>
- <wire from="(550,570)" to="(550,750)"/>
- <wire from="(550,750)" to="(690,750)"/>
- <wire from="(560,490)" to="(560,550)"/>
- <wire from="(560,490)" to="(690,490)"/>
- <wire from="(560,560)" to="(560,620)"/>
- <wire from="(560,620)" to="(690,620)"/>
- <wire from="(580,80)" to="(690,80)"/>
- <wire from="(670,1030)" to="(690,1030)"/>
- <wire from="(670,1060)" to="(720,1060)"/>
- <wire from="(670,120)" to="(690,120)"/>
- <wire from="(670,150)" to="(720,150)"/>
- <wire from="(670,210)" to="(690,210)"/>
- <wire from="(670,250)" to="(690,250)"/>
- <wire from="(670,280)" to="(720,280)"/>
- <wire from="(670,340)" to="(690,340)"/>
- <wire from="(670,380)" to="(690,380)"/>
- <wire from="(670,410)" to="(720,410)"/>
- <wire from="(670,470)" to="(690,470)"/>
- <wire from="(670,510)" to="(690,510)"/>
- <wire from="(670,540)" to="(720,540)"/>
- <wire from="(670,600)" to="(690,600)"/>
- <wire from="(670,640)" to="(690,640)"/>
- <wire from="(670,670)" to="(720,670)"/>
- <wire from="(670,730)" to="(690,730)"/>
- <wire from="(670,770)" to="(690,770)"/>
- <wire from="(670,800)" to="(720,800)"/>
- <wire from="(670,860)" to="(690,860)"/>
- <wire from="(670,900)" to="(690,900)"/>
- <wire from="(670,930)" to="(720,930)"/>
- <wire from="(670,990)" to="(690,990)"/>
- <wire from="(720,1050)" to="(720,1060)"/>
- <wire from="(720,140)" to="(720,150)"/>
- <wire from="(720,270)" to="(720,280)"/>
- <wire from="(720,400)" to="(720,410)"/>
- <wire from="(720,530)" to="(720,540)"/>
- <wire from="(720,660)" to="(720,670)"/>
- <wire from="(720,790)" to="(720,800)"/>
- <wire from="(720,920)" to="(720,930)"/>
- <wire from="(750,210)" to="(1040,210)"/>
- <wire from="(750,340)" to="(1030,340)"/>
- <wire from="(750,470)" to="(1020,470)"/>
- <wire from="(750,600)" to="(1020,600)"/>
- <wire from="(750,730)" to="(1030,730)"/>
- <wire from="(750,80)" to="(1050,80)"/>
- <wire from="(750,860)" to="(1040,860)"/>
- <wire from="(750,990)" to="(1050,990)"/>
</circuit>
<circuit name="CPU_RAM16">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="CPU_RAM16"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(1130,490)" to="(1130,510)"/>
+ <wire from="(670,370)" to="(730,370)"/>
+ <wire from="(830,340)" to="(870,340)"/>
+ <wire from="(830,360)" to="(870,360)"/>
+ <wire from="(830,400)" to="(870,400)"/>
+ <wire from="(830,420)" to="(870,420)"/>
+ <wire from="(830,480)" to="(870,480)"/>
+ <wire from="(830,500)" to="(870,500)"/>
+ <wire from="(830,540)" to="(870,540)"/>
+ <wire from="(830,560)" to="(870,560)"/>
+ <wire from="(760,380)" to="(870,380)"/>
+ <wire from="(760,520)" to="(870,520)"/>
+ <wire from="(420,250)" to="(520,250)"/>
+ <wire from="(420,290)" to="(520,290)"/>
+ <wire from="(420,310)" to="(520,310)"/>
+ <wire from="(450,150)" to="(490,150)"/>
+ <wire from="(490,230)" to="(520,230)"/>
+ <wire from="(510,120)" to="(540,120)"/>
+ <wire from="(510,140)" to="(540,140)"/>
+ <wire from="(1090,340)" to="(1100,340)"/>
+ <wire from="(670,390)" to="(690,390)"/>
+ <wire from="(710,390)" to="(730,390)"/>
+ <wire from="(710,510)" to="(730,510)"/>
+ <wire from="(710,530)" to="(730,530)"/>
+ <wire from="(1100,340)" to="(1100,460)"/>
+ <wire from="(1090,480)" to="(1120,480)"/>
+ <wire from="(1150,470)" to="(1180,470)"/>
+ <wire from="(1100,460)" to="(1120,460)"/>
<comp lib="0" loc="(1130,510)" name="Tunnel">
<a name="facing" val="north"/>
<a name="label" val="SEL"/>
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(1180,470)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="DATA_OUT"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_OUT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(420,250)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="EN_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(420,290)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(420,310)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="RESET"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(450,150)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="ADD"/>
<a name="width" val="4"/>
+ <a name="label" val="ADD"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(490,150)" name="Splitter">
+ <a name="incoming" val="4"/>
+ <a name="spacing" val="2"/>
<a name="bit1" val="0"/>
<a name="bit2" val="0"/>
<a name="bit3" val="1"/>
- <a name="incoming" val="4"/>
- <a name="spacing" val="2"/>
</comp>
<comp lib="0" loc="(490,230)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="DATA_WR"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(520,230)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(520,250)" name="Tunnel">
<a name="label" val="EN_WR"/>
@@ -3033,9 +3221,9 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(540,120)" name="Tunnel">
+ <a name="width" val="3"/>
<a name="label" val="ADD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(540,140)" name="Tunnel">
<a name="label" val="SEL"/>
@@ -3063,15 +3251,15 @@
</comp>
<comp lib="0" loc="(830,340)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(830,360)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(830,400)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3085,15 +3273,15 @@
</comp>
<comp lib="0" loc="(830,480)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="3"/>
<a name="label" val="ADD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="3"/>
</comp>
<comp lib="0" loc="(830,500)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(830,540)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3123,39 +3311,172 @@
<comp loc="(1090,480)" name="CPU_RAM8">
<a name="label" val="RAM8_2"/>
</comp>
- <wire from="(1090,340)" to="(1100,340)"/>
- <wire from="(1090,480)" to="(1120,480)"/>
- <wire from="(1100,340)" to="(1100,460)"/>
- <wire from="(1100,460)" to="(1120,460)"/>
- <wire from="(1130,490)" to="(1130,510)"/>
- <wire from="(1150,470)" to="(1180,470)"/>
+ </circuit>
+ <circuit name="CPU_RAM24">
+ <a name="circuit" val="CPU_RAM24"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="custom"/>
+ <a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <appear>
+ <rect height="4" stroke="none" width="10" x="50" y="58"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="64">ADDR</text>
+ <rect height="4" stroke="none" width="10" x="50" y="78"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="84">DATA_WR</text>
+ <rect height="3" stroke="none" width="10" x="50" y="99"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="104">EN_WR</text>
+ <rect height="3" stroke="none" width="10" x="50" y="119"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="124">CLK</text>
+ <rect height="3" stroke="none" width="10" x="50" y="139"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="144">RESET</text>
+ <rect height="4" stroke="none" width="10" x="50" y="158"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="start" x="65" y="164">UART_BLUE..</text>
+ <rect height="4" stroke="none" width="10" x="260" y="58"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="64">DATA_OUT</text>
+ <rect height="4" stroke="none" width="10" x="260" y="78"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="84">WHEEL_RIG..</text>
+ <circ-port height="10" pin="1920,620" width="10" x="265" y="75"/>
+ <circ-port height="10" pin="1750,510" width="10" x="265" y="55"/>
+ <circ-port height="8" pin="420,330" width="8" x="46" y="156"/>
+ <circ-port height="8" pin="420,310" width="8" x="46" y="136"/>
+ <circ-port height="8" pin="420,290" width="8" x="46" y="116"/>
+ <circ-port height="8" pin="420,250" width="8" x="46" y="96"/>
+ <circ-port height="8" pin="490,230" width="8" x="46" y="76"/>
+ <circ-port height="8" pin="460,150" width="8" x="46" y="56"/>
+ <rect height="4" stroke="none" width="10" x="260" y="98"/>
+ <circ-port height="10" pin="1920,640" width="10" x="265" y="95"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="104">WHEEL_LEF..</text>
+ <rect height="4" stroke="none" width="10" x="260" y="118"/>
+ <circ-port height="10" pin="1920,660" width="10" x="265" y="115"/>
+ <text dominant-baseline="alphabetic" fill="#404040" font-family="Courier 10 Pitch" font-size="12" text-anchor="end" x="255" y="124">UART_OUT</text>
+ <rect height="20" stroke="none" width="200" x="60" y="170"/>
+ <rect fill="none" height="140" stroke="#000000" stroke-width="2" width="200" x="60" y="50"/>
+ <text dominant-baseline="alphabetic" fill="#ffffff" font-family="Courier 10 Pitch" font-size="14" font-weight="bold" text-anchor="middle" x="160" y="184">CPU_RAM24</text>
+ <visible-register height="10" path="/Register(1010,520)" stroke-width="0" width="13" x="138" y="70"/>
+ <visible-register height="10" path="/Register(1010,650)" stroke-width="0" width="13" x="138" y="80"/>
+ <visible-register height="10" path="/Register(1010,780)" stroke-width="0" width="13" x="138" y="90"/>
+ <circ-anchor facing="east" height="6" width="6" x="267" y="57"/>
+ </appear>
+ <wire from="(990,1270)" to="(1040,1270)"/>
+ <wire from="(990,750)" to="(1040,750)"/>
+ <wire from="(1070,1460)" to="(1370,1460)"/>
+ <wire from="(780,1020)" to="(880,1020)"/>
+ <wire from="(1040,1000)" to="(1040,1010)"/>
+ <wire from="(1040,1520)" to="(1040,1530)"/>
+ <wire from="(1350,810)" to="(1350,990)"/>
+ <wire from="(1670,380)" to="(1670,500)"/>
+ <wire from="(860,700)" to="(860,1000)"/>
+ <wire from="(990,1460)" to="(1010,1460)"/>
+ <wire from="(990,1500)" to="(1010,1500)"/>
+ <wire from="(990,940)" to="(1010,940)"/>
+ <wire from="(990,980)" to="(1010,980)"/>
+ <wire from="(1360,980)" to="(1440,980)"/>
+ <wire from="(490,230)" to="(520,230)"/>
+ <wire from="(670,1020)" to="(690,1020)"/>
+ <wire from="(720,1030)" to="(740,1030)"/>
+ <wire from="(860,700)" to="(1010,700)"/>
+ <wire from="(1340,940)" to="(1340,1000)"/>
+ <wire from="(850,1480)" to="(1010,1480)"/>
+ <wire from="(1370,1040)" to="(1440,1040)"/>
+ <wire from="(1660,380)" to="(1670,380)"/>
+ <wire from="(880,960)" to="(880,1020)"/>
+ <wire from="(1370,550)" to="(1370,970)"/>
+ <wire from="(1670,520)" to="(1670,1010)"/>
+ <wire from="(1670,500)" to="(1690,500)"/>
+ <wire from="(1370,550)" to="(1400,550)"/>
+ <wire from="(1070,1200)" to="(1350,1200)"/>
+ <wire from="(1360,680)" to="(1360,980)"/>
+ <wire from="(780,1000)" to="(860,1000)"/>
+ <wire from="(1240,430)" to="(1260,430)"/>
+ <wire from="(1280,430)" to="(1300,430)"/>
+ <wire from="(990,1400)" to="(1040,1400)"/>
+ <wire from="(990,880)" to="(1040,880)"/>
+ <wire from="(1070,550)" to="(1370,550)"/>
+ <wire from="(1400,380)" to="(1440,380)"/>
+ <wire from="(1400,460)" to="(1440,460)"/>
+ <wire from="(1500,1100)" to="(1500,1190)"/>
+ <wire from="(1070,680)" to="(1360,680)"/>
+ <wire from="(780,1030)" to="(880,1030)"/>
+ <wire from="(1480,1010)" to="(1670,1010)"/>
+ <wire from="(1040,1130)" to="(1040,1140)"/>
+ <wire from="(1040,610)" to="(1040,620)"/>
+ <wire from="(420,310)" to="(520,310)"/>
+ <wire from="(1350,1020)" to="(1350,1200)"/>
+ <wire from="(1070,940)" to="(1340,940)"/>
+ <wire from="(990,1070)" to="(1010,1070)"/>
+ <wire from="(990,1110)" to="(1010,1110)"/>
+ <wire from="(990,550)" to="(1010,550)"/>
+ <wire from="(990,590)" to="(1010,590)"/>
+ <wire from="(1360,1030)" to="(1440,1030)"/>
+ <wire from="(510,140)" to="(540,140)"/>
+ <wire from="(860,1350)" to="(1010,1350)"/>
+ <wire from="(780,1040)" to="(870,1040)"/>
+ <wire from="(980,570)" to="(1010,570)"/>
+ <wire from="(1370,970)" to="(1440,970)"/>
+ <wire from="(1370,1040)" to="(1370,1460)"/>
+ <wire from="(780,1060)" to="(850,1060)"/>
+ <wire from="(1070,810)" to="(1350,810)"/>
+ <wire from="(1720,510)" to="(1750,510)"/>
+ <wire from="(780,1050)" to="(860,1050)"/>
+ <wire from="(1890,640)" to="(1920,640)"/>
+ <wire from="(990,1010)" to="(1040,1010)"/>
+ <wire from="(990,1530)" to="(1040,1530)"/>
+ <wire from="(1330,420)" to="(1440,420)"/>
+ <wire from="(1340,1000)" to="(1440,1000)"/>
+ <wire from="(1070,1330)" to="(1360,1330)"/>
+ <wire from="(1240,410)" to="(1300,410)"/>
+ <wire from="(1040,1260)" to="(1040,1270)"/>
+ <wire from="(1040,740)" to="(1040,750)"/>
+ <wire from="(1350,810)" to="(1400,810)"/>
+ <wire from="(1070,1070)" to="(1340,1070)"/>
+ <wire from="(990,1200)" to="(1010,1200)"/>
+ <wire from="(990,1240)" to="(1010,1240)"/>
+ <wire from="(990,680)" to="(1010,680)"/>
+ <wire from="(990,720)" to="(1010,720)"/>
+ <wire from="(670,1040)" to="(690,1040)"/>
+ <wire from="(780,1010)" to="(870,1010)"/>
+ <wire from="(1350,1020)" to="(1440,1020)"/>
+ <wire from="(880,960)" to="(1010,960)"/>
+ <wire from="(1670,520)" to="(1690,520)"/>
+ <wire from="(870,1220)" to="(1010,1220)"/>
+ <wire from="(870,830)" to="(870,1010)"/>
+ <wire from="(990,1140)" to="(1040,1140)"/>
+ <wire from="(990,620)" to="(1040,620)"/>
+ <wire from="(1340,1010)" to="(1440,1010)"/>
+ <wire from="(1360,680)" to="(1400,680)"/>
+ <wire from="(1400,400)" to="(1440,400)"/>
+ <wire from="(1400,440)" to="(1440,440)"/>
+ <wire from="(1700,530)" to="(1700,550)"/>
+ <wire from="(1440,1200)" to="(1480,1200)"/>
+ <wire from="(1460,1100)" to="(1500,1100)"/>
+ <wire from="(670,1110)" to="(710,1110)"/>
+ <wire from="(760,1070)" to="(760,1100)"/>
+ <wire from="(1040,1390)" to="(1040,1400)"/>
+ <wire from="(1040,870)" to="(1040,880)"/>
<wire from="(420,250)" to="(520,250)"/>
<wire from="(420,290)" to="(520,290)"/>
- <wire from="(420,310)" to="(520,310)"/>
- <wire from="(450,150)" to="(490,150)"/>
- <wire from="(490,230)" to="(520,230)"/>
+ <wire from="(420,330)" to="(520,330)"/>
+ <wire from="(860,1050)" to="(860,1350)"/>
+ <wire from="(990,1330)" to="(1010,1330)"/>
+ <wire from="(990,1370)" to="(1010,1370)"/>
+ <wire from="(990,810)" to="(1010,810)"/>
+ <wire from="(990,850)" to="(1010,850)"/>
+ <wire from="(1460,1050)" to="(1460,1100)"/>
+ <wire from="(460,150)" to="(490,150)"/>
<wire from="(510,120)" to="(540,120)"/>
- <wire from="(510,140)" to="(540,140)"/>
- <wire from="(670,370)" to="(730,370)"/>
- <wire from="(670,390)" to="(690,390)"/>
- <wire from="(710,390)" to="(730,390)"/>
- <wire from="(710,510)" to="(730,510)"/>
- <wire from="(710,530)" to="(730,530)"/>
- <wire from="(760,380)" to="(870,380)"/>
- <wire from="(760,520)" to="(870,520)"/>
- <wire from="(830,340)" to="(870,340)"/>
- <wire from="(830,360)" to="(870,360)"/>
- <wire from="(830,400)" to="(870,400)"/>
- <wire from="(830,420)" to="(870,420)"/>
- <wire from="(830,480)" to="(870,480)"/>
- <wire from="(830,500)" to="(870,500)"/>
- <wire from="(830,540)" to="(870,540)"/>
- <wire from="(830,560)" to="(870,560)"/>
- </circuit>
- <circuit name="CPU_RAM24">
- <a name="appearance" val="logisim_evolution"/>
- <a name="circuit" val="CPU_RAM24"/>
- <a name="circuitnamedboxfixedsize" val="true"/>
+ <wire from="(1340,1010)" to="(1340,1070)"/>
+ <wire from="(730,1100)" to="(760,1100)"/>
+ <wire from="(850,1060)" to="(850,1480)"/>
+ <wire from="(880,1030)" to="(880,1090)"/>
+ <wire from="(1350,990)" to="(1440,990)"/>
+ <wire from="(880,1090)" to="(1010,1090)"/>
+ <wire from="(1360,1030)" to="(1360,1330)"/>
+ <wire from="(870,1040)" to="(870,1220)"/>
+ <wire from="(870,830)" to="(1010,830)"/>
+ <wire from="(1890,620)" to="(1920,620)"/>
+ <wire from="(1890,660)" to="(1920,660)"/>
<comp lib="0" loc="(1240,410)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="EN_WR"/>
@@ -3168,15 +3489,15 @@
</comp>
<comp lib="0" loc="(1400,380)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="ADD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(1400,400)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(1400,440)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3189,27 +3510,27 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(1400,680)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="WHEEL_RIGHT"/>
<a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(1400,810)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="WHEEL_LEFT"/>
<a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(1440,1200)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="ADD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(1480,1200)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="4"/>
<a name="bit1" val="0"/>
<a name="bit2" val="0"/>
<a name="bit3" val="none"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(1700,550)" name="Tunnel">
<a name="facing" val="north"/>
@@ -3217,77 +3538,77 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(1750,510)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="DATA_OUT"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_OUT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(1890,620)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="WHEEL_RIGHT"/>
<a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(1890,640)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="WHEEL_LEFT"/>
<a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(1920,620)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="WHEEL_RIGHT_PWM"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="WHEEL_RIGHT_PWM"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(1920,640)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="WHEEL_LEFT_PWM"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="WHEEL_LEFT_PWM"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(420,250)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="EN_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(420,290)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(420,310)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="RESET"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(420,330)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="UART_BLUETOOTH"/>
<a name="width" val="8"/>
+ <a name="label" val="UART_BLUETOOTH"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(460,150)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="ADDR"/>
<a name="width" val="5"/>
+ <a name="label" val="ADDR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(490,150)" name="Splitter">
+ <a name="incoming" val="5"/>
+ <a name="spacing" val="2"/>
<a name="bit1" val="0"/>
<a name="bit2" val="0"/>
<a name="bit3" val="0"/>
<a name="bit4" val="1"/>
- <a name="incoming" val="5"/>
- <a name="spacing" val="2"/>
</comp>
<comp lib="0" loc="(490,230)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="label" val="DATA_WR"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(520,230)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(520,250)" name="Tunnel">
<a name="label" val="EN_WR"/>
@@ -3302,14 +3623,14 @@
<a name="labelfont" val="SansSerif bold 8"/>
</comp>
<comp lib="0" loc="(520,330)" name="Tunnel">
+ <a name="width" val="8"/>
<a name="label" val="UART_BLUETOOTH"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(540,120)" name="Tunnel">
+ <a name="width" val="4"/>
<a name="label" val="ADD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(540,140)" name="Tunnel">
<a name="label" val="SEL"/>
@@ -3327,16 +3648,16 @@
</comp>
<comp lib="0" loc="(670,1110)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="4"/>
<a name="label" val="ADD"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="4"/>
</comp>
<comp lib="0" loc="(710,1110)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="4"/>
<a name="bit1" val="0"/>
<a name="bit2" val="0"/>
<a name="bit3" val="none"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(980,570)" name="Constant"/>
<comp lib="0" loc="(990,1010)" name="Tunnel">
@@ -3346,9 +3667,9 @@
</comp>
<comp lib="0" loc="(990,1070)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(990,1110)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3362,9 +3683,9 @@
</comp>
<comp lib="0" loc="(990,1200)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(990,1240)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3378,9 +3699,9 @@
</comp>
<comp lib="0" loc="(990,1330)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(990,1370)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3394,9 +3715,9 @@
</comp>
<comp lib="0" loc="(990,1460)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(990,1500)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3410,9 +3731,9 @@
</comp>
<comp lib="0" loc="(990,550)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="UART_BLUETOOTH"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(990,590)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3426,9 +3747,9 @@
</comp>
<comp lib="0" loc="(990,680)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(990,720)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3442,9 +3763,9 @@
</comp>
<comp lib="0" loc="(990,810)" name="Tunnel">
<a name="facing" val="east"/>
+ <a name="width" val="8"/>
<a name="label" val="DATA_WR"/>
<a name="labelfont" val="SansSerif bold 8"/>
- <a name="width" val="8"/>
</comp>
<comp lib="0" loc="(990,850)" name="Tunnel">
<a name="facing" val="east"/>
@@ -3454,496 +3775,570 @@
<comp lib="0" loc="(990,880)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 8"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(990,940)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="DATA_WR"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="0" loc="(990,980)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 8"/>
+ </comp>
+ <comp lib="1" loc="(1280,430)" name="NOT Gate">
+ <a name="size" val="20"/>
+ </comp>
+ <comp lib="1" loc="(1330,420)" name="AND Gate">
+ <a name="size" val="30"/>
+ </comp>
+ <comp lib="1" loc="(720,1030)" name="AND Gate">
+ <a name="size" val="30"/>
+ </comp>
+ <comp lib="2" loc="(1480,1010)" name="Multiplexer">
+ <a name="select" val="3"/>
+ <a name="width" val="8"/>
+ </comp>
+ <comp lib="2" loc="(1720,510)" name="Multiplexer">
+ <a name="width" val="8"/>
+ </comp>
+ <comp lib="2" loc="(740,1030)" name="Demultiplexer">
+ <a name="select" val="3"/>
+ </comp>
+ <comp lib="4" loc="(1010,1040)" name="Register"/>
+ <comp lib="4" loc="(1010,1170)" name="Register"/>
+ <comp lib="4" loc="(1010,1300)" name="Register"/>
+ <comp lib="4" loc="(1010,1430)" name="Register"/>
+ <comp lib="4" loc="(1010,520)" name="Register"/>
+ <comp lib="4" loc="(1010,650)" name="Register"/>
+ <comp lib="4" loc="(1010,780)" name="Register"/>
+ <comp lib="4" loc="(1010,910)" name="Register"/>
+ <comp lib="6" loc="(1177,802)" name="Text">
+ <a name="text" val="WHEEL_LEFT"/>
+ <a name="font" val="SansSerif plain 12"/>
+ </comp>
+ <comp lib="6" loc="(1180,671)" name="Text">
+ <a name="text" val="WHEEL_RIGHT"/>
+ <a name="font" val="SansSerif plain 12"/>
+ </comp>
+ <comp lib="6" loc="(1191,543)" name="Text">
+ <a name="text" val="UART BLUETOOTH"/>
+ <a name="font" val="SansSerif plain 12"/>
+ </comp>
+ <comp loc="(1660,380)" name="CPU_RAM16">
+ <a name="label" val="RAM16_PROCESSOR"/>
+ </comp>
+ <comp lib="0" loc="(1400,550)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="UART_OUT"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(1890,660)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="UART_OUT"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(1920,660)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="8"/>
+ <a name="label" val="UART_OUT"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ </circuit>
+ <circuit name="TOP">
+ <a name="circuit" val="TOP"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
+ <a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(1040,340)" to="(1090,340)"/>
+ <wire from="(1040,360)" to="(1090,360)"/>
+ <wire from="(1040,380)" to="(1090,380)"/>
+ <wire from="(800,500)" to="(1630,500)"/>
+ <wire from="(740,690)" to="(800,690)"/>
+ <wire from="(1630,490)" to="(1630,500)"/>
+ <wire from="(710,360)" to="(820,360)"/>
+ <wire from="(1040,660)" to="(1050,660)"/>
+ <wire from="(340,340)" to="(370,340)"/>
+ <wire from="(340,360)" to="(370,360)"/>
+ <wire from="(340,380)" to="(370,380)"/>
+ <wire from="(650,730)" to="(680,730)"/>
+ <wire from="(800,440)" to="(800,500)"/>
+ <wire from="(1040,680)" to="(1070,680)"/>
+ <wire from="(1040,760)" to="(1070,760)"/>
+ <wire from="(1040,780)" to="(1070,780)"/>
+ <wire from="(800,500)" to="(800,690)"/>
+ <wire from="(590,340)" to="(660,340)"/>
+ <wire from="(1650,380)" to="(1670,380)"/>
+ <wire from="(1650,460)" to="(1670,460)"/>
+ <wire from="(1650,400)" to="(1670,400)"/>
+ <wire from="(1650,480)" to="(1670,480)"/>
+ <wire from="(1650,420)" to="(1670,420)"/>
+ <wire from="(1650,340)" to="(1670,340)"/>
+ <wire from="(1650,440)" to="(1670,440)"/>
+ <wire from="(1650,360)" to="(1670,360)"/>
+ <wire from="(1050,660)" to="(1070,660)"/>
+ <wire from="(1290,660)" to="(1310,660)"/>
+ <wire from="(1290,760)" to="(1310,760)"/>
+ <wire from="(1310,640)" to="(1310,660)"/>
+ <wire from="(1310,740)" to="(1310,760)"/>
+ <wire from="(590,360)" to="(710,360)"/>
+ <wire from="(1050,590)" to="(1350,590)"/>
+ <wire from="(660,210)" to="(660,340)"/>
+ <wire from="(710,100)" to="(710,360)"/>
+ <wire from="(760,380)" to="(820,380)"/>
+ <wire from="(1440,540)" to="(1500,540)"/>
+ <wire from="(1050,590)" to="(1050,660)"/>
+ <wire from="(1290,680)" to="(1340,680)"/>
+ <wire from="(1290,780)" to="(1340,780)"/>
+ <wire from="(410,170)" to="(450,170)"/>
+ <wire from="(410,130)" to="(450,130)"/>
+ <wire from="(410,150)" to="(450,150)"/>
+ <wire from="(590,380)" to="(760,380)"/>
+ <wire from="(800,440)" to="(820,440)"/>
+ <wire from="(1350,300)" to="(1620,300)"/>
+ <wire from="(360,690)" to="(390,690)"/>
+ <wire from="(360,710)" to="(390,710)"/>
+ <wire from="(360,730)" to="(390,730)"/>
+ <wire from="(660,340)" to="(820,340)"/>
+ <wire from="(790,400)" to="(820,400)"/>
+ <wire from="(790,420)" to="(820,420)"/>
+ <wire from="(760,260)" to="(760,380)"/>
+ <wire from="(610,690)" to="(680,690)"/>
+ <wire from="(610,710)" to="(680,710)"/>
+ <wire from="(1310,660)" to="(1340,660)"/>
+ <wire from="(1310,740)" to="(1340,740)"/>
+ <wire from="(1310,760)" to="(1340,760)"/>
+ <wire from="(1310,640)" to="(1340,640)"/>
+ <wire from="(1350,300)" to="(1350,590)"/>
+ <wire from="(1640,210)" to="(1670,210)"/>
+ <wire from="(1640,290)" to="(1670,290)"/>
+ <wire from="(1640,150)" to="(1670,150)"/>
+ <wire from="(1640,230)" to="(1670,230)"/>
+ <wire from="(1640,250)" to="(1670,250)"/>
+ <wire from="(1640,170)" to="(1670,170)"/>
+ <wire from="(1640,270)" to="(1670,270)"/>
+ <wire from="(1640,190)" to="(1670,190)"/>
+ <comp lib="0" loc="(1090,340)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="RAM_OUT"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(1090,360)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="WHEEL_RIGHT"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(1090,380)" name="Tunnel">
+ <a name="width" val="8"/>
+ <a name="label" val="WHEEL_LEFT"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(1440,540)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RX"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(1500,540)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="UART_RX_PC"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(340,340)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(340,360)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(990,940)" name="Tunnel">
+ <comp lib="0" loc="(340,380)" name="Tunnel">
<a name="facing" val="east"/>
- <a name="label" val="DATA_WR"/>
- <a name="labelfont" val="SansSerif bold 8"/>
<a name="width" val="8"/>
+ <a name="label" val="RAM_OUT"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(990,980)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 8"/>
+ <comp lib="0" loc="(660,210)" name="Probe">
+ <a name="facing" val="south"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="1" loc="(1280,430)" name="NOT Gate">
- <a name="size" val="20"/>
+ <comp lib="0" loc="(760,260)" name="Probe">
+ <a name="facing" val="south"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="1" loc="(1330,420)" name="AND Gate">
- <a name="size" val="30"/>
+ <comp lib="0" loc="(790,400)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="1" loc="(720,1030)" name="AND Gate">
- <a name="size" val="30"/>
+ <comp lib="0" loc="(790,420)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="2" loc="(1480,1010)" name="Multiplexer">
- <a name="select" val="3"/>
- <a name="width" val="8"/>
+ <comp lib="6" loc="(916,275)" name="Text">
+ <a name="text" val="BAS - 0x42"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="2" loc="(1720,510)" name="Multiplexer">
- <a name="width" val="8"/>
+ <comp lib="6" loc="(920,258)" name="Text">
+ <a name="text" val="HAUT - 0x41"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="2" loc="(740,1030)" name="Demultiplexer">
- <a name="select" val="3"/>
+ <comp lib="6" loc="(926,294)" name="Text">
+ <a name="text" val="DROITE - 0x43"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="4" loc="(1010,1040)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp lib="6" loc="(928,312)" name="Text">
+ <a name="text" val="GAUCHE - 0x44"/>
+ <a name="font" val="SansSerif plain 12"/>
</comp>
- <comp lib="4" loc="(1010,1170)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp loc="(1040,340)" name="CPU_RAM24">
+ <a name="label" val="CPU_RAM"/>
</comp>
- <comp lib="4" loc="(1010,1300)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp loc="(590,340)" name="CPU">
+ <a name="label" val="CPU_1"/>
</comp>
- <comp lib="4" loc="(1010,1430)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp loc="(1290,760)" name="PERI_SIGNED_PWM">
+ <a name="label" val="peri2"/>
</comp>
- <comp lib="4" loc="(1010,520)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp lib="0" loc="(1340,640)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="LED_RIGHT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="4" loc="(1010,650)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp loc="(1290,660)" name="PERI_SIGNED_PWM">
+ <a name="label" val="peri1"/>
</comp>
- <comp lib="4" loc="(1010,780)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp lib="0" loc="(1340,780)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="DIR_WHEEL_LEFT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="4" loc="(1010,910)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
+ <comp lib="0" loc="(1340,760)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="WHEEL_LEFT_PWM"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="6" loc="(1177,802)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="WHEEL_LEFT"/>
+ <comp lib="0" loc="(1340,660)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="WHEEL_RIGHT_PWM"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="6" loc="(1180,671)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="WHEEL_RIGHT"/>
+ <comp lib="0" loc="(1040,660)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="8"/>
+ <a name="label" val="WHEEL_RIGHT"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="6" loc="(1191,543)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="UART BLUETOOTH"/>
+ <comp lib="0" loc="(1040,680)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp loc="(1660,380)" name="CPU_RAM16">
- <a name="label" val="RAM16_PROCESSOR"/>
+ <comp lib="0" loc="(1340,740)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="LED_LEFT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <wire from="(1040,1000)" to="(1040,1010)"/>
- <wire from="(1040,1130)" to="(1040,1140)"/>
- <wire from="(1040,1260)" to="(1040,1270)"/>
- <wire from="(1040,1390)" to="(1040,1400)"/>
- <wire from="(1040,1520)" to="(1040,1530)"/>
- <wire from="(1040,610)" to="(1040,620)"/>
- <wire from="(1040,740)" to="(1040,750)"/>
- <wire from="(1040,870)" to="(1040,880)"/>
- <wire from="(1070,1070)" to="(1340,1070)"/>
- <wire from="(1070,1200)" to="(1350,1200)"/>
- <wire from="(1070,1330)" to="(1360,1330)"/>
- <wire from="(1070,1460)" to="(1370,1460)"/>
- <wire from="(1070,550)" to="(1370,550)"/>
- <wire from="(1070,680)" to="(1360,680)"/>
- <wire from="(1070,810)" to="(1350,810)"/>
- <wire from="(1070,940)" to="(1340,940)"/>
- <wire from="(1240,410)" to="(1300,410)"/>
- <wire from="(1240,430)" to="(1260,430)"/>
- <wire from="(1280,430)" to="(1300,430)"/>
- <wire from="(1330,420)" to="(1440,420)"/>
- <wire from="(1340,1000)" to="(1440,1000)"/>
- <wire from="(1340,1010)" to="(1340,1070)"/>
- <wire from="(1340,1010)" to="(1440,1010)"/>
- <wire from="(1340,940)" to="(1340,1000)"/>
- <wire from="(1350,1020)" to="(1350,1200)"/>
- <wire from="(1350,1020)" to="(1440,1020)"/>
- <wire from="(1350,810)" to="(1350,990)"/>
- <wire from="(1350,810)" to="(1400,810)"/>
- <wire from="(1350,990)" to="(1440,990)"/>
- <wire from="(1360,1030)" to="(1360,1330)"/>
- <wire from="(1360,1030)" to="(1440,1030)"/>
- <wire from="(1360,680)" to="(1360,980)"/>
- <wire from="(1360,680)" to="(1400,680)"/>
- <wire from="(1360,980)" to="(1440,980)"/>
- <wire from="(1370,1040)" to="(1370,1460)"/>
- <wire from="(1370,1040)" to="(1440,1040)"/>
- <wire from="(1370,550)" to="(1370,970)"/>
- <wire from="(1370,970)" to="(1440,970)"/>
- <wire from="(1400,380)" to="(1440,380)"/>
- <wire from="(1400,400)" to="(1440,400)"/>
- <wire from="(1400,440)" to="(1440,440)"/>
- <wire from="(1400,460)" to="(1440,460)"/>
- <wire from="(1440,1200)" to="(1480,1200)"/>
- <wire from="(1460,1050)" to="(1460,1100)"/>
- <wire from="(1460,1100)" to="(1500,1100)"/>
- <wire from="(1480,1010)" to="(1670,1010)"/>
- <wire from="(1500,1100)" to="(1500,1190)"/>
- <wire from="(1660,380)" to="(1670,380)"/>
- <wire from="(1670,380)" to="(1670,500)"/>
- <wire from="(1670,500)" to="(1690,500)"/>
- <wire from="(1670,520)" to="(1670,1010)"/>
- <wire from="(1670,520)" to="(1690,520)"/>
- <wire from="(1700,530)" to="(1700,550)"/>
- <wire from="(1720,510)" to="(1750,510)"/>
- <wire from="(1890,620)" to="(1920,620)"/>
- <wire from="(1890,640)" to="(1920,640)"/>
- <wire from="(420,250)" to="(520,250)"/>
- <wire from="(420,290)" to="(520,290)"/>
- <wire from="(420,310)" to="(520,310)"/>
- <wire from="(420,330)" to="(520,330)"/>
- <wire from="(460,150)" to="(490,150)"/>
- <wire from="(490,230)" to="(520,230)"/>
- <wire from="(510,120)" to="(540,120)"/>
- <wire from="(510,140)" to="(540,140)"/>
- <wire from="(670,1020)" to="(690,1020)"/>
- <wire from="(670,1040)" to="(690,1040)"/>
- <wire from="(670,1110)" to="(710,1110)"/>
- <wire from="(720,1030)" to="(740,1030)"/>
- <wire from="(730,1100)" to="(760,1100)"/>
- <wire from="(760,1070)" to="(760,1100)"/>
- <wire from="(780,1000)" to="(860,1000)"/>
- <wire from="(780,1010)" to="(870,1010)"/>
- <wire from="(780,1020)" to="(880,1020)"/>
- <wire from="(780,1030)" to="(880,1030)"/>
- <wire from="(780,1040)" to="(870,1040)"/>
- <wire from="(780,1050)" to="(860,1050)"/>
- <wire from="(780,1060)" to="(850,1060)"/>
- <wire from="(850,1060)" to="(850,1480)"/>
- <wire from="(850,1480)" to="(1010,1480)"/>
- <wire from="(860,1050)" to="(860,1350)"/>
- <wire from="(860,1350)" to="(1010,1350)"/>
- <wire from="(860,700)" to="(1010,700)"/>
- <wire from="(860,700)" to="(860,1000)"/>
- <wire from="(870,1040)" to="(870,1220)"/>
- <wire from="(870,1220)" to="(1010,1220)"/>
- <wire from="(870,830)" to="(1010,830)"/>
- <wire from="(870,830)" to="(870,1010)"/>
- <wire from="(880,1030)" to="(880,1090)"/>
- <wire from="(880,1090)" to="(1010,1090)"/>
- <wire from="(880,960)" to="(1010,960)"/>
- <wire from="(880,960)" to="(880,1020)"/>
- <wire from="(980,570)" to="(1010,570)"/>
- <wire from="(990,1010)" to="(1040,1010)"/>
- <wire from="(990,1070)" to="(1010,1070)"/>
- <wire from="(990,1110)" to="(1010,1110)"/>
- <wire from="(990,1140)" to="(1040,1140)"/>
- <wire from="(990,1200)" to="(1010,1200)"/>
- <wire from="(990,1240)" to="(1010,1240)"/>
- <wire from="(990,1270)" to="(1040,1270)"/>
- <wire from="(990,1330)" to="(1010,1330)"/>
- <wire from="(990,1370)" to="(1010,1370)"/>
- <wire from="(990,1400)" to="(1040,1400)"/>
- <wire from="(990,1460)" to="(1010,1460)"/>
- <wire from="(990,1500)" to="(1010,1500)"/>
- <wire from="(990,1530)" to="(1040,1530)"/>
- <wire from="(990,550)" to="(1010,550)"/>
- <wire from="(990,590)" to="(1010,590)"/>
- <wire from="(990,620)" to="(1040,620)"/>
- <wire from="(990,680)" to="(1010,680)"/>
- <wire from="(990,720)" to="(1010,720)"/>
- <wire from="(990,750)" to="(1040,750)"/>
- <wire from="(990,810)" to="(1010,810)"/>
- <wire from="(990,850)" to="(1010,850)"/>
- <wire from="(990,880)" to="(1040,880)"/>
- <wire from="(990,940)" to="(1010,940)"/>
- <wire from="(990,980)" to="(1010,980)"/>
- </circuit>
- <circuit name="TOP">
- <a name="appearance" val="logisim_evolution"/>
- <a name="circuit" val="TOP"/>
- <a name="circuitnamedboxfixedsize" val="true"/>
- <a name="simulationFrequency" val="1.0"/>
- <comp lib="0" loc="(1090,340)" name="Tunnel">
- <a name="label" val="RAM_OUT"/>
+ <comp lib="0" loc="(1040,780)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
<a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
</comp>
- <comp lib="0" loc="(1090,360)" name="Tunnel">
- <a name="label" val="WHEEL_RIGHT"/>
- <a name="labelfont" val="SansSerif bold 10"/>
+ <comp lib="0" loc="(1040,760)" name="Tunnel">
+ <a name="facing" val="east"/>
<a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(1090,380)" name="Tunnel">
<a name="label" val="WHEEL_LEFT"/>
<a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
</comp>
- <comp lib="0" loc="(1100,660)" name="Pin">
- <a name="appearance" val="NewPins"/>
+ <comp lib="0" loc="(1340,680)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="WHEEL_RIGHT_PWM"/>
<a name="output" val="true"/>
+ <a name="label" val="DIR_WHEEL_RIGHT"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(650,730)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(360,730)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RX"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="0" loc="(360,690)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="RESET"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
+ </comp>
+ <comp lib="4" loc="(680,660)" name="Register"/>
+ <comp lib="0" loc="(360,710)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="label" val="CLK"/>
+ <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(1100,680)" name="Pin">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="DIR_WHEEL_RIGHT"/>
- <a name="output" val="true"/>
+ <comp loc="(610,690)" name="PERI_UART_RCVE_9600">
+ <a name="label" val="UART1"/>
</comp>
- <comp lib="0" loc="(1100,760)" name="Pin">
- <a name="appearance" val="NewPins"/>
+ <comp lib="0" loc="(1670,360)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="WHEEL_LEFT_PWM"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1100,780)" name="Pin">
+ <a name="label" val="LED_1"/>
<a name="appearance" val="NewPins"/>
- <a name="facing" val="west"/>
- <a name="label" val="DIR_WHEEL_LEFT"/>
- <a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1440,540)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RX"/>
- <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(1460,500)" name="Splitter">
+ <comp lib="0" loc="(1630,490)" name="Splitter">
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
<a name="spacing" val="2"/>
</comp>
- <comp lib="0" loc="(1500,350)" name="Pin">
- <a name="appearance" val="NewPins"/>
+ <comp lib="0" loc="(1670,440)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_0"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1500,370)" name="Pin">
+ <a name="label" val="LED_5"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,340)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_1"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1500,390)" name="Pin">
+ <a name="label" val="LED_0"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,420)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_2"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1500,410)" name="Pin">
+ <a name="label" val="LED_4"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,460)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_3"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1500,430)" name="Pin">
+ <a name="label" val="LED_6"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,400)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_4"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1500,450)" name="Pin">
+ <a name="label" val="LED_3"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,380)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_5"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1500,470)" name="Pin">
+ <a name="label" val="LED_2"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,480)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_6"/>
<a name="output" val="true"/>
- </comp>
- <comp lib="0" loc="(1500,490)" name="Pin">
+ <a name="label" val="LED_7"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,230)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="LED_7"/>
<a name="output" val="true"/>
+ <a name="label" val="PWM4"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(1500,540)" name="Pin">
+ <comp lib="0" loc="(1670,150)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="PWM0"/>
<a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1670,270)" name="Pin">
<a name="facing" val="west"/>
- <a name="label" val="UART_RX_PC"/>
<a name="output" val="true"/>
+ <a name="label" val="PWM6"/>
+ <a name="appearance" val="NewPins"/>
+ </comp>
+ <comp lib="0" loc="(1620,300)" name="Splitter">
+ <a name="fanout" val="8"/>
+ <a name="incoming" val="8"/>
+ <a name="spacing" val="2"/>
</comp>
- <comp lib="0" loc="(270,110)" name="Pin">
+ <comp lib="0" loc="(1670,210)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="PWM3"/>
<a name="appearance" val="NewPins"/>
- <a name="label" val="CLK"/>
</comp>
- <comp lib="0" loc="(270,130)" name="Pin">
+ <comp lib="0" loc="(1670,290)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="PWM7"/>
<a name="appearance" val="NewPins"/>
- <a name="label" val="RESET"/>
</comp>
- <comp lib="0" loc="(270,150)" name="Pin">
+ <comp lib="0" loc="(1670,250)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="PWM5"/>
<a name="appearance" val="NewPins"/>
- <a name="label" val="RX"/>
</comp>
- <comp lib="0" loc="(310,110)" name="Tunnel">
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 10"/>
+ <comp lib="0" loc="(1670,170)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="PWM1"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(310,130)" name="Tunnel">
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 10"/>
+ <comp lib="0" loc="(1670,190)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="label" val="PWM2"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(310,150)" name="Tunnel">
- <a name="label" val="RX"/>
- <a name="labelfont" val="SansSerif bold 10"/>
+ <comp lib="0" loc="(710,100)" name="Probe">
+ <a name="facing" val="south"/>
+ <a name="radix" val="10signed"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(340,340)" name="Tunnel">
- <a name="facing" val="east"/>
+ <comp lib="0" loc="(410,130)" name="Pin">
<a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- </comp>
- <comp lib="0" loc="(340,360)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- </comp>
- <comp lib="0" loc="(340,380)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RAM_OUT"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(340,500)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="RESET"/>
- <a name="labelfont" val="SansSerif bold 10"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp lib="0" loc="(340,520)" name="Tunnel">
- <a name="facing" val="east"/>
+ <comp lib="0" loc="(450,130)" name="Tunnel">
<a name="label" val="CLK"/>
<a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(340,540)" name="Tunnel">
- <a name="facing" val="east"/>
+ <comp lib="0" loc="(450,170)" name="Tunnel">
<a name="label" val="RX"/>
<a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(630,540)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- </comp>
- <comp lib="0" loc="(660,210)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- </comp>
- <comp lib="0" loc="(710,230)" name="Probe">
- <a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- </comp>
- <comp lib="0" loc="(760,260)" name="Probe">
+ <comp lib="0" loc="(410,170)" name="Pin">
+ <a name="label" val="RX"/>
<a name="appearance" val="NewPins"/>
- <a name="facing" val="south"/>
- </comp>
- <comp lib="0" loc="(790,400)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(790,420)" name="Tunnel">
- <a name="facing" val="east"/>
+ <comp lib="0" loc="(450,150)" name="Tunnel">
<a name="label" val="RESET"/>
<a name="labelfont" val="SansSerif bold 10"/>
</comp>
- <comp lib="0" loc="(800,660)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="WHEEL_RIGHT"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(800,680)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- </comp>
- <comp lib="0" loc="(800,760)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="WHEEL_LEFT"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- <a name="width" val="8"/>
- </comp>
- <comp lib="0" loc="(800,780)" name="Tunnel">
- <a name="facing" val="east"/>
- <a name="label" val="CLK"/>
- <a name="labelfont" val="SansSerif bold 10"/>
- </comp>
- <comp lib="4" loc="(660,470)" name="Register">
- <a name="appearance" val="logisim_evolution"/>
- </comp>
- <comp lib="6" loc="(916,275)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="BAS - 0x42"/>
- </comp>
- <comp lib="6" loc="(920,258)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="HAUT - 0x41"/>
- </comp>
- <comp lib="6" loc="(926,294)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="DROITE - 0x43"/>
- </comp>
- <comp lib="6" loc="(928,312)" name="Text">
- <a name="font" val="SansSerif plain 12"/>
- <a name="text" val="GAUCHE - 0x44"/>
- </comp>
- <comp loc="(1040,340)" name="CPU_RAM24">
- <a name="label" val="CPU_RAM"/>
- </comp>
- <comp loc="(1050,660)" name="PERI_SIGNED_PWM">
- <a name="label" val="peri1"/>
- </comp>
- <comp loc="(1050,760)" name="PERI_SIGNED_PWM">
- <a name="label" val="peri2"/>
- </comp>
- <comp loc="(590,340)" name="CPU">
- <a name="label" val="CPU_1"/>
+ <comp lib="0" loc="(410,150)" name="Pin">
+ <a name="label" val="RESET"/>
+ <a name="appearance" val="NewPins"/>
</comp>
- <comp loc="(590,500)" name="PERI_UART_RCVE_9600"/>
- <wire from="(1040,340)" to="(1090,340)"/>
- <wire from="(1040,360)" to="(1090,360)"/>
- <wire from="(1040,380)" to="(1090,380)"/>
- <wire from="(1050,660)" to="(1100,660)"/>
- <wire from="(1050,680)" to="(1100,680)"/>
- <wire from="(1050,760)" to="(1100,760)"/>
- <wire from="(1050,780)" to="(1100,780)"/>
- <wire from="(1440,540)" to="(1500,540)"/>
- <wire from="(1480,350)" to="(1500,350)"/>
- <wire from="(1480,370)" to="(1500,370)"/>
- <wire from="(1480,390)" to="(1500,390)"/>
- <wire from="(1480,410)" to="(1500,410)"/>
- <wire from="(1480,430)" to="(1500,430)"/>
- <wire from="(1480,450)" to="(1500,450)"/>
- <wire from="(1480,470)" to="(1500,470)"/>
- <wire from="(1480,490)" to="(1500,490)"/>
- <wire from="(270,110)" to="(310,110)"/>
- <wire from="(270,130)" to="(310,130)"/>
- <wire from="(270,150)" to="(310,150)"/>
- <wire from="(340,340)" to="(370,340)"/>
- <wire from="(340,360)" to="(370,360)"/>
- <wire from="(340,380)" to="(370,380)"/>
- <wire from="(340,500)" to="(370,500)"/>
- <wire from="(340,520)" to="(370,520)"/>
- <wire from="(340,540)" to="(370,540)"/>
- <wire from="(590,340)" to="(660,340)"/>
- <wire from="(590,360)" to="(820,360)"/>
- <wire from="(590,380)" to="(760,380)"/>
- <wire from="(590,500)" to="(660,500)"/>
- <wire from="(590,520)" to="(660,520)"/>
- <wire from="(630,540)" to="(660,540)"/>
- <wire from="(660,210)" to="(660,340)"/>
- <wire from="(660,340)" to="(710,340)"/>
- <wire from="(710,230)" to="(710,340)"/>
- <wire from="(710,340)" to="(820,340)"/>
- <wire from="(720,500)" to="(800,500)"/>
- <wire from="(760,260)" to="(760,380)"/>
- <wire from="(760,380)" to="(820,380)"/>
- <wire from="(790,400)" to="(820,400)"/>
- <wire from="(790,420)" to="(820,420)"/>
- <wire from="(800,440)" to="(800,500)"/>
- <wire from="(800,440)" to="(820,440)"/>
- <wire from="(800,500)" to="(1460,500)"/>
- <wire from="(800,660)" to="(830,660)"/>
- <wire from="(800,680)" to="(830,680)"/>
- <wire from="(800,760)" to="(830,760)"/>
- <wire from="(800,780)" to="(830,780)"/>
</circuit>
<circuit name="PERI_UART_RCV_16_BITS_9600">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="PERI_UART_RCV_16_BITS_9600"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
- <a name="simulationFrequency" val="1.0"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(1090,880)" to="(1090,960)"/>
+ <wire from="(520,920)" to="(520,930)"/>
+ <wire from="(510,220)" to="(570,220)"/>
+ <wire from="(620,200)" to="(620,210)"/>
+ <wire from="(420,270)" to="(420,720)"/>
+ <wire from="(1200,400)" to="(1200,420)"/>
+ <wire from="(1200,460)" to="(1200,480)"/>
+ <wire from="(420,160)" to="(1060,160)"/>
+ <wire from="(1260,380)" to="(1260,400)"/>
+ <wire from="(1210,470)" to="(1210,500)"/>
+ <wire from="(440,780)" to="(560,780)"/>
+ <wire from="(520,930)" to="(560,930)"/>
+ <wire from="(1020,740)" to="(1020,770)"/>
+ <wire from="(510,190)" to="(1060,190)"/>
+ <wire from="(780,880)" to="(780,910)"/>
+ <wire from="(760,970)" to="(800,970)"/>
+ <wire from="(700,200)" to="(700,230)"/>
+ <wire from="(780,790)" to="(820,790)"/>
+ <wire from="(790,740)" to="(1020,740)"/>
+ <wire from="(790,740)" to="(790,830)"/>
+ <wire from="(1190,450)" to="(1190,460)"/>
+ <wire from="(790,830)" to="(790,850)"/>
+ <wire from="(800,880)" to="(800,900)"/>
+ <wire from="(1140,970)" to="(1580,970)"/>
+ <wire from="(510,190)" to="(510,220)"/>
+ <wire from="(1190,430)" to="(1240,430)"/>
+ <wire from="(1190,450)" to="(1240,450)"/>
+ <wire from="(1180,420)" to="(1190,420)"/>
+ <wire from="(1180,460)" to="(1190,460)"/>
+ <wire from="(1030,890)" to="(1040,890)"/>
+ <wire from="(1080,880)" to="(1090,880)"/>
+ <wire from="(700,230)" to="(720,230)"/>
+ <wire from="(760,910)" to="(780,910)"/>
+ <wire from="(580,240)" to="(610,240)"/>
+ <wire from="(1010,870)" to="(1040,870)"/>
+ <wire from="(790,830)" to="(820,830)"/>
+ <wire from="(1180,380)" to="(1210,380)"/>
+ <wire from="(1180,500)" to="(1210,500)"/>
+ <wire from="(1210,410)" to="(1240,410)"/>
+ <wire from="(1210,470)" to="(1240,470)"/>
+ <wire from="(180,190)" to="(510,190)"/>
+ <wire from="(620,200)" to="(700,200)"/>
+ <wire from="(1220,480)" to="(1220,520)"/>
+ <wire from="(810,810)" to="(820,810)"/>
+ <wire from="(1120,680)" to="(1270,680)"/>
+ <wire from="(1090,960)" to="(1110,960)"/>
+ <wire from="(1100,790)" to="(1120,790)"/>
+ <wire from="(180,130)" to="(440,130)"/>
+ <wire from="(540,240)" to="(550,240)"/>
+ <wire from="(550,890)" to="(560,890)"/>
+ <wire from="(670,280)" to="(670,780)"/>
+ <wire from="(790,150)" to="(1060,150)"/>
+ <wire from="(600,220)" to="(610,220)"/>
+ <wire from="(840,980)" to="(1110,980)"/>
+ <wire from="(560,910)" to="(560,920)"/>
+ <wire from="(790,150)" to="(790,740)"/>
+ <wire from="(780,790)" to="(780,800)"/>
+ <wire from="(1180,520)" to="(1220,520)"/>
+ <wire from="(1200,420)" to="(1240,420)"/>
+ <wire from="(1200,460)" to="(1240,460)"/>
+ <wire from="(1210,380)" to="(1210,410)"/>
+ <wire from="(440,130)" to="(440,780)"/>
+ <wire from="(440,130)" to="(1060,130)"/>
+ <wire from="(770,140)" to="(1060,140)"/>
+ <wire from="(1180,440)" to="(1240,440)"/>
+ <wire from="(1010,810)" to="(1050,810)"/>
+ <wire from="(1190,420)" to="(1190,430)"/>
+ <wire from="(790,900)" to="(790,920)"/>
+ <wire from="(560,780)" to="(670,780)"/>
+ <wire from="(670,780)" to="(820,780)"/>
+ <wire from="(420,270)" to="(640,270)"/>
+ <wire from="(420,840)" to="(420,940)"/>
+ <wire from="(1120,790)" to="(1120,840)"/>
+ <wire from="(540,920)" to="(560,920)"/>
+ <wire from="(420,160)" to="(420,270)"/>
+ <wire from="(420,720)" to="(1270,720)"/>
+ <wire from="(560,780)" to="(560,880)"/>
+ <wire from="(1020,770)" to="(1050,770)"/>
+ <wire from="(1120,840)" to="(1570,840)"/>
+ <wire from="(150,160)" to="(420,160)"/>
+ <wire from="(1260,380)" to="(1610,380)"/>
+ <wire from="(420,940)" to="(560,940)"/>
+ <wire from="(420,840)" to="(820,840)"/>
+ <wire from="(1330,680)" to="(1670,680)"/>
+ <wire from="(770,800)" to="(780,800)"/>
+ <wire from="(790,900)" to="(800,900)"/>
+ <wire from="(1180,400)" to="(1200,400)"/>
+ <wire from="(1180,480)" to="(1200,480)"/>
+ <wire from="(1220,480)" to="(1240,480)"/>
+ <wire from="(420,720)" to="(420,840)"/>
+ <wire from="(510,920)" to="(520,920)"/>
+ <wire from="(1120,680)" to="(1120,790)"/>
<comp lib="0" loc="(1030,890)" name="Constant">
- <a name="value" val="0x0"/>
<a name="width" val="5"/>
+ <a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(1260,400)" name="Splitter">
+ <a name="facing" val="west"/>
+ <a name="fanout" val="8"/>
+ <a name="incoming" val="8"/>
<a name="bit0" val="7"/>
<a name="bit1" val="6"/>
<a name="bit2" val="5"/>
@@ -3952,12 +4347,8 @@
<a name="bit5" val="2"/>
<a name="bit6" val="1"/>
<a name="bit7" val="0"/>
- <a name="facing" val="west"/>
- <a name="fanout" val="8"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(150,160)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="label" val="CLK"/>
</comp>
<comp lib="0" loc="(1570,840)" name="Tunnel">
@@ -3967,29 +4358,25 @@
<a name="label" val="half"/>
</comp>
<comp lib="0" loc="(1610,380)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="facing" val="west"/>
- <a name="label" val="DATA"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA"/>
</comp>
<comp lib="0" loc="(1670,680)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="facing" val="west"/>
- <a name="label" val="DONE"/>
<a name="output" val="true"/>
+ <a name="label" val="DONE"/>
</comp>
<comp lib="0" loc="(180,130)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="label" val="RESET"/>
</comp>
<comp lib="0" loc="(180,190)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="label" val="RX"/>
</comp>
<comp lib="0" loc="(390,1060)" name="Constant">
- <a name="value" val="0x28aa"/>
<a name="width" val="16"/>
+ <a name="value" val="0x28aa"/>
</comp>
<comp lib="0" loc="(510,920)" name="Tunnel">
<a name="facing" val="east"/>
@@ -4005,8 +4392,8 @@
<a name="label" val="half"/>
</comp>
<comp lib="0" loc="(560,970)" name="Constant">
- <a name="value" val="0x0"/>
<a name="width" val="16"/>
+ <a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(720,230)" name="Tunnel">
<a name="label" val="state"/>
@@ -4021,13 +4408,13 @@
<a name="label" val="half"/>
</comp>
<comp lib="0" loc="(800,990)" name="Constant">
- <a name="value" val="0x1455"/>
<a name="width" val="16"/>
+ <a name="value" val="0x1455"/>
</comp>
<comp lib="0" loc="(810,810)" name="Power"/>
<comp lib="0" loc="(820,870)" name="Constant">
- <a name="value" val="0x0"/>
<a name="width" val="5"/>
+ <a name="value" val="0x0"/>
</comp>
<comp lib="1" loc="(1100,790)" name="AND Gate"/>
<comp lib="1" loc="(1140,970)" name="AND Gate">
@@ -4040,7 +4427,6 @@
<a name="size" val="30"/>
</comp>
<comp lib="2" loc="(640,230)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="selloc" val="tr"/>
</comp>
<comp lib="3" loc="(1080,880)" name="Comparator">
@@ -4050,141 +4436,81 @@
<a name="width" val="16"/>
</comp>
<comp lib="4" loc="(1060,110)" name="Shift Register">
- <a name="appearance" val="logisim_evolution"/>
<a name="length" val="17"/>
+ <a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(1280,670)" name="D Flip-Flop">
<a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(560,860)" name="Counter">
- <a name="appearance" val="logisim_evolution"/>
- <a name="max" val="0x28aa"/>
<a name="width" val="16"/>
+ <a name="max" val="0x28aa"/>
+ <a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(650,220)" name="D Flip-Flop">
<a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(820,760)" name="Counter">
- <a name="appearance" val="logisim_evolution"/>
- <a name="max" val="0x11"/>
<a name="width" val="5"/>
+ <a name="max" val="0x11"/>
+ <a name="appearance" val="logisim_evolution"/>
</comp>
- <wire from="(1010,810)" to="(1050,810)"/>
- <wire from="(1010,870)" to="(1040,870)"/>
- <wire from="(1020,740)" to="(1020,770)"/>
- <wire from="(1020,770)" to="(1050,770)"/>
- <wire from="(1030,890)" to="(1040,890)"/>
- <wire from="(1080,880)" to="(1090,880)"/>
- <wire from="(1090,880)" to="(1090,960)"/>
- <wire from="(1090,960)" to="(1110,960)"/>
- <wire from="(1100,790)" to="(1120,790)"/>
- <wire from="(1120,680)" to="(1120,790)"/>
- <wire from="(1120,680)" to="(1270,680)"/>
- <wire from="(1120,790)" to="(1120,840)"/>
- <wire from="(1120,840)" to="(1570,840)"/>
- <wire from="(1140,970)" to="(1580,970)"/>
- <wire from="(1180,380)" to="(1210,380)"/>
- <wire from="(1180,400)" to="(1200,400)"/>
- <wire from="(1180,420)" to="(1190,420)"/>
- <wire from="(1180,440)" to="(1240,440)"/>
- <wire from="(1180,460)" to="(1190,460)"/>
- <wire from="(1180,480)" to="(1200,480)"/>
- <wire from="(1180,500)" to="(1210,500)"/>
- <wire from="(1180,520)" to="(1220,520)"/>
- <wire from="(1190,420)" to="(1190,430)"/>
- <wire from="(1190,430)" to="(1240,430)"/>
- <wire from="(1190,450)" to="(1190,460)"/>
- <wire from="(1190,450)" to="(1240,450)"/>
- <wire from="(1200,400)" to="(1200,420)"/>
- <wire from="(1200,420)" to="(1240,420)"/>
- <wire from="(1200,460)" to="(1200,480)"/>
- <wire from="(1200,460)" to="(1240,460)"/>
- <wire from="(1210,380)" to="(1210,410)"/>
- <wire from="(1210,410)" to="(1240,410)"/>
- <wire from="(1210,470)" to="(1210,500)"/>
- <wire from="(1210,470)" to="(1240,470)"/>
- <wire from="(1220,480)" to="(1220,520)"/>
- <wire from="(1220,480)" to="(1240,480)"/>
- <wire from="(1260,380)" to="(1260,400)"/>
- <wire from="(1260,380)" to="(1610,380)"/>
- <wire from="(1330,680)" to="(1670,680)"/>
- <wire from="(150,160)" to="(420,160)"/>
- <wire from="(180,130)" to="(440,130)"/>
- <wire from="(180,190)" to="(510,190)"/>
- <wire from="(420,160)" to="(1060,160)"/>
- <wire from="(420,160)" to="(420,270)"/>
- <wire from="(420,270)" to="(420,720)"/>
- <wire from="(420,270)" to="(640,270)"/>
- <wire from="(420,720)" to="(1270,720)"/>
- <wire from="(420,720)" to="(420,840)"/>
- <wire from="(420,840)" to="(420,940)"/>
- <wire from="(420,840)" to="(820,840)"/>
- <wire from="(420,940)" to="(560,940)"/>
- <wire from="(440,130)" to="(1060,130)"/>
- <wire from="(440,130)" to="(440,780)"/>
- <wire from="(440,780)" to="(560,780)"/>
- <wire from="(510,190)" to="(1060,190)"/>
- <wire from="(510,190)" to="(510,220)"/>
- <wire from="(510,220)" to="(570,220)"/>
- <wire from="(510,920)" to="(520,920)"/>
- <wire from="(520,920)" to="(520,930)"/>
- <wire from="(520,930)" to="(560,930)"/>
- <wire from="(540,240)" to="(550,240)"/>
- <wire from="(540,920)" to="(560,920)"/>
- <wire from="(550,890)" to="(560,890)"/>
- <wire from="(560,780)" to="(560,880)"/>
- <wire from="(560,780)" to="(670,780)"/>
- <wire from="(560,910)" to="(560,920)"/>
- <wire from="(580,240)" to="(610,240)"/>
- <wire from="(600,220)" to="(610,220)"/>
- <wire from="(620,200)" to="(620,210)"/>
- <wire from="(620,200)" to="(700,200)"/>
- <wire from="(670,280)" to="(670,780)"/>
- <wire from="(670,780)" to="(820,780)"/>
- <wire from="(700,200)" to="(700,230)"/>
- <wire from="(700,230)" to="(720,230)"/>
- <wire from="(760,910)" to="(780,910)"/>
- <wire from="(760,970)" to="(800,970)"/>
- <wire from="(770,140)" to="(1060,140)"/>
- <wire from="(770,800)" to="(780,800)"/>
- <wire from="(780,790)" to="(780,800)"/>
- <wire from="(780,790)" to="(820,790)"/>
- <wire from="(780,880)" to="(780,910)"/>
- <wire from="(790,150)" to="(1060,150)"/>
- <wire from="(790,150)" to="(790,740)"/>
- <wire from="(790,740)" to="(1020,740)"/>
- <wire from="(790,740)" to="(790,830)"/>
- <wire from="(790,830)" to="(790,850)"/>
- <wire from="(790,830)" to="(820,830)"/>
- <wire from="(790,900)" to="(790,920)"/>
- <wire from="(790,900)" to="(800,900)"/>
- <wire from="(800,880)" to="(800,900)"/>
- <wire from="(810,810)" to="(820,810)"/>
- <wire from="(840,980)" to="(1110,980)"/>
</circuit>
<circuit name="PERI_SIGNED_PWM">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="PERI_SIGNED_PWM"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(730,270)" to="(780,270)"/>
+ <wire from="(940,310)" to="(940,380)"/>
+ <wire from="(710,290)" to="(710,380)"/>
+ <wire from="(710,380)" to="(940,380)"/>
+ <wire from="(880,270)" to="(980,270)"/>
+ <wire from="(550,320)" to="(550,350)"/>
+ <wire from="(940,290)" to="(980,290)"/>
+ <wire from="(940,310)" to="(980,310)"/>
+ <wire from="(790,230)" to="(790,250)"/>
+ <wire from="(810,230)" to="(810,250)"/>
+ <wire from="(470,260)" to="(700,260)"/>
+ <wire from="(430,260)" to="(470,260)"/>
+ <wire from="(490,370)" to="(530,370)"/>
+ <wire from="(470,260)" to="(470,360)"/>
+ <wire from="(490,380)" to="(710,380)"/>
+ <wire from="(600,340)" to="(620,340)"/>
+ <wire from="(660,330)" to="(680,330)"/>
+ <wire from="(680,280)" to="(700,280)"/>
+ <wire from="(590,320)" to="(620,320)"/>
+ <wire from="(1200,270)" to="(1230,270)"/>
+ <wire from="(1200,290)" to="(1230,290)"/>
+ <wire from="(880,210)" to="(880,270)"/>
+ <wire from="(810,210)" to="(880,210)"/>
+ <wire from="(680,280)" to="(680,330)"/>
+ <wire from="(800,230)" to="(810,230)"/>
+ <wire from="(520,360)" to="(530,360)"/>
+ <wire from="(550,320)" to="(560,320)"/>
<comp lib="0" loc="(1230,270)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="PWM_OUT"/>
<a name="output" val="true"/>
+ <a name="label" val="PWM_OUT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(1230,290)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="DIR_OUT"/>
<a name="output" val="true"/>
+ <a name="label" val="DIR_OUT"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(430,260)" name="Pin">
- <a name="appearance" val="NewPins"/>
+ <a name="width" val="8"/>
<a name="label" val="SPEED_IN"/>
<a name="radix" val="10signed"/>
- <a name="width" val="8"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(470,360)" name="Splitter">
+ <a name="incoming" val="8"/>
<a name="appear" val="right"/>
<a name="bit1" val="0"/>
<a name="bit2" val="0"/>
@@ -4193,12 +4519,13 @@
<a name="bit5" val="0"/>
<a name="bit6" val="0"/>
<a name="bit7" val="1"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(520,360)" name="Constant">
<a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(550,350)" name="Splitter">
+ <a name="facing" val="west"/>
+ <a name="incoming" val="8"/>
<a name="bit0" val="1"/>
<a name="bit2" val="1"/>
<a name="bit3" val="1"/>
@@ -4206,13 +4533,14 @@
<a name="bit5" val="1"/>
<a name="bit6" val="1"/>
<a name="bit7" val="0"/>
- <a name="facing" val="west"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(600,340)" name="Constant">
<a name="width" val="8"/>
</comp>
<comp lib="0" loc="(780,270)" name="Splitter">
+ <a name="facing" val="north"/>
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="8"/>
<a name="appear" val="right"/>
<a name="bit1" val="0"/>
<a name="bit2" val="0"/>
@@ -4221,11 +4549,10 @@
<a name="bit5" val="0"/>
<a name="bit6" val="0"/>
<a name="bit7" val="none"/>
- <a name="facing" val="north"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(810,210)" name="Splitter">
+ <a name="facing" val="south"/>
+ <a name="incoming" val="8"/>
<a name="appear" val="right"/>
<a name="bit2" val="1"/>
<a name="bit3" val="1"/>
@@ -4233,16 +4560,14 @@
<a name="bit5" val="1"/>
<a name="bit6" val="1"/>
<a name="bit7" val="1"/>
- <a name="facing" val="south"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(810,250)" name="Constant">
<a name="facing" val="north"/>
<a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(940,290)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="1" loc="(590,320)" name="NOT Gate">
<a name="width" val="8"/>
@@ -4254,57 +4579,50 @@
<comp loc="(1200,270)" name="PERI_PWM">
<a name="label" val="PERI"/>
</comp>
- <wire from="(1200,270)" to="(1230,270)"/>
- <wire from="(1200,290)" to="(1230,290)"/>
- <wire from="(430,260)" to="(470,260)"/>
- <wire from="(470,260)" to="(470,360)"/>
- <wire from="(470,260)" to="(700,260)"/>
- <wire from="(490,370)" to="(530,370)"/>
- <wire from="(490,380)" to="(710,380)"/>
- <wire from="(520,360)" to="(530,360)"/>
- <wire from="(550,320)" to="(550,350)"/>
- <wire from="(550,320)" to="(560,320)"/>
- <wire from="(590,320)" to="(620,320)"/>
- <wire from="(600,340)" to="(620,340)"/>
- <wire from="(660,330)" to="(680,330)"/>
- <wire from="(680,280)" to="(680,330)"/>
- <wire from="(680,280)" to="(700,280)"/>
- <wire from="(710,290)" to="(710,380)"/>
- <wire from="(710,380)" to="(940,380)"/>
- <wire from="(730,270)" to="(780,270)"/>
- <wire from="(790,230)" to="(790,250)"/>
- <wire from="(800,230)" to="(810,230)"/>
- <wire from="(810,210)" to="(880,210)"/>
- <wire from="(810,230)" to="(810,250)"/>
- <wire from="(880,210)" to="(880,270)"/>
- <wire from="(880,270)" to="(980,270)"/>
- <wire from="(940,290)" to="(980,290)"/>
- <wire from="(940,310)" to="(940,380)"/>
- <wire from="(940,310)" to="(980,310)"/>
</circuit>
<circuit name="PERI_PWM">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="PERI_PWM"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(610,390)" to="(760,390)"/>
+ <wire from="(610,440)" to="(1110,440)"/>
+ <wire from="(630,330)" to="(650,330)"/>
+ <wire from="(630,350)" to="(650,350)"/>
+ <wire from="(780,340)" to="(830,340)"/>
+ <wire from="(720,350)" to="(750,350)"/>
+ <wire from="(850,350)" to="(1010,350)"/>
+ <wire from="(980,370)" to="(1010,370)"/>
+ <wire from="(690,340)" to="(750,340)"/>
+ <wire from="(830,280)" to="(830,340)"/>
+ <wire from="(630,280)" to="(830,280)"/>
+ <wire from="(1050,370)" to="(1110,370)"/>
+ <wire from="(760,360)" to="(760,390)"/>
+ <wire from="(770,360)" to="(770,410)"/>
+ <wire from="(630,280)" to="(630,330)"/>
+ <wire from="(760,410)" to="(770,410)"/>
<comp lib="0" loc="(1110,370)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="SIG"/>
<a name="output" val="true"/>
+ <a name="label" val="SIG"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(1110,440)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
- <a name="label" val="DIR"/>
<a name="output" val="true"/>
+ <a name="label" val="DIR"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(610,390)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(610,440)" name="Pin">
- <a name="appearance" val="NewPins"/>
<a name="label" val="DIR_IN"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(630,350)" name="Constant">
<a name="width" val="10"/>
@@ -4314,6 +4632,8 @@
<a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(830,340)" name="Splitter">
+ <a name="fanout" val="1"/>
+ <a name="incoming" val="10"/>
<a name="appear" val="right"/>
<a name="bit0" val="none"/>
<a name="bit1" val="none"/>
@@ -4325,14 +4645,12 @@
<a name="bit7" val="0"/>
<a name="bit8" val="0"/>
<a name="bit9" val="0"/>
- <a name="fanout" val="1"/>
- <a name="incoming" val="10"/>
</comp>
<comp lib="0" loc="(980,370)" name="Pin">
- <a name="appearance" val="NewPins"/>
+ <a name="width" val="8"/>
<a name="label" val="speed"/>
<a name="radix" val="10unsigned"/>
- <a name="width" val="8"/>
+ <a name="appearance" val="NewPins"/>
</comp>
<comp lib="3" loc="(1050,360)" name="Comparator">
<a name="mode" val="unsigned"/>
@@ -4341,59 +4659,132 @@
<a name="width" val="10"/>
</comp>
<comp lib="4" loc="(780,340)" name="Register">
- <a name="appearance" val="classic"/>
<a name="width" val="10"/>
+ <a name="appearance" val="classic"/>
</comp>
- <wire from="(1050,370)" to="(1110,370)"/>
- <wire from="(610,390)" to="(760,390)"/>
- <wire from="(610,440)" to="(1110,440)"/>
- <wire from="(630,280)" to="(630,330)"/>
- <wire from="(630,280)" to="(830,280)"/>
- <wire from="(630,330)" to="(650,330)"/>
- <wire from="(630,350)" to="(650,350)"/>
- <wire from="(690,340)" to="(750,340)"/>
- <wire from="(720,350)" to="(750,350)"/>
- <wire from="(760,360)" to="(760,390)"/>
- <wire from="(760,410)" to="(770,410)"/>
- <wire from="(770,360)" to="(770,410)"/>
- <wire from="(780,340)" to="(830,340)"/>
- <wire from="(830,280)" to="(830,340)"/>
- <wire from="(850,350)" to="(1010,350)"/>
- <wire from="(980,370)" to="(1010,370)"/>
</circuit>
<circuit name="PERI_UART_RCVE_9600">
- <a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="PERI_UART_RCVE_9600"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif bold 16"/>
+ <a name="appearance" val="logisim_evolution"/>
<a name="circuitnamedboxfixedsize" val="true"/>
- <a name="simulationFrequency" val="1.0"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(1060,530)" to="(1060,610)"/>
+ <wire from="(480,210)" to="(540,210)"/>
+ <wire from="(590,190)" to="(590,200)"/>
+ <wire from="(910,250)" to="(910,260)"/>
+ <wire from="(410,120)" to="(780,120)"/>
+ <wire from="(900,270)" to="(960,270)"/>
+ <wire from="(490,570)" to="(490,580)"/>
+ <wire from="(410,430)" to="(530,430)"/>
+ <wire from="(930,210)" to="(930,240)"/>
+ <wire from="(760,390)" to="(760,480)"/>
+ <wire from="(760,390)" to="(990,390)"/>
+ <wire from="(990,390)" to="(990,420)"/>
+ <wire from="(730,620)" to="(770,620)"/>
+ <wire from="(740,130)" to="(780,130)"/>
+ <wire from="(750,440)" to="(790,440)"/>
+ <wire from="(670,190)" to="(670,220)"/>
+ <wire from="(750,530)" to="(750,560)"/>
+ <wire from="(900,350)" to="(940,350)"/>
+ <wire from="(920,250)" to="(960,250)"/>
+ <wire from="(920,290)" to="(960,290)"/>
+ <wire from="(1110,620)" to="(1550,620)"/>
+ <wire from="(480,180)" to="(480,210)"/>
+ <wire from="(390,370)" to="(1130,370)"/>
+ <wire from="(490,580)" to="(530,580)"/>
+ <wire from="(760,480)" to="(760,500)"/>
+ <wire from="(770,530)" to="(770,550)"/>
+ <wire from="(900,230)" to="(920,230)"/>
+ <wire from="(900,310)" to="(920,310)"/>
+ <wire from="(940,310)" to="(960,310)"/>
+ <wire from="(1050,530)" to="(1060,530)"/>
+ <wire from="(670,220)" to="(690,220)"/>
+ <wire from="(730,560)" to="(750,560)"/>
+ <wire from="(390,260)" to="(390,370)"/>
+ <wire from="(760,480)" to="(790,480)"/>
+ <wire from="(550,230)" to="(580,230)"/>
+ <wire from="(980,520)" to="(1010,520)"/>
+ <wire from="(510,230)" to="(520,230)"/>
+ <wire from="(150,180)" to="(480,180)"/>
+ <wire from="(1000,540)" to="(1010,540)"/>
+ <wire from="(590,190)" to="(670,190)"/>
+ <wire from="(780,460)" to="(790,460)"/>
+ <wire from="(1060,610)" to="(1080,610)"/>
+ <wire from="(1070,440)" to="(1090,440)"/>
+ <wire from="(390,150)" to="(780,150)"/>
+ <wire from="(1190,330)" to="(1530,330)"/>
+ <wire from="(150,120)" to="(410,120)"/>
+ <wire from="(520,540)" to="(530,540)"/>
+ <wire from="(570,210)" to="(580,210)"/>
+ <wire from="(810,630)" to="(1080,630)"/>
+ <wire from="(750,440)" to="(750,450)"/>
+ <wire from="(530,560)" to="(530,570)"/>
+ <wire from="(910,260)" to="(960,260)"/>
+ <wire from="(910,280)" to="(960,280)"/>
+ <wire from="(910,280)" to="(910,290)"/>
+ <wire from="(1090,330)" to="(1130,330)"/>
+ <wire from="(930,300)" to="(930,330)"/>
+ <wire from="(480,180)" to="(780,180)"/>
+ <wire from="(980,230)" to="(1530,230)"/>
+ <wire from="(980,460)" to="(1020,460)"/>
+ <wire from="(530,430)" to="(640,430)"/>
+ <wire from="(920,230)" to="(920,250)"/>
+ <wire from="(920,290)" to="(920,310)"/>
+ <wire from="(760,550)" to="(760,570)"/>
+ <wire from="(1090,440)" to="(1090,490)"/>
+ <wire from="(390,260)" to="(610,260)"/>
+ <wire from="(390,490)" to="(390,590)"/>
+ <wire from="(640,430)" to="(790,430)"/>
+ <wire from="(510,570)" to="(530,570)"/>
+ <wire from="(940,310)" to="(940,350)"/>
+ <wire from="(760,140)" to="(780,140)"/>
+ <wire from="(640,270)" to="(640,430)"/>
+ <wire from="(390,150)" to="(390,260)"/>
+ <wire from="(530,430)" to="(530,530)"/>
+ <wire from="(930,240)" to="(960,240)"/>
+ <wire from="(930,300)" to="(960,300)"/>
+ <wire from="(990,420)" to="(1020,420)"/>
+ <wire from="(1090,490)" to="(1540,490)"/>
+ <wire from="(900,210)" to="(930,210)"/>
+ <wire from="(900,330)" to="(930,330)"/>
+ <wire from="(120,150)" to="(390,150)"/>
+ <wire from="(410,120)" to="(410,430)"/>
+ <wire from="(480,570)" to="(490,570)"/>
+ <wire from="(760,140)" to="(760,390)"/>
+ <wire from="(390,590)" to="(530,590)"/>
+ <wire from="(390,490)" to="(790,490)"/>
+ <wire from="(900,250)" to="(910,250)"/>
+ <wire from="(900,290)" to="(910,290)"/>
+ <wire from="(740,450)" to="(750,450)"/>
+ <wire from="(760,550)" to="(770,550)"/>
+ <wire from="(1090,330)" to="(1090,440)"/>
+ <wire from="(390,370)" to="(390,490)"/>
<comp lib="0" loc="(1000,540)" name="Constant">
- <a name="value" val="0x0"/>
<a name="width" val="4"/>
+ <a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(120,150)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="label" val="CLK"/>
</comp>
<comp lib="0" loc="(150,120)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="label" val="RESET"/>
</comp>
<comp lib="0" loc="(150,180)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="label" val="RX"/>
</comp>
<comp lib="0" loc="(1530,230)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="facing" val="west"/>
- <a name="label" val="DATA"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
+ <a name="label" val="DATA"/>
</comp>
<comp lib="0" loc="(1530,330)" name="Pin">
- <a name="appearance" val="classic"/>
<a name="facing" val="west"/>
- <a name="label" val="DONE"/>
<a name="output" val="true"/>
+ <a name="label" val="DONE"/>
</comp>
<comp lib="0" loc="(1540,490)" name="Tunnel">
<a name="label" val="done_sig"/>
@@ -4402,8 +4793,8 @@
<a name="label" val="half"/>
</comp>
<comp lib="0" loc="(360,710)" name="Constant">
- <a name="value" val="0x28aa"/>
<a name="width" val="16"/>
+ <a name="value" val="0x28aa"/>
</comp>
<comp lib="0" loc="(480,570)" name="Tunnel">
<a name="facing" val="east"/>
@@ -4419,8 +4810,8 @@
<a name="label" val="half"/>
</comp>
<comp lib="0" loc="(530,620)" name="Constant">
- <a name="value" val="0x0"/>
<a name="width" val="16"/>
+ <a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(690,220)" name="Tunnel">
<a name="label" val="state"/>
@@ -4435,15 +4826,18 @@
<a name="label" val="half"/>
</comp>
<comp lib="0" loc="(770,640)" name="Constant">
- <a name="value" val="0x1455"/>
<a name="width" val="16"/>
+ <a name="value" val="0x1455"/>
</comp>
<comp lib="0" loc="(780,460)" name="Power"/>
<comp lib="0" loc="(790,520)" name="Constant">
- <a name="value" val="0x0"/>
<a name="width" val="4"/>
+ <a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(980,230)" name="Splitter">
+ <a name="facing" val="west"/>
+ <a name="fanout" val="8"/>
+ <a name="incoming" val="8"/>
<a name="bit0" val="7"/>
<a name="bit1" val="6"/>
<a name="bit2" val="5"/>
@@ -4452,9 +4846,6 @@
<a name="bit5" val="2"/>
<a name="bit6" val="1"/>
<a name="bit7" val="0"/>
- <a name="facing" val="west"/>
- <a name="fanout" val="8"/>
- <a name="incoming" val="8"/>
</comp>
<comp lib="1" loc="(1070,440)" name="AND Gate"/>
<comp lib="1" loc="(1110,620)" name="AND Gate">
@@ -4467,7 +4858,6 @@
<a name="size" val="30"/>
</comp>
<comp lib="2" loc="(610,220)" name="Multiplexer">
- <a name="enable" val="true"/>
<a name="selloc" val="tr"/>
</comp>
<comp lib="3" loc="(1050,530)" name="Comparator">
@@ -4480,112 +4870,21 @@
<a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(530,510)" name="Counter">
- <a name="appearance" val="logisim_evolution"/>
- <a name="max" val="0x28aa"/>
<a name="width" val="16"/>
+ <a name="max" val="0x28aa"/>
+ <a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(620,210)" name="D Flip-Flop">
<a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(780,100)" name="Shift Register">
- <a name="appearance" val="logisim_evolution"/>
<a name="length" val="9"/>
+ <a name="appearance" val="logisim_evolution"/>
</comp>
<comp lib="4" loc="(790,410)" name="Counter">
- <a name="appearance" val="logisim_evolution"/>
- <a name="max" val="0x9"/>
<a name="width" val="4"/>
+ <a name="max" val="0x9"/>
+ <a name="appearance" val="logisim_evolution"/>
</comp>
- <wire from="(1000,540)" to="(1010,540)"/>
- <wire from="(1050,530)" to="(1060,530)"/>
- <wire from="(1060,530)" to="(1060,610)"/>
- <wire from="(1060,610)" to="(1080,610)"/>
- <wire from="(1070,440)" to="(1090,440)"/>
- <wire from="(1090,330)" to="(1090,440)"/>
- <wire from="(1090,330)" to="(1130,330)"/>
- <wire from="(1090,440)" to="(1090,490)"/>
- <wire from="(1090,490)" to="(1540,490)"/>
- <wire from="(1110,620)" to="(1550,620)"/>
- <wire from="(1190,330)" to="(1530,330)"/>
- <wire from="(120,150)" to="(390,150)"/>
- <wire from="(150,120)" to="(410,120)"/>
- <wire from="(150,180)" to="(480,180)"/>
- <wire from="(390,150)" to="(390,260)"/>
- <wire from="(390,150)" to="(780,150)"/>
- <wire from="(390,260)" to="(390,370)"/>
- <wire from="(390,260)" to="(610,260)"/>
- <wire from="(390,370)" to="(1130,370)"/>
- <wire from="(390,370)" to="(390,490)"/>
- <wire from="(390,490)" to="(390,590)"/>
- <wire from="(390,490)" to="(790,490)"/>
- <wire from="(390,590)" to="(530,590)"/>
- <wire from="(410,120)" to="(410,430)"/>
- <wire from="(410,120)" to="(780,120)"/>
- <wire from="(410,430)" to="(530,430)"/>
- <wire from="(480,180)" to="(480,210)"/>
- <wire from="(480,180)" to="(780,180)"/>
- <wire from="(480,210)" to="(540,210)"/>
- <wire from="(480,570)" to="(490,570)"/>
- <wire from="(490,570)" to="(490,580)"/>
- <wire from="(490,580)" to="(530,580)"/>
- <wire from="(510,230)" to="(520,230)"/>
- <wire from="(510,570)" to="(530,570)"/>
- <wire from="(520,540)" to="(530,540)"/>
- <wire from="(530,430)" to="(530,530)"/>
- <wire from="(530,430)" to="(640,430)"/>
- <wire from="(530,560)" to="(530,570)"/>
- <wire from="(550,230)" to="(580,230)"/>
- <wire from="(570,210)" to="(580,210)"/>
- <wire from="(590,190)" to="(590,200)"/>
- <wire from="(590,190)" to="(670,190)"/>
- <wire from="(640,270)" to="(640,430)"/>
- <wire from="(640,430)" to="(790,430)"/>
- <wire from="(670,190)" to="(670,220)"/>
- <wire from="(670,220)" to="(690,220)"/>
- <wire from="(730,560)" to="(750,560)"/>
- <wire from="(730,620)" to="(770,620)"/>
- <wire from="(740,130)" to="(780,130)"/>
- <wire from="(740,450)" to="(750,450)"/>
- <wire from="(750,440)" to="(750,450)"/>
- <wire from="(750,440)" to="(790,440)"/>
- <wire from="(750,530)" to="(750,560)"/>
- <wire from="(760,140)" to="(760,390)"/>
- <wire from="(760,140)" to="(780,140)"/>
- <wire from="(760,390)" to="(760,480)"/>
- <wire from="(760,390)" to="(990,390)"/>
- <wire from="(760,480)" to="(760,500)"/>
- <wire from="(760,480)" to="(790,480)"/>
- <wire from="(760,550)" to="(760,570)"/>
- <wire from="(760,550)" to="(770,550)"/>
- <wire from="(770,530)" to="(770,550)"/>
- <wire from="(780,460)" to="(790,460)"/>
- <wire from="(810,630)" to="(1080,630)"/>
- <wire from="(900,210)" to="(930,210)"/>
- <wire from="(900,230)" to="(920,230)"/>
- <wire from="(900,250)" to="(910,250)"/>
- <wire from="(900,270)" to="(960,270)"/>
- <wire from="(900,290)" to="(910,290)"/>
- <wire from="(900,310)" to="(920,310)"/>
- <wire from="(900,330)" to="(930,330)"/>
- <wire from="(900,350)" to="(940,350)"/>
- <wire from="(910,250)" to="(910,260)"/>
- <wire from="(910,260)" to="(960,260)"/>
- <wire from="(910,280)" to="(910,290)"/>
- <wire from="(910,280)" to="(960,280)"/>
- <wire from="(920,230)" to="(920,250)"/>
- <wire from="(920,250)" to="(960,250)"/>
- <wire from="(920,290)" to="(920,310)"/>
- <wire from="(920,290)" to="(960,290)"/>
- <wire from="(930,210)" to="(930,240)"/>
- <wire from="(930,240)" to="(960,240)"/>
- <wire from="(930,300)" to="(930,330)"/>
- <wire from="(930,300)" to="(960,300)"/>
- <wire from="(940,310)" to="(940,350)"/>
- <wire from="(940,310)" to="(960,310)"/>
- <wire from="(980,230)" to="(1530,230)"/>
- <wire from="(980,460)" to="(1020,460)"/>
- <wire from="(980,520)" to="(1010,520)"/>
- <wire from="(990,390)" to="(990,420)"/>
- <wire from="(990,420)" to="(1020,420)"/>
</circuit>
</project>
diff --git a/CPU/TOP-RobotMyLab-MAP.xml b/CPU/TOP-RobotMyLab-MAP.xml
index 9dd3ec648bbc8b640e7d3d924e9afe52e60f529d..4756e81c5049ac4ca6cbc910a9a439092c5dd276 100644
--- a/CPU/TOP-RobotMyLab-MAP.xml
+++ b/CPU/TOP-RobotMyLab-MAP.xml
@@ -12,9 +12,19 @@
<MAPPEDCOMPONENT_9 Height="9" Key="PIN: /LED_5#Pin0" LocationX="317" LocationY="291" Width="9"/>
<MAPPEDCOMPONENT_a Height="9" Key="PIN: /LED_6#Pin0" LocationX="291" LocationY="291" Width="9"/>
<MAPPEDCOMPONENT_b Height="9" Key="PIN: /LED_7#Pin0" LocationX="265" LocationY="291" Width="9"/>
- <MAPPEDCOMPONENT_c Height="18" Key="PIN: /RESET#Pin0" LocationX="360" LocationY="240" Width="18"/>
- <MAPPEDCOMPONENT_d Height="8" Key="PIN: /RX#Pin0" LocationX="44" LocationY="153" Width="8"/>
- <MAPPEDCOMPONENT_e Height="15" Key="PIN: /UART_RX_PC#Pin0" LocationX="123" LocationY="115" Width="15"/>
- <MAPPEDCOMPONENT_f Height="10" Key="PIN: /WHEEL_LEFT_PWM#Pin0" LocationX="676" LocationY="73" Width="25"/>
- <MAPPEDCOMPONENT_10 Height="10" Key="PIN: /WHEEL_RIGHT_PWM#Pin0" LocationX="673" LocationY="369" Width="25"/>
+ <MAPPEDCOMPONENT_c Height="9" Key="PIN: /LED_LEFT#Pin0" LocationX="60" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_d Height="9" Key="PIN: /LED_RIGHT#Pin0" LocationX="84" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_e Height="9" Key="PIN: /PWM0#Pin0" LocationX="239" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_f Height="9" Key="PIN: /PWM1#Pin0" LocationX="213" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_10 Height="9" Key="PIN: /PWM2#Pin0" LocationX="187" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_11 Height="9" Key="PIN: /PWM3#Pin0" LocationX="161" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_12 Height="9" Key="PIN: /PWM4#Pin0" LocationX="136" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_13 Height="9" Key="PIN: /PWM5#Pin0" LocationX="110" LocationY="291" Width="9"/>
+ <MAPPEDCOMPONENT_14 Height="5" Key="PIN: /PWM6#Pin0" LocationX="170" LocationY="274" Width="17"/>
+ <MAPPEDCOMPONENT_15 Height="5" Key="PIN: /PWM7#Pin0" LocationX="172" LocationY="258" Width="14"/>
+ <MAPPEDCOMPONENT_16 Height="18" Key="PIN: /RESET#Pin0" LocationX="360" LocationY="240" Width="18"/>
+ <MAPPEDCOMPONENT_17 Height="8" Key="PIN: /RX#Pin0" LocationX="44" LocationY="153" Width="8"/>
+ <MAPPEDCOMPONENT_18 Height="15" Key="PIN: /UART_RX_PC#Pin0" LocationX="123" LocationY="115" Width="15"/>
+ <MAPPEDCOMPONENT_19 Height="10" Key="PIN: /WHEEL_LEFT_PWM#Pin0" LocationX="676" LocationY="73" Width="25"/>
+ <MAPPEDCOMPONENT_1a Height="10" Key="PIN: /WHEEL_RIGHT_PWM#Pin0" LocationX="673" LocationY="369" Width="25"/>
</LogisimGoesFPGABoardMapInformation>
diff --git a/CPU/logi_compiler_sources/instructions.circ b/CPU/logi_compiler_sources/instructions.circ
index 97048ef0fae4e13cbee55d424135a19f316d00ae..f2271e20473fdeecf82be1f420c5e9338ac4f1d5 100644
--- a/CPU/logi_compiler_sources/instructions.circ
+++ b/CPU/logi_compiler_sources/instructions.circ
@@ -1,1045 +1,578 @@
-<?xml version="1.0" ?>
-<project source="2.10.1" version="1.0">
-
-This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project source="3.0.0" version="1.0">
+ This file is intended to be loaded by Logisim-evolution (https://github.com/reds-heig/logisim-evolution).
- <lib desc="#Wiring" name="0">
-
-
- <tool name="Splitter">
-
-
- <a name="fanout" val="32"/>
-
-
- <a name="incoming" val="32"/>
-
-
- </tool>
-
-
- </lib>
-
-
- <lib desc="#Gates" name="1"/>
-
-
- <lib desc="#Plexers" name="2"/>
-
-
- <lib desc="#Arithmetic" name="3"/>
-
-
- <lib desc="#Memory" name="4"/>
-
-
- <lib desc="#I/O" name="5"/>
-
-
- <lib desc="#HDL-IP" name="6"/>
-
-
- <lib desc="#Base" name="7">
-
-
- <tool name="Text Tool">
-
-
- <a name="text" val=""/>
-
-
- <a name="font" val="SansSerif plain 12"/>
-
-
- <a name="halign" val="center"/>
-
-
- <a name="valign" val="base"/>
-
-
- </tool>
-
-
- </lib>
-
-
- <main name="rom"/>
-
-
- <options>
-
-
- <a name="gateUndefined" val="ignore"/>
-
-
- <a name="simlimit" val="1000"/>
-
-
- <a name="simrand" val="0"/>
-
-
- <a name="tickmain" val="half_period"/>
-
-
- </options>
-
-
- <mappings>
-
-
- <tool lib="7" map="Button2" name="Menu Tool"/>
-
-
- <tool lib="7" map="Ctrl Button1" name="Menu Tool"/>
-
-
- <tool lib="7" map="Button3" name="Menu Tool"/>
-
-
- </mappings>
-
-
- <toolbar>
-
-
- <tool lib="7" name="Poke Tool"/>
-
-
- <tool lib="7" name="Edit Tool"/>
-
-
- <tool lib="7" name="Text Tool">
-
-
- <a name="text" val=""/>
-
-
- <a name="font" val="SansSerif plain 12"/>
-
-
- <a name="halign" val="center"/>
-
-
- <a name="valign" val="base"/>
-
-
- </tool>
-
-
- <sep/>
-
-
- <tool lib="0" name="Pin">
-
-
- <a name="tristate" val="false"/>
-
-
- </tool>
-
-
- <tool lib="0" name="Pin">
-
-
- <a name="facing" val="west"/>
-
-
- <a name="output" val="true"/>
-
-
- <a name="labelloc" val="east"/>
-
-
- </tool>
-
-
- <tool lib="1" name="NOT Gate"/>
-
-
- <tool lib="1" name="AND Gate"/>
-
-
- <tool lib="1" name="OR Gate"/>
-
-
- </toolbar>
-
-
- <circuit name="rom">
-
-
- <a name="circuit" val="rom"/>
-
-
- <a name="clabel" val=""/>
-
-
- <a name="clabelup" val="east"/>
-
-
- <a name="clabelfont" val="SansSerif plain 12"/>
-
-
- <a name="circuitvhdl" val="false"/>
-
-
- <a name="circuitvhdlpath" val=""/>
-
-
- <wire from="(410,680)" to="(450,680)"/>
-
-
- <wire from="(300,810)" to="(370,810)"/>
-
-
- <wire from="(550,180)" to="(660,180)"/>
-
-
- <wire from="(260,180)" to="(370,180)"/>
-
-
- <wire from="(180,510)" to="(190,510)"/>
-
-
- <wire from="(550,240)" to="(660,240)"/>
-
-
- <wire from="(590,750)" to="(660,750)"/>
-
-
- <wire from="(300,190)" to="(370,190)"/>
-
-
- <wire from="(590,310)" to="(660,310)"/>
-
-
- <wire from="(260,240)" to="(370,240)"/>
-
-
- <wire from="(980,650)" to="(1000,650)"/>
-
-
- <wire from="(590,250)" to="(660,250)"/>
-
-
- <wire from="(590,190)" to="(660,190)"/>
-
-
- <wire from="(300,750)" to="(370,750)"/>
-
-
- <wire from="(300,310)" to="(370,310)"/>
-
-
- <wire from="(550,400)" to="(660,400)"/>
-
-
- <wire from="(590,550)" to="(660,550)"/>
-
-
- <wire from="(550,680)" to="(660,680)"/>
-
-
- <wire from="(260,620)" to="(370,620)"/>
-
-
- <wire from="(260,400)" to="(370,400)"/>
-
-
- <wire from="(300,550)" to="(370,550)"/>
-
-
- <wire from="(300,630)" to="(370,630)"/>
-
-
- <wire from="(550,620)" to="(660,620)"/>
-
-
- <wire from="(260,680)" to="(370,680)"/>
-
-
- <wire from="(550,280)" to="(660,280)"/>
-
-
- <wire from="(180,480)" to="(390,480)"/>
-
-
- <wire from="(260,340)" to="(370,340)"/>
-
-
- <wire from="(590,690)" to="(660,690)"/>
-
-
- <wire from="(300,690)" to="(370,690)"/>
-
-
- <wire from="(300,250)" to="(370,250)"/>
-
-
- <wire from="(550,780)" to="(660,780)"/>
-
-
- <wire from="(260,520)" to="(370,520)"/>
-
-
- <wire from="(410,300)" to="(450,300)"/>
-
-
- <wire from="(260,740)" to="(370,740)"/>
-
-
- <wire from="(550,340)" to="(660,340)"/>
-
-
- <wire from="(550,560)" to="(660,560)"/>
-
-
- <wire from="(260,560)" to="(370,560)"/>
-
-
- <wire from="(590,630)" to="(660,630)"/>
-
-
- <wire from="(550,740)" to="(660,740)"/>
-
-
- <wire from="(700,680)" to="(740,680)"/>
-
-
- <wire from="(300,610)" to="(370,610)"/>
-
-
- <wire from="(300,790)" to="(370,790)"/>
-
-
- <wire from="(550,440)" to="(660,440)"/>
-
-
- <wire from="(260,780)" to="(370,780)"/>
-
-
- <wire from="(550,520)" to="(660,520)"/>
-
-
- <wire from="(590,210)" to="(660,210)"/>
-
-
- <wire from="(300,390)" to="(370,390)"/>
-
-
- <wire from="(300,730)" to="(370,730)"/>
-
-
- <wire from="(300,230)" to="(370,230)"/>
-
-
- <wire from="(550,580)" to="(660,580)"/>
-
-
- <wire from="(260,720)" to="(370,720)"/>
-
-
- <wire from="(590,270)" to="(660,270)"/>
-
-
- <wire from="(140,490)" to="(160,490)"/>
-
-
- <wire from="(260,280)" to="(370,280)"/>
-
-
- <wire from="(300,670)" to="(370,670)"/>
-
-
- <wire from="(300,450)" to="(370,450)"/>
-
-
- <wire from="(550,140)" to="(660,140)"/>
-
-
- <wire from="(260,360)" to="(370,360)"/>
-
-
- <wire from="(260,800)" to="(370,800)"/>
-
-
- <wire from="(260,600)" to="(370,600)"/>
-
-
- <wire from="(590,590)" to="(660,590)"/>
-
-
- <wire from="(550,700)" to="(660,700)"/>
-
-
- <wire from="(260,420)" to="(370,420)"/>
-
-
- <wire from="(300,350)" to="(370,350)"/>
-
-
- <wire from="(300,570)" to="(370,570)"/>
-
-
- <wire from="(590,370)" to="(660,370)"/>
-
-
- <wire from="(590,150)" to="(660,150)"/>
-
-
- <wire from="(300,290)" to="(370,290)"/>
-
-
- <wire from="(550,820)" to="(660,820)"/>
-
-
- <wire from="(590,810)" to="(660,810)"/>
-
-
- <wire from="(260,300)" to="(370,300)"/>
-
-
- <wire from="(550,200)" to="(660,200)"/>
-
-
- <wire from="(680,460)" to="(680,480)"/>
-
-
- <wire from="(810,740)" to="(910,740)"/>
-
-
- <wire from="(550,640)" to="(660,640)"/>
-
-
- <wire from="(180,490)" to="(180,510)"/>
-
-
- <wire from="(260,660)" to="(370,660)"/>
-
-
- <wire from="(390,480)" to="(390,520)"/>
-
-
- <wire from="(590,430)" to="(660,430)"/>
-
-
- <wire from="(550,260)" to="(660,260)"/>
-
-
- <wire from="(300,590)" to="(370,590)"/>
-
-
- <wire from="(860,730)" to="(910,730)"/>
-
-
- <wire from="(590,350)" to="(660,350)"/>
-
-
- <wire from="(260,380)" to="(370,380)"/>
-
-
- <wire from="(300,530)" to="(370,530)"/>
-
-
- <wire from="(550,320)" to="(660,320)"/>
-
-
- <wire from="(590,710)" to="(660,710)"/>
-
-
- <wire from="(260,320)" to="(370,320)"/>
-
-
- <wire from="(950,740)" to="(1000,740)"/>
-
-
- <wire from="(550,760)" to="(660,760)"/>
-
-
- <wire from="(590,650)" to="(660,650)"/>
-
-
- <wire from="(260,540)" to="(370,540)"/>
-
-
- <wire from="(550,540)" to="(660,540)"/>
-
-
- <wire from="(260,760)" to="(370,760)"/>
-
-
- <wire from="(300,710)" to="(370,710)"/>
-
-
- <wire from="(300,410)" to="(370,410)"/>
-
-
- <wire from="(590,530)" to="(660,530)"/>
-
-
- <wire from="(260,220)" to="(370,220)"/>
-
-
- <wire from="(590,330)" to="(660,330)"/>
-
-
- <wire from="(300,770)" to="(370,770)"/>
-
-
- <wire from="(590,770)" to="(660,770)"/>
-
-
- <wire from="(550,220)" to="(660,220)"/>
-
-
- <wire from="(300,170)" to="(370,170)"/>
-
-
- <wire from="(590,410)" to="(660,410)"/>
-
-
- <wire from="(300,830)" to="(370,830)"/>
-
-
- <wire from="(550,380)" to="(660,380)"/>
-
-
- <wire from="(260,160)" to="(370,160)"/>
-
-
- <wire from="(590,830)" to="(660,830)"/>
-
-
- <wire from="(550,160)" to="(660,160)"/>
-
-
- <wire from="(920,820)" to="(930,820)"/>
-
-
- <wire from="(860,750)" to="(910,750)"/>
-
-
- <wire from="(590,790)" to="(660,790)"/>
-
-
- <wire from="(1000,650)" to="(1000,740)"/>
-
-
- <wire from="(590,570)" to="(660,570)"/>
-
-
- <wire from="(260,640)" to="(370,640)"/>
-
-
- <wire from="(810,720)" to="(910,720)"/>
-
-
- <wire from="(550,660)" to="(660,660)"/>
-
-
- <wire from="(590,170)" to="(660,170)"/>
-
-
- <wire from="(590,610)" to="(660,610)"/>
-
-
- <wire from="(550,720)" to="(660,720)"/>
-
-
- <wire from="(260,580)" to="(370,580)"/>
-
-
- <wire from="(300,330)" to="(370,330)"/>
-
-
- <wire from="(260,440)" to="(370,440)"/>
-
-
- <wire from="(550,360)" to="(660,360)"/>
-
-
- <wire from="(590,450)" to="(660,450)"/>
-
-
- <wire from="(390,480)" to="(680,480)"/>
-
-
- <wire from="(590,670)" to="(660,670)"/>
-
-
- <wire from="(700,300)" to="(740,300)"/>
-
-
- <wire from="(300,270)" to="(370,270)"/>
-
-
- <wire from="(550,800)" to="(660,800)"/>
-
-
- <wire from="(590,390)" to="(660,390)"/>
-
-
- <wire from="(590,730)" to="(660,730)"/>
-
-
- <wire from="(930,760)" to="(930,820)"/>
-
-
- <wire from="(1000,740)" to="(1030,740)"/>
-
-
- <wire from="(260,200)" to="(370,200)"/>
-
-
- <wire from="(260,820)" to="(370,820)"/>
-
-
- <wire from="(300,370)" to="(370,370)"/>
-
-
- <wire from="(300,150)" to="(370,150)"/>
-
-
- <wire from="(300,430)" to="(370,430)"/>
-
-
- <wire from="(550,420)" to="(660,420)"/>
-
-
- <wire from="(260,140)" to="(370,140)"/>
-
-
- <wire from="(590,230)" to="(660,230)"/>
-
-
- <wire from="(680,480)" to="(680,520)"/>
-
-
- <wire from="(260,260)" to="(370,260)"/>
-
-
- <wire from="(590,290)" to="(660,290)"/>
-
-
- <wire from="(300,650)" to="(370,650)"/>
-
-
- <wire from="(390,460)" to="(390,480)"/>
-
-
- <wire from="(300,210)" to="(370,210)"/>
-
-
- <wire from="(260,700)" to="(370,700)"/>
-
-
- <wire from="(550,300)" to="(660,300)"/>
-
-
- <wire from="(550,600)" to="(660,600)"/>
-
-
- <comp lib="0" loc="(920,820)" name="Tunnel">
-
-
- <a name="facing" val="east"/>
-
-
- <a name="width" val="2"/>
-
-
- <a name="label" val="sel"/>
-
-
- </comp>
-
-
- <comp lib="2" loc="(410,300)" name="Multiplexer">
-
-
- <a name="select" val="5"/>
-
-
- <a name="width" val="16"/>
-
-
- </comp>
-
-
- <comp lib="2" loc="(700,300)" name="Multiplexer">
-
-
- <a name="select" val="5"/>
-
-
- <a name="width" val="16"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(980,650)" name="Probe">
-
-
- <a name="radix" val="16"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(810,720)" name="Tunnel">
-
-
- <a name="facing" val="east"/>
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux0"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(160,490)" name="Splitter">
-
-
- <a name="incoming" val="7"/>
-
-
- <a name="appear" val="center"/>
-
-
- <a name="bit1" val="0"/>
-
-
- <a name="bit2" val="0"/>
-
-
- <a name="bit3" val="0"/>
-
-
- <a name="bit4" val="0"/>
-
-
- <a name="bit5" val="1"/>
-
-
- <a name="bit6" val="1"/>
-
-
- </comp>
-
-
- <comp lib="2" loc="(410,680)" name="Multiplexer">
-
-
- <a name="selloc" val="tr"/>
-
-
- <a name="select" val="5"/>
-
-
- <a name="width" val="16"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(450,680)" name="Tunnel">
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux1"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(740,300)" name="Tunnel">
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux2"/>
-
-
- </comp>
-
-
- <comp lib="2" loc="(700,680)" name="Multiplexer">
-
-
- <a name="selloc" val="tr"/>
-
-
- <a name="select" val="5"/>
-
-
- <a name="width" val="16"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(190,510)" name="Tunnel">
-
-
- <a name="width" val="2"/>
-
-
- <a name="label" val="sel"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(1030,740)" name="Pin">
-
-
- <a name="facing" val="west"/>
-
-
- <a name="output" val="true"/>
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="data_out"/>
-
-
- <a name="labelloc" val="east"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(450,300)" name="Tunnel">
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux0"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(860,730)" name="Tunnel">
-
-
- <a name="facing" val="east"/>
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux1"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(860,750)" name="Tunnel">
-
-
- <a name="facing" val="east"/>
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux3"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(810,740)" name="Tunnel">
-
-
- <a name="facing" val="east"/>
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux2"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(140,490)" name="Pin">
-
-
- <a name="width" val="7"/>
-
-
- <a name="tristate" val="false"/>
-
-
- <a name="label" val="addr"/>
-
-
- </comp>
-
-
- <comp lib="2" loc="(950,740)" name="Multiplexer">
-
-
- <a name="select" val="2"/>
-
-
- <a name="width" val="16"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(740,680)" name="Tunnel">
-
-
- <a name="width" val="16"/>
-
-
- <a name="label" val="mux3"/>
-
-
- </comp>
-
-
- <comp lib="0" loc="(260, 140)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000000000010000"/>
- </comp>
- <comp lib="0" loc="(300, 150)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1100001000000000"/>
- </comp>
- <comp lib="0" loc="(260, 160)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000010001110111"/>
- </comp>
- <comp lib="0" loc="(300, 170)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b0001011001010000"/>
- </comp>
- <comp lib="0" loc="(260, 180)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1010100000000010"/>
- </comp>
- <comp lib="0" loc="(300, 190)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1110111000010011"/>
- </comp>
- <comp lib="0" loc="(260, 200)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000010001100001"/>
- </comp>
- <comp lib="0" loc="(300, 210)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b0001011001010000"/>
- </comp>
- <comp lib="0" loc="(260, 220)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1010100000000010"/>
- </comp>
- <comp lib="0" loc="(300, 230)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1110111000011001"/>
- </comp>
- <comp lib="0" loc="(260, 240)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000010001110011"/>
- </comp>
- <comp lib="0" loc="(300, 250)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b0001011001010000"/>
- </comp>
- <comp lib="0" loc="(260, 260)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1010100000000010"/>
- </comp>
- <comp lib="0" loc="(300, 270)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1110111000010110"/>
- </comp>
- <comp lib="0" loc="(260, 280)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000010001100100"/>
- </comp>
- <comp lib="0" loc="(300, 290)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b0001011001010000"/>
- </comp>
- <comp lib="0" loc="(260, 300)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1010100000000010"/>
- </comp>
- <comp lib="0" loc="(300, 310)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1110111000011001"/>
- </comp>
- <comp lib="0" loc="(260, 320)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1011111111101110"/>
- </comp>
- <comp lib="0" loc="(300, 330)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000100001100100"/>
- </comp>
- <comp lib="0" loc="(260, 340)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000101001100100"/>
- </comp>
- <comp lib="0" loc="(300, 350)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1111111000000000"/>
- </comp>
- <comp lib="0" loc="(260, 360)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000100010011100"/>
- </comp>
- <comp lib="0" loc="(300, 370)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000101010011100"/>
- </comp>
- <comp lib="0" loc="(260, 380)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1111111000000000"/>
- </comp>
- <comp lib="0" loc="(300, 390)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000100000110010"/>
- </comp>
- <comp lib="0" loc="(260, 400)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000101011001110"/>
- </comp>
- <comp lib="0" loc="(300, 410)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1111111000000000"/>
- </comp>
- <comp lib="0" loc="(260, 420)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000100011001110"/>
- </comp>
- <comp lib="0" loc="(300, 430)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1000101000110010"/>
- </comp>
- <comp lib="0" loc="(260, 440)" name="Constant">
- <a name="width" val="16"/>
- <a name="value" val="0b1111111000000000"/>
- </comp>
- </circuit>
-
+ <lib desc="#Wiring" name="0">
+ <tool name="Splitter">
+ <a name="fanout" val="32"/>
+ <a name="incoming" val="32"/>
+ </tool>
+ <tool name="Pin">
+ <a name="appearance" val="NewPins"/>
+ </tool>
+ <tool name="Probe">
+ <a name="appearance" val="NewPins"/>
+ </tool>
+ <tool name="Tunnel">
+ <a name="facing" val="east"/>
+ </tool>
+ </lib>
+ <lib desc="#Gates" name="1"/>
+ <lib desc="#Plexers" name="2">
+ <tool name="Multiplexer">
+ <a name="enable" val="false"/>
+ </tool>
+ <tool name="Demultiplexer">
+ <a name="enable" val="false"/>
+ </tool>
+ </lib>
+ <lib desc="#Arithmetic" name="3"/>
+ <lib desc="#Memory" name="4">
+ <tool name="D Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="T Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="J-K Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="S-R Flip-Flop">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="Counter">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="Shift Register">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="Random">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="RAM">
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ <tool name="ROM">
+ <a name="contents">addr/data: 8 8
+0
+</a>
+ <a name="appearance" val="logisim_evolution"/>
+ </tool>
+ </lib>
+ <lib desc="#I/O" name="5"/>
+ <lib desc="#HDL-IP" name="6">
+ <tool name="VHDL Entity">
+ <a name="content">--------------------------------------------------------------------------------
+-- HEPIA, 4 rue de la prairie, 1205 Genève
+-- Project :
+-- File :
+-- Autor :
+-- Date :
+--
+--------------------------------------------------------------------------------
+-- Description :
+--
+--------------------------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity VHDL_Component is
+ port(
+ ------------------------------------------------------------------------------
+ --Insert input ports below
+ entree : in std_logic; -- input bit example
+ entree_vec : in std_logic_vector(3 downto 0); -- input vector example
+ ------------------------------------------------------------------------------
+ --Insert output ports below
+ sortie : out std_logic; -- output bit example
+ sortie_vec : out std_logic_vector(3 downto 0) -- output vector example
+ );
+end VHDL_Component;
+
+--------------------------------------------------------------------------------
+--Complete your VHDL description below
+architecture behavioral of VHDL_Component is
+
+
+begin
+
+
+end behavioral;
+</a>
+ </tool>
+ </lib>
+ <lib desc="#Base" name="7">
+ <tool name="Text Tool">
+ <a name="text" val=""/>
+ <a name="font" val="SansSerif plain 12"/>
+ <a name="halign" val="center"/>
+ <a name="valign" val="base"/>
+ </tool>
+ </lib>
+ <main name="rom"/>
+ <options>
+ <a name="gateUndefined" val="ignore"/>
+ <a name="simlimit" val="1000"/>
+ <a name="simrand" val="0"/>
+ <a name="tickmain" val="half_period"/>
+ </options>
+ <mappings>
+ <tool lib="7" map="Button2" name="Menu Tool"/>
+ <tool lib="7" map="Ctrl Button1" name="Menu Tool"/>
+ <tool lib="7" map="Button3" name="Menu Tool"/>
+ </mappings>
+ <toolbar>
+ <tool lib="7" name="Poke Tool"/>
+ <tool lib="7" name="Edit Tool"/>
+ <tool lib="7" name="Text Tool">
+ <a name="text" val=""/>
+ <a name="font" val="SansSerif plain 12"/>
+ <a name="halign" val="center"/>
+ <a name="valign" val="base"/>
+ </tool>
+ <sep/>
+ <tool lib="0" name="Pin">
+ <a name="appearance" val="NewPins"/>
+ </tool>
+ <tool lib="0" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="appearance" val="NewPins"/>
+ </tool>
+ <tool lib="1" name="NOT Gate"/>
+ <tool lib="1" name="AND Gate"/>
+ <tool lib="1" name="OR Gate"/>
+ </toolbar>
+ <circuit name="rom">
+ <a name="circuit" val="rom"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif plain 12"/>
+ <a name="appearance" val="classic"/>
+ <a name="circuitnamedboxfixedsize" val="false"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(550,620)" to="(660,620)"/>
+ <wire from="(550,340)" to="(660,340)"/>
+ <wire from="(550,180)" to="(660,180)"/>
+ <wire from="(550,140)" to="(660,140)"/>
+ <wire from="(550,700)" to="(660,700)"/>
+ <wire from="(550,660)" to="(660,660)"/>
+ <wire from="(550,260)" to="(660,260)"/>
+ <wire from="(550,300)" to="(660,300)"/>
+ <wire from="(550,220)" to="(660,220)"/>
+ <wire from="(550,780)" to="(660,780)"/>
+ <wire from="(550,820)" to="(660,820)"/>
+ <wire from="(550,740)" to="(660,740)"/>
+ <wire from="(550,580)" to="(660,580)"/>
+ <wire from="(550,540)" to="(660,540)"/>
+ <wire from="(550,380)" to="(660,380)"/>
+ <wire from="(550,420)" to="(660,420)"/>
+ <wire from="(410,300)" to="(450,300)"/>
+ <wire from="(680,480)" to="(680,520)"/>
+ <wire from="(980,650)" to="(1000,650)"/>
+ <wire from="(1000,740)" to="(1030,740)"/>
+ <wire from="(140,490)" to="(160,490)"/>
+ <wire from="(300,450)" to="(370,450)"/>
+ <wire from="(300,810)" to="(370,810)"/>
+ <wire from="(300,410)" to="(370,410)"/>
+ <wire from="(300,330)" to="(370,330)"/>
+ <wire from="(300,370)" to="(370,370)"/>
+ <wire from="(300,530)" to="(370,530)"/>
+ <wire from="(300,690)" to="(370,690)"/>
+ <wire from="(300,730)" to="(370,730)"/>
+ <wire from="(300,770)" to="(370,770)"/>
+ <wire from="(300,250)" to="(370,250)"/>
+ <wire from="(300,170)" to="(370,170)"/>
+ <wire from="(300,210)" to="(370,210)"/>
+ <wire from="(300,290)" to="(370,290)"/>
+ <wire from="(300,610)" to="(370,610)"/>
+ <wire from="(300,650)" to="(370,650)"/>
+ <wire from="(300,570)" to="(370,570)"/>
+ <wire from="(860,750)" to="(910,750)"/>
+ <wire from="(810,740)" to="(910,740)"/>
+ <wire from="(700,680)" to="(740,680)"/>
+ <wire from="(260,420)" to="(370,420)"/>
+ <wire from="(260,620)" to="(370,620)"/>
+ <wire from="(260,180)" to="(370,180)"/>
+ <wire from="(260,140)" to="(370,140)"/>
+ <wire from="(260,660)" to="(370,660)"/>
+ <wire from="(260,700)" to="(370,700)"/>
+ <wire from="(260,340)" to="(370,340)"/>
+ <wire from="(260,380)" to="(370,380)"/>
+ <wire from="(260,300)" to="(370,300)"/>
+ <wire from="(260,260)" to="(370,260)"/>
+ <wire from="(260,220)" to="(370,220)"/>
+ <wire from="(260,540)" to="(370,540)"/>
+ <wire from="(260,580)" to="(370,580)"/>
+ <wire from="(260,740)" to="(370,740)"/>
+ <wire from="(260,780)" to="(370,780)"/>
+ <wire from="(260,820)" to="(370,820)"/>
+ <wire from="(390,480)" to="(680,480)"/>
+ <wire from="(390,480)" to="(390,520)"/>
+ <wire from="(590,350)" to="(660,350)"/>
+ <wire from="(590,310)" to="(660,310)"/>
+ <wire from="(590,750)" to="(660,750)"/>
+ <wire from="(590,830)" to="(660,830)"/>
+ <wire from="(590,790)" to="(660,790)"/>
+ <wire from="(590,710)" to="(660,710)"/>
+ <wire from="(590,190)" to="(660,190)"/>
+ <wire from="(590,150)" to="(660,150)"/>
+ <wire from="(590,550)" to="(660,550)"/>
+ <wire from="(590,430)" to="(660,430)"/>
+ <wire from="(590,390)" to="(660,390)"/>
+ <wire from="(590,630)" to="(660,630)"/>
+ <wire from="(590,670)" to="(660,670)"/>
+ <wire from="(590,590)" to="(660,590)"/>
+ <wire from="(590,270)" to="(660,270)"/>
+ <wire from="(590,230)" to="(660,230)"/>
+ <wire from="(180,510)" to="(190,510)"/>
+ <wire from="(1000,650)" to="(1000,740)"/>
+ <wire from="(550,320)" to="(660,320)"/>
+ <wire from="(550,200)" to="(660,200)"/>
+ <wire from="(550,160)" to="(660,160)"/>
+ <wire from="(550,240)" to="(660,240)"/>
+ <wire from="(550,400)" to="(660,400)"/>
+ <wire from="(550,360)" to="(660,360)"/>
+ <wire from="(550,680)" to="(660,680)"/>
+ <wire from="(550,640)" to="(660,640)"/>
+ <wire from="(550,280)" to="(660,280)"/>
+ <wire from="(550,760)" to="(660,760)"/>
+ <wire from="(550,800)" to="(660,800)"/>
+ <wire from="(550,720)" to="(660,720)"/>
+ <wire from="(550,560)" to="(660,560)"/>
+ <wire from="(550,600)" to="(660,600)"/>
+ <wire from="(550,520)" to="(660,520)"/>
+ <wire from="(550,440)" to="(660,440)"/>
+ <wire from="(410,680)" to="(450,680)"/>
+ <wire from="(680,460)" to="(680,480)"/>
+ <wire from="(920,820)" to="(930,820)"/>
+ <wire from="(300,630)" to="(370,630)"/>
+ <wire from="(300,790)" to="(370,790)"/>
+ <wire from="(300,830)" to="(370,830)"/>
+ <wire from="(300,190)" to="(370,190)"/>
+ <wire from="(300,150)" to="(370,150)"/>
+ <wire from="(300,750)" to="(370,750)"/>
+ <wire from="(300,310)" to="(370,310)"/>
+ <wire from="(300,550)" to="(370,550)"/>
+ <wire from="(300,430)" to="(370,430)"/>
+ <wire from="(300,390)" to="(370,390)"/>
+ <wire from="(300,350)" to="(370,350)"/>
+ <wire from="(300,670)" to="(370,670)"/>
+ <wire from="(300,710)" to="(370,710)"/>
+ <wire from="(300,230)" to="(370,230)"/>
+ <wire from="(300,270)" to="(370,270)"/>
+ <wire from="(300,590)" to="(370,590)"/>
+ <wire from="(950,740)" to="(1000,740)"/>
+ <wire from="(860,730)" to="(910,730)"/>
+ <wire from="(810,720)" to="(910,720)"/>
+ <wire from="(700,300)" to="(740,300)"/>
+ <wire from="(390,460)" to="(390,480)"/>
+ <wire from="(260,360)" to="(370,360)"/>
+ <wire from="(260,400)" to="(370,400)"/>
+ <wire from="(260,440)" to="(370,440)"/>
+ <wire from="(180,490)" to="(180,510)"/>
+ <wire from="(260,160)" to="(370,160)"/>
+ <wire from="(260,200)" to="(370,200)"/>
+ <wire from="(260,240)" to="(370,240)"/>
+ <wire from="(260,680)" to="(370,680)"/>
+ <wire from="(260,720)" to="(370,720)"/>
+ <wire from="(260,280)" to="(370,280)"/>
+ <wire from="(260,320)" to="(370,320)"/>
+ <wire from="(260,520)" to="(370,520)"/>
+ <wire from="(260,760)" to="(370,760)"/>
+ <wire from="(260,800)" to="(370,800)"/>
+ <wire from="(260,560)" to="(370,560)"/>
+ <wire from="(260,600)" to="(370,600)"/>
+ <wire from="(260,640)" to="(370,640)"/>
+ <wire from="(180,480)" to="(390,480)"/>
+ <wire from="(930,760)" to="(930,820)"/>
+ <wire from="(590,530)" to="(660,530)"/>
+ <wire from="(590,810)" to="(660,810)"/>
+ <wire from="(590,770)" to="(660,770)"/>
+ <wire from="(590,730)" to="(660,730)"/>
+ <wire from="(590,250)" to="(660,250)"/>
+ <wire from="(590,370)" to="(660,370)"/>
+ <wire from="(590,410)" to="(660,410)"/>
+ <wire from="(590,450)" to="(660,450)"/>
+ <wire from="(590,330)" to="(660,330)"/>
+ <wire from="(590,290)" to="(660,290)"/>
+ <wire from="(590,690)" to="(660,690)"/>
+ <wire from="(590,650)" to="(660,650)"/>
+ <wire from="(590,570)" to="(660,570)"/>
+ <wire from="(590,610)" to="(660,610)"/>
+ <wire from="(590,210)" to="(660,210)"/>
+ <wire from="(590,170)" to="(660,170)"/>
+ <comp lib="0" loc="(920,820)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="2"/>
+ <a name="label" val="sel"/>
+ </comp>
+ <comp lib="2" loc="(410,300)" name="Multiplexer">
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="2" loc="(700,300)" name="Multiplexer">
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(980,650)" name="Probe">
+ <a name="radix" val="16"/>
+ </comp>
+ <comp lib="0" loc="(810,720)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux0"/>
+ </comp>
+ <comp lib="0" loc="(160,490)" name="Splitter">
+ <a name="incoming" val="7"/>
+ <a name="appear" val="center"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="0"/>
+ <a name="bit4" val="0"/>
+ <a name="bit5" val="1"/>
+ <a name="bit6" val="1"/>
+ </comp>
+ <comp lib="2" loc="(410,680)" name="Multiplexer">
+ <a name="selloc" val="tr"/>
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(450,680)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux1"/>
+ </comp>
+ <comp lib="0" loc="(740,300)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux2"/>
+ </comp>
+ <comp lib="2" loc="(700,680)" name="Multiplexer">
+ <a name="selloc" val="tr"/>
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(190,510)" name="Tunnel">
+ <a name="width" val="2"/>
+ <a name="label" val="sel"/>
+ </comp>
+ <comp lib="0" loc="(1030,740)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="16"/>
+ <a name="label" val="data_out"/>
+ </comp>
+ <comp lib="0" loc="(450,300)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux0"/>
+ </comp>
+ <comp lib="0" loc="(860,730)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux1"/>
+ </comp>
+ <comp lib="0" loc="(860,750)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux3"/>
+ </comp>
+ <comp lib="0" loc="(810,740)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux2"/>
+ </comp>
+ <comp lib="0" loc="(140,490)" name="Pin">
+ <a name="width" val="7"/>
+ <a name="label" val="addr"/>
+ </comp>
+ <comp lib="2" loc="(950,740)" name="Multiplexer">
+ <a name="select" val="2"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(740,680)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux3"/>
+ </comp>
+ <comp lib="0" loc="(260,140)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8010"/>
+ </comp>
+ <comp lib="0" loc="(300,150)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xc200"/>
+ </comp>
+ <comp lib="0" loc="(260,160)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8477"/>
+ </comp>
+ <comp lib="0" loc="(300,170)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(260,180)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(300,190)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(260,200)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee1e"/>
+ </comp>
+ <comp lib="0" loc="(300,210)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8461"/>
+ </comp>
+ <comp lib="0" loc="(260,220)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(300,230)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(260,240)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(300,250)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee24"/>
+ </comp>
+ <comp lib="0" loc="(260,260)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8473"/>
+ </comp>
+ <comp lib="0" loc="(300,270)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(260,280)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(300,290)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(260,300)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee21"/>
+ </comp>
+ <comp lib="0" loc="(300,310)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8464"/>
+ </comp>
+ <comp lib="0" loc="(260,320)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(300,330)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(260,340)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(300,350)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee27"/>
+ </comp>
+ <comp lib="0" loc="(260,360)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8478"/>
+ </comp>
+ <comp lib="0" loc="(300,370)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x1650"/>
+ </comp>
+ <comp lib="0" loc="(260,380)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xa802"/>
+ </comp>
+ <comp lib="0" loc="(300,390)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xb002"/>
+ </comp>
+ <comp lib="0" loc="(260,400)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xee2a"/>
+ </comp>
+ <comp lib="0" loc="(300,410)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xd801"/>
+ </comp>
+ <comp lib="0" loc="(260,420)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xda02"/>
+ </comp>
+ <comp lib="0" loc="(300,430)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xbfe3"/>
+ </comp>
+ <comp lib="0" loc="(260,440)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8864"/>
+ </comp>
+ <comp lib="0" loc="(300,450)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a64"/>
+ </comp>
+ <comp lib="0" loc="(260,520)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(300,530)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x889c"/>
+ </comp>
+ <comp lib="0" loc="(260,540)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a9c"/>
+ </comp>
+ <comp lib="0" loc="(300,550)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(260,560)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8832"/>
+ </comp>
+ <comp lib="0" loc="(300,570)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8ace"/>
+ </comp>
+ <comp lib="0" loc="(260,580)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(300,590)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x88ce"/>
+ </comp>
+ <comp lib="0" loc="(260,600)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a32"/>
+ </comp>
+ <comp lib="0" loc="(300,610)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ <comp lib="0" loc="(260,620)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8800"/>
+ </comp>
+ <comp lib="0" loc="(300,630)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0x8a00"/>
+ </comp>
+ <comp lib="0" loc="(260,640)" name="Constant">
+ <a name="width" val="16"/>
+ <a name="value" val="0xfe00"/>
+ </comp>
+ </circuit>
</project>
diff --git a/CPU/logi_compiler_sources/prog.lsn b/CPU/logi_compiler_sources/prog.lsn
index 0bf9bca44e3739fc09ebdb787831c131239b066c..c50d1035e2c5378e0bce8e3e70870077d55baac4 100644
--- a/CPU/logi_compiler_sources/prog.lsn
+++ b/CPU/logi_compiler_sources/prog.lsn
@@ -1,5 +1,5 @@
# COMPILE
-# python .\logi_compiler.py .\prog.lsn .\instructions.circ
+# python logi_compiler.py prog.lsn instructions.circ
# ############# PERIPHERALS ADDRESSES ############
# 0x10 UART BLUETOOTH IN
@@ -13,6 +13,7 @@
# 0x61 'a'
# 0x73 's'
# 0x64 'd'
+# 0x78 'x'
# ################################################
@@ -34,7 +35,6 @@
# LEFT = 50
# ################################################
-
loop:
# SET ADDR TO READ UART
r0 = 0x10
@@ -48,6 +48,7 @@ r2 = 0x77
r3 = r1 - r2
# IF THE UART IN == 'w' , GO FORWARD
bcz 2
+b 2
bl [r7] goforward
# CHECK FOR a
@@ -55,23 +56,36 @@ r2 = 0x61
r3 = r1 - r2
# IF THE UART IN == 'a' , GO LEFT
bcz 2
+b 2
bl [r7] goleft
-# CHECK FOR S
+# CHECK FOR s
r2 = 0x73
r3 = r1 - r2
# IF THE UART IN == 's' , GO BACKWARD
bcz 2
+b 2
bl [r7] gobackward
-
# CHECK FOR d
r2 = 0x64
r3 = r1 - r2
# IF THE UART IN == 'd' , GO RIGHT
bcz 2
-bl [r7] goleft
+b 2
+bl [r7] goright
+
+# CHECK FOR x
+r2 = 0x78
+r3 = r1 - r2
+# IF THE UART IN == 'x'
+bcz 2
+b 2
+bl [r7] stop
+
+st r4,1[r0]
+st r5,2[r0]
# BRANCH LOOP - GET BACK UP TO LOOP LABEL
b loop
@@ -104,4 +118,10 @@ r4 = 0xCE
r5 = 50
br[r7]
+# FONCTION TO SET REGS AT FORWARD
+stop:
+r4 = 0
+r5 = 0
+br[r7]
+
# ################################################
diff --git a/CPU/logi_compiler_sources/prog2.lsn b/CPU/logi_compiler_sources/prog2.lsn
new file mode 100644
index 0000000000000000000000000000000000000000..1d87f47150011357f1273125a5b4aa6adaf59805
--- /dev/null
+++ b/CPU/logi_compiler_sources/prog2.lsn
@@ -0,0 +1,12 @@
+# COMPILE
+# python logi_compiler.py prog.lsn instructions.circ
+
+
+loop:
+r0 = 0x10
+
+r4 = 100
+r5 = 100
+st r4,1[r0]
+st r5,2[r0]
+b loop
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.jou b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.jou
index ce2a0765569e00d607e8b208668fa6c0952ace0a..e7eb7fcfe17fa2d7f7340403b1205566bf8dc1c7 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.jou
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.jou
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:24:59 2022
-# Process ID: 109728
+# Start of session at: Sun Jun 19 15:24:55 2022
+# Process ID: 150011
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
# Command line: vivado -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//vivadoLoadBitStream.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
index 31982bfb91c496db306d1b2ae2128256379c6377..4cdfc8d3e0fb9bfcf073cddb77ac2e64055b9c6e 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:24:59 2022
-# Process ID: 109728
+# Start of session at: Sun Jun 19 15:24:55 2022
+# Process ID: 150011
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
# Command line: vivado -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//vivadoLoadBitStream.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
@@ -48,7 +48,7 @@ WARNING: 'close_hw' is deprecated, please use 'close_hw_manager' instead.
**** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-109728-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
-INFO: [Common 17-206] Exiting Webtalk at Fri Jun 17 15:25:14 2022...
+source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-150011-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
+INFO: [Common 17-206] Exiting Webtalk at Sun Jun 19 15:25:07 2022...
# exit
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:25:14 2022...
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:25:07 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107233.backup.jou b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145228.backup.jou
similarity index 91%
rename from LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107233.backup.jou
rename to LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145228.backup.jou
index a6b5813d8005d336d1181b29e7e934f314c56917..17e0058cc319b7dd3b3ff96c06d250053ac383cd 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107233.backup.jou
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145228.backup.jou
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:21:52 2022
-# Process ID: 107233
+# Start of session at: Sun Jun 19 15:21:47 2022
+# Process ID: 145228
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
# Command line: vivado -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//vivadoCreateProject.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107233.backup.log b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145228.backup.log
similarity index 95%
rename from LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107233.backup.log
rename to LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145228.backup.log
index a2958592c855c354fcfa58503e6804d13507706c..3560d2d8a30cf13cb786d82b9fdaeca9002c930f 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107233.backup.log
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145228.backup.log
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:21:52 2022
-# Process ID: 107233
+# Start of session at: Sun Jun 19 15:21:47 2022
+# Process ID: 145228
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
# Command line: vivado -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//vivadoCreateProject.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
@@ -19,24 +19,22 @@ source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/Shift_Register_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_BUS_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_8_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_2_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM8_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_entity.vhd"
@@ -45,11 +43,14 @@ source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_NOT_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/TOP_entity.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/toplevel/LogisimToplevelShell_entity.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd"
@@ -57,25 +58,23 @@ source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd"
+CRITICAL WARNING: [Vivado 12-3645] Please note that adding or importing multiple files, one at a time, can be performance intensive. Both add_files and import_files commands accept multiple files as input, and passing a collection of multiple files to a single add_files or import_files commands can offer significant performance improvement.
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd"
-CRITICAL WARNING: [Vivado 12-3645] Please note that adding or importing multiple files, one at a time, can be performance intensive. Both add_files and import_files commands accept multiple files as input, and passing a collection of multiple files to a single add_files or import_files commands can offer significant performance improvement.
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM8_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd"
@@ -84,12 +83,15 @@ CRITICAL WARNING: [Vivado 12-3645] Please note that adding or importing multiple
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/TOP_behavior.vhd"
-# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd"
+# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd"
# add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd"
# add_files -fileset constrs_1 "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc"
# exit
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:22:00 2022...
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:21:56 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107357.backup.jou b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145356.backup.jou
similarity index 91%
rename from LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107357.backup.jou
rename to LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145356.backup.jou
index 7bf4ed3f017a2f19f82a9f632233271d6f03081d..b9eb645869da8f6810d390ab28e6b744f074e212 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107357.backup.jou
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145356.backup.jou
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:22:11 2022
-# Process ID: 107357
+# Start of session at: Sun Jun 19 15:22:07 2022
+# Process ID: 145356
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
# Command line: vivado -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//vivadoGenerateBitStream.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107357.backup.log b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145356.backup.log
similarity index 74%
rename from LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107357.backup.log
rename to LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145356.backup.log
index c49bdfaf26ae08f6bb7ee60fceb00dda4ef8d8e7..0d8642f8203850db921eb2c0bf57f88ef8ac7d45 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_107357.backup.log
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado_145356.backup.log
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:22:11 2022
-# Process ID: 107357
+# Start of session at: Sun Jun 19 15:22:07 2022
+# Process ID: 145356
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
# Command line: vivado -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/scripts//vivadoGenerateBitStream.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vivado.log
@@ -16,10 +16,10 @@ Finished scanning sources
WARNING: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.srcs/sources_1'.
# update_compile_order -fileset sources_1
# launch_runs synth_1
-[Fri Jun 17 15:22:22 2022] Launched synth_1...
+[Sun Jun 19 15:22:17 2022] Launched synth_1...
Run output will be captured here: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/runme.log
# wait_on_run synth_1
-[Fri Jun 17 15:22:22 2022] Waiting for synth_1 to finish...
+[Sun Jun 19 15:22:17 2022] Waiting for synth_1 to finish...
*** Running vivado
with args -log LogisimToplevelShell.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source LogisimToplevelShell.tcl
@@ -38,80 +38,72 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 107574
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20081 ; free virtual = 33425
----------------------------------------------------------------------------------
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:286]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:287]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:294]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:295]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:296]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:297]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:298]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:299]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:300]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:301]
+INFO: [Synth 8-7075] Helper process launched with PID 145612
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20147 ; free virtual = 32953
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:263]
+WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:271]
INFO: [Synth 8-638] synthesizing module 'LogisimToplevelShell' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'TOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd:15' bound to instance 'TOP_0' of component 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:82]
+INFO: [Synth 8-3491] module 'TOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd:15' bound to instance 'TOP_0' of component 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:112]
INFO: [Synth 8-638] synthesizing module 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:112]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:123]
INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP' (1#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'CPU_RAM24' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd:15' bound to instance 'CPU_RAM' of component 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:126]
+INFO: [Synth 8-3491] module 'CPU_RAM24' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd:15' bound to instance 'CPU_RAM' of component 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:137]
INFO: [Synth 8-638] synthesizing module 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:146]
+INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:147]
INFO: [Synth 8-638] synthesizing module 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'NOT_GATE' (2#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:150]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:151]
INFO: [Synth 8-638] synthesizing module 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'AND_GATE' (3#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:156]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:157]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:162]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:163]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_8' (4#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:176]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:177]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2' (5#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:184]
+INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:185]
INFO: [Synth 8-638] synthesizing module 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'Demultiplexer_8' (6#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:197]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:198]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:207]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:208]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:217]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:218]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:227]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:228]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:237]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:238]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:247]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:248]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:257]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:258]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:267]
-INFO: [Synth 8-3491] module 'CPU_RAM16' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd:15' bound to instance 'RAM16_PROCESSOR' of component 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:281]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:268]
+INFO: [Synth 8-3491] module 'CPU_RAM16' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd:15' bound to instance 'RAM16_PROCESSOR' of component 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:282]
INFO: [Synth 8-638] synthesizing module 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:10]
INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:80]
Parameter BubblesMask bound to: 0 - type: integer
@@ -153,188 +145,138 @@ INFO: [Synth 8-256] done synthesizing module 'CPU_RAM8' (7#1) [/home/jonas.stirn
INFO: [Synth 8-3491] module 'CPU_RAM8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM8_entity.vhd:15' bound to instance 'RAM8_2' of component 'CPU_RAM8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:116]
INFO: [Synth 8-256] done synthesizing module 'CPU_RAM16' (8#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'CPU_RAM24' (9#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_SIGNED_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd:15' bound to instance 'peri1' of component 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:137]
-INFO: [Synth 8-638] synthesizing module 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:124]
-INFO: [Synth 8-638] synthesizing module 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'NOT_GATE_BUS' (10#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:129]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:137]
-INFO: [Synth 8-638] synthesizing module 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Adder' (11#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_entity.vhd:15' bound to instance 'PERI' of component 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:150]
-INFO: [Synth 8-638] synthesizing module 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
- Parameter TwosComplement bound to: 0 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:88]
-INFO: [Synth 8-638] synthesizing module 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter TwosComplement bound to: 0 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter ExtendedBits bound to: 11 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:97]
-INFO: [Synth 8-638] synthesizing module 'Adder__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ExtendedBits bound to: 11 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Adder__parameterized1' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:106]
-INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
- Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'PERI_PWM' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'PERI_SIGNED_PWM' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_SIGNED_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd:15' bound to instance 'peri2' of component 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:143]
INFO: [Synth 8-3491] module 'CPU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_entity.vhd:15' bound to instance 'CPU_1' of component 'CPU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:149]
INFO: [Synth 8-638] synthesizing module 'CPU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:226]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:234]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:232]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:240]
INFO: [Synth 8-638] synthesizing module 'AND_GATE__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE__parameterized2' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE__parameterized2' (9#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:238]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:246]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:244]
+INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:252]
INFO: [Synth 8-638] synthesizing module 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'OR_GATE' (15#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_5' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:250]
- Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_6' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:256]
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE' (10#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd:15' bound to instance 'GATE_7' of component 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:262]
+INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd:15' bound to instance 'GATE_5' of component 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:258]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS' (11#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_8' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:269]
+INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_6' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:265]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:276]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:284]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:292]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:272]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:300]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:280]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_2__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2__parameterized2' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2__parameterized2' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:308]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:288]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_6' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:316]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_7' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:324]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:296]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_8' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:332]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:304]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_9' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:340]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_10' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:348]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:356]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_6' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:312]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:365]
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:320]
+INFO: [Synth 8-638] synthesizing module 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized1' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Comparator' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_2' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:374]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_2' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:329]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_3' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:383]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_3' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:338]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_4' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:392]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_4' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:347]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_5' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:401]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_5' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:356]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_6' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:410]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_6' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:365]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_7' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:419]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_7' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:374]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:428]
-INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:383]
+INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:393]
+INFO: [Synth 8-638] synthesizing module 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Adder' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_7' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:402]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:438]
-INFO: [Synth 8-3491] module 'CPU_INSTRUCTION_MEMORY' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd:15' bound to instance 'CIM_1' of component 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:452]
-INFO: [Synth 8-638] synthesizing module 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_4' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:283]
-INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_4' (18#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:293]
-INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_32' (19#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:331]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:369]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:407]
-INFO: [Synth 8-256] done synthesizing module 'CPU_INSTRUCTION_MEMORY' (20#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'ALU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_entity.vhd:15' bound to instance 'ALU1' of component 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:456]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:410]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_8' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:420]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_9' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:428]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_7' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:436]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_2' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:442]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-3491] module 'OR_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_8' of component 'OR_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:451]
+INFO: [Synth 8-638] synthesizing module 'OR_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd:10]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE_3_INPUTS' (15#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'ALU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_entity.vhd:15' bound to instance 'ALU1' of component 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:462]
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
INFO: [Synth 8-3491] module 'Multiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:145]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_8' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_8' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:158]
Parameter TwosComplement bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:172]
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized3' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized3' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized2' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_ADD_SOUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_entity.vhd:15' bound to instance 'ALU_ADDER' of component 'ALU_ADD_SOUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:185]
INFO: [Synth 8-638] synthesizing module 'ALU_ADD_SOUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:89]
+INFO: [Synth 8-638] synthesizing module 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'NOT_GATE_BUS' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 6 - type: integer
INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:94]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 6 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized1' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized1' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:101]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS__parameterized3' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized3' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized3' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:108]
Parameter NrOfBits bound to: 8 - type: integer
@@ -342,18 +284,18 @@ INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnem
Parameter ExtendedBits bound to: 9 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:122]
-INFO: [Synth 8-256] done synthesizing module 'ALU_ADD_SOUS' (22#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_ADD_SOUS' (18#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_SHIFT' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_entity.vhd:15' bound to instance 'ALU_SH' of component 'ALU_SHIFT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:193]
INFO: [Synth 8-638] synthesizing module 'ALU_SHIFT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
INFO: [Synth 8-3491] module 'Multiplexer_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:114]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_2' (23#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_2' (19#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:121]
-INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT' (24#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT' (20#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_SHIFT_SIGNED' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_entity.vhd:15' bound to instance 'ALU_SH_SIGNED' of component 'ALU_SHIFT_SIGNED' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:199]
INFO: [Synth 8-638] synthesizing module 'ALU_SHIFT_SIGNED' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT_SIGNED' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT_SIGNED' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_AND' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_entity.vhd:15' bound to instance 'ALU_ET' of component 'ALU_AND' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:204]
INFO: [Synth 8-638] synthesizing module 'ALU_AND' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
@@ -362,8 +304,8 @@ INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Doc
INFO: [Synth 8-638] synthesizing module 'AND_GATE_BUS__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS__parameterized1' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_AND' (26#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS__parameterized1' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_AND' (22#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_OR' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_entity.vhd:15' bound to instance 'ALU_OU' of component 'ALU_OR' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:209]
INFO: [Synth 8-638] synthesizing module 'ALU_OR' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
@@ -372,110 +314,164 @@ INFO: [Synth 8-3491] module 'OR_GATE_BUS' declared at '/home/jonas.stirnema/Docu
INFO: [Synth 8-638] synthesizing module 'OR_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'OR_GATE_BUS' (27#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_OR' (28#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE_BUS' (23#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_OR' (24#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_NOT' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_entity.vhd:15' bound to instance 'ALU_NON' of component 'ALU_NOT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:214]
INFO: [Synth 8-638] synthesizing module 'ALU_NOT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:43]
-INFO: [Synth 8-256] done synthesizing module 'ALU_NOT' (29#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU' (30#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'CPU_REG_BANK' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd:15' bound to instance 'CRB' of component 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:466]
-INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+INFO: [Synth 8-256] done synthesizing module 'ALU_NOT' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU' (26#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'CPU_REG_BANK' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd:15' bound to instance 'CRB' of component 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:472]
INFO: [Synth 8-638] synthesizing module 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:107]
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:121]
+INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:135]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:148]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:158]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:168]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:178]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:188]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:198]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:208]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'CPU_REG_BANK' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'CPU' (32#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
-INFO: [Synth 8-638] synthesizing module 'PERI_UART_RCV_16_BITS_9600' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:218]
+INFO: [Synth 8-256] done synthesizing module 'CPU_REG_BANK' (27#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'CPU_INSTRUCTION_MEMORY' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd:15' bound to instance 'CIM_1' of component 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:483]
+INFO: [Synth 8-638] synthesizing module 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_4' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:313]
+INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_4' (28#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:323]
+INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_32' (29#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:361]
+INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+ Parameter NrOfBits bound to: 16 - type: integer
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'CPU_INSTRUCTION_MEMORY' (30#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'CPU' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-638] synthesizing module 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
+ Parameter TwosComplement bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter TwosComplement bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized4' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 11 - type: integer
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Adder__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 11 - type: integer
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Adder__parameterized2' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
-INFO: [Synth 8-638] synthesizing module 'D_FLIPFLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'D_FLIPFLOP' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
- Parameter mode bound to: 0 - type: integer
- Parameter ClkEdge bound to: 1 - type: integer
- Parameter max_val bound to: 17 - type: integer
- Parameter width bound to: 5 - type: integer
-INFO: [Synth 8-638] synthesizing module 'LogisimCounter' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
- Parameter mode bound to: 0 - type: integer
- Parameter ClkEdge bound to: 1 - type: integer
- Parameter max_val bound to: 17 - type: integer
- Parameter width bound to: 5 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'LogisimCounter' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_PWM' (32#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_SIGNED_PWM' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'PERI_UART_RCVE_9600' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:10]
+ Parameter BubblesMask bound to: 0 - type: integer
+ Parameter BubblesMask bound to: 0 - type: integer
+ Parameter BubblesMask bound to: 0 - type: integer
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized5' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter NrOfBits bound to: 4 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized6' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized5' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 4 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized6' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 5 - type: integer
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized7' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 5 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized7' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
- Parameter BubblesMask bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized8' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter ActiveLevel bound to: 1 - type: integer
+INFO: [Synth 8-638] synthesizing module 'D_FLIPFLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
+ Parameter ActiveLevel bound to: 1 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'D_FLIPFLOP' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
Parameter mode bound to: 0 - type: integer
Parameter ClkEdge bound to: 1 - type: integer
Parameter max_val bound to: 10410 - type: integer
Parameter width bound to: 16 - type: integer
-INFO: [Synth 8-638] synthesizing module 'LogisimCounter__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'LogisimCounter' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
Parameter mode bound to: 0 - type: integer
Parameter ClkEdge bound to: 1 - type: integer
Parameter max_val bound to: 10410 - type: integer
Parameter width bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'LogisimCounter__parameterized1' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'LogisimCounter' (35#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfParBits bound to: 17 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfParBits bound to: 9 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
Parameter NrOfBits bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'Shift_Register' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
- Parameter NrOfParBits bound to: 17 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfParBits bound to: 9 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
Parameter NrOfBits bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
INFO: [Synth 8-638] synthesizing module 'SingleBitShiftReg' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'SingleBitShiftReg' (35#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Shift_Register' (36#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
-INFO: [Synth 8-256] done synthesizing module 'PERI_UART_RCV_16_BITS_9600' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'TOP' (38#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'LogisimToplevelShell' (39#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
+ Parameter NrOfStages bound to: 9 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'SingleBitShiftReg' (36#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Shift_Register' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
+ Parameter mode bound to: 0 - type: integer
+ Parameter ClkEdge bound to: 1 - type: integer
+ Parameter max_val bound to: 9 - type: integer
+ Parameter width bound to: 4 - type: integer
+INFO: [Synth 8-638] synthesizing module 'LogisimCounter__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+ Parameter mode bound to: 0 - type: integer
+ Parameter ClkEdge bound to: 1 - type: integer
+ Parameter max_val bound to: 9 - type: integer
+ Parameter width bound to: 4 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'LogisimCounter__parameterized1' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_UART_RCVE_9600' (38#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'TOP' (39#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'LogisimToplevelShell' (40#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2127.602 ; gain = 2.840 ; free physical = 20168 ; free virtual = 33512
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2128.602 ; gain = 3.840 ; free physical = 20204 ; free virtual = 33011
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2142.445 ; gain = 17.684 ; free physical = 20163 ; free virtual = 33507
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2144.445 ; gain = 19.684 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2142.445 ; gain = 17.684 ; free physical = 20163 ; free virtual = 33507
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2144.445 ; gain = 19.684 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2142.445 ; gain = 0.000 ; free physical = 20166 ; free virtual = 33510
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2144.445 ; gain = 0.000 ; free physical = 20193 ; free virtual = 33000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -486,33 +482,31 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
Resolution: To avoid this warning, move constraints listed in [.Xil/LogisimToplevelShell_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20112 ; free virtual = 33455
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20109 ; free virtual = 32917
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20112 ; free virtual = 33455
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20109 ; free virtual = 32917
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20156 ; free virtual = 33500
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/GATE_4' (OR_GATE) to 'TOP_0/CPU_1/GATE_6'
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_3' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_4'
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_3' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_5'
+INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_4' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_5'
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
@@ -520,28 +514,28 @@ Detailed RTL Component Info :
+---Adders :
2 Input 16 Bit Adders := 1
3 Input 11 Bit Adders := 2
- 3 Input 9 Bit Adders := 4
- 2 Input 5 Bit Adders := 1
+ 3 Input 9 Bit Adders := 5
+ 2 Input 4 Bit Adders := 1
+---Registers :
- 17 Bit Registers := 1
16 Bit Registers := 1
10 Bit Registers := 2
+ 9 Bit Registers := 1
8 Bit Registers := 34
- 5 Bit Registers := 1
- 4 Bit Registers := 1
+ 4 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
- 2 Input 17 Bit Muxes := 1
4 Input 16 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 5
+ 2 Input 16 Bit Muxes := 6
2 Input 14 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 32
- 2 Input 5 Bit Muxes := 1
- 3 Input 5 Bit Muxes := 1
+ 2 Input 9 Bit Muxes := 1
+ 2 Input 8 Bit Muxes := 30
+ 2 Input 4 Bit Muxes := 1
+ 3 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 6
2 Input 2 Bit Muxes := 2
- 2 Input 1 Bit Muxes := 3
- 3 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 2
+ 3 Input 1 Bit Muxes := 1
+ 4 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
@@ -558,25 +552,40 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20148 ; free virtual = 33493
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20171 ; free virtual = 32983
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+ROM: Preliminary Mapping Report
++-----------------------+--------------------+---------------+----------------+
+|Module Name | RTL Object | Depth x Width | Implemented As |
++-----------------------+--------------------+---------------+----------------+
+|CPU_INSTRUCTION_MEMORY | MUX_2/MuxOut | 32x16 | LUT |
+|CPU | CIM_1/MUX_2/MuxOut | 32x16 | LUT |
++-----------------------+--------------------+---------------+----------------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20027 ; free virtual = 33373
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20058 ; free virtual = 32870
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20027 ; free virtual = 33373
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20058 ; free virtual = 32870
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33371
+Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20056 ; free virtual = 32868
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -594,37 +603,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -641,48 +650,49 @@ Report Cell Usage:
| |Cell |Count |
+------+-------+------+
|1 |BUFG | 1|
-|2 |CARRY4 | 4|
-|3 |LUT1 | 1|
-|4 |LUT2 | 1|
-|5 |LUT3 | 3|
-|6 |LUT4 | 22|
-|7 |LUT5 | 6|
-|8 |LUT6 | 2|
-|9 |FDCE | 39|
-|10 |FDRE | 9|
-|11 |IBUF | 3|
-|12 |OBUF | 13|
+|2 |CARRY4 | 11|
+|3 |LUT1 | 6|
+|4 |LUT2 | 12|
+|5 |LUT3 | 83|
+|6 |LUT4 | 47|
+|7 |LUT5 | 75|
+|8 |LUT6 | 173|
+|9 |MUXF7 | 11|
+|10 |FDCE | 298|
+|11 |FDRE | 29|
+|12 |IBUF | 3|
+|13 |OBUF | 23|
+------+-------+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 2311.164 ; gain = 17.684 ; free physical = 20069 ; free virtual = 33415
-Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20068 ; free virtual = 33414
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2311.227 ; gain = 19.684 ; free physical = 20110 ; free virtual = 32921
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20110 ; free virtual = 32921
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20152 ; free virtual = 33497
-INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20181 ; free virtual = 32993
+INFO: [Netlist 29-17] Analyzing 22 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20098 ; free virtual = 33444
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20129 ; free virtual = 32940
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
-223 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
+223 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 2311.164 ; gain = 186.727 ; free physical = 20240 ; free virtual = 33585
+synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:45 . Memory (MB): peak = 2311.227 ; gain = 186.789 ; free physical = 20265 ; free virtual = 33077
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file LogisimToplevelShell_utilization_synth.rpt -pb LogisimToplevelShell_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:23:01 2022...
-[Fri Jun 17 15:23:12 2022] synth_1 finished
-wait_on_run: Time (s): cpu = 00:00:30 ; elapsed = 00:00:49 . Memory (MB): peak = 2124.703 ; gain = 0.000 ; free physical = 21055 ; free virtual = 34396
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:23:09 2022...
+[Sun Jun 19 15:23:19 2022] synth_1 finished
+wait_on_run: Time (s): cpu = 00:00:35 ; elapsed = 00:01:02 . Memory (MB): peak = 2124.699 ; gain = 0.000 ; free physical = 21084 ; free virtual = 33892
# launch_runs impl_1 -to_step write_bitstream -jobs 8
-[Fri Jun 17 15:23:15 2022] Launched impl_1...
+[Sun Jun 19 15:23:19 2022] Launched impl_1...
Run output will be captured here: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/runme.log
# wait_on_run impl_1
-[Fri Jun 17 15:23:15 2022] Waiting for impl_1 to finish...
+[Sun Jun 19 15:23:19 2022] Waiting for impl_1 to finish...
*** Running vivado
with args -log LogisimToplevelShell.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source LogisimToplevelShell.tcl -notrace
@@ -698,21 +708,21 @@ Command: link_design -top LogisimToplevelShell -part xc7a35tcpg236-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20470 ; free virtual = 33812
-INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20500 ; free virtual = 33307
+INFO: [Netlist 29-17] Analyzing 22 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc]
Finished Parsing XDC File [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2180.629 ; gain = 0.000 ; free physical = 20384 ; free virtual = 33725
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2180.629 ; gain = 0.000 ; free physical = 20413 ; free virtual = 33221
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
-link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:21 . Memory (MB): peak = 2180.629 ; gain = 56.191 ; free physical = 20384 ; free virtual = 33726
+link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 2180.629 ; gain = 56.191 ; free physical = 20413 ; free virtual = 33221
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -723,54 +733,54 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2244.660 ; gain = 64.031 ; free physical = 20372 ; free virtual = 33714
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2244.660 ; gain = 64.031 ; free physical = 20403 ; free virtual = 33211
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 1d54d65c5
+Ending Cache Timing Information Task | Checksum: 1e074b608
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2553.629 ; gain = 308.969 ; free physical = 20001 ; free virtual = 33342
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2557.598 ; gain = 312.938 ; free physical = 20033 ; free virtual = 32841
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 1 Retarget | Checksum: 1d54d65c5
+Phase 1 Retarget | Checksum: 11034237b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 2 Constant propagation | Checksum: 1d54d65c5
+Phase 2 Constant propagation | Checksum: 11034237b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
-Phase 3 Sweep | Checksum: 1a4cae45e
+Phase 3 Sweep | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+INFO: [Opt 31-389] Phase Sweep created 16 cells and removed 0 cells
Phase 4 BUFG optimization
-Phase 4 BUFG optimization | Checksum: 1a4cae45e
+Phase 4 BUFG optimization | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 5 Shift Register Optimization | Checksum: 1a4cae45e
+Phase 5 Shift Register Optimization | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
-Phase 6 Post Processing Netlist | Checksum: 1a4cae45e
+Phase 6 Post Processing Netlist | Checksum: 10ab69b4e
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
@@ -779,9 +789,9 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
-| Retarget | 0 | 0 | 0 |
+| Retarget | 0 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
-| Sweep | 0 | 0 | 0 |
+| Sweep | 16 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
@@ -791,37 +801,37 @@ Opt_design Change Summary
Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-Ending Logic Optimization Task | Checksum: 1617bafc8
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+Ending Logic Optimization Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 1617bafc8
+Ending Power Optimization Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 1617bafc8
+Ending Final Cleanup Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-Ending Netlist Obfuscation Task | Checksum: 1617bafc8
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+Ending Netlist Obfuscation Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
-opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2716.566 ; gain = 535.938 ; free physical = 19838 ; free virtual = 33179
+opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2719.566 ; gain = 538.938 ; free physical = 19868 ; free virtual = 32676
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2756.586 ; gain = 0.000 ; free physical = 19835 ; free virtual = 33177
+Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2759.586 ; gain = 0.000 ; free physical = 19863 ; free virtual = 32672
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LogisimToplevelShell_drc_opted.rpt -pb LogisimToplevelShell_drc_opted.pb -rpx LogisimToplevelShell_drc_opted.rpx
Command: report_drc -file LogisimToplevelShell_drc_opted.rpt -pb LogisimToplevelShell_drc_opted.pb -rpx LogisimToplevelShell_drc_opted.rpx
@@ -848,115 +858,115 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19814 ; free virtual = 33156
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11077ac8a
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e889e152
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19814 ; free virtual = 33156
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19815 ; free virtual = 33156
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d068e46b
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f460932d
-Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 1169f904c
+Phase 1.3 Build Placer Netlist Model | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 1169f904c
+Phase 1.4 Constrain Clocks/Macros | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
-Phase 1 Placer Initialization | Checksum: 1169f904c
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
+Phase 1 Placer Initialization | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19826 ; free virtual = 32634
Phase 2 Global Placement
Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1169f904c
+Phase 2.1 Floorplanning | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33139
+Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19826 ; free virtual = 32634
Phase 2.2 Global Placement Core
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
-Phase 2.2 Global Placement Core | Checksum: 1b0e606ff
+Phase 2.2 Global Placement Core | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
-Phase 2 Global Placement | Checksum: 1b0e606ff
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
+Phase 2 Global Placement | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 1b0e606ff
+Phase 3.1 Commit Multi Column Macros | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b5e198c1
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1204b2476
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 132110350
+Phase 3.3 Area Swap Optimization | Checksum: 1213bc1fe
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 1a4bbab23
+Phase 3.4 Pipeline Register Optimization | Checksum: 1213bc1fe
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 1a4d9f964
+Phase 3.5 Small Shape Detail Placement | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 1a4d9f964
+Phase 3.6 Re-assign LUT pins | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 1a4d9f964
+Phase 3.7 Pipeline Register Optimization | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
-Phase 3 Detail Placement | Checksum: 1a4d9f964
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
+Phase 3 Detail Placement | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
-Phase 4.1 Post Commit Optimization | Checksum: 1a4d9f964
+Phase 4.1 Post Commit Optimization | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 1a4d9f964
+Phase 4.2 Post Placement Cleanup | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
Phase 4.3 Placer Reporting
-Phase 4.3 Placer Reporting | Checksum: 1a4d9f964
+Phase 4.3 Placer Reporting | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Phase 4.4 Final Placement Cleanup | Checksum: 128f427ac
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Phase 4.4 Final Placement Cleanup | Checksum: 2114adf7b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 128f427ac
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2114adf7b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Ending Placer Task | Checksum: 560976a7
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Ending Placer Task | Checksum: 124ee9605
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
INFO: [Common 17-83] Releasing license: Implementation
42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
@@ -965,13 +975,13 @@ Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19794 ; free virtual = 33136
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19816 ; free virtual = 32625
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file LogisimToplevelShell_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19796 ; free virtual = 32604
INFO: [runtcl-4] Executing : report_utilization -file LogisimToplevelShell_utilization_placed.rpt -pb LogisimToplevelShell_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file LogisimToplevelShell_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19793 ; free virtual = 33135
+report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19820 ; free virtual = 32628
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -984,7 +994,7 @@ Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19758 ; free virtual = 33100
+Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19785 ; free virtual = 32595
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -997,30 +1007,30 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
-Checksum: PlaceDB: 5cdd313 ConstDB: 0 ShapeSum: 503ba394 RouteDB: 0
+Checksum: PlaceDB: 9d948354 ConstDB: 0 ShapeSum: 875a12b1 RouteDB: 0
Phase 1 Build RT Design
-Phase 1 Build RT Design | Checksum: 20ce1e99
+Phase 1 Build RT Design | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19653 ; free virtual = 32995
-Post Restoration Checksum: NetGraph: b839e54 NumContArr: 154a8045 Constraints: 0 Timing: 0
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19676 ; free virtual = 32485
+Post Restoration Checksum: NetGraph: 8169e9d4 NumContArr: b2b18a6e Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 20ce1e99
+Phase 2.1 Fix Topology Constraints | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19620 ; free virtual = 32962
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19643 ; free virtual = 32452
Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 20ce1e99
+Phase 2.2 Pre Route Cleanup | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19620 ; free virtual = 32962
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19643 ; free virtual = 32452
Number of Nodes with overlaps = 0
-Phase 2 Router Initialization | Checksum: f83c145e
+Phase 2 Router Initialization | Checksum: 16420495
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19612 ; free virtual = 32954
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
@@ -1028,50 +1038,50 @@ Router Utilization Summary
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
- Number of Failed Nets = 82
+ Number of Failed Nets = 698
(Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 82
+ Number of Unrouted Nets = 698
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 3 Initial Routing
-Phase 3 Initial Routing | Checksum: cb847c6f
+Phase 3 Initial Routing | Checksum: 561368d2
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19615 ; free virtual = 32957
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 97
Number of Nodes with overlaps = 0
-Phase 4.1 Global Iteration 0 | Checksum: ce53bb98
+Phase 4.1 Global Iteration 0 | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
-Phase 4 Rip-up And Reroute | Checksum: ce53bb98
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
+Phase 4 Rip-up And Reroute | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 5 Delay and Skew Optimization
-Phase 5 Delay and Skew Optimization | Checksum: ce53bb98
+Phase 5 Delay and Skew Optimization | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
-Phase 6.1 Hold Fix Iter | Checksum: ce53bb98
+Phase 6.1 Hold Fix Iter | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
-Phase 6 Post Hold Fix | Checksum: ce53bb98
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
+Phase 6 Post Hold Fix | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 7 Route finalize
Router Utilization Summary
- Global Vertical Routing Utilization = 0.0401818 %
- Global Horizontal Routing Utilization = 0.0300625 %
+ Global Vertical Routing Utilization = 0.191422 %
+ Global Horizontal Routing Utilization = 0.228136 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -1083,9 +1093,9 @@ Router Utilization Summary
Congestion Report
North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions.
-South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
-East Dir 1x1 Area, Max Cong = 11.7647%, No Congested Regions.
-West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 24.3243%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 25%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 36.7647%, No Congested Regions.
------------------------------
Reporting congestion hotspots
@@ -1107,36 +1117,36 @@ Direction: West
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Phase 7 Route finalize | Checksum: ce53bb98
+Phase 7 Route finalize | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 8 Verifying routed nets
Verification completed successfully
-Phase 8 Verifying routed nets | Checksum: ce53bb98
+Phase 8 Verifying routed nets | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19613 ; free virtual = 32955
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Phase 9 Depositing Routes
-Phase 9 Depositing Routes | Checksum: 156701353
+Phase 9 Depositing Routes | Checksum: 11350863b
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
INFO: [Route 35-16] Router Completed Successfully
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19647 ; free virtual = 32989
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19669 ; free virtual = 32478
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
60 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
-route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2924.484 ; gain = 89.090 ; free physical = 19645 ; free virtual = 32987
+route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2931.570 ; gain = 91.945 ; free physical = 19665 ; free virtual = 32474
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2924.492 ; gain = 0.000 ; free physical = 19639 ; free virtual = 32982
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2931.570 ; gain = 0.000 ; free physical = 19661 ; free virtual = 32472
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LogisimToplevelShell_drc_routed.rpt -pb LogisimToplevelShell_drc_routed.pb -rpx LogisimToplevelShell_drc_routed.rpx
Command: report_drc -file LogisimToplevelShell_drc_routed.rpt -pb LogisimToplevelShell_drc_routed.pb -rpx LogisimToplevelShell_drc_routed.rpx
@@ -1200,9 +1210,9 @@ INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
90 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:22 . Memory (MB): peak = 3258.129 ; gain = 193.297 ; free physical = 19614 ; free virtual = 32958
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:24:39 2022...
-[Fri Jun 17 15:24:44 2022] impl_1 finished
-wait_on_run: Time (s): cpu = 00:00:00.76 ; elapsed = 00:01:29 . Memory (MB): peak = 2124.703 ; gain = 0.000 ; free physical = 21054 ; free virtual = 34399
+write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:29 . Memory (MB): peak = 3264.066 ; gain = 171.223 ; free physical = 19628 ; free virtual = 32440
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:24:43 2022...
+[Sun Jun 19 15:24:43 2022] impl_1 finished
+wait_on_run: Time (s): cpu = 00:00:52 ; elapsed = 00:01:23 . Memory (MB): peak = 2124.699 ; gain = 0.000 ; free physical = 21076 ; free virtual = 33888
# exit
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:24:44 2022...
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:24:43 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/synthesis.wdf b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/synthesis.wdf
index 4b20c3db57c05c2955a5df247f485102281b6f46..5b45f9c1029a7db93af825b597c19413d5dfa4de 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/synthesis.wdf
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/synthesis.wdf
@@ -34,7 +34,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313773:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323331312e3136344d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3138362e3732374d42:00:00
-eof:3105153205
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323173:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323331312e3232374d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3138362e3738394d42:00:00
+eof:629031889
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/webtalk_pa.xml b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/webtalk_pa.xml
index 9215025e34be991dc2590efea03db2aeaeee0440..3d8017a6db163e8a99ed8e2260b01ffaec101b68 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/webtalk_pa.xml
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.cache/wt/webtalk_pa.xml
@@ -3,9 +3,9 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Fri Jun 17 15:23:15 2022">
+<application name="pa" timeStamp="Sun Jun 19 15:23:19 2022">
<section name="Project Information" visible="false">
-<property name="ProjectID" value="24a17b707600439697980dffda942e02" type="ProjectID"/>
+<property name="ProjectID" value="2dde2e97990f4890b729e4bb3aa0a4b9" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.init_design.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.init_design.begin.rst
index fbdf717fa1f260aecd75afb1ffd975b10250a2c4..3eeadca0372e0cb973a1f7e2d2fa639ae2629cfe 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.init_design.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.init_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="107830">
+ <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="145875">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.opt_design.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.opt_design.begin.rst
index fbdf717fa1f260aecd75afb1ffd975b10250a2c4..3eeadca0372e0cb973a1f7e2d2fa639ae2629cfe 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.opt_design.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.opt_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="107830">
+ <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="145875">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.phys_opt_design.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.phys_opt_design.begin.rst
index fbdf717fa1f260aecd75afb1ffd975b10250a2c4..3eeadca0372e0cb973a1f7e2d2fa639ae2629cfe 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.phys_opt_design.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.phys_opt_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="107830">
+ <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="145875">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.place_design.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.place_design.begin.rst
index fbdf717fa1f260aecd75afb1ffd975b10250a2c4..3eeadca0372e0cb973a1f7e2d2fa639ae2629cfe 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.place_design.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.place_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="107830">
+ <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="145875">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.route_design.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.route_design.begin.rst
index fbdf717fa1f260aecd75afb1ffd975b10250a2c4..3eeadca0372e0cb973a1f7e2d2fa639ae2629cfe 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.route_design.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.route_design.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="107830">
+ <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="145875">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.vivado.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.vivado.begin.rst
index 87684244c4b8d55e7b3b7f67908e064fa79efc62..35d1d0d531da953037eb96977225c7e671b62ce8 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.vivado.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="jonas.stirnema" Host="" Pid="107790" HostCore="8" HostMemory="32659472">
+ <Process Command="vivado" Owner="jonas.stirnema" Host="" Pid="145835" HostCore="8" HostMemory="32659472">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.write_bitstream.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.write_bitstream.begin.rst
index fbdf717fa1f260aecd75afb1ffd975b10250a2c4..3eeadca0372e0cb973a1f7e2d2fa639ae2629cfe 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.write_bitstream.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/.write_bitstream.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="107830">
+ <Process Command=".planAhead." Owner="jonas.stirnema" Host="" Pid="145875">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.bit b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.bit
index 066dac964150e6c4e99a5b5bf65c1028aa92d58b..de7b3d811798d8aa1ff2243735ab8561cf7923e9 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.bit and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.bit differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.vdi b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.vdi
index 107b280015688c88a621a0c21113bce9e89b05c5..427ea30462a7c2c38b61904950b462ffdc1e8862 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.vdi
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.vdi
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:23:13 2022
-# Process ID: 107830
+# Start of session at: Sun Jun 19 15:23:21 2022
+# Process ID: 145875
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1
# Command line: vivado -log LogisimToplevelShell.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source LogisimToplevelShell.tcl -notrace
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.vdi
@@ -14,21 +14,21 @@ Command: link_design -top LogisimToplevelShell -part xc7a35tcpg236-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20470 ; free virtual = 33812
-INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20500 ; free virtual = 33307
+INFO: [Netlist 29-17] Analyzing 22 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc]
Finished Parsing XDC File [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2180.629 ; gain = 0.000 ; free physical = 20384 ; free virtual = 33725
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2180.629 ; gain = 0.000 ; free physical = 20413 ; free virtual = 33221
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
-link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:21 . Memory (MB): peak = 2180.629 ; gain = 56.191 ; free physical = 20384 ; free virtual = 33726
+link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 2180.629 ; gain = 56.191 ; free physical = 20413 ; free virtual = 33221
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -39,54 +39,54 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2244.660 ; gain = 64.031 ; free physical = 20372 ; free virtual = 33714
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2244.660 ; gain = 64.031 ; free physical = 20403 ; free virtual = 33211
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 1d54d65c5
+Ending Cache Timing Information Task | Checksum: 1e074b608
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2553.629 ; gain = 308.969 ; free physical = 20001 ; free virtual = 33342
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2557.598 ; gain = 312.938 ; free physical = 20033 ; free virtual = 32841
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 1 Retarget | Checksum: 1d54d65c5
+Phase 1 Retarget | Checksum: 11034237b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 2 Constant propagation | Checksum: 1d54d65c5
+Phase 2 Constant propagation | Checksum: 11034237b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
-Phase 3 Sweep | Checksum: 1a4cae45e
+Phase 3 Sweep | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+INFO: [Opt 31-389] Phase Sweep created 16 cells and removed 0 cells
Phase 4 BUFG optimization
-Phase 4 BUFG optimization | Checksum: 1a4cae45e
+Phase 4 BUFG optimization | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 5 Shift Register Optimization | Checksum: 1a4cae45e
+Phase 5 Shift Register Optimization | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
-Phase 6 Post Processing Netlist | Checksum: 1a4cae45e
+Phase 6 Post Processing Netlist | Checksum: 10ab69b4e
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
@@ -95,9 +95,9 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
-| Retarget | 0 | 0 | 0 |
+| Retarget | 0 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
-| Sweep | 0 | 0 | 0 |
+| Sweep | 16 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
@@ -107,37 +107,37 @@ Opt_design Change Summary
Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-Ending Logic Optimization Task | Checksum: 1617bafc8
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+Ending Logic Optimization Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 1617bafc8
+Ending Power Optimization Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 1617bafc8
+Ending Final Cleanup Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-Ending Netlist Obfuscation Task | Checksum: 1617bafc8
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+Ending Netlist Obfuscation Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
-opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2716.566 ; gain = 535.938 ; free physical = 19838 ; free virtual = 33179
+opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2719.566 ; gain = 538.938 ; free physical = 19868 ; free virtual = 32676
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2756.586 ; gain = 0.000 ; free physical = 19835 ; free virtual = 33177
+Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2759.586 ; gain = 0.000 ; free physical = 19863 ; free virtual = 32672
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LogisimToplevelShell_drc_opted.rpt -pb LogisimToplevelShell_drc_opted.pb -rpx LogisimToplevelShell_drc_opted.rpx
Command: report_drc -file LogisimToplevelShell_drc_opted.rpt -pb LogisimToplevelShell_drc_opted.pb -rpx LogisimToplevelShell_drc_opted.rpx
@@ -164,115 +164,115 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19814 ; free virtual = 33156
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11077ac8a
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e889e152
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19814 ; free virtual = 33156
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19815 ; free virtual = 33156
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d068e46b
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f460932d
-Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 1169f904c
+Phase 1.3 Build Placer Netlist Model | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 1169f904c
+Phase 1.4 Constrain Clocks/Macros | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
-Phase 1 Placer Initialization | Checksum: 1169f904c
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
+Phase 1 Placer Initialization | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19826 ; free virtual = 32634
Phase 2 Global Placement
Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1169f904c
+Phase 2.1 Floorplanning | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33139
+Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19826 ; free virtual = 32634
Phase 2.2 Global Placement Core
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
-Phase 2.2 Global Placement Core | Checksum: 1b0e606ff
+Phase 2.2 Global Placement Core | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
-Phase 2 Global Placement | Checksum: 1b0e606ff
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
+Phase 2 Global Placement | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 1b0e606ff
+Phase 3.1 Commit Multi Column Macros | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b5e198c1
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1204b2476
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 132110350
+Phase 3.3 Area Swap Optimization | Checksum: 1213bc1fe
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 1a4bbab23
+Phase 3.4 Pipeline Register Optimization | Checksum: 1213bc1fe
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 1a4d9f964
+Phase 3.5 Small Shape Detail Placement | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 1a4d9f964
+Phase 3.6 Re-assign LUT pins | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 1a4d9f964
+Phase 3.7 Pipeline Register Optimization | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
-Phase 3 Detail Placement | Checksum: 1a4d9f964
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
+Phase 3 Detail Placement | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
-Phase 4.1 Post Commit Optimization | Checksum: 1a4d9f964
+Phase 4.1 Post Commit Optimization | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 1a4d9f964
+Phase 4.2 Post Placement Cleanup | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
Phase 4.3 Placer Reporting
-Phase 4.3 Placer Reporting | Checksum: 1a4d9f964
+Phase 4.3 Placer Reporting | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Phase 4.4 Final Placement Cleanup | Checksum: 128f427ac
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Phase 4.4 Final Placement Cleanup | Checksum: 2114adf7b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 128f427ac
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2114adf7b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Ending Placer Task | Checksum: 560976a7
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Ending Placer Task | Checksum: 124ee9605
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
INFO: [Common 17-83] Releasing license: Implementation
42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
@@ -281,13 +281,13 @@ Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19794 ; free virtual = 33136
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19816 ; free virtual = 32625
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file LogisimToplevelShell_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19796 ; free virtual = 32604
INFO: [runtcl-4] Executing : report_utilization -file LogisimToplevelShell_utilization_placed.rpt -pb LogisimToplevelShell_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file LogisimToplevelShell_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19793 ; free virtual = 33135
+report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19820 ; free virtual = 32628
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -300,7 +300,7 @@ Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19758 ; free virtual = 33100
+Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19785 ; free virtual = 32595
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -313,30 +313,30 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
-Checksum: PlaceDB: 5cdd313 ConstDB: 0 ShapeSum: 503ba394 RouteDB: 0
+Checksum: PlaceDB: 9d948354 ConstDB: 0 ShapeSum: 875a12b1 RouteDB: 0
Phase 1 Build RT Design
-Phase 1 Build RT Design | Checksum: 20ce1e99
+Phase 1 Build RT Design | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19653 ; free virtual = 32995
-Post Restoration Checksum: NetGraph: b839e54 NumContArr: 154a8045 Constraints: 0 Timing: 0
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19676 ; free virtual = 32485
+Post Restoration Checksum: NetGraph: 8169e9d4 NumContArr: b2b18a6e Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 20ce1e99
+Phase 2.1 Fix Topology Constraints | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19620 ; free virtual = 32962
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19643 ; free virtual = 32452
Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 20ce1e99
+Phase 2.2 Pre Route Cleanup | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19620 ; free virtual = 32962
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19643 ; free virtual = 32452
Number of Nodes with overlaps = 0
-Phase 2 Router Initialization | Checksum: f83c145e
+Phase 2 Router Initialization | Checksum: 16420495
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19612 ; free virtual = 32954
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
@@ -344,50 +344,50 @@ Router Utilization Summary
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
- Number of Failed Nets = 82
+ Number of Failed Nets = 698
(Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 82
+ Number of Unrouted Nets = 698
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 3 Initial Routing
-Phase 3 Initial Routing | Checksum: cb847c6f
+Phase 3 Initial Routing | Checksum: 561368d2
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19615 ; free virtual = 32957
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 97
Number of Nodes with overlaps = 0
-Phase 4.1 Global Iteration 0 | Checksum: ce53bb98
+Phase 4.1 Global Iteration 0 | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
-Phase 4 Rip-up And Reroute | Checksum: ce53bb98
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
+Phase 4 Rip-up And Reroute | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 5 Delay and Skew Optimization
-Phase 5 Delay and Skew Optimization | Checksum: ce53bb98
+Phase 5 Delay and Skew Optimization | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
-Phase 6.1 Hold Fix Iter | Checksum: ce53bb98
+Phase 6.1 Hold Fix Iter | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
-Phase 6 Post Hold Fix | Checksum: ce53bb98
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
+Phase 6 Post Hold Fix | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 7 Route finalize
Router Utilization Summary
- Global Vertical Routing Utilization = 0.0401818 %
- Global Horizontal Routing Utilization = 0.0300625 %
+ Global Vertical Routing Utilization = 0.191422 %
+ Global Horizontal Routing Utilization = 0.228136 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -399,9 +399,9 @@ Router Utilization Summary
Congestion Report
North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions.
-South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
-East Dir 1x1 Area, Max Cong = 11.7647%, No Congested Regions.
-West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 24.3243%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 25%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 36.7647%, No Congested Regions.
------------------------------
Reporting congestion hotspots
@@ -423,36 +423,36 @@ Direction: West
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Phase 7 Route finalize | Checksum: ce53bb98
+Phase 7 Route finalize | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 8 Verifying routed nets
Verification completed successfully
-Phase 8 Verifying routed nets | Checksum: ce53bb98
+Phase 8 Verifying routed nets | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19613 ; free virtual = 32955
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Phase 9 Depositing Routes
-Phase 9 Depositing Routes | Checksum: 156701353
+Phase 9 Depositing Routes | Checksum: 11350863b
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
INFO: [Route 35-16] Router Completed Successfully
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19647 ; free virtual = 32989
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19669 ; free virtual = 32478
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
60 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
-route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2924.484 ; gain = 89.090 ; free physical = 19645 ; free virtual = 32987
+route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2931.570 ; gain = 91.945 ; free physical = 19665 ; free virtual = 32474
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2924.492 ; gain = 0.000 ; free physical = 19639 ; free virtual = 32982
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2931.570 ; gain = 0.000 ; free physical = 19661 ; free virtual = 32472
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LogisimToplevelShell_drc_routed.rpt -pb LogisimToplevelShell_drc_routed.pb -rpx LogisimToplevelShell_drc_routed.rpx
Command: report_drc -file LogisimToplevelShell_drc_routed.rpt -pb LogisimToplevelShell_drc_routed.pb -rpx LogisimToplevelShell_drc_routed.rpx
@@ -516,5 +516,5 @@ INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
90 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:22 . Memory (MB): peak = 3258.129 ; gain = 193.297 ; free physical = 19614 ; free virtual = 32958
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:24:39 2022...
+write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:29 . Memory (MB): peak = 3264.066 ; gain = 171.223 ; free physical = 19628 ; free virtual = 32440
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:24:43 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpt
index 2d54914621191807390787f0732738ca0c319d8c..f6c4abacfd1aee0f094fb15bc0cb0aec2a31976f 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:24:16 2022
+| Date : Sun Jun 19 15:24:13 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_bus_skew -warn_on_violation -file LogisimToplevelShell_bus_skew_routed.rpt -pb LogisimToplevelShell_bus_skew_routed.pb -rpx LogisimToplevelShell_bus_skew_routed.rpx
| Design : LogisimToplevelShell
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpx b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpx
index 75fd729baa681f6bf13782a37089ec42461b4bc6..87ea2383af9223b3b7100ef87fcd031b20903093 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpx and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_bus_skew_routed.rpx differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_clock_utilization_routed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_clock_utilization_routed.rpt
index 6421d18ae479e10c7da0dd426427c5e3c740b4ce..707d36f74963e502b13fc32ed845651c085129f1 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_clock_utilization_routed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_clock_utilization_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:24:16 2022
+| Date : Sun Jun 19 15:24:13 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_clock_utilization -file LogisimToplevelShell_clock_utilization_routed.rpt
| Design : LogisimToplevelShell
@@ -21,8 +21,6 @@ Table of Contents
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y0
-8. Clock Region Cell Placement per Global Clock: Region X0Y1
-9. Clock Region Cell Placement per Global Clock: Region X1Y1
1. Clock Primitive Utilization
------------------------------
@@ -46,7 +44,7 @@ Table of Contents
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------------------+----------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------------------+----------------------------+
-| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 3 | 48 | 0 | | | FPGA_INPUT_PIN_2_IBUF_BUFG_inst/O | FPGA_INPUT_PIN_2_IBUF_BUFG |
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 343 | 0 | | | FPGA_INPUT_PIN_2_IBUF_BUFG_inst/O | FPGA_INPUT_PIN_2_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+-----------------------------------+----------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
@@ -72,10 +70,10 @@ Table of Contents
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
-| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 42 | 1200 | 4 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 343 | 1200 | 127 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
-| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
-| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 5 | 1500 | 1 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
+| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
@@ -90,7 +88,7 @@ All Modules
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
-| Y1 | 1 | 1 |
+| Y1 | 0 | 0 |
| Y0 | 1 | 0 |
+----+----+----+
@@ -101,7 +99,7 @@ All Modules
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------------------+
-| g0 | BUFG/O | n/a | | | | 48 | 0 | 0 | 0 | FPGA_INPUT_PIN_2_IBUF_BUFG |
+| g0 | BUFG/O | n/a | | | | 343 | 0 | 0 | 0 | FPGA_INPUT_PIN_2_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+----------------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
@@ -109,49 +107,23 @@ All Modules
**** GT Loads column represents load cell count of GT types
-+----+-----+----+
-| | X0 | X1 |
-+----+-----+----+
-| Y2 | 0 | 0 |
-| Y1 | 1 | 5 |
-| Y0 | 42 | 0 |
-+----+-----+----+
++----+------+----+
+| | X0 | X1 |
++----+------+----+
+| Y2 | 0 | 0 |
+| Y1 | 0 | 0 |
+| Y0 | 343 | 0 |
++----+------+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y0
------------------------------------------------------------
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-| g0 | n/a | BUFG/O | None | 42 | 0 | 42 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FPGA_INPUT_PIN_2_IBUF_BUFG |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-* Clock Loads column represents the clock pin loads (pin count)
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
-
-
-8. Clock Region Cell Placement per Global Clock: Region X0Y1
-------------------------------------------------------------
-
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-| g0 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FPGA_INPUT_PIN_2_IBUF_BUFG |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-* Clock Loads column represents the clock pin loads (pin count)
-** Non-Clock Loads column represents the non-clock pin loads (pin count)
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
-
-
-9. Clock Region Cell Placement per Global Clock: Region X1Y1
-------------------------------------------------------------
-
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
-| g0 | n/a | BUFG/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FPGA_INPUT_PIN_2_IBUF_BUFG |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------------+
+| g0 | n/a | BUFG/O | None | 343 | 0 | 343 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FPGA_INPUT_PIN_2_IBUF_BUFG |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
@@ -170,5 +142,5 @@ set_property LOC IOB_X1Y26 [get_ports FPGA_INPUT_PIN_2]
#startgroup
create_pblock {CLKAG_FPGA_INPUT_PIN_2_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_FPGA_INPUT_PIN_2_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="FPGA_INPUT_PIN_2_IBUF_BUFG"}]]]
-resize_pblock [get_pblocks {CLKAG_FPGA_INPUT_PIN_2_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
+resize_pblock [get_pblocks {CLKAG_FPGA_INPUT_PIN_2_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
#endgroup
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_control_sets_placed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_control_sets_placed.rpt
index 476d5467ea3c186d7e0487adc56d60c9143a958c..2ba6e7ef7e59bbce02cb3153f411ba5332fd5090 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_control_sets_placed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_control_sets_placed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:23:54 2022
+| Date : Sun Jun 19 15:23:57 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_control_sets -verbose -file LogisimToplevelShell_control_sets_placed.rpt
| Design : LogisimToplevelShell
@@ -23,11 +23,11 @@ Table of Contents
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
-| Total control sets | 5 |
-| Minimum number of control sets | 5 |
+| Total control sets | 37 |
+| Minimum number of control sets | 37 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
-| Unused register locations in slices containing registers | 16 |
+| Unused register locations in slices containing registers | 25 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
@@ -39,15 +39,15 @@ Table of Contents
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
-| Total control sets | 5 |
-| >= 0 to < 4 | 2 |
-| >= 4 to < 6 | 0 |
+| Total control sets | 37 |
+| >= 0 to < 4 | 0 |
+| >= 4 to < 6 | 1 |
| >= 6 to < 8 | 0 |
-| >= 8 to < 10 | 1 |
+| >= 8 to < 10 | 30 |
| >= 10 to < 12 | 0 |
-| >= 12 to < 14 | 0 |
-| >= 14 to < 16 | 0 |
-| >= 16 | 2 |
+| >= 12 to < 14 | 1 |
+| >= 14 to < 16 | 1 |
+| >= 16 | 4 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design
@@ -58,11 +58,11 @@ Table of Contents
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
-| No | No | No | 1 | 1 |
-| No | No | Yes | 1 | 1 |
+| No | No | No | 21 | 7 |
+| No | No | Yes | 17 | 8 |
| No | Yes | No | 0 | 0 |
-| Yes | No | No | 8 | 3 |
-| Yes | No | Yes | 38 | 15 |
+| Yes | No | No | 16 | 6 |
+| Yes | No | Yes | 289 | 94 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
@@ -70,14 +70,46 @@ Table of Contents
4. Detailed Control Set Information
-----------------------------------
-+-----------------------------+---------------------------------------------------------+-----------------------+------------------+----------------+--------------+
-| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
-+-----------------------------+---------------------------------------------------------+-----------------------+------------------+----------------+--------------+
-| FPGA_INPUT_PIN_2_IBUF_BUFG | | | 1 | 1 | 1.00 |
-| FPGA_INPUT_PIN_2_IBUF_BUFG | | FPGA_INPUT_PIN_1_IBUF | 1 | 1 | 1.00 |
-| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/peri_uart/FF_LATCH_2/DONE | | 3 | 8 | 2.67 |
-| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/peri_uart/FF_LATCH_1/s_current_state_reg_reg_0[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 16 | 5.33 |
-| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/peri_uart/COUNTER_2/E[0] | FPGA_INPUT_PIN_1_IBUF | 12 | 22 | 1.83 |
-+-----------------------------+---------------------------------------------------------+-----------------------+------------------+----------------+--------------+
++-----------------------------+------------------------------------------------------+-----------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++-----------------------------+------------------------------------------------------+-----------------------+------------------+----------------+--------------+
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_28[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 4 | 1.33 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/E[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_14[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_11[0] | FPGA_INPUT_PIN_1_IBUF | 4 | 8 | 2.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_12[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_13[0] | FPGA_INPUT_PIN_1_IBUF | 4 | 8 | 2.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_4[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 8 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_15[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_16[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_3[0] | FPGA_INPUT_PIN_1_IBUF | 1 | 8 | 8.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_5[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_10[0] | FPGA_INPUT_PIN_1_IBUF | 1 | 8 | 8.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_8[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_9[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_9[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_8[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 8 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_10[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 8 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_7[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 8 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_12[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_21[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_11[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 8 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_20[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 8 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_24[0] | FPGA_INPUT_PIN_1_IBUF | 1 | 8 | 8.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_19[0] | FPGA_INPUT_PIN_1_IBUF | 4 | 8 | 2.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_26[0] | FPGA_INPUT_PIN_1_IBUF | 1 | 8 | 8.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_23[0] | FPGA_INPUT_PIN_1_IBUF | 1 | 8 | 8.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_22[0] | FPGA_INPUT_PIN_1_IBUF | 6 | 8 | 1.33 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_25[0] | FPGA_INPUT_PIN_1_IBUF | 5 | 8 | 1.60 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_7[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 8 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_5[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 8 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]_6[0] | FPGA_INPUT_PIN_1_IBUF | 2 | 9 | 4.50 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/UART1/COUNTER_1/E[0] | FPGA_INPUT_PIN_1_IBUF | 3 | 13 | 4.33 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]_6[0] | FPGA_INPUT_PIN_1_IBUF | 9 | 15 | 1.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/UART1/FF_LATCH_1/DONE | | 6 | 16 | 2.67 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | TOP_0/UART1/FF_LATCH_2/s_current_state_reg_reg_0[0] | FPGA_INPUT_PIN_1_IBUF | 4 | 16 | 4.00 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | | FPGA_INPUT_PIN_1_IBUF | 8 | 17 | 2.12 |
+| FPGA_INPUT_PIN_2_IBUF_BUFG | | | 7 | 21 | 3.00 |
++-----------------------------+------------------------------------------------------+-----------------------+------------------+----------------+--------------+
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_opted.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_opted.rpt
index 12ed82eed567fd66afb7e7810ef582fa7d2e6753..345e31db4e84437f1cbbad3b7b6ae9db1dfd157b 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_opted.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_opted.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:23:51 2022
+| Date : Sun Jun 19 15:23:54 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_drc -file LogisimToplevelShell_drc_opted.rpt -pb LogisimToplevelShell_drc_opted.pb -rpx LogisimToplevelShell_drc_opted.rpx
| Design : LogisimToplevelShell
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_routed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_routed.rpt
index c02fd7fdf587cd26e8e07ef6de9be19526183f63..f213448e6ce666ee4cea1806a44791df2ce73067 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_routed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_drc_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:24:14 2022
+| Date : Sun Jun 19 15:24:11 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_drc -file LogisimToplevelShell_drc_routed.rpt -pb LogisimToplevelShell_drc_routed.pb -rpx LogisimToplevelShell_drc_routed.rpx
| Design : LogisimToplevelShell
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_io_placed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_io_placed.rpt
index bc10935728c1c493c2f72ddf498224d00a7bc893..a55afc5ca6613f5ee189271f355aee095519d3a7 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_io_placed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_io_placed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:23:54 2022
+| Date : Sun Jun 19 15:23:57 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_io -file LogisimToplevelShell_io_placed.rpt
| Design : LogisimToplevelShell
@@ -25,7 +25,7 @@ Table of Contents
+---------------+
| Total User IO |
+---------------+
-| 16 |
+| 26 |
+---------------+
@@ -48,11 +48,11 @@ Table of Contents
| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
-| A14 | FPGA_OUTPUT_PIN_8 | High Range | IO_L6P_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A14 | FPGA_OUTPUT_PIN_6 | High Range | IO_L6P_T0_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
-| A16 | FPGA_OUTPUT_PIN_12 | High Range | IO_L12P_T1_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A16 | FPGA_OUTPUT_PIN_22 | High Range | IO_L12P_T1_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
-| A18 | FPGA_OUTPUT_PIN_10 | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A18 | FPGA_OUTPUT_PIN_8 | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
@@ -68,8 +68,8 @@ Table of Contents
| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| B15 | FPGA_OUTPUT_PIN_6 | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
-| B16 | FPGA_OUTPUT_PIN_2 | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B15 | FPGA_OUTPUT_PIN_4 | High Range | IO_L11N_T1_SRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B16 | FPGA_OUTPUT_PIN_13 | High Range | IO_L13N_T2_MRCC_16 | OUTPUT | LVCMOS33 | 16 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | |
@@ -103,7 +103,7 @@ Table of Contents
| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
-| E19 | FPGA_OUTPUT_PIN_1 | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| E19 | FPGA_OUTPUT_PIN_12 | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
@@ -159,7 +159,7 @@ Table of Contents
| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
-| L1 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| L1 | FPGA_OUTPUT_PIN_14 | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
@@ -187,7 +187,7 @@ Table of Contents
| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
-| N3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| N3 | FPGA_OUTPUT_PIN_0 | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
@@ -198,9 +198,9 @@ Table of Contents
| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
-| P1 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P1 | FPGA_OUTPUT_PIN_19 | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| P3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| P3 | FPGA_OUTPUT_PIN_1 | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
@@ -218,45 +218,45 @@ Table of Contents
| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
-| U3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | FPGA_OUTPUT_PIN_9 | High Range | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U5 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| U7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U7 | FPGA_OUTPUT_PIN_2 | High Range | IO_L19P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U8 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
-| U14 | FPGA_OUTPUT_PIN_9 | High Range | IO_25_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
-| U15 | FPGA_OUTPUT_PIN_4 | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
-| U16 | FPGA_OUTPUT_PIN_0 | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U14 | FPGA_OUTPUT_PIN_20 | High Range | IO_25_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U15 | FPGA_OUTPUT_PIN_16 | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U16 | FPGA_OUTPUT_PIN_11 | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| U18 | FPGA_INPUT_PIN_1 | High Range | IO_L18N_T2_A11_D27_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
-| U19 | FPGA_OUTPUT_PIN_5 | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U19 | FPGA_OUTPUT_PIN_17 | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| V2 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| V3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | FPGA_OUTPUT_PIN_5 | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
-| V8 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | FPGA_OUTPUT_PIN_3 | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
-| V13 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
-| V14 | FPGA_OUTPUT_PIN_11 | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V13 | FPGA_OUTPUT_PIN_7 | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V14 | FPGA_OUTPUT_PIN_21 | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V15 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| V16 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
| V17 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
-| V19 | FPGA_OUTPUT_PIN_7 | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V19 | FPGA_OUTPUT_PIN_18 | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W2 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
-| W3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| W3 | FPGA_OUTPUT_PIN_10 | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W5 | FPGA_INPUT_PIN_2 | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| W6 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
@@ -271,7 +271,7 @@ Table of Contents
| W15 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
| W16 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
| W17 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
-| W18 | FPGA_OUTPUT_PIN_3 | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| W18 | FPGA_OUTPUT_PIN_15 | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+------------+--------------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.pb
index ccfc7bd65256dcce69f4c7b9a836123f3fbbdf06..df52a92e2511c977a36a34bbde64627d8c4d7d76 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpt
index a41ede73152e37bf9b361d7624ed7e336638dd63..372e7bffbeef28cac8516c074226333d1dfd8c6b 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:24:16 2022
+| Date : Sun Jun 19 15:24:13 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_methodology -file LogisimToplevelShell_methodology_drc_routed.rpt -pb LogisimToplevelShell_methodology_drc_routed.pb -rpx LogisimToplevelShell_methodology_drc_routed.rpx
| Design : LogisimToplevelShell
@@ -23,253 +23,1728 @@ Table of Contents
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
- Violations found: 48
+ Violations found: 343
+-----------+------------------+-----------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+------------------+-----------------------------+------------+
-| TIMING-17 | Critical Warning | Non-clocked sequential cell | 48 |
+| TIMING-17 | Critical Warning | Non-clocked sequential cell | 343 |
+-----------+------------------+-----------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-17#1 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#2 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#3 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#4 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#5 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#6 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#7 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#8 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#9 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_1/s_counter_value_reg[0]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#10 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_1/s_counter_value_reg[1]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#11 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_1/s_counter_value_reg[2]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#12 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_1/s_counter_value_reg[3]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#13 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_1/s_counter_value_reg[4]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#14 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[0]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#15 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[10]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#16 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[11]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_2/s_state_reg_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#17 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[12]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#18 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[13]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#19 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[14]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#20 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[15]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#21 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[1]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#22 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[2]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#23 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[3]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#24 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[4]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_3/s_state_reg_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#25 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[5]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#26 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[6]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#27 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[7]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#28 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[8]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#29 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/COUNTER_2/s_counter_value_reg[9]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#30 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/FF_LATCH_1/s_current_state_reg_reg/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#31 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/FF_LATCH_2/s_current_state_reg_reg/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#32 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[0]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_4/s_state_reg_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#33 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[10]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#34 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[11]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#35 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[12]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#36 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[13]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#37 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[14]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#38 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[15]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#39 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[16]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#40 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[1]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_5/s_state_reg_reg[7]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#41 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[2]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[0]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#42 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[3]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[1]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#43 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[4]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[2]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#44 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[5]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[3]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#45 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[6]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[4]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#46 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[7]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[5]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#47 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[8]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[6]/C is not reached by a timing clock
Related violations: <none>
TIMING-17#48 Critical Warning
Non-clocked sequential cell
-The clock pin TOP_0/peri_uart/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[9]/C is not reached by a timing clock
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_6/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#49 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#50 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#51 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#52 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#53 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#54 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#55 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#56 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_7/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#57 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#58 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#59 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#60 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#61 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#62 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#63 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#64 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/CRB/REGISTER_FILE_8/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#65 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#66 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#67 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#68 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#69 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#70 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#71 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#72 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#73 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#74 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#75 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#76 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_1/REGISTER_FILE_2/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#77 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#78 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#79 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#80 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#81 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#82 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#83 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#84 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#85 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#86 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#87 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#88 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#89 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#90 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#91 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#92 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_2/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#93 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#94 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#95 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#96 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#97 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#98 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#99 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#100 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_3/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#101 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#102 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#103 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#104 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#105 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#106 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#107 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#108 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_4/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#109 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#110 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#111 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#112 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#113 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#114 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#115 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#116 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_5/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#117 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#118 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#119 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#120 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#121 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#122 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#123 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#124 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_6/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#125 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#126 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#127 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#128 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#129 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#130 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#131 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#132 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_7/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#133 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#134 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#135 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#136 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#137 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#138 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#139 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#140 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_1/REGISTER_FILE_8/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#141 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#142 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#143 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#144 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#145 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#146 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#147 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#148 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#149 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#150 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#151 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#152 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#153 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#154 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#155 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#156 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_2/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#157 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#158 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#159 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#160 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#161 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#162 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#163 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#164 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_3/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#165 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#166 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#167 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#168 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#169 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#170 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#171 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#172 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_4/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#173 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#174 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#175 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#176 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#177 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#178 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#179 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#180 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_5/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#181 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#182 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#183 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#184 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#185 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#186 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#187 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#188 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_6/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#189 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#190 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#191 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#192 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#193 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#194 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#195 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#196 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_7/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#197 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#198 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#199 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#200 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#201 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#202 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#203 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#204 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/RAM16_PROCESSOR/RAM8_2/REGISTER_FILE_8/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#205 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#206 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#207 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#208 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#209 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#210 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#211 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#212 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#213 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#214 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#215 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#216 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#217 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#218 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#219 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#220 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_2/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#221 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#222 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#223 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#224 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#225 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#226 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#227 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#228 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_3/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#229 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#230 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#231 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#232 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#233 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#234 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#235 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#236 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_4/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#237 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#238 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#239 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#240 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#241 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#242 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#243 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#244 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_5/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#245 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#246 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[0]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#247 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#248 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[1]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#249 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#250 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[2]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#251 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#252 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[3]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#253 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#254 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[4]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#255 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#256 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[5]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#257 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#258 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#259 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_6/s_state_reg_reg[7]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#260 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#261 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#262 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#263 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#264 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#265 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#266 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#267 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#268 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_7/s_state_reg_reg[7]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#269 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#270 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#271 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#272 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#273 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#274 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#275 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#276 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/CPU_RAM/REGISTER_FILE_8/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#277 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#278 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[0]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#279 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#280 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[1]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#281 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#282 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[2]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#283 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#284 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[3]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#285 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#286 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[4]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#287 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#288 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[5]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#289 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#290 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[6]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#291 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#292 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/REGISTER_FILE_1/s_state_reg_reg[7]_lopt_replica/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#293 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#294 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[10]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#295 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[11]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#296 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[12]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#297 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[13]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#298 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[14]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#299 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[15]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#300 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#301 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#302 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#303 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#304 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#305 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#306 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#307 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[8]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#308 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_1/s_counter_value_reg[9]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#309 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_2/s_counter_value_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#310 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_2/s_counter_value_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#311 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_2/s_counter_value_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#312 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/COUNTER_2/s_counter_value_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#313 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/FF_LATCH_1/s_current_state_reg_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#314 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/FF_LATCH_2/s_current_state_reg_reg/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#315 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#316 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#317 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#318 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#319 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#320 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#321 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#322 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#323 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/UART1/SHIFTER_1/GenBits[0].OneBit/s_state_reg_reg[8]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#324 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#325 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#326 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#327 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#328 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#329 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#330 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#331 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#332 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[8]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#333 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri1/PERI/REGISTER_FILE_1/s_state_reg_reg[9]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#334 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[0]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#335 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[1]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#336 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[2]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#337 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[3]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#338 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[4]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#339 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[5]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#340 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[6]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#341 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[7]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#342 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[8]/C is not reached by a timing clock
+Related violations: <none>
+
+TIMING-17#343 Critical Warning
+Non-clocked sequential cell
+The clock pin TOP_0/peri2/PERI/REGISTER_FILE_1/s_state_reg_reg[9]/C is not reached by a timing clock
Related violations: <none>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpx b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpx
index 6e5a96f13ef25717931383b9ee87b71cd54c37f5..64ce3a83eb298c41196bbc160dceed2fccac199e 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpx and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_methodology_drc_routed.rpx differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_opt.dcp b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_opt.dcp
index 7ed5c3a42c2a3fe863f4df892001ba3f8f41dfa8..28c574ee276aa4d2f8e10e3c9621fab80e664ecd 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_opt.dcp and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_opt.dcp differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_physopt.dcp b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_physopt.dcp
index 75cca7e8d8e00012517448ebdff37be204be0545..84cf0757af3f374a4866310e7b2e6e7d81e0a4ac 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_physopt.dcp and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_physopt.dcp differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_placed.dcp b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_placed.dcp
index 5c2351fbef4beab4d0a60077f5a1562e7259bf67..df07278058a410d071dda061a985c0a8e796dc58 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_placed.dcp and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_placed.dcp differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpt
index e2572f23a6307cdb44631e4895a7c9445cb47d02..650a7d6fa57d4cffe26387ff1ad548139b74acab 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:24:16 2022
+| Date : Sun Jun 19 15:24:13 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_power -file LogisimToplevelShell_power_routed.rpt -pb LogisimToplevelShell_power_summary_routed.pb -rpx LogisimToplevelShell_power_routed.rpx
| Design : LogisimToplevelShell
@@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
-| Total On-Chip Power (W) | 1.073 |
+| Total On-Chip Power (W) | 10.602 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
-| Dynamic (W) | 0.999 |
-| Device Static (W) | 0.074 |
+| Dynamic (W) | 10.452 |
+| Device Static (W) | 0.150 |
| Effective TJA (C/W) | 5.0 |
-| Max Ambient (C) | 79.6 |
-| Junction Temperature (C) | 30.4 |
+| Max Ambient (C) | 32.0 |
+| Junction Temperature (C) | 78.0 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
@@ -52,16 +52,17 @@ Table of Contents
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
-| Slice Logic | 0.117 | 94 | --- | --- |
-| LUT as Logic | 0.091 | 22 | 20800 | 0.11 |
-| CARRY4 | 0.011 | 4 | 8150 | 0.05 |
-| Register | 0.009 | 48 | 41600 | 0.12 |
+| Slice Logic | 4.296 | 777 | --- | --- |
+| LUT as Logic | 4.188 | 322 | 20800 | 1.55 |
+| CARRY4 | 0.042 | 11 | 8150 | 0.13 |
+| Register | 0.036 | 343 | 41600 | 0.82 |
+| F7/F8 Muxes | 0.024 | 11 | 32600 | 0.03 |
| BUFG | 0.006 | 1 | 32 | 3.13 |
-| Others | 0.000 | 6 | --- | --- |
-| Signals | 0.146 | 84 | --- | --- |
-| I/O | 0.737 | 16 | 106 | 15.09 |
-| Static Power | 0.074 | | | |
-| Total | 1.073 | | | |
+| Others | 0.000 | 16 | --- | --- |
+| Signals | 5.226 | 700 | --- | --- |
+| I/O | 0.931 | 26 | 106 | 24.53 |
+| Static Power | 0.150 | | | |
+| Total | 10.602 | | | |
+----------------+-----------+----------+-----------+-----------------+
@@ -71,16 +72,16 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-| Vccint | 1.000 | 0.282 | 0.270 | 0.012 | NA | Unspecified | NA |
-| Vccaux | 1.800 | 0.039 | 0.027 | 0.013 | NA | Unspecified | NA |
-| Vcco33 | 3.300 | 0.207 | 0.206 | 0.001 | NA | Unspecified | NA |
+| Vccint | 1.000 | 9.603 | 9.530 | 0.073 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.054 | 0.034 | 0.020 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.262 | 0.261 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
-| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.002 | 0.000 | 0.002 | NA | Unspecified | NA |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
@@ -135,14 +136,30 @@ Table of Contents
3.1 By Hierarchy
----------------
-+----------------------+-----------+
-| Name | Power (W) |
-+----------------------+-----------+
-| LogisimToplevelShell | 0.999 |
-| TOP_0 | 0.220 |
-| peri_uart | 0.220 |
-| COUNTER_1 | 0.002 |
-| COUNTER_2 | 0.217 |
-+----------------------+-----------+
++-----------------------+-----------+
+| Name | Power (W) |
++-----------------------+-----------+
+| LogisimToplevelShell | 10.452 |
+| TOP_0 | 9.470 |
+| CPU_1 | 8.508 |
+| ADDER2C_1 | 0.046 |
+| ALU1 | 0.119 |
+| CRB | 3.927 |
+| REGISTER_FILE_1 | 0.035 |
+| REGISTER_FILE_2 | 4.380 |
+| CPU_RAM | 0.536 |
+| REGISTER_FILE_2 | 0.052 |
+| REGISTER_FILE_4 | 0.339 |
+| REGISTER_FILE_6 | 0.075 |
+| REGISTER_FILE_7 | 0.003 |
+| REGISTER_FILE_8 | 0.067 |
+| UART1 | 0.215 |
+| COUNTER_1 | 0.207 |
+| COUNTER_2 | 0.007 |
+| peri1 | 0.091 |
+| PERI | 0.091 |
+| peri2 | 0.121 |
+| PERI | 0.121 |
++-----------------------+-----------+
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpx b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpx
index 9f02b031ead8068d77be8782c87e93370532d0e5..b8a928676320187c17420a4e693fb40f5cd78e52 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpx and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_routed.rpx differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_summary_routed.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_summary_routed.pb
index 000e8fe6aceacd0bba9aac7f67af1610216251c4..a44f5a460e736d7700dc7748aa5f4c3a0fdf4944 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_summary_routed.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_power_summary_routed.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.pb
index ea512a3ca6ef619049f6390da217e113eb8050f7..fd44beb51e7e9af2302d006323be3b06a37038f7 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.rpt
index 252be80fd2667943812da41c8a13b106d23f60d8..18074f64f96f7b0a9c1b8f179effe39721045041 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_route_status.rpt
@@ -1,11 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
- # of logical nets.......................... : 123 :
- # of nets not needing routing.......... : 37 :
- # of internally routed nets........ : 37 :
- # of routable nets..................... : 86 :
- # of fully routed nets............. : 86 :
+ # of logical nets.......................... : 821 :
+ # of nets not needing routing.......... : 119 :
+ # of internally routed nets........ : 119 :
+ # of routable nets..................... : 702 :
+ # of fully routed nets............. : 702 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_routed.dcp b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_routed.dcp
index d68fecc32170437bbf23c50be6c2c933d2224e71..6cabd9a96a6c5dafc1ba63ae8130f34f339d6276 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_routed.dcp and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_routed.dcp differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpt
index 540fd6c68fd1788713ac05566424ce5e486e0aee..de4bfac6d248559b7f89020b96bf02d42e4cba24 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:24:16 2022
+| Date : Sun Jun 19 15:24:13 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_timing_summary -max_paths 10 -file LogisimToplevelShell_timing_summary_routed.rpt -pb LogisimToplevelShell_timing_summary_routed.pb -rpx LogisimToplevelShell_timing_summary_routed.rpx -warn_on_violation
| Design : LogisimToplevelShell
@@ -39,12 +39,12 @@ check_timing report
Table of Contents
-----------------
-1. checking no_clock (48)
+1. checking no_clock (343)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
-4. checking unconstrained_internal_endpoints (133)
+4. checking unconstrained_internal_endpoints (954)
5. checking no_input_delay (2)
-6. checking no_output_delay (8)
+6. checking no_output_delay (22)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
@@ -52,9 +52,9 @@ Table of Contents
11. checking partial_output_delay (0)
12. checking latch_loops (0)
-1. checking no_clock (48)
--------------------------
- There are 48 register/latch pins with no clock driven by root clock pin: FPGA_INPUT_PIN_2 (HIGH)
+1. checking no_clock (343)
+--------------------------
+ There are 343 register/latch pins with no clock driven by root clock pin: FPGA_INPUT_PIN_2 (HIGH)
2. checking constant_clock (0)
@@ -67,9 +67,9 @@ Table of Contents
There are 0 register/latch pins which need pulse_width check
-4. checking unconstrained_internal_endpoints (133)
+4. checking unconstrained_internal_endpoints (954)
--------------------------------------------------
- There are 133 pins that are not constrained for maximum delay. (HIGH)
+ There are 954 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
@@ -81,9 +81,9 @@ Table of Contents
There are 0 input ports with no input delay but user has a false path constraint.
-6. checking no_output_delay (8)
--------------------------------
- There are 8 ports with no output delay specified. (HIGH)
+6. checking no_output_delay (22)
+--------------------------------
+ There are 22 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpx b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpx
index 26bae5772eba059adc61c39253b4537026d93ac6..b2c907033fd36ab1d71e3897e0d915f50cd0ff9d 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpx and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_timing_summary_routed.rpx differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.pb
index 8383e90f0a6e49cc35c5771a06256411ac2a04b3..5ac8375a14691fd44e534763d68bbc1383611cff 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.rpt
index c9e1c64ae5847364071a097b81dfe2a61e52a17b..9fb537cb96caf5b16537a10dfbac73aa58251dbd 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_utilization_placed.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:23:54 2022
+| Date : Sun Jun 19 15:23:57 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_utilization -file LogisimToplevelShell_utilization_placed.rpt -pb LogisimToplevelShell_utilization_placed.pb
| Design : LogisimToplevelShell
@@ -31,13 +31,13 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
-| Slice LUTs | 22 | 0 | 20800 | 0.11 |
-| LUT as Logic | 22 | 0 | 20800 | 0.11 |
+| Slice LUTs | 322 | 0 | 20800 | 1.55 |
+| LUT as Logic | 322 | 0 | 20800 | 1.55 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
-| Slice Registers | 48 | 0 | 41600 | 0.12 |
-| Register as Flip Flop | 48 | 0 | 41600 | 0.12 |
+| Slice Registers | 343 | 0 | 41600 | 0.82 |
+| Register as Flip Flop | 343 | 0 | 41600 | 0.82 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
-| F7 Muxes | 0 | 0 | 16300 | 0.00 |
+| F7 Muxes | 11 | 0 | 16300 | 0.07 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
@@ -55,9 +55,9 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
-| 39 | Yes | - | Reset |
+| 306 | Yes | - | Reset |
| 0 | Yes | Set | - |
-| 9 | Yes | Reset | - |
+| 37 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -67,22 +67,22 @@ Table of Contents
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
-| Slice | 24 | 0 | 8150 | 0.29 |
-| SLICEL | 16 | 0 | | |
-| SLICEM | 8 | 0 | | |
-| LUT as Logic | 22 | 0 | 20800 | 0.11 |
+| Slice | 136 | 0 | 8150 | 1.67 |
+| SLICEL | 90 | 0 | | |
+| SLICEM | 46 | 0 | | |
+| LUT as Logic | 322 | 0 | 20800 | 1.55 |
| using O5 output only | 0 | | | |
-| using O6 output only | 9 | | | |
-| using O5 and O6 | 13 | | | |
+| using O6 output only | 249 | | | |
+| using O5 and O6 | 73 | | | |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
-| Slice Registers | 48 | 0 | 41600 | 0.12 |
-| Register driven from within the Slice | 22 | | | |
-| Register driven from outside the Slice | 26 | | | |
-| LUT in front of the register is unused | 22 | | | |
-| LUT in front of the register is used | 4 | | | |
-| Unique Control Sets | 5 | | 8150 | 0.06 |
+| Slice Registers | 343 | 0 | 41600 | 0.82 |
+| Register driven from within the Slice | 52 | | | |
+| Register driven from outside the Slice | 291 | | | |
+| LUT in front of the register is unused | 132 | | | |
+| LUT in front of the register is used | 159 | | | |
+| Unique Control Sets | 37 | | 8150 | 0.45 |
+--------------------------------------------+------+-------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -116,9 +116,9 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
-| Bonded IOB | 16 | 16 | 106 | 15.09 |
-| IOB Master Pads | 7 | | | |
-| IOB Slave Pads | 8 | | | |
+| Bonded IOB | 26 | 26 | 106 | 24.53 |
+| IOB Master Pads | 12 | | | |
+| IOB Slave Pads | 13 | | | |
| Bonded IPADs | 0 | 0 | 10 | 0.00 |
| Bonded OPADs | 0 | 0 | 4 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
@@ -177,17 +177,18 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
-| FDCE | 39 | Flop & Latch |
-| LUT4 | 22 | LUT |
-| OBUF | 13 | IO |
-| FDRE | 9 | Flop & Latch |
-| LUT5 | 6 | LUT |
-| CARRY4 | 4 | CarryLogic |
-| LUT3 | 3 | LUT |
+| FDCE | 306 | Flop & Latch |
+| LUT6 | 173 | LUT |
+| LUT3 | 83 | LUT |
+| LUT5 | 75 | LUT |
+| LUT4 | 47 | LUT |
+| FDRE | 37 | Flop & Latch |
+| OBUF | 23 | IO |
+| LUT2 | 12 | LUT |
+| MUXF7 | 11 | MuxFx |
+| CARRY4 | 11 | CarryLogic |
+| LUT1 | 5 | LUT |
| IBUF | 3 | IO |
-| LUT6 | 2 | LUT |
-| LUT2 | 1 | LUT |
-| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/gen_run.xml b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/gen_run.xml
index bc06894e3fd32a64f2f8506c4fb9e23b15771b3a..f4be074a19ae275bc61a102fc5bbd7c3c136fade 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/gen_run.xml
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/gen_run.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1655472192">
+<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1655644999">
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
<File Type="BITSTR-SYSDEF" Name="LogisimToplevelShell.sysdef"/>
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
@@ -431,6 +431,18 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/../../vhdl/gates/OR_GATE_3_INPUTS_entity.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<File Path="$PPRDIR/../../vhdl/gates/OR_GATE_BUS_entity.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -479,13 +491,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd">
+ <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd">
+ <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/init_design.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/init_design.pb
index 7b17bfb1697b560217e10715517968e605885ffb..a487d9371540cec1461b808f7bbab0222ddb00d4 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/init_design.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/init_design.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/opt_design.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/opt_design.pb
index 105d8ae20b5831fd1fef97203faeb289bfa55f40..d35d0176ff8cff2259b399ff8f220ebd651720b4 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/opt_design.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/opt_design.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/phys_opt_design.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/phys_opt_design.pb
index 22f361794aa013ec066b66d31e1dfa739e00bf3f..111c222f8317e786f3774490fcab81ca05646a2e 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/phys_opt_design.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/phys_opt_design.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/place_design.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/place_design.pb
index 438d8dd29ade2904c15cac37c91674f5beda7dc4..37969a1b6a1d2c8ee1ede354a5fac9415eda2a0a 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/place_design.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/place_design.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/project.wdf b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/project.wdf
index 6dddc1b59579d353619df8622afc6f25faefef5c..7a8ef044392e182e82ef132d723e28b4650f2751 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/project.wdf
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/project.wdf
@@ -1,5 +1,5 @@
version:1
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3736:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3738:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
@@ -27,5 +27,5 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
-5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6432313938613465363064663466343062636263386536393763373562616265:506172656e742050412070726f6a656374204944:00
-eof:3850207768
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6461626139613831663538643430653138346634373563646435386365636433:506172656e742050412070726f6a656374204944:00
+eof:1604076918
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/route_design.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/route_design.pb
index c3a79d9b18503dd1a4c0789b08ff0c79c8893c9c..11efc466312f601dc1b716c3643897eb7a9f34d9 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/route_design.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/route_design.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/runme.log b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/runme.log
index 8d8d269b525adedffc033b38cca09b7cbd427c61..dcf3803d5c8be00e46ceaa6e9e7697e64e62b9c6 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/runme.log
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/runme.log
@@ -13,21 +13,21 @@ Command: link_design -top LogisimToplevelShell -part xc7a35tcpg236-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20470 ; free virtual = 33812
-INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20500 ; free virtual = 33307
+INFO: [Netlist 29-17] Analyzing 22 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc]
Finished Parsing XDC File [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2180.629 ; gain = 0.000 ; free physical = 20384 ; free virtual = 33725
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2180.629 ; gain = 0.000 ; free physical = 20413 ; free virtual = 33221
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
-link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:21 . Memory (MB): peak = 2180.629 ; gain = 56.191 ; free physical = 20384 ; free virtual = 33726
+link_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 2180.629 ; gain = 56.191 ; free physical = 20413 ; free virtual = 33221
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -38,54 +38,54 @@ INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2244.660 ; gain = 64.031 ; free physical = 20372 ; free virtual = 33714
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2244.660 ; gain = 64.031 ; free physical = 20403 ; free virtual = 33211
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 1d54d65c5
+Ending Cache Timing Information Task | Checksum: 1e074b608
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2553.629 ; gain = 308.969 ; free physical = 20001 ; free virtual = 33342
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2557.598 ; gain = 312.938 ; free physical = 20033 ; free virtual = 32841
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 1 Retarget | Checksum: 1d54d65c5
+Phase 1 Retarget | Checksum: 11034237b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 2 Constant propagation | Checksum: 1d54d65c5
+Phase 2 Constant propagation | Checksum: 11034237b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
-Phase 3 Sweep | Checksum: 1a4cae45e
+Phase 3 Sweep | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+INFO: [Opt 31-389] Phase Sweep created 16 cells and removed 0 cells
Phase 4 BUFG optimization
-Phase 4 BUFG optimization | Checksum: 1a4cae45e
+Phase 4 BUFG optimization | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 5 Shift Register Optimization | Checksum: 1a4cae45e
+Phase 5 Shift Register Optimization | Checksum: 1d6787e4b
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
-Phase 6 Post Processing Netlist | Checksum: 1a4cae45e
+Phase 6 Post Processing Netlist | Checksum: 10ab69b4e
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================
@@ -94,9 +94,9 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
-| Retarget | 0 | 0 | 0 |
+| Retarget | 0 | 1 | 0 |
| Constant propagation | 0 | 0 | 0 |
-| Sweep | 0 | 0 | 0 |
+| Sweep | 16 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
@@ -106,37 +106,37 @@ Opt_design Change Summary
Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-Ending Logic Optimization Task | Checksum: 1617bafc8
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+Ending Logic Optimization Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 1617bafc8
+Ending Power Optimization Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 1617bafc8
+Ending Final Cleanup Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
-Ending Netlist Obfuscation Task | Checksum: 1617bafc8
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
+Ending Netlist Obfuscation Task | Checksum: 125c2130b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2716.566 ; gain = 0.000 ; free physical = 19838 ; free virtual = 33179
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2719.566 ; gain = 0.000 ; free physical = 19868 ; free virtual = 32676
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
-opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2716.566 ; gain = 535.938 ; free physical = 19838 ; free virtual = 33179
+opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2719.566 ; gain = 538.938 ; free physical = 19868 ; free virtual = 32676
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2756.586 ; gain = 0.000 ; free physical = 19835 ; free virtual = 33177
+Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2759.586 ; gain = 0.000 ; free physical = 19863 ; free virtual = 32672
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LogisimToplevelShell_drc_opted.rpt -pb LogisimToplevelShell_drc_opted.pb -rpx LogisimToplevelShell_drc_opted.rpx
Command: report_drc -file LogisimToplevelShell_drc_opted.rpt -pb LogisimToplevelShell_drc_opted.pb -rpx LogisimToplevelShell_drc_opted.rpx
@@ -163,115 +163,115 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19814 ; free virtual = 33156
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11077ac8a
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: e889e152
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19814 ; free virtual = 33156
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19815 ; free virtual = 33156
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19844 ; free virtual = 32652
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d068e46b
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f460932d
-Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 1169f904c
+Phase 1.3 Build Placer Netlist Model | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 1169f904c
+Phase 1.4 Constrain Clocks/Macros | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
-Phase 1 Placer Initialization | Checksum: 1169f904c
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19827 ; free virtual = 32635
+Phase 1 Placer Initialization | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33140
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19826 ; free virtual = 32634
Phase 2 Global Placement
Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 1169f904c
+Phase 2.1 Floorplanning | Checksum: 15b1c2fb7
-Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19798 ; free virtual = 33139
+Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19826 ; free virtual = 32634
Phase 2.2 Global Placement Core
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
-Phase 2.2 Global Placement Core | Checksum: 1b0e606ff
+Phase 2.2 Global Placement Core | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
-Phase 2 Global Placement | Checksum: 1b0e606ff
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
+Phase 2 Global Placement | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 1b0e606ff
+Phase 3.1 Commit Multi Column Macros | Checksum: 15c3185c6
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.72 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b5e198c1
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1204b2476
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 132110350
+Phase 3.3 Area Swap Optimization | Checksum: 1213bc1fe
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 1a4bbab23
+Phase 3.4 Pipeline Register Optimization | Checksum: 1213bc1fe
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32621
Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 1a4d9f964
+Phase 3.5 Small Shape Detail Placement | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 1a4d9f964
+Phase 3.6 Re-assign LUT pins | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 1a4d9f964
+Phase 3.7 Pipeline Register Optimization | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
-Phase 3 Detail Placement | Checksum: 1a4d9f964
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
+Phase 3 Detail Placement | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
-Phase 4.1 Post Commit Optimization | Checksum: 1a4d9f964
+Phase 4.1 Post Commit Optimization | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19785 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19812 ; free virtual = 32620
Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 1a4d9f964
+Phase 4.2 Post Placement Cleanup | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
Phase 4.3 Placer Reporting
-Phase 4.3 Placer Reporting | Checksum: 1a4d9f964
+Phase 4.3 Placer Reporting | Checksum: 18dc631ea
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Phase 4.4 Final Placement Cleanup | Checksum: 128f427ac
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Phase 4.4 Final Placement Cleanup | Checksum: 2114adf7b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 128f427ac
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2114adf7b
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
-Ending Placer Task | Checksum: 560976a7
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
+Ending Placer Task | Checksum: 124ee9605
-Time (s): cpu = 00:00:04 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19786 ; free virtual = 33127
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19813 ; free virtual = 32620
INFO: [Common 17-83] Releasing license: Implementation
42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
@@ -280,13 +280,13 @@ Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19794 ; free virtual = 33136
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19816 ; free virtual = 32625
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file LogisimToplevelShell_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19788 ; free virtual = 33129
+report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19796 ; free virtual = 32604
INFO: [runtcl-4] Executing : report_utilization -file LogisimToplevelShell_utilization_placed.rpt -pb LogisimToplevelShell_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file LogisimToplevelShell_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19793 ; free virtual = 33135
+report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19820 ; free virtual = 32628
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -299,7 +299,7 @@ Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2835.395 ; gain = 0.000 ; free physical = 19758 ; free virtual = 33100
+Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2839.625 ; gain = 0.000 ; free physical = 19785 ; free virtual = 32595
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -312,30 +312,30 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
-Checksum: PlaceDB: 5cdd313 ConstDB: 0 ShapeSum: 503ba394 RouteDB: 0
+Checksum: PlaceDB: 9d948354 ConstDB: 0 ShapeSum: 875a12b1 RouteDB: 0
Phase 1 Build RT Design
-Phase 1 Build RT Design | Checksum: 20ce1e99
+Phase 1 Build RT Design | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19653 ; free virtual = 32995
-Post Restoration Checksum: NetGraph: b839e54 NumContArr: 154a8045 Constraints: 0 Timing: 0
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19676 ; free virtual = 32485
+Post Restoration Checksum: NetGraph: 8169e9d4 NumContArr: b2b18a6e Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 20ce1e99
+Phase 2.1 Fix Topology Constraints | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19620 ; free virtual = 32962
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19643 ; free virtual = 32452
Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 20ce1e99
+Phase 2.2 Pre Route Cleanup | Checksum: 1341b7442
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19620 ; free virtual = 32962
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19643 ; free virtual = 32452
Number of Nodes with overlaps = 0
-Phase 2 Router Initialization | Checksum: f83c145e
+Phase 2 Router Initialization | Checksum: 16420495
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19612 ; free virtual = 32954
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Router Utilization Summary
Global Vertical Routing Utilization = 0 %
@@ -343,50 +343,50 @@ Router Utilization Summary
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
- Number of Failed Nets = 82
+ Number of Failed Nets = 698
(Failed Nets is the sum of unrouted and partially routed nets)
- Number of Unrouted Nets = 82
+ Number of Unrouted Nets = 698
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 3 Initial Routing
-Phase 3 Initial Routing | Checksum: cb847c6f
+Phase 3 Initial Routing | Checksum: 561368d2
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19615 ; free virtual = 32957
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 97
Number of Nodes with overlaps = 0
-Phase 4.1 Global Iteration 0 | Checksum: ce53bb98
+Phase 4.1 Global Iteration 0 | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
-Phase 4 Rip-up And Reroute | Checksum: ce53bb98
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
+Phase 4 Rip-up And Reroute | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 5 Delay and Skew Optimization
-Phase 5 Delay and Skew Optimization | Checksum: ce53bb98
+Phase 5 Delay and Skew Optimization | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
-Phase 6.1 Hold Fix Iter | Checksum: ce53bb98
+Phase 6.1 Hold Fix Iter | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
-Phase 6 Post Hold Fix | Checksum: ce53bb98
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
+Phase 6 Post Hold Fix | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 7 Route finalize
Router Utilization Summary
- Global Vertical Routing Utilization = 0.0401818 %
- Global Horizontal Routing Utilization = 0.0300625 %
+ Global Vertical Routing Utilization = 0.191422 %
+ Global Horizontal Routing Utilization = 0.228136 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -398,9 +398,9 @@ Router Utilization Summary
Congestion Report
North Dir 1x1 Area, Max Cong = 19.8198%, No Congested Regions.
-South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
-East Dir 1x1 Area, Max Cong = 11.7647%, No Congested Regions.
-West Dir 1x1 Area, Max Cong = 13.2353%, No Congested Regions.
+South Dir 1x1 Area, Max Cong = 24.3243%, No Congested Regions.
+East Dir 1x1 Area, Max Cong = 25%, No Congested Regions.
+West Dir 1x1 Area, Max Cong = 36.7647%, No Congested Regions.
------------------------------
Reporting congestion hotspots
@@ -422,36 +422,36 @@ Direction: West
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Phase 7 Route finalize | Checksum: ce53bb98
+Phase 7 Route finalize | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19638 ; free virtual = 32447
Phase 8 Verifying routed nets
Verification completed successfully
-Phase 8 Verifying routed nets | Checksum: ce53bb98
+Phase 8 Verifying routed nets | Checksum: 11b9b3579
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19613 ; free virtual = 32955
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
Phase 9 Depositing Routes
-Phase 9 Depositing Routes | Checksum: 156701353
+Phase 9 Depositing Routes | Checksum: 11350863b
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19614 ; free virtual = 32956
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19636 ; free virtual = 32445
INFO: [Route 35-16] Router Completed Successfully
-Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2924.484 ; gain = 16.008 ; free physical = 19647 ; free virtual = 32989
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2931.570 ; gain = 16.008 ; free physical = 19669 ; free virtual = 32478
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
60 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
-route_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:18 . Memory (MB): peak = 2924.484 ; gain = 89.090 ; free physical = 19645 ; free virtual = 32987
+route_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2931.570 ; gain = 91.945 ; free physical = 19665 ; free virtual = 32474
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
-Write XDEF Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2924.492 ; gain = 0.000 ; free physical = 19639 ; free virtual = 32982
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2931.570 ; gain = 0.000 ; free physical = 19661 ; free virtual = 32472
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file LogisimToplevelShell_drc_routed.rpt -pb LogisimToplevelShell_drc_routed.pb -rpx LogisimToplevelShell_drc_routed.rpx
Command: report_drc -file LogisimToplevelShell_drc_routed.rpt -pb LogisimToplevelShell_drc_routed.pb -rpx LogisimToplevelShell_drc_routed.rpx
@@ -515,5 +515,5 @@ INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
90 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:06 ; elapsed = 00:00:22 . Memory (MB): peak = 3258.129 ; gain = 193.297 ; free physical = 19614 ; free virtual = 32958
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:24:39 2022...
+write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:29 . Memory (MB): peak = 3264.066 ; gain = 171.223 ; free physical = 19628 ; free virtual = 32440
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:24:43 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.jou b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.jou
index 798ef161e075677f94e62273a6b041123e44be82..dc376009651788da4b1776852a8132911c2b0802 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.jou
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.jou
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:23:13 2022
-# Process ID: 107830
+# Start of session at: Sun Jun 19 15:23:21 2022
+# Process ID: 145875
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1
# Command line: vivado -log LogisimToplevelShell.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source LogisimToplevelShell.tcl -notrace
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/LogisimToplevelShell.vdi
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.pb
index 41daf17bc96f5e4d2d369d936f1e32ade78aaba1..e1a6a1ad8a9ffd6a670216897f92a4020d11a25b 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/vivado.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/write_bitstream.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/write_bitstream.pb
index 696a1bf6f3dc0eddc5bcdb4190884a5c6756f87f..8e2da6a4659cac8d9d281b3d6c725c167e6fdffb 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/write_bitstream.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/impl_1/write_bitstream.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.Xil/LogisimToplevelShell_propImpl.xdc b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.Xil/LogisimToplevelShell_propImpl.xdc
index a514effb07a0fb65108a72588a2ad707bfba0da4..1ce2ff793c1d7608a9aadedc679d8b480fe1f16b 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.Xil/LogisimToplevelShell_propImpl.xdc
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.Xil/LogisimToplevelShell_propImpl.xdc
@@ -6,28 +6,48 @@ set_property PACKAGE_PIN G3 [get_ports {FPGA_INPUT_PIN_0}]
set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN U18 [get_ports {FPGA_INPUT_PIN_1}]
set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN B16 [get_ports {FPGA_OUTPUT_PIN_2}]
+set_property PACKAGE_PIN B16 [get_ports {FPGA_OUTPUT_PIN_13}]
set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U14 [get_ports {FPGA_OUTPUT_PIN_9}]
+set_property PACKAGE_PIN U14 [get_ports {FPGA_OUTPUT_PIN_20}]
set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN A16 [get_ports {FPGA_OUTPUT_PIN_12}]
+set_property PACKAGE_PIN A16 [get_ports {FPGA_OUTPUT_PIN_22}]
set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U16 [get_ports {FPGA_OUTPUT_PIN_0}]
+set_property PACKAGE_PIN A18 [get_ports {FPGA_OUTPUT_PIN_8}]
set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN A18 [get_ports {FPGA_OUTPUT_PIN_10}]
+set_property PACKAGE_PIN U16 [get_ports {FPGA_OUTPUT_PIN_11}]
set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V19 [get_ports {FPGA_OUTPUT_PIN_7}]
+set_property PACKAGE_PIN U3 [get_ports {FPGA_OUTPUT_PIN_9}]
set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W18 [get_ports {FPGA_OUTPUT_PIN_3}]
+set_property PACKAGE_PIN V19 [get_ports {FPGA_OUTPUT_PIN_18}]
set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN E19 [get_ports {FPGA_OUTPUT_PIN_1}]
+set_property PACKAGE_PIN N3 [get_ports {FPGA_OUTPUT_PIN_0}]
set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN V14 [get_ports {FPGA_OUTPUT_PIN_11}]
+set_property PACKAGE_PIN V13 [get_ports {FPGA_OUTPUT_PIN_7}]
set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U19 [get_ports {FPGA_OUTPUT_PIN_5}]
+set_property PACKAGE_PIN L1 [get_ports {FPGA_OUTPUT_PIN_14}]
set_property src_info {type:XDC file:1 line:40 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN B15 [get_ports {FPGA_OUTPUT_PIN_6}]
+set_property PACKAGE_PIN W18 [get_ports {FPGA_OUTPUT_PIN_15}]
set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN U15 [get_ports {FPGA_OUTPUT_PIN_4}]
+set_property PACKAGE_PIN W3 [get_ports {FPGA_OUTPUT_PIN_10}]
set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN A14 [get_ports {FPGA_OUTPUT_PIN_8}]
+set_property PACKAGE_PIN E19 [get_ports {FPGA_OUTPUT_PIN_12}]
+set_property src_info {type:XDC file:1 line:49 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P3 [get_ports {FPGA_OUTPUT_PIN_1}]
+set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V3 [get_ports {FPGA_OUTPUT_PIN_5}]
+set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U7 [get_ports {FPGA_OUTPUT_PIN_2}]
+set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P1 [get_ports {FPGA_OUTPUT_PIN_19}]
+set_property src_info {type:XDC file:1 line:61 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V14 [get_ports {FPGA_OUTPUT_PIN_21}]
+set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN B15 [get_ports {FPGA_OUTPUT_PIN_4}]
+set_property src_info {type:XDC file:1 line:67 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U19 [get_ports {FPGA_OUTPUT_PIN_17}]
+set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U15 [get_ports {FPGA_OUTPUT_PIN_16}]
+set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V8 [get_ports {FPGA_OUTPUT_PIN_3}]
+set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN A14 [get_ports {FPGA_OUTPUT_PIN_6}]
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.vivado.begin.rst b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.vivado.begin.rst
index f3bb57b44660d7ed7a656f807024c7b53b282dc6..65d793a70974c2534209c3ba45f8c29da479aaf4 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.vivado.begin.rst
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
- <Process Command="vivado" Owner="jonas.stirnema" Host="" Pid="107435" HostCore="8" HostMemory="32659472">
+ <Process Command="vivado" Owner="jonas.stirnema" Host="" Pid="145425" HostCore="8" HostMemory="32659472">
</Process>
</ProcessHandle>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.dcp b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.dcp
index 1718b0ec2061335625188fd0dba74d61c321115f..73bea64bd8af29f2ec1d0fd099353b7d2b0b7467 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.dcp and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.dcp differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.tcl b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.tcl
index ee3712d8120eaba47adcceec69a32c039a15f664..8604f861c2722e38c5c20de6a28e53c11b6d40d2 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.tcl
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.tcl
@@ -143,6 +143,8 @@ read_vhdl -library xil_defaultlib {
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd
+ /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd
+ /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_entity.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd
@@ -151,8 +153,8 @@ read_vhdl -library xil_defaultlib {
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd
- /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd
- /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd
+ /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd
+ /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd
/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_entity.vhd
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.vds b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.vds
index 40dce49d806d955261ccc5fbf71725b1ca249db2..fb452ca203dbc30fb67e48884b6a7eb6aa8a2c99 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.vds
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.vds
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:22:20 2022
-# Process ID: 107475
+# Start of session at: Sun Jun 19 15:22:17 2022
+# Process ID: 145476
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1
# Command line: vivado -log LogisimToplevelShell.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source LogisimToplevelShell.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.vds
@@ -17,80 +17,72 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 107574
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20081 ; free virtual = 33425
----------------------------------------------------------------------------------
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:286]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:287]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:294]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:295]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:296]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:297]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:298]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:299]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:300]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:301]
+INFO: [Synth 8-7075] Helper process launched with PID 145612
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20147 ; free virtual = 32953
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:263]
+WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:271]
INFO: [Synth 8-638] synthesizing module 'LogisimToplevelShell' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'TOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd:15' bound to instance 'TOP_0' of component 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:82]
+INFO: [Synth 8-3491] module 'TOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd:15' bound to instance 'TOP_0' of component 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:112]
INFO: [Synth 8-638] synthesizing module 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:112]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:123]
INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP' (1#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'CPU_RAM24' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd:15' bound to instance 'CPU_RAM' of component 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:126]
+INFO: [Synth 8-3491] module 'CPU_RAM24' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd:15' bound to instance 'CPU_RAM' of component 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:137]
INFO: [Synth 8-638] synthesizing module 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:146]
+INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:147]
INFO: [Synth 8-638] synthesizing module 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'NOT_GATE' (2#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:150]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:151]
INFO: [Synth 8-638] synthesizing module 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'AND_GATE' (3#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:156]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:157]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:162]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:163]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_8' (4#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:176]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:177]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2' (5#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:184]
+INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:185]
INFO: [Synth 8-638] synthesizing module 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'Demultiplexer_8' (6#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:197]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:198]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:207]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:208]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:217]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:218]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:227]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:228]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:237]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:238]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:247]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:248]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:257]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:258]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:267]
-INFO: [Synth 8-3491] module 'CPU_RAM16' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd:15' bound to instance 'RAM16_PROCESSOR' of component 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:281]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:268]
+INFO: [Synth 8-3491] module 'CPU_RAM16' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd:15' bound to instance 'RAM16_PROCESSOR' of component 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:282]
INFO: [Synth 8-638] synthesizing module 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:10]
INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:80]
Parameter BubblesMask bound to: 0 - type: integer
@@ -132,188 +124,138 @@ INFO: [Synth 8-256] done synthesizing module 'CPU_RAM8' (7#1) [/home/jonas.stirn
INFO: [Synth 8-3491] module 'CPU_RAM8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM8_entity.vhd:15' bound to instance 'RAM8_2' of component 'CPU_RAM8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:116]
INFO: [Synth 8-256] done synthesizing module 'CPU_RAM16' (8#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'CPU_RAM24' (9#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_SIGNED_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd:15' bound to instance 'peri1' of component 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:137]
-INFO: [Synth 8-638] synthesizing module 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:124]
-INFO: [Synth 8-638] synthesizing module 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'NOT_GATE_BUS' (10#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:129]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:137]
-INFO: [Synth 8-638] synthesizing module 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Adder' (11#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_entity.vhd:15' bound to instance 'PERI' of component 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:150]
-INFO: [Synth 8-638] synthesizing module 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
- Parameter TwosComplement bound to: 0 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:88]
-INFO: [Synth 8-638] synthesizing module 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter TwosComplement bound to: 0 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter ExtendedBits bound to: 11 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:97]
-INFO: [Synth 8-638] synthesizing module 'Adder__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ExtendedBits bound to: 11 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Adder__parameterized1' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:106]
-INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
- Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'PERI_PWM' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'PERI_SIGNED_PWM' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_SIGNED_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd:15' bound to instance 'peri2' of component 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:143]
INFO: [Synth 8-3491] module 'CPU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_entity.vhd:15' bound to instance 'CPU_1' of component 'CPU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:149]
INFO: [Synth 8-638] synthesizing module 'CPU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:226]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:234]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:232]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:240]
INFO: [Synth 8-638] synthesizing module 'AND_GATE__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE__parameterized2' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE__parameterized2' (9#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:238]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:246]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:244]
+INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:252]
INFO: [Synth 8-638] synthesizing module 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'OR_GATE' (15#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_5' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:250]
- Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_6' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:256]
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE' (10#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd:15' bound to instance 'GATE_7' of component 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:262]
+INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd:15' bound to instance 'GATE_5' of component 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:258]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS' (11#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_8' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:269]
+INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_6' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:265]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:276]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:284]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:292]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:272]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:300]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:280]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_2__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2__parameterized2' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2__parameterized2' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:308]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:288]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_6' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:316]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_7' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:324]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:296]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_8' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:332]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:304]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_9' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:340]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_10' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:348]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:356]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_6' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:312]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:365]
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:320]
+INFO: [Synth 8-638] synthesizing module 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized1' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Comparator' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_2' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:374]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_2' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:329]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_3' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:383]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_3' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:338]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_4' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:392]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_4' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:347]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_5' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:401]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_5' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:356]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_6' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:410]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_6' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:365]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_7' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:419]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_7' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:374]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:428]
-INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:383]
+INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:393]
+INFO: [Synth 8-638] synthesizing module 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Adder' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_7' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:402]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:438]
-INFO: [Synth 8-3491] module 'CPU_INSTRUCTION_MEMORY' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd:15' bound to instance 'CIM_1' of component 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:452]
-INFO: [Synth 8-638] synthesizing module 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_4' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:283]
-INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_4' (18#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:293]
-INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_32' (19#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:331]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:369]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:407]
-INFO: [Synth 8-256] done synthesizing module 'CPU_INSTRUCTION_MEMORY' (20#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'ALU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_entity.vhd:15' bound to instance 'ALU1' of component 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:456]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:410]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_8' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:420]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_9' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:428]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_7' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:436]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_2' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:442]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-3491] module 'OR_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_8' of component 'OR_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:451]
+INFO: [Synth 8-638] synthesizing module 'OR_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd:10]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE_3_INPUTS' (15#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'ALU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_entity.vhd:15' bound to instance 'ALU1' of component 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:462]
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
INFO: [Synth 8-3491] module 'Multiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:145]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_8' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_8' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:158]
Parameter TwosComplement bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:172]
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized3' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized3' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized2' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_ADD_SOUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_entity.vhd:15' bound to instance 'ALU_ADDER' of component 'ALU_ADD_SOUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:185]
INFO: [Synth 8-638] synthesizing module 'ALU_ADD_SOUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:89]
+INFO: [Synth 8-638] synthesizing module 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'NOT_GATE_BUS' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 6 - type: integer
INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:94]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 6 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized1' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized1' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:101]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS__parameterized3' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized3' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized3' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:108]
Parameter NrOfBits bound to: 8 - type: integer
@@ -321,18 +263,18 @@ INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnem
Parameter ExtendedBits bound to: 9 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:122]
-INFO: [Synth 8-256] done synthesizing module 'ALU_ADD_SOUS' (22#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_ADD_SOUS' (18#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_SHIFT' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_entity.vhd:15' bound to instance 'ALU_SH' of component 'ALU_SHIFT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:193]
INFO: [Synth 8-638] synthesizing module 'ALU_SHIFT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
INFO: [Synth 8-3491] module 'Multiplexer_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:114]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_2' (23#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_2' (19#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:121]
-INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT' (24#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT' (20#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_SHIFT_SIGNED' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_entity.vhd:15' bound to instance 'ALU_SH_SIGNED' of component 'ALU_SHIFT_SIGNED' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:199]
INFO: [Synth 8-638] synthesizing module 'ALU_SHIFT_SIGNED' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT_SIGNED' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT_SIGNED' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_AND' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_entity.vhd:15' bound to instance 'ALU_ET' of component 'ALU_AND' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:204]
INFO: [Synth 8-638] synthesizing module 'ALU_AND' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
@@ -341,8 +283,8 @@ INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Doc
INFO: [Synth 8-638] synthesizing module 'AND_GATE_BUS__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS__parameterized1' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_AND' (26#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS__parameterized1' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_AND' (22#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_OR' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_entity.vhd:15' bound to instance 'ALU_OU' of component 'ALU_OR' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:209]
INFO: [Synth 8-638] synthesizing module 'ALU_OR' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
@@ -351,110 +293,164 @@ INFO: [Synth 8-3491] module 'OR_GATE_BUS' declared at '/home/jonas.stirnema/Docu
INFO: [Synth 8-638] synthesizing module 'OR_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'OR_GATE_BUS' (27#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_OR' (28#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE_BUS' (23#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_OR' (24#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_NOT' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_entity.vhd:15' bound to instance 'ALU_NON' of component 'ALU_NOT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:214]
INFO: [Synth 8-638] synthesizing module 'ALU_NOT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:43]
-INFO: [Synth 8-256] done synthesizing module 'ALU_NOT' (29#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU' (30#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'CPU_REG_BANK' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd:15' bound to instance 'CRB' of component 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:466]
-INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+INFO: [Synth 8-256] done synthesizing module 'ALU_NOT' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU' (26#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'CPU_REG_BANK' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd:15' bound to instance 'CRB' of component 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:472]
INFO: [Synth 8-638] synthesizing module 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:107]
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:121]
+INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:135]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:148]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:158]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:168]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:178]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:188]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:198]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:208]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'CPU_REG_BANK' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'CPU' (32#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
-INFO: [Synth 8-638] synthesizing module 'PERI_UART_RCV_16_BITS_9600' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:218]
+INFO: [Synth 8-256] done synthesizing module 'CPU_REG_BANK' (27#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'CPU_INSTRUCTION_MEMORY' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd:15' bound to instance 'CIM_1' of component 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:483]
+INFO: [Synth 8-638] synthesizing module 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_4' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:313]
+INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_4' (28#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:323]
+INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_32' (29#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:361]
+INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+ Parameter NrOfBits bound to: 16 - type: integer
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'CPU_INSTRUCTION_MEMORY' (30#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'CPU' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-638] synthesizing module 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
+ Parameter TwosComplement bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter TwosComplement bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized4' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 11 - type: integer
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Adder__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 11 - type: integer
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Adder__parameterized2' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
-INFO: [Synth 8-638] synthesizing module 'D_FLIPFLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'D_FLIPFLOP' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
- Parameter mode bound to: 0 - type: integer
- Parameter ClkEdge bound to: 1 - type: integer
- Parameter max_val bound to: 17 - type: integer
- Parameter width bound to: 5 - type: integer
-INFO: [Synth 8-638] synthesizing module 'LogisimCounter' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
- Parameter mode bound to: 0 - type: integer
- Parameter ClkEdge bound to: 1 - type: integer
- Parameter max_val bound to: 17 - type: integer
- Parameter width bound to: 5 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'LogisimCounter' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_PWM' (32#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_SIGNED_PWM' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'PERI_UART_RCVE_9600' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:10]
+ Parameter BubblesMask bound to: 0 - type: integer
+ Parameter BubblesMask bound to: 0 - type: integer
+ Parameter BubblesMask bound to: 0 - type: integer
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized5' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter NrOfBits bound to: 4 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized6' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized5' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 4 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized6' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 5 - type: integer
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized7' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 5 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized7' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
- Parameter BubblesMask bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized8' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter ActiveLevel bound to: 1 - type: integer
+INFO: [Synth 8-638] synthesizing module 'D_FLIPFLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
+ Parameter ActiveLevel bound to: 1 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'D_FLIPFLOP' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
Parameter mode bound to: 0 - type: integer
Parameter ClkEdge bound to: 1 - type: integer
Parameter max_val bound to: 10410 - type: integer
Parameter width bound to: 16 - type: integer
-INFO: [Synth 8-638] synthesizing module 'LogisimCounter__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'LogisimCounter' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
Parameter mode bound to: 0 - type: integer
Parameter ClkEdge bound to: 1 - type: integer
Parameter max_val bound to: 10410 - type: integer
Parameter width bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'LogisimCounter__parameterized1' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'LogisimCounter' (35#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfParBits bound to: 17 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfParBits bound to: 9 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
Parameter NrOfBits bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'Shift_Register' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
- Parameter NrOfParBits bound to: 17 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfParBits bound to: 9 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
Parameter NrOfBits bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
INFO: [Synth 8-638] synthesizing module 'SingleBitShiftReg' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'SingleBitShiftReg' (35#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Shift_Register' (36#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
-INFO: [Synth 8-256] done synthesizing module 'PERI_UART_RCV_16_BITS_9600' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'TOP' (38#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'LogisimToplevelShell' (39#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
+ Parameter NrOfStages bound to: 9 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'SingleBitShiftReg' (36#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Shift_Register' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
+ Parameter mode bound to: 0 - type: integer
+ Parameter ClkEdge bound to: 1 - type: integer
+ Parameter max_val bound to: 9 - type: integer
+ Parameter width bound to: 4 - type: integer
+INFO: [Synth 8-638] synthesizing module 'LogisimCounter__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+ Parameter mode bound to: 0 - type: integer
+ Parameter ClkEdge bound to: 1 - type: integer
+ Parameter max_val bound to: 9 - type: integer
+ Parameter width bound to: 4 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'LogisimCounter__parameterized1' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_UART_RCVE_9600' (38#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'TOP' (39#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'LogisimToplevelShell' (40#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2127.602 ; gain = 2.840 ; free physical = 20168 ; free virtual = 33512
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2128.602 ; gain = 3.840 ; free physical = 20204 ; free virtual = 33011
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2142.445 ; gain = 17.684 ; free physical = 20163 ; free virtual = 33507
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2144.445 ; gain = 19.684 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2142.445 ; gain = 17.684 ; free physical = 20163 ; free virtual = 33507
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2144.445 ; gain = 19.684 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2142.445 ; gain = 0.000 ; free physical = 20166 ; free virtual = 33510
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2144.445 ; gain = 0.000 ; free physical = 20193 ; free virtual = 33000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -465,33 +461,31 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
Resolution: To avoid this warning, move constraints listed in [.Xil/LogisimToplevelShell_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20112 ; free virtual = 33455
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20109 ; free virtual = 32917
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20112 ; free virtual = 33455
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20109 ; free virtual = 32917
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20156 ; free virtual = 33500
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/GATE_4' (OR_GATE) to 'TOP_0/CPU_1/GATE_6'
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_3' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_4'
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_3' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_5'
+INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_4' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_5'
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
@@ -499,28 +493,28 @@ Detailed RTL Component Info :
+---Adders :
2 Input 16 Bit Adders := 1
3 Input 11 Bit Adders := 2
- 3 Input 9 Bit Adders := 4
- 2 Input 5 Bit Adders := 1
+ 3 Input 9 Bit Adders := 5
+ 2 Input 4 Bit Adders := 1
+---Registers :
- 17 Bit Registers := 1
16 Bit Registers := 1
10 Bit Registers := 2
+ 9 Bit Registers := 1
8 Bit Registers := 34
- 5 Bit Registers := 1
- 4 Bit Registers := 1
+ 4 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
- 2 Input 17 Bit Muxes := 1
4 Input 16 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 5
+ 2 Input 16 Bit Muxes := 6
2 Input 14 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 32
- 2 Input 5 Bit Muxes := 1
- 3 Input 5 Bit Muxes := 1
+ 2 Input 9 Bit Muxes := 1
+ 2 Input 8 Bit Muxes := 30
+ 2 Input 4 Bit Muxes := 1
+ 3 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 6
2 Input 2 Bit Muxes := 2
- 2 Input 1 Bit Muxes := 3
- 3 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 2
+ 3 Input 1 Bit Muxes := 1
+ 4 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
@@ -537,25 +531,40 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20148 ; free virtual = 33493
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20171 ; free virtual = 32983
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+ROM: Preliminary Mapping Report
++-----------------------+--------------------+---------------+----------------+
+|Module Name | RTL Object | Depth x Width | Implemented As |
++-----------------------+--------------------+---------------+----------------+
+|CPU_INSTRUCTION_MEMORY | MUX_2/MuxOut | 32x16 | LUT |
+|CPU | CIM_1/MUX_2/MuxOut | 32x16 | LUT |
++-----------------------+--------------------+---------------+----------------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20027 ; free virtual = 33373
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20058 ; free virtual = 32870
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20027 ; free virtual = 33373
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20058 ; free virtual = 32870
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33371
+Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20056 ; free virtual = 32868
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -573,37 +582,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -620,38 +629,39 @@ Report Cell Usage:
| |Cell |Count |
+------+-------+------+
|1 |BUFG | 1|
-|2 |CARRY4 | 4|
-|3 |LUT1 | 1|
-|4 |LUT2 | 1|
-|5 |LUT3 | 3|
-|6 |LUT4 | 22|
-|7 |LUT5 | 6|
-|8 |LUT6 | 2|
-|9 |FDCE | 39|
-|10 |FDRE | 9|
-|11 |IBUF | 3|
-|12 |OBUF | 13|
+|2 |CARRY4 | 11|
+|3 |LUT1 | 6|
+|4 |LUT2 | 12|
+|5 |LUT3 | 83|
+|6 |LUT4 | 47|
+|7 |LUT5 | 75|
+|8 |LUT6 | 173|
+|9 |MUXF7 | 11|
+|10 |FDCE | 298|
+|11 |FDRE | 29|
+|12 |IBUF | 3|
+|13 |OBUF | 23|
+------+-------+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 2311.164 ; gain = 17.684 ; free physical = 20069 ; free virtual = 33415
-Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20068 ; free virtual = 33414
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2311.227 ; gain = 19.684 ; free physical = 20110 ; free virtual = 32921
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20110 ; free virtual = 32921
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20152 ; free virtual = 33497
-INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20181 ; free virtual = 32993
+INFO: [Netlist 29-17] Analyzing 22 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20098 ; free virtual = 33444
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20129 ; free virtual = 32940
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
-223 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
+223 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 2311.164 ; gain = 186.727 ; free physical = 20240 ; free virtual = 33585
+synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:45 . Memory (MB): peak = 2311.227 ; gain = 186.789 ; free physical = 20265 ; free virtual = 33077
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file LogisimToplevelShell_utilization_synth.rpt -pb LogisimToplevelShell_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:23:01 2022...
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:23:09 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.pb
index 8383e90f0a6e49cc35c5771a06256411ac2a04b3..ee7ae5882942df67bfdbd59bd73867addbf0b352 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.rpt b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.rpt
index fbe8cf7f53d1094cc182694433d13bed6106daa8..6b4f9229875825b04ca7cfac4d3d539aa662fa36 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.rpt
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell_utilization_synth.rpt
@@ -1,7 +1,7 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-| Date : Fri Jun 17 15:23:01 2022
+| Date : Sun Jun 19 15:23:09 2022
| Host : hepia-ws-8840-lx running 64-bit Ubuntu 20.04.3 LTS
| Command : report_utilization -file LogisimToplevelShell_utilization_synth.rpt -pb LogisimToplevelShell_utilization_synth.pb
| Design : LogisimToplevelShell
@@ -30,13 +30,13 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
-| Slice LUTs* | 22 | 0 | 20800 | 0.11 |
-| LUT as Logic | 22 | 0 | 20800 | 0.11 |
+| Slice LUTs* | 322 | 0 | 20800 | 1.55 |
+| LUT as Logic | 322 | 0 | 20800 | 1.55 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
-| Slice Registers | 48 | 0 | 41600 | 0.12 |
-| Register as Flip Flop | 48 | 0 | 41600 | 0.12 |
+| Slice Registers | 327 | 0 | 41600 | 0.79 |
+| Register as Flip Flop | 327 | 0 | 41600 | 0.79 |
| Register as Latch | 0 | 0 | 41600 | 0.00 |
-| F7 Muxes | 0 | 0 | 16300 | 0.00 |
+| F7 Muxes | 11 | 0 | 16300 | 0.07 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -55,9 +55,9 @@ Table of Contents
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
-| 39 | Yes | - | Reset |
+| 298 | Yes | - | Reset |
| 0 | Yes | Set | - |
-| 9 | Yes | Reset | - |
+| 29 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -90,7 +90,7 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
-| Bonded IOB | 16 | 0 | 106 | 15.09 |
+| Bonded IOB | 26 | 0 | 106 | 24.53 |
| Bonded IPADs | 0 | 0 | 10 | 0.00 |
| Bonded OPADs | 0 | 0 | 4 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
@@ -149,17 +149,18 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
-| FDCE | 39 | Flop & Latch |
-| LUT4 | 22 | LUT |
-| OBUF | 13 | IO |
-| FDRE | 9 | Flop & Latch |
-| LUT5 | 6 | LUT |
-| CARRY4 | 4 | CarryLogic |
-| LUT3 | 3 | LUT |
+| FDCE | 298 | Flop & Latch |
+| LUT6 | 173 | LUT |
+| LUT3 | 83 | LUT |
+| LUT5 | 75 | LUT |
+| LUT4 | 47 | LUT |
+| FDRE | 29 | Flop & Latch |
+| OBUF | 23 | IO |
+| LUT2 | 12 | LUT |
+| MUXF7 | 11 | MuxFx |
+| CARRY4 | 11 | CarryLogic |
+| LUT1 | 6 | LUT |
| IBUF | 3 | IO |
-| LUT6 | 2 | LUT |
-| LUT2 | 1 | LUT |
-| LUT1 | 1 | LUT |
| BUFG | 1 | Clock |
+----------+------+---------------------+
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/gen_run.xml b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/gen_run.xml
index f0fea2fce7f07e577d053d0d35ec0ba3d759c9b2..06540e4a7ff7fb620f39a18ff08b3e87c4a394d1 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/gen_run.xml
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/gen_run.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1655472139">
+<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1655644935">
<File Type="VDS-TIMING-PB" Name="LogisimToplevelShell_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="LogisimToplevelShell_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="LogisimToplevelShell.dcp"/>
@@ -365,6 +365,18 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/../../vhdl/gates/OR_GATE_3_INPUTS_entity.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<File Path="$PPRDIR/../../vhdl/gates/OR_GATE_BUS_entity.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -413,13 +425,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd">
+ <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd">
+ <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/project.wdf b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/project.wdf
index 6dddc1b59579d353619df8622afc6f25faefef5c..7a8ef044392e182e82ef132d723e28b4650f2751 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/project.wdf
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/project.wdf
@@ -1,5 +1,5 @@
version:1
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3736:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3738:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
@@ -27,5 +27,5 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
-5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6432313938613465363064663466343062636263386536393763373562616265:506172656e742050412070726f6a656374204944:00
-eof:3850207768
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6461626139613831663538643430653138346634373563646435386365636433:506172656e742050412070726f6a656374204944:00
+eof:1604076918
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/runme.log b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/runme.log
index 097488d009cd4c77119c4dcca37216c12bc40e78..91523ef9c1c1e77d62716f734bc9b25717342413 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/runme.log
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/runme.log
@@ -16,80 +16,72 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 107574
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20081 ; free virtual = 33425
----------------------------------------------------------------------------------
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:286]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:287]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:294]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:295]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:296]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:297]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:298]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:299]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:300]
-WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:301]
+INFO: [Synth 8-7075] Helper process launched with PID 145612
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2124.762 ; gain = 0.000 ; free physical = 20147 ; free virtual = 32953
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:263]
+WARNING: [Synth 8-2519] partially associated formal q cannot have actual OPEN [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:271]
INFO: [Synth 8-638] synthesizing module 'LogisimToplevelShell' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'TOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd:15' bound to instance 'TOP_0' of component 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:82]
+INFO: [Synth 8-3491] module 'TOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd:15' bound to instance 'TOP_0' of component 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:112]
INFO: [Synth 8-638] synthesizing module 'TOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:112]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:123]
INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP' (1#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'CPU_RAM24' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd:15' bound to instance 'CPU_RAM' of component 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:126]
+INFO: [Synth 8-3491] module 'CPU_RAM24' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd:15' bound to instance 'CPU_RAM' of component 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:137]
INFO: [Synth 8-638] synthesizing module 'CPU_RAM24' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:146]
+INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:147]
INFO: [Synth 8-638] synthesizing module 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'NOT_GATE' (2#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:150]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:151]
INFO: [Synth 8-638] synthesizing module 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
INFO: [Synth 8-256] done synthesizing module 'AND_GATE' (3#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:156]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:157]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:162]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:163]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_8' (4#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:176]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:177]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2' (5#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:184]
+INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:185]
INFO: [Synth 8-638] synthesizing module 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'Demultiplexer_8' (6#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:197]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:198]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:207]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:208]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:217]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:218]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:227]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:228]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:237]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:238]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:247]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:248]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:257]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:258]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:267]
-INFO: [Synth 8-3491] module 'CPU_RAM16' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd:15' bound to instance 'RAM16_PROCESSOR' of component 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:281]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:268]
+INFO: [Synth 8-3491] module 'CPU_RAM16' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd:15' bound to instance 'RAM16_PROCESSOR' of component 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:282]
INFO: [Synth 8-638] synthesizing module 'CPU_RAM16' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:10]
INFO: [Synth 8-3491] module 'NOT_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:80]
Parameter BubblesMask bound to: 0 - type: integer
@@ -131,188 +123,138 @@ INFO: [Synth 8-256] done synthesizing module 'CPU_RAM8' (7#1) [/home/jonas.stirn
INFO: [Synth 8-3491] module 'CPU_RAM8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM8_entity.vhd:15' bound to instance 'RAM8_2' of component 'CPU_RAM8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:116]
INFO: [Synth 8-256] done synthesizing module 'CPU_RAM16' (8#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd:10]
INFO: [Synth 8-256] done synthesizing module 'CPU_RAM24' (9#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_SIGNED_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd:15' bound to instance 'peri1' of component 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:137]
-INFO: [Synth 8-638] synthesizing module 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:124]
-INFO: [Synth 8-638] synthesizing module 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'NOT_GATE_BUS' (10#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:129]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:137]
-INFO: [Synth 8-638] synthesizing module 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Adder' (11#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_entity.vhd:15' bound to instance 'PERI' of component 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:150]
-INFO: [Synth 8-638] synthesizing module 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
- Parameter TwosComplement bound to: 0 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:88]
-INFO: [Synth 8-638] synthesizing module 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter TwosComplement bound to: 0 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter ExtendedBits bound to: 11 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:97]
-INFO: [Synth 8-638] synthesizing module 'Adder__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ExtendedBits bound to: 11 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Adder__parameterized1' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
- Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:106]
-INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
- Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfBits bound to: 10 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'PERI_PWM' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'PERI_SIGNED_PWM' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'PERI_SIGNED_PWM' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd:15' bound to instance 'peri2' of component 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:143]
INFO: [Synth 8-3491] module 'CPU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_entity.vhd:15' bound to instance 'CPU_1' of component 'CPU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:149]
INFO: [Synth 8-638] synthesizing module 'CPU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:226]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_1' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:234]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:232]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:240]
INFO: [Synth 8-638] synthesizing module 'AND_GATE__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE__parameterized2' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE__parameterized2' (9#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:238]
+INFO: [Synth 8-3491] module 'AND_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:246]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:244]
+INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:252]
INFO: [Synth 8-638] synthesizing module 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'OR_GATE' (15#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_5' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:250]
- Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_6' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:256]
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE' (10#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd:15' bound to instance 'GATE_7' of component 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:262]
+INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd:15' bound to instance 'GATE_5' of component 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:258]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS' (11#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_8' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:269]
+INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_6' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:265]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:276]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:284]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:292]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:272]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:300]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:280]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_2__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2__parameterized2' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_2__parameterized2' (12#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:308]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:288]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_6' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:316]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_7' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:324]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:296]
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_8' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:332]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:304]
Parameter NrOfBits bound to: 3 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_9' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:340]
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_10' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:348]
- Parameter ExtendedBits bound to: 9 - type: integer
- Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:356]
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_6' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:312]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:365]
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:320]
+INFO: [Synth 8-638] synthesizing module 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized1' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Comparator' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_2' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:374]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_2' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:329]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_3' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:383]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_3' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:338]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_4' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:392]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_4' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:347]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_5' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:401]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_5' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:356]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_6' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:410]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_6' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:365]
Parameter TwosComplement bound to: 0 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_7' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:419]
+INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_7' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:374]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:428]
-INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:383]
+INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 4 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized2' (13#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:393]
+INFO: [Synth 8-638] synthesizing module 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Adder' (14#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_7' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:402]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:438]
-INFO: [Synth 8-3491] module 'CPU_INSTRUCTION_MEMORY' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd:15' bound to instance 'CIM_1' of component 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:452]
-INFO: [Synth 8-638] synthesizing module 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_4' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:283]
-INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_4' (18#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:293]
-INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_32' (19#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:331]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_4' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:369]
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_5' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:407]
-INFO: [Synth 8-256] done synthesizing module 'CPU_INSTRUCTION_MEMORY' (20#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'ALU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_entity.vhd:15' bound to instance 'ALU1' of component 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:456]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:410]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_8' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:420]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_9' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:428]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_7' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:436]
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_2' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:442]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-3491] module 'OR_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_8' of component 'OR_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:451]
+INFO: [Synth 8-638] synthesizing module 'OR_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd:10]
+ Parameter BubblesMask bound to: 0 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE_3_INPUTS' (15#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'ALU' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_entity.vhd:15' bound to instance 'ALU1' of component 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:462]
INFO: [Synth 8-638] synthesizing module 'ALU' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
INFO: [Synth 8-3491] module 'Multiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:145]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_8' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_8' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:158]
Parameter TwosComplement bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Comparator' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd:15' bound to instance 'Comparator_1' of component 'Comparator' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:172]
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized3' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized3' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized2' (16#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_ADD_SOUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_entity.vhd:15' bound to instance 'ALU_ADDER' of component 'ALU_ADD_SOUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:185]
INFO: [Synth 8-638] synthesizing module 'ALU_ADD_SOUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:89]
+INFO: [Synth 8-638] synthesizing module 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'NOT_GATE_BUS' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 6 - type: integer
INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_2' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:94]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 6 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized1' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized1' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
INFO: [Synth 8-3491] module 'AND_GATE_3_INPUTS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd:15' bound to instance 'GATE_3' of component 'AND_GATE_3_INPUTS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:101]
INFO: [Synth 8-638] synthesizing module 'AND_GATE_3_INPUTS__parameterized3' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized3' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_3_INPUTS__parameterized3' (17#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'OR_GATE' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_entity.vhd:15' bound to instance 'GATE_4' of component 'OR_GATE' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:108]
Parameter NrOfBits bound to: 8 - type: integer
@@ -320,18 +262,18 @@ INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnem
Parameter ExtendedBits bound to: 9 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Adder' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_entity.vhd:15' bound to instance 'ADDER2C_1' of component 'Adder' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:122]
-INFO: [Synth 8-256] done synthesizing module 'ALU_ADD_SOUS' (22#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_ADD_SOUS' (18#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_SHIFT' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_entity.vhd:15' bound to instance 'ALU_SH' of component 'ALU_SHIFT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:193]
INFO: [Synth 8-638] synthesizing module 'ALU_SHIFT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
INFO: [Synth 8-3491] module 'Multiplexer_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:114]
INFO: [Synth 8-638] synthesizing module 'Multiplexer_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Multiplexer_2' (23#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_2' (19#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'Multiplexer_bus_2' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:121]
-INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT' (24#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT' (20#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_SHIFT_SIGNED' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_entity.vhd:15' bound to instance 'ALU_SH_SIGNED' of component 'ALU_SHIFT_SIGNED' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:199]
INFO: [Synth 8-638] synthesizing module 'ALU_SHIFT_SIGNED' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT_SIGNED' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_SHIFT_SIGNED' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_AND' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_entity.vhd:15' bound to instance 'ALU_ET' of component 'ALU_AND' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:204]
INFO: [Synth 8-638] synthesizing module 'ALU_AND' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
@@ -340,8 +282,8 @@ INFO: [Synth 8-3491] module 'AND_GATE_BUS' declared at '/home/jonas.stirnema/Doc
INFO: [Synth 8-638] synthesizing module 'AND_GATE_BUS__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS__parameterized1' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_AND' (26#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'AND_GATE_BUS__parameterized1' (21#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_AND' (22#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_AND_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_OR' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_entity.vhd:15' bound to instance 'ALU_OU' of component 'ALU_OR' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:209]
INFO: [Synth 8-638] synthesizing module 'ALU_OR' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
@@ -350,110 +292,164 @@ INFO: [Synth 8-3491] module 'OR_GATE_BUS' declared at '/home/jonas.stirnema/Docu
INFO: [Synth 8-638] synthesizing module 'OR_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
Parameter BubblesMask bound to: 0 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'OR_GATE_BUS' (27#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU_OR' (28#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'OR_GATE_BUS' (23#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU_OR' (24#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_OR_behavior.vhd:10]
INFO: [Synth 8-3491] module 'ALU_NOT' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_entity.vhd:15' bound to instance 'ALU_NON' of component 'ALU_NOT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:214]
INFO: [Synth 8-638] synthesizing module 'ALU_NOT' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
INFO: [Synth 8-3491] module 'NOT_GATE_BUS' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd:15' bound to instance 'GATE_1' of component 'NOT_GATE_BUS' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:43]
-INFO: [Synth 8-256] done synthesizing module 'ALU_NOT' (29#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'ALU' (30#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
-INFO: [Synth 8-3491] module 'CPU_REG_BANK' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd:15' bound to instance 'CRB' of component 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:466]
-INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+INFO: [Synth 8-256] done synthesizing module 'ALU_NOT' (25#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'ALU' (26#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/ALU_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'CPU_REG_BANK' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd:15' bound to instance 'CRB' of component 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:472]
INFO: [Synth 8-638] synthesizing module 'CPU_REG_BANK' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:107]
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:121]
+INFO: [Synth 8-3491] module 'Demultiplexer_8' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd:15' bound to instance 'DEMUX_1' of component 'Demultiplexer_8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:135]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_1' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:148]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_2' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:158]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_3' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:168]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_4' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:178]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_5' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:188]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_6' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:198]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_7' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:208]
Parameter ActiveLevel bound to: 1 - type: integer
Parameter NrOfBits bound to: 8 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'CPU_REG_BANK' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'CPU' (32#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
-INFO: [Synth 8-638] synthesizing module 'PERI_UART_RCV_16_BITS_9600' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'REGISTER_FLIP_FLOP' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_entity.vhd:15' bound to instance 'REGISTER_FILE_8' of component 'REGISTER_FLIP_FLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:218]
+INFO: [Synth 8-256] done synthesizing module 'CPU_REG_BANK' (27#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd:10]
+INFO: [Synth 8-3491] module 'CPU_INSTRUCTION_MEMORY' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd:15' bound to instance 'CIM_1' of component 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:483]
+INFO: [Synth 8-638] synthesizing module 'CPU_INSTRUCTION_MEMORY' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_4' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd:15' bound to instance 'MUX_1' of component 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:313]
+INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_4' (28#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_2' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:323]
+INFO: [Synth 8-638] synthesizing module 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Multiplexer_bus_32' (29#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-3491] module 'Multiplexer_bus_32' declared at '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd:15' bound to instance 'MUX_3' of component 'Multiplexer_bus_32' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:361]
+INFO: [Common 17-14] Message 'Synth 8-3491' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+ Parameter NrOfBits bound to: 16 - type: integer
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'CPU_INSTRUCTION_MEMORY' (30#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'CPU' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'PERI_SIGNED_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
+ Parameter NrOfBits bound to: 8 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+ Parameter ExtendedBits bound to: 9 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-638] synthesizing module 'PERI_PWM' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
+ Parameter TwosComplement bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter TwosComplement bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 8 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized4' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 11 - type: integer
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Adder__parameterized2' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
+ Parameter ExtendedBits bound to: 11 - type: integer
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Adder__parameterized2' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
-INFO: [Synth 8-638] synthesizing module 'D_FLIPFLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-638] synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'D_FLIPFLOP' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
- Parameter mode bound to: 0 - type: integer
- Parameter ClkEdge bound to: 1 - type: integer
- Parameter max_val bound to: 17 - type: integer
- Parameter width bound to: 5 - type: integer
-INFO: [Synth 8-638] synthesizing module 'LogisimCounter' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
- Parameter mode bound to: 0 - type: integer
- Parameter ClkEdge bound to: 1 - type: integer
- Parameter max_val bound to: 17 - type: integer
- Parameter width bound to: 5 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'LogisimCounter' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+ Parameter NrOfBits bound to: 10 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'REGISTER_FLIP_FLOP__parameterized4' (31#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_PWM' (32#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_SIGNED_PWM' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'PERI_UART_RCVE_9600' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:10]
+ Parameter BubblesMask bound to: 0 - type: integer
+ Parameter BubblesMask bound to: 0 - type: integer
+ Parameter BubblesMask bound to: 0 - type: integer
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized5' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter NrOfBits bound to: 4 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized6' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized5' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 4 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized6' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 5 - type: integer
-INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized7' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-638] synthesizing module 'Comparator__parameterized8' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
Parameter TwosComplement bound to: 1 - type: integer
- Parameter NrOfBits bound to: 5 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized7' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
- Parameter BubblesMask bound to: 0 - type: integer
- Parameter BubblesMask bound to: 0 - type: integer
+ Parameter NrOfBits bound to: 16 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'Comparator__parameterized8' (33#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd:10]
+ Parameter ActiveLevel bound to: 1 - type: integer
+INFO: [Synth 8-638] synthesizing module 'D_FLIPFLOP' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
+ Parameter ActiveLevel bound to: 1 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'D_FLIPFLOP' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd:10]
Parameter mode bound to: 0 - type: integer
Parameter ClkEdge bound to: 1 - type: integer
Parameter max_val bound to: 10410 - type: integer
Parameter width bound to: 16 - type: integer
-INFO: [Synth 8-638] synthesizing module 'LogisimCounter__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-638] synthesizing module 'LogisimCounter' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
Parameter mode bound to: 0 - type: integer
Parameter ClkEdge bound to: 1 - type: integer
Parameter max_val bound to: 10410 - type: integer
Parameter width bound to: 16 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'LogisimCounter__parameterized1' (34#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'LogisimCounter' (35#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfParBits bound to: 17 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfParBits bound to: 9 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
Parameter NrOfBits bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
INFO: [Synth 8-638] synthesizing module 'Shift_Register' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
- Parameter NrOfParBits bound to: 17 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfParBits bound to: 9 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
Parameter NrOfBits bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
+ Parameter NrOfStages bound to: 9 - type: integer
INFO: [Synth 8-638] synthesizing module 'SingleBitShiftReg' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
Parameter ActiveLevel bound to: 1 - type: integer
- Parameter NrOfStages bound to: 17 - type: integer
-INFO: [Synth 8-256] done synthesizing module 'SingleBitShiftReg' (35#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'Shift_Register' (36#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
-INFO: [Synth 8-256] done synthesizing module 'PERI_UART_RCV_16_BITS_9600' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'TOP' (38#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
-INFO: [Synth 8-256] done synthesizing module 'LogisimToplevelShell' (39#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
+ Parameter NrOfStages bound to: 9 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'SingleBitShiftReg' (36#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'Shift_Register' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd:45]
+ Parameter mode bound to: 0 - type: integer
+ Parameter ClkEdge bound to: 1 - type: integer
+ Parameter max_val bound to: 9 - type: integer
+ Parameter width bound to: 4 - type: integer
+INFO: [Synth 8-638] synthesizing module 'LogisimCounter__parameterized1' [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+ Parameter mode bound to: 0 - type: integer
+ Parameter ClkEdge bound to: 1 - type: integer
+ Parameter max_val bound to: 9 - type: integer
+ Parameter width bound to: 4 - type: integer
+INFO: [Synth 8-256] done synthesizing module 'LogisimCounter__parameterized1' (37#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/memory/LogisimCounter_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'PERI_UART_RCVE_9600' (38#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'TOP' (39#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd:10]
+INFO: [Synth 8-256] done synthesizing module 'LogisimToplevelShell' (40#1) [/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd:10]
---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2127.602 ; gain = 2.840 ; free physical = 20168 ; free virtual = 33512
+Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2128.602 ; gain = 3.840 ; free physical = 20204 ; free virtual = 33011
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2142.445 ; gain = 17.684 ; free physical = 20163 ; free virtual = 33507
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2144.445 ; gain = 19.684 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2142.445 ; gain = 17.684 ; free physical = 20163 ; free virtual = 33507
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2144.445 ; gain = 19.684 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2142.445 ; gain = 0.000 ; free physical = 20166 ; free virtual = 33510
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2144.445 ; gain = 0.000 ; free physical = 20193 ; free virtual = 33000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -464,33 +460,31 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
Resolution: To avoid this warning, move constraints listed in [.Xil/LogisimToplevelShell_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20112 ; free virtual = 33455
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20109 ; free virtual = 32917
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20112 ; free virtual = 33455
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20109 ; free virtual = 32917
---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1
---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20174 ; free virtual = 33517
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20209 ; free virtual = 33017
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20156 ; free virtual = 33500
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20199 ; free virtual = 33007
---------------------------------------------------------------------------------
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/GATE_4' (OR_GATE) to 'TOP_0/CPU_1/GATE_6'
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_3' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_4'
-INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_3' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_5'
+INFO: [Synth 8-223] decloning instance 'TOP_0/CPU_1/CIM_1/MUX_4' (Multiplexer_bus_32) to 'TOP_0/CPU_1/CIM_1/MUX_5'
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
@@ -498,28 +492,28 @@ Detailed RTL Component Info :
+---Adders :
2 Input 16 Bit Adders := 1
3 Input 11 Bit Adders := 2
- 3 Input 9 Bit Adders := 4
- 2 Input 5 Bit Adders := 1
+ 3 Input 9 Bit Adders := 5
+ 2 Input 4 Bit Adders := 1
+---Registers :
- 17 Bit Registers := 1
16 Bit Registers := 1
10 Bit Registers := 2
+ 9 Bit Registers := 1
8 Bit Registers := 34
- 5 Bit Registers := 1
- 4 Bit Registers := 1
+ 4 Bit Registers := 2
1 Bit Registers := 2
+---Muxes :
- 2 Input 17 Bit Muxes := 1
4 Input 16 Bit Muxes := 1
- 2 Input 16 Bit Muxes := 5
+ 2 Input 16 Bit Muxes := 6
2 Input 14 Bit Muxes := 1
- 2 Input 8 Bit Muxes := 32
- 2 Input 5 Bit Muxes := 1
- 3 Input 5 Bit Muxes := 1
+ 2 Input 9 Bit Muxes := 1
+ 2 Input 8 Bit Muxes := 30
+ 2 Input 4 Bit Muxes := 1
+ 3 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 6
2 Input 2 Bit Muxes := 2
- 2 Input 1 Bit Muxes := 3
- 3 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 2
+ 3 Input 1 Bit Muxes := 1
+ 4 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
@@ -536,25 +530,40 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20148 ; free virtual = 33493
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20171 ; free virtual = 32983
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+ROM: Preliminary Mapping Report
++-----------------------+--------------------+---------------+----------------+
+|Module Name | RTL Object | Depth x Width | Implemented As |
++-----------------------+--------------------+---------------+----------------+
+|CPU_INSTRUCTION_MEMORY | MUX_2/MuxOut | 32x16 | LUT |
+|CPU | CIM_1/MUX_2/MuxOut | 32x16 | LUT |
++-----------------------+--------------------+---------------+----------------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20027 ; free virtual = 33373
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20058 ; free virtual = 32870
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20027 ; free virtual = 33373
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20058 ; free virtual = 32870
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33371
+Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20056 ; free virtual = 32868
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -572,37 +581,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -619,38 +628,39 @@ Report Cell Usage:
| |Cell |Count |
+------+-------+------+
|1 |BUFG | 1|
-|2 |CARRY4 | 4|
-|3 |LUT1 | 1|
-|4 |LUT2 | 1|
-|5 |LUT3 | 3|
-|6 |LUT4 | 22|
-|7 |LUT5 | 6|
-|8 |LUT6 | 2|
-|9 |FDCE | 39|
-|10 |FDRE | 9|
-|11 |IBUF | 3|
-|12 |OBUF | 13|
+|2 |CARRY4 | 11|
+|3 |LUT1 | 6|
+|4 |LUT2 | 12|
+|5 |LUT3 | 83|
+|6 |LUT4 | 47|
+|7 |LUT5 | 75|
+|8 |LUT6 | 173|
+|9 |MUXF7 | 11|
+|10 |FDCE | 298|
+|11 |FDRE | 29|
+|12 |IBUF | 3|
+|13 |OBUF | 23|
+------+-------+------+
---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20026 ; free virtual = 33372
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20055 ; free virtual = 32867
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 2311.164 ; gain = 17.684 ; free physical = 20069 ; free virtual = 33415
-Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.164 ; gain = 186.402 ; free physical = 20068 ; free virtual = 33414
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 2311.227 ; gain = 19.684 ; free physical = 20110 ; free virtual = 32921
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2311.227 ; gain = 186.465 ; free physical = 20110 ; free virtual = 32921
INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20152 ; free virtual = 33497
-INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20181 ; free virtual = 32993
+INFO: [Netlist 29-17] Analyzing 22 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.164 ; gain = 0.000 ; free physical = 20098 ; free virtual = 33444
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.227 ; gain = 0.000 ; free physical = 20129 ; free virtual = 32940
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
-223 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
+223 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 2311.164 ; gain = 186.727 ; free physical = 20240 ; free virtual = 33585
+synth_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:45 . Memory (MB): peak = 2311.227 ; gain = 186.789 ; free physical = 20265 ; free virtual = 33077
INFO: [Common 17-1381] The checkpoint '/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file LogisimToplevelShell_utilization_synth.rpt -pb LogisimToplevelShell_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri Jun 17 15:23:01 2022...
+INFO: [Common 17-206] Exiting Vivado at Sun Jun 19 15:23:09 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.jou b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.jou
index 439252f2f8a5640d96824caa89f35a328215c955..2d3abe6295e2cc1e3e69bd1a8349d099f8e672ca 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.jou
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.jou
@@ -2,8 +2,8 @@
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:22:20 2022
-# Process ID: 107475
+# Start of session at: Sun Jun 19 15:22:17 2022
+# Process ID: 145476
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1
# Command line: vivado -log LogisimToplevelShell.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source LogisimToplevelShell.tcl
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/LogisimToplevelShell.vds
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.pb b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.pb
index 15abf63b74ea25f7a8984ac69770c4b9857b5d93..c11690d27b7ad7471958a0029fed38595e0417d6 100644
Binary files a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.pb and b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.runs/synth_1/vivado.pb differ
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.xpr b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.xpr
index 59aa4d5c38b3415769286f9a85a1a988866a574d..9ecf0aedc9ba43933bd140396a12b72f667c9b7a 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.xpr
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.xpr
@@ -6,7 +6,7 @@
<Project Version="7" Minor="49" Path="/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/vp/vp.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
- <Option Name="Id" Val="d2198a4e60df4f40bcbc8e697c75babe"/>
+ <Option Name="Id" Val="daba9a81f58d40e184f475cdd58cecd3"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -421,6 +421,18 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
+ <File Path="$PPRDIR/../../vhdl/gates/OR_GATE_3_INPUTS_entity.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/../../vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
<File Path="$PPRDIR/../../vhdl/gates/OR_GATE_BUS_entity.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -469,13 +481,13 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd">
+ <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd">
+ <File Path="$PPRDIR/../../vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.jou b/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.jou
index 1bf201af89b92c451e2522f04543a18ecfaf9a66..b28a02b5b5347fc88d567f11b227e25d27f3c12a 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.jou
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.jou
@@ -2,11 +2,11 @@
# Webtalk v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:25:14 2022
-# Process ID: 109964
+# Start of session at: Sun Jun 19 15:25:07 2022
+# Process ID: 150243
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
-# Command line: wbtcv -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-109728-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
+# Command line: wbtcv -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-150011-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.log
# Journal file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.jou
#-----------------------------------------------------------
-source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-109728-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
+source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-150011-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
diff --git a/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.log b/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.log
index b17f996aa0ce8a8dfc2446f7541c9f754e644fcc..fe2c806afdf356b8877703ec1f640d7ef5869eb6 100644
--- a/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.log
+++ b/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.log
@@ -2,12 +2,12 @@
# Webtalk v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
-# Start of session at: Fri Jun 17 15:25:14 2022
-# Process ID: 109964
+# Start of session at: Sun Jun 19 15:25:07 2022
+# Process ID: 150243
# Current directory: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox
-# Command line: wbtcv -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-109728-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
+# Command line: wbtcv -mode batch -source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-150011-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
# Log file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.log
# Journal file: /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/webtalk.jou
#-----------------------------------------------------------
-source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-109728-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
-INFO: [Common 17-206] Exiting Webtalk at Fri Jun 17 15:25:14 2022...
+source /home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/sandbox/.Xil/Vivado-150011-hepia-ws-8840-lx/webtalk/labtool_webtalk.tcl -notrace
+INFO: [Common 17-206] Exiting Webtalk at Sun Jun 19 15:25:07 2022...
diff --git a/LABO/FULL_ADDER/CPU/TOP/scripts/vivadoCreateProject.tcl b/LABO/FULL_ADDER/CPU/TOP/scripts/vivadoCreateProject.tcl
index 77d8b5e04c555419f6314e3f7a1b085ce814a694..29fea89f5aec3974b364e5c436733ead2e5f2379 100644
--- a/LABO/FULL_ADDER/CPU/TOP/scripts/vivadoCreateProject.tcl
+++ b/LABO/FULL_ADDER/CPU/TOP/scripts/vivadoCreateProject.tcl
@@ -7,24 +7,22 @@ add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/Shift_Register_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_BUS_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_BUS_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_8_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_2_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Demultiplexer_8_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_8_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_2_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM8_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM16_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_entity.vhd"
@@ -33,11 +31,14 @@ add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_NOT_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_REG_BANK_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/TOP_entity.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Comparator_entity.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/toplevel/LogisimToplevelShell_entity.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/REGISTER_FLIP_FLOP_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/D_FLIPFLOP_behavior.vhd"
@@ -45,24 +46,22 @@ add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/memory/Shift_Register_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_BUS_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/AND_GATE_3_INPUTS_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/NOT_GATE_BUS_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/gates/OR_GATE_BUS_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_8_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_2_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Demultiplexer_8_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_8_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_2_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_4_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/plexers/Multiplexer_bus_32_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM8_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM16_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_ADD_SOUS_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_SHIFT_SIGNED_behavior.vhd"
@@ -71,11 +70,14 @@ add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_NOT_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/ALU_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_REG_BANK_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/CPU_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_PWM_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_SIGNED_PWM_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/circuit/TOP_behavior.vhd"
-add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Comparator_behavior.vhd"
+add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/arithmetic/Adder_behavior.vhd"
add_files "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER//CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd"
add_files -fileset constrs_1 "/home/jonas.stirnema/Documents/sys_log/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc"
exit
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd
index dd749ab969cf3aecc7ebb9675fb85338e30fffd9..00f8e09a795bc5132197a6560426f8d33da21b39 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_INSTRUCTION_MEMORY_behavior.vhd
@@ -216,65 +216,95 @@ BEGIN
-----------------------------------------------------------------------------
-- Here all in-lined components are defined --
-----------------------------------------------------------------------------
- s_LOGISIM_BUS_1(15 DOWNTO 0) <= std_logic_vector(to_unsigned(32784,16));
+ s_LOGISIM_BUS_123(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60964,16));
- s_LOGISIM_BUS_70(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33911,16));
+ s_LOGISIM_BUS_6(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
+
+ s_LOGISIM_BUS_122(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33889,16));
+
+ s_LOGISIM_BUS_59(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
s_LOGISIM_BUS_2(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
- s_LOGISIM_BUS_71(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
+ s_LOGISIM_BUS_3(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
- s_LOGISIM_BUS_3(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60952,16));
+ s_LOGISIM_BUS_79(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
- s_LOGISIM_BUS_68(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
+ s_LOGISIM_BUS_77(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35378,16));
- s_LOGISIM_BUS_0(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60949,16));
+ s_LOGISIM_BUS_0(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33907,16));
- s_LOGISIM_BUS_76(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
+ s_LOGISIM_BUS_57(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35328,16));
- s_LOGISIM_BUS_4(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60952,16));
+ s_LOGISIM_BUS_9(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35484,16));
- s_LOGISIM_BUS_69(15 DOWNTO 0) <= std_logic_vector(to_unsigned(34916,16));
+ s_LOGISIM_BUS_69(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
- s_LOGISIM_BUS_5(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
+ s_LOGISIM_BUS_121(15 DOWNTO 0) <= std_logic_vector(to_unsigned(45058,16));
- s_LOGISIM_BUS_72(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35484,16));
+ s_LOGISIM_BUS_60(15 DOWNTO 0) <= std_logic_vector(to_unsigned(49123,16));
- s_LOGISIM_BUS_6(15 DOWNTO 0) <= std_logic_vector(to_unsigned(34866,16));
+ s_LOGISIM_BUS_63(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33892,16));
- s_LOGISIM_BUS_75(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
+ s_LOGISIM_BUS_68(15 DOWNTO 0) <= std_logic_vector(to_unsigned(45058,16));
- s_LOGISIM_BUS_7(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35378,16));
+ s_LOGISIM_BUS_11(15 DOWNTO 0) <= std_logic_vector(to_unsigned(34816,16));
- s_LOGISIM_BUS_64(15 DOWNTO 0) <= std_logic_vector(to_unsigned(49664,16));
+ s_LOGISIM_BUS_10(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
- s_LOGISIM_BUS_124(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
+ s_LOGISIM_BUS_58(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35022,16));
- s_LOGISIM_BUS_65(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60946,16));
+ s_LOGISIM_BUS_130(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35534,16));
- s_LOGISIM_BUS_122(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
+ s_LOGISIM_BUS_76(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
- s_LOGISIM_BUS_66(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33892,16));
+ s_LOGISIM_BUS_75(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60970,16));
- s_LOGISIM_BUS_123(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
+ s_LOGISIM_BUS_65(15 DOWNTO 0) <= std_logic_vector(to_unsigned(45058,16));
- s_LOGISIM_BUS_67(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33892,16));
+ s_LOGISIM_BUS_70(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33911,16));
+
+ s_LOGISIM_BUS_72(15 DOWNTO 0) <= std_logic_vector(to_unsigned(33912,16));
+
+ s_LOGISIM_BUS_5(15 DOWNTO 0) <= std_logic_vector(to_unsigned(45058,16));
- s_LOGISIM_BUS_121(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
+ s_LOGISIM_BUS_66(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
- s_LOGISIM_BUS_63(15 DOWNTO 0) <= std_logic_vector(to_unsigned(49135,16));
+ s_LOGISIM_BUS_67(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
- s_LOGISIM_BUS_135(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35428,16));
+ s_LOGISIM_BUS_7(15 DOWNTO 0) <= std_logic_vector(to_unsigned(55810,16));
- s_LOGISIM_BUS_62(15 DOWNTO 0) <= std_logic_vector(to_unsigned(34972,16));
+ s_LOGISIM_BUS_61(15 DOWNTO 0) <= std_logic_vector(to_unsigned(45058,16));
+
+ s_LOGISIM_BUS_133(15 DOWNTO 0) <= std_logic_vector(to_unsigned(55297,16));
+
+ s_LOGISIM_BUS_64(15 DOWNTO 0) <= std_logic_vector(to_unsigned(49664,16));
- s_LOGISIM_BUS_134(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
+ s_LOGISIM_BUS_62(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60967,16));
- s_LOGISIM_BUS_61(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35534,16));
+ s_LOGISIM_BUS_129(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
- s_LOGISIM_BUS_133(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35022,16));
+ s_LOGISIM_BUS_74(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
+
+ s_LOGISIM_BUS_71(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60958,16));
+
+ s_LOGISIM_BUS_4(15 DOWNTO 0) <= std_logic_vector(to_unsigned(60961,16));
+
+ s_LOGISIM_BUS_73(15 DOWNTO 0) <= std_logic_vector(to_unsigned(34916,16));
+
+ s_LOGISIM_BUS_1(15 DOWNTO 0) <= std_logic_vector(to_unsigned(32784,16));
+
+ s_LOGISIM_BUS_134(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
+
+ s_LOGISIM_BUS_78(15 DOWNTO 0) <= std_logic_vector(to_unsigned(34866,16));
+
+ s_LOGISIM_BUS_135(15 DOWNTO 0) <= std_logic_vector(to_unsigned(43010,16));
+
+ s_LOGISIM_BUS_131(15 DOWNTO 0) <= std_logic_vector(to_unsigned(34972,16));
+
+ s_LOGISIM_BUS_124(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5712,16));
- s_LOGISIM_BUS_60(15 DOWNTO 0) <= std_logic_vector(to_unsigned(65024,16));
+ s_LOGISIM_BUS_132(15 DOWNTO 0) <= std_logic_vector(to_unsigned(35428,16));
-----------------------------------------------------------------------------
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd
index 19326433fb8ebd1b71374bab41d98662d7d00e1b..b7d336c89264cf7cce7be8aaf38fa4161597d0b1 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_behavior.vhd
@@ -87,191 +87,192 @@ ARCHITECTURE PlatformIndependent OF CPU_RAM24 IS
-- Here all used signals are defined --
-----------------------------------------------------------------------------
SIGNAL s_LOGISIM_BUS_0 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_14 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_13 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_17 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_18 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_19 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_2 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_21 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_20 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_25 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_26 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_27 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_29 : std_logic_vector( 4 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_28 : std_logic_vector( 4 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_30 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_31 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_5 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_7 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_8 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_9 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_NET_1 : std_logic;
- SIGNAL s_LOGISIM_NET_10 : std_logic;
+ SIGNAL s_LOGISIM_NET_11 : std_logic;
SIGNAL s_LOGISIM_NET_12 : std_logic;
- SIGNAL s_LOGISIM_NET_13 : std_logic;
+ SIGNAL s_LOGISIM_NET_14 : std_logic;
SIGNAL s_LOGISIM_NET_15 : std_logic;
SIGNAL s_LOGISIM_NET_16 : std_logic;
- SIGNAL s_LOGISIM_NET_17 : std_logic;
- SIGNAL s_LOGISIM_NET_20 : std_logic;
- SIGNAL s_LOGISIM_NET_22 : std_logic;
- SIGNAL s_LOGISIM_NET_25 : std_logic;
- SIGNAL s_LOGISIM_NET_28 : std_logic;
+ SIGNAL s_LOGISIM_NET_19 : std_logic;
+ SIGNAL s_LOGISIM_NET_21 : std_logic;
+ SIGNAL s_LOGISIM_NET_24 : std_logic;
+ SIGNAL s_LOGISIM_NET_27 : std_logic;
SIGNAL s_LOGISIM_NET_3 : std_logic;
SIGNAL s_LOGISIM_NET_4 : std_logic;
SIGNAL s_LOGISIM_NET_6 : std_logic;
+ SIGNAL s_LOGISIM_NET_9 : std_logic;
BEGIN
-----------------------------------------------------------------------------
-- Here all input connections are defined --
-----------------------------------------------------------------------------
- s_LOGISIM_NET_25 <= EN_WR;
- s_LOGISIM_NET_28 <= CLK;
- s_LOGISIM_NET_13 <= RESET;
- s_LOGISIM_BUS_26(7 DOWNTO 0) <= UART_BLUETOOTH;
- s_LOGISIM_BUS_29(4 DOWNTO 0) <= ADDR;
- s_LOGISIM_BUS_27(7 DOWNTO 0) <= DATA_WR;
+ s_LOGISIM_NET_24 <= EN_WR;
+ s_LOGISIM_NET_27 <= CLK;
+ s_LOGISIM_NET_12 <= RESET;
+ s_LOGISIM_BUS_25(7 DOWNTO 0) <= UART_BLUETOOTH;
+ s_LOGISIM_BUS_28(4 DOWNTO 0) <= ADDR;
+ s_LOGISIM_BUS_26(7 DOWNTO 0) <= DATA_WR;
-----------------------------------------------------------------------------
-- Here all output connections are defined --
-----------------------------------------------------------------------------
- DATA_OUT <= s_LOGISIM_BUS_18(7 DOWNTO 0);
- WHEEL_RIGHT_PWM <= s_LOGISIM_BUS_31(7 DOWNTO 0);
- WHEEL_LEFT_PWM <= s_LOGISIM_BUS_19(7 DOWNTO 0);
+ DATA_OUT <= s_LOGISIM_BUS_17(7 DOWNTO 0);
+ WHEEL_RIGHT_PWM <= s_LOGISIM_BUS_30(7 DOWNTO 0);
+ WHEEL_LEFT_PWM <= s_LOGISIM_BUS_18(7 DOWNTO 0);
+ UART_OUT <= s_LOGISIM_BUS_31(7 DOWNTO 0);
-----------------------------------------------------------------------------
-- Here all in-lined components are defined --
-----------------------------------------------------------------------------
- s_LOGISIM_NET_17 <= '1';
+ s_LOGISIM_NET_16 <= '1';
-----------------------------------------------------------------------------
-- Here all normal components are defined --
-----------------------------------------------------------------------------
GATE_1 : NOT_GATE
- PORT MAP ( Input_1 => s_LOGISIM_BUS_29(4),
- Result => s_LOGISIM_NET_10);
+ PORT MAP ( Input_1 => s_LOGISIM_BUS_28(4),
+ Result => s_LOGISIM_NET_9);
GATE_2 : AND_GATE
GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_25,
- Input_2 => s_LOGISIM_NET_10,
- Result => s_LOGISIM_NET_20);
+ PORT MAP ( Input_1 => s_LOGISIM_NET_24,
+ Input_2 => s_LOGISIM_NET_9,
+ Result => s_LOGISIM_NET_19);
GATE_3 : AND_GATE
GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_25,
- Input_2 => s_LOGISIM_BUS_29(4),
+ PORT MAP ( Input_1 => s_LOGISIM_NET_24,
+ Input_2 => s_LOGISIM_BUS_28(4),
Result => s_LOGISIM_NET_4);
MUX_1 : Multiplexer_bus_8
GENERIC MAP ( NrOfBits => 8)
PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_7(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_31(7 DOWNTO 0),
- MuxIn_2 => s_LOGISIM_BUS_19(7 DOWNTO 0),
+ MuxIn_0 => s_LOGISIM_BUS_31(7 DOWNTO 0),
+ MuxIn_1 => s_LOGISIM_BUS_30(7 DOWNTO 0),
+ MuxIn_2 => s_LOGISIM_BUS_18(7 DOWNTO 0),
MuxIn_3 => s_LOGISIM_BUS_5(7 DOWNTO 0),
- MuxIn_4 => s_LOGISIM_BUS_21(7 DOWNTO 0),
- MuxIn_5 => s_LOGISIM_BUS_9(7 DOWNTO 0),
- MuxIn_6 => s_LOGISIM_BUS_14(7 DOWNTO 0),
+ MuxIn_4 => s_LOGISIM_BUS_20(7 DOWNTO 0),
+ MuxIn_5 => s_LOGISIM_BUS_8(7 DOWNTO 0),
+ MuxIn_6 => s_LOGISIM_BUS_13(7 DOWNTO 0),
MuxIn_7 => s_LOGISIM_BUS_0(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_8(7 DOWNTO 0),
- Sel => s_LOGISIM_BUS_29(2 DOWNTO 0));
+ MuxOut => s_LOGISIM_BUS_7(7 DOWNTO 0),
+ Sel => s_LOGISIM_BUS_28(2 DOWNTO 0));
MUX_2 : Multiplexer_bus_2
GENERIC MAP ( NrOfBits => 8)
PORT MAP ( Enable => '1',
MuxIn_0 => s_LOGISIM_BUS_2(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_8(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_18(7 DOWNTO 0),
- Sel => s_LOGISIM_BUS_29(4));
+ MuxIn_1 => s_LOGISIM_BUS_7(7 DOWNTO 0),
+ MuxOut => s_LOGISIM_BUS_17(7 DOWNTO 0),
+ Sel => s_LOGISIM_BUS_28(4));
DEMUX_1 : Demultiplexer_8
PORT MAP ( DemuxIn => s_LOGISIM_NET_4,
DemuxOut_0 => OPEN,
DemuxOut_1 => s_LOGISIM_NET_3,
- DemuxOut_2 => s_LOGISIM_NET_22,
+ DemuxOut_2 => s_LOGISIM_NET_21,
DemuxOut_3 => s_LOGISIM_NET_1,
- DemuxOut_4 => s_LOGISIM_NET_12,
- DemuxOut_5 => s_LOGISIM_NET_16,
- DemuxOut_6 => s_LOGISIM_NET_15,
+ DemuxOut_4 => s_LOGISIM_NET_11,
+ DemuxOut_5 => s_LOGISIM_NET_15,
+ DemuxOut_6 => s_LOGISIM_NET_14,
DemuxOut_7 => s_LOGISIM_NET_6,
Enable => '1',
- Sel => s_LOGISIM_BUS_29(2 DOWNTO 0));
+ Sel => s_LOGISIM_BUS_28(2 DOWNTO 0));
REGISTER_FILE_1 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
- ClockEnable => s_LOGISIM_NET_12,
- D => s_LOGISIM_BUS_27(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_21(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
+ ClockEnable => s_LOGISIM_NET_11,
+ D => s_LOGISIM_BUS_26(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_20(7 DOWNTO 0),
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
REGISTER_FILE_2 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
- ClockEnable => s_LOGISIM_NET_16,
- D => s_LOGISIM_BUS_27(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_9(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
+ ClockEnable => s_LOGISIM_NET_15,
+ D => s_LOGISIM_BUS_26(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_8(7 DOWNTO 0),
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
REGISTER_FILE_3 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
- ClockEnable => s_LOGISIM_NET_15,
- D => s_LOGISIM_BUS_27(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_14(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
+ ClockEnable => s_LOGISIM_NET_14,
+ D => s_LOGISIM_BUS_26(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_13(7 DOWNTO 0),
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
REGISTER_FILE_4 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
ClockEnable => s_LOGISIM_NET_6,
- D => s_LOGISIM_BUS_27(7 DOWNTO 0),
+ D => s_LOGISIM_BUS_26(7 DOWNTO 0),
Q => s_LOGISIM_BUS_0(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
REGISTER_FILE_5 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
- ClockEnable => s_LOGISIM_NET_17,
- D => s_LOGISIM_BUS_26(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_7(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
+ ClockEnable => s_LOGISIM_NET_16,
+ D => s_LOGISIM_BUS_25(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_31(7 DOWNTO 0),
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
REGISTER_FILE_6 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
ClockEnable => s_LOGISIM_NET_3,
- D => s_LOGISIM_BUS_27(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_31(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ D => s_LOGISIM_BUS_26(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_30(7 DOWNTO 0),
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
REGISTER_FILE_7 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
- ClockEnable => s_LOGISIM_NET_22,
- D => s_LOGISIM_BUS_27(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_19(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
+ ClockEnable => s_LOGISIM_NET_21,
+ D => s_LOGISIM_BUS_26(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_18(7 DOWNTO 0),
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
REGISTER_FILE_8 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_28,
+ PORT MAP ( Clock => s_LOGISIM_NET_27,
ClockEnable => s_LOGISIM_NET_1,
- D => s_LOGISIM_BUS_27(7 DOWNTO 0),
+ D => s_LOGISIM_BUS_26(7 DOWNTO 0),
Q => s_LOGISIM_BUS_5(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_13,
+ Reset => s_LOGISIM_NET_12,
Tick => '1');
@@ -279,12 +280,12 @@ BEGIN
-- Here all sub-circuits are defined --
-----------------------------------------------------------------------------
RAM16_PROCESSOR : CPU_RAM16
- PORT MAP ( ADD => s_LOGISIM_BUS_29(3 DOWNTO 0),
- CLK => s_LOGISIM_NET_28,
+ PORT MAP ( ADD => s_LOGISIM_BUS_28(3 DOWNTO 0),
+ CLK => s_LOGISIM_NET_27,
DATA_OUT => s_LOGISIM_BUS_2(7 DOWNTO 0),
- DATA_WR => s_LOGISIM_BUS_27(7 DOWNTO 0),
- EN_WR => s_LOGISIM_NET_20,
- RESET => s_LOGISIM_NET_13);
+ DATA_WR => s_LOGISIM_BUS_26(7 DOWNTO 0),
+ EN_WR => s_LOGISIM_NET_19,
+ RESET => s_LOGISIM_NET_12);
END PlatformIndependent;
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd
index 919bf0d598a18f717a92b6e08c6adba47c195577..42efaab123ed23f23814015d467ad04f92b64560 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_RAM24_entity.vhd
@@ -20,6 +20,7 @@ ENTITY CPU_RAM24 IS
RESET : IN std_logic;
UART_BLUETOOTH : IN std_logic_vector( 7 DOWNTO 0 );
DATA_OUT : OUT std_logic_vector( 7 DOWNTO 0 );
+ UART_OUT : OUT std_logic_vector( 7 DOWNTO 0 );
WHEEL_LEFT_PWM : OUT std_logic_vector( 7 DOWNTO 0 );
WHEEL_RIGHT_PWM : OUT std_logic_vector( 7 DOWNTO 0 ));
END CPU_RAM24;
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd
index ce61d931c26df2d9a0bad428caf5eb2f9ed645c1..74281fb365a17869ba341f5a49dcad249ab4cbb6 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/CPU_behavior.vhd
@@ -51,16 +51,6 @@ ARCHITECTURE PlatformIndependent OF CPU IS
MuxOut : OUT std_logic_vector( (NrOfBits-1) DOWNTO 0 ));
END COMPONENT;
- COMPONENT Adder
- GENERIC ( ExtendedBits : INTEGER;
- NrOfBits : INTEGER);
- PORT ( CarryIn : IN std_logic;
- DataA : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
- DataB : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
- CarryOut : OUT std_logic;
- Result : OUT std_logic_vector( (NrOfBits-1) DOWNTO 0 ));
- END COMPONENT;
-
COMPONENT Comparator
GENERIC ( TwosComplement : INTEGER;
NrOfBits : INTEGER);
@@ -82,9 +72,22 @@ ARCHITECTURE PlatformIndependent OF CPU IS
Q : OUT std_logic_vector( (NrOfBits-1) DOWNTO 0 ));
END COMPONENT;
- COMPONENT CPU_INSTRUCTION_MEMORY
- PORT ( ADDR_INSTR : IN std_logic_vector( 6 DOWNTO 0 );
- INSTRUCTION : OUT std_logic_vector( 15 DOWNTO 0 ));
+ COMPONENT Adder
+ GENERIC ( ExtendedBits : INTEGER;
+ NrOfBits : INTEGER);
+ PORT ( CarryIn : IN std_logic;
+ DataA : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
+ DataB : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
+ CarryOut : OUT std_logic;
+ Result : OUT std_logic_vector( (NrOfBits-1) DOWNTO 0 ));
+ END COMPONENT;
+
+ COMPONENT OR_GATE_3_INPUTS
+ GENERIC ( BubblesMask : INTEGER);
+ PORT ( Input_1 : IN std_logic;
+ Input_2 : IN std_logic;
+ Input_3 : IN std_logic;
+ Result : OUT std_logic);
END COMPONENT;
COMPONENT ALU
@@ -110,56 +113,61 @@ ARCHITECTURE PlatformIndependent OF CPU IS
OUT_B : OUT std_logic_vector( 7 DOWNTO 0 ));
END COMPONENT;
+ COMPONENT CPU_INSTRUCTION_MEMORY
+ PORT ( ADDR_INSTR : IN std_logic_vector( 6 DOWNTO 0 );
+ INSTRUCTION : OUT std_logic_vector( 15 DOWNTO 0 ));
+ END COMPONENT;
+
-----------------------------------------------------------------------------
-- Here all used signals are defined --
-----------------------------------------------------------------------------
- SIGNAL s_LOGISIM_BUS_0 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_13 : std_logic_vector( 2 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_14 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_15 : std_logic_vector( 2 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_16 : std_logic_vector( 2 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_18 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_20 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_19 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_2 : std_logic_vector( 2 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_22 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_23 : std_logic_vector( 3 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_26 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_30 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_24 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_31 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_34 : std_logic_vector( 3 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_35 : std_logic_vector( 5 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_32 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_33 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_37 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_38 : std_logic_vector( 5 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_4 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_40 : std_logic_vector( 3 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_43 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_44 : std_logic_vector( 3 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_45 : std_logic_vector( 3 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_46 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_40 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_43 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_46 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_47 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_48 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_49 : std_logic_vector( 3 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_5 : std_logic_vector( 2 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_50 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_51 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_52 : std_logic_vector( 15 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_57 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_59 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_60 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_61 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_62 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_63 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_66 : std_logic_vector( 3 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_67 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_7 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_8 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_9 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_NET_10 : std_logic;
- SIGNAL s_LOGISIM_NET_13 : std_logic;
- SIGNAL s_LOGISIM_NET_14 : std_logic;
- SIGNAL s_LOGISIM_NET_19 : std_logic;
- SIGNAL s_LOGISIM_NET_2 : std_logic;
- SIGNAL s_LOGISIM_NET_22 : std_logic;
- SIGNAL s_LOGISIM_NET_24 : std_logic;
- SIGNAL s_LOGISIM_NET_28 : std_logic;
- SIGNAL s_LOGISIM_NET_33 : std_logic;
- SIGNAL s_LOGISIM_NET_37 : std_logic;
- SIGNAL s_LOGISIM_NET_38 : std_logic;
+ SIGNAL s_LOGISIM_NET_11 : std_logic;
+ SIGNAL s_LOGISIM_NET_12 : std_logic;
+ SIGNAL s_LOGISIM_NET_20 : std_logic;
+ SIGNAL s_LOGISIM_NET_26 : std_logic;
+ SIGNAL s_LOGISIM_NET_34 : std_logic;
+ SIGNAL s_LOGISIM_NET_36 : std_logic;
SIGNAL s_LOGISIM_NET_41 : std_logic;
- SIGNAL s_LOGISIM_NET_48 : std_logic;
+ SIGNAL s_LOGISIM_NET_44 : std_logic;
+ SIGNAL s_LOGISIM_NET_5 : std_logic;
SIGNAL s_LOGISIM_NET_53 : std_logic;
SIGNAL s_LOGISIM_NET_54 : std_logic;
SIGNAL s_LOGISIM_NET_55 : std_logic;
+ SIGNAL s_LOGISIM_NET_59 : std_logic;
+ SIGNAL s_LOGISIM_NET_6 : std_logic;
+ SIGNAL s_LOGISIM_NET_62 : std_logic;
SIGNAL s_LOGISIM_NET_65 : std_logic;
BEGIN
@@ -167,57 +175,57 @@ BEGIN
-----------------------------------------------------------------------------
-- Here all wiring is defined --
-----------------------------------------------------------------------------
- s_LOGISIM_BUS_35(0) <= s_LOGISIM_BUS_52(0);
- s_LOGISIM_BUS_9(2) <= s_LOGISIM_BUS_35(0);
- s_LOGISIM_BUS_35(1) <= s_LOGISIM_BUS_52(1);
- s_LOGISIM_BUS_9(3) <= s_LOGISIM_BUS_35(1);
- s_LOGISIM_BUS_35(2) <= s_LOGISIM_BUS_52(2);
- s_LOGISIM_BUS_9(4) <= s_LOGISIM_BUS_35(2);
- s_LOGISIM_BUS_35(3) <= s_LOGISIM_BUS_52(3);
- s_LOGISIM_BUS_9(5) <= s_LOGISIM_BUS_35(3);
- s_LOGISIM_BUS_35(4) <= s_LOGISIM_BUS_52(4);
- s_LOGISIM_BUS_9(6) <= s_LOGISIM_BUS_35(4);
- s_LOGISIM_BUS_35(5) <= s_LOGISIM_BUS_52(5);
- s_LOGISIM_BUS_9(7) <= s_LOGISIM_BUS_35(5);
- s_LOGISIM_BUS_46(0) <= s_LOGISIM_BUS_52(12);
- s_LOGISIM_BUS_46(1) <= s_LOGISIM_BUS_52(13);
- s_LOGISIM_BUS_46(2) <= s_LOGISIM_BUS_52(14);
- s_LOGISIM_BUS_46(3) <= s_LOGISIM_BUS_52(15);
+ s_LOGISIM_BUS_38(0) <= s_LOGISIM_BUS_52(0);
+ s_LOGISIM_BUS_22(0) <= s_LOGISIM_BUS_38(0);
+ s_LOGISIM_BUS_38(1) <= s_LOGISIM_BUS_52(1);
+ s_LOGISIM_BUS_22(1) <= s_LOGISIM_BUS_38(1);
+ s_LOGISIM_BUS_38(2) <= s_LOGISIM_BUS_52(2);
+ s_LOGISIM_BUS_22(2) <= s_LOGISIM_BUS_38(2);
+ s_LOGISIM_BUS_38(3) <= s_LOGISIM_BUS_52(3);
+ s_LOGISIM_BUS_22(3) <= s_LOGISIM_BUS_38(3);
+ s_LOGISIM_BUS_38(4) <= s_LOGISIM_BUS_52(4);
+ s_LOGISIM_BUS_22(4) <= s_LOGISIM_BUS_38(4);
+ s_LOGISIM_BUS_38(5) <= s_LOGISIM_BUS_52(5);
+ s_LOGISIM_BUS_22(5) <= s_LOGISIM_BUS_38(5);
+ s_LOGISIM_BUS_49(0) <= s_LOGISIM_BUS_52(12);
+ s_LOGISIM_BUS_49(1) <= s_LOGISIM_BUS_52(13);
+ s_LOGISIM_BUS_49(2) <= s_LOGISIM_BUS_52(14);
+ s_LOGISIM_BUS_49(3) <= s_LOGISIM_BUS_52(15);
-----------------------------------------------------------------------------
-- Here all input connections are defined --
-----------------------------------------------------------------------------
+ s_LOGISIM_NET_20 <= RESET;
s_LOGISIM_NET_65 <= CLK;
- s_LOGISIM_NET_19 <= RESET;
- s_LOGISIM_BUS_59(7 DOWNTO 0) <= WB_RAM;
+ s_LOGISIM_BUS_61(7 DOWNTO 0) <= WB_RAM;
-----------------------------------------------------------------------------
-- Here all output connections are defined --
-----------------------------------------------------------------------------
- RAM_DATA_WR <= s_LOGISIM_BUS_67(7 DOWNTO 0);
- RAM_ADDR <= s_LOGISIM_BUS_31(4 DOWNTO 0);
+ RAM_DATA_WR <= s_LOGISIM_BUS_9(7 DOWNTO 0);
RAM_EN_WR <= s_LOGISIM_NET_54;
+ RAM_ADDR <= s_LOGISIM_BUS_40(4 DOWNTO 0);
-----------------------------------------------------------------------------
-- Here all in-lined components are defined --
-----------------------------------------------------------------------------
- s_LOGISIM_BUS_9(1 DOWNTO 0) <= std_logic_vector(to_unsigned(0,2));
+ s_LOGISIM_BUS_50(3 DOWNTO 0) <= std_logic_vector(to_unsigned(11,4));
- s_LOGISIM_BUS_20(7 DOWNTO 0) <= std_logic_vector(to_unsigned(1,8));
+ s_LOGISIM_BUS_66(3 DOWNTO 0) <= std_logic_vector(to_unsigned(10,4));
- s_LOGISIM_BUS_49(3 DOWNTO 0) <= std_logic_vector(to_unsigned(11,4));
+ s_LOGISIM_BUS_47(3 DOWNTO 0) <= std_logic_vector(to_unsigned(12,4));
- s_LOGISIM_BUS_66(3 DOWNTO 0) <= std_logic_vector(to_unsigned(10,4));
+ s_LOGISIM_BUS_48(3 DOWNTO 0) <= std_logic_vector(to_unsigned(13,4));
- s_LOGISIM_BUS_44(3 DOWNTO 0) <= std_logic_vector(to_unsigned(12,4));
+ s_LOGISIM_BUS_63(3 DOWNTO 0) <= std_logic_vector(to_unsigned(8,4));
- s_LOGISIM_BUS_45(3 DOWNTO 0) <= std_logic_vector(to_unsigned(13,4));
+ s_LOGISIM_BUS_23(3 DOWNTO 0) <= std_logic_vector(to_unsigned(9,4));
- s_LOGISIM_NET_37 <= '1';
+ s_LOGISIM_NET_59 <= '1';
- s_LOGISIM_BUS_62(3 DOWNTO 0) <= std_logic_vector(to_unsigned(8,4));
+ s_LOGISIM_BUS_24(7 DOWNTO 0) <= std_logic_vector(to_unsigned(1,8));
- s_LOGISIM_BUS_23(3 DOWNTO 0) <= std_logic_vector(to_unsigned(9,4));
+ s_LOGISIM_BUS_22(7 DOWNTO 6) <= std_logic_vector(to_unsigned(0,2));
-----------------------------------------------------------------------------
@@ -225,159 +233,106 @@ BEGIN
-----------------------------------------------------------------------------
GATE_1 : AND_GATE
GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_BUS_46(0),
- Input_2 => s_LOGISIM_NET_22,
- Result => s_LOGISIM_NET_14);
+ PORT MAP ( Input_1 => s_LOGISIM_BUS_49(0),
+ Input_2 => s_LOGISIM_NET_34,
+ Result => s_LOGISIM_NET_12);
GATE_2 : AND_GATE
GENERIC MAP ( BubblesMask => 1)
- PORT MAP ( Input_1 => s_LOGISIM_BUS_46(0),
- Input_2 => s_LOGISIM_NET_22,
- Result => s_LOGISIM_NET_41);
+ PORT MAP ( Input_1 => s_LOGISIM_BUS_49(0),
+ Input_2 => s_LOGISIM_NET_34,
+ Result => s_LOGISIM_NET_44);
GATE_3 : AND_GATE
GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_10,
- Input_2 => s_LOGISIM_NET_13,
- Result => s_LOGISIM_NET_38);
+ PORT MAP ( Input_1 => s_LOGISIM_NET_6,
+ Input_2 => s_LOGISIM_NET_10,
+ Result => s_LOGISIM_NET_41);
GATE_4 : OR_GATE
GENERIC MAP ( BubblesMask => 0)
PORT MAP ( Input_1 => s_LOGISIM_NET_53,
Input_2 => s_LOGISIM_NET_54,
- Result => s_LOGISIM_NET_24);
-
- GATE_5 : OR_GATE
- GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_33,
- Input_2 => s_LOGISIM_NET_38,
- Result => s_LOGISIM_NET_2);
-
- GATE_6 : OR_GATE
- GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_53,
- Input_2 => s_LOGISIM_NET_54,
- Result => s_LOGISIM_NET_28);
+ Result => s_LOGISIM_NET_26);
- GATE_7 : AND_GATE_BUS
+ GATE_5 : AND_GATE_BUS
GENERIC MAP ( BubblesMask => 0,
NrOfBits => 4)
- PORT MAP ( Input_1 => s_LOGISIM_BUS_34(3 DOWNTO 0),
+ PORT MAP ( Input_1 => s_LOGISIM_BUS_37(3 DOWNTO 0),
Input_2 => s_LOGISIM_BUS_52(11 DOWNTO 8),
Result => s_LOGISIM_BUS_60(3 DOWNTO 0));
- GATE_8 : AND_GATE_3_INPUTS
+ GATE_6 : AND_GATE_3_INPUTS
GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_BUS_46(1),
- Input_2 => s_LOGISIM_BUS_46(2),
- Input_3 => s_LOGISIM_BUS_46(3),
- Result => s_LOGISIM_NET_22);
+ PORT MAP ( Input_1 => s_LOGISIM_BUS_49(1),
+ Input_2 => s_LOGISIM_BUS_49(2),
+ Input_3 => s_LOGISIM_BUS_49(3),
+ Result => s_LOGISIM_NET_34);
MUX_1 : Multiplexer_bus_2
- GENERIC MAP ( NrOfBits => 8)
- PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_67(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_9(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_7(7 DOWNTO 0),
- Sel => s_LOGISIM_NET_24);
-
- MUX_2 : Multiplexer_bus_2
- GENERIC MAP ( NrOfBits => 8)
- PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_20(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_52(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_26(7 DOWNTO 0),
- Sel => s_LOGISIM_NET_2);
-
- MUX_3 : Multiplexer_bus_2
GENERIC MAP ( NrOfBits => 8)
PORT MAP ( Enable => '1',
MuxIn_0 => s_LOGISIM_BUS_52(7 DOWNTO 0),
MuxIn_1 => s_LOGISIM_BUS_57(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_8(7 DOWNTO 0),
- Sel => s_LOGISIM_NET_41);
+ MuxOut => s_LOGISIM_BUS_4(7 DOWNTO 0),
+ Sel => s_LOGISIM_NET_44);
- MUX_4 : Multiplexer_bus_2
+ MUX_2 : Multiplexer_bus_2
GENERIC MAP ( NrOfBits => 3)
PORT MAP ( Enable => '1',
MuxIn_0 => s_LOGISIM_BUS_52(8 DOWNTO 6),
MuxIn_1 => s_LOGISIM_BUS_52(11 DOWNTO 9),
- MuxOut => s_LOGISIM_BUS_15(2 DOWNTO 0),
- Sel => s_LOGISIM_NET_14);
+ MuxOut => s_LOGISIM_BUS_13(2 DOWNTO 0),
+ Sel => s_LOGISIM_NET_12);
- MUX_5 : Multiplexer_bus_2
+ MUX_3 : Multiplexer_bus_2
GENERIC MAP ( NrOfBits => 8)
PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_31(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_8(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_43(7 DOWNTO 0),
- Sel => s_LOGISIM_BUS_46(3));
+ MuxIn_0 => s_LOGISIM_BUS_32(7 DOWNTO 0),
+ MuxIn_1 => s_LOGISIM_BUS_4(7 DOWNTO 0),
+ MuxOut => s_LOGISIM_BUS_46(7 DOWNTO 0),
+ Sel => s_LOGISIM_BUS_49(3));
- MUX_6 : Multiplexer_bus_2
+ MUX_4 : Multiplexer_bus_2
GENERIC MAP ( NrOfBits => 3)
PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_15(2 DOWNTO 0),
+ MuxIn_0 => s_LOGISIM_BUS_13(2 DOWNTO 0),
MuxIn_1 => s_LOGISIM_BUS_52(8 DOWNTO 6),
- MuxOut => s_LOGISIM_BUS_5(2 DOWNTO 0),
- Sel => s_LOGISIM_NET_28);
+ MuxOut => s_LOGISIM_BUS_2(2 DOWNTO 0),
+ Sel => s_LOGISIM_NET_26);
- MUX_7 : Multiplexer_bus_2
+ MUX_5 : Multiplexer_bus_2
GENERIC MAP ( NrOfBits => 8)
PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_43(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_59(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_61(7 DOWNTO 0),
+ MuxIn_0 => s_LOGISIM_BUS_46(7 DOWNTO 0),
+ MuxIn_1 => s_LOGISIM_BUS_61(7 DOWNTO 0),
+ MuxOut => s_LOGISIM_BUS_18(7 DOWNTO 0),
Sel => s_LOGISIM_NET_53);
- MUX_8 : Multiplexer_bus_2
- GENERIC MAP ( NrOfBits => 8)
- PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_30(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_52(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_4(7 DOWNTO 0),
- Sel => s_LOGISIM_NET_41);
-
- MUX_9 : Multiplexer_bus_2
+ MUX_6 : Multiplexer_bus_2
GENERIC MAP ( NrOfBits => 3)
PORT MAP ( Enable => '1',
MuxIn_0 => s_LOGISIM_BUS_52(5 DOWNTO 3),
MuxIn_1 => s_LOGISIM_BUS_52(11 DOWNTO 9),
- MuxOut => s_LOGISIM_BUS_16(2 DOWNTO 0),
+ MuxOut => s_LOGISIM_BUS_15(2 DOWNTO 0),
Sel => s_LOGISIM_NET_54);
- MUX_10 : Multiplexer_bus_2
- GENERIC MAP ( NrOfBits => 8)
- PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_BUS_57(7 DOWNTO 0),
- MuxIn_1 => s_LOGISIM_BUS_4(7 DOWNTO 0),
- MuxOut => s_LOGISIM_BUS_18(7 DOWNTO 0),
- Sel => s_LOGISIM_NET_22);
-
- ADDER2C_1 : Adder
- GENERIC MAP ( ExtendedBits => 9,
- NrOfBits => 8)
- PORT MAP ( CarryIn => '0',
- CarryOut => OPEN,
- DataA => s_LOGISIM_BUS_26(7 DOWNTO 0),
- DataB => s_LOGISIM_BUS_0(7 DOWNTO 0),
- Result => s_LOGISIM_BUS_57(7 DOWNTO 0));
-
Comparator_1 : Comparator
GENERIC MAP ( NrOfBits => 4,
TwosComplement => 0)
- PORT MAP ( A_EQ_B => s_LOGISIM_NET_33,
+ PORT MAP ( A_EQ_B => s_LOGISIM_NET_36,
A_GT_B => OPEN,
A_LT_B => OPEN,
- DataA => s_LOGISIM_BUS_46(3 DOWNTO 0),
- DataB => s_LOGISIM_BUS_49(3 DOWNTO 0));
+ DataA => s_LOGISIM_BUS_49(3 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_50(3 DOWNTO 0));
Comparator_2 : Comparator
GENERIC MAP ( NrOfBits => 4,
TwosComplement => 0)
- PORT MAP ( A_EQ_B => s_LOGISIM_NET_10,
+ PORT MAP ( A_EQ_B => s_LOGISIM_NET_6,
A_GT_B => OPEN,
A_LT_B => OPEN,
- DataA => s_LOGISIM_BUS_46(3 DOWNTO 0),
+ DataA => s_LOGISIM_BUS_49(3 DOWNTO 0),
DataB => s_LOGISIM_BUS_66(3 DOWNTO 0));
Comparator_3 : Comparator
@@ -386,8 +341,8 @@ BEGIN
PORT MAP ( A_EQ_B => s_LOGISIM_NET_53,
A_GT_B => OPEN,
A_LT_B => OPEN,
- DataA => s_LOGISIM_BUS_46(3 DOWNTO 0),
- DataB => s_LOGISIM_BUS_44(3 DOWNTO 0));
+ DataA => s_LOGISIM_BUS_49(3 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_47(3 DOWNTO 0));
Comparator_4 : Comparator
GENERIC MAP ( NrOfBits => 4,
@@ -395,8 +350,8 @@ BEGIN
PORT MAP ( A_EQ_B => s_LOGISIM_NET_54,
A_GT_B => OPEN,
A_LT_B => OPEN,
- DataA => s_LOGISIM_BUS_46(3 DOWNTO 0),
- DataB => s_LOGISIM_BUS_45(3 DOWNTO 0));
+ DataA => s_LOGISIM_BUS_49(3 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_48(3 DOWNTO 0));
Comparator_5 : Comparator
GENERIC MAP ( NrOfBits => 4,
@@ -404,22 +359,22 @@ BEGIN
PORT MAP ( A_EQ_B => OPEN,
A_GT_B => OPEN,
A_LT_B => s_LOGISIM_NET_55,
- DataA => s_LOGISIM_BUS_46(3 DOWNTO 0),
- DataB => s_LOGISIM_BUS_62(3 DOWNTO 0));
+ DataA => s_LOGISIM_BUS_49(3 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_63(3 DOWNTO 0));
Comparator_6 : Comparator
GENERIC MAP ( NrOfBits => 4,
TwosComplement => 0)
PORT MAP ( A_EQ_B => OPEN,
A_GT_B => OPEN,
- A_LT_B => s_LOGISIM_NET_48,
- DataA => s_LOGISIM_BUS_46(3 DOWNTO 0),
+ A_LT_B => s_LOGISIM_NET_62,
+ DataA => s_LOGISIM_BUS_49(3 DOWNTO 0),
DataB => s_LOGISIM_BUS_23(3 DOWNTO 0));
Comparator_7 : Comparator
GENERIC MAP ( NrOfBits => 4,
TwosComplement => 0)
- PORT MAP ( A_EQ_B => s_LOGISIM_NET_13,
+ PORT MAP ( A_EQ_B => s_LOGISIM_NET_10,
A_GT_B => OPEN,
A_LT_B => OPEN,
DataA => s_LOGISIM_BUS_60(3 DOWNTO 0),
@@ -430,49 +385,104 @@ BEGIN
NrOfBits => 4)
PORT MAP ( Clock => s_LOGISIM_NET_65,
ClockEnable => s_LOGISIM_NET_55,
- D => s_LOGISIM_BUS_40(3 DOWNTO 0),
- Q => s_LOGISIM_BUS_34(3 DOWNTO 0),
- Reset => s_LOGISIM_NET_19,
+ D => s_LOGISIM_BUS_43(3 DOWNTO 0),
+ Q => s_LOGISIM_BUS_37(3 DOWNTO 0),
+ Reset => s_LOGISIM_NET_20,
Tick => '1');
+ ADDER2C_1 : Adder
+ GENERIC MAP ( ExtendedBits => 9,
+ NrOfBits => 8)
+ PORT MAP ( CarryIn => '0',
+ CarryOut => OPEN,
+ DataA => s_LOGISIM_BUS_33(7 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_19(7 DOWNTO 0),
+ Result => s_LOGISIM_BUS_57(7 DOWNTO 0));
+
+ MUX_7 : Multiplexer_bus_2
+ GENERIC MAP ( NrOfBits => 8)
+ PORT MAP ( Enable => '1',
+ MuxIn_0 => s_LOGISIM_BUS_57(7 DOWNTO 0),
+ MuxIn_1 => s_LOGISIM_BUS_14(7 DOWNTO 0),
+ MuxOut => s_LOGISIM_BUS_31(7 DOWNTO 0),
+ Sel => s_LOGISIM_NET_34);
+
REGISTER_FILE_2 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
PORT MAP ( Clock => s_LOGISIM_NET_65,
- ClockEnable => s_LOGISIM_NET_37,
- D => s_LOGISIM_BUS_18(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_0(7 DOWNTO 0),
- Reset => s_LOGISIM_NET_19,
+ ClockEnable => s_LOGISIM_NET_59,
+ D => s_LOGISIM_BUS_31(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_19(7 DOWNTO 0),
+ Reset => s_LOGISIM_NET_20,
Tick => '1');
+ MUX_8 : Multiplexer_bus_2
+ GENERIC MAP ( NrOfBits => 8)
+ PORT MAP ( Enable => '1',
+ MuxIn_0 => s_LOGISIM_BUS_51(7 DOWNTO 0),
+ MuxIn_1 => s_LOGISIM_BUS_52(7 DOWNTO 0),
+ MuxOut => s_LOGISIM_BUS_14(7 DOWNTO 0),
+ Sel => s_LOGISIM_NET_44);
+
+ MUX_9 : Multiplexer_bus_2
+ GENERIC MAP ( NrOfBits => 8)
+ PORT MAP ( Enable => '1',
+ MuxIn_0 => s_LOGISIM_BUS_24(7 DOWNTO 0),
+ MuxIn_1 => s_LOGISIM_BUS_52(7 DOWNTO 0),
+ MuxOut => s_LOGISIM_BUS_33(7 DOWNTO 0),
+ Sel => s_LOGISIM_NET_11);
+
+ GATE_7 : OR_GATE
+ GENERIC MAP ( BubblesMask => 0)
+ PORT MAP ( Input_1 => s_LOGISIM_NET_36,
+ Input_2 => s_LOGISIM_NET_41,
+ Result => s_LOGISIM_NET_11);
+
+ ADDER2C_2 : Adder
+ GENERIC MAP ( ExtendedBits => 9,
+ NrOfBits => 8)
+ PORT MAP ( CarryIn => '0',
+ CarryOut => OPEN,
+ DataA => s_LOGISIM_BUS_51(7 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_22(7 DOWNTO 0),
+ Result => s_LOGISIM_BUS_40(7 DOWNTO 0));
+
+ GATE_8 : OR_GATE_3_INPUTS
+ GENERIC MAP ( BubblesMask => 0)
+ PORT MAP ( Input_1 => s_LOGISIM_NET_53,
+ Input_2 => s_LOGISIM_NET_62,
+ Input_3 => s_LOGISIM_NET_44,
+ Result => s_LOGISIM_NET_5);
+
-----------------------------------------------------------------------------
-- Here all sub-circuits are defined --
-----------------------------------------------------------------------------
- CIM_1 : CPU_INSTRUCTION_MEMORY
- PORT MAP ( ADDR_INSTR => s_LOGISIM_BUS_0(6 DOWNTO 0),
- INSTRUCTION => s_LOGISIM_BUS_52(15 DOWNTO 0));
-
ALU1 : ALU
- PORT MAP ( A_in => s_LOGISIM_BUS_30(7 DOWNTO 0),
- B_in => s_LOGISIM_BUS_7(7 DOWNTO 0),
- C => s_LOGISIM_BUS_40(1),
- N => s_LOGISIM_BUS_40(2),
- OP_in => s_LOGISIM_BUS_46(2 DOWNTO 0),
- R => s_LOGISIM_BUS_31(7 DOWNTO 0),
- V => s_LOGISIM_BUS_40(0),
- Z => s_LOGISIM_BUS_40(3));
+ PORT MAP ( A_in => s_LOGISIM_BUS_51(7 DOWNTO 0),
+ B_in => s_LOGISIM_BUS_9(7 DOWNTO 0),
+ C => s_LOGISIM_BUS_43(1),
+ N => s_LOGISIM_BUS_43(2),
+ OP_in => s_LOGISIM_BUS_49(2 DOWNTO 0),
+ R => s_LOGISIM_BUS_32(7 DOWNTO 0),
+ V => s_LOGISIM_BUS_43(0),
+ Z => s_LOGISIM_BUS_43(3));
CRB : CPU_REG_BANK
- PORT MAP ( ADD_A => s_LOGISIM_BUS_5(2 DOWNTO 0),
- ADD_B => s_LOGISIM_BUS_16(2 DOWNTO 0),
+ PORT MAP ( ADD_A => s_LOGISIM_BUS_2(2 DOWNTO 0),
+ ADD_B => s_LOGISIM_BUS_15(2 DOWNTO 0),
ADD_WR => s_LOGISIM_BUS_52(11 DOWNTO 9),
CLK => s_LOGISIM_NET_65,
- DATA_WR => s_LOGISIM_BUS_61(7 DOWNTO 0),
- EN_WR => s_LOGISIM_NET_48,
- OUT_A => s_LOGISIM_BUS_30(7 DOWNTO 0),
- OUT_B => s_LOGISIM_BUS_67(7 DOWNTO 0),
- RESET => s_LOGISIM_NET_19);
+ DATA_WR => s_LOGISIM_BUS_18(7 DOWNTO 0),
+ EN_WR => s_LOGISIM_NET_5,
+ OUT_A => s_LOGISIM_BUS_51(7 DOWNTO 0),
+ OUT_B => s_LOGISIM_BUS_9(7 DOWNTO 0),
+ RESET => s_LOGISIM_NET_20);
+
+ CIM_1 : CPU_INSTRUCTION_MEMORY
+ PORT MAP ( ADDR_INSTR => s_LOGISIM_BUS_19(6 DOWNTO 0),
+ INSTRUCTION => s_LOGISIM_BUS_52(15 DOWNTO 0));
END PlatformIndependent;
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd
similarity index 79%
rename from LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd
rename to LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd
index 981f56ad7bca057108b5d60b23fedd6f3ce6aa40..e89d8367ef4b0f84455aa26d9537e7e264ca332b 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_behavior.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_behavior.vhd
@@ -3,24 +3,20 @@
--== ==
--== ==
--== Project : CPU ==
---== Component : PERI_UART_RCV_16_BITS_9600 ==
+--== Component : PERI_UART_RCVE_9600 ==
--== ==
--==============================================================================
-ARCHITECTURE PlatformIndependent OF PERI_UART_RCV_16_BITS_9600 IS
+ARCHITECTURE PlatformIndependent OF PERI_UART_RCVE_9600 IS
-----------------------------------------------------------------------------
-- Here all used components are defined --
-----------------------------------------------------------------------------
- COMPONENT D_FLIPFLOP
- GENERIC ( ActiveLevel : INTEGER);
- PORT ( Clock : IN std_logic;
- D : IN std_logic;
- Preset : IN std_logic;
- Reset : IN std_logic;
- Tick : IN std_logic;
- Q : OUT std_logic;
- Q_bar : OUT std_logic);
+ COMPONENT AND_GATE
+ GENERIC ( BubblesMask : INTEGER);
+ PORT ( Input_1 : IN std_logic;
+ Input_2 : IN std_logic;
+ Result : OUT std_logic);
END COMPONENT;
COMPONENT NOT_GATE
@@ -28,6 +24,13 @@ ARCHITECTURE PlatformIndependent OF PERI_UART_RCV_16_BITS_9600 IS
Result : OUT std_logic);
END COMPONENT;
+ COMPONENT OR_GATE
+ GENERIC ( BubblesMask : INTEGER);
+ PORT ( Input_1 : IN std_logic;
+ Input_2 : IN std_logic;
+ Result : OUT std_logic);
+ END COMPONENT;
+
COMPONENT Multiplexer_2
PORT ( Enable : IN std_logic;
MuxIn_0 : IN std_logic;
@@ -36,6 +39,27 @@ ARCHITECTURE PlatformIndependent OF PERI_UART_RCV_16_BITS_9600 IS
MuxOut : OUT std_logic);
END COMPONENT;
+ COMPONENT Comparator
+ GENERIC ( TwosComplement : INTEGER;
+ NrOfBits : INTEGER);
+ PORT ( DataA : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
+ DataB : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
+ A_EQ_B : OUT std_logic;
+ A_GT_B : OUT std_logic;
+ A_LT_B : OUT std_logic);
+ END COMPONENT;
+
+ COMPONENT D_FLIPFLOP
+ GENERIC ( ActiveLevel : INTEGER);
+ PORT ( Clock : IN std_logic;
+ D : IN std_logic;
+ Preset : IN std_logic;
+ Reset : IN std_logic;
+ Tick : IN std_logic;
+ Q : OUT std_logic;
+ Q_bar : OUT std_logic);
+ END COMPONENT;
+
COMPONENT LogisimCounter
GENERIC ( mode : INTEGER;
ClkEdge : INTEGER;
@@ -52,30 +76,6 @@ ARCHITECTURE PlatformIndependent OF PERI_UART_RCV_16_BITS_9600 IS
CountValue : OUT std_logic_vector( (width-1) DOWNTO 0 ));
END COMPONENT;
- COMPONENT Comparator
- GENERIC ( TwosComplement : INTEGER;
- NrOfBits : INTEGER);
- PORT ( DataA : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
- DataB : IN std_logic_vector( (NrOfBits-1) DOWNTO 0 );
- A_EQ_B : OUT std_logic;
- A_GT_B : OUT std_logic;
- A_LT_B : OUT std_logic);
- END COMPONENT;
-
- COMPONENT AND_GATE
- GENERIC ( BubblesMask : INTEGER);
- PORT ( Input_1 : IN std_logic;
- Input_2 : IN std_logic;
- Result : OUT std_logic);
- END COMPONENT;
-
- COMPONENT OR_GATE
- GENERIC ( BubblesMask : INTEGER);
- PORT ( Input_1 : IN std_logic;
- Input_2 : IN std_logic;
- Result : OUT std_logic);
- END COMPONENT;
-
COMPONENT Shift_Register
GENERIC ( NrOfParBits : INTEGER;
NrOfStages : INTEGER;
@@ -96,30 +96,30 @@ ARCHITECTURE PlatformIndependent OF PERI_UART_RCV_16_BITS_9600 IS
-----------------------------------------------------------------------------
-- Here all used signals are defined --
-----------------------------------------------------------------------------
- SIGNAL s_LOGISIM_BUS_11 : std_logic_vector( 15 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_14 : std_logic_vector( 4 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_16 : std_logic_vector( 4 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_30 : std_logic_vector( 4 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_31 : std_logic_vector( 15 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_32 : std_logic_vector( 15 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_6 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_16 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_17 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_27 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_29 : std_logic_vector( 15 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_30 : std_logic_vector( 15 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_32 : std_logic_vector( 3 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_8 : std_logic_vector( 15 DOWNTO 0 );
SIGNAL s_LOGISIM_NET_0 : std_logic;
SIGNAL s_LOGISIM_NET_1 : std_logic;
SIGNAL s_LOGISIM_NET_10 : std_logic;
+ SIGNAL s_LOGISIM_NET_14 : std_logic;
SIGNAL s_LOGISIM_NET_15 : std_logic;
SIGNAL s_LOGISIM_NET_18 : std_logic;
- SIGNAL s_LOGISIM_NET_2 : std_logic;
+ SIGNAL s_LOGISIM_NET_19 : std_logic;
SIGNAL s_LOGISIM_NET_20 : std_logic;
SIGNAL s_LOGISIM_NET_21 : std_logic;
SIGNAL s_LOGISIM_NET_22 : std_logic;
SIGNAL s_LOGISIM_NET_23 : std_logic;
SIGNAL s_LOGISIM_NET_24 : std_logic;
- SIGNAL s_LOGISIM_NET_25 : std_logic;
- SIGNAL s_LOGISIM_NET_27 : std_logic;
SIGNAL s_LOGISIM_NET_28 : std_logic;
- SIGNAL s_LOGISIM_NET_29 : std_logic;
SIGNAL s_LOGISIM_NET_3 : std_logic;
- SIGNAL s_LOGISIM_NET_8 : std_logic;
+ SIGNAL s_LOGISIM_NET_31 : std_logic;
+ SIGNAL s_LOGISIM_NET_5 : std_logic;
+ SIGNAL s_LOGISIM_NET_7 : std_logic;
SIGNAL s_LOGISIM_NET_9 : std_logic;
BEGIN
@@ -127,153 +127,131 @@ BEGIN
-----------------------------------------------------------------------------
-- Here all input connections are defined --
-----------------------------------------------------------------------------
- s_LOGISIM_NET_3 <= CLK;
+ s_LOGISIM_NET_14 <= CLK;
+ s_LOGISIM_NET_3 <= RESET;
s_LOGISIM_NET_1 <= RX;
- s_LOGISIM_NET_8 <= RESET;
-----------------------------------------------------------------------------
-- Here all output connections are defined --
-----------------------------------------------------------------------------
- DONE <= s_LOGISIM_NET_28;
- DATA <= s_LOGISIM_BUS_6(7 DOWNTO 0);
+ DATA <= s_LOGISIM_BUS_27(7 DOWNTO 0);
+ DONE <= s_LOGISIM_NET_20;
-----------------------------------------------------------------------------
-- Here all in-lined components are defined --
-----------------------------------------------------------------------------
- s_LOGISIM_NET_25 <= '0';
-
- s_LOGISIM_BUS_32(15 DOWNTO 0) <= std_logic_vector(to_unsigned(0,16));
+ s_LOGISIM_BUS_17(3 DOWNTO 0) <= std_logic_vector(to_unsigned(0,4));
s_LOGISIM_NET_24 <= '1';
- s_LOGISIM_BUS_14(4 DOWNTO 0) <= std_logic_vector(to_unsigned(0,5));
+ s_LOGISIM_BUS_30(15 DOWNTO 0) <= std_logic_vector(to_unsigned(0,16));
- s_LOGISIM_BUS_30(4 DOWNTO 0) <= std_logic_vector(to_unsigned(0,5));
+ s_LOGISIM_NET_9 <= '0';
- s_LOGISIM_BUS_31(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5205,16));
+ s_LOGISIM_BUS_29(15 DOWNTO 0) <= std_logic_vector(to_unsigned(5205,16));
s_LOGISIM_NET_18 <= '1';
+ s_LOGISIM_BUS_32(3 DOWNTO 0) <= std_logic_vector(to_unsigned(0,4));
+
-----------------------------------------------------------------------------
-- Here all normal components are defined --
-----------------------------------------------------------------------------
- FF_LATCH_1 : D_FLIPFLOP
- GENERIC MAP ( ActiveLevel => 1)
- PORT MAP ( Clock => s_LOGISIM_NET_3,
- D => s_LOGISIM_NET_29,
- Preset => '0',
- Q => s_LOGISIM_NET_2,
- Q_bar => OPEN,
- Reset => s_LOGISIM_NET_8,
- Tick => '1');
+ GATE_1 : AND_GATE
+ GENERIC MAP ( BubblesMask => 0)
+ PORT MAP ( Input_1 => s_LOGISIM_NET_7,
+ Input_2 => s_LOGISIM_NET_28,
+ Result => s_LOGISIM_NET_19);
- GATE_1 : NOT_GATE
- PORT MAP ( Input_1 => s_LOGISIM_NET_20,
+ GATE_2 : AND_GATE
+ GENERIC MAP ( BubblesMask => 0)
+ PORT MAP ( Input_1 => s_LOGISIM_NET_0,
+ Input_2 => s_LOGISIM_NET_23,
+ Result => s_LOGISIM_NET_21);
+
+ GATE_3 : NOT_GATE
+ PORT MAP ( Input_1 => s_LOGISIM_NET_19,
Result => s_LOGISIM_NET_15);
- GATE_2 : NOT_GATE
+ GATE_4 : NOT_GATE
PORT MAP ( Input_1 => s_LOGISIM_NET_1,
- Result => s_LOGISIM_NET_23);
+ Result => s_LOGISIM_NET_22);
+
+ GATE_5 : OR_GATE
+ GENERIC MAP ( BubblesMask => 0)
+ PORT MAP ( Input_1 => s_LOGISIM_NET_10,
+ Input_2 => s_LOGISIM_NET_21,
+ Result => s_LOGISIM_NET_7);
MUX_1 : Multiplexer_2
PORT MAP ( Enable => '1',
- MuxIn_0 => s_LOGISIM_NET_23,
+ MuxIn_0 => s_LOGISIM_NET_22,
MuxIn_1 => s_LOGISIM_NET_15,
- MuxOut => s_LOGISIM_NET_29,
- Sel => s_LOGISIM_NET_2);
-
- COUNTER_1 : LogisimCounter
- GENERIC MAP ( ClkEdge => 1,
- max_val => 17,
- mode => 0,
- width => 5)
- PORT MAP ( ClockEnable => '1',
- CompareOut => s_LOGISIM_NET_27,
- CountValue => s_LOGISIM_BUS_16(4 DOWNTO 0),
- Enable => s_LOGISIM_NET_9,
- GlobalClock => s_LOGISIM_NET_3,
- LoadData => s_LOGISIM_BUS_30(4 DOWNTO 0),
- Up_n_Down => s_LOGISIM_NET_18,
- clear => s_LOGISIM_NET_8,
- load => s_LOGISIM_NET_20);
+ MuxOut => s_LOGISIM_NET_31,
+ Sel => s_LOGISIM_NET_5);
Comparator_1 : Comparator
- GENERIC MAP ( NrOfBits => 16,
+ GENERIC MAP ( NrOfBits => 4,
TwosComplement => 1)
- PORT MAP ( A_EQ_B => s_LOGISIM_NET_22,
+ PORT MAP ( A_EQ_B => s_LOGISIM_NET_0,
A_GT_B => OPEN,
A_LT_B => OPEN,
- DataA => s_LOGISIM_BUS_11(15 DOWNTO 0),
- DataB => s_LOGISIM_BUS_31(15 DOWNTO 0));
-
- GATE_3 : AND_GATE
- GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_9,
- Input_2 => s_LOGISIM_NET_27,
- Result => s_LOGISIM_NET_20);
+ DataA => s_LOGISIM_BUS_16(3 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_17(3 DOWNTO 0));
Comparator_2 : Comparator
- GENERIC MAP ( NrOfBits => 5,
+ GENERIC MAP ( NrOfBits => 16,
TwosComplement => 1)
- PORT MAP ( A_EQ_B => s_LOGISIM_NET_0,
+ PORT MAP ( A_EQ_B => s_LOGISIM_NET_23,
A_GT_B => OPEN,
A_LT_B => OPEN,
- DataA => s_LOGISIM_BUS_16(4 DOWNTO 0),
- DataB => s_LOGISIM_BUS_14(4 DOWNTO 0));
+ DataA => s_LOGISIM_BUS_8(15 DOWNTO 0),
+ DataB => s_LOGISIM_BUS_29(15 DOWNTO 0));
- GATE_4 : OR_GATE
- GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_10,
- Input_2 => s_LOGISIM_NET_21,
- Result => s_LOGISIM_NET_9);
-
- GATE_5 : AND_GATE
- GENERIC MAP ( BubblesMask => 0)
- PORT MAP ( Input_1 => s_LOGISIM_NET_0,
- Input_2 => s_LOGISIM_NET_22,
- Result => s_LOGISIM_NET_21);
+ FF_LATCH_1 : D_FLIPFLOP
+ GENERIC MAP ( ActiveLevel => 1)
+ PORT MAP ( Clock => s_LOGISIM_NET_14,
+ D => s_LOGISIM_NET_19,
+ Preset => '0',
+ Q => s_LOGISIM_NET_20,
+ Q_bar => OPEN,
+ Reset => '0',
+ Tick => '1');
- COUNTER_2 : LogisimCounter
+ COUNTER_1 : LogisimCounter
GENERIC MAP ( ClkEdge => 1,
max_val => 10410,
mode => 0,
width => 16)
PORT MAP ( ClockEnable => '1',
CompareOut => s_LOGISIM_NET_10,
- CountValue => s_LOGISIM_BUS_11(15 DOWNTO 0),
- Enable => s_LOGISIM_NET_2,
- GlobalClock => s_LOGISIM_NET_3,
- LoadData => s_LOGISIM_BUS_32(15 DOWNTO 0),
+ CountValue => s_LOGISIM_BUS_8(15 DOWNTO 0),
+ Enable => s_LOGISIM_NET_5,
+ GlobalClock => s_LOGISIM_NET_14,
+ LoadData => s_LOGISIM_BUS_30(15 DOWNTO 0),
Up_n_Down => s_LOGISIM_NET_24,
- clear => s_LOGISIM_NET_8,
+ clear => s_LOGISIM_NET_3,
load => s_LOGISIM_NET_21);
FF_LATCH_2 : D_FLIPFLOP
GENERIC MAP ( ActiveLevel => 1)
- PORT MAP ( Clock => s_LOGISIM_NET_3,
- D => s_LOGISIM_NET_20,
+ PORT MAP ( Clock => s_LOGISIM_NET_14,
+ D => s_LOGISIM_NET_31,
Preset => '0',
- Q => s_LOGISIM_NET_28,
+ Q => s_LOGISIM_NET_5,
Q_bar => OPEN,
- Reset => '0',
+ Reset => s_LOGISIM_NET_3,
Tick => '1');
SHIFTER_1 : Shift_Register
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 1,
- NrOfParBits => 17,
- NrOfStages => 17)
- PORT MAP ( Clock => s_LOGISIM_NET_3,
+ NrOfParBits => 9,
+ NrOfStages => 9)
+ PORT MAP ( Clock => s_LOGISIM_NET_14,
D(0) => '0',
D(1) => '0',
- D(10) => '0',
- D(11) => '0',
- D(12) => '0',
- D(13) => '0',
- D(14) => '0',
- D(15) => '0',
- D(16) => '0',
D(2) => '0',
D(3) => '0',
D(4) => '0',
@@ -281,30 +259,36 @@ BEGIN
D(6) => '0',
D(7) => '0',
D(8) => '0',
- D(9) => '0',
- ParLoad => s_LOGISIM_NET_25,
+ ParLoad => s_LOGISIM_NET_9,
Q(0) => OPEN,
- Q(1) => OPEN,
- Q(10) => s_LOGISIM_BUS_6(6),
- Q(11) => s_LOGISIM_BUS_6(5),
- Q(12) => s_LOGISIM_BUS_6(4),
- Q(13) => s_LOGISIM_BUS_6(3),
- Q(14) => s_LOGISIM_BUS_6(2),
- Q(15) => s_LOGISIM_BUS_6(1),
- Q(16) => OPEN,
- Q(2) => OPEN,
- Q(3) => OPEN,
- Q(4) => OPEN,
- Q(5) => OPEN,
- Q(6) => OPEN,
- Q(7) => OPEN,
+ Q(1) => s_LOGISIM_BUS_27(7),
+ Q(2) => s_LOGISIM_BUS_27(6),
+ Q(3) => s_LOGISIM_BUS_27(5),
+ Q(4) => s_LOGISIM_BUS_27(4),
+ Q(5) => s_LOGISIM_BUS_27(3),
+ Q(6) => s_LOGISIM_BUS_27(2),
+ Q(7) => s_LOGISIM_BUS_27(1),
Q(8) => OPEN,
- Q(9) => s_LOGISIM_BUS_6(7),
- Reset => s_LOGISIM_NET_8,
- ShiftEnable => s_LOGISIM_NET_9,
+ Reset => s_LOGISIM_NET_3,
+ ShiftEnable => s_LOGISIM_NET_7,
ShiftIn(0) => s_LOGISIM_NET_1,
- ShiftOut(0) => s_LOGISIM_BUS_6(0),
+ ShiftOut(0) => s_LOGISIM_BUS_27(0),
Tick => '1');
+ COUNTER_2 : LogisimCounter
+ GENERIC MAP ( ClkEdge => 1,
+ max_val => 9,
+ mode => 0,
+ width => 4)
+ PORT MAP ( ClockEnable => '1',
+ CompareOut => s_LOGISIM_NET_28,
+ CountValue => s_LOGISIM_BUS_16(3 DOWNTO 0),
+ Enable => s_LOGISIM_NET_7,
+ GlobalClock => s_LOGISIM_NET_14,
+ LoadData => s_LOGISIM_BUS_32(3 DOWNTO 0),
+ Up_n_Down => s_LOGISIM_NET_18,
+ clear => s_LOGISIM_NET_3,
+ load => s_LOGISIM_NET_19);
+
END PlatformIndependent;
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd
similarity index 87%
rename from LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd
rename to LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd
index a5f76239d0efddf24de58093182cd853fc3041a8..2f8a4bbfeb0b9399721aa0408f9fab9bc239c99e 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCV_16_BITS_9600_entity.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/PERI_UART_RCVE_9600_entity.vhd
@@ -3,7 +3,7 @@
--== ==
--== ==
--== Project : CPU ==
---== Component : PERI_UART_RCV_16_BITS_9600 ==
+--== Component : PERI_UART_RCVE_9600 ==
--== ==
--==============================================================================
@@ -12,11 +12,11 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-ENTITY PERI_UART_RCV_16_BITS_9600 IS
+ENTITY PERI_UART_RCVE_9600 IS
PORT ( CLK : IN std_logic;
RESET : IN std_logic;
RX : IN std_logic;
DATA : OUT std_logic_vector( 7 DOWNTO 0 );
DONE : OUT std_logic);
-END PERI_UART_RCV_16_BITS_9600;
+END PERI_UART_RCVE_9600;
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd
index 942f18d3a124149d9fb2009135f323ef7ec295b5..7a43c94bb0d14db45fcae3937288e09db66e78cc 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_behavior.vhd
@@ -31,17 +31,11 @@ ARCHITECTURE PlatformIndependent OF TOP IS
RESET : IN std_logic;
UART_BLUETOOTH : IN std_logic_vector( 7 DOWNTO 0 );
DATA_OUT : OUT std_logic_vector( 7 DOWNTO 0 );
+ UART_OUT : OUT std_logic_vector( 7 DOWNTO 0 );
WHEEL_LEFT_PWM : OUT std_logic_vector( 7 DOWNTO 0 );
WHEEL_RIGHT_PWM : OUT std_logic_vector( 7 DOWNTO 0 ));
END COMPONENT;
- COMPONENT PERI_SIGNED_PWM
- PORT ( CLK : IN std_logic;
- SPEED_IN : IN std_logic_vector( 7 DOWNTO 0 );
- DIR_OUT : OUT std_logic;
- PWM_OUT : OUT std_logic);
- END COMPONENT;
-
COMPONENT CPU
PORT ( CLK : IN std_logic;
RESET : IN std_logic;
@@ -51,7 +45,14 @@ ARCHITECTURE PlatformIndependent OF TOP IS
RAM_EN_WR : OUT std_logic);
END COMPONENT;
- COMPONENT PERI_UART_RCV_16_BITS_9600
+ COMPONENT PERI_SIGNED_PWM
+ PORT ( CLK : IN std_logic;
+ SPEED_IN : IN std_logic_vector( 7 DOWNTO 0 );
+ DIR_OUT : OUT std_logic;
+ PWM_OUT : OUT std_logic);
+ END COMPONENT;
+
+ COMPONENT PERI_UART_RCVE_9600
PORT ( CLK : IN std_logic;
RESET : IN std_logic;
RX : IN std_logic;
@@ -63,48 +64,58 @@ ARCHITECTURE PlatformIndependent OF TOP IS
-----------------------------------------------------------------------------
-- Here all used signals are defined --
-----------------------------------------------------------------------------
- SIGNAL s_LOGISIM_BUS_0 : std_logic_vector( 4 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_10 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_11 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_14 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_0 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_1 : std_logic_vector( 7 DOWNTO 0 );
SIGNAL s_LOGISIM_BUS_2 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_7 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_BUS_8 : std_logic_vector( 7 DOWNTO 0 );
- SIGNAL s_LOGISIM_NET_1 : std_logic;
- SIGNAL s_LOGISIM_NET_12 : std_logic;
- SIGNAL s_LOGISIM_NET_13 : std_logic;
+ SIGNAL s_LOGISIM_BUS_22 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_3 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_4 : std_logic_vector( 7 DOWNTO 0 );
+ SIGNAL s_LOGISIM_BUS_5 : std_logic_vector( 4 DOWNTO 0 );
+ SIGNAL s_LOGISIM_NET_14 : std_logic;
SIGNAL s_LOGISIM_NET_15 : std_logic;
- SIGNAL s_LOGISIM_NET_3 : std_logic;
- SIGNAL s_LOGISIM_NET_4 : std_logic;
- SIGNAL s_LOGISIM_NET_5 : std_logic;
- SIGNAL s_LOGISIM_NET_6 : std_logic;
- SIGNAL s_LOGISIM_NET_9 : std_logic;
+ SIGNAL s_LOGISIM_NET_16 : std_logic;
+ SIGNAL s_LOGISIM_NET_17 : std_logic;
+ SIGNAL s_LOGISIM_NET_18 : std_logic;
+ SIGNAL s_LOGISIM_NET_19 : std_logic;
+ SIGNAL s_LOGISIM_NET_20 : std_logic;
+ SIGNAL s_LOGISIM_NET_21 : std_logic;
+ SIGNAL s_LOGISIM_NET_23 : std_logic;
BEGIN
-----------------------------------------------------------------------------
-- Here all input connections are defined --
-----------------------------------------------------------------------------
- s_LOGISIM_NET_12 <= CLK;
- s_LOGISIM_NET_13 <= RESET;
- s_LOGISIM_NET_9 <= RX;
+ s_LOGISIM_NET_20 <= CLK;
+ s_LOGISIM_NET_19 <= RX;
+ s_LOGISIM_NET_21 <= RESET;
-----------------------------------------------------------------------------
-- Here all output connections are defined --
-----------------------------------------------------------------------------
- WHEEL_RIGHT_PWM <= s_LOGISIM_NET_3;
- DIR_WHEEL_RIGHT <= s_LOGISIM_NET_4;
- WHEEL_LEFT_PWM <= s_LOGISIM_NET_5;
- DIR_WHEEL_LEFT <= s_LOGISIM_NET_6;
- LED_0 <= s_LOGISIM_BUS_7(0);
- LED_1 <= s_LOGISIM_BUS_7(1);
- LED_2 <= s_LOGISIM_BUS_7(2);
- LED_3 <= s_LOGISIM_BUS_7(3);
- LED_4 <= s_LOGISIM_BUS_7(4);
- LED_5 <= s_LOGISIM_BUS_7(5);
- LED_6 <= s_LOGISIM_BUS_7(6);
- LED_7 <= s_LOGISIM_BUS_7(7);
- UART_RX_PC <= s_LOGISIM_NET_9;
+ UART_RX_PC <= s_LOGISIM_NET_19;
+ LED_RIGHT <= s_LOGISIM_NET_14;
+ DIR_WHEEL_LEFT <= s_LOGISIM_NET_18;
+ WHEEL_LEFT_PWM <= s_LOGISIM_NET_15;
+ WHEEL_RIGHT_PWM <= s_LOGISIM_NET_14;
+ LED_LEFT <= s_LOGISIM_NET_15;
+ DIR_WHEEL_RIGHT <= s_LOGISIM_NET_17;
+ LED_1 <= s_LOGISIM_BUS_0(1);
+ LED_5 <= s_LOGISIM_BUS_0(5);
+ LED_0 <= s_LOGISIM_BUS_0(0);
+ LED_4 <= s_LOGISIM_BUS_0(4);
+ LED_6 <= s_LOGISIM_BUS_0(6);
+ LED_3 <= s_LOGISIM_BUS_0(3);
+ LED_2 <= s_LOGISIM_BUS_0(2);
+ LED_7 <= s_LOGISIM_BUS_0(7);
+ PWM4 <= s_LOGISIM_BUS_2(4);
+ PWM0 <= s_LOGISIM_BUS_2(0);
+ PWM6 <= s_LOGISIM_BUS_2(6);
+ PWM3 <= s_LOGISIM_BUS_2(3);
+ PWM7 <= s_LOGISIM_BUS_2(7);
+ PWM5 <= s_LOGISIM_BUS_2(5);
+ PWM1 <= s_LOGISIM_BUS_2(1);
+ PWM2 <= s_LOGISIM_BUS_2(2);
-----------------------------------------------------------------------------
-- Here all normal components are defined --
@@ -112,10 +123,10 @@ BEGIN
REGISTER_FILE_1 : REGISTER_FLIP_FLOP
GENERIC MAP ( ActiveLevel => 1,
NrOfBits => 8)
- PORT MAP ( Clock => s_LOGISIM_NET_12,
- ClockEnable => s_LOGISIM_NET_15,
- D => s_LOGISIM_BUS_14(7 DOWNTO 0),
- Q => s_LOGISIM_BUS_7(7 DOWNTO 0),
+ PORT MAP ( Clock => s_LOGISIM_NET_20,
+ ClockEnable => s_LOGISIM_NET_23,
+ D => s_LOGISIM_BUS_22(7 DOWNTO 0),
+ Q => s_LOGISIM_BUS_0(7 DOWNTO 0),
Reset => '0',
Tick => '1');
@@ -124,42 +135,43 @@ BEGIN
-- Here all sub-circuits are defined --
-----------------------------------------------------------------------------
CPU_RAM : CPU_RAM24
- PORT MAP ( ADDR => s_LOGISIM_BUS_0(4 DOWNTO 0),
- CLK => s_LOGISIM_NET_12,
- DATA_OUT => s_LOGISIM_BUS_8(7 DOWNTO 0),
- DATA_WR => s_LOGISIM_BUS_2(7 DOWNTO 0),
- EN_WR => s_LOGISIM_NET_1,
- RESET => s_LOGISIM_NET_13,
- UART_BLUETOOTH => s_LOGISIM_BUS_7(7 DOWNTO 0),
- WHEEL_LEFT_PWM => s_LOGISIM_BUS_11(7 DOWNTO 0),
- WHEEL_RIGHT_PWM => s_LOGISIM_BUS_10(7 DOWNTO 0));
+ PORT MAP ( ADDR => s_LOGISIM_BUS_5(4 DOWNTO 0),
+ CLK => s_LOGISIM_NET_20,
+ DATA_OUT => s_LOGISIM_BUS_3(7 DOWNTO 0),
+ DATA_WR => s_LOGISIM_BUS_1(7 DOWNTO 0),
+ EN_WR => s_LOGISIM_NET_16,
+ RESET => s_LOGISIM_NET_21,
+ UART_BLUETOOTH => s_LOGISIM_BUS_0(7 DOWNTO 0),
+ UART_OUT => OPEN,
+ WHEEL_LEFT_PWM => s_LOGISIM_BUS_4(7 DOWNTO 0),
+ WHEEL_RIGHT_PWM => s_LOGISIM_BUS_2(7 DOWNTO 0));
- peri1 : PERI_SIGNED_PWM
- PORT MAP ( CLK => s_LOGISIM_NET_12,
- DIR_OUT => s_LOGISIM_NET_4,
- PWM_OUT => s_LOGISIM_NET_3,
- SPEED_IN => s_LOGISIM_BUS_10(7 DOWNTO 0));
+ CPU_1 : CPU
+ PORT MAP ( CLK => s_LOGISIM_NET_20,
+ RAM_ADDR => s_LOGISIM_BUS_5(4 DOWNTO 0),
+ RAM_DATA_WR => s_LOGISIM_BUS_1(7 DOWNTO 0),
+ RAM_EN_WR => s_LOGISIM_NET_16,
+ RESET => s_LOGISIM_NET_21,
+ WB_RAM => s_LOGISIM_BUS_3(7 DOWNTO 0));
peri2 : PERI_SIGNED_PWM
- PORT MAP ( CLK => s_LOGISIM_NET_12,
- DIR_OUT => s_LOGISIM_NET_6,
- PWM_OUT => s_LOGISIM_NET_5,
- SPEED_IN => s_LOGISIM_BUS_11(7 DOWNTO 0));
+ PORT MAP ( CLK => s_LOGISIM_NET_20,
+ DIR_OUT => s_LOGISIM_NET_18,
+ PWM_OUT => s_LOGISIM_NET_15,
+ SPEED_IN => s_LOGISIM_BUS_4(7 DOWNTO 0));
- CPU_1 : CPU
- PORT MAP ( CLK => s_LOGISIM_NET_12,
- RAM_ADDR => s_LOGISIM_BUS_0(4 DOWNTO 0),
- RAM_DATA_WR => s_LOGISIM_BUS_2(7 DOWNTO 0),
- RAM_EN_WR => s_LOGISIM_NET_1,
- RESET => s_LOGISIM_NET_13,
- WB_RAM => s_LOGISIM_BUS_8(7 DOWNTO 0));
-
- peri_uart : PERI_UART_RCV_16_BITS_9600
- PORT MAP ( CLK => s_LOGISIM_NET_12,
- DATA => s_LOGISIM_BUS_14(7 DOWNTO 0),
- DONE => s_LOGISIM_NET_15,
- RESET => s_LOGISIM_NET_13,
- RX => s_LOGISIM_NET_9);
+ peri1 : PERI_SIGNED_PWM
+ PORT MAP ( CLK => s_LOGISIM_NET_20,
+ DIR_OUT => s_LOGISIM_NET_17,
+ PWM_OUT => s_LOGISIM_NET_14,
+ SPEED_IN => s_LOGISIM_BUS_2(7 DOWNTO 0));
+
+ UART1 : PERI_UART_RCVE_9600
+ PORT MAP ( CLK => s_LOGISIM_NET_20,
+ DATA => s_LOGISIM_BUS_22(7 DOWNTO 0),
+ DONE => s_LOGISIM_NET_23,
+ RESET => s_LOGISIM_NET_21,
+ RX => s_LOGISIM_NET_19);
END PlatformIndependent;
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd
index bf5355f0fc7db5e320dc8d526ccee123986aa608..0cb0db9675881b5bebb0bf16f7ab1b6907a0ede3 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/circuit/TOP_entity.vhd
@@ -26,6 +26,16 @@ ENTITY TOP IS
LED_5 : OUT std_logic;
LED_6 : OUT std_logic;
LED_7 : OUT std_logic;
+ LED_LEFT : OUT std_logic;
+ LED_RIGHT : OUT std_logic;
+ PWM0 : OUT std_logic;
+ PWM1 : OUT std_logic;
+ PWM2 : OUT std_logic;
+ PWM3 : OUT std_logic;
+ PWM4 : OUT std_logic;
+ PWM5 : OUT std_logic;
+ PWM6 : OUT std_logic;
+ PWM7 : OUT std_logic;
UART_RX_PC : OUT std_logic;
WHEEL_LEFT_PWM : OUT std_logic;
WHEEL_RIGHT_PWM : OUT std_logic);
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fc76d3415b3e79f0f57d1a3a5658357c2a2d9dff
--- /dev/null
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_behavior.vhd
@@ -0,0 +1,43 @@
+--==============================================================================
+--== Logisim goes FPGA automatic generated VHDL code ==
+--== ==
+--== ==
+--== Project : CPU ==
+--== Component : OR_GATE_3_INPUTS ==
+--== ==
+--==============================================================================
+
+ARCHITECTURE PlatformIndependent OF OR_GATE_3_INPUTS IS
+
+ -----------------------------------------------------------------------------
+ -- Here all used signals are defined --
+ -----------------------------------------------------------------------------
+ SIGNAL s_real_input_1 : std_logic;
+ SIGNAL s_real_input_2 : std_logic;
+ SIGNAL s_real_input_3 : std_logic;
+ SIGNAL s_signal_invert_mask : std_logic_vector( 2 DOWNTO 0 );
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- Here the bubbles are processed --
+ -----------------------------------------------------------------------------
+ s_signal_invert_mask <= std_logic_vector(to_unsigned(BubblesMask,3));
+ s_real_input_1 <= NOT( Input_1 )
+ WHEN s_signal_invert_mask(0) = '1' ELSE
+ Input_1;
+ s_real_input_2 <= NOT( Input_2 )
+ WHEN s_signal_invert_mask(1) = '1' ELSE
+ Input_2;
+ s_real_input_3 <= NOT( Input_3 )
+ WHEN s_signal_invert_mask(2) = '1' ELSE
+ Input_3;
+
+ -----------------------------------------------------------------------------
+ -- Here the functionality is defined --
+ -----------------------------------------------------------------------------
+ Result <= s_real_input_1 OR
+ s_real_input_2 OR
+ s_real_input_3;
+
+END PlatformIndependent;
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1f4e3949043532f7415ff72044f73e70c9750799
--- /dev/null
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/gates/OR_GATE_3_INPUTS_entity.vhd
@@ -0,0 +1,22 @@
+--==============================================================================
+--== Logisim goes FPGA automatic generated VHDL code ==
+--== ==
+--== ==
+--== Project : CPU ==
+--== Component : OR_GATE_3_INPUTS ==
+--== ==
+--==============================================================================
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY OR_GATE_3_INPUTS IS
+ GENERIC ( BubblesMask : INTEGER);
+ PORT ( Input_1 : IN std_logic;
+ Input_2 : IN std_logic;
+ Input_3 : IN std_logic;
+ Result : OUT std_logic);
+END OR_GATE_3_INPUTS;
+
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd
index cfa02ef8e43abe6d7ceb6faeb968cdc246180001..087f0aec4949f782e74c1585d9c82eebe3b686f6 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_behavior.vhd
@@ -26,6 +26,16 @@ ARCHITECTURE PlatformIndependent OF LogisimToplevelShell IS
LED_5 : OUT std_logic;
LED_6 : OUT std_logic;
LED_7 : OUT std_logic;
+ LED_LEFT : OUT std_logic;
+ LED_RIGHT : OUT std_logic;
+ PWM0 : OUT std_logic;
+ PWM1 : OUT std_logic;
+ PWM2 : OUT std_logic;
+ PWM3 : OUT std_logic;
+ PWM4 : OUT std_logic;
+ PWM5 : OUT std_logic;
+ PWM6 : OUT std_logic;
+ PWM7 : OUT std_logic;
UART_RX_PC : OUT std_logic;
WHEEL_LEFT_PWM : OUT std_logic;
WHEEL_RIGHT_PWM : OUT std_logic);
@@ -46,6 +56,16 @@ ARCHITECTURE PlatformIndependent OF LogisimToplevelShell IS
SIGNAL s_LED_5 : std_logic;
SIGNAL s_LED_6 : std_logic;
SIGNAL s_LED_7 : std_logic;
+ SIGNAL s_LED_LEFT : std_logic;
+ SIGNAL s_LED_RIGHT : std_logic;
+ SIGNAL s_PWM0 : std_logic;
+ SIGNAL s_PWM1 : std_logic;
+ SIGNAL s_PWM2 : std_logic;
+ SIGNAL s_PWM3 : std_logic;
+ SIGNAL s_PWM4 : std_logic;
+ SIGNAL s_PWM5 : std_logic;
+ SIGNAL s_PWM6 : std_logic;
+ SIGNAL s_PWM7 : std_logic;
SIGNAL s_RESET : std_logic;
SIGNAL s_RX : std_logic;
SIGNAL s_UART_RX_PC : std_logic;
@@ -56,21 +76,31 @@ BEGIN
-----------------------------------------------------------------------------
-- Here all signal adaptations are performed --
-----------------------------------------------------------------------------
+ FPGA_OUTPUT_PIN_0 <= s_PWM5;
+ FPGA_OUTPUT_PIN_1 <= s_PWM4;
+ FPGA_OUTPUT_PIN_2 <= NOT s_PWM7;
+ FPGA_OUTPUT_PIN_3 <= NOT s_PWM6;
+ FPGA_OUTPUT_PIN_4 <= s_WHEEL_RIGHT_PWM;
+ FPGA_OUTPUT_PIN_5 <= s_PWM1;
+ FPGA_OUTPUT_PIN_6 <= s_DIR_WHEEL_RIGHT;
+ FPGA_OUTPUT_PIN_7 <= s_PWM0;
+ FPGA_OUTPUT_PIN_8 <= s_UART_RX_PC;
+ FPGA_OUTPUT_PIN_9 <= s_PWM3;
+ FPGA_OUTPUT_PIN_10 <= s_PWM2;
s_RX <= FPGA_INPUT_PIN_0;
- FPGA_OUTPUT_PIN_0 <= s_LED_0;
- FPGA_OUTPUT_PIN_1 <= s_LED_1;
- FPGA_OUTPUT_PIN_2 <= s_DIR_WHEEL_LEFT;
- FPGA_OUTPUT_PIN_3 <= s_LED_4;
- FPGA_OUTPUT_PIN_4 <= s_LED_5;
- FPGA_OUTPUT_PIN_5 <= s_LED_2;
- FPGA_OUTPUT_PIN_6 <= s_WHEEL_RIGHT_PWM;
- FPGA_OUTPUT_PIN_7 <= s_LED_3;
- FPGA_OUTPUT_PIN_8 <= s_DIR_WHEEL_RIGHT;
+ FPGA_OUTPUT_PIN_11 <= s_LED_0;
+ FPGA_OUTPUT_PIN_12 <= s_LED_1;
+ FPGA_OUTPUT_PIN_13 <= s_DIR_WHEEL_LEFT;
+ FPGA_OUTPUT_PIN_14 <= s_LED_LEFT;
+ FPGA_OUTPUT_PIN_15 <= s_LED_4;
+ FPGA_OUTPUT_PIN_16 <= s_LED_5;
+ FPGA_OUTPUT_PIN_17 <= s_LED_2;
+ FPGA_OUTPUT_PIN_18 <= s_LED_3;
+ FPGA_OUTPUT_PIN_19 <= s_LED_RIGHT;
s_RESET <= FPGA_INPUT_PIN_1;
- FPGA_OUTPUT_PIN_9 <= s_LED_6;
- FPGA_OUTPUT_PIN_10 <= s_UART_RX_PC;
- FPGA_OUTPUT_PIN_11 <= s_LED_7;
- FPGA_OUTPUT_PIN_12 <= s_WHEEL_LEFT_PWM;
+ FPGA_OUTPUT_PIN_20 <= s_LED_6;
+ FPGA_OUTPUT_PIN_21 <= s_LED_7;
+ FPGA_OUTPUT_PIN_22 <= s_WHEEL_LEFT_PWM;
s_CLK <= FPGA_INPUT_PIN_2;
-----------------------------------------------------------------------------
-- Here all inlined adaptations are performed --
@@ -91,6 +121,16 @@ BEGIN
LED_5 => s_LED_5,
LED_6 => s_LED_6,
LED_7 => s_LED_7,
+ LED_LEFT => s_LED_LEFT,
+ LED_RIGHT => s_LED_RIGHT,
+ PWM0 => s_PWM0,
+ PWM1 => s_PWM1,
+ PWM2 => s_PWM2,
+ PWM3 => s_PWM3,
+ PWM4 => s_PWM4,
+ PWM5 => s_PWM5,
+ PWM6 => s_PWM6,
+ PWM7 => s_PWM7,
RESET => s_RESET,
RX => s_RX,
UART_RX_PC => s_UART_RX_PC,
diff --git a/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_entity.vhd b/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_entity.vhd
index ad01c8fd8578227bc98b3d109283369d84811065..040e876d68a922eb7da27d3b9716cfe495630b00 100644
--- a/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_entity.vhd
+++ b/LABO/FULL_ADDER/CPU/TOP/vhdl/toplevel/LogisimToplevelShell_entity.vhd
@@ -21,7 +21,17 @@ ENTITY LogisimToplevelShell IS
FPGA_OUTPUT_PIN_10 : OUT std_logic;
FPGA_OUTPUT_PIN_11 : OUT std_logic;
FPGA_OUTPUT_PIN_12 : OUT std_logic;
+ FPGA_OUTPUT_PIN_13 : OUT std_logic;
+ FPGA_OUTPUT_PIN_14 : OUT std_logic;
+ FPGA_OUTPUT_PIN_15 : OUT std_logic;
+ FPGA_OUTPUT_PIN_16 : OUT std_logic;
+ FPGA_OUTPUT_PIN_17 : OUT std_logic;
+ FPGA_OUTPUT_PIN_18 : OUT std_logic;
+ FPGA_OUTPUT_PIN_19 : OUT std_logic;
FPGA_OUTPUT_PIN_2 : OUT std_logic;
+ FPGA_OUTPUT_PIN_20 : OUT std_logic;
+ FPGA_OUTPUT_PIN_21 : OUT std_logic;
+ FPGA_OUTPUT_PIN_22 : OUT std_logic;
FPGA_OUTPUT_PIN_3 : OUT std_logic;
FPGA_OUTPUT_PIN_4 : OUT std_logic;
FPGA_OUTPUT_PIN_5 : OUT std_logic;
diff --git a/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc b/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc
index 2ff3b3ffb5f3f999590886e62742c3194d235962..7f5b4636eaa6b100d43592e3fa4f0f1bd7ae623f 100644
--- a/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc
+++ b/LABO/FULL_ADDER/CPU/TOP/xdc/vivadoConstraints.xdc
@@ -7,42 +7,72 @@ set_property PACKAGE_PIN G3 [get_ports {FPGA_INPUT_PIN_0}]
set_property PACKAGE_PIN U18 [get_ports {FPGA_INPUT_PIN_1}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_INPUT_PIN_1}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_INPUT_PIN_1}]
-set_property PACKAGE_PIN B16 [get_ports {FPGA_OUTPUT_PIN_2}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_2}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_2}]
-set_property PACKAGE_PIN U14 [get_ports {FPGA_OUTPUT_PIN_9}]
+set_property PACKAGE_PIN B16 [get_ports {FPGA_OUTPUT_PIN_13}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_13}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_13}]
+set_property PACKAGE_PIN U14 [get_ports {FPGA_OUTPUT_PIN_20}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_20}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_20}]
+set_property PACKAGE_PIN A16 [get_ports {FPGA_OUTPUT_PIN_22}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_22}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_22}]
+set_property PACKAGE_PIN A18 [get_ports {FPGA_OUTPUT_PIN_8}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_8}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_8}]
+set_property PACKAGE_PIN U16 [get_ports {FPGA_OUTPUT_PIN_11}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_11}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_11}]
+set_property PACKAGE_PIN U3 [get_ports {FPGA_OUTPUT_PIN_9}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_9}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_9}]
-set_property PACKAGE_PIN A16 [get_ports {FPGA_OUTPUT_PIN_12}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_12}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_12}]
-set_property PACKAGE_PIN U16 [get_ports {FPGA_OUTPUT_PIN_0}]
+set_property PACKAGE_PIN V19 [get_ports {FPGA_OUTPUT_PIN_18}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_18}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_18}]
+set_property PACKAGE_PIN N3 [get_ports {FPGA_OUTPUT_PIN_0}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_0}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_0}]
-set_property PACKAGE_PIN A18 [get_ports {FPGA_OUTPUT_PIN_10}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_10}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_10}]
-set_property PACKAGE_PIN V19 [get_ports {FPGA_OUTPUT_PIN_7}]
+set_property PACKAGE_PIN V13 [get_ports {FPGA_OUTPUT_PIN_7}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_7}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_7}]
-set_property PACKAGE_PIN W18 [get_ports {FPGA_OUTPUT_PIN_3}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_3}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_3}]
-set_property PACKAGE_PIN E19 [get_ports {FPGA_OUTPUT_PIN_1}]
+set_property PACKAGE_PIN L1 [get_ports {FPGA_OUTPUT_PIN_14}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_14}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_14}]
+set_property PACKAGE_PIN W18 [get_ports {FPGA_OUTPUT_PIN_15}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_15}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_15}]
+set_property PACKAGE_PIN W3 [get_ports {FPGA_OUTPUT_PIN_10}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_10}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_10}]
+set_property PACKAGE_PIN E19 [get_ports {FPGA_OUTPUT_PIN_12}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_12}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_12}]
+set_property PACKAGE_PIN P3 [get_ports {FPGA_OUTPUT_PIN_1}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_1}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_1}]
-set_property PACKAGE_PIN V14 [get_ports {FPGA_OUTPUT_PIN_11}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_11}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_11}]
-set_property PACKAGE_PIN U19 [get_ports {FPGA_OUTPUT_PIN_5}]
+set_property PACKAGE_PIN V3 [get_ports {FPGA_OUTPUT_PIN_5}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_5}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_5}]
-set_property PACKAGE_PIN B15 [get_ports {FPGA_OUTPUT_PIN_6}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_6}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_6}]
-set_property PACKAGE_PIN U15 [get_ports {FPGA_OUTPUT_PIN_4}]
+set_property PACKAGE_PIN U7 [get_ports {FPGA_OUTPUT_PIN_2}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_2}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_2}]
+set_property PACKAGE_PIN P1 [get_ports {FPGA_OUTPUT_PIN_19}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_19}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_19}]
+set_property PACKAGE_PIN V14 [get_ports {FPGA_OUTPUT_PIN_21}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_21}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_21}]
+set_property PACKAGE_PIN B15 [get_ports {FPGA_OUTPUT_PIN_4}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_4}]
set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_4}]
-set_property PACKAGE_PIN A14 [get_ports {FPGA_OUTPUT_PIN_8}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_8}]
- set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_8}]
+set_property PACKAGE_PIN U19 [get_ports {FPGA_OUTPUT_PIN_17}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_17}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_17}]
+set_property PACKAGE_PIN U15 [get_ports {FPGA_OUTPUT_PIN_16}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_16}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_16}]
+set_property PACKAGE_PIN V8 [get_ports {FPGA_OUTPUT_PIN_3}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_3}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_3}]
+set_property PACKAGE_PIN A14 [get_ports {FPGA_OUTPUT_PIN_6}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_6}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_OUTPUT_PIN_6}]