diff --git a/CPU/logi_compiler_sources.zip b/CPU/logi_compiler_sources.zip
new file mode 100644
index 0000000000000000000000000000000000000000..76b33af66dd4197ce4b4b479cc9671ea4def363d
Binary files /dev/null and b/CPU/logi_compiler_sources.zip differ
diff --git a/CPU/logi_compiler_sources/README.txt b/CPU/logi_compiler_sources/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..de1ffd4a8a29857626c412a1e967784e9cc42dbf
--- /dev/null
+++ b/CPU/logi_compiler_sources/README.txt
@@ -0,0 +1,9 @@
+Vous devez avoir python installé sur votre PC afin de pouvoir utiliser cet outil.
+
+Le fichier instruction_test.lsn contient des exemples pour le syntaxe des instructions.
+
+Le script logi_compiler.py vous permettra de générer un fichier .circ contenant une mémoire ROM avec l'exécutable pour votre processeur HepiaRISC.
+
+Pour le lancer:
+
+python logi_compiler.py instruction_test.lsn instruction_test.circ
diff --git a/CPU/logi_compiler_sources/circ_manager.py b/CPU/logi_compiler_sources/circ_manager.py
new file mode 100755
index 0000000000000000000000000000000000000000..867a40790faa93515599a0b4f1146c9930869726
--- /dev/null
+++ b/CPU/logi_compiler_sources/circ_manager.py
@@ -0,0 +1,67 @@
+#!/usr/bin/env python2
+# encoding: utf-8
+
+# Author: adrien.lescourt@hesge.ch
+# 04.2014, hepia
+
+from xml.dom import minidom
+import sys
+import os
+
+
+def resource_path(relative):
+ if hasattr(sys, "_MEIPASS"):
+ return os.path.join(sys._MEIPASS, relative)
+ return os.path.join(relative)
+
+
+class CircManager():
+
+ """
+ This class is used to append multiple 'constant' composant into a base .circ class
+ Used to add instructions into a simple instruction ROM designed by LSN student. The ROM is a
+ list of constant with a multiplexer
+ """
+ def __init__(self):
+ self.xmldoc = minidom.parse(resource_path('rom_base.circ'))
+ self.circuit = self.xmldoc.getElementsByTagName('circuit')[0]
+
+ def append_constant_from_binary_list(self, binary_list):
+ pos_X_left = 260
+ pos_X_right = 300
+ pos_Y = 140
+ step_Y = 10
+ count = 0
+ for elem in binary_list:
+ if count % 2 == 0:
+ self.__add_component(str((pos_X_left, pos_Y)), '0b' + elem)
+ else:
+ self.__add_component(str((pos_X_right, pos_Y)), '0b' + elem)
+ count += 1
+ pos_Y += step_Y
+ if count == 32:
+ pos_Y = 520
+ if count == 64:
+ pos_Y = 140
+ pos_X_left = 550
+ pos_X_right = 590
+ if count == 96:
+ pos_Y = 520
+
+ def get_XML(self):
+ return self.xmldoc.toprettyxml()
+
+ def __add_component(self, loc, val):
+ comp = self.xmldoc.createElement('comp')
+ comp.setAttribute("lib", '0')
+ comp.setAttribute("loc", loc)
+ comp.setAttribute("name", 'Constant')
+ sub_comp = self.xmldoc.createElement('a')
+ sub_comp.setAttribute('name', 'width')
+ sub_comp.setAttribute('val', '16')
+ comp.appendChild(sub_comp)
+ sub_comp = self.xmldoc.createElement('a')
+ sub_comp.setAttribute('name', 'value')
+ sub_comp.setAttribute('val', val)
+ comp.appendChild(sub_comp)
+ self.circuit.appendChild(comp)
diff --git a/CPU/logi_compiler_sources/instruction_test.lsn b/CPU/logi_compiler_sources/instruction_test.lsn
new file mode 100644
index 0000000000000000000000000000000000000000..a1903dd7b52b3e93f8df83d290c10db69bfbf87c
--- /dev/null
+++ b/CPU/logi_compiler_sources/instruction_test.lsn
@@ -0,0 +1,52 @@
+# Note: Ce fichier a comme but de donner des exemples pour la syntaxe des instructions.
+# Il n'est pas censé s'executer de façon cohérente
+
+# Constantes
+R0 = 10
+R1 = 0xAF
+R1 = 0x01
+R1 = 0b10
+R1 = 0b101011
+
+# Operations
+#r3 = r0 + r1
+#r3 = r1 - R0
+#r3 = R0 << 1
+#r3 = r3 >> 1
+#r3 = asr r1
+#r3 = r1 and r0
+#r3 = r1 or r0
+#r3 = not r3
+
+# labels afin d'indiquer la destination des instrcutions de saut
+
+loop:
+r1=r2+r3
+
+# Sauts
+bcz -1
+bcn 2
+bcc -3
+bcv 4
+bcc loop
+
+b -5
+b 3
+b loop
+
+bl [r7] 0x21
+bl [r7] 4
+bl [r7] fonction
+
+fonction:
+r0 = r0 + r0
+br [r7]
+
+# Lecture et écriture mémoire
+ld r0,0x20[r2]
+ld r3,0b1010[r4]
+ld r3,3[r4]
+
+st r0,0x2A[r2]
+st r1,19[r3]
+
diff --git a/CPU/logi_compiler_sources/logi_compiler.py b/CPU/logi_compiler_sources/logi_compiler.py
new file mode 100755
index 0000000000000000000000000000000000000000..257afc1c4bdea5098e65697409159bb20f85af5a
--- /dev/null
+++ b/CPU/logi_compiler_sources/logi_compiler.py
@@ -0,0 +1,344 @@
+#!/usr/bin/env python2
+# encoding: utf-8
+
+# Author: adrien.lescourt@hesge.ch
+# 04.2014, hepia
+
+import sys
+import os
+from circ_manager import CircManager
+
+
+def error_message(message, error_level='FATAL ERROR'):
+ if error_level is not None:
+ print '***', error_level, '***'
+ print message
+ sys.exit(0)
+
+
+class LogiCompiler():
+
+ specialchar = ['+', '-', '<<', '>>', '=', '[', ']', '#']
+
+ comment_char = '#'
+
+ opcode = {'+': '0000',
+ '-': '0001',
+ '<<': '0010',
+ '>>': '0011',
+ 'asr': '0100',
+ 'and': '0101',
+ 'or': '0110',
+ 'not': '0111',
+ '=': '1000',
+ 'bcz': '1010',
+ 'bcn': '1010',
+ 'bcc': '1010',
+ 'bcv': '1010',
+ 'b': '1011',
+ 'ld': '1100',
+ 'st': '1101',
+ 'bl': '1110',
+ 'br': '1111',
+ }
+
+ condition = {'bcz': '1000',
+ 'bcn': '0100',
+ 'bcc': '0010',
+ 'bcv': '0001'}
+
+ register = {'r0': '000',
+ 'r1': '001',
+ 'r2': '010',
+ 'r3': '011',
+ 'r4': '100',
+ 'r5': '101',
+ 'r6': '110',
+ 'r7': '111'}
+
+ def get_binary_list(self, assembly_code):
+ """
+ Read the assembly_code list and return the corresponding binary_code list
+ """
+ self.current_line = 0
+ binary_list = []
+ (all_operands, label_list) = self.__get_operands(assembly_code)
+
+ if self.__has_multiple_label([elem[0][0] for elem in label_list]):
+ error_message('A label is present more than once!')
+
+ for operands in all_operands:
+ self.current_line += 1
+ if operands is None: # blank line or comment
+ continue
+
+ try:
+ instruction = self.Instruction(operands, label_list)
+ except:
+ error_message('On line ' + str(self.current_line))
+ if instruction.data is not None:
+ if instruction.data is 'label':
+ print operands[0][0]
+ else:
+ print instruction.data, ' : ', ' '.join(operands[0])
+ binary_list.append(instruction.data)
+ else:
+ error_message('On line ' + str(self.current_line))
+ return binary_list
+
+ def __get_operands(self, assembly_code):
+ """
+ Return an operands list for every assembly line (operands, instruction_line),
+ and an array of label (label, instruction_line)
+ """
+ current_line = 0
+ instruction_line = 1
+ all_operands = []
+ label_list = []
+ for assembly_line in assembly_code:
+ current_line += 1
+ assembly_line = self.__add_spaces(assembly_line)
+ if len(assembly_line) < 1 or self.__is_comment(assembly_line):
+ all_operands.append(None)
+ else:
+ operands = assembly_line.split()
+ if self.__is_label(operands):
+ label_list.append((operands, instruction_line))
+ else:
+ instruction_line += 1
+ all_operands.append((operands, instruction_line - 1))
+ return (all_operands, label_list)
+
+ def __add_spaces(self, line):
+ if '=' in line or '[' in line:
+ for op in LogiCompiler.specialchar:
+ line = line.replace(op, ' ' + op + ' ')
+ return ' '.join(line.split()).strip()
+ return line.strip()
+
+ def __is_comment(self, line):
+ return line[0] == LogiCompiler.comment_char
+
+ def __is_label(self, operands):
+ return operands[0].find(':') != -1
+
+ def __has_multiple_label(self, label_list):
+ return len(label_list) != len(set(label_list))
+
+ class Instruction():
+ def __init__(self, operands_with_line, label_with_line):
+ self.load_size = 8
+ self.jump_cond_size = 8
+ self.jump_size = 12
+ self.perif_size = 8
+ operands = operands_with_line[0]
+ line_nbr = operands_with_line[1]
+ self.data = None
+ operands_size = len(operands)
+ if operands_size == 1:
+ self.data = self.__get_binary_from_1_operands(operands)
+ if operands_size == 2:
+ self.data = self.__get_binary_from_2_operands(operands, line_nbr, label_with_line)
+ if operands_size == 3:
+ self.data = self.__get_binary_from_3_operands(operands)
+ elif operands_size == 4:
+ self.data = self.__get_binary_from_4_operands(operands)
+ elif operands_size == 5:
+ self.data = self.__get_binary_from_5_operands(operands, label_with_line)
+ elif operands_size == 10:
+ self.data = self.__get_binary_from_10_operands(operands)
+
+ def __get_binary_from_1_operands(self, operands):
+ if operands[0][-1] != ':' or not operands[0][:-1].isalnum():
+ error_message('Label must be alphanumeric and end with colon', None)
+ return
+ return 'label'
+
+ def __get_binary_from_2_operands(self, operands, line_nbr, label_with_line):
+ if operands[0] not in LogiCompiler.opcode:
+ print 'Error:', operands[0], 'not reconized'
+ return
+ opcode = LogiCompiler.opcode[operands[0]]
+ # bcz / bcn / bcc / bcv
+ if operands[0] in LogiCompiler.condition:
+ cond = LogiCompiler.condition[operands[0]]
+ jump_offset = self.__get_jump_offset(operands[1], line_nbr, label_with_line)
+ jump = self.__num_to_binary(jump_offset, self.jump_cond_size)
+ return opcode + cond + jump
+ # b
+ elif operands[0] == 'b':
+ jump_offset = self.__get_jump_offset(operands[1], line_nbr, label_with_line)
+ jump = self.__num_to_binary(jump_offset, self.jump_size)
+ return opcode + jump
+ # bl <label>
+ elif operands[0] == 'bl':
+ jump = self.__get_abs_jump_ofset(operands[1],label_with_line)
+ func_adr = self.__num_to_binary(str(jump), self.jump_cond_size)
+ reserved = '0'
+ return opcode+LogiCompiler.register["r7"]+reserved+func_adr
+
+ def __get_abs_jump_ofset(self, operand, label_with_line):
+ return self.__get_jump_offset(operand,1,label_with_line)
+
+ def __get_jump_offset(self, operand, line_nbr, label_with_line):
+ if self.__is_integer(operand):
+ return operand
+ else:
+ label_pos = [elem[1] for elem in label_with_line if elem[0][0] == (operand + ':')]
+ if not label_pos:
+ error_message('"' + operand + '" label not found')
+ else:
+ return str(label_pos[0] - line_nbr)
+
+ def __get_binary_from_3_operands(self, operands):
+ if operands[1] not in LogiCompiler.opcode:
+ print 'Error:', operands[1], 'not reconized'
+ return
+ # Affectation
+ opcode = LogiCompiler.opcode[operands[1]]
+ result = LogiCompiler.register[operands[0]]
+ reserved = '0'
+ load = self.__num_to_binary(operands[2], self.load_size)
+ return opcode + result + reserved + load
+
+ def __get_binary_from_4_operands(self, operands):
+ # br
+ if operands[1] == '[' and operands[3] == ']':
+ opcode = LogiCompiler.opcode[operands[0]]
+ result = LogiCompiler.register[operands[2]]
+ reserved = '000000000'
+ return opcode + result + reserved
+ if operands[2] not in LogiCompiler.opcode:
+ print 'Error:', operands[2], 'not reconized'
+ return
+ # asr / not
+ opcode = LogiCompiler.opcode[operands[2]]
+ result = LogiCompiler.register[operands[0]]
+ source_0 = LogiCompiler.register[operands[3]]
+ source_1 = '000'
+ reserved = '000'
+ return opcode + result + source_0 + source_1 + reserved
+
+ def __get_binary_from_5_operands(self, operands, label_with_line):
+ # ld / st
+ if operands[0] == "ld" or operands[0] == "st":
+ opcode = LogiCompiler.opcode[operands[0]]
+ res = operands[1].split(',')
+ rd = LogiCompiler.register[res[0]]
+ val = self.__num_to_binary(res[1],self.load_size-2)
+ rp = LogiCompiler.register[operands[3]]
+ return opcode + rd + rp + val
+ # ldr
+ if operands[2] == '[' and operands[4] == ']':
+ opcode = LogiCompiler.opcode[operands[2]]
+ result = LogiCompiler.register[operands[0]]
+ reserved = '0'
+ perif = self.__num_to_binary(operands[3], self.perif_size)
+ return opcode + result + reserved + perif
+ # bl [rl] <label> or <val>
+ if operands[1] == '[' and operands[3] == ']':
+ opcode = LogiCompiler.opcode[operands[0]]
+ result = LogiCompiler.register[operands[2]]
+ value = self.__num_to_binary(operands[4], self.load_size)
+ if value == "-1":
+ jump = self.__get_abs_jump_ofset(operands[4],label_with_line)
+ value = self.__num_to_binary(str(jump), self.jump_cond_size)
+ reserved = '0'
+ return opcode + result + reserved + value
+ # str
+ if operands[0] == '[' and operands[2] == ']':
+ opcode = LogiCompiler.opcode[operands[2]]
+ result = LogiCompiler.register[operands[4]]
+ reserved = '0'
+ perif = self.__num_to_binary(operands[1], self.perif_size)
+ return opcode + result + reserved + perif
+
+ # add / sub / shift / or / and
+ else:
+ if operands[3] not in LogiCompiler.opcode:
+ print 'Error:', operands[3], 'not reconized'
+ return
+ opcode = LogiCompiler.opcode[operands[3]]
+ result = LogiCompiler.register[operands[0]]
+ source_0 = LogiCompiler.register[operands[2]]
+ source_1 = ''
+ if operands[3] == '<<' or operands[3] == '>>':
+ source_1 = '000'
+ else:
+ source_1 = LogiCompiler.register[operands[4]]
+ reserved = '000'
+ return opcode + result + source_0 + source_1 + reserved
+
+ def __get_binary_from_10_operands(self, operands):
+ # GR / GW
+ if operands[0] not in LogiCompiler.opcode:
+ print 'Error:', operands[0], 'not reconized'
+ return
+ print(operands)
+ opcode = LogiCompiler.opcode[operands[0]]
+ data = LogiCompiler.register[operands[2]]
+ ah = LogiCompiler.register[operands[5]]
+ al = LogiCompiler.register[operands[8]]
+ reserved = '000'
+ return opcode + data + ah + al + reserved
+
+ def __num_to_binary(self, num, bits):
+ if len(num) >= 2:
+ prefix = num[:2]
+ if prefix == '0x' or prefix == '0X':
+ return self.__hex_to_binary(num, bits)
+ elif prefix == '0b' or prefix == '0B':
+ return self.__bin_to_binary(num, bits)
+ if (num[0] >= 'a' and num[0] <= 'z') or (num[0] >= 'A' and num[0] <= 'Z'):
+ return "-1"
+ return self.__int_to_binary(num, bits)
+
+ def __int_to_binary(self, num, bits):
+ num = int(num)
+ binary = ''
+ while bits:
+ binary = ('1' if num & 1 else '0') + binary
+ bits = bits - 1
+ num = num >> 1
+ return binary
+
+ def __hex_to_binary(self, hexnum, bits):
+ return bin(int(hexnum, 16))[2:].zfill(bits)
+
+ def __bin_to_binary(self, binnum, bits):
+ if len(binnum) > bits+2:
+ print binnum, 'size must not be longer than', bits, 'bits'
+ return
+ elif len(binnum) <= 2:
+ print binnum, 'is too short'
+ return
+ return binnum[2:].zfill(bits)
+
+ def __is_integer(self, nbr):
+ try:
+ int(nbr)
+ return True
+ except ValueError:
+ return False
+
+if __name__ == '__main__':
+ if len(sys.argv) != 3:
+ print 'usage: ./logi_compiler lsn_assembly_file output_file.circ'
+ sys.exit(0)
+ in_file = sys.argv[1]
+ out_file = sys.argv[2]
+ assembly = [line.rstrip().lower() for line in open(in_file, 'r')]
+ logicomp = LogiCompiler()
+ binary_list = logicomp.get_binary_list(assembly)
+ if len(binary_list) > 128:
+ print len(binary_list), 'instructions found. Max limit is 128'
+ sys.exit(0)
+ circ_manager = CircManager()
+ circ_manager.append_constant_from_binary_list(binary_list)
+ if os.path.isfile(out_file):
+ os.remove(out_file)
+ f = open(out_file, 'w')
+ for char in circ_manager.get_XML():
+ f.write(char)
+ f.close()
+ print out_file, 'successfully generated'
diff --git a/CPU/logi_compiler_sources/rom_base.circ b/CPU/logi_compiler_sources/rom_base.circ
new file mode 100644
index 0000000000000000000000000000000000000000..19fca5f1c39ca70b9446d516c5fe1e0d66240643
--- /dev/null
+++ b/CPU/logi_compiler_sources/rom_base.circ
@@ -0,0 +1,309 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project source="2.10.1" version="1.0">
+This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+<lib desc="#Wiring" name="0">
+ <tool name="Splitter">
+ <a name="fanout" val="32"/>
+ <a name="incoming" val="32"/>
+ </tool>
+ </lib>
+ <lib desc="#Gates" name="1"/>
+ <lib desc="#Plexers" name="2"/>
+ <lib desc="#Arithmetic" name="3"/>
+ <lib desc="#Memory" name="4"/>
+ <lib desc="#I/O" name="5"/>
+ <lib desc="#HDL-IP" name="6"/>
+ <lib desc="#Base" name="7">
+ <tool name="Text Tool">
+ <a name="text" val=""/>
+ <a name="font" val="SansSerif plain 12"/>
+ <a name="halign" val="center"/>
+ <a name="valign" val="base"/>
+ </tool>
+ </lib>
+ <main name="rom"/>
+ <options>
+ <a name="gateUndefined" val="ignore"/>
+ <a name="simlimit" val="1000"/>
+ <a name="simrand" val="0"/>
+ <a name="tickmain" val="half_period"/>
+ </options>
+ <mappings>
+ <tool lib="7" map="Button2" name="Menu Tool"/>
+ <tool lib="7" map="Ctrl Button1" name="Menu Tool"/>
+ <tool lib="7" map="Button3" name="Menu Tool"/>
+ </mappings>
+ <toolbar>
+ <tool lib="7" name="Poke Tool"/>
+ <tool lib="7" name="Edit Tool"/>
+ <tool lib="7" name="Text Tool">
+ <a name="text" val=""/>
+ <a name="font" val="SansSerif plain 12"/>
+ <a name="halign" val="center"/>
+ <a name="valign" val="base"/>
+ </tool>
+ <sep/>
+ <tool lib="0" name="Pin">
+ <a name="tristate" val="false"/>
+ </tool>
+ <tool lib="0" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="labelloc" val="east"/>
+ </tool>
+ <tool lib="1" name="NOT Gate"/>
+ <tool lib="1" name="AND Gate"/>
+ <tool lib="1" name="OR Gate"/>
+ </toolbar>
+ <circuit name="rom">
+ <a name="circuit" val="rom"/>
+ <a name="clabel" val=""/>
+ <a name="clabelup" val="east"/>
+ <a name="clabelfont" val="SansSerif plain 12"/>
+ <a name="circuitvhdl" val="false"/>
+ <a name="circuitvhdlpath" val=""/>
+ <wire from="(410,680)" to="(450,680)"/>
+ <wire from="(300,810)" to="(370,810)"/>
+ <wire from="(550,180)" to="(660,180)"/>
+ <wire from="(260,180)" to="(370,180)"/>
+ <wire from="(180,510)" to="(190,510)"/>
+ <wire from="(550,240)" to="(660,240)"/>
+ <wire from="(590,750)" to="(660,750)"/>
+ <wire from="(300,190)" to="(370,190)"/>
+ <wire from="(590,310)" to="(660,310)"/>
+ <wire from="(260,240)" to="(370,240)"/>
+ <wire from="(980,650)" to="(1000,650)"/>
+ <wire from="(590,250)" to="(660,250)"/>
+ <wire from="(590,190)" to="(660,190)"/>
+ <wire from="(300,750)" to="(370,750)"/>
+ <wire from="(300,310)" to="(370,310)"/>
+ <wire from="(550,400)" to="(660,400)"/>
+ <wire from="(590,550)" to="(660,550)"/>
+ <wire from="(550,680)" to="(660,680)"/>
+ <wire from="(260,620)" to="(370,620)"/>
+ <wire from="(260,400)" to="(370,400)"/>
+ <wire from="(300,550)" to="(370,550)"/>
+ <wire from="(300,630)" to="(370,630)"/>
+ <wire from="(550,620)" to="(660,620)"/>
+ <wire from="(260,680)" to="(370,680)"/>
+ <wire from="(550,280)" to="(660,280)"/>
+ <wire from="(180,480)" to="(390,480)"/>
+ <wire from="(260,340)" to="(370,340)"/>
+ <wire from="(590,690)" to="(660,690)"/>
+ <wire from="(300,690)" to="(370,690)"/>
+ <wire from="(300,250)" to="(370,250)"/>
+ <wire from="(550,780)" to="(660,780)"/>
+ <wire from="(260,520)" to="(370,520)"/>
+ <wire from="(410,300)" to="(450,300)"/>
+ <wire from="(260,740)" to="(370,740)"/>
+ <wire from="(550,340)" to="(660,340)"/>
+ <wire from="(550,560)" to="(660,560)"/>
+ <wire from="(260,560)" to="(370,560)"/>
+ <wire from="(590,630)" to="(660,630)"/>
+ <wire from="(550,740)" to="(660,740)"/>
+ <wire from="(700,680)" to="(740,680)"/>
+ <wire from="(300,610)" to="(370,610)"/>
+ <wire from="(300,790)" to="(370,790)"/>
+ <wire from="(550,440)" to="(660,440)"/>
+ <wire from="(260,780)" to="(370,780)"/>
+ <wire from="(550,520)" to="(660,520)"/>
+ <wire from="(590,210)" to="(660,210)"/>
+ <wire from="(300,390)" to="(370,390)"/>
+ <wire from="(300,730)" to="(370,730)"/>
+ <wire from="(300,230)" to="(370,230)"/>
+ <wire from="(550,580)" to="(660,580)"/>
+ <wire from="(260,720)" to="(370,720)"/>
+ <wire from="(590,270)" to="(660,270)"/>
+ <wire from="(140,490)" to="(160,490)"/>
+ <wire from="(260,280)" to="(370,280)"/>
+ <wire from="(300,670)" to="(370,670)"/>
+ <wire from="(300,450)" to="(370,450)"/>
+ <wire from="(550,140)" to="(660,140)"/>
+ <wire from="(260,360)" to="(370,360)"/>
+ <wire from="(260,800)" to="(370,800)"/>
+ <wire from="(260,600)" to="(370,600)"/>
+ <wire from="(590,590)" to="(660,590)"/>
+ <wire from="(550,700)" to="(660,700)"/>
+ <wire from="(260,420)" to="(370,420)"/>
+ <wire from="(300,350)" to="(370,350)"/>
+ <wire from="(300,570)" to="(370,570)"/>
+ <wire from="(590,370)" to="(660,370)"/>
+ <wire from="(590,150)" to="(660,150)"/>
+ <wire from="(300,290)" to="(370,290)"/>
+ <wire from="(550,820)" to="(660,820)"/>
+ <wire from="(590,810)" to="(660,810)"/>
+ <wire from="(260,300)" to="(370,300)"/>
+ <wire from="(550,200)" to="(660,200)"/>
+ <wire from="(680,460)" to="(680,480)"/>
+ <wire from="(810,740)" to="(910,740)"/>
+ <wire from="(550,640)" to="(660,640)"/>
+ <wire from="(180,490)" to="(180,510)"/>
+ <wire from="(260,660)" to="(370,660)"/>
+ <wire from="(390,480)" to="(390,520)"/>
+ <wire from="(590,430)" to="(660,430)"/>
+ <wire from="(550,260)" to="(660,260)"/>
+ <wire from="(300,590)" to="(370,590)"/>
+ <wire from="(860,730)" to="(910,730)"/>
+ <wire from="(590,350)" to="(660,350)"/>
+ <wire from="(260,380)" to="(370,380)"/>
+ <wire from="(300,530)" to="(370,530)"/>
+ <wire from="(550,320)" to="(660,320)"/>
+ <wire from="(590,710)" to="(660,710)"/>
+ <wire from="(260,320)" to="(370,320)"/>
+ <wire from="(950,740)" to="(1000,740)"/>
+ <wire from="(550,760)" to="(660,760)"/>
+ <wire from="(590,650)" to="(660,650)"/>
+ <wire from="(260,540)" to="(370,540)"/>
+ <wire from="(550,540)" to="(660,540)"/>
+ <wire from="(260,760)" to="(370,760)"/>
+ <wire from="(300,710)" to="(370,710)"/>
+ <wire from="(300,410)" to="(370,410)"/>
+ <wire from="(590,530)" to="(660,530)"/>
+ <wire from="(260,220)" to="(370,220)"/>
+ <wire from="(590,330)" to="(660,330)"/>
+ <wire from="(300,770)" to="(370,770)"/>
+ <wire from="(590,770)" to="(660,770)"/>
+ <wire from="(550,220)" to="(660,220)"/>
+ <wire from="(300,170)" to="(370,170)"/>
+ <wire from="(590,410)" to="(660,410)"/>
+ <wire from="(300,830)" to="(370,830)"/>
+ <wire from="(550,380)" to="(660,380)"/>
+ <wire from="(260,160)" to="(370,160)"/>
+ <wire from="(590,830)" to="(660,830)"/>
+ <wire from="(550,160)" to="(660,160)"/>
+ <wire from="(920,820)" to="(930,820)"/>
+ <wire from="(860,750)" to="(910,750)"/>
+ <wire from="(590,790)" to="(660,790)"/>
+ <wire from="(1000,650)" to="(1000,740)"/>
+ <wire from="(590,570)" to="(660,570)"/>
+ <wire from="(260,640)" to="(370,640)"/>
+ <wire from="(810,720)" to="(910,720)"/>
+ <wire from="(550,660)" to="(660,660)"/>
+ <wire from="(590,170)" to="(660,170)"/>
+ <wire from="(590,610)" to="(660,610)"/>
+ <wire from="(550,720)" to="(660,720)"/>
+ <wire from="(260,580)" to="(370,580)"/>
+ <wire from="(300,330)" to="(370,330)"/>
+ <wire from="(260,440)" to="(370,440)"/>
+ <wire from="(550,360)" to="(660,360)"/>
+ <wire from="(590,450)" to="(660,450)"/>
+ <wire from="(390,480)" to="(680,480)"/>
+ <wire from="(590,670)" to="(660,670)"/>
+ <wire from="(700,300)" to="(740,300)"/>
+ <wire from="(300,270)" to="(370,270)"/>
+ <wire from="(550,800)" to="(660,800)"/>
+ <wire from="(590,390)" to="(660,390)"/>
+ <wire from="(590,730)" to="(660,730)"/>
+ <wire from="(930,760)" to="(930,820)"/>
+ <wire from="(1000,740)" to="(1030,740)"/>
+ <wire from="(260,200)" to="(370,200)"/>
+ <wire from="(260,820)" to="(370,820)"/>
+ <wire from="(300,370)" to="(370,370)"/>
+ <wire from="(300,150)" to="(370,150)"/>
+ <wire from="(300,430)" to="(370,430)"/>
+ <wire from="(550,420)" to="(660,420)"/>
+ <wire from="(260,140)" to="(370,140)"/>
+ <wire from="(590,230)" to="(660,230)"/>
+ <wire from="(680,480)" to="(680,520)"/>
+ <wire from="(260,260)" to="(370,260)"/>
+ <wire from="(590,290)" to="(660,290)"/>
+ <wire from="(300,650)" to="(370,650)"/>
+ <wire from="(390,460)" to="(390,480)"/>
+ <wire from="(300,210)" to="(370,210)"/>
+ <wire from="(260,700)" to="(370,700)"/>
+ <wire from="(550,300)" to="(660,300)"/>
+ <wire from="(550,600)" to="(660,600)"/>
+ <comp lib="0" loc="(920,820)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="2"/>
+ <a name="label" val="sel"/>
+ </comp>
+ <comp lib="2" loc="(410,300)" name="Multiplexer">
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="2" loc="(700,300)" name="Multiplexer">
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(980,650)" name="Probe">
+ <a name="radix" val="16"/>
+ </comp>
+ <comp lib="0" loc="(810,720)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux0"/>
+ </comp>
+ <comp lib="0" loc="(160,490)" name="Splitter">
+ <a name="incoming" val="7"/>
+ <a name="appear" val="center"/>
+ <a name="bit1" val="0"/>
+ <a name="bit2" val="0"/>
+ <a name="bit3" val="0"/>
+ <a name="bit4" val="0"/>
+ <a name="bit5" val="1"/>
+ <a name="bit6" val="1"/>
+ </comp>
+ <comp lib="2" loc="(410,680)" name="Multiplexer">
+ <a name="selloc" val="tr"/>
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(450,680)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux1"/>
+ </comp>
+ <comp lib="0" loc="(740,300)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux2"/>
+ </comp>
+ <comp lib="2" loc="(700,680)" name="Multiplexer">
+ <a name="selloc" val="tr"/>
+ <a name="select" val="5"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(190,510)" name="Tunnel">
+ <a name="width" val="2"/>
+ <a name="label" val="sel"/>
+ </comp>
+ <comp lib="0" loc="(1030,740)" name="Pin">
+ <a name="facing" val="west"/>
+ <a name="output" val="true"/>
+ <a name="width" val="16"/>
+ <a name="label" val="data_out"/>
+ <a name="labelloc" val="east"/>
+ </comp>
+ <comp lib="0" loc="(450,300)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux0"/>
+ </comp>
+ <comp lib="0" loc="(860,730)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux1"/>
+ </comp>
+ <comp lib="0" loc="(860,750)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux3"/>
+ </comp>
+ <comp lib="0" loc="(810,740)" name="Tunnel">
+ <a name="facing" val="east"/>
+ <a name="width" val="16"/>
+ <a name="label" val="mux2"/>
+ </comp>
+ <comp lib="0" loc="(140,490)" name="Pin">
+ <a name="width" val="7"/>
+ <a name="tristate" val="false"/>
+ <a name="label" val="addr"/>
+ </comp>
+ <comp lib="2" loc="(950,740)" name="Multiplexer">
+ <a name="select" val="2"/>
+ <a name="width" val="16"/>
+ </comp>
+ <comp lib="0" loc="(740,680)" name="Tunnel">
+ <a name="width" val="16"/>
+ <a name="label" val="mux3"/>
+ </comp>
+ </circuit>
+</project>
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