From 95f332163a4a1e99694901ae3b15d4344811a9cd Mon Sep 17 00:00:00 2001
From: "sebastie.gendre" <sebastien.gendre@etu.hesge.ch>
Date: Sat, 29 Mar 2025 01:05:01 +0100
Subject: [PATCH] Add the copyright again, don't know if this is trivial enough
to don't be copyrighted
---
.../microblaze-demo.srcs/sources_1/new/mb_top.vhd | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd b/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd
index c3b402c..591d5a5 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/new/mb_top.vhd
@@ -1,3 +1,5 @@
+--Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
--Date : Tue Mar 4 22:03:33 2025
@@ -6,10 +8,12 @@
--Design : mb_design_1_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
+
entity mb_design_1_wrapper is
Generic (
-- Hog build info
@@ -37,6 +41,7 @@ architecture STRUCTURE of mb_design_1_wrapper is
hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component mb_design_1;
+
begin
mb_design_1_i: component mb_design_1
port map (
--
GitLab