diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
index c927a4a2182bbf49915669eae7f5ca5984f332f5..918c957ee331ec11bf84f5ea0845391d31484830 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/hdl/mb_design_1_wrapper.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
---Date : Tue Mar 4 22:34:13 2025
+--Date : Thu Mar 20 16:44:45 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1_wrapper.bd
--Design : mb_design_1_wrapper
@@ -16,6 +16,10 @@ entity mb_design_1_wrapper is
port (
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk_in1 : in STD_LOGIC;
+ hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
reset : in STD_LOGIC
);
end mb_design_1_wrapper;
@@ -23,9 +27,13 @@ end mb_design_1_wrapper;
architecture STRUCTURE of mb_design_1_wrapper is
component mb_design_1 is
port (
+ GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk_in1 : in STD_LOGIC;
reset : in STD_LOGIC;
- GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
+ hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component mb_design_1;
begin
@@ -33,6 +41,10 @@ mb_design_1_i: component mb_design_1
port map (
GPIO_0_tri_o(7 downto 0) => GPIO_0_tri_o(7 downto 0),
clk_in1 => clk_in1,
+ hog_global_date_i_0(31 downto 0) => hog_global_date_i_0(31 downto 0),
+ hog_global_sha_i_0(31 downto 0) => hog_global_sha_i_0(31 downto 0),
+ hog_global_time_i_0(31 downto 0) => hog_global_time_i_0(31 downto 0),
+ hog_global_ver_i_0(31 downto 0) => hog_global_ver_i_0(31 downto 0),
reset => reset
);
end STRUCTURE;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
index e025cf639d69b0052ddc06001d8f4967d2c10c96..aa0b815b2ad5afc75307993cf62797ed8be29e6a 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xml
@@ -378,7 +378,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -516,7 +516,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xml
index 734bbb24061664ddd727dc8851a5f5ec8750bd6f..541cfa6a8878b4ba38f9de897c0d3083652395fb 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xml
@@ -344,7 +344,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -353,7 +353,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
@@ -2007,9 +2007,9 @@ Read: 0 - No interrupt has occurred 1 - Interrupt has occurred Write:
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
index 10953fd7a5eb5b762581c9fb0fdccdc38be32e18..e6405dfaf8698a91b978b0a3e6f9906fa52e2fb6 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xml
@@ -5356,7 +5356,7 @@
<spirit:modelParameter spirit:dataType="std_logic_vector">
<spirit:name>C_MASK</spirit:name>
<spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x0000000040000000</spirit:value>
+ <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MASK" spirit:bitStringLength="64">0x00000000c0000000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector">
<spirit:name>C_MASK1</spirit:name>
@@ -5753,7 +5753,7 @@
<spirit:parameter>
<spirit:name>C_MASK</spirit:name>
<spirit:displayName>SLMB Address Decode Mask</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="4" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x0000000040000000</spirit:value>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_MASK" spirit:order="4" spirit:configGroups="1 Addresses" spirit:bitStringLength="64">0x00000000c0000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
index 96e692583f03084ab1e9a18a0914484ecec3e3ed..d072aac2f5b75f8c5e588f6303c584d882202347 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xml
@@ -6632,7 +6632,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -6641,7 +6641,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
- <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -8318,7 +8318,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
- <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M04_AXI.CLK_DOMAIN"/>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.M04_AXI.CLK_DOMAIN">/clk_wiz_0_clk_out1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.tlm</xilinx:parameterUsage>
@@ -31658,11 +31658,11 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector">
<spirit:name>C_M_AXI_BASE_ADDR</spirit:name>
- <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_BASE_ADDR" spirit:bitStringLength="320">0xffffffffffffffffffffffffffffffff000000004120000000000000400000000000000041400000</spirit:value>
+ <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_BASE_ADDR" spirit:bitStringLength="320">0x000000008000000000000000412000000000000041c0000000000000400000000000000041400000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector">
<spirit:name>C_M_AXI_ADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ADDR_WIDTH" spirit:bitStringLength="160">0x000000000000000000000010000000100000000c</spirit:value>
+ <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ADDR_WIDTH" spirit:bitStringLength="160">0x000000070000001000000010000000100000000c</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S_AXI_BASE_ID</spirit:name>
@@ -40756,7 +40756,7 @@
<spirit:parameter>
<spirit:name>M02_A00_BASE_ADDR</spirit:name>
<spirit:displayName>My M02_A00_BASE_ADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M02_A00_BASE_ADDR" spirit:order="725" spirit:bitStringLength="64">0x0000000041200000</spirit:value>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M02_A00_BASE_ADDR" spirit:order="725" spirit:bitStringLength="64">0x0000000041C00000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -40948,7 +40948,7 @@
<spirit:parameter>
<spirit:name>M03_A00_BASE_ADDR</spirit:name>
<spirit:displayName>My M03_A00_BASE_ADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_BASE_ADDR" spirit:order="741" spirit:bitStringLength="64">0xffffffffffffffff</spirit:value>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_BASE_ADDR" spirit:order="741" spirit:bitStringLength="64">0x0000000041200000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -41140,7 +41140,7 @@
<spirit:parameter>
<spirit:name>M04_A00_BASE_ADDR</spirit:name>
<spirit:displayName>My M04_A00_BASE_ADDR</spirit:displayName>
- <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M04_A00_BASE_ADDR" spirit:order="757" spirit:bitStringLength="64">0xffffffffffffffff</spirit:value>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M04_A00_BASE_ADDR" spirit:order="757" spirit:bitStringLength="64">0x0000000080000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -44020,7 +44020,7 @@
<spirit:parameter>
<spirit:name>M03_A00_ADDR_WIDTH</spirit:name>
<spirit:displayName>My M03_A00_ADDR_WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_ADDR_WIDTH" spirit:order="997" spirit:minimum="0" spirit:maximum="64" spirit:rangeType="long">0</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_ADDR_WIDTH" spirit:order="997" spirit:minimum="0" spirit:maximum="64" spirit:rangeType="long">16</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -44212,7 +44212,7 @@
<spirit:parameter>
<spirit:name>M04_A00_ADDR_WIDTH</spirit:name>
<spirit:displayName>My M04_A00_ADDR_WIDTH</spirit:displayName>
- <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M04_A00_ADDR_WIDTH" spirit:order="1013" spirit:minimum="0" spirit:maximum="64" spirit:rangeType="long">0</spirit:value>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M04_A00_ADDR_WIDTH" spirit:order="1013" spirit:minimum="0" spirit:maximum="64" spirit:rangeType="long">7</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -46628,7 +46628,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.BUSER_WIDTH" xilinx:valuePermission="bd"/>
@@ -46636,19 +46636,19 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.FREQ_HZ" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_CACHE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_LOCK" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_QOS" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_REGION" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_THREADS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.PHASE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
@@ -46675,7 +46675,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.NUM_READ_THREADS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
@@ -46685,7 +46685,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.RUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
- <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.WUSER_BITS_PER_BYTE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M04_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RSTIF.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
@@ -46925,8 +46925,8 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M02_S15_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M02_S15_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M02_WRITE_ISSUING" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_BASE_ADDR" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_BASE_ADDR" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A01_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A01_BASE_ADDR" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A02_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
@@ -46958,8 +46958,8 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A15_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A15_BASE_ADDR" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_READ_ISSUING" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_READ_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_WRITE_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S01_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S01_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S02_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
@@ -46991,8 +46991,8 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S15_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S15_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_WRITE_ISSUING" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A00_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A00_BASE_ADDR" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A00_ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A00_BASE_ADDR" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A01_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A01_BASE_ADDR" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A02_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
@@ -47024,8 +47024,8 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A15_ADDR_WIDTH" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_A15_BASE_ADDR" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_READ_ISSUING" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_S00_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
- <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_S00_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_S00_READ_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_S00_WRITE_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_S01_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_S01_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M04_S02_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bda b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bda
index 13572b024d84e97e06301bc6d21c8fb295e36242..f56212cc1d3125eab24354cdcdd8823d3b0f6953 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bda
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bda
@@ -278,6 +278,42 @@
"SV": "xilinx.com:ip:mdm:3.2",
"TM": "data",
"TU": "register"
+ },
+ "V8": {
+ "VT": "AC",
+ "BA": "0x41C00000",
+ "HA": "0x41C0FFFF",
+ "BP": "C_BASEADDR",
+ "HP": "C_HIGHADDR",
+ "MA": "Data",
+ "MX": "/microblaze_0",
+ "MI": "M_AXI_DP",
+ "MS": "SEG_axi_timer_0_Reg",
+ "MV": "xilinx.com:ip:microblaze:11.0",
+ "SX": "/axi_timer_0",
+ "SI": "S_AXI",
+ "SS": "Reg",
+ "SV": "xilinx.com:ip:axi_timer:2.0",
+ "TM": "data",
+ "TU": "register"
+ },
+ "V9": {
+ "VT": "AC",
+ "BA": "0x80000000",
+ "HA": "0x8000007F",
+ "BP": "C_BASEADDR",
+ "HP": "C_HIGHADDR",
+ "MA": "Data",
+ "MX": "/microblaze_0",
+ "MI": "M_AXI_DP",
+ "MS": "SEG_axi4lite_hog_build_i_0_reg0",
+ "MV": "xilinx.com:ip:microblaze:11.0",
+ "SX": "/axi4lite_hog_build_i_0",
+ "SI": "s_axi",
+ "SS": "reg0",
+ "SV": "xilinx.com:module_ref:axi4lite_hog_build_info:1.0",
+ "TM": "data",
+ "TU": "register"
}
},
"edges": [
@@ -313,6 +349,16 @@
"src": "V7",
"trg": "V2",
"EH": "2"
+ },
+ {
+ "src": "V8",
+ "trg": "V2",
+ "EH": "2"
+ },
+ {
+ "src": "V9",
+ "trg": "V2",
+ "EH": "2"
}
]
}
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
index d4a556ff86b5d20cb98a15b760b4eaa083ff8297..f4217e021dfa8a881e7b16ef73d3bf306d786f55 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/mb_design_1.bmm
@@ -1,11 +1,11 @@
WORKFLOW_OPERATION simulation,dialog;
-DEFINE_MEMORY_TYPE blk_mem_gen_0_32K_1_MEM_DEVICE [0x00008000] 32;
+DEFINE_MEMORY_TYPE blk_mem_gen_0_MEM_DEVICE [0x00008000] 32;
ADDRESS_MAP microblaze_0 MICROBLAZE-LE 100 microblaze_0
- ADDRESS_SPACE blk_mem_gen_0_32K_1_ADDR_SPACE blk_mem_gen_0_32K_1_MEM_DEVICE [0x00000000:0x00007FFF] dlmb_bram_if_cntlr_0
+ ADDRESS_SPACE blk_mem_gen_0_ADDR_SPACE blk_mem_gen_0_MEM_DEVICE [0x00000000:0x00007FFF] dlmb_bram_if_cntlr_0
BUS_BLOCK
- blk_mem_gen_0_32K_1_BUS_BLK [31:0] INPUT = "mb_design_1_blk_mem_gen_0_0.mem";
+ blk_mem_gen_0_BUS_BLK [31:0] INPUT = "mb_design_1_blk_mem_gen_0_0.mem";
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
index 56a9211ca1cc9b2b520f090a3a5d5b3780d58953..0dd7f56ac3047c33fcae4003b781f6084ff10a13 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/sim/mb_design_1.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
---Date : Tue Mar 4 22:34:13 2025
+--Date : Thu Mar 20 16:44:45 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1.bd
--Design : mb_design_1
@@ -319,193 +319,204 @@ entity m03_couplers_imp_DKAE7P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
- M_AXI_araddr : out STD_LOGIC;
- M_AXI_arburst : out STD_LOGIC;
- M_AXI_arcache : out STD_LOGIC;
- M_AXI_arlen : out STD_LOGIC;
- M_AXI_arlock : out STD_LOGIC;
- M_AXI_arprot : out STD_LOGIC;
- M_AXI_arqos : out STD_LOGIC;
+ M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
- M_AXI_arregion : out STD_LOGIC;
- M_AXI_arsize : out STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
- M_AXI_awaddr : out STD_LOGIC;
- M_AXI_awburst : out STD_LOGIC;
- M_AXI_awcache : out STD_LOGIC;
- M_AXI_awlen : out STD_LOGIC;
- M_AXI_awlock : out STD_LOGIC;
- M_AXI_awprot : out STD_LOGIC;
- M_AXI_awqos : out STD_LOGIC;
+ M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
- M_AXI_awregion : out STD_LOGIC;
- M_AXI_awsize : out STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
- M_AXI_bresp : in STD_LOGIC;
+ M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
- M_AXI_rdata : in STD_LOGIC;
- M_AXI_rlast : in STD_LOGIC;
+ M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
- M_AXI_rresp : in STD_LOGIC;
+ M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
- M_AXI_wdata : out STD_LOGIC;
- M_AXI_wlast : out STD_LOGIC;
+ M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
- M_AXI_wstrb : out STD_LOGIC;
+ M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
- S_AXI_araddr : in STD_LOGIC;
- S_AXI_arburst : in STD_LOGIC;
- S_AXI_arcache : in STD_LOGIC;
- S_AXI_arlen : in STD_LOGIC;
- S_AXI_arlock : in STD_LOGIC;
- S_AXI_arprot : in STD_LOGIC;
- S_AXI_arqos : in STD_LOGIC;
+ S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
- S_AXI_arregion : in STD_LOGIC;
- S_AXI_arsize : in STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
- S_AXI_awaddr : in STD_LOGIC;
- S_AXI_awburst : in STD_LOGIC;
- S_AXI_awcache : in STD_LOGIC;
- S_AXI_awlen : in STD_LOGIC;
- S_AXI_awlock : in STD_LOGIC;
- S_AXI_awprot : in STD_LOGIC;
- S_AXI_awqos : in STD_LOGIC;
+ S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
- S_AXI_awregion : in STD_LOGIC;
- S_AXI_awsize : in STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
- S_AXI_bresp : out STD_LOGIC;
+ S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
- S_AXI_rdata : out STD_LOGIC;
- S_AXI_rlast : out STD_LOGIC;
+ S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
- S_AXI_rresp : out STD_LOGIC;
+ S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
- S_AXI_wdata : in STD_LOGIC;
- S_AXI_wlast : in STD_LOGIC;
+ S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
- S_AXI_wstrb : in STD_LOGIC;
+ S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_DKAE7P;
architecture STRUCTURE of m03_couplers_imp_DKAE7P is
- signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARBURST : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARCACHE : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARLEN : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARLOCK : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARQOS : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARREGION : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARSIZE : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWBURST : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWCACHE : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWLEN : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWLOCK : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWQOS : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWREGION : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWSIZE : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_RLAST : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_WLAST : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
- M_AXI_araddr <= m03_couplers_to_m03_couplers_ARADDR;
- M_AXI_arburst <= m03_couplers_to_m03_couplers_ARBURST;
- M_AXI_arcache <= m03_couplers_to_m03_couplers_ARCACHE;
- M_AXI_arlen <= m03_couplers_to_m03_couplers_ARLEN;
- M_AXI_arlock <= m03_couplers_to_m03_couplers_ARLOCK;
- M_AXI_arprot <= m03_couplers_to_m03_couplers_ARPROT;
- M_AXI_arqos <= m03_couplers_to_m03_couplers_ARQOS;
- M_AXI_arregion <= m03_couplers_to_m03_couplers_ARREGION;
- M_AXI_arsize <= m03_couplers_to_m03_couplers_ARSIZE;
+ M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
- M_AXI_awaddr <= m03_couplers_to_m03_couplers_AWADDR;
- M_AXI_awburst <= m03_couplers_to_m03_couplers_AWBURST;
- M_AXI_awcache <= m03_couplers_to_m03_couplers_AWCACHE;
- M_AXI_awlen <= m03_couplers_to_m03_couplers_AWLEN;
- M_AXI_awlock <= m03_couplers_to_m03_couplers_AWLOCK;
- M_AXI_awprot <= m03_couplers_to_m03_couplers_AWPROT;
- M_AXI_awqos <= m03_couplers_to_m03_couplers_AWQOS;
- M_AXI_awregion <= m03_couplers_to_m03_couplers_AWREGION;
- M_AXI_awsize <= m03_couplers_to_m03_couplers_AWSIZE;
+ M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
- M_AXI_wdata <= m03_couplers_to_m03_couplers_WDATA;
- M_AXI_wlast <= m03_couplers_to_m03_couplers_WLAST;
- M_AXI_wstrb <= m03_couplers_to_m03_couplers_WSTRB;
+ M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
+ M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
- S_AXI_bresp <= m03_couplers_to_m03_couplers_BRESP;
+ S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
- S_AXI_rdata <= m03_couplers_to_m03_couplers_RDATA;
- S_AXI_rlast <= m03_couplers_to_m03_couplers_RLAST;
- S_AXI_rresp <= m03_couplers_to_m03_couplers_RRESP;
+ S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
+ S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
- m03_couplers_to_m03_couplers_ARADDR <= S_AXI_araddr;
- m03_couplers_to_m03_couplers_ARBURST <= S_AXI_arburst;
- m03_couplers_to_m03_couplers_ARCACHE <= S_AXI_arcache;
- m03_couplers_to_m03_couplers_ARLEN <= S_AXI_arlen;
- m03_couplers_to_m03_couplers_ARLOCK <= S_AXI_arlock;
- m03_couplers_to_m03_couplers_ARPROT <= S_AXI_arprot;
- m03_couplers_to_m03_couplers_ARQOS <= S_AXI_arqos;
+ m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
- m03_couplers_to_m03_couplers_ARREGION <= S_AXI_arregion;
- m03_couplers_to_m03_couplers_ARSIZE <= S_AXI_arsize;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
- m03_couplers_to_m03_couplers_AWADDR <= S_AXI_awaddr;
- m03_couplers_to_m03_couplers_AWBURST <= S_AXI_awburst;
- m03_couplers_to_m03_couplers_AWCACHE <= S_AXI_awcache;
- m03_couplers_to_m03_couplers_AWLEN <= S_AXI_awlen;
- m03_couplers_to_m03_couplers_AWLOCK <= S_AXI_awlock;
- m03_couplers_to_m03_couplers_AWPROT <= S_AXI_awprot;
- m03_couplers_to_m03_couplers_AWQOS <= S_AXI_awqos;
+ m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
- m03_couplers_to_m03_couplers_AWREGION <= S_AXI_awregion;
- m03_couplers_to_m03_couplers_AWSIZE <= S_AXI_awsize;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
- m03_couplers_to_m03_couplers_BRESP <= M_AXI_bresp;
+ m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
- m03_couplers_to_m03_couplers_RDATA <= M_AXI_rdata;
- m03_couplers_to_m03_couplers_RLAST <= M_AXI_rlast;
+ m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
- m03_couplers_to_m03_couplers_RRESP <= M_AXI_rresp;
+ m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
- m03_couplers_to_m03_couplers_WDATA <= S_AXI_wdata;
- m03_couplers_to_m03_couplers_WLAST <= S_AXI_wlast;
+ m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
- m03_couplers_to_m03_couplers_WSTRB <= S_AXI_wstrb;
+ m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
+entity m04_couplers_imp_OP7ZFX is
+ port (
+ M_ACLK : in STD_LOGIC;
+ M_ARESETN : in STD_LOGIC;
+ M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_arready : in STD_LOGIC;
+ M_AXI_arvalid : out STD_LOGIC;
+ M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_awready : in STD_LOGIC;
+ M_AXI_awvalid : out STD_LOGIC;
+ M_AXI_bready : out STD_LOGIC;
+ M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_bvalid : in STD_LOGIC;
+ M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_rready : out STD_LOGIC;
+ M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_rvalid : in STD_LOGIC;
+ M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_wready : in STD_LOGIC;
+ M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_wvalid : out STD_LOGIC;
+ S_ACLK : in STD_LOGIC;
+ S_ARESETN : in STD_LOGIC;
+ S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_arready : out STD_LOGIC;
+ S_AXI_arvalid : in STD_LOGIC;
+ S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_awready : out STD_LOGIC;
+ S_AXI_awvalid : in STD_LOGIC;
+ S_AXI_bready : in STD_LOGIC;
+ S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_bvalid : out STD_LOGIC;
+ S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_rready : in STD_LOGIC;
+ S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_rvalid : out STD_LOGIC;
+ S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_wready : out STD_LOGIC;
+ S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_wvalid : in STD_LOGIC
+ );
+end m04_couplers_imp_OP7ZFX;
+
+architecture STRUCTURE of m04_couplers_imp_OP7ZFX is
+ signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
+begin
+ M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
+ M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
+ M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
+ M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
+ M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
+ M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
+ M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
+ M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
+ M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
+ S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
+ S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
+ S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
+ S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
+ S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
+ S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
+ S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
+ S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
+ m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+ m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
+ m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
+ m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+ m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
+ m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
+ m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
+ m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+ m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
+ m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+ m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
+ m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+ m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
+ m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+ m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
+ m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+ m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1AM08ZQ is
port (
M_ACLK : in STD_LOGIC;
@@ -680,41 +691,42 @@ entity mb_design_1_axi_interconnect_0_0 is
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
- M03_AXI_araddr : out STD_LOGIC;
- M03_AXI_arburst : out STD_LOGIC;
- M03_AXI_arcache : out STD_LOGIC;
- M03_AXI_arlen : out STD_LOGIC;
- M03_AXI_arlock : out STD_LOGIC;
- M03_AXI_arprot : out STD_LOGIC;
- M03_AXI_arqos : out STD_LOGIC;
+ M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
- M03_AXI_arregion : out STD_LOGIC;
- M03_AXI_arsize : out STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
- M03_AXI_awaddr : out STD_LOGIC;
- M03_AXI_awburst : out STD_LOGIC;
- M03_AXI_awcache : out STD_LOGIC;
- M03_AXI_awlen : out STD_LOGIC;
- M03_AXI_awlock : out STD_LOGIC;
- M03_AXI_awprot : out STD_LOGIC;
- M03_AXI_awqos : out STD_LOGIC;
+ M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
- M03_AXI_awregion : out STD_LOGIC;
- M03_AXI_awsize : out STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
- M03_AXI_bresp : in STD_LOGIC;
+ M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
- M03_AXI_rdata : in STD_LOGIC;
- M03_AXI_rlast : in STD_LOGIC;
+ M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
- M03_AXI_rresp : in STD_LOGIC;
+ M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
- M03_AXI_wdata : out STD_LOGIC;
- M03_AXI_wlast : out STD_LOGIC;
+ M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
- M03_AXI_wstrb : out STD_LOGIC;
+ M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
+ M04_ACLK : in STD_LOGIC;
+ M04_ARESETN : in STD_LOGIC;
+ M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_arready : in STD_LOGIC;
+ M04_AXI_arvalid : out STD_LOGIC;
+ M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_awready : in STD_LOGIC;
+ M04_AXI_awvalid : out STD_LOGIC;
+ M04_AXI_bready : out STD_LOGIC;
+ M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M04_AXI_bvalid : in STD_LOGIC;
+ M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_rready : out STD_LOGIC;
+ M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M04_AXI_rvalid : in STD_LOGIC;
+ M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_wready : in STD_LOGIC;
+ M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M04_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -763,25 +775,25 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component mb_design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
@@ -792,6 +804,8 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
+ signal M04_ACLK_1 : STD_LOGIC;
+ signal M04_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
@@ -866,41 +880,40 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
signal m02_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARBURST : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARCACHE : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARLEN : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARLOCK : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARQOS : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARREGION : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARSIZE : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWBURST : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWCACHE : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWLEN : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWLOCK : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWQOS : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWREGION : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWSIZE : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_RLAST : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_WLAST : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
@@ -972,27 +985,41 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
- signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
- signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
- signal xbar_to_m03_couplers_BRESP : STD_LOGIC;
+ signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
- signal xbar_to_m03_couplers_RDATA : STD_LOGIC;
+ signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
- signal xbar_to_m03_couplers_RRESP : STD_LOGIC;
+ signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_m03_couplers_S_AXI_rlast_UNCONNECTED : STD_LOGIC;
- signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
- signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
+ signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+ signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
+ signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+ signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
+ signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
+ signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
+ signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
+ signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
+ signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
+ signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+ signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
@@ -1029,32 +1056,26 @@ begin
M02_AXI_wvalid <= m02_couplers_to_axi_interconnect_0_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
- M03_AXI_araddr <= m03_couplers_to_axi_interconnect_0_ARADDR;
- M03_AXI_arburst <= m03_couplers_to_axi_interconnect_0_ARBURST;
- M03_AXI_arcache <= m03_couplers_to_axi_interconnect_0_ARCACHE;
- M03_AXI_arlen <= m03_couplers_to_axi_interconnect_0_ARLEN;
- M03_AXI_arlock <= m03_couplers_to_axi_interconnect_0_ARLOCK;
- M03_AXI_arprot <= m03_couplers_to_axi_interconnect_0_ARPROT;
- M03_AXI_arqos <= m03_couplers_to_axi_interconnect_0_ARQOS;
- M03_AXI_arregion <= m03_couplers_to_axi_interconnect_0_ARREGION;
- M03_AXI_arsize <= m03_couplers_to_axi_interconnect_0_ARSIZE;
+ M03_AXI_araddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_axi_interconnect_0_ARVALID;
- M03_AXI_awaddr <= m03_couplers_to_axi_interconnect_0_AWADDR;
- M03_AXI_awburst <= m03_couplers_to_axi_interconnect_0_AWBURST;
- M03_AXI_awcache <= m03_couplers_to_axi_interconnect_0_AWCACHE;
- M03_AXI_awlen <= m03_couplers_to_axi_interconnect_0_AWLEN;
- M03_AXI_awlock <= m03_couplers_to_axi_interconnect_0_AWLOCK;
- M03_AXI_awprot <= m03_couplers_to_axi_interconnect_0_AWPROT;
- M03_AXI_awqos <= m03_couplers_to_axi_interconnect_0_AWQOS;
- M03_AXI_awregion <= m03_couplers_to_axi_interconnect_0_AWREGION;
- M03_AXI_awsize <= m03_couplers_to_axi_interconnect_0_AWSIZE;
+ M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_axi_interconnect_0_AWVALID;
M03_AXI_bready <= m03_couplers_to_axi_interconnect_0_BREADY;
M03_AXI_rready <= m03_couplers_to_axi_interconnect_0_RREADY;
- M03_AXI_wdata <= m03_couplers_to_axi_interconnect_0_WDATA;
- M03_AXI_wlast <= m03_couplers_to_axi_interconnect_0_WLAST;
- M03_AXI_wstrb <= m03_couplers_to_axi_interconnect_0_WSTRB;
+ M03_AXI_wdata(31 downto 0) <= m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+ M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_axi_interconnect_0_WVALID;
+ M04_ACLK_1 <= M04_ACLK;
+ M04_ARESETN_1 <= M04_ARESETN;
+ M04_AXI_araddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+ M04_AXI_arvalid <= m04_couplers_to_axi_interconnect_0_ARVALID;
+ M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+ M04_AXI_awvalid <= m04_couplers_to_axi_interconnect_0_AWVALID;
+ M04_AXI_bready <= m04_couplers_to_axi_interconnect_0_BREADY;
+ M04_AXI_rready <= m04_couplers_to_axi_interconnect_0_RREADY;
+ M04_AXI_wdata(31 downto 0) <= m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+ M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+ M04_AXI_wvalid <= m04_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready(0) <= axi_interconnect_0_to_s00_couplers_ARREADY(0);
@@ -1104,13 +1125,20 @@ begin
m02_couplers_to_axi_interconnect_0_WREADY <= M02_AXI_wready;
m03_couplers_to_axi_interconnect_0_ARREADY <= M03_AXI_arready;
m03_couplers_to_axi_interconnect_0_AWREADY <= M03_AXI_awready;
- m03_couplers_to_axi_interconnect_0_BRESP <= M03_AXI_bresp;
+ m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_BVALID <= M03_AXI_bvalid;
- m03_couplers_to_axi_interconnect_0_RDATA <= M03_AXI_rdata;
- m03_couplers_to_axi_interconnect_0_RLAST <= M03_AXI_rlast;
- m03_couplers_to_axi_interconnect_0_RRESP <= M03_AXI_rresp;
+ m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
+ m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_RVALID <= M03_AXI_rvalid;
m03_couplers_to_axi_interconnect_0_WREADY <= M03_AXI_wready;
+ m04_couplers_to_axi_interconnect_0_ARREADY <= M04_AXI_arready;
+ m04_couplers_to_axi_interconnect_0_AWREADY <= M04_AXI_awready;
+ m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
+ m04_couplers_to_axi_interconnect_0_BVALID <= M04_AXI_bvalid;
+ m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
+ m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
+ m04_couplers_to_axi_interconnect_0_RVALID <= M04_AXI_rvalid;
+ m04_couplers_to_axi_interconnect_0_WREADY <= M04_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_L30N86
port map (
M_ACLK => M00_ACLK_1,
@@ -1238,79 +1266,84 @@ m03_couplers: entity work.m03_couplers_imp_DKAE7P
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
- M_AXI_araddr => m03_couplers_to_axi_interconnect_0_ARADDR,
- M_AXI_arburst => m03_couplers_to_axi_interconnect_0_ARBURST,
- M_AXI_arcache => m03_couplers_to_axi_interconnect_0_ARCACHE,
- M_AXI_arlen => m03_couplers_to_axi_interconnect_0_ARLEN,
- M_AXI_arlock => m03_couplers_to_axi_interconnect_0_ARLOCK,
- M_AXI_arprot => m03_couplers_to_axi_interconnect_0_ARPROT,
- M_AXI_arqos => m03_couplers_to_axi_interconnect_0_ARQOS,
+ M_AXI_araddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_axi_interconnect_0_ARREADY,
- M_AXI_arregion => m03_couplers_to_axi_interconnect_0_ARREGION,
- M_AXI_arsize => m03_couplers_to_axi_interconnect_0_ARSIZE,
M_AXI_arvalid => m03_couplers_to_axi_interconnect_0_ARVALID,
- M_AXI_awaddr => m03_couplers_to_axi_interconnect_0_AWADDR,
- M_AXI_awburst => m03_couplers_to_axi_interconnect_0_AWBURST,
- M_AXI_awcache => m03_couplers_to_axi_interconnect_0_AWCACHE,
- M_AXI_awlen => m03_couplers_to_axi_interconnect_0_AWLEN,
- M_AXI_awlock => m03_couplers_to_axi_interconnect_0_AWLOCK,
- M_AXI_awprot => m03_couplers_to_axi_interconnect_0_AWPROT,
- M_AXI_awqos => m03_couplers_to_axi_interconnect_0_AWQOS,
+ M_AXI_awaddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_axi_interconnect_0_AWREADY,
- M_AXI_awregion => m03_couplers_to_axi_interconnect_0_AWREGION,
- M_AXI_awsize => m03_couplers_to_axi_interconnect_0_AWSIZE,
M_AXI_awvalid => m03_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m03_couplers_to_axi_interconnect_0_BREADY,
- M_AXI_bresp => m03_couplers_to_axi_interconnect_0_BRESP,
+ M_AXI_bresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_axi_interconnect_0_BVALID,
- M_AXI_rdata => m03_couplers_to_axi_interconnect_0_RDATA,
- M_AXI_rlast => m03_couplers_to_axi_interconnect_0_RLAST,
+ M_AXI_rdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_axi_interconnect_0_RREADY,
- M_AXI_rresp => m03_couplers_to_axi_interconnect_0_RRESP,
+ M_AXI_rresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_axi_interconnect_0_RVALID,
- M_AXI_wdata => m03_couplers_to_axi_interconnect_0_WDATA,
- M_AXI_wlast => m03_couplers_to_axi_interconnect_0_WLAST,
+ M_AXI_wdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_axi_interconnect_0_WREADY,
- M_AXI_wstrb => m03_couplers_to_axi_interconnect_0_WSTRB,
+ M_AXI_wstrb(3 downto 0) => m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
- S_AXI_araddr => xbar_to_m03_couplers_ARADDR(96),
- S_AXI_arburst => '0',
- S_AXI_arcache => '0',
- S_AXI_arlen => '0',
- S_AXI_arlock => '0',
- S_AXI_arprot => xbar_to_m03_couplers_ARPROT(9),
- S_AXI_arqos => '0',
+ S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
- S_AXI_arregion => '0',
- S_AXI_arsize => '0',
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
- S_AXI_awaddr => xbar_to_m03_couplers_AWADDR(96),
- S_AXI_awburst => '0',
- S_AXI_awcache => '0',
- S_AXI_awlen => '0',
- S_AXI_awlock => '0',
- S_AXI_awprot => xbar_to_m03_couplers_AWPROT(9),
- S_AXI_awqos => '0',
+ S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
- S_AXI_awregion => '0',
- S_AXI_awsize => '0',
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
- S_AXI_bresp => xbar_to_m03_couplers_BRESP,
+ S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
- S_AXI_rdata => xbar_to_m03_couplers_RDATA,
- S_AXI_rlast => NLW_m03_couplers_S_AXI_rlast_UNCONNECTED,
+ S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
- S_AXI_rresp => xbar_to_m03_couplers_RRESP,
+ S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
- S_AXI_wdata => xbar_to_m03_couplers_WDATA(96),
- S_AXI_wlast => '0',
+ S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
- S_AXI_wstrb => xbar_to_m03_couplers_WSTRB(12),
+ S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
+m04_couplers: entity work.m04_couplers_imp_OP7ZFX
+ port map (
+ M_ACLK => M04_ACLK_1,
+ M_ARESETN => M04_ARESETN_1,
+ M_AXI_araddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+ M_AXI_arready => m04_couplers_to_axi_interconnect_0_ARREADY,
+ M_AXI_arvalid => m04_couplers_to_axi_interconnect_0_ARVALID,
+ M_AXI_awaddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+ M_AXI_awready => m04_couplers_to_axi_interconnect_0_AWREADY,
+ M_AXI_awvalid => m04_couplers_to_axi_interconnect_0_AWVALID,
+ M_AXI_bready => m04_couplers_to_axi_interconnect_0_BREADY,
+ M_AXI_bresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+ M_AXI_bvalid => m04_couplers_to_axi_interconnect_0_BVALID,
+ M_AXI_rdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+ M_AXI_rready => m04_couplers_to_axi_interconnect_0_RREADY,
+ M_AXI_rresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+ M_AXI_rvalid => m04_couplers_to_axi_interconnect_0_RVALID,
+ M_AXI_wdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+ M_AXI_wready => m04_couplers_to_axi_interconnect_0_WREADY,
+ M_AXI_wstrb(3 downto 0) => m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+ M_AXI_wvalid => m04_couplers_to_axi_interconnect_0_WVALID,
+ S_ACLK => axi_interconnect_0_ACLK_net,
+ S_ARESETN => axi_interconnect_0_ARESETN_net,
+ S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
+ S_AXI_arready => xbar_to_m04_couplers_ARREADY,
+ S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
+ S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
+ S_AXI_awready => xbar_to_m04_couplers_AWREADY,
+ S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
+ S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
+ S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
+ S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
+ S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
+ S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
+ S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
+ S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
+ S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
+ S_AXI_wready => xbar_to_m04_couplers_WREADY,
+ S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
+ S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
+ );
s00_couplers: entity work.s00_couplers_imp_1AM08ZQ
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
@@ -1360,107 +1393,89 @@ xbar: component mb_design_1_xbar_0
port map (
aclk => axi_interconnect_0_ACLK_net,
aresetn => axi_interconnect_0_ARESETN_net,
+ m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
- m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
- m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0),
+ m_axi_arprot(14 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(14 downto 0),
+ m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
+ m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
+ m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
- m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
- m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0),
+ m_axi_awprot(14 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(14 downto 0),
+ m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
+ m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
+ m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
- m_axi_bresp(7) => xbar_to_m03_couplers_BRESP,
- m_axi_bresp(6) => xbar_to_m03_couplers_BRESP,
+ m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
+ m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
+ m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
- m_axi_rdata(127) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(126) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(125) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(124) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(123) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(122) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(121) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(120) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(119) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(118) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(117) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(116) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(115) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(114) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(113) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(112) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(111) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(110) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(109) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(108) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(107) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(106) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(105) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(104) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(103) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(102) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(101) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(100) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(99) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(98) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(97) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(96) => xbar_to_m03_couplers_RDATA,
+ m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
+ m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
+ m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
- m_axi_rresp(7) => xbar_to_m03_couplers_RRESP,
- m_axi_rresp(6) => xbar_to_m03_couplers_RRESP,
+ m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
+ m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
+ m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
+ m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
+ m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
+ m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
+ m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
@@ -1494,10 +1509,14 @@ entity mb_design_1 is
port (
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk_in1 : in STD_LOGIC;
+ hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=20,numReposBlks=14,numNonXlnxBlks=0,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
+ attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=15,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of mb_design_1 : entity is "mb_design_1.hwdef";
end mb_design_1;
@@ -1563,8 +1582,8 @@ architecture STRUCTURE of mb_design_1 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
- locked : out STD_LOGIC;
- clk_100mhz : out STD_LOGIC
+ clk_100mhz : out STD_LOGIC;
+ locked : out STD_LOGIC
);
end component mb_design_1_clk_wiz_0_0;
component mb_design_1_proc_sys_reset_0_0 is
@@ -1826,6 +1845,33 @@ architecture STRUCTURE of mb_design_1 is
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mb_design_1_xlconcat_0_0;
+ component mb_design_1_axi4lite_hog_build_i_0_0 is
+ port (
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+ end component mb_design_1_axi4lite_hog_build_i_0_0;
signal Conn1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_ADDRSTROBE : STD_LOGIC;
signal Conn1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
@@ -1920,6 +1966,40 @@ architecture STRUCTURE of mb_design_1 is
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_timer_0_interrupt : STD_LOGIC;
signal clk_in1_0_1 : STD_LOGIC;
signal clk_wiz_0_clk_100mhz : STD_LOGIC;
@@ -1931,6 +2011,10 @@ architecture STRUCTURE of mb_design_1 is
signal dlmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
+ signal hog_global_date_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal hog_global_sha_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal hog_global_time_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal hog_global_ver_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
@@ -1973,43 +2057,9 @@ architecture STRUCTURE of mb_design_1 is
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal reset_0_1 : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_axi_interconnect_0_M03_AXI_araddr_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arburst_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arcache_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arlen_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arlock_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arprot_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arqos_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arregion_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arsize_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awaddr_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awburst_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awcache_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awlen_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awlock_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awprot_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awqos_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awregion_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awsize_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_bready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_rready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wdata_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wlast_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wstrb_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_arready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_awready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_wready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_axi_timer_0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_axi_timer_0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
@@ -2034,7 +2084,37 @@ architecture STRUCTURE of mb_design_1 is
begin
GPIO_0_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
clk_in1_0_1 <= clk_in1;
+ hog_global_date_i_0_1(31 downto 0) <= hog_global_date_i_0(31 downto 0);
+ hog_global_sha_i_0_1(31 downto 0) <= hog_global_sha_i_0(31 downto 0);
+ hog_global_time_i_0_1(31 downto 0) <= hog_global_time_i_0(31 downto 0);
+ hog_global_ver_i_0_1(31 downto 0) <= hog_global_ver_i_0(31 downto 0);
reset_0_1 <= reset;
+axi4lite_hog_build_i_0: component mb_design_1_axi4lite_hog_build_i_0_0
+ port map (
+ hog_global_date_i(31 downto 0) => hog_global_date_i_0_1(31 downto 0),
+ hog_global_sha_i(31 downto 0) => hog_global_sha_i_0_1(31 downto 0),
+ hog_global_time_i(31 downto 0) => hog_global_time_i_0_1(31 downto 0),
+ hog_global_ver_i(31 downto 0) => hog_global_ver_i_0_1(31 downto 0),
+ s_axi_aclk => clk_wiz_0_clk_100mhz,
+ s_axi_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+ s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+ s_axi_arready => axi_interconnect_0_M04_AXI_ARREADY,
+ s_axi_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+ s_axi_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+ s_axi_awready => axi_interconnect_0_M04_AXI_AWREADY,
+ s_axi_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+ s_axi_bready => axi_interconnect_0_M04_AXI_BREADY,
+ s_axi_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+ s_axi_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+ s_axi_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+ s_axi_rready => axi_interconnect_0_M04_AXI_RREADY,
+ s_axi_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+ s_axi_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+ s_axi_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+ s_axi_wready => axi_interconnect_0_M04_AXI_WREADY,
+ s_axi_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+ s_axi_wvalid => axi_interconnect_0_M04_AXI_WVALID
+ );
axi_gpio_0: component mb_design_1_axi_gpio_0_0
port map (
gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
@@ -2063,24 +2143,24 @@ axi_intc_0: component mb_design_1_axi_intc_0_0
intr(0) => xlconcat_0_dout(0),
irq => axi_intc_0_interrupt_INTERRUPT,
s_axi_aclk => clk_wiz_0_clk_100mhz,
- s_axi_araddr(8 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(8 downto 0),
+ s_axi_araddr(8 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(8 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
- s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
- s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
- s_axi_awaddr(8 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(8 downto 0),
- s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
- s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
- s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
- s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
- s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
- s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
- s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
- s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
- s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
- s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
- s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
- s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
- s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
+ s_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
+ s_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+ s_axi_awaddr(8 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(8 downto 0),
+ s_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
+ s_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+ s_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
+ s_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+ s_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+ s_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+ s_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
+ s_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+ s_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+ s_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+ s_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
+ s_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+ s_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
port map (
@@ -2145,41 +2225,42 @@ axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_100mhz,
M03_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
- M03_AXI_araddr => NLW_axi_interconnect_0_M03_AXI_araddr_UNCONNECTED,
- M03_AXI_arburst => NLW_axi_interconnect_0_M03_AXI_arburst_UNCONNECTED,
- M03_AXI_arcache => NLW_axi_interconnect_0_M03_AXI_arcache_UNCONNECTED,
- M03_AXI_arlen => NLW_axi_interconnect_0_M03_AXI_arlen_UNCONNECTED,
- M03_AXI_arlock => NLW_axi_interconnect_0_M03_AXI_arlock_UNCONNECTED,
- M03_AXI_arprot => NLW_axi_interconnect_0_M03_AXI_arprot_UNCONNECTED,
- M03_AXI_arqos => NLW_axi_interconnect_0_M03_AXI_arqos_UNCONNECTED,
- M03_AXI_arready => '0',
- M03_AXI_arregion => NLW_axi_interconnect_0_M03_AXI_arregion_UNCONNECTED,
- M03_AXI_arsize => NLW_axi_interconnect_0_M03_AXI_arsize_UNCONNECTED,
- M03_AXI_arvalid => NLW_axi_interconnect_0_M03_AXI_arvalid_UNCONNECTED,
- M03_AXI_awaddr => NLW_axi_interconnect_0_M03_AXI_awaddr_UNCONNECTED,
- M03_AXI_awburst => NLW_axi_interconnect_0_M03_AXI_awburst_UNCONNECTED,
- M03_AXI_awcache => NLW_axi_interconnect_0_M03_AXI_awcache_UNCONNECTED,
- M03_AXI_awlen => NLW_axi_interconnect_0_M03_AXI_awlen_UNCONNECTED,
- M03_AXI_awlock => NLW_axi_interconnect_0_M03_AXI_awlock_UNCONNECTED,
- M03_AXI_awprot => NLW_axi_interconnect_0_M03_AXI_awprot_UNCONNECTED,
- M03_AXI_awqos => NLW_axi_interconnect_0_M03_AXI_awqos_UNCONNECTED,
- M03_AXI_awready => '0',
- M03_AXI_awregion => NLW_axi_interconnect_0_M03_AXI_awregion_UNCONNECTED,
- M03_AXI_awsize => NLW_axi_interconnect_0_M03_AXI_awsize_UNCONNECTED,
- M03_AXI_awvalid => NLW_axi_interconnect_0_M03_AXI_awvalid_UNCONNECTED,
- M03_AXI_bready => NLW_axi_interconnect_0_M03_AXI_bready_UNCONNECTED,
- M03_AXI_bresp => '0',
- M03_AXI_bvalid => '0',
- M03_AXI_rdata => '0',
- M03_AXI_rlast => '0',
- M03_AXI_rready => NLW_axi_interconnect_0_M03_AXI_rready_UNCONNECTED,
- M03_AXI_rresp => '0',
- M03_AXI_rvalid => '0',
- M03_AXI_wdata => NLW_axi_interconnect_0_M03_AXI_wdata_UNCONNECTED,
- M03_AXI_wlast => NLW_axi_interconnect_0_M03_AXI_wlast_UNCONNECTED,
- M03_AXI_wready => '0',
- M03_AXI_wstrb => NLW_axi_interconnect_0_M03_AXI_wstrb_UNCONNECTED,
- M03_AXI_wvalid => NLW_axi_interconnect_0_M03_AXI_wvalid_UNCONNECTED,
+ M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
+ M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
+ M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+ M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
+ M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
+ M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+ M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
+ M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+ M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+ M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+ M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
+ M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+ M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+ M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+ M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
+ M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+ M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
+ M04_ACLK => clk_wiz_0_clk_100mhz,
+ M04_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+ M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+ M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
+ M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+ M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+ M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
+ M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+ M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
+ M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+ M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+ M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+ M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
+ M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+ M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+ M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+ M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
+ M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+ M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_100mhz,
S00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
@@ -2212,24 +2293,24 @@ axi_timer_0: component mb_design_1_axi_timer_0_0
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => clk_wiz_0_clk_100mhz,
- s_axi_araddr(4 downto 0) => B"00000",
+ s_axi_araddr(4 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(4 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
- s_axi_arready => NLW_axi_timer_0_s_axi_arready_UNCONNECTED,
- s_axi_arvalid => '0',
- s_axi_awaddr(4 downto 0) => B"00000",
- s_axi_awready => NLW_axi_timer_0_s_axi_awready_UNCONNECTED,
- s_axi_awvalid => '0',
- s_axi_bready => '0',
- s_axi_bresp(1 downto 0) => NLW_axi_timer_0_s_axi_bresp_UNCONNECTED(1 downto 0),
- s_axi_bvalid => NLW_axi_timer_0_s_axi_bvalid_UNCONNECTED,
- s_axi_rdata(31 downto 0) => NLW_axi_timer_0_s_axi_rdata_UNCONNECTED(31 downto 0),
- s_axi_rready => '0',
- s_axi_rresp(1 downto 0) => NLW_axi_timer_0_s_axi_rresp_UNCONNECTED(1 downto 0),
- s_axi_rvalid => NLW_axi_timer_0_s_axi_rvalid_UNCONNECTED,
- s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
- s_axi_wready => NLW_axi_timer_0_s_axi_wready_UNCONNECTED,
- s_axi_wstrb(3 downto 0) => B"1111",
- s_axi_wvalid => '0'
+ s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
+ s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
+ s_axi_awaddr(4 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(4 downto 0),
+ s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
+ s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
+ s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
+ s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
+ s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
+ s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
+ s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
+ s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
+ s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
+ s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
+ s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
+ s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
+ s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
blk_mem_gen_0: component mb_design_1_blk_mem_gen_0_0
port map (
diff --git a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
index 56a9211ca1cc9b2b520f090a3a5d5b3780d58953..0dd7f56ac3047c33fcae4003b781f6084ff10a13 100644
--- a/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
+++ b/microblaze-demo/microblaze-demo.gen/sources_1/bd/mb_design_1/synth/mb_design_1.vhd
@@ -2,7 +2,7 @@
--Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep 5 14:36:28 MDT 2024
---Date : Tue Mar 4 22:34:13 2025
+--Date : Thu Mar 20 16:44:45 2025
--Host : hogtest running 64-bit unknown
--Command : generate_target mb_design_1.bd
--Design : mb_design_1
@@ -319,193 +319,204 @@ entity m03_couplers_imp_DKAE7P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
- M_AXI_araddr : out STD_LOGIC;
- M_AXI_arburst : out STD_LOGIC;
- M_AXI_arcache : out STD_LOGIC;
- M_AXI_arlen : out STD_LOGIC;
- M_AXI_arlock : out STD_LOGIC;
- M_AXI_arprot : out STD_LOGIC;
- M_AXI_arqos : out STD_LOGIC;
+ M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
- M_AXI_arregion : out STD_LOGIC;
- M_AXI_arsize : out STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
- M_AXI_awaddr : out STD_LOGIC;
- M_AXI_awburst : out STD_LOGIC;
- M_AXI_awcache : out STD_LOGIC;
- M_AXI_awlen : out STD_LOGIC;
- M_AXI_awlock : out STD_LOGIC;
- M_AXI_awprot : out STD_LOGIC;
- M_AXI_awqos : out STD_LOGIC;
+ M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
- M_AXI_awregion : out STD_LOGIC;
- M_AXI_awsize : out STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
- M_AXI_bresp : in STD_LOGIC;
+ M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
- M_AXI_rdata : in STD_LOGIC;
- M_AXI_rlast : in STD_LOGIC;
+ M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
- M_AXI_rresp : in STD_LOGIC;
+ M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
- M_AXI_wdata : out STD_LOGIC;
- M_AXI_wlast : out STD_LOGIC;
+ M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
- M_AXI_wstrb : out STD_LOGIC;
+ M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
- S_AXI_araddr : in STD_LOGIC;
- S_AXI_arburst : in STD_LOGIC;
- S_AXI_arcache : in STD_LOGIC;
- S_AXI_arlen : in STD_LOGIC;
- S_AXI_arlock : in STD_LOGIC;
- S_AXI_arprot : in STD_LOGIC;
- S_AXI_arqos : in STD_LOGIC;
+ S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
- S_AXI_arregion : in STD_LOGIC;
- S_AXI_arsize : in STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
- S_AXI_awaddr : in STD_LOGIC;
- S_AXI_awburst : in STD_LOGIC;
- S_AXI_awcache : in STD_LOGIC;
- S_AXI_awlen : in STD_LOGIC;
- S_AXI_awlock : in STD_LOGIC;
- S_AXI_awprot : in STD_LOGIC;
- S_AXI_awqos : in STD_LOGIC;
+ S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
- S_AXI_awregion : in STD_LOGIC;
- S_AXI_awsize : in STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
- S_AXI_bresp : out STD_LOGIC;
+ S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
- S_AXI_rdata : out STD_LOGIC;
- S_AXI_rlast : out STD_LOGIC;
+ S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
- S_AXI_rresp : out STD_LOGIC;
+ S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
- S_AXI_wdata : in STD_LOGIC;
- S_AXI_wlast : in STD_LOGIC;
+ S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
- S_AXI_wstrb : in STD_LOGIC;
+ S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_DKAE7P;
architecture STRUCTURE of m03_couplers_imp_DKAE7P is
- signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARBURST : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARCACHE : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARLEN : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARLOCK : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARPROT : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARQOS : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARREGION : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_ARSIZE : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWBURST : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWCACHE : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWLEN : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWLOCK : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWPROT : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWQOS : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWREGION : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_AWSIZE : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_RLAST : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_WLAST : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
- signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC;
+ signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
- M_AXI_araddr <= m03_couplers_to_m03_couplers_ARADDR;
- M_AXI_arburst <= m03_couplers_to_m03_couplers_ARBURST;
- M_AXI_arcache <= m03_couplers_to_m03_couplers_ARCACHE;
- M_AXI_arlen <= m03_couplers_to_m03_couplers_ARLEN;
- M_AXI_arlock <= m03_couplers_to_m03_couplers_ARLOCK;
- M_AXI_arprot <= m03_couplers_to_m03_couplers_ARPROT;
- M_AXI_arqos <= m03_couplers_to_m03_couplers_ARQOS;
- M_AXI_arregion <= m03_couplers_to_m03_couplers_ARREGION;
- M_AXI_arsize <= m03_couplers_to_m03_couplers_ARSIZE;
+ M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
- M_AXI_awaddr <= m03_couplers_to_m03_couplers_AWADDR;
- M_AXI_awburst <= m03_couplers_to_m03_couplers_AWBURST;
- M_AXI_awcache <= m03_couplers_to_m03_couplers_AWCACHE;
- M_AXI_awlen <= m03_couplers_to_m03_couplers_AWLEN;
- M_AXI_awlock <= m03_couplers_to_m03_couplers_AWLOCK;
- M_AXI_awprot <= m03_couplers_to_m03_couplers_AWPROT;
- M_AXI_awqos <= m03_couplers_to_m03_couplers_AWQOS;
- M_AXI_awregion <= m03_couplers_to_m03_couplers_AWREGION;
- M_AXI_awsize <= m03_couplers_to_m03_couplers_AWSIZE;
+ M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
- M_AXI_wdata <= m03_couplers_to_m03_couplers_WDATA;
- M_AXI_wlast <= m03_couplers_to_m03_couplers_WLAST;
- M_AXI_wstrb <= m03_couplers_to_m03_couplers_WSTRB;
+ M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
+ M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
- S_AXI_bresp <= m03_couplers_to_m03_couplers_BRESP;
+ S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
- S_AXI_rdata <= m03_couplers_to_m03_couplers_RDATA;
- S_AXI_rlast <= m03_couplers_to_m03_couplers_RLAST;
- S_AXI_rresp <= m03_couplers_to_m03_couplers_RRESP;
+ S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
+ S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
- m03_couplers_to_m03_couplers_ARADDR <= S_AXI_araddr;
- m03_couplers_to_m03_couplers_ARBURST <= S_AXI_arburst;
- m03_couplers_to_m03_couplers_ARCACHE <= S_AXI_arcache;
- m03_couplers_to_m03_couplers_ARLEN <= S_AXI_arlen;
- m03_couplers_to_m03_couplers_ARLOCK <= S_AXI_arlock;
- m03_couplers_to_m03_couplers_ARPROT <= S_AXI_arprot;
- m03_couplers_to_m03_couplers_ARQOS <= S_AXI_arqos;
+ m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
- m03_couplers_to_m03_couplers_ARREGION <= S_AXI_arregion;
- m03_couplers_to_m03_couplers_ARSIZE <= S_AXI_arsize;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
- m03_couplers_to_m03_couplers_AWADDR <= S_AXI_awaddr;
- m03_couplers_to_m03_couplers_AWBURST <= S_AXI_awburst;
- m03_couplers_to_m03_couplers_AWCACHE <= S_AXI_awcache;
- m03_couplers_to_m03_couplers_AWLEN <= S_AXI_awlen;
- m03_couplers_to_m03_couplers_AWLOCK <= S_AXI_awlock;
- m03_couplers_to_m03_couplers_AWPROT <= S_AXI_awprot;
- m03_couplers_to_m03_couplers_AWQOS <= S_AXI_awqos;
+ m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
- m03_couplers_to_m03_couplers_AWREGION <= S_AXI_awregion;
- m03_couplers_to_m03_couplers_AWSIZE <= S_AXI_awsize;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
- m03_couplers_to_m03_couplers_BRESP <= M_AXI_bresp;
+ m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
- m03_couplers_to_m03_couplers_RDATA <= M_AXI_rdata;
- m03_couplers_to_m03_couplers_RLAST <= M_AXI_rlast;
+ m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
- m03_couplers_to_m03_couplers_RRESP <= M_AXI_rresp;
+ m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
- m03_couplers_to_m03_couplers_WDATA <= S_AXI_wdata;
- m03_couplers_to_m03_couplers_WLAST <= S_AXI_wlast;
+ m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
- m03_couplers_to_m03_couplers_WSTRB <= S_AXI_wstrb;
+ m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
+entity m04_couplers_imp_OP7ZFX is
+ port (
+ M_ACLK : in STD_LOGIC;
+ M_ARESETN : in STD_LOGIC;
+ M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_arready : in STD_LOGIC;
+ M_AXI_arvalid : out STD_LOGIC;
+ M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_awready : in STD_LOGIC;
+ M_AXI_awvalid : out STD_LOGIC;
+ M_AXI_bready : out STD_LOGIC;
+ M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_bvalid : in STD_LOGIC;
+ M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_rready : out STD_LOGIC;
+ M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M_AXI_rvalid : in STD_LOGIC;
+ M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M_AXI_wready : in STD_LOGIC;
+ M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M_AXI_wvalid : out STD_LOGIC;
+ S_ACLK : in STD_LOGIC;
+ S_ARESETN : in STD_LOGIC;
+ S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_arready : out STD_LOGIC;
+ S_AXI_arvalid : in STD_LOGIC;
+ S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_awready : out STD_LOGIC;
+ S_AXI_awvalid : in STD_LOGIC;
+ S_AXI_bready : in STD_LOGIC;
+ S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_bvalid : out STD_LOGIC;
+ S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_rready : in STD_LOGIC;
+ S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ S_AXI_rvalid : out STD_LOGIC;
+ S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ S_AXI_wready : out STD_LOGIC;
+ S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ S_AXI_wvalid : in STD_LOGIC
+ );
+end m04_couplers_imp_OP7ZFX;
+
+architecture STRUCTURE of m04_couplers_imp_OP7ZFX is
+ signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
+ signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
+begin
+ M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
+ M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
+ M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
+ M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
+ M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
+ M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
+ M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
+ M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
+ M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
+ S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
+ S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
+ S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
+ S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
+ S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
+ S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
+ S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
+ S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
+ m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
+ m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
+ m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
+ m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
+ m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
+ m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
+ m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
+ m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
+ m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
+ m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
+ m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
+ m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
+ m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
+ m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
+ m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
+ m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
+ m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1AM08ZQ is
port (
M_ACLK : in STD_LOGIC;
@@ -680,41 +691,42 @@ entity mb_design_1_axi_interconnect_0_0 is
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
- M03_AXI_araddr : out STD_LOGIC;
- M03_AXI_arburst : out STD_LOGIC;
- M03_AXI_arcache : out STD_LOGIC;
- M03_AXI_arlen : out STD_LOGIC;
- M03_AXI_arlock : out STD_LOGIC;
- M03_AXI_arprot : out STD_LOGIC;
- M03_AXI_arqos : out STD_LOGIC;
+ M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
- M03_AXI_arregion : out STD_LOGIC;
- M03_AXI_arsize : out STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
- M03_AXI_awaddr : out STD_LOGIC;
- M03_AXI_awburst : out STD_LOGIC;
- M03_AXI_awcache : out STD_LOGIC;
- M03_AXI_awlen : out STD_LOGIC;
- M03_AXI_awlock : out STD_LOGIC;
- M03_AXI_awprot : out STD_LOGIC;
- M03_AXI_awqos : out STD_LOGIC;
+ M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
- M03_AXI_awregion : out STD_LOGIC;
- M03_AXI_awsize : out STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
- M03_AXI_bresp : in STD_LOGIC;
+ M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
- M03_AXI_rdata : in STD_LOGIC;
- M03_AXI_rlast : in STD_LOGIC;
+ M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
- M03_AXI_rresp : in STD_LOGIC;
+ M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
- M03_AXI_wdata : out STD_LOGIC;
- M03_AXI_wlast : out STD_LOGIC;
+ M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
- M03_AXI_wstrb : out STD_LOGIC;
+ M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
+ M04_ACLK : in STD_LOGIC;
+ M04_ARESETN : in STD_LOGIC;
+ M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_arready : in STD_LOGIC;
+ M04_AXI_arvalid : out STD_LOGIC;
+ M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_awready : in STD_LOGIC;
+ M04_AXI_awvalid : out STD_LOGIC;
+ M04_AXI_bready : out STD_LOGIC;
+ M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M04_AXI_bvalid : in STD_LOGIC;
+ M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_rready : out STD_LOGIC;
+ M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ M04_AXI_rvalid : in STD_LOGIC;
+ M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ M04_AXI_wready : in STD_LOGIC;
+ M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
+ M04_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -763,25 +775,25 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
- m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
- m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
- m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
- m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
- m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
- m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
+ m_axi_awaddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_awprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_awvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_awready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_wstrb : out STD_LOGIC_VECTOR ( 19 downto 0 );
+ m_axi_wvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_wready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_bvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_bready : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_araddr : out STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_arprot : out STD_LOGIC_VECTOR ( 14 downto 0 );
+ m_axi_arvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_arready : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
+ m_axi_rresp : in STD_LOGIC_VECTOR ( 9 downto 0 );
+ m_axi_rvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
+ m_axi_rready : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component mb_design_1_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
@@ -792,6 +804,8 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
+ signal M04_ACLK_1 : STD_LOGIC;
+ signal M04_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
@@ -866,41 +880,40 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
signal m02_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m02_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARBURST : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARCACHE : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARLEN : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARLOCK : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARQOS : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARREGION : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_ARSIZE : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWBURST : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWCACHE : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWLEN : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWLOCK : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWQOS : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWREGION : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_AWSIZE : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m03_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_RLAST : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_WLAST : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
- signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC;
+ signal m03_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
+ signal m04_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal m04_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
@@ -972,27 +985,41 @@ architecture STRUCTURE of mb_design_1_axi_interconnect_0_0 is
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
- signal xbar_to_m03_couplers_ARPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
- signal xbar_to_m03_couplers_AWPROT : STD_LOGIC_VECTOR ( 11 downto 9 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
- signal xbar_to_m03_couplers_BRESP : STD_LOGIC;
+ signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
- signal xbar_to_m03_couplers_RDATA : STD_LOGIC;
+ signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
- signal xbar_to_m03_couplers_RRESP : STD_LOGIC;
+ signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
- signal NLW_m03_couplers_S_AXI_rlast_UNCONNECTED : STD_LOGIC;
- signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
- signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
+ signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+ signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
+ signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
+ signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
+ signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
+ signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
+ signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
+ signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
+ signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
+ signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
+ signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
+ signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
@@ -1029,32 +1056,26 @@ begin
M02_AXI_wvalid <= m02_couplers_to_axi_interconnect_0_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
- M03_AXI_araddr <= m03_couplers_to_axi_interconnect_0_ARADDR;
- M03_AXI_arburst <= m03_couplers_to_axi_interconnect_0_ARBURST;
- M03_AXI_arcache <= m03_couplers_to_axi_interconnect_0_ARCACHE;
- M03_AXI_arlen <= m03_couplers_to_axi_interconnect_0_ARLEN;
- M03_AXI_arlock <= m03_couplers_to_axi_interconnect_0_ARLOCK;
- M03_AXI_arprot <= m03_couplers_to_axi_interconnect_0_ARPROT;
- M03_AXI_arqos <= m03_couplers_to_axi_interconnect_0_ARQOS;
- M03_AXI_arregion <= m03_couplers_to_axi_interconnect_0_ARREGION;
- M03_AXI_arsize <= m03_couplers_to_axi_interconnect_0_ARSIZE;
+ M03_AXI_araddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_axi_interconnect_0_ARVALID;
- M03_AXI_awaddr <= m03_couplers_to_axi_interconnect_0_AWADDR;
- M03_AXI_awburst <= m03_couplers_to_axi_interconnect_0_AWBURST;
- M03_AXI_awcache <= m03_couplers_to_axi_interconnect_0_AWCACHE;
- M03_AXI_awlen <= m03_couplers_to_axi_interconnect_0_AWLEN;
- M03_AXI_awlock <= m03_couplers_to_axi_interconnect_0_AWLOCK;
- M03_AXI_awprot <= m03_couplers_to_axi_interconnect_0_AWPROT;
- M03_AXI_awqos <= m03_couplers_to_axi_interconnect_0_AWQOS;
- M03_AXI_awregion <= m03_couplers_to_axi_interconnect_0_AWREGION;
- M03_AXI_awsize <= m03_couplers_to_axi_interconnect_0_AWSIZE;
+ M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_axi_interconnect_0_AWVALID;
M03_AXI_bready <= m03_couplers_to_axi_interconnect_0_BREADY;
M03_AXI_rready <= m03_couplers_to_axi_interconnect_0_RREADY;
- M03_AXI_wdata <= m03_couplers_to_axi_interconnect_0_WDATA;
- M03_AXI_wlast <= m03_couplers_to_axi_interconnect_0_WLAST;
- M03_AXI_wstrb <= m03_couplers_to_axi_interconnect_0_WSTRB;
+ M03_AXI_wdata(31 downto 0) <= m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+ M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_axi_interconnect_0_WVALID;
+ M04_ACLK_1 <= M04_ACLK;
+ M04_ARESETN_1 <= M04_ARESETN;
+ M04_AXI_araddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0);
+ M04_AXI_arvalid <= m04_couplers_to_axi_interconnect_0_ARVALID;
+ M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0);
+ M04_AXI_awvalid <= m04_couplers_to_axi_interconnect_0_AWVALID;
+ M04_AXI_bready <= m04_couplers_to_axi_interconnect_0_BREADY;
+ M04_AXI_rready <= m04_couplers_to_axi_interconnect_0_RREADY;
+ M04_AXI_wdata(31 downto 0) <= m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
+ M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
+ M04_AXI_wvalid <= m04_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready(0) <= axi_interconnect_0_to_s00_couplers_ARREADY(0);
@@ -1104,13 +1125,20 @@ begin
m02_couplers_to_axi_interconnect_0_WREADY <= M02_AXI_wready;
m03_couplers_to_axi_interconnect_0_ARREADY <= M03_AXI_arready;
m03_couplers_to_axi_interconnect_0_AWREADY <= M03_AXI_awready;
- m03_couplers_to_axi_interconnect_0_BRESP <= M03_AXI_bresp;
+ m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_BVALID <= M03_AXI_bvalid;
- m03_couplers_to_axi_interconnect_0_RDATA <= M03_AXI_rdata;
- m03_couplers_to_axi_interconnect_0_RLAST <= M03_AXI_rlast;
- m03_couplers_to_axi_interconnect_0_RRESP <= M03_AXI_rresp;
+ m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
+ m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_axi_interconnect_0_RVALID <= M03_AXI_rvalid;
m03_couplers_to_axi_interconnect_0_WREADY <= M03_AXI_wready;
+ m04_couplers_to_axi_interconnect_0_ARREADY <= M04_AXI_arready;
+ m04_couplers_to_axi_interconnect_0_AWREADY <= M04_AXI_awready;
+ m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
+ m04_couplers_to_axi_interconnect_0_BVALID <= M04_AXI_bvalid;
+ m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
+ m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
+ m04_couplers_to_axi_interconnect_0_RVALID <= M04_AXI_rvalid;
+ m04_couplers_to_axi_interconnect_0_WREADY <= M04_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_L30N86
port map (
M_ACLK => M00_ACLK_1,
@@ -1238,79 +1266,84 @@ m03_couplers: entity work.m03_couplers_imp_DKAE7P
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
- M_AXI_araddr => m03_couplers_to_axi_interconnect_0_ARADDR,
- M_AXI_arburst => m03_couplers_to_axi_interconnect_0_ARBURST,
- M_AXI_arcache => m03_couplers_to_axi_interconnect_0_ARCACHE,
- M_AXI_arlen => m03_couplers_to_axi_interconnect_0_ARLEN,
- M_AXI_arlock => m03_couplers_to_axi_interconnect_0_ARLOCK,
- M_AXI_arprot => m03_couplers_to_axi_interconnect_0_ARPROT,
- M_AXI_arqos => m03_couplers_to_axi_interconnect_0_ARQOS,
+ M_AXI_araddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_axi_interconnect_0_ARREADY,
- M_AXI_arregion => m03_couplers_to_axi_interconnect_0_ARREGION,
- M_AXI_arsize => m03_couplers_to_axi_interconnect_0_ARSIZE,
M_AXI_arvalid => m03_couplers_to_axi_interconnect_0_ARVALID,
- M_AXI_awaddr => m03_couplers_to_axi_interconnect_0_AWADDR,
- M_AXI_awburst => m03_couplers_to_axi_interconnect_0_AWBURST,
- M_AXI_awcache => m03_couplers_to_axi_interconnect_0_AWCACHE,
- M_AXI_awlen => m03_couplers_to_axi_interconnect_0_AWLEN,
- M_AXI_awlock => m03_couplers_to_axi_interconnect_0_AWLOCK,
- M_AXI_awprot => m03_couplers_to_axi_interconnect_0_AWPROT,
- M_AXI_awqos => m03_couplers_to_axi_interconnect_0_AWQOS,
+ M_AXI_awaddr(31 downto 0) => m03_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_axi_interconnect_0_AWREADY,
- M_AXI_awregion => m03_couplers_to_axi_interconnect_0_AWREGION,
- M_AXI_awsize => m03_couplers_to_axi_interconnect_0_AWSIZE,
M_AXI_awvalid => m03_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m03_couplers_to_axi_interconnect_0_BREADY,
- M_AXI_bresp => m03_couplers_to_axi_interconnect_0_BRESP,
+ M_AXI_bresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_axi_interconnect_0_BVALID,
- M_AXI_rdata => m03_couplers_to_axi_interconnect_0_RDATA,
- M_AXI_rlast => m03_couplers_to_axi_interconnect_0_RLAST,
+ M_AXI_rdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_axi_interconnect_0_RREADY,
- M_AXI_rresp => m03_couplers_to_axi_interconnect_0_RRESP,
+ M_AXI_rresp(1 downto 0) => m03_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_axi_interconnect_0_RVALID,
- M_AXI_wdata => m03_couplers_to_axi_interconnect_0_WDATA,
- M_AXI_wlast => m03_couplers_to_axi_interconnect_0_WLAST,
+ M_AXI_wdata(31 downto 0) => m03_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_axi_interconnect_0_WREADY,
- M_AXI_wstrb => m03_couplers_to_axi_interconnect_0_WSTRB,
+ M_AXI_wstrb(3 downto 0) => m03_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN => axi_interconnect_0_ARESETN_net,
- S_AXI_araddr => xbar_to_m03_couplers_ARADDR(96),
- S_AXI_arburst => '0',
- S_AXI_arcache => '0',
- S_AXI_arlen => '0',
- S_AXI_arlock => '0',
- S_AXI_arprot => xbar_to_m03_couplers_ARPROT(9),
- S_AXI_arqos => '0',
+ S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
- S_AXI_arregion => '0',
- S_AXI_arsize => '0',
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
- S_AXI_awaddr => xbar_to_m03_couplers_AWADDR(96),
- S_AXI_awburst => '0',
- S_AXI_awcache => '0',
- S_AXI_awlen => '0',
- S_AXI_awlock => '0',
- S_AXI_awprot => xbar_to_m03_couplers_AWPROT(9),
- S_AXI_awqos => '0',
+ S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
- S_AXI_awregion => '0',
- S_AXI_awsize => '0',
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
- S_AXI_bresp => xbar_to_m03_couplers_BRESP,
+ S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
- S_AXI_rdata => xbar_to_m03_couplers_RDATA,
- S_AXI_rlast => NLW_m03_couplers_S_AXI_rlast_UNCONNECTED,
+ S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
- S_AXI_rresp => xbar_to_m03_couplers_RRESP,
+ S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
- S_AXI_wdata => xbar_to_m03_couplers_WDATA(96),
- S_AXI_wlast => '0',
+ S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
- S_AXI_wstrb => xbar_to_m03_couplers_WSTRB(12),
+ S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
+m04_couplers: entity work.m04_couplers_imp_OP7ZFX
+ port map (
+ M_ACLK => M04_ACLK_1,
+ M_ARESETN => M04_ARESETN_1,
+ M_AXI_araddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_ARADDR(31 downto 0),
+ M_AXI_arready => m04_couplers_to_axi_interconnect_0_ARREADY,
+ M_AXI_arvalid => m04_couplers_to_axi_interconnect_0_ARVALID,
+ M_AXI_awaddr(31 downto 0) => m04_couplers_to_axi_interconnect_0_AWADDR(31 downto 0),
+ M_AXI_awready => m04_couplers_to_axi_interconnect_0_AWREADY,
+ M_AXI_awvalid => m04_couplers_to_axi_interconnect_0_AWVALID,
+ M_AXI_bready => m04_couplers_to_axi_interconnect_0_BREADY,
+ M_AXI_bresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
+ M_AXI_bvalid => m04_couplers_to_axi_interconnect_0_BVALID,
+ M_AXI_rdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
+ M_AXI_rready => m04_couplers_to_axi_interconnect_0_RREADY,
+ M_AXI_rresp(1 downto 0) => m04_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
+ M_AXI_rvalid => m04_couplers_to_axi_interconnect_0_RVALID,
+ M_AXI_wdata(31 downto 0) => m04_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
+ M_AXI_wready => m04_couplers_to_axi_interconnect_0_WREADY,
+ M_AXI_wstrb(3 downto 0) => m04_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
+ M_AXI_wvalid => m04_couplers_to_axi_interconnect_0_WVALID,
+ S_ACLK => axi_interconnect_0_ACLK_net,
+ S_ARESETN => axi_interconnect_0_ARESETN_net,
+ S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
+ S_AXI_arready => xbar_to_m04_couplers_ARREADY,
+ S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
+ S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
+ S_AXI_awready => xbar_to_m04_couplers_AWREADY,
+ S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
+ S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
+ S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
+ S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
+ S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
+ S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
+ S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
+ S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
+ S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
+ S_AXI_wready => xbar_to_m04_couplers_WREADY,
+ S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
+ S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
+ );
s00_couplers: entity work.s00_couplers_imp_1AM08ZQ
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
@@ -1360,107 +1393,89 @@ xbar: component mb_design_1_xbar_0
port map (
aclk => axi_interconnect_0_ACLK_net,
aresetn => axi_interconnect_0_ARESETN_net,
+ m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
- m_axi_arprot(11 downto 9) => xbar_to_m03_couplers_ARPROT(11 downto 9),
- m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0),
+ m_axi_arprot(14 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(14 downto 0),
+ m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
+ m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
+ m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
- m_axi_awprot(11 downto 9) => xbar_to_m03_couplers_AWPROT(11 downto 9),
- m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0),
+ m_axi_awprot(14 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(14 downto 0),
+ m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
+ m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
+ m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
- m_axi_bresp(7) => xbar_to_m03_couplers_BRESP,
- m_axi_bresp(6) => xbar_to_m03_couplers_BRESP,
+ m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
+ m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
+ m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
- m_axi_rdata(127) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(126) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(125) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(124) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(123) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(122) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(121) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(120) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(119) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(118) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(117) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(116) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(115) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(114) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(113) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(112) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(111) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(110) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(109) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(108) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(107) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(106) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(105) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(104) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(103) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(102) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(101) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(100) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(99) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(98) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(97) => xbar_to_m03_couplers_RDATA,
- m_axi_rdata(96) => xbar_to_m03_couplers_RDATA,
+ m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
+ m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
+ m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
- m_axi_rresp(7) => xbar_to_m03_couplers_RRESP,
- m_axi_rresp(6) => xbar_to_m03_couplers_RRESP,
+ m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
+ m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
+ m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
+ m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
+ m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
+ m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
+ m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
@@ -1494,10 +1509,14 @@ entity mb_design_1 is
port (
GPIO_0_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk_in1 : in STD_LOGIC;
+ hog_global_date_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
reset : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=20,numReposBlks=14,numNonXlnxBlks=0,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
+ attribute CORE_GENERATION_INFO of mb_design_1 : entity is "mb_design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=mb_design_1,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=15,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=Hierarchical}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of mb_design_1 : entity is "mb_design_1.hwdef";
end mb_design_1;
@@ -1563,8 +1582,8 @@ architecture STRUCTURE of mb_design_1 is
port (
reset : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
- locked : out STD_LOGIC;
- clk_100mhz : out STD_LOGIC
+ clk_100mhz : out STD_LOGIC;
+ locked : out STD_LOGIC
);
end component mb_design_1_clk_wiz_0_0;
component mb_design_1_proc_sys_reset_0_0 is
@@ -1826,6 +1845,33 @@ architecture STRUCTURE of mb_design_1 is
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component mb_design_1_xlconcat_0_0;
+ component mb_design_1_axi4lite_hog_build_i_0_0 is
+ port (
+ s_axi_aclk : in STD_LOGIC;
+ s_axi_aresetn : in STD_LOGIC;
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_arready : out STD_LOGIC;
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ hog_global_date_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_time_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_ver_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ hog_global_sha_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+ );
+ end component mb_design_1_axi4lite_hog_build_i_0_0;
signal Conn1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal Conn1_ADDRSTROBE : STD_LOGIC;
signal Conn1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
@@ -1920,6 +1966,40 @@ architecture STRUCTURE of mb_design_1 is
signal axi_interconnect_0_M02_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M02_AXI_WVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_ARREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_ARVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_AWREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_AWVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_BREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M03_AXI_BVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_RREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M03_AXI_RVALID : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M03_AXI_WREADY : STD_LOGIC;
+ signal axi_interconnect_0_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal axi_interconnect_0_M03_AXI_WVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_ARREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_ARVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_AWREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_AWVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_BREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M04_AXI_BVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_RREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal axi_interconnect_0_M04_AXI_RVALID : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal axi_interconnect_0_M04_AXI_WREADY : STD_LOGIC;
+ signal axi_interconnect_0_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal axi_interconnect_0_M04_AXI_WVALID : STD_LOGIC;
signal axi_timer_0_interrupt : STD_LOGIC;
signal clk_in1_0_1 : STD_LOGIC;
signal clk_wiz_0_clk_100mhz : STD_LOGIC;
@@ -1931,6 +2011,10 @@ architecture STRUCTURE of mb_design_1 is
signal dlmb_bram_if_cntlr_0_BRAM_PORT_EN : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_RST : STD_LOGIC;
signal dlmb_bram_if_cntlr_0_BRAM_PORT_WE : STD_LOGIC_VECTOR ( 0 to 3 );
+ signal hog_global_date_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal hog_global_sha_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal hog_global_time_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal hog_global_ver_i_0_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal ilmb_bram_if_cntlr_0_BRAM_PORT_CLK : STD_LOGIC;
signal ilmb_bram_if_cntlr_0_BRAM_PORT_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
@@ -1973,43 +2057,9 @@ architecture STRUCTURE of mb_design_1 is
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal reset_0_1 : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
- signal NLW_axi_interconnect_0_M03_AXI_araddr_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arburst_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arcache_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arlen_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arlock_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arprot_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arqos_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arregion_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arsize_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_arvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awaddr_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awburst_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awcache_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awlen_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awlock_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awprot_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awqos_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awregion_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awsize_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_awvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_bready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_rready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wdata_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wlast_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wstrb_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_interconnect_0_M03_AXI_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_arready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_awready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_wready_UNCONNECTED : STD_LOGIC;
- signal NLW_axi_timer_0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
- signal NLW_axi_timer_0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal NLW_axi_timer_0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_blk_mem_gen_0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_blk_mem_gen_0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_dlmb_v10_0_LMB_Rst_UNCONNECTED : STD_LOGIC;
@@ -2034,7 +2084,37 @@ architecture STRUCTURE of mb_design_1 is
begin
GPIO_0_tri_o(7 downto 0) <= axi_gpio_0_GPIO_TRI_O(7 downto 0);
clk_in1_0_1 <= clk_in1;
+ hog_global_date_i_0_1(31 downto 0) <= hog_global_date_i_0(31 downto 0);
+ hog_global_sha_i_0_1(31 downto 0) <= hog_global_sha_i_0(31 downto 0);
+ hog_global_time_i_0_1(31 downto 0) <= hog_global_time_i_0(31 downto 0);
+ hog_global_ver_i_0_1(31 downto 0) <= hog_global_ver_i_0(31 downto 0);
reset_0_1 <= reset;
+axi4lite_hog_build_i_0: component mb_design_1_axi4lite_hog_build_i_0_0
+ port map (
+ hog_global_date_i(31 downto 0) => hog_global_date_i_0_1(31 downto 0),
+ hog_global_sha_i(31 downto 0) => hog_global_sha_i_0_1(31 downto 0),
+ hog_global_time_i(31 downto 0) => hog_global_time_i_0_1(31 downto 0),
+ hog_global_ver_i(31 downto 0) => hog_global_ver_i_0_1(31 downto 0),
+ s_axi_aclk => clk_wiz_0_clk_100mhz,
+ s_axi_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+ s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
+ s_axi_arready => axi_interconnect_0_M04_AXI_ARREADY,
+ s_axi_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+ s_axi_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+ s_axi_awready => axi_interconnect_0_M04_AXI_AWREADY,
+ s_axi_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+ s_axi_bready => axi_interconnect_0_M04_AXI_BREADY,
+ s_axi_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+ s_axi_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+ s_axi_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+ s_axi_rready => axi_interconnect_0_M04_AXI_RREADY,
+ s_axi_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+ s_axi_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+ s_axi_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+ s_axi_wready => axi_interconnect_0_M04_AXI_WREADY,
+ s_axi_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+ s_axi_wvalid => axi_interconnect_0_M04_AXI_WVALID
+ );
axi_gpio_0: component mb_design_1_axi_gpio_0_0
port map (
gpio_io_o(7 downto 0) => axi_gpio_0_GPIO_TRI_O(7 downto 0),
@@ -2063,24 +2143,24 @@ axi_intc_0: component mb_design_1_axi_intc_0_0
intr(0) => xlconcat_0_dout(0),
irq => axi_intc_0_interrupt_INTERRUPT,
s_axi_aclk => clk_wiz_0_clk_100mhz,
- s_axi_araddr(8 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(8 downto 0),
+ s_axi_araddr(8 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(8 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
- s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
- s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
- s_axi_awaddr(8 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(8 downto 0),
- s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
- s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
- s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
- s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
- s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
- s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
- s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
- s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
- s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
- s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
- s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
- s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
- s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
+ s_axi_arready => axi_interconnect_0_M03_AXI_ARREADY,
+ s_axi_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+ s_axi_awaddr(8 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(8 downto 0),
+ s_axi_awready => axi_interconnect_0_M03_AXI_AWREADY,
+ s_axi_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+ s_axi_bready => axi_interconnect_0_M03_AXI_BREADY,
+ s_axi_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+ s_axi_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+ s_axi_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+ s_axi_rready => axi_interconnect_0_M03_AXI_RREADY,
+ s_axi_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+ s_axi_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+ s_axi_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+ s_axi_wready => axi_interconnect_0_M03_AXI_WREADY,
+ s_axi_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+ s_axi_wvalid => axi_interconnect_0_M03_AXI_WVALID
);
axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
port map (
@@ -2145,41 +2225,42 @@ axi_interconnect_0: entity work.mb_design_1_axi_interconnect_0_0
M02_AXI_wvalid => axi_interconnect_0_M02_AXI_WVALID,
M03_ACLK => clk_wiz_0_clk_100mhz,
M03_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
- M03_AXI_araddr => NLW_axi_interconnect_0_M03_AXI_araddr_UNCONNECTED,
- M03_AXI_arburst => NLW_axi_interconnect_0_M03_AXI_arburst_UNCONNECTED,
- M03_AXI_arcache => NLW_axi_interconnect_0_M03_AXI_arcache_UNCONNECTED,
- M03_AXI_arlen => NLW_axi_interconnect_0_M03_AXI_arlen_UNCONNECTED,
- M03_AXI_arlock => NLW_axi_interconnect_0_M03_AXI_arlock_UNCONNECTED,
- M03_AXI_arprot => NLW_axi_interconnect_0_M03_AXI_arprot_UNCONNECTED,
- M03_AXI_arqos => NLW_axi_interconnect_0_M03_AXI_arqos_UNCONNECTED,
- M03_AXI_arready => '0',
- M03_AXI_arregion => NLW_axi_interconnect_0_M03_AXI_arregion_UNCONNECTED,
- M03_AXI_arsize => NLW_axi_interconnect_0_M03_AXI_arsize_UNCONNECTED,
- M03_AXI_arvalid => NLW_axi_interconnect_0_M03_AXI_arvalid_UNCONNECTED,
- M03_AXI_awaddr => NLW_axi_interconnect_0_M03_AXI_awaddr_UNCONNECTED,
- M03_AXI_awburst => NLW_axi_interconnect_0_M03_AXI_awburst_UNCONNECTED,
- M03_AXI_awcache => NLW_axi_interconnect_0_M03_AXI_awcache_UNCONNECTED,
- M03_AXI_awlen => NLW_axi_interconnect_0_M03_AXI_awlen_UNCONNECTED,
- M03_AXI_awlock => NLW_axi_interconnect_0_M03_AXI_awlock_UNCONNECTED,
- M03_AXI_awprot => NLW_axi_interconnect_0_M03_AXI_awprot_UNCONNECTED,
- M03_AXI_awqos => NLW_axi_interconnect_0_M03_AXI_awqos_UNCONNECTED,
- M03_AXI_awready => '0',
- M03_AXI_awregion => NLW_axi_interconnect_0_M03_AXI_awregion_UNCONNECTED,
- M03_AXI_awsize => NLW_axi_interconnect_0_M03_AXI_awsize_UNCONNECTED,
- M03_AXI_awvalid => NLW_axi_interconnect_0_M03_AXI_awvalid_UNCONNECTED,
- M03_AXI_bready => NLW_axi_interconnect_0_M03_AXI_bready_UNCONNECTED,
- M03_AXI_bresp => '0',
- M03_AXI_bvalid => '0',
- M03_AXI_rdata => '0',
- M03_AXI_rlast => '0',
- M03_AXI_rready => NLW_axi_interconnect_0_M03_AXI_rready_UNCONNECTED,
- M03_AXI_rresp => '0',
- M03_AXI_rvalid => '0',
- M03_AXI_wdata => NLW_axi_interconnect_0_M03_AXI_wdata_UNCONNECTED,
- M03_AXI_wlast => NLW_axi_interconnect_0_M03_AXI_wlast_UNCONNECTED,
- M03_AXI_wready => '0',
- M03_AXI_wstrb => NLW_axi_interconnect_0_M03_AXI_wstrb_UNCONNECTED,
- M03_AXI_wvalid => NLW_axi_interconnect_0_M03_AXI_wvalid_UNCONNECTED,
+ M03_AXI_araddr(31 downto 0) => axi_interconnect_0_M03_AXI_ARADDR(31 downto 0),
+ M03_AXI_arready => axi_interconnect_0_M03_AXI_ARREADY,
+ M03_AXI_arvalid => axi_interconnect_0_M03_AXI_ARVALID,
+ M03_AXI_awaddr(31 downto 0) => axi_interconnect_0_M03_AXI_AWADDR(31 downto 0),
+ M03_AXI_awready => axi_interconnect_0_M03_AXI_AWREADY,
+ M03_AXI_awvalid => axi_interconnect_0_M03_AXI_AWVALID,
+ M03_AXI_bready => axi_interconnect_0_M03_AXI_BREADY,
+ M03_AXI_bresp(1 downto 0) => axi_interconnect_0_M03_AXI_BRESP(1 downto 0),
+ M03_AXI_bvalid => axi_interconnect_0_M03_AXI_BVALID,
+ M03_AXI_rdata(31 downto 0) => axi_interconnect_0_M03_AXI_RDATA(31 downto 0),
+ M03_AXI_rready => axi_interconnect_0_M03_AXI_RREADY,
+ M03_AXI_rresp(1 downto 0) => axi_interconnect_0_M03_AXI_RRESP(1 downto 0),
+ M03_AXI_rvalid => axi_interconnect_0_M03_AXI_RVALID,
+ M03_AXI_wdata(31 downto 0) => axi_interconnect_0_M03_AXI_WDATA(31 downto 0),
+ M03_AXI_wready => axi_interconnect_0_M03_AXI_WREADY,
+ M03_AXI_wstrb(3 downto 0) => axi_interconnect_0_M03_AXI_WSTRB(3 downto 0),
+ M03_AXI_wvalid => axi_interconnect_0_M03_AXI_WVALID,
+ M04_ACLK => clk_wiz_0_clk_100mhz,
+ M04_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
+ M04_AXI_araddr(31 downto 0) => axi_interconnect_0_M04_AXI_ARADDR(31 downto 0),
+ M04_AXI_arready => axi_interconnect_0_M04_AXI_ARREADY,
+ M04_AXI_arvalid => axi_interconnect_0_M04_AXI_ARVALID,
+ M04_AXI_awaddr(31 downto 0) => axi_interconnect_0_M04_AXI_AWADDR(31 downto 0),
+ M04_AXI_awready => axi_interconnect_0_M04_AXI_AWREADY,
+ M04_AXI_awvalid => axi_interconnect_0_M04_AXI_AWVALID,
+ M04_AXI_bready => axi_interconnect_0_M04_AXI_BREADY,
+ M04_AXI_bresp(1 downto 0) => axi_interconnect_0_M04_AXI_BRESP(1 downto 0),
+ M04_AXI_bvalid => axi_interconnect_0_M04_AXI_BVALID,
+ M04_AXI_rdata(31 downto 0) => axi_interconnect_0_M04_AXI_RDATA(31 downto 0),
+ M04_AXI_rready => axi_interconnect_0_M04_AXI_RREADY,
+ M04_AXI_rresp(1 downto 0) => axi_interconnect_0_M04_AXI_RRESP(1 downto 0),
+ M04_AXI_rvalid => axi_interconnect_0_M04_AXI_RVALID,
+ M04_AXI_wdata(31 downto 0) => axi_interconnect_0_M04_AXI_WDATA(31 downto 0),
+ M04_AXI_wready => axi_interconnect_0_M04_AXI_WREADY,
+ M04_AXI_wstrb(3 downto 0) => axi_interconnect_0_M04_AXI_WSTRB(3 downto 0),
+ M04_AXI_wvalid => axi_interconnect_0_M04_AXI_WVALID,
S00_ACLK => clk_wiz_0_clk_100mhz,
S00_ARESETN => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
@@ -2212,24 +2293,24 @@ axi_timer_0: component mb_design_1_axi_timer_0_0
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => clk_wiz_0_clk_100mhz,
- s_axi_araddr(4 downto 0) => B"00000",
+ s_axi_araddr(4 downto 0) => axi_interconnect_0_M02_AXI_ARADDR(4 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
- s_axi_arready => NLW_axi_timer_0_s_axi_arready_UNCONNECTED,
- s_axi_arvalid => '0',
- s_axi_awaddr(4 downto 0) => B"00000",
- s_axi_awready => NLW_axi_timer_0_s_axi_awready_UNCONNECTED,
- s_axi_awvalid => '0',
- s_axi_bready => '0',
- s_axi_bresp(1 downto 0) => NLW_axi_timer_0_s_axi_bresp_UNCONNECTED(1 downto 0),
- s_axi_bvalid => NLW_axi_timer_0_s_axi_bvalid_UNCONNECTED,
- s_axi_rdata(31 downto 0) => NLW_axi_timer_0_s_axi_rdata_UNCONNECTED(31 downto 0),
- s_axi_rready => '0',
- s_axi_rresp(1 downto 0) => NLW_axi_timer_0_s_axi_rresp_UNCONNECTED(1 downto 0),
- s_axi_rvalid => NLW_axi_timer_0_s_axi_rvalid_UNCONNECTED,
- s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
- s_axi_wready => NLW_axi_timer_0_s_axi_wready_UNCONNECTED,
- s_axi_wstrb(3 downto 0) => B"1111",
- s_axi_wvalid => '0'
+ s_axi_arready => axi_interconnect_0_M02_AXI_ARREADY,
+ s_axi_arvalid => axi_interconnect_0_M02_AXI_ARVALID,
+ s_axi_awaddr(4 downto 0) => axi_interconnect_0_M02_AXI_AWADDR(4 downto 0),
+ s_axi_awready => axi_interconnect_0_M02_AXI_AWREADY,
+ s_axi_awvalid => axi_interconnect_0_M02_AXI_AWVALID,
+ s_axi_bready => axi_interconnect_0_M02_AXI_BREADY,
+ s_axi_bresp(1 downto 0) => axi_interconnect_0_M02_AXI_BRESP(1 downto 0),
+ s_axi_bvalid => axi_interconnect_0_M02_AXI_BVALID,
+ s_axi_rdata(31 downto 0) => axi_interconnect_0_M02_AXI_RDATA(31 downto 0),
+ s_axi_rready => axi_interconnect_0_M02_AXI_RREADY,
+ s_axi_rresp(1 downto 0) => axi_interconnect_0_M02_AXI_RRESP(1 downto 0),
+ s_axi_rvalid => axi_interconnect_0_M02_AXI_RVALID,
+ s_axi_wdata(31 downto 0) => axi_interconnect_0_M02_AXI_WDATA(31 downto 0),
+ s_axi_wready => axi_interconnect_0_M02_AXI_WREADY,
+ s_axi_wstrb(3 downto 0) => axi_interconnect_0_M02_AXI_WSTRB(3 downto 0),
+ s_axi_wvalid => axi_interconnect_0_M02_AXI_WVALID
);
blk_mem_gen_0: component mb_design_1_blk_mem_gen_0_0
port map (
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
index 91158f84cbeb6b459a2823acbcf98f2f94ccd127..15b940b54cf99b4fee5b799e4dcc585c2299e340 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi4lite_hog_build_i_0_0/mb_design_1_axi4lite_hog_build_i_0_0.xci
@@ -97,7 +97,7 @@
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
- "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
@@ -146,7 +146,7 @@
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
- "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xci
index 7c6a455d64913505c0a497915253b7e766c8800e..65c50a73a06a478a9fd3b0e5493504f55e740321 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_axi_timer_0_0/mb_design_1_axi_timer_0_0.xci
@@ -110,8 +110,8 @@
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
- "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci
index 5f196d703bdede814f448019e318ac8a18898980..4ca283aad91705bd5558e57c9a807605f2184376 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_lmb_bram_if_cntlr_0_0/mb_design_1_lmb_bram_if_cntlr_0_0.xci
@@ -10,7 +10,7 @@
"component_parameters": {
"C_BASEADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_HIGHADDR": [ { "value": "0x0000000000007FFF", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
- "C_MASK": [ { "value": "0x0000000040000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+ "C_MASK": [ { "value": "0x00000000c0000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"C_MASK1": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
"C_MASK2": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
"C_MASK3": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
@@ -44,7 +44,7 @@
"C_HIGHADDR": [ { "value": "0x0000000000007FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
- "C_MASK": [ { "value": "0x0000000040000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+ "C_MASK": [ { "value": "0x00000000c0000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_MASK1": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
"C_MASK2": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
"C_MASK3": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci
index 7863a765097896e7170bfa0cb82d5c4dd9bdd110..e2e47699e5298c3d9a6aa2014063d4c5674ecd26 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ip/mb_design_1_xbar_0/mb_design_1_xbar_0.xci
@@ -71,7 +71,7 @@
"M02_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
- "M03_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "M03_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -87,7 +87,7 @@
"M03_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
- "M04_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "M04_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -327,7 +327,7 @@
"M02_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
- "M03_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "M03_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -343,7 +343,7 @@
"M03_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
- "M04_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "M04_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -727,7 +727,7 @@
"M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
- "M02_A00_BASE_ADDR": [ { "value": "0x0000000041200000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+ "M02_A00_BASE_ADDR": [ { "value": "0x0000000041C00000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -743,7 +743,7 @@
"M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
- "M03_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+ "M03_A00_BASE_ADDR": [ { "value": "0x0000000041200000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -759,7 +759,7 @@
"M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
- "M04_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+ "M04_A00_BASE_ADDR": [ { "value": "0x0000000080000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
@@ -999,7 +999,7 @@
"M02_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M02_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
- "M03_A00_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "M03_A00_ADDR_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1015,7 +1015,7 @@
"M03_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M03_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
- "M04_A00_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "M04_A00_ADDR_WIDTH": [ { "value": "7", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"M04_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -1218,8 +1218,8 @@
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_ADDR_RANGES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
- "C_M_AXI_BASE_ADDR": [ { "value": "0xffffffffffffffffffffffffffffffff000000004120000000000000400000000000000041400000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
- "C_M_AXI_ADDR_WIDTH": [ { "value": "0x000000000000000000000010000000100000000c", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+ "C_M_AXI_BASE_ADDR": [ { "value": "0x000000008000000000000000412000000000000041c0000000000000400000000000000041400000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+ "C_M_AXI_ADDR_WIDTH": [ { "value": "0x000000070000001000000010000000100000000c", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_S_AXI_BASE_ID": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -1585,25 +1585,25 @@
"PROTOCOL": [ { "value": "AXI4LITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_LOCK": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_LOCK": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_CACHE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_QOS": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "HAS_REGION": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_CACHE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_QOS": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "HAS_REGION": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
- "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+ "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
@@ -1660,12 +1660,12 @@
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
- "MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
+ "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
- "CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "/clk_wiz_0_clk_out1", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
index 8103a85b861cccd8a42086349e3b4dd722c8db9e..5716a4c17a60dd03102e1f63d319540f6127bfa8 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bd
@@ -7,7 +7,8 @@
"name": "mb_design_1",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
- "tool_version": "2024.1.2"
+ "tool_version": "2024.1.2",
+ "validated": "true"
},
"design_tree": {
"microblaze_0": "",
@@ -56,6 +57,26 @@
"parameters": {
"ASSOCIATED_RESET": {
"value": "reset"
+ },
+ "CLK_DOMAIN": {
+ "value": "mb_design_1_clk_in1_0",
+ "value_src": "default"
+ },
+ "FREQ_HZ": {
+ "value": "100000000",
+ "value_src": "default"
+ },
+ "FREQ_TOLERANCE_HZ": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
+ "PHASE": {
+ "value": "0.0",
+ "value_src": "default"
}
}
},
@@ -63,6 +84,10 @@
"type": "rst",
"direction": "I",
"parameters": {
+ "INSERT_VIP": {
+ "value": "0",
+ "value_src": "default"
+ },
"POLARITY": {
"value": "ACTIVE_HIGH"
}
@@ -1365,7 +1390,8 @@
"axi_gpio_0/s_axi_aclk",
"axi_intc_0/s_axi_aclk",
"axi_timer_0/s_axi_aclk",
- "axi4lite_hog_build_i_0/s_axi_aclk"
+ "axi4lite_hog_build_i_0/s_axi_aclk",
+ "axi_interconnect_0/M04_ACLK"
]
},
"clk_wiz_0_locked": {
@@ -1437,7 +1463,8 @@
"axi_gpio_0/s_axi_aresetn",
"axi_intc_0/s_axi_aresetn",
"axi_timer_0/s_axi_aresetn",
- "axi4lite_hog_build_i_0/s_axi_aresetn"
+ "axi4lite_hog_build_i_0/s_axi_aresetn",
+ "axi_interconnect_0/M04_ARESETN"
]
},
"reset_0_1": {
@@ -1459,6 +1486,11 @@
"address_spaces": {
"Data": {
"segments": {
+ "SEG_axi4lite_hog_build_i_0_reg0": {
+ "address_block": "/axi4lite_hog_build_i_0/s_axi/reg0",
+ "offset": "0x80000000",
+ "range": "128"
+ },
"SEG_axi_gpio_0_Reg": {
"address_block": "/axi_gpio_0/S_AXI/Reg",
"offset": "0x40000000",
@@ -1469,6 +1501,11 @@
"offset": "0x41200000",
"range": "64K"
},
+ "SEG_axi_timer_0_Reg": {
+ "address_block": "/axi_timer_0/S_AXI/Reg",
+ "offset": "0x41C00000",
+ "range": "64K"
+ },
"SEG_dlmb_bram_if_cntlr_0_Mem": {
"address_block": "/dlmb_bram_if_cntlr_0/SLMB/Mem",
"offset": "0x00000000",
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bda b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bda
index 13572b024d84e97e06301bc6d21c8fb295e36242..f56212cc1d3125eab24354cdcdd8823d3b0f6953 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bda
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/mb_design_1.bda
@@ -278,6 +278,42 @@
"SV": "xilinx.com:ip:mdm:3.2",
"TM": "data",
"TU": "register"
+ },
+ "V8": {
+ "VT": "AC",
+ "BA": "0x41C00000",
+ "HA": "0x41C0FFFF",
+ "BP": "C_BASEADDR",
+ "HP": "C_HIGHADDR",
+ "MA": "Data",
+ "MX": "/microblaze_0",
+ "MI": "M_AXI_DP",
+ "MS": "SEG_axi_timer_0_Reg",
+ "MV": "xilinx.com:ip:microblaze:11.0",
+ "SX": "/axi_timer_0",
+ "SI": "S_AXI",
+ "SS": "Reg",
+ "SV": "xilinx.com:ip:axi_timer:2.0",
+ "TM": "data",
+ "TU": "register"
+ },
+ "V9": {
+ "VT": "AC",
+ "BA": "0x80000000",
+ "HA": "0x8000007F",
+ "BP": "C_BASEADDR",
+ "HP": "C_HIGHADDR",
+ "MA": "Data",
+ "MX": "/microblaze_0",
+ "MI": "M_AXI_DP",
+ "MS": "SEG_axi4lite_hog_build_i_0_reg0",
+ "MV": "xilinx.com:ip:microblaze:11.0",
+ "SX": "/axi4lite_hog_build_i_0",
+ "SI": "s_axi",
+ "SS": "reg0",
+ "SV": "xilinx.com:module_ref:axi4lite_hog_build_info:1.0",
+ "TM": "data",
+ "TU": "register"
}
},
"edges": [
@@ -313,6 +349,16 @@
"src": "V7",
"trg": "V2",
"EH": "2"
+ },
+ {
+ "src": "V8",
+ "trg": "V2",
+ "EH": "2"
+ },
+ {
+ "src": "V9",
+ "trg": "V2",
+ "EH": "2"
}
]
}
diff --git a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui
index 510ffc4f3239b67d3427111529f9da53fb6b727b..5e80db92dc4a9da7ebd78a94bf159bb42e5f01eb 100644
--- a/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui
+++ b/microblaze-demo/microblaze-demo.srcs/sources_1/bd/mb_design_1/ui/bd_4c94b93a.ui
@@ -1,7 +1,7 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.16629",
- "Default View_TopLeft":"-614,818",
+ "Default View_TopLeft":"1130,188",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD