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Commit 97e5d0a6 authored by Boris Stefanovic's avatar Boris Stefanovic
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ADD: presentation

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.gitignore
+ 3
− 0
View file @ 97e5d0a6
......@@ -73,3 +73,6 @@ meta/report/**/*.dvi
meta/report/xout/
meta/report/*.pdf
!meta/report/template/images/statements/originalstatements.pdf
meta/presentation/*.pdf
meta/diagrams/*.bkp
Makefile
+ 31
− 7
View file @ 97e5d0a6
SRCD := hw/spinal/kyber
REPORT := ISC_EMB_memoire_diplome_Stefanovic_Upegui_2024.pdf
PRESENTATION := ISC_EMB_presentation_diplome_Stefanovic_Upegui_2024.pdf
LATEX_MAIN_NAME := toplevel
LATEX_MAIN_FILE := ${LATEX_MAIN_NAME}.tex
LATEX_MAIN_OUTPUT := ${LATEX_MAIN_NAME}.pdf
LATEX_TMP_DIR := /tmp/latex-$(shell date +%Y%m%d-%H%M%S-%N)
#LATEX_CMD_PDF := pdflatex -interaction=nonstopmode -synctex=1 --output-directory=${LATEX_TMP_DIR} --aux-directory=${LATEX_TMP_DIR} ${LATEX_MAIN_FILE}
LATEX_CMD_PDF := pdflatex -interaction=nonstopmode -synctex=1 --output-directory=${LATEX_TMP_DIR} ${LATEX_MAIN_FILE}
LATEX_CMD_BIB := biber --input-directory ${LATEX_TMP_DIR} --output-directory ${LATEX_TMP_DIR} ${LATEX_MAIN_NAME}
LATEX_SRC := $(shell find meta/report -type f -name '*.tex')
PRES_MAIN_NAME := main
PRES_MAIN_FILE := ${PRES_MAIN_NAME}.tex
PRES_MAIN_OUTPUT := ${PRES_MAIN_NAME}.pdf
PRES_TMP_DIR := /tmp/pres-$(shell date +%Y%m%d-%H%M%S-%N)
#PRES_CMD_PDF := pdflatex -interaction=nonstopmode -synctex=1 --output-directory=${PRES_TMP_DIR} ${PRES_MAIN_FILE}
PRES_CMD_PDF := pdflatex -interaction=nonstopmode -synctex=1 --output-directory=${PRES_TMP_DIR} --shell-escape ${PRES_MAIN_FILE}
PRES_CMD_BIB := biber --input-directory ${PRES_TMP_DIR} --output-directory ${PRES_TMP_DIR} ${PRES_MAIN_NAME}
PRESENTATION_SRC := $(shell find meta/presentation -type f -name '*.tex' -o -name '*.cls')
ntt: clean $(wildcard ${SRCD}/ntt/*)
sbt "runMain kyber.ntt.NttGEN"
......@@ -41,7 +48,6 @@ pdf: ${LATEX_SRC}
view: pdf
#firefox meta/report/${LATEX_MAIN_OUTPUT}
firefox meta/report/${REPORT}
......@@ -51,8 +57,25 @@ repdf: clean pdf
review: clean view
presentation: ${PRESENTATION_SRC}
mkdir -p ${PRES_TMP_DIR}
cd meta/presentation && \
${PRES_CMD_PDF} ; \
${PRES_CMD_PDF} ; \
${PRES_CMD_PDF} ; \
${PRES_CMD_BIB} ; \
${PRES_CMD_PDF} ; \
${PRES_CMD_PDF} ; \
cp ${PRES_TMP_DIR}/${PRES_MAIN_OUTPUT} ${PRESENTATION}
rm -rf ${PRES_TMP_DIR}
presentnow: clean presentation
firefox meta/presentation/${PRESENTATION}
clean:
rm -rf gen out simWorkspace target meta/report/xout meta/report/*.pdf
rm -rf gen out simWorkspace target sw/a.out meta/report/xout meta/report/*.pdf
find meta/report -type f \
\(\
-name '*.aux' -o \
......@@ -71,8 +94,9 @@ clean:
-not -name 'originalstatements.pdf' \
\)\
-print -delete
rm -rf meta/presentation/*.pdf meta/diagrams/.*.bkp
.PHONY: clean ntt pdf repdf review view
.PHONY: clean ntt pdf presentation presentnow repdf review view
.NOTPARALLEL: repdf review
.NOTPARALLEL: presentnow repdf review
hw/spinal/kyber/ntt/AddressTable.scala
+ 4
− 7
View file @ 97e5d0a6
......@@ -15,11 +15,10 @@ case class AddressTable(nports: Int = 1) extends Component {
SoftChecks.require_NPORTS(nports)
val io = new Bundle {
val i_iteration = Vec.fill(nports)(in UInt (log2Up(SoftConstants.TABLE_LENGTH) bits)) // 10 bits
val o_j = Vec.fill(nports)(out UInt (log2Up(SoftConstants.WORD_COUNT) bits)) // 8 bits
val o_l = Vec.fill(nports)(out UInt (log2Up(SoftConstants.WORD_COUNT) bits)) // 8 bits
//val o_k = Vec.fill(nports)(out UInt (log2Up(SoftConstants.ZETAS_TABLE_LENGTH) bits)) // 7 bits
val o_zeta = Vec.fill(nports)(out SInt (SoftConstants.WORD_WIDTH bits)) //16 bits
val i_iteration = in(Vec.fill(nports)(UInt(log2Up(SoftConstants.TABLE_LENGTH) bits))) // 10 bits
val o_j = out(Vec.fill(nports)(UInt(log2Up(SoftConstants.WORD_COUNT) bits))) // 8 bits
val o_l = out(Vec.fill(nports)(UInt(log2Up(SoftConstants.WORD_COUNT) bits))) // 8 bits
val o_zeta = out(Vec.fill(nports)(SInt(SoftConstants.WORD_WIDTH bits))) //16 bits
}
val sig_loop_n = Vec.fill(nports)(UInt(log2Up(SoftConstants.TABLE_LENGTH) - 7 bits))
......@@ -48,7 +47,6 @@ case class AddressTable(nports: Int = 1) extends Component {
// outputs
io.o_j(n) <> sig_j(n)
io.o_l(n) <> sig_l(n)
//io.o_k(n) <> sig_k(n)
io.o_zeta(n) <> sig_z(n)
}
}
......@@ -65,7 +63,6 @@ object AddressTableSIM extends App {
for (n <- 0 until dut.nports) {
assert(dut.io.o_j(n).toInt == SoftFunctions.expr_J(i))
assert(dut.io.o_l(n).toInt == SoftFunctions.expr_L(i))
//assert(dut.io.o_k(n).toInt == SoftFunctions.expr_K(i))
assert(dut.io.o_zeta(n).toInt == SoftFunctions.expr_Z(i))
}
}
......
hw/spinal/kyber/ntt/IndexDispatcher.scala
+ 1
− 1
View file @ 97e5d0a6
......@@ -21,7 +21,7 @@ case class IndexDispatcher(nports: Int = 1) extends Component {
val io = new Bundle {
val i_step = in UInt (log2Up(SoftConstants.TABLE_LENGTH / nports) bits)
val o_tabidx = Vec.fill(nports)(out UInt (log2Up(SoftConstants.TABLE_LENGTH) bits))
val o_tabidx = out(Vec.fill(nports)(UInt(log2Up(SoftConstants.TABLE_LENGTH) bits)))
}
for (n <- 0 until nports) {
......
hw/spinal/kyber/ntt/MemoryBuffer.scala
+ 3
− 3
View file @ 97e5d0a6
......@@ -19,10 +19,10 @@ case class MemoryBuffer(
val i_single_addr = in UInt (log2Up(word_count) bits)
val i_single_load = in Bool()
val o_single_data = out Bits (word_width bits)
val i_parallel_data = Vec.fill(nports)(Vec.fill(2)(in Bits (word_width bits)))
val i_parallel_addr = Vec.fill(nports)(Vec.fill(2)(in UInt (log2Up(word_count) bits)))
val i_parallel_data = in(Vec.fill(nports)(Vec.fill(2)(Bits(word_width bits))))
val i_parallel_addr = in(Vec.fill(nports)(Vec.fill(2)(UInt(log2Up(word_count) bits))))
val i_parallel_update = in Bool()
val o_parallel_data = Vec.fill(nports)(Vec.fill(2)(out Bits (word_width bits)))
val o_parallel_data = out(Vec.fill(nports)(Vec.fill(2)(Bits(word_width bits))))
}
// REGISTERS
......
hw/spinal/kyber/ntt/Ntt.scala
+ 1
− 0
View file @ 97e5d0a6
......@@ -135,6 +135,7 @@ object NttGEN extends App {
object NttSIM extends App {
for (nports <- (0 to 7).map(1 << _)) {
//Config.sim.withVcdWave.compile(Ntt(nports = nports)).doSim { dut =>
Config.sim.compile(Ntt(nports = nports)).doSim { dut =>
val t = Ticker(dut)
dut.io.i_data #= 0
......
hw/spinal/kyber/ntt/NttMemoryMap.scala
+ 52
− 35
View file @ 97e5d0a6
......@@ -12,13 +12,13 @@ import spinal.lib.bus.amba4.axi._
*
* @param nports the number of "butterflies" or parallel multiplications
*/
case class NttAxi(nports: Int = 1) extends Component {
case class NttAxi(nports: Int = 1, adrwid: Int = 32, datwid: Int = 32) extends Component {
SoftChecks.require_NPORTS(nports)
val io = new Bundle {
val axi = slave(Axi4(Axi4Config(
addressWidth = 32,
dataWidth = 32,
addressWidth = adrwid,
dataWidth = datwid,
idWidth = 0,
useId = false,
useRegion = false,
......@@ -37,39 +37,56 @@ case class NttAxi(nports: Int = 1) extends Component {
val ntt = Ntt(nports = nports)
// SPEC (AXI4) : on reset, drive VALID to '0'
val reg_rvalid = Reg(Bool()) init false
reg_rvalid := ntt.io.o_valid
val reg_bvalid = Reg(Bool()) init false
reg_bvalid := True
val sig_is_write = Bool() // TODO: define
// NTT INPUTS
ntt.io.i_data := io.axi.w.data(ntt.io.i_data.getBitsWidth - 1 downto 0)
ntt.io.i_addr := sig_is_write.mux(
io.axi.aw.addr.asBits.asUInt(ntt.io.i_addr.getBitsWidth - 1 downto 0),
io.axi.ar.addr.asBits.asUInt(ntt.io.i_addr.getBitsWidth - 1 downto 0),
)
ntt.io.i_load
ntt.io.i_go
ntt.io.i_stop
// CONSUMABLE
io.axi.ar.addr
io.axi.ar.valid
io.axi.r.ready
io.axi.aw.addr
io.axi.aw.valid
io.axi.w.data
io.axi.w.valid
val read = new Area {
val reg_rd_dat = Reg(Bits(datwid bits)) init 0
val reg_rd_valid = Reg(Bool()) init false // requested data is registered and ready for reading
ntt.io.i_addr := io.axi.ar.addr(ntt.io.i_addr.high downto 0) // ignore MSB
io.axi.ar.ready := !reg_rd_valid
io.axi.r.data := reg_rd_dat
io.axi.r.valid := reg_rd_valid
when(io.axi.ar.valid) {
reg_rd_valid := True
when(!io.axi.ar.addr.asBits(ntt.io.i_addr.getWidth)) {
reg_rd_dat := ((ntt.io.o_data.high downto 0) -> ntt.io.o_data, default -> false)
} elsewhen (io.axi.ar.addr(io.axi.ar.addr.high - 1 downto 0) === 0) {
reg_rd_dat := (1 -> ntt.io.o_valid, 0 -> ntt.io.o_ready, default -> false)
} otherwise {
reg_rd_valid := False
}
}
when(io.axi.r.ready && reg_rd_valid) {
reg_rd_valid := False
}
}
// SETTABLE
io.axi.ar.ready := True
io.axi.r.data := ((ntt.io.o_data.getBitsWidth - 1 downto 0) -> ntt.io.o_data, default -> false)
io.axi.r.valid := ntt.io.o_valid
io.axi.aw.ready := True
//TODO: WIP
val writ = new Area {
val reg_ntt_load = Reg(Bool()) init false
reg_ntt_load := False
val reg_ntt_idat = Reg(Bits(ntt.io.i_data.getWidth bits)) init 0
reg_ntt_idat := (default -> false)
val reg_ntt_go = Reg(Bool()) init false
reg_ntt_go := False
val reg_ntt_stop = Reg(Bool()) init false
reg_ntt_stop := False
val reg_aw_ready = Reg(Bool()) init false
reg_aw_ready := True
val reg_aw_adr = Reg(UInt(ntt.io.i_addr.getWidth bits))
ntt.io.i_load := reg_ntt_load
ntt.io.i_data := reg_ntt_idat
ntt.io.i_go := reg_ntt_go
ntt.io.i_stop := reg_ntt_stop
io.axi.aw.ready := reg_aw_ready
io.axi.w.ready := ntt.io.o_ready
when(io.axi.aw.valid) {
when(!io.axi.aw.addr.asBits(ntt.io.i_addr.getWidth)) {
reg_aw_adr := io.axi.aw.addr(ntt.io.i_addr.high downto 0)
reg_aw_ready := False
}
}
io.axi.b.valid := True
//io.axi.b.resp := (default -> false) // valid should be set but this is available only when useResp is set in config
}
}
......
meta/circ/MemoryBuffer_4x8x4.circ
+ 12
− 12
View file @ 97e5d0a6
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.8.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.8.0(https://github.com/logisim-evolution/).
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
......@@ -554,19 +554,19 @@
</comp>
<comp lib="0" loc="(1510,1590)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="AXIA"/>
<a name="label" val="SADR"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="width" val="3"/>
</comp>
<comp lib="0" loc="(1510,3090)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="AXID"/>
<a name="label" val="SDAT"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(1530,3150)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="AXIA"/>
<a name="label" val="SADR"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="width" val="3"/>
</comp>
......@@ -961,7 +961,7 @@
</comp>
<comp lib="0" loc="(300,1020)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="I_AXI_LOAD"/>
<a name="label" val="I_SINGLE_LOAD"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
</comp>
<comp lib="0" loc="(300,1180)" name="Pin">
......@@ -995,14 +995,14 @@
</comp>
<comp lib="0" loc="(300,940)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="I_AXI_DATA"/>
<a name="label" val="I_SINGLE_DATA"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="radix" val="16"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(300,980)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="I_AXI_ADDR"/>
<a name="label" val="I_SINGLE_ADDR"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="radix" val="8"/>
<a name="width" val="3"/>
......@@ -1069,12 +1069,12 @@
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
</comp>
<comp lib="0" loc="(320,940)" name="Tunnel">
<a name="label" val="AXID"/>
<a name="label" val="SDAT"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(320,980)" name="Tunnel">
<a name="label" val="AXIA"/>
<a name="label" val="SADR"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="width" val="3"/>
</comp>
......@@ -1464,7 +1464,7 @@
</comp>
<comp lib="0" loc="(3650,2570)" name="Tunnel">
<a name="facing" val="east"/>
<a name="label" val="AXIA"/>
<a name="label" val="SADR"/>
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="width" val="3"/>
</comp>
......@@ -1884,7 +1884,7 @@
<a name="labelfont" val="DejaVu Sans Mono bold 16"/>
<a name="width" val="4"/>
</comp>
<comp lib="8" loc="(1986,102)" name="Text">
<comp lib="8" loc="(1985,100)" name="Text">
<a name="font" val="DejaVu Sans Mono bold 64"/>
<a name="text" val="MemoryBuffer with parameters : N = 4 , R = 8 , W = 4"/>
</comp>
......
meta/diagrams/archflow.drawio 0 → 100644
+ 88
− 0
View file @ 97e5d0a6
<mxfile host="Electron" agent="Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/24.7.8 Chrome/128.0.6613.36 Electron/32.0.1 Safari/537.36" version="24.7.8">
<diagram id="C5RBs43oDa-KdzZeNtuy" name="Page-1">
<mxGraphModel dx="1488" dy="1046" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1600" pageHeight="900" math="0" shadow="0">
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meta/diagrams/dio_method.svg 0 → 100644
+ 4
− 0
View file @ 97e5d0a6
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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 440px; margin-left: 1290px;"><div data-drawio-colors="color: rgb(240, 240, 240); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(240, 240, 240); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;"><font style="font-size: 24px;">ASIC</font></div></div></div></foreignObject><text x="1369" y="444" fill="rgb(240, 240, 240)" font-family="&quot;Helvetica&quot;" font-size="12px" text-anchor="middle">ASIC</text></switch></g></g></g><g data-cell-id="5SgrSzUetFcjJ_riC5Sn-9"><g><rect x="899" y="300" width="320" height="40" fill="none" stroke="none" pointer-events="all"/></g><g><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 318px; height: 1px; padding-top: 320px; margin-left: 900px;"><div data-drawio-colors="color: rgb(240, 240, 240); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 18px; font-family: Helvetica; color: rgb(240, 240, 240); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Tous composants implémentés</div></div></div></foreignObject><text x="1059" y="325" fill="rgb(240, 240, 240)" font-family="&quot;Helvetica&quot;" font-size="18px" text-anchor="middle">Tous composants implémentés</text></switch></g></g></g></g></g></g><switch><g requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"/><a transform="translate(0,-5)" xlink:href="https://www.drawio.com/doc/faq/svg-export-text-problems" target="_blank"><text text-anchor="middle" font-size="10px" x="50%" y="100%">Text is not SVG - cannot display</text></a></switch></svg>
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