feat: ex1 lab4 pretty much done, irq_handler should be adjusted

labo4.1_DMA_new/src/dma.c

@@ -16,6 +16,9 @@ volatile uint32_t DMAErrCount = 0;
 void DMA_IRQHandler (void) 
 {
 	/*...*/
+	DMATCCount += 1;
+	// Clears the channels terminal count interrupt
+	LPC_GPDMA->DMACIntTCClear = 1;
 }
 
 
@@ -34,17 +37,33 @@ void DMA_IRQHandler (void)
 ******************************************************************************/
 void DMA_Init(uint32_t *src, uint32_t *dest, uint32_t len, uint32_t LLI)
 {
+	NVIC_EnableIRQ(DMA_IRQn);
 	LPC_SC->PCONP |= (1 << 29);	/* Enable GPDMA clock */
-	LPC_GPDMACH0->DMACCConfig |= (1 << 0); // Enabling channel 0 (bit 1 is associated with endianness [by default val = 0] => little-endian)
-	LPC_GPDMA->DMACIntTCClear |= (1 << 0); // Clears the channels terminal count interrupt
-	LPC_GPDMA->DMACIntErrClr |= (1 << 0); // Clears the channels error interrupt
+
+	// Enabling DMA controller
+	LPC_GPDMA->DMACConfig = 1;
+
+	// Clears the channels terminal count interrupt
+	LPC_GPDMA->DMACIntTCClear = 1;
+	// Clears the channels error interrupt
+	LPC_GPDMA->DMACIntErrClr = 1;
+
+
 	LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)src;
 	LPC_GPDMACH0->DMACCDestAddr = (uint32_t)dest;
+
+
 	LPC_GPDMACH0->DMACCLLI = LLI;
-	LPC_GPDMACH0->DMACCControl |= (len & 0xFFF); // Setting transfer size
-	LPC_GPDMACH0->DMACCControl |= (1 << 12); // Burst size of 4 for src
-	LPC_GPDMACH0->DMACCControl |= (1 << 15); // Burst size of 4 for dst
-	LPC_GPDMACH0->DMACCControl |= (1 << 31); // Enabling interrupt on terminal count
-	NVIC_EnableIRQ(DMA_IRQn);
-  /*...*/
+
+//	LPC_GPDMACH0->DMACCControl |= (len & 0xFFF); // Setting transfer size
+	LPC_GPDMACH0->DMACCControl = (len | DMA_CFG);
+
+//	LPC_GPDMACH0->DMACCControl |= (1 << 12); // Burst size of 4 for src
+//	LPC_GPDMACH0->DMACCControl &= ~(3 << 13); // Setting the rest of burst src to 0
+//
+//	LPC_GPDMACH0->DMACCControl |= (1 << 15); // Burst size of 4 for dst
+//	LPC_GPDMACH0->DMACCControl &= ~(3 << 16); // Setting the rest of burst dst to 0
+//
+	//  Enabling ITC (bit 15) / Enabling channel 0 (bit 1 is associated with endianness [by default val = 0] => little-endian)
+	LPC_GPDMACH0->DMACCConfig = (1 << 15) | (1 << 0);
 }

labo4.1_DMA_new/src/dmatest.c

@@ -24,6 +24,8 @@ void single_copy()
 	DMA_Init(src1, dest, DMA_SIZE/4, 0);
 
     while (!DMATCCount);		/* Wait until DMA is done */
+
+    volatile char rnd = 0;
 }
 
 // copy 3 source buffers in 1 destination buffer with DMA linked lists