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julien.borel
vhdl-balayeur
Commits
140c803d
Commit
140c803d
authored
5 years ago
by
julien.borel
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balayeur.vhd
+89
-0
89 additions, 0 deletions
balayeur.vhd
balayeurPkg.vhd
+38
-0
38 additions, 0 deletions
balayeurPkg.vhd
balayeur_test.vhd
+76
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76 additions, 0 deletions
balayeur_test.vhd
decodeur.vhd
+28
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28 additions, 0 deletions
decodeur.vhd
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0 deletions
balayeur.vhd
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−
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140c803d
---------------------------------------
------- Created by Julien Borel -------
---------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
balayeurPkg
.
all
;
entity
balayeur
is
port
(
clk
:
in
std_logic
;
rst
:
in
std_logic
;
data
:
in
image
;
column
:
out
std_logic_vector
(
MATRIX_WIDTH
-1
downto
0
);
leds_red
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
);
leds_green
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
);
leds_blue
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
)
);
end
balayeur
;
architecture
behaviour
of
balayeur
is
signal
cnts
:
unsigned
(
CPT1_SIZE
-1
downto
0
);
signal
cycle
:
std_logic
;
signal
n_col
:
unsigned
(
CPT2_SIZE
-1
downto
0
);
begin
-- 1st counter. He manages the time a column stay switched on.
process
(
clk
)
begin
if
rising_edge
(
clk
)
then
if
not
rst
=
'1'
then
cnts
<=
(
others
=>
'0'
);
else
if
cnts
=
CPT1_MAX
then
cnts
<=
(
others
=>
'0'
);
cycle
<=
'1'
;
else
cnts
<=
cnts
+
1
;
cycle
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
-- 2nd counter. He manages the column number to be switched on.
process
(
clk
)
begin
if
rising_edge
(
clk
)
then
if
not
rst
=
'1'
then
n_col
<=
(
others
=>
'0'
);
elsif
cycle
=
'1'
then
if
n_col
=
CPT2_MAX
then
n_col
<=
(
others
=>
'0'
);
else
n_col
<=
n_col
+
1
;
end
if
;
end
if
;
end
if
;
end
process
;
-- This process writes the pattern.
process
(
n_col
)
begin
if
rising_edge
(
clk
)
then
leds_red
<=
data
(
0
)(
to_integer
(
n_col
));
leds_green
<=
data
(
1
)(
to_integer
(
n_col
));
leds_blue
<=
data
(
2
)(
to_integer
(
n_col
));
end
if
;
end
process
;
-- Decoding the column number. Ex: 0000 -> 111111111110
-- 0001 -> 111111111101
D1
:
decodeur
port
map
(
clk
=>
clk
,
D
=>
std_logic_vector
(
n_col
),
Q
=>
column
);
end
behaviour
;
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balayeurPkg.vhd
0 → 100755
+
38
−
0
View file @
140c803d
---------------------------------------
------- Created by Julien Borel -------
---------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
-- This library doesn't work on quartus...
-- use ieee.math_real.all;
-- use ieee.math_real."ceil";
-- use ieee.math_real."log2";
package
balayeurPkg
is
constant
CPT1_MAX
:
natural
:
=
500
;
-- 100 (Hz) : 0.01 (ms) or use 5000000; -- 100 (ms)
constant
CPT2_MAX
:
natural
:
=
12
;
-- there is 12 colonnes
constant
CPT1_SIZE
:
natural
:
=
23
;
--natural(ceil(log2(real(CPT1_MAX))));
constant
CPT2_SIZE
:
natural
:
=
4
;
--natural(ceil(log2(real(CPT2_MAX))));
CONSTANT
MATRIX_WIDTH
:
natural
:
=
12
;
CONSTANT
MATRIX_HEIGHT
:
natural
:
=
8
;
-- Declaration of type image
type
under_image
is
array
(
0
to
MATRIX_WIDTH
-1
)
of
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
);
type
image
is
array
(
0
to
2
)
of
under_image
;
component
decodeur
port
(
clk
:
std_logic
;
D
:
in
std_logic_vector
(
3
downto
0
);
Q
:
out
std_logic_vector
(
11
downto
0
)
);
end
component
;
end
package
balayeurPkg
;
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balayeur_test.vhd
0 → 100755
+
76
−
0
View file @
140c803d
---------------------------------------
------- Created by Julien Borel -------
---------------------------------------
-- This is a top level entity using to test the "balayeur" on the FPGA
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
library
work
;
use
work
.
balayeurPkg
.
all
;
entity
balayeur_test
is
port
(
CLOCK
:
in
std_logic
;
Button_n0
:
in
std_logic
;
-- used for reset.
LED_SelC_n
:
out
std_logic_vector
(
MATRIX_WIDTH
-1
downto
0
);
LED_Sel_R
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
);
LED_Sel_G
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
);
LED_Sel_B
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
)
);
end
balayeur_test
;
architecture
behaviour
of
balayeur_test
is
component
balayeur
port
(
clk
:
in
std_logic
;
rst
:
in
std_logic
;
data
:
in
image
;
column
:
out
std_logic_vector
(
MATRIX_WIDTH
-1
downto
0
);
leds_red
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
);
leds_green
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
);
leds_blue
:
out
std_logic_vector
(
MATRIX_HEIGHT
-1
downto
0
)
);
end
component
;
-- Declaration of a signal of type image with the pattern of a beautiful red heart.
signal
red_heart
:
image
:
=
(
(
"00000000"
,
"00000000"
,
"00011100"
,
"00111110"
,
"01111110"
,
"01111100"
,
"11111000"
,
"01111100"
,
"01111110"
,
"00111110"
,
"00011100"
,
"00000000"
),(
others
=>
"00000000"
),(
others
=>
"00000000"
)
);
begin
balayeur0
:
balayeur
port
map
(
clk
=>
CLOCK
,
rst
=>
Button_n0
,
data
=>
red_heart
,
column
=>
LED_SelC_n
,
leds_red
=>
LED_Sel_R
,
leds_green
=>
LED_Sel_G
,
leds_blue
=>
LED_Sel_B
);
end
behaviour
;
This diff is collapsed.
Click to expand it.
decodeur.vhd
0 → 100755
+
28
−
0
View file @
140c803d
---------------------------------------
---- Written by Nicholas Hamilton -----
---------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
decodeur
is
port
(
clk
:
in
std_logic
;
D
:
in
std_logic_vector
(
3
downto
0
);
Q
:
out
std_logic_vector
(
11
downto
0
)
);
end
decodeur
;
architecture
struct_behav
of
decodeur
is
signal
Q_s
:
std_logic_vector
(
11
downto
0
)
:
=
(
others
=>
'0'
);
begin
Q
<=
not
Q_s
;
process
(
clk
)
begin
if
rising_edge
(
clk
)
then
Q_s
<=
(
others
=>
'0'
);
Q_s
(
to_integer
(
unsigned
(
D
)))
<=
'1'
;
end
if
;
end
process
;
end
struct_behav
;
\ No newline at end of file
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