Select Git revision
component.xml
Forked from
soma / scalp_firmware
Source project has a limited visibility.
component.xml 102.90 KiB
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>hepia-cores.ch</spirit:vendor>
<spirit:library>scalp</spirit:library>
<spirit:name>scalp_hl2</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>S00_AXI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_AWADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_AWPROT</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_AWVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_AWREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_WDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_WSTRB</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_WVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_WREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_BRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_BVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_BREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_ARADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_ARPROT</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_ARVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_ARREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_RDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_RRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_RVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S00_AXI_RREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S01_AXI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="S01_AXI"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWLEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWLEN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWSIZE</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWBURST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWLOCK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWCACHE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWCACHE</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWPROT</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREGION</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWREGION</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWQOS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWQOS</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_AWREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_WDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_WSTRB</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_WLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_WVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_WREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_BID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_BRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_BVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_BREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARADDR</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARLEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARLEN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARSIZE</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARBURST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARLOCK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARCACHE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARCACHE</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARPROT</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREGION</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARREGION</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARQOS</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARQOS</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_ARREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_RID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_RDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_RRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_RLAST</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_RVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S01_AXI_RREADY</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>AXI_ARESETN</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>AXI_ARESETN</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>AXI_ACLK</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>AXI_ACLK</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXI_ACLK.ASSOCIATED_BUSIF">S00_AXI:S01_AXI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.AXI_ACLK.ASSOCIATED_RESET">AXI_ARESETN</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>S00_AXI</spirit:name>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1) + 1)" spirit:minimum="4096" spirit:rangeType="long">4096</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1) + 1">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
<spirit:memoryMap>
<spirit:name>S01_AXI</spirit:name>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH')) - 1) + 1)" spirit:minimum="4096" spirit:rangeType="long">524288</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH')) - 1) + 1">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
<spirit:displayName>Synthesis</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>VHDL</spirit:language>
<spirit:modelName>scalp_hl2_v1_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>85b1c87b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_xpgui</spirit:name>
<spirit:displayName>UI Layout</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>a2be5a47</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>scalp_hl2_v1_0</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>01a5699c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>HL2UartxSO</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.G_PORT_COUNT')) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>AXI_ACLK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>AXI_ARESETN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_AWADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_AWPROT</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_AWVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_AWREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_WDATA</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_WSTRB</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_WVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_WREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_BRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_BVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_BREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_ARADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_ARPROT</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_ARVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_ARREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_RDATA</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_RRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_RVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S00_AXI_RREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_ID_WIDTH')) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH')) - 1)">18</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWLEN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWSIZE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWBURST</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWLOCK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWCACHE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">3</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWPROT</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWQOS</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWREGION</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_AWREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_WDATA</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_WSTRB</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_WLAST</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_WVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_WREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_BID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_ID_WIDTH')) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_BRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_BVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_BREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_ID_WIDTH')) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARADDR</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH')) - 1)">18</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARLEN</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">7</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARSIZE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARBURST</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARLOCK</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARCACHE</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">3</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARPROT</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">2</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARQOS</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARREGION</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARVALID</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_ARREADY</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_RID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_ID_WIDTH')) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_RDATA</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_RRESP</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_RLAST</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_RVALID</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S01_AXI_RREADY</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>G_PORT_COUNT</spirit:name>
<spirit:displayName>G Port Count</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.G_PORT_COUNT">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>G_CLK_DIV</spirit:name>
<spirit:displayName>G Clk Div</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.G_CLK_DIV">200</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 Axi Data Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 Axi Addr Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH">4</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_ID_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Id Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_ID_WIDTH">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Data Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_DATA_WIDTH">32</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Addr Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_ADDR_WIDTH">19</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_AWUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Awuser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_AWUSER_WIDTH">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_ARUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Aruser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_ARUSER_WIDTH">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_WUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Wuser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_WUSER_WIDTH">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_RUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Ruser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_RUSER_WIDTH">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S01_AXI_BUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Buser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S01_AXI_BUSER_WIDTH">0</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:choices>
<spirit:choice>
<spirit:name>choice_list_9d8b0d81</spirit:name>
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/ip_core/blk_mem_gen_0/blk_mem_gen_0.xci</spirit:name>
<spirit:userFileType>xci</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_S00_AXI.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_S01_AXI.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_bram.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_uart.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_fee885df</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:name>
<spirit:vendorExtensions>
<xilinx:subCoreRef>
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="blk_mem_gen" xilinx:version="8.4">
<xilinx:mode xilinx:name="create_mode"/>
</xilinx:componentRef>
</xilinx:subCoreRef>
</spirit:vendorExtensions>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xgui/scalp_hl2_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_a2be5a47</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_S00_AXI.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_S01_AXI.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_bram.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_ctrl.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2_uart.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/hdl/scalp_hl2.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_blk_mem_gen_8_4__ref_view_fileset</spirit:name>
<spirit:vendorExtensions>
<xilinx:subCoreRef>
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="blk_mem_gen" xilinx:version="8.4">
<xilinx:mode xilinx:name="create_mode"/>
</xilinx:componentRef>
</xilinx:subCoreRef>
</spirit:vendorExtensions>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>SCALP-HEPIALight2 interface IP</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>G_PORT_COUNT</spirit:name>
<spirit:displayName>HL2 ports count</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_PORT_COUNT" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>G_CLK_DIV</spirit:name>
<spirit:displayName>Clock division value</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.G_CLK_DIV" spirit:minimum="1" spirit:maximum="65535" spirit:rangeType="long">200</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S00 Axi Data Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S00 Axi Addr Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_ID_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Id Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_ID_WIDTH">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Data Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_DATA_WIDTH">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Addr Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_ADDR_WIDTH">19</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_AWUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Awuser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_AWUSER_WIDTH">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_ARUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Aruser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_ARUSER_WIDTH">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_WUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Wuser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_WUSER_WIDTH">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_RUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Ruser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_RUSER_WIDTH">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S01_AXI_BUSER_WIDTH</spirit:name>
<spirit:displayName>C S01 Axi Buser Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S01_AXI_BUSER_WIDTH">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">scalp_hl2_v1_0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/SCALP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>scalp_hl2</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:xpmLibraries>
<xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
</xilinx:xpmLibraries>
<xilinx:vendorDisplayName>HEPIA CoRES</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://hepia-cores.ch/</xilinx:vendorURL>
<xilinx:coreRevision>10</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2020-12-21T16:08:00Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="ui.data.coregen.dd@28bf71ef_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@387c5664_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@390af341_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@96da8a0_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1aa5363b_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6ac7b5e3_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@337fc8af_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@20645def_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4cbdc6e4_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@e9197fe_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@570b961f_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4fc0877f_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@47f5024d_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@732a9a3d_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2ad75a08_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ea1f7b5_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@419fb015_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3a9a0ade_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4739fe85_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@382e375_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@492fa79e_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7602c245_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@a35f949_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@150bc33_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@689f3b91_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7fad9f6_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@58315ab0_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@315542a9_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1e3e6609_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@33a53e51_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@664d4891_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3530edff_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@11c14c4c_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6fddf7d1_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@18aa7543_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@236a7419_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2844ce01_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@314194f3_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2cf5aa5e_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@46213e8d_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@53982c97_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@352133db_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@a909227_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@740cabe1_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@18684e20_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5219d0cf_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@19a5bd78_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@669a2ace_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@229d19b9_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@72a55e2f_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@40f5db59_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6b619f95_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5c1a56_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5505d5ce_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@74a3a6ed_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5c19d118_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@aaafb59_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d9fc45b_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@520e0b6d_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@629616f3_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@f5609df_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6d4efd1d_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7f32a52_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@127bd79a_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5ea67a28_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@531e0346_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@12c80df1_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5a08adb2_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@73b7b411_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@238de4c8_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@412a12b7_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e8d019e_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@18c80f27_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@65e008d1_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1ff55db_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@48a34cdf_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@15f1118_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@76d4024d_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5771bc00_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@182f44e1_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@19e562c5_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@470214ac_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5096063d_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@543b23a7_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@23cf7a06_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5d8187c_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@181efed3_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@399ea19c_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@10e63bc9_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@44535f1f_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@556e8b81_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@58c61057_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d350c3f_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@66d81827_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@51ae9e00_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@d757cdf_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@474fb808_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3060cadf_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ad94084_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7dff35f_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@45585f28_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7f255cad_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@79789fb1_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@324fc112_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@62f69301_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@66986200_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@bccfa19_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@fabcbc4_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@22fe3279_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6782aa8a_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5a37209c_ARCHIVE_LOCATION">/home/quentin/Dropbox/HEPIA/SOMA/scalp_firmware_uart_hl2/peripherals/hw/scalp_hl2</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2019.2_AR72614</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b7cf672f"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="a9994d9e"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7d4ccd67"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="08c76ac2"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b6fbdf14"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="dee1c1c6"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>