Creation of a project for the Zynq processor in the SOC folder.

soc/hw/scalp_zynqps/src/hdl/scalp_zynqps.vhd

soc/hw/scalp_zynqps/src/sim/tb_scalp_zynqps.vhd

...ado/scalp_zynqps/2019.2/lin64/.scripts/.prompt_colors.tcl

...lp_zynqps/2019.2/lin64/.scripts/clean_prj_scalp_zynqps.sh

...p_zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.sh

..._zynqps/2019.2/lin64/.scripts/create_prj_scalp_zynqps.tcl

...alp_zynqps/2019.2/lin64/.scripts/open_prj_scalp_zynqps.sh

.../lin64/.scripts/scalp_zynqps/hdl/scalp_zynqps_wrapper.vhd

...in64/.scripts/scalp_zynqps/hw_handoff/scalp_zynqps_bd.tcl

...alp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xci

...alp_zynqps_gnd_constant_0/scalp_zynqps_gnd_constant_0.xml

...p_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.h

...p_zynqps_gnd_constant_0/sim/scalp_zynqps_gnd_constant_0.v

...ps/ip/scalp_zynqps_gnd_constant_0/sim/xlconstant_v1_1_6.h

...zynqps_gnd_constant_0/synth/scalp_zynqps_gnd_constant_0.v

.../hdl/verilog/processing_system7_v5_5_processing_system7.v

..._zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.c

..._zynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.h

...ynqps/ip/scalp_zynqps_processing_system7_0_0/ps7_init.tcl

...qps/ip/scalp_zynqps_processing_system7_0_0/ps7_init_gpl.c