Skip to content
Snippets Groups Projects
Commit 2b34341c authored by joachim.schmidt's avatar joachim.schmidt
Browse files

Creation of the IP core scalp_aurora_phy_rx_fifo

parent 2c8a0195
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 809 additions and 0 deletions
ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd 0 → 100644
+ 257
− 0
View file @ 2b34341c
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: scalp_aurora_phy_rx_fifo - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: scalp_aurora_phy_rx_fifo
--
-- Last update: 2020-11-07
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi4_pkg.all;
entity scalp_aurora_phy_rx_fifo is
port (
-- Clocks and Reset
RXClkxCI : in std_ulogic;
TXClkxCI : in std_ulogic;
RXRstxRANI : in std_ulogic;
-- North
-- RX Data
NorthRXM2SxDI : in t_axi4m2s;
NorthRXS2MxDO : out t_axi4s2m;
-- TX Data
NorthTXM2SxDO : out t_axi4m2s;
NorthTXS2MxDI : in t_axi4s2m;
-- Fifo Status
NorthFifoStatusxDO : out t_axi4fifo_status;
-- East
-- RX Data
EastRXM2SxDI : in t_axi4m2s;
EastRXS2MxDO : out t_axi4s2m;
-- TX Data
EastTXM2SxDO : out t_axi4m2s;
EastTXS2MxDI : in t_axi4s2m;
-- Fifo Status
EastFifoStatusxDO : out t_axi4fifo_status;
-- South
-- RX Data
SouthRXM2SxDI : in t_axi4m2s;
SouthRXS2MxDO : out t_axi4s2m;
-- TX Data
SouthTXM2SxDO : out t_axi4m2s;
SouthTXS2MxDI : in t_axi4s2m;
-- Fifo Status
SouthFifoStatusxDO : out t_axi4fifo_status;
-- West
-- RX Data
WestRXM2SxDI : in t_axi4m2s;
WestRXS2MxDO : out t_axi4s2m;
-- TX Data
WestTXM2SxDO : out t_axi4m2s;
WestTXS2MxDI : in t_axi4s2m;
-- Fifo Status
WestFifoStatusxDO : out t_axi4fifo_status);
end scalp_aurora_phy_rx_fifo;
architecture arch of scalp_aurora_phy_rx_fifo is
component axis_data_fifo
port (
s_axis_aresetn : in std_logic;
s_axis_aclk : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
s_axis_tkeep : in std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
s_axis_tlast : in std_logic;
m_axis_aclk : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
m_axis_tkeep : out std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
m_axis_tlast : out std_logic;
axis_wr_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
axis_rd_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
prog_empty : out std_logic;
prog_full : out std_logic);
end component;
signal RXClkxC : std_ulogic := '0';
signal TXClkxC : std_ulogic := '0';
signal RXRstxRAN : std_ulogic := '0';
-- North
signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal NorthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal NorthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
-- East
signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal EastRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EastFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
-- South
signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal SouthRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal SouthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
-- West
signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal WestRXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal WestFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
begin
AxisDataFifoxB : block is
begin -- block AxisDataFifoxB
EntityIOxB : block is
begin -- block EntityIOxB
RXClkxAS : RXClkxC <= RXClkxCI;
TXClkxAS : TXClkxC <= TXClkxCI;
RXRstxAS : RXRstxRAN <= RXRstxRANI;
-- North
NorthRXM2SxAS : NorthRXM2SxD <= NorthRXM2SxDI;
NorthRXS2MxAS : NorthRXS2MxDO <= NorthRXS2MxD;
NorthTXM2SxAS : NorthTXM2SxDO <= NorthTXM2SxD;
NorthTXS2MxAS : NorthTXS2MxD <= NorthTXS2MxDI;
NorthFifoStatusxAS : NorthFifoStatusxDO <= NorthFifoStatusxD;
-- East
EastRXM2SxAS : EastRXM2SxD <= EastRXM2SxDI;
EastRXS2MxAS : EastRXS2MxDO <= EastRXS2MxD;
EastTXM2SxAS : EastTXM2SxDO <= EastTXM2SxD;
EastTXS2MxAS : EastTXS2MxD <= EastTXS2MxDI;
EastFifoStatusxAS : EastFifoStatusxDO <= EastFifoStatusxD;
-- South
SouthRXM2SxAS : SouthRXM2SxD <= SouthRXM2SxDI;
SouthRXS2MxAS : SouthRXS2MxDO <= SouthRXS2MxD;
SouthTXM2SxAS : SouthTXM2SxDO <= SouthTXM2SxD;
SouthTXS2MxAS : SouthTXS2MxD <= SouthTXS2MxDI;
SouthFifoStatusxAS : SouthFifoStatusxDO <= SouthFifoStatusxD;
-- West
WestRXM2SxAS : WestRXM2SxD <= WestRXM2SxDI;
WestRXS2MxAS : WestRXS2MxDO <= WestRXS2MxD;
WestTXM2SxAS : WestTXM2SxDO <= WestTXM2SxD;
WestTXS2MxAS : WestTXS2MxD <= WestTXS2MxDI;
WestFifoStatusxAS : WestFifoStatusxDO <= WestFifoStatusxD;
end block EntityIOxB;
NorthAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
s_axis_aresetn => RXRstxRAN,
s_axis_aclk => RXClkxC,
s_axis_tdata => NorthRXM2SxD.DataxD,
s_axis_tkeep => NorthRXM2SxD.KeepxD,
s_axis_tlast => NorthRXM2SxD.LastxS,
s_axis_tvalid => NorthRXM2SxD.ValidxS,
s_axis_tready => NorthRXS2MxD.ReadyxS,
-- Master side
m_axis_aclk => TXClkxC,
m_axis_tdata => NorthTXM2SxD.DataxD,
m_axis_tkeep => NorthTXM2SxD.KeepxD,
m_axis_tlast => NorthTXM2SxD.LastxS,
m_axis_tvalid => NorthTXM2SxD.ValidxS,
m_axis_tready => NorthTXS2MxD.ReadyxS,
-- Status
axis_wr_data_count => NorthFifoStatusxD.WrDataCntxD,
axis_rd_data_count => NorthFifoStatusxD.RdDataCntxD,
prog_empty => NorthFifoStatusxD.ProgEmptyxS,
prog_full => NorthFifoStatusxD.ProgFullxS);
EastAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
s_axis_aresetn => RXRstxRAN,
s_axis_aclk => RXClkxC,
s_axis_tdata => EastRXM2SxD.DataxD,
s_axis_tkeep => EastRXM2SxD.KeepxD,
s_axis_tlast => EastRXM2SxD.LastxS,
s_axis_tvalid => EastRXM2SxD.ValidxS,
s_axis_tready => EastRXS2MxD.ReadyxS,
-- Master side
m_axis_aclk => TXClkxC,
m_axis_tdata => EastTXM2SxD.DataxD,
m_axis_tkeep => EastTXM2SxD.KeepxD,
m_axis_tlast => EastTXM2SxD.LastxS,
m_axis_tvalid => EastTXM2SxD.ValidxS,
m_axis_tready => EastTXS2MxD.ReadyxS,
-- Status
axis_wr_data_count => EastFifoStatusxD.WrDataCntxD,
axis_rd_data_count => EastFifoStatusxD.RdDataCntxD,
prog_empty => EastFifoStatusxD.ProgEmptyxS,
prog_full => EastFifoStatusxD.ProgFullxS);
SouthAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
s_axis_aresetn => RXRstxRAN,
s_axis_aclk => RXClkxC,
s_axis_tdata => SouthRXM2SxD.DataxD,
s_axis_tkeep => SouthRXM2SxD.KeepxD,
s_axis_tlast => SouthRXM2SxD.LastxS,
s_axis_tvalid => SouthRXM2SxD.ValidxS,
s_axis_tready => SouthRXS2MxD.ReadyxS,
-- Master side
m_axis_aclk => TXClkxC,
m_axis_tdata => SouthTXM2SxD.DataxD,
m_axis_tkeep => SouthTXM2SxD.KeepxD,
m_axis_tlast => SouthTXM2SxD.LastxS,
m_axis_tvalid => SouthTXM2SxD.ValidxS,
m_axis_tready => SouthTXS2MxD.ReadyxS,
-- Status
axis_wr_data_count => SouthFifoStatusxD.WrDataCntxD,
axis_rd_data_count => SouthFifoStatusxD.RdDataCntxD,
prog_empty => SouthFifoStatusxD.ProgEmptyxS,
prog_full => SouthFifoStatusxD.ProgFullxS);
WestAxisDataFifoxI : axis_data_fifo
port map (
-- Slave side
s_axis_aresetn => RXRstxRAN,
s_axis_aclk => RXClkxC,
s_axis_tdata => WestRXM2SxD.DataxD,
s_axis_tkeep => WestRXM2SxD.KeepxD,
s_axis_tlast => WestRXM2SxD.LastxS,
s_axis_tvalid => WestRXM2SxD.ValidxS,
s_axis_tready => WestRXS2MxD.ReadyxS,
-- Master side
m_axis_aclk => TXClkxC,
m_axis_tdata => WestTXM2SxD.DataxD,
m_axis_tkeep => WestTXM2SxD.KeepxD,
m_axis_tlast => WestTXM2SxD.LastxS,
m_axis_tvalid => WestTXM2SxD.ValidxS,
m_axis_tready => WestTXS2MxD.ReadyxS,
-- Status
axis_wr_data_count => WestFifoStatusxD.WrDataCntxD,
axis_rd_data_count => WestFifoStatusxD.RdDataCntxD,
prog_empty => WestFifoStatusxD.ProgEmptyxS,
prog_full => WestFifoStatusxD.ProgFullxS);
end block AxisDataFifoxB;
end arch;
ips/hw/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci 0 → 100644
+ 142
− 0
View file @ 2b34341c
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>axis_data_fifo</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axis_data_fifo" spirit:version="2.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKENIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_CLKIF.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKENIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_CLKIF.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_RSTIF.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_RSTIF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_SIGNAL_SET">0b00000000000000000000000000011011</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ECC_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_DEPTH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_MEMORY_TYPE">block</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_MODE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_ACLK_ASYNC">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH">920</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ADV_FEATURES">826617925</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN_CONV_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axis_data_fifo</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_DEPTH">1024</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE">block</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_MODE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AEMPTY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_AFULL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ECC_ERR_INJECT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_EMPTY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_PROG_FULL">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TLAST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TREADY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_WR_DATA_COUNT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_ACLK_ASYNC">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_EMPTY_THRESH">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROG_FULL_THRESH">920</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z015</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg485</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_DEPTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_MEMORY_TYPE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FIFO_MODE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_PROG_EMPTY" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_PROG_FULL" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_RD_DATA_COUNT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TKEEP" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_TLAST" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.HAS_WR_DATA_COUNT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IS_ACLK_ASYNC" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROG_EMPTY_THRESH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PROG_FULL_THRESH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
ips/hw/scalp_aurora_phy_rx_fifo/src/sim/tb_scalp_aurora_phy_rx_fifo.vhd 0 → 100644
+ 34
− 0
View file @ 2b34341c
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_aurora_phy_rx_fifo - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: Testbench for scalp_aurora_phy_rx_fifo
--
-- Last update: 2020-11-07 08:30:46
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_scalp_aurora_phy_rx_fifo is
end tb_scalp_aurora_phy_rx_fifo;
architecture behavioral of tb_scalp_aurora_phy_rx_fifo is
begin
end behavioral;
ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/.prompt_colors.tcl 0 → 100644
+ 37
− 0
View file @ 2b34341c
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Console color print utility
#
# Last update: 2020-11-07 08:30:46
#
##################################################################################
# Text attributes
set RESET [exec tput sgr0]
set BOLD [exec tput bold]
set ITALIC [exec tput sitm]
set BLINK [exec tput blink]
set HIGHL [exec tput smso]
# Text colors
set RED [exec tput setaf 1]
set GREEN [exec tput setaf 2]
set YELLOW [exec tput setaf 3]
set BLUE [exec tput setaf 4]
set MAGENTA [exec tput setaf 5]
set CYAN [exec tput setaf 6]
set WHITE [exec tput setaf 7]
ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/clean_prj_scalp_aurora_phy_rx_fifo.sh 0 → 100755
+ 40
− 0
View file @ 2b34341c
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Cleanup project directory
#
# Last update: 2020-11-07 08:30:46
#
##################################################################################
echo "> Cleanup project directory..."
PRJ_DIR=..
# Clean current directory
rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory
rm -rf ${PRJ_DIR}/scalp_aurora_phy_rx_fifo/ 2> /dev/null
# Clean app directory
rm ${PRJ_DIR}/app/*.h 2> /dev/null
rm ${PRJ_DIR}/app/*.c 2> /dev/null
rm ${PRJ_DIR}/app/*.html 2> /dev/null
echo "> Done"
ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.sh 0 → 100755
+ 27
− 0
View file @ 2b34341c
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-11-07 08:30:46
#
##################################################################################
echo "> Create Vivado project..."
vivado -nojournal -nolog -mode tcl -source create_prj_scalp_aurora_phy_rx_fifo.tcl -notrace
echo "> Done"
ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/create_prj_scalp_aurora_phy_rx_fifo.tcl 0 → 100644
+ 155
− 0
View file @ 2b34341c
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_aurora_phy_rx_fifo'
#
# Last update: 2020-11-07 08:30:46
#
##################################################################################
# Include files
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_aurora_phy_rx_fifo"
set PKG_DIR "${PRJ_DIR}/../../../../../packages"
set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
# Set project type
set PRJ_TYPE "COMP_PRJ_TYPE"
# Create a variable to store the start time
set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
set pkg_src_dir "${PKG_DIR}/hw"
set soc_src_dir "${SOC_DIR}/hw"
print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
#set_property board_part SCALP [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset]
update_ip_catalog
#----------------------------------------------------------------
# Add project sources
#----------------------------------------------------------------
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
# add IPs source file
#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
read_ip $comp_src_dir/ip_core/axis_data_fifo/axis_data_fifo.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
#----------------------------------------------------------------
# Add constraints files
#----------------------------------------------------------------
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
# Create the IP Integrator portion of the design
#create_bd_design "axi_design"
#update_compile_order -fileset sources_1
# launch the TCL script to generate the IPI design
source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
print_status "Add IPI design" "OK"
# Set the top level design
set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1
# Add testbench sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $src_dir/sim *.v]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
}
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK"
# Add SoC wrapper sources files
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Display the start and end time to the screen
puts $start_time
puts $end_time
exit
ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/open_prj_scalp_aurora_phy_rx_fifo.sh 0 → 100755
+ 25
− 0
View file @ 2b34341c
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-11-07 08:30:46
#
##################################################################################
echo "> Open Vivado GUI..."
vivado -nojournal -nolog -notrace ../scalp_aurora_phy_rx_fifo/scalp_aurora_phy_rx_fifo.xpr
ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/.scripts/utils.tcl 0 → 100644
+ 62
− 0
View file @ 2b34341c
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Project management utilities
#
# Last update: 2020-11-07 08:30:46
#
##################################################################################
# findFiles
# basedir - the directory to start looking in
# pattern - A pattern, as defined by the glob command, that the files must match
proc findFiles { basedir pattern } {
# Fix the directory name, this ensures the directory name is in the
# native format for the platform and contains a final directory seperator
set basedir [string trimright [file join [file normalize $basedir] { }]]
set fileList {}
# Look in the current directory for matching files, -type {f r}
# means ony readable normal files are looked at, -nocomplain stops
# an error being thrown if the returned list is empty
foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
lappend fileList $fileName
}
# Now look for any sub direcories in the current directory
foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
# Recusively call the routine on the sub directory and append any
# new files to the results
set subDirList [findFiles $dirName $pattern]
if { [llength $subDirList] > 0 } {
foreach subDirFile $subDirList {
lappend fileList $subDirFile
}
}
}
return $fileList
}
# Print a progress status
# str The string describing the current status
# status The status as a string (eg. "OK", "FAILED")
proc print_status {str status} {
set MAX_STR_LENGTH 70
source .prompt_colors.tcl
puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
}
ips/vivado/scalp_aurora_phy_rx_fifo/2019.2/lin64/setup.sh 0 → 100755
+ 30
− 0
View file @ 2b34341c
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_aurora_phy_rx_fifo
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2020-11-07 08:30:46
#
##################################################################################
# Create aliases
alias create_project='cd .scripts && ./create_prj_scalp_aurora_phy_rx_fifo.sh && cd ..'
alias clean_project='cd .scripts && ./clean_prj_scalp_aurora_phy_rx_fifo.sh && cd ..'
alias export_hw='cd .scripts && ./export_hw_scalp_aurora_phy_rx_fifo.sh && cd ..'
alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_aurora_phy_rx_fifo.sh && cd ..'
alias load_bitstream='cd .scripts && ./load_bitstream_scalp_aurora_phy_rx_fifo.sh && cd ..'
alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_aurora_phy_rx_fifo.sh && cd ..'
alias load_sw_app='cd .scripts && ./load_sw_app_scalp_aurora_phy_rx_fifo.sh && cd ..'
alias open_gui='cd .scripts && ./open_prj_scalp_aurora_phy_rx_fifo.sh && cd ..'
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment