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Commit 481beee0 authored by joachim.schmidt's avatar joachim.schmidt
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Zynq SoC update with IP Core scalp_axilite.

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soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+ 18
− 3
View file @ 481beee0
......@@ -15,7 +15,7 @@
-- Tool version: 2019.2
-- Description: scalp_zynqps_wrapper
--
-- Last update: 2020-09-07
-- Last update: 2020-11-08
--
---------------------------------------------------------------------------------
......@@ -58,7 +58,15 @@ entity scalp_zynqps_wrapper is
Spi1SSxSO : out std_logic;
Spi1SclkxCO : out std_logic;
-- MIO
FIXED_IO_mio : inout std_logic_vector (53 downto 0));
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
-- Scalp Axi Lite interface and IRQ
InterruptxSI : in std_logic;
RdAddrxDO : out std_logic_vector (11 downto 0);
RdDataxDI : in std_logic_vector (31 downto 0);
RdValidxSO : out std_logic;
WrAddrxDO : out std_logic_vector (11 downto 0);
WrDataxDO : out std_logic_vector (31 downto 0);
WrValidxSO : out std_logic);
end scalp_zynqps_wrapper;
......@@ -94,6 +102,13 @@ begin
Spi1MOSIxSO => Spi1MOSIxSO,
Spi1SSxSO => Spi1SSxSO,
Spi1SclkxCO => Spi1SclkxCO,
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI);
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
InterruptxSI => InterruptxSI,
RdAddrxDO => RdAddrxDO,
RdDataxDI => RdDataxDI,
RdValidxSO => RdValidxSO,
WrAddrxDO => WrAddrxDO,
WrDataxDO => WrDataxDO,
WrValidxSO => WrValidxSO);
end arch;
soc/vivado/scalp_zynqps/2019.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+ 50
− 6
View file @ 481beee0
################################################################
# This is a generated script based on design: scalp_safe_fw_bd
# This is a generated script based on design: scalp_zynqps
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
......@@ -35,7 +35,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source scalp_safe_fw_bd_script.tcl
# source scalp_zynqps_script.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
......@@ -57,9 +57,8 @@ set design_name scalp_zynqps
set run_remote_bd_flow 1
if { $run_remote_bd_flow == 1 } {
# Set the reference directory for source file relative paths (by default
# the value is script directory path)
# the value is script directory path)
set origin_dir .
#set origin_dir ./Documents/Projets/Hepia/build_scalp_fw/soma/scalp_safe_fw/design/hw/scalp_safe_fw/src/bd
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
......@@ -123,7 +122,10 @@ set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
hepia.hesge.ch:user:scalp_axi4lite:1.0\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
"
......@@ -200,10 +202,17 @@ proc create_root_design { parentCell } {
CONFIG.FREQ_HZ {125000000} \
] $FclkClk0xCO
set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
set InterruptxSI [ create_bd_port -dir I -type intr InterruptxSI ]
set RdAddrxDO [ create_bd_port -dir O -from 11 -to 0 RdAddrxDO ]
set RdDataxDI [ create_bd_port -dir I -from 31 -to 0 RdDataxDI ]
set RdValidxSO [ create_bd_port -dir O RdValidxSO ]
set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
set WrAddrxDO [ create_bd_port -dir O -from 11 -to 0 WrAddrxDO ]
set WrDataxDO [ create_bd_port -dir O -from 31 -to 0 WrDataxDO ]
set WrValidxSO [ create_bd_port -dir O WrValidxSO ]
# Create instance: gnd_constant, and set properties
set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
......@@ -211,6 +220,12 @@ proc create_root_design { parentCell } {
CONFIG.CONST_VAL {0} \
] $gnd_constant
# Create instance: irq_xlconcat, and set properties
set irq_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 irq_xlconcat ]
set_property -dict [ list \
CONFIG.NUM_PORTS {1} \
] $irq_xlconcat
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
......@@ -317,6 +332,7 @@ proc create_root_design { parentCell } {
CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {35} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1750.000} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_MIO_0_DIRECTION {inout} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_0_PULLUP {enabled} \
......@@ -620,8 +636,22 @@ proc create_root_design { parentCell } {
CONFIG.PCW_USB1_RESET_ENABLE {0} \
CONFIG.PCW_USB_RESET_ENABLE {1} \
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_S_AXI_GP0 {0} \
] $processing_system7_0
# Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
] $ps7_0_axi_periph
# Create instance: rst_ps7_0_125M, and set properties
set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
# Create instance: scalp_axi4lite_0, and set properties
set scalp_axi4lite_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_axi4lite:1.0 scalp_axi4lite_0 ]
# Create instance: util_vector_logic_0, and set properties
set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
set_property -dict [ list \
......@@ -648,20 +678,33 @@ proc create_root_design { parentCell } {
# Create interface connections
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO]
# Create port connections
connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
connect_bd_net -net RdDataxDI_0_1 [get_bd_ports RdDataxDI] [get_bd_pins scalp_axi4lite_0/RdDataxDI]
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI]
connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO]
connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
connect_bd_net -net scalp_axi4lite_0_WrAddrxDO [get_bd_ports WrAddrxDO] [get_bd_pins scalp_axi4lite_0/WrAddrxDO]
connect_bd_net -net scalp_axi4lite_0_WrDataxDO [get_bd_ports WrDataxDO] [get_bd_pins scalp_axi4lite_0/WrDataxDO]
connect_bd_net -net scalp_axi4lite_0_WrValidxSO [get_bd_ports WrValidxSO] [get_bd_pins scalp_axi4lite_0/WrValidxSO]
connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
# Create address segments
assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr] -force
# Restore current instance
......@@ -679,3 +722,4 @@ proc create_root_design { parentCell } {
create_root_design ""
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