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Commit 5971938c authored by joachim.schmidt's avatar joachim.schmidt
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Creation of three packages for the SCALP project.

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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-09-21 10:57:55
#
##################################################################################
echo "> Open Vivado GUI..."
vivado -nojournal -nolog -notrace ../aurora_status_pkg/aurora_status_pkg.xpr
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Project management utilities
#
# Last update: 2020-09-21 10:57:55
#
##################################################################################
# findFiles
# basedir - the directory to start looking in
# pattern - A pattern, as defined by the glob command, that the files must match
proc findFiles { basedir pattern } {
# Fix the directory name, this ensures the directory name is in the
# native format for the platform and contains a final directory seperator
set basedir [string trimright [file join [file normalize $basedir] { }]]
set fileList {}
# Look in the current directory for matching files, -type {f r}
# means ony readable normal files are looked at, -nocomplain stops
# an error being thrown if the returned list is empty
foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
lappend fileList $fileName
}
# Now look for any sub direcories in the current directory
foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
# Recusively call the routine on the sub directory and append any
# new files to the results
set subDirList [findFiles $dirName $pattern]
if { [llength $subDirList] > 0 } {
foreach subDirFile $subDirList {
lappend fileList $subDirFile
}
}
}
return $fileList
}
# Print a progress status
# str The string describing the current status
# status The status as a string (eg. "OK", "FAILED")
proc print_status {str status} {
set MAX_STR_LENGTH 70
source .prompt_colors.tcl
puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
}
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: aurora_status_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2020-09-21 10:57:55
#
##################################################################################
# Create aliases
alias create_project='cd .scripts && ./create_prj_aurora_status_pkg.sh && cd ..'
alias clean_project='cd .scripts && ./clean_prj_aurora_status_pkg.sh && cd ..'
alias export_hw='cd .scripts && ./export_hw_aurora_status_pkg.sh && cd ..'
alias gen_bitstream='cd .scripts && ./gen_bitstream_aurora_status_pkg.sh && cd ..'
alias load_bitstream='cd .scripts && ./load_bitstream_aurora_status_pkg.sh && cd ..'
alias gen_sw_apps='cd .scripts && ./gen_sw_apps_aurora_status_pkg.sh && cd ..'
alias load_sw_app='cd .scripts && ./load_sw_app_aurora_status_pkg.sh && cd ..'
alias open_gui='cd .scripts && ./open_prj_aurora_status_pkg.sh && cd ..'
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Console color print utility
#
# Last update: 2020-09-21 10:58:57
#
##################################################################################
# Text attributes
set RESET [exec tput sgr0]
set BOLD [exec tput bold]
set ITALIC [exec tput sitm]
set BLINK [exec tput blink]
set HIGHL [exec tput smso]
# Text colors
set RED [exec tput setaf 1]
set GREEN [exec tput setaf 2]
set YELLOW [exec tput setaf 3]
set BLUE [exec tput setaf 4]
set MAGENTA [exec tput setaf 5]
set CYAN [exec tput setaf 6]
set WHITE [exec tput setaf 7]
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Cleanup project directory
#
# Last update: 2020-09-21 10:58:57
#
##################################################################################
echo "> Cleanup project directory..."
PRJ_DIR=..
# Clean current directory
rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory
rm -rf ${PRJ_DIR}/axi4_pkg/ 2> /dev/null
# Clean app directory
rm ${PRJ_DIR}/app/*.h 2> /dev/null
rm ${PRJ_DIR}/app/*.c 2> /dev/null
rm ${PRJ_DIR}/app/*.html 2> /dev/null
echo "> Done"
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-09-21 10:58:57
#
##################################################################################
echo "> Create Vivado project..."
vivado -nojournal -nolog -mode tcl -source create_prj_axi4_pkg.tcl -notrace
echo "> Done"
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'axi4_pkg'
#
# Last update: 2020-09-21 10:58:57
#
##################################################################################
# Include files
source utils.tcl
set PRJ_DIR ".."
set prj_name "axi4_pkg"
set PKG_DIR "${PRJ_DIR}/../../../../../packages"
set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
# Set project type
set PRJ_TYPE "COMP_PRJ_TYPE"
# Create a variable to store the start time
set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../packages/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
set pkg_src_dir "${PKG_DIR}/hw"
set soc_src_dir "${SOC_DIR}/hw"
print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
set_property board_part SCALP [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset]
update_ip_catalog
#----------------------------------------------------------------
# Add project sources
#----------------------------------------------------------------
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file
#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
# Create the IP Integrator portion of the design
#create_bd_design "axi_design"
#update_compile_order -fileset sources_1
# launch the TCL script to generate the IPI design
source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
print_status "Add IPI design" "OK"
# Set the top level design
set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1
# Add testbench sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $src_dir/sim *.v]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
}
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources
# Add SoC wrapper sources files
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Display the start and end time to the screen
puts $start_time
puts $end_time
exit
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-09-21 10:58:57
#
##################################################################################
echo "> Open Vivado GUI..."
vivado -nojournal -nolog -notrace ../axi4_pkg/axi4_pkg.xpr
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Project management utilities
#
# Last update: 2020-09-21 10:58:57
#
##################################################################################
# findFiles
# basedir - the directory to start looking in
# pattern - A pattern, as defined by the glob command, that the files must match
proc findFiles { basedir pattern } {
# Fix the directory name, this ensures the directory name is in the
# native format for the platform and contains a final directory seperator
set basedir [string trimright [file join [file normalize $basedir] { }]]
set fileList {}
# Look in the current directory for matching files, -type {f r}
# means ony readable normal files are looked at, -nocomplain stops
# an error being thrown if the returned list is empty
foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
lappend fileList $fileName
}
# Now look for any sub direcories in the current directory
foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
# Recusively call the routine on the sub directory and append any
# new files to the results
set subDirList [findFiles $dirName $pattern]
if { [llength $subDirList] > 0 } {
foreach subDirFile $subDirList {
lappend fileList $subDirFile
}
}
}
return $fileList
}
# Print a progress status
# str The string describing the current status
# status The status as a string (eg. "OK", "FAILED")
proc print_status {str status} {
set MAX_STR_LENGTH 70
source .prompt_colors.tcl
puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
}
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: axi4_pkg
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2020-09-21 10:58:57
#
##################################################################################
# Create aliases
alias create_project='cd .scripts && ./create_prj_axi4_pkg.sh && cd ..'
alias clean_project='cd .scripts && ./clean_prj_axi4_pkg.sh && cd ..'
alias export_hw='cd .scripts && ./export_hw_axi4_pkg.sh && cd ..'
alias gen_bitstream='cd .scripts && ./gen_bitstream_axi4_pkg.sh && cd ..'
alias load_bitstream='cd .scripts && ./load_bitstream_axi4_pkg.sh && cd ..'
alias gen_sw_apps='cd .scripts && ./gen_sw_apps_axi4_pkg.sh && cd ..'
alias load_sw_app='cd .scripts && ./load_sw_app_axi4_pkg.sh && cd ..'
alias open_gui='cd .scripts && ./open_prj_axi4_pkg.sh && cd ..'
{
"author": {
"name": "Joachim Schmidt",
"email": "<joachim.schmidt@hesge.ch>"
},
"project": {
"name": "aurora_drp_pkg",
"type": "COMP_PRJ_TYPE",
"category": "PACKAGES",
"vivado_version": "2019.2",
"target_language": "VHDL",
"vhdl_version": "VHDL 2008"
},
"hardware": {
"part_name": "xc7z015clg485-2",
"board_name": "SCALP"
}
}
{
"author": {
"name": "Joachim Schmidt",
"email": "<joachim.schmidt@hesge.ch>"
},
"project": {
"name": "aurora_status_pkg",
"type": "COMP_PRJ_TYPE",
"category": "PACKAGES",
"vivado_version": "2019.2",
"target_language": "VHDL",
"vhdl_version": "VHDL 2008"
},
"hardware": {
"part_name": "xc7z015clg485-2",
"board_name": "SCALP"
}
}
{
"author": {
"name": "Joachim Schmidt",
"email": "<joachim.schmidt@hesge.ch>"
},
"project": {
"name": "axi4_pkg",
"type": "COMP_PRJ_TYPE",
"category": "PACKAGES",
"vivado_version": "2019.2",
"target_language": "VHDL",
"vhdl_version": "VHDL 2008"
},
"hardware": {
"part_name": "xc7z015clg485-2",
"board_name": "SCALP"
}
}
...@@ -14,5 +14,15 @@ ...@@ -14,5 +14,15 @@
"hardware" : { "hardware" : {
"part_name" : "xc7z015clg485-2", "part_name" : "xc7z015clg485-2",
"board_name" : "SCALP" "board_name" : "SCALP"
},
"components" : {
"packages" : {
"aurora_drp_pkg" : "true",
"aurora_status_pkg" : "true",
"axi4_pkg" : "true"
},
"soc" : {
"scalp_zynqps" : "true"
}
} }
} }
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