Firmware with four GTP interfaces (north, east, south, west) and congestion...

Firmware with four GTP interfaces (north, east, south, west) and congestion management and with Zynq SoC.

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Console color print utility
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Cleanup project directory
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Create Vivado project
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script for re-creating Vivado project 'scalp_firmware'
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 
@@ -44,7 +44,7 @@ print_status "Set directory paths" "OK"
 
 # Create the project
 create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
-#set_property board_part SCALP [current_project]
+set_property board_part SCALP [current_project]
 set_property target_language VHDL [current_project]
 print_status "Create project" "OK"
 
@@ -96,6 +96,7 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
 	}
 	read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
 	read_ip ${ip_dir}/scalp_packet_fifo_wrapper/src/ip_core/scalp_packet_fifo/scalp_packet_fifo.xci
+	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Export the hardware design to SDK
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Export the hardware design to SDK
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Generate bitstream file
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to generate bitstream file
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Generate software application
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to generate software application
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Load bitstream file
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to load FPGA bitstream
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Load software application
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to load software application
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Create Vivado project
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Project management utilities
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/lin64/setup.sh

@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script creating aliases for Vivado project management scripts
 #
-# Last update: 2020-11-08 11:36:32
+# Last update: 2020-11-25 14:35:23
 #
 ##################################################################################
 

designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc

+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 4 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {SouthWritePhyStatexDP[0]} {SouthWritePhyStatexDP[1]} {SouthWritePhyStatexDP[2]} {SouthWritePhyStatexDP[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 4 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {SouthRXM2SxD[KeepxD][3]} {SouthRXM2SxD[KeepxD][2]} {SouthRXM2SxD[KeepxD][1]} {SouthRXM2SxD[KeepxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 32 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {SouthRXM2SxD[DataxD][31]} {SouthRXM2SxD[DataxD][30]} {SouthRXM2SxD[DataxD][29]} {SouthRXM2SxD[DataxD][28]} {SouthRXM2SxD[DataxD][27]} {SouthRXM2SxD[DataxD][26]} {SouthRXM2SxD[DataxD][25]} {SouthRXM2SxD[DataxD][24]} {SouthRXM2SxD[DataxD][23]} {SouthRXM2SxD[DataxD][22]} {SouthRXM2SxD[DataxD][21]} {SouthRXM2SxD[DataxD][20]} {SouthRXM2SxD[DataxD][19]} {SouthRXM2SxD[DataxD][18]} {SouthRXM2SxD[DataxD][17]} {SouthRXM2SxD[DataxD][16]} {SouthRXM2SxD[DataxD][15]} {SouthRXM2SxD[DataxD][14]} {SouthRXM2SxD[DataxD][13]} {SouthRXM2SxD[DataxD][12]} {SouthRXM2SxD[DataxD][11]} {SouthRXM2SxD[DataxD][10]} {SouthRXM2SxD[DataxD][9]} {SouthRXM2SxD[DataxD][8]} {SouthRXM2SxD[DataxD][7]} {SouthRXM2SxD[DataxD][6]} {SouthRXM2SxD[DataxD][5]} {SouthRXM2SxD[DataxD][4]} {SouthRXM2SxD[DataxD][3]} {SouthRXM2SxD[DataxD][2]} {SouthRXM2SxD[DataxD][1]} {SouthRXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 4 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {NorthWritePhyStatexDP[0]} {NorthWritePhyStatexDP[1]} {NorthWritePhyStatexDP[2]} {NorthWritePhyStatexDP[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 4 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {NorthRXM2SxD[KeepxD][3]} {NorthRXM2SxD[KeepxD][2]} {NorthRXM2SxD[KeepxD][1]} {NorthRXM2SxD[KeepxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 32 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {NorthRXM2SxD[DataxD][31]} {NorthRXM2SxD[DataxD][30]} {NorthRXM2SxD[DataxD][29]} {NorthRXM2SxD[DataxD][28]} {NorthRXM2SxD[DataxD][27]} {NorthRXM2SxD[DataxD][26]} {NorthRXM2SxD[DataxD][25]} {NorthRXM2SxD[DataxD][24]} {NorthRXM2SxD[DataxD][23]} {NorthRXM2SxD[DataxD][22]} {NorthRXM2SxD[DataxD][21]} {NorthRXM2SxD[DataxD][20]} {NorthRXM2SxD[DataxD][19]} {NorthRXM2SxD[DataxD][18]} {NorthRXM2SxD[DataxD][17]} {NorthRXM2SxD[DataxD][16]} {NorthRXM2SxD[DataxD][15]} {NorthRXM2SxD[DataxD][14]} {NorthRXM2SxD[DataxD][13]} {NorthRXM2SxD[DataxD][12]} {NorthRXM2SxD[DataxD][11]} {NorthRXM2SxD[DataxD][10]} {NorthRXM2SxD[DataxD][9]} {NorthRXM2SxD[DataxD][8]} {NorthRXM2SxD[DataxD][7]} {NorthRXM2SxD[DataxD][6]} {NorthRXM2SxD[DataxD][5]} {NorthRXM2SxD[DataxD][4]} {NorthRXM2SxD[DataxD][3]} {NorthRXM2SxD[DataxD][2]} {NorthRXM2SxD[DataxD][1]} {NorthRXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 4 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 4 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[KeepxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[KeepxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[KeepxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[KeepxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 32 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 4 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 4 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[KeepxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[KeepxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[KeepxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[KeepxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 32 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 2 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXFifoResetDoneStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXFifoResetDoneStatexDP[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 3 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthNFCStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthNFCStatexDP[1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthNFCStatexDP[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 4 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 4 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[KeepxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[KeepxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[KeepxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[KeepxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+set_property port_width 32 [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+set_property port_width 4 [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+set_property port_width 4 [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[KeepxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[KeepxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[KeepxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[KeepxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+set_property port_width 32 [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[DataxD][0]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+set_property port_width 2 [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXFifoResetDoneStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXFifoResetDoneStatexDP[1]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+set_property port_width 3 [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthNFCStatexDP[0]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthNFCStatexDP[1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthNFCStatexDP[2]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+set_property port_width 1 [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthProgEmptyxSP]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+set_property port_width 1 [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthProgFullxSP]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+set_property port_width 1 [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {NorthRXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+set_property port_width 1 [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+set_property port_width 1 [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+set_property port_width 1 [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {NorthRXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+set_property port_width 1 [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthRXNFCM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+set_property port_width 1 [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {NorthRXS2MxD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+set_property port_width 1 [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXNFCS2MxD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/NorthTXS2MxD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[EastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[NorthxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[SouthxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDoneDelayedxD[WestxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[EastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[NorthxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[SouthxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/RXFifoResetDonexD[WestxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthProgEmptyxSP]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+set_property port_width 1 [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthProgFullxSP]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list {SouthRXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
+set_property port_width 1 [get_debug_ports u_ila_0/probe48]
+connect_debug_port u_ila_0/probe48 [get_nets [list {SouthRXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
+set_property port_width 1 [get_debug_ports u_ila_0/probe49]
+connect_debug_port u_ila_0/probe49 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthRXNFCM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
+set_property port_width 1 [get_debug_ports u_ila_0/probe50]
+connect_debug_port u_ila_0/probe50 [get_nets [list {SouthRXS2MxD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
+set_property port_width 1 [get_debug_ports u_ila_0/probe51]
+connect_debug_port u_ila_0/probe51 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[LastxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
+set_property port_width 1 [get_debug_ports u_ila_0/probe52]
+connect_debug_port u_ila_0/probe52 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
+set_property port_width 1 [get_debug_ports u_ila_0/probe53]
+connect_debug_port u_ila_0/probe53 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCM2SxD[ValidxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
+set_property port_width 1 [get_debug_ports u_ila_0/probe54]
+connect_debug_port u_ila_0/probe54 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXNFCS2mxD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
+set_property port_width 1 [get_debug_ports u_ila_0/probe55]
+connect_debug_port u_ila_0/probe55 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/SouthTXS2MxD[ReadyxS]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
+set_property port_width 1 [get_debug_ports u_ila_0/probe56]
+connect_debug_port u_ila_0/probe56 [get_nets [list {DebugCounterResetxR[EastxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
+set_property port_width 1 [get_debug_ports u_ila_0/probe57]
+connect_debug_port u_ila_0/probe57 [get_nets [list {DebugCounterResetxR[NorthxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
+set_property port_width 1 [get_debug_ports u_ila_0/probe58]
+connect_debug_port u_ila_0/probe58 [get_nets [list {DebugCounterResetxR[SouthxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
+set_property port_width 1 [get_debug_ports u_ila_0/probe59]
+connect_debug_port u_ila_0/probe59 [get_nets [list {DebugCounterResetxR[WestxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
+set_property port_width 1 [get_debug_ports u_ila_0/probe60]
+connect_debug_port u_ila_0/probe60 [get_nets [list {DebugRXFifoResetxR[EastxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
+set_property port_width 1 [get_debug_ports u_ila_0/probe61]
+connect_debug_port u_ila_0/probe61 [get_nets [list {DebugRXFifoResetxR[NorthxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
+set_property port_width 1 [get_debug_ports u_ila_0/probe62]
+connect_debug_port u_ila_0/probe62 [get_nets [list {DebugRXFifoResetxR[SouthxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
+set_property port_width 1 [get_debug_ports u_ila_0/probe63]
+connect_debug_port u_ila_0/probe63 [get_nets [list {DebugRXFifoResetxR[WestxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
+set_property port_width 1 [get_debug_ports u_ila_0/probe64]
+connect_debug_port u_ila_0/probe64 [get_nets [list {DebugBackPressureResetxR[EastxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
+set_property port_width 1 [get_debug_ports u_ila_0/probe65]
+connect_debug_port u_ila_0/probe65 [get_nets [list {DebugBackPressureResetxR[NorthxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
+set_property port_width 1 [get_debug_ports u_ila_0/probe66]
+connect_debug_port u_ila_0/probe66 [get_nets [list {DebugBackPressureResetxR[SouthxR]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
+set_property port_width 1 [get_debug_ports u_ila_0/probe67]
+connect_debug_port u_ila_0/probe67 [get_nets [list {DebugBackPressureResetxR[WestxR]}]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]

designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd

@@ -15,7 +15,7 @@
 -- Tool version: 2019.2
 -- Description: Testbench for scalp_firmware
 --
--- Last update: 2020-11-07 09:14:14
+-- Last update: 2020-11-25 14:35:23
 --
 ---------------------------------------------------------------------------------