Modification of variable names in the TCL script create_prj_scalp_firmware.tcl...

Modification of variable names in the TCL script create_prj_scalp_firmware.tcl of the project design.

designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl

@@ -37,6 +37,7 @@ set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
 set comp_dir "${ip_dir}/$prj_name"
 set comp_src_dir "${comp_dir}/src"
 # USER DEFINE
+set lib_dir "${PRJ_DIR}/../../../../../lib/${prj_name}_hdl_lib/hw/src"
 #set PRJ_ZYNPS "scalp_zynqps"
 #set zynqps_dir "${PRJ_DIR}/../../../../../soc/hw/${scalp_zynqps}/src"
 ##
@@ -59,20 +60,40 @@ update_ip_catalog
 
 if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
 	# add HDL sources
-	set hdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+	set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
 	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
-	set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
+    #USER DEFINE
+    set vhdl_lib_src_file_list [findFiles $lib_dir/hdl *.vhd]
+    set verilog_lib_src_file_list [findFiles $lib_dir/hdl *.v]
+    ##
+	set vhdl_src_file_list [list {*}$vhdl_src_file_list {*}$vhdl_lib_src_file_list]
+    set verilog_src_file_list [list {*}$verilog_src_file_list {*}$verilog_lib_src_file_list]
+    ##
+    set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]   
+    
 	add_files -norecurse $hdl_src_file_list
 	# add the constraints file (XDC)
 	add_files -fileset constrs_1 -norecurse  $src_dir/constrs/${prj_name}.xdc
+    # USER DEFINE
+    add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
+    add_files -fileset constrs_1 -norecurse  $src_dir/constrs/debug.xdc
+    add_files -fileset constrs_1 -norecurse  $src_dir/constrs/timing_constraints.xdc
 	# add IPs source file
 	#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
 } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
 	# components sources are stored in an external directory
 	# add the project component
-	set hdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+	set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
 	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
-	set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
+    #USER DEFINE
+    set vhdl_lib_src_file_list [findFiles $lib_dir/hdl *.vhd]    
+    set verilog_lib_src_file_list [findFiles $lib_dir/hdl *.v]
+
+    set vhdl_src_file_list [list {*}$vhdl_src_file_list {*}$vhdl_lib_src_file_list]
+    set verilog_src_file_list [list {*}$verilog_src_file_list {*}$verilog_lib_src_file_list]
+    ##
+    set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+    
 	add_files -norecurse $hdl_src_file_list
 	# add IPs source file
 	#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
@@ -81,6 +102,13 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
 }
 print_status "Add project sources" "OK"
 
+foreach j $vhdl_src_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
 # Set packages libraries if any
 #set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
 #update_compile_order -fileset sources_1
@@ -99,17 +127,24 @@ update_compile_order -fileset sources_1
 
 # Add testbench sources
 if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	set hdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+	set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
 	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
 } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
-	set hdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+	set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
 	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
 }
-set hdl_sim_file_list [list {*}$hdl_sim_file_list {*}$verilog_sim_file_list]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
 add_files -fileset sim_1 -norecurse $hdl_sim_file_list
 update_compile_order -fileset sim_1
 print_status "Add testbench sources" "OK"
 
+foreach j $vhdl_sim_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
 # Set the completion time
 set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
 

designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd

@@ -270,22 +270,22 @@ end scalp_firmware;
 architecture arch of scalp_firmware is
 
     -- Constantes
-    constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
+    -- constant C_PS_SYS_RESET_SIZE : integer range 0 to 7 := 1;
 
     -- Signals
     -- Clocks
     -- Processing system clock
-    signal PSSysClkxC   : std_logic                                            := '0';
+    signal PSSysClkxC   : std_logic := '0';
     -- GTP Clocks
-    signal GTPRefClk0xC : std_logic                                            := '0';
-    signal GTPRefClk1xC : std_logic                                            := '0';
+    signal GTPRefClk0xC : std_logic := '0';
+    signal GTPRefClk1xC : std_logic := '0';
     -- Resets
     -- Processing system reset
-    signal PSSysResetxR : std_logic_vector((C_PS_SYS_RESET_SIZE - 1) downto 0) := (others => '0');
+    signal PSSysResetxR : std_logic := '0';
 
     -- Attributes
-    attribute mark_debug : string;
-    attribute keep       : string;
+    attribute mark_debug                 : string;
+    attribute keep                       : string;
     -- Clocks
     attribute mark_debug of PSSysClkxC   : signal is "true";
     attribute keep of PSSysClkxC         : signal is "true";
@@ -302,7 +302,7 @@ begin
     ProcessingSystemxB : block is
     begin  -- block ProcessingSystemxB
 
-        ZynqxI : entity work.scalp_firmware_ps
+        ZynqxI : entity work.scalp_zynqps_wrapper
             port map (
                 -- Processor interface
                 FIXED_IO_ps_clk     => PSClkxCIO,