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Commit 89df81f8 authored by joachim.schmidt's avatar joachim.schmidt
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Delete main design project.

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designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl deleted 100644 → 0
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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Console color print utility
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
# Text attributes
set RESET [exec tput sgr0]
set BOLD [exec tput bold]
set ITALIC [exec tput sitm]
set BLINK [exec tput blink]
set HIGHL [exec tput smso]
# Text colors
set RED [exec tput setaf 1]
set GREEN [exec tput setaf 2]
set YELLOW [exec tput setaf 3]
set BLUE [exec tput setaf 4]
set MAGENTA [exec tput setaf 5]
set CYAN [exec tput setaf 6]
set WHITE [exec tput setaf 7]
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh deleted 100755 → 0
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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Cleanup project directory
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
echo "> Cleanup project directory..."
PRJ_DIR=..
# Clean current directory
rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory
rm -rf ${PRJ_DIR}/scalp_firmware/ 2> /dev/null
# Clean app directory
rm ${PRJ_DIR}/app/*.h 2> /dev/null
rm ${PRJ_DIR}/app/*.c 2> /dev/null
rm ${PRJ_DIR}/app/*.html 2> /dev/null
echo "> Done"
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh deleted 100755 → 0
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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
echo "> Create Vivado project..."
vivado -nojournal -nolog -mode tcl -source create_prj_scalp_firmware.tcl -notrace
echo "> Done"
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl deleted 100644 → 0
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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware'
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
# Include files
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_firmware"
# Set project type
set PRJ_TYPE "DESIGN_PRJ_TYPE"
# Create a variable to store the start time
set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
# USER DEFINE
set lib_dir "${PRJ_DIR}/../../../../../lib/${prj_name}_hdl_lib/hw/src"
#set PRJ_ZYNPS "scalp_zynqps"
#set zynqps_dir "${PRJ_DIR}/../../../../../soc/hw/${scalp_zynqps}/src"
##
print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
#set_property board_part SCALP [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset]
update_ip_catalog
#----------------------------------------------------------------
# Add project sources
#----------------------------------------------------------------
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
#USER DEFINE
set vhdl_lib_src_file_list [findFiles $lib_dir/hdl *.vhd]
set verilog_lib_src_file_list [findFiles $lib_dir/hdl *.v]
##
set vhdl_src_file_list [list {*}$vhdl_src_file_list {*}$vhdl_lib_src_file_list]
set verilog_src_file_list [list {*}$verilog_src_file_list {*}$verilog_lib_src_file_list]
##
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# USER DEFINE
add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
# add IPs source file
#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
#USER DEFINE
set vhdl_lib_src_file_list [findFiles $lib_dir/hdl *.vhd]
set verilog_lib_src_file_list [findFiles $lib_dir/hdl *.v]
set vhdl_src_file_list [list {*}$vhdl_src_file_list {*}$vhdl_lib_src_file_list]
set verilog_src_file_list [list {*}$verilog_src_file_list {*}$verilog_lib_src_file_list]
##
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
# Create the IP Integrator portion of the design
#create_bd_design "axi_design"
#update_compile_order -fileset sources_1
# launch the TCL script to generate the IPI design
source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
print_status "Add IPI design" "OK"
# Set the top level design
set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1
# Add testbench sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $src_dir/sim *.v]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
}
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Display the start and end time to the screen
puts $start_time
puts $end_time
exit
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh deleted 100755 → 0
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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
echo "> Export the hardware design to SDK"
vivado -nojournal -nolog -mode tcl -source ./export_hw_scalp_firmware.tcl -notrace
echo "> Done"
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl deleted 100644 → 0
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View file @ 1680a27c
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
source utils.tcl
set PRJ_DIR ".."
# Initialize workspace directories name
set prj_name "scalp_firmware"
set impl_dir "${PRJ_DIR}/${prj_name}/${prj_name}.runs/impl_1/"
set export_dir "${PRJ_DIR}/${prj_name}/${prj_name}.sdk"
print_status "Initialize workspace directories name" "OK"
# Open the project
open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
print_status "Open project $prj_name" "OK"
# export the hardware
file mkdir $export_dir
file copy -force $impl_dir/$prj_name.sysdef $export_dir/$prj_name.hdf
print_status "Export hardware to SDK" "OK"
exit
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh deleted 100755 → 0
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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Generate bitstream file
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
PRJ_DIR=..
echo "> Generate bitstream file..."
vivado -nojournal -nolog -mode tcl -source ./gen_bitstream_scalp_firmware.tcl -notrace
echo "> Copy bitstream file in current directory..."
mkdir -p ${PRJ_DIR}/bitstream/
cp ${PRJ_DIR}/scalp_firmware/scalp_firmware.runs/impl_1/scalp_firmware.bit ${PRJ_DIR}/bitstream/scalp_firmware.bit
echo "> Done"
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl deleted 100644 → 0
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#!/usr/bin/tcl
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script used to generate bitstream file
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_firmware"
# Create a variable to store the start time
set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Open the project
open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
update_compile_order -fileset sources_1
print_status "Open project $prj_name" "OK"
# Run synthesis
print_status "Run synthesis" "IN_PROGRESS"
launch_runs synth_1
wait_on_run synth_1
print_status "Run synthesis" "OK"
# Run implementation
print_status "Run implementation" "IN_PROGRESS"
launch_runs impl_1 -to_step write_bitstream -jobs 8
wait_on_run impl_1
print_status "Run implementation" "OK"
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Display the start and end time on the screen
puts $start_time
puts $end_time
exit
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh deleted 100755 → 0
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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Generate software application
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
PRJ_DIR=..
echo "> Generate software applications..."
xsdk -batch -source ./gen_sw_apps_scalp_firmware.tcl -notrace
echo "> Copy application file in current directory..."
mkdir -p ${PRJ_DIR}/app/
cp ${PRJ_DIR}/scalp_firmware/scalp_firmware.sdk/scalp_firmware_app/Debug/scalp_firmware_app.elf ${PRJ_DIR}/app/scalp_firmware_app.elf
cp ${PRJ_DIR}/scalp_firmware/scalp_firmware.sdk/scalp_firmware_hw_platform_0/system.hdf ${PRJ_DIR}/app/scalp_firmware.hdf
cp ${PRJ_DIR}/scalp_firmware/scalp_firmware.sdk/scalp_firmware_hw_platform_0/ps7_init.tcl ${PRJ_DIR}/app/ps7_init.tcl
echo "> Done"
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl deleted 100644 → 0
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#!/usr/bin/tcl
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script used to generate software application
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_firmware"
set workspace_dir "${PRJ_DIR}/$prj_name/$prj_name.sdk/"
set hw_spec_file "$prj_name.hdf"
set hw_platform_name "${prj_name}_hw_platform_0"
set proc_name "ps7_cortexa9_0"
set os_name "freertos823_xilinx"
set bsp_name "${prj_name}_bsp"
set app_name "${prj_name}_app"
# Set the SDK workspace
setws $workspace_dir
print_status "Set workspace directory" "OK"
# Create the hardware project
sdk createhw -name $hw_platform_name -hwspec $workspace_dir/$hw_spec_file
print_status "Create hardware project" "OK"
# Create the FreeRTOS BSP
sdk createbsp -name $bsp_name -hwproject $hw_platform_name -proc $proc_name -os $os_name
print_status "Create FreeRTOS BSP project" "OK"
# Create the empty application
sdk createapp -name $app_name -hwproject $hw_platform_name -proc $proc_name -lang C -app {Empty Application} -os $os_name -bsp $bsp_name
print_status "Create Empty Application project" "OK"
# Import source files
sdk importsources -name $app_name -path ${PRJ_DIR}/../src/sw/ -linker-script
print_status "Import project source files" "OK"
# Set the include directories
configapp -app $app_name include-path "${PRJ_DIR}/../src/inc/"
configapp -app $app_name include-path "${PRJ_DIR}/../src/lib/"
configapp -app $app_name include-path "${PRJ_DIR}/../src/mod/"
print_status "Set includes directories" "OK"
# Build the projects
print_status "Build BSP project" "IN_PROGRESS"
sdk projects -build -type bsp -name $bsp_name
print_status "Build BSP project" "OK"
print_status "Build application project" "IN_PROGRESS"
sdk projects -build -type app -name $app_name
print_status "Build application project" "OK"
exit
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh deleted 100755 → 0
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View file @ 1680a27c
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Load bitstream file
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
echo "> Load bitstream file..."
vivado -nojournal -nolog -mode tcl -source ./load_bitstream_scalp_firmware.tcl -notrace
echo "> Done"
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl deleted 100644 → 0
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− 61
View file @ 1680a27c
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script used to load FPGA bitstream
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_firmware"
# Open the hardware manager and connect to the hardware server
open_hw
print_status "Open hardware manager" "OK"
connect_hw_server -url localhost:3121
print_status "Connect to hardware server" "OK"
# Get the hardware target and open it
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
open_hw_target
print_status "Open hardware target" "OK"
# Display targets list
set index -1
set targets [lindex [get_hw_devices]]
puts "Found target(s):"
foreach target $targets {
incr index
puts "$index : $target"
}
puts "Which target do you want to program?"
set sel_target [read stdin 1]
# Set the program file
set_property PROGRAM.FILE ${PRJ_DIR}/bitstream/$prj_name.bit [lindex [get_hw_devices] $sel_target]
current_hw_device [lindex [get_hw_devices] $sel_target]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] $sel_target]
print_status "Set program file" "OK"
# Program the device
print_status "Program device" "IN_PROGRESS"
program_hw_device [lindex [get_hw_devices] $sel_target]
print_status "Program device" "OK"
exit
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh deleted 100755 → 0
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View file @ 1680a27c
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Load software application
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
echo "> Load software application..."
xsdk -batch -source ./load_sw_app_scalp_firmware.tcl -notrace
echo "> Done"
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl deleted 100644 → 0
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View file @ 1680a27c
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script used to load software application
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_firmware"
set hw_platform_name "${prj_name}_hw_platform_0"
set app_name "${prj_name}_app"
# Connect to the hardware server
connect -url tcp:127.0.0.1:3121
print_status "Connect to hardware server" "OK"
# Connect to the processor
targets 2
print_status "Connect to ARM Cortex-A9 MPCore #0" "OK"
# Load the hardware design
loadhw -hw ${PRJ_DIR}/app/$prj_name.hdf
print_status "Load hardware design" "OK"
# Reset the processor
rst -processor
print_status "Reset ARM Cortex-A9 MPCore #0" "OK"
# Initialize the MPSoC
source ${PRJ_DIR}/app/ps7_init.tcl
ps7_init
ps7_post_config
print_status "Initialize PS7" "OK"
# Load the application
dow ${PRJ_DIR}/app/$app_name.elf
print_status "Load software application" "OK"
# Run the application
con
print_status "Run software application" "OK"
# Disconnect from the target
disconnect
print_status "Disconnect from hardware server" "OK"
exit
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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
echo "> Open Vivado GUI..."
vivado -nojournal -nolog -notrace ../scalp_firmware/scalp_firmware.xpr
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl deleted 100644 → 0
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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Project management utilities
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
# findFiles
# basedir - the directory to start looking in
# pattern - A pattern, as defined by the glob command, that the files must match
proc findFiles { basedir pattern } {
# Fix the directory name, this ensures the directory name is in the
# native format for the platform and contains a final directory seperator
set basedir [string trimright [file join [file normalize $basedir] { }]]
set fileList {}
# Look in the current directory for matching files, -type {f r}
# means ony readable normal files are looked at, -nocomplain stops
# an error being thrown if the returned list is empty
foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
lappend fileList $fileName
}
# Now look for any sub direcories in the current directory
foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
# Recusively call the routine on the sub directory and append any
# new files to the results
set subDirList [findFiles $dirName $pattern]
if { [llength $subDirList] > 0 } {
foreach subDirFile $subDirList {
lappend fileList $subDirFile
}
}
}
return $fileList
}
# Print a progress status
# str The string describing the current status
# status The status as a string (eg. "OK", "FAILED")
proc print_status {str status} {
set MAX_STR_LENGTH 70
source .prompt_colors.tcl
puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
}
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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2020-09-03 11:28:21
#
##################################################################################
# Create aliases
alias create_project='cd .scripts && ./create_prj_scalp_firmware.sh && cd ..'
alias clean_project='cd .scripts && ./clean_prj_scalp_firmware.sh && cd ..'
alias export_hw='cd .scripts && ./export_hw_scalp_firmware.sh && cd ..'
alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_firmware.sh && cd ..'
alias load_bitstream='cd .scripts && ./load_bitstream_scalp_firmware.sh && cd ..'
alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_firmware.sh && cd ..'
alias load_sw_app='cd .scripts && ./load_sw_app_scalp_firmware.sh && cd ..'
alias open_gui='cd .scripts && ./open_prj_scalp_firmware.sh && cd ..'
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############################################################################
# Programmable Logic placement constraints #
############################################################################
##### USB interface (bank 13) #####
# USB_VBUS_PWRFAULT_i
set_property PACKAGE_PIN AA19 [get_ports UsbVbusPwrFaultxSI]
set_property IOSTANDARD LVCMOS25 [get_ports UsbVbusPwrFaultxSI]
##### PLL interface (banks 35 and 34) #####
# PLL_2V5_CLKuWire_o
set_property PACKAGE_PIN G8 [get_ports Pll2V5ClkuWirexCO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkuWirexCO]
# PLL_2V5_DATAuWire_o
set_property PACKAGE_PIN G7 [get_ports Pll2V5DatauWirexSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5DatauWirexSO]
# PLL_2V5_LEuWire_o
set_property PACKAGE_PIN G6 [get_ports Pll2V5LEuWirexSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LEuWirexSO]
# PLL_2V5_GOE_o
set_property PACKAGE_PIN F6 [get_ports Pll2V5GOExSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5GOExSO]
# PLL_2V5_LD_i
set_property PACKAGE_PIN H6 [get_ports Pll2V5LDxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LDxSI]
# PLL_2V5_SYNC_n_o
set_property PACKAGE_PIN H5 [get_ports Pll2V5SyncxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5SyncxSO]
# PLL_2V5_CLKIN0_LOS_i (bank 34)
set_property PACKAGE_PIN J3 [get_ports Pll2V5ClkIn0LOSxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn0LOSxSI]
# PLL_2V5_CLKIN1_LOS_i (bank 34)
set_property PACKAGE_PIN K2 [get_ports Pll2V5ClkIn1LOSxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
##### GTP interfaces (bank 112) #####
set_property PACKAGE_PIN "U9" [get_ports "GTPRefClk0PxCI"]
set_property PACKAGE_PIN "V9" [get_ports "GTPRefClk0NxCI"]
set_property PACKAGE_PIN "U5" [get_ports "GTPRefClk1PxCI"]
set_property PACKAGE_PIN "V5" [get_ports "GTPRefClk1NxCI"]
set_property PACKAGE_PIN "Y8" [get_ports "GTPFromNorthNxSI"]
set_property PACKAGE_PIN "W8" [get_ports "GTPFromNorthPxSI"]
set_property PACKAGE_PIN "Y4" [get_ports "GTPToNorthNxSO"]
set_property PACKAGE_PIN "W4" [get_ports "GTPToNorthPxSO"]
set_property PACKAGE_PIN "AB7" [get_ports "GTPFromSouthNxSI"]
set_property PACKAGE_PIN "AA7" [get_ports "GTPFromSouthPxSI"]
set_property PACKAGE_PIN "AB3" [get_ports "GTPToSouthNxSO"]
set_property PACKAGE_PIN "AA3" [get_ports "GTPToSouthPxSO"]
set_property PACKAGE_PIN "AA9" [get_ports "GTPFromEastPxSI"]
set_property PACKAGE_PIN "AB9" [get_ports "GTPFromEastNxSI"]
set_property PACKAGE_PIN "AA5" [get_ports "GTPToEastPxSO"]
set_property PACKAGE_PIN "AB5" [get_ports "GTPToEastNxSO"]
set_property PACKAGE_PIN "W6" [get_ports "GTPFromWestPxSI"]
set_property PACKAGE_PIN "Y6" [get_ports "GTPFromWestNxSI"]
set_property PACKAGE_PIN "W2" [get_ports "GTPToWestPxSO"]
set_property PACKAGE_PIN "Y2" [get_ports "GTPToWestNxSO"]
##### LVDS links towards edge connectors #####
# North (bank 35)
set_property PACKAGE_PIN "E8" [get_ports "LVDS2V5North7PxSIO"]
set_property PACKAGE_PIN "D8" [get_ports "LVDS2V5North7NxSIO"]
set_property PACKAGE_PIN "D7" [get_ports "LVDS2V5North6PxSIO"]
set_property PACKAGE_PIN "D6" [get_ports "LVDS2V5North6NxSIO"]
set_property PACKAGE_PIN "C8" [get_ports "LVDS2V5North5PxSIO"]
set_property PACKAGE_PIN "B8" [get_ports "LVDS2V5North5NxSIO"]
set_property PACKAGE_PIN "B7" [get_ports "LVDS2V5North4PxSIO"]
set_property PACKAGE_PIN "B6" [get_ports "LVDS2V5North4NxSIO"]
set_property PACKAGE_PIN "A7" [get_ports "LVDS2V5North3PxSIO"]
set_property PACKAGE_PIN "A6" [get_ports "LVDS2V5North3NxSIO"]
set_property PACKAGE_PIN "A5" [get_ports "LVDS2V5North2PxSIO"]
set_property PACKAGE_PIN "A4" [get_ports "LVDS2V5North2NxSIO"]
set_property PACKAGE_PIN "B2" [get_ports "LVDS2V5North1PxSIO"]
set_property PACKAGE_PIN "B1" [get_ports "LVDS2V5North1NxSIO"]
set_property PACKAGE_PIN "A2" [get_ports "LVDS2V5North0PxSIO"]
set_property PACKAGE_PIN "A1" [get_ports "LVDS2V5North0NxSIO"]
# South (bank 13)
set_property PACKAGE_PIN "V15" [get_ports "LVDS2V5South7PxSIO"]
set_property PACKAGE_PIN "W15" [get_ports "LVDS2V5South7NxSIO"]
set_property PACKAGE_PIN "AB13" [get_ports "LVDS2V5South6PxSIO"]
set_property PACKAGE_PIN "AB14" [get_ports "LVDS2V5South6NxSIO"]
set_property PACKAGE_PIN "V13" [get_ports "LVDS2V5South5PxSIO"]
set_property PACKAGE_PIN "V14" [get_ports "LVDS2V5South5NxSIO"]
set_property PACKAGE_PIN "Y12" [get_ports "LVDS2V5South4PxSIO"]
set_property PACKAGE_PIN "Y13" [get_ports "LVDS2V5South4NxSIO"]
set_property PACKAGE_PIN "AA12" [get_ports "LVDS2V5South3PxSIO"]
set_property PACKAGE_PIN "AB12" [get_ports "LVDS2V5South3NxSIO"]
set_property PACKAGE_PIN "W12" [get_ports "LVDS2V5South2PxSIO"]
set_property PACKAGE_PIN "W13" [get_ports "LVDS2V5South2NxSIO"]
set_property PACKAGE_PIN "AA11" [get_ports "LVDS2V5South1PxSIO"]
set_property PACKAGE_PIN "AB11" [get_ports "LVDS2V5South1NxSIO"]
set_property PACKAGE_PIN "V11" [get_ports "LVDS2V5South0PxSIO"]
set_property PACKAGE_PIN "W11" [get_ports "LVDS2V5South0NxSIO"]
# East (bank 13)
set_property PACKAGE_PIN "V16" [get_ports "LVDS2V5East7PxSIO"]
set_property PACKAGE_PIN "W16" [get_ports "LVDS2V5East7NxSIO"]
set_property PACKAGE_PIN "W17" [get_ports "LVDS2V5East6PxSIO"]
set_property PACKAGE_PIN "Y17" [get_ports "LVDS2V5East6NxSIO"]
set_property PACKAGE_PIN "U13" [get_ports "LVDS2V5East5PxSIO"]
set_property PACKAGE_PIN "U14" [get_ports "LVDS2V5East5NxSIO"]
set_property PACKAGE_PIN "V18" [get_ports "LVDS2V5East4PxSIO"]
set_property PACKAGE_PIN "W18" [get_ports "LVDS2V5East4NxSIO"]
set_property PACKAGE_PIN "U11" [get_ports "LVDS2V5East3PxSIO"]
set_property PACKAGE_PIN "U12" [get_ports "LVDS2V5East3NxSIO"]
set_property PACKAGE_PIN "U19" [get_ports "LVDS2V5East2PxSIO"]
set_property PACKAGE_PIN "V19" [get_ports "LVDS2V5East2NxSIO"]
set_property PACKAGE_PIN "R17" [get_ports "LVDS2V5East1PxSIO"]
set_property PACKAGE_PIN "T17" [get_ports "LVDS2V5East1NxSIO"]
set_property PACKAGE_PIN "U17" [get_ports "LVDS2V5East0PxSIO"]
set_property PACKAGE_PIN "U18" [get_ports "LVDS2V5East0NxSIO"]
# West (bank 35)
set_property PACKAGE_PIN "H4" [get_ports "LVDS2V5West7PxSIO"]
set_property PACKAGE_PIN "H3" [get_ports "LVDS2V5West7NxSIO"]
set_property PACKAGE_PIN "H1" [get_ports "LVDS2V5West6PxSIO"]
set_property PACKAGE_PIN "G1" [get_ports "LVDS2V5West6NxSIO"]
set_property PACKAGE_PIN "G3" [get_ports "LVDS2V5West5PxSIO"]
set_property PACKAGE_PIN "G2" [get_ports "LVDS2V5West5NxSIO"]
set_property PACKAGE_PIN "F2" [get_ports "LVDS2V5West4PxSIO"]
set_property PACKAGE_PIN "F1" [get_ports "LVDS2V5West4NxSIO"]
set_property PACKAGE_PIN "G4" [get_ports "LVDS2V5West3PxSIO"]
set_property PACKAGE_PIN "F4" [get_ports "LVDS2V5West3NxSIO"]
set_property PACKAGE_PIN "E2" [get_ports "LVDS2V5West2PxSIO"]
set_property PACKAGE_PIN "D2" [get_ports "LVDS2V5West2NxSIO"]
set_property PACKAGE_PIN "E4" [get_ports "LVDS2V5West1PxSIO"]
set_property PACKAGE_PIN "E3" [get_ports "LVDS2V5West1NxSIO"]
set_property PACKAGE_PIN "D1" [get_ports "LVDS2V5West0PxSIO"]
set_property PACKAGE_PIN "C1" [get_ports "LVDS2V5West0NxSIO"]
##### LVDS links towards top-bottom connectors #####
# Top (bank 34)
set_property PACKAGE_PIN "J8" [get_ports "LVDS2V5Top7PxSIO"]
set_property PACKAGE_PIN "K8" [get_ports "LVDS2V5Top7NxSIO"]
set_property PACKAGE_PIN "K7" [get_ports "LVDS2V5Top6PxSIO"]
set_property PACKAGE_PIN "L7" [get_ports "LVDS2V5Top6NxSIO"]
set_property PACKAGE_PIN "N8" [get_ports "LVDS2V5Top5PxSIO"]
set_property PACKAGE_PIN "P8" [get_ports "LVDS2V5Top5NxSIO"]
set_property PACKAGE_PIN "M8" [get_ports "LVDS2V5Top4PxSIO"]
set_property PACKAGE_PIN "M7" [get_ports "LVDS2V5Top4NxSIO"]
set_property PACKAGE_PIN "L6" [get_ports "LVDS2V5Top3PxSIO"]
set_property PACKAGE_PIN "M6" [get_ports "LVDS2V5Top3NxSIO"]
set_property PACKAGE_PIN "J7" [get_ports "LVDS2V5Top2PxSIO"]
set_property PACKAGE_PIN "J6" [get_ports "LVDS2V5Top2NxSIO"]
set_property PACKAGE_PIN "J5" [get_ports "LVDS2V5Top1PxSIO"]
set_property PACKAGE_PIN "K5" [get_ports "LVDS2V5Top1NxSIO"]
set_property PACKAGE_PIN "J2" [get_ports "LVDS2V5Top0PxSIO"]
set_property PACKAGE_PIN "J1" [get_ports "LVDS2V5Top0NxSIO"]
# Bottom (bank 34)
set_property PACKAGE_PIN "N6" [get_ports "LVDS2V5Bottom7PxSIO"]
set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
set_property PACKAGE_PIN "P6" [get_ports "LVDS2V5Bottom6PxSIO"]
set_property PACKAGE_PIN "P5" [get_ports "LVDS2V5Bottom6NxSIO"]
set_property PACKAGE_PIN "R5" [get_ports "LVDS2V5Bottom5PxSIO"]
set_property PACKAGE_PIN "R4" [get_ports "LVDS2V5Bottom5NxSIO"]
set_property PACKAGE_PIN "R3" [get_ports "LVDS2V5Bottom4PxSIO"]
set_property PACKAGE_PIN "R2" [get_ports "LVDS2V5Bottom4NxSIO"]
set_property PACKAGE_PIN "P3" [get_ports "LVDS2V5Bottom3PxSIO"]
set_property PACKAGE_PIN "P2" [get_ports "LVDS2V5Bottom3NxSIO"]
set_property PACKAGE_PIN "N1" [get_ports "LVDS2V5Bottom2PxSIO"]
set_property PACKAGE_PIN "P1" [get_ports "LVDS2V5Bottom2NxSIO"]
set_property PACKAGE_PIN "N4" [get_ports "LVDS2V5Bottom1PxSIO"]
set_property PACKAGE_PIN "N3" [get_ports "LVDS2V5Bottom1NxSIO"]
set_property PACKAGE_PIN "M2" [get_ports "LVDS2V5Bottom0PxSIO"]
set_property PACKAGE_PIN "M1" [get_ports "LVDS2V5Bottom0NxSIO"]
##### RGB LEDs (banks 34 and 13) #####
# LED1_2V5_R_o (bank 34)
set_property PACKAGE_PIN "L2" [get_ports "Led12V5RxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led12V5RxSO"]
# LED1_2V5_G_o (bank 34)
set_property PACKAGE_PIN "L1" [get_ports "Led12V5GxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led12V5GxSO"]
# LED1_2V5_B_o (bank 34)
set_property PACKAGE_PIN "R8" [get_ports "Led12V5BxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led12V5BxSO"]
# LED2_2V5_R_o (bank 13)
set_property PACKAGE_PIN "T16" [get_ports "Led22V5RxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led22V5RxSO"]
# LED2_2V5_G_o (bank 13)
set_property PACKAGE_PIN "U16" [get_ports "Led22V5GxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led22V5GxSO"]
# LED2_2V5_B_o (bank 13)
set_property PACKAGE_PIN "AA20" [get_ports "Led22V5BxSO"]
set_property iostandard "LVCMOS25" [get_ports "Led22V5BxSO"]
##### Self reset (bank 34) #####
set_property PACKAGE_PIN "H8" [get_ports "SelfRstxRNO"]
set_property iostandard "LVCMOS25" [get_ports "SelfRstxRNO"]
##### Clock dedicated pins (Multi-region) #####
# Bank 35
set_property PACKAGE_PIN "D5" [get_ports "PLLClk2V5LocalPxCI"]
set_property PACKAGE_PIN "C4" [get_ports "PLLClk2V5LocalNxCI"]
set_property PACKAGE_PIN "B4" [get_ports "PLLClk2V5NorthPxCI"]
set_property PACKAGE_PIN "B3" [get_ports "PLLClk2V5NorthNxCI"]
# Bank 34
set_property PACKAGE_PIN "T2" [get_ports "PLLClk2V5TopxCI"]
set_property PACKAGE_PIN "L5" [get_ports "PLLClk2V5BottomxCI"]
# Bank 13
set_property PACKAGE_PIN "Y14" [get_ports "PLLClk2V5SouthPxCI"]
set_property PACKAGE_PIN "Y15" [get_ports "PLLClk2V5SouthNxCI"]
set_property PACKAGE_PIN "Y18" [get_ports "Clk2V5RecoveryPxCO"]
set_property PACKAGE_PIN "Y19" [get_ports "Clk2V5RecoveryNxCO"]
##### Clock dedicated pins (Single-region) #####
# Bank 35
set_property PACKAGE_PIN "C6" [get_ports "Clk2V5NorthPxCI"]
set_property PACKAGE_PIN "C5" [get_ports "Clk2V5NorthNxCI"]
set_property PACKAGE_PIN "D3" [get_ports "Clk2V5WestPxCI"]
set_property PACKAGE_PIN "C3" [get_ports "Clk2V5WestNxCI"]
# Bank 34
set_property PACKAGE_PIN "K4" [get_ports "Clk2V5TopPxCI"]
set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
set_property PACKAGE_PIN "U2" [get_ports "Clk2V5BottomPxCI"]
set_property PACKAGE_PIN "U1" [get_ports "Clk2V5BottomNxCI"]
# Bank 13
set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
set_property PACKAGE_PIN "AA16" [get_ports "Clk2V5EastPxCI"]
set_property PACKAGE_PIN "AA17" [get_ports "Clk2V5EastNxCI"]
##### Clock outputs #####
## Bank 35
set_property PACKAGE_PIN "F7" [get_ports "Clk2V5NorthPxCO"]
set_property PACKAGE_PIN "E7" [get_ports "Clk2V5NorthNxCO"]
set_property PACKAGE_PIN "F5" [get_ports "Clk2V5WestPxCO"]
set_property PACKAGE_PIN "E5" [get_ports "Clk2V5WestNxCO"]
# Bank 34
set_property PACKAGE_PIN "P7" [get_ports "Clk2V5TopPxCO"]
set_property PACKAGE_PIN "R7" [get_ports "Clk2V5TopNxCO"]
set_property PACKAGE_PIN "M4" [get_ports "Clk2V5BottomPxCO"]
set_property PACKAGE_PIN "M3" [get_ports "Clk2V5BottomNxCO"]
# Bank 13
set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
set_property PACKAGE_PIN "AB21" [get_ports "Clk2V5EastPxCO"]
set_property PACKAGE_PIN "AB22" [get_ports "Clk2V5EastNxCO"]
############################################################################
# Other constraints #
############################################################################
##### Operating conditions (for XPE report) #####
# Extended grade (as for -2 speed grade) and maximum consumption estimation
set_operating_conditions -grade extended -process maximum
# 4'' by 4'' PCB, no heatsink, no air flow
set_operating_conditions -airflow 0 -heatsink none -board small
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