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Commit c4925c31 authored by quentin.berthet's avatar quentin.berthet
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Update project creation scripts

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designs/vivado/scalp_firmware/2019.2/lin64/.gitignore 0 → 100644
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− 0
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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Git ignore file
#
# Last update: 2020-12-17 17:50:45
#
##################################################################################
# Ignore generated project directory
scalp_firmware
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/.prompt_colors.tcl
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− 14
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...@@ -15,23 +15,33 @@ ...@@ -15,23 +15,33 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Console color print utility # Description: Console color print utility
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
# Try to set a variable with an execution command
# If the command fails, set the variable to an empty string
# cmd - The command to be executed
# return The variable to be set
proc try_setexec {cmd} {
set code [catch { set var [exec {*}$cmd] } ]
if { $code != 0 } { set var "" }
return ${var}
}
# Text attributes # Text attributes
set RESET [exec tput sgr0] set RESET [try_setexec "tput sgr0"]
set BOLD [exec tput bold] set BOLD [try_setexec "tput bold"]
set ITALIC [exec tput sitm] set ITALIC [try_setexec "tput sitm"]
set BLINK [exec tput blink] set BLINK [try_setexec "tput blink"]
set HIGHL [exec tput smso] set HIGHL [try_setexec "tput smso"]
# Text colors # Text colors
set RED [exec tput setaf 1] set RED [try_setexec "tput setaf 1"]
set GREEN [exec tput setaf 2] set GREEN [try_setexec "tput setaf 2"]
set YELLOW [exec tput setaf 3] set YELLOW [try_setexec "tput setaf 3"]
set BLUE [exec tput setaf 4] set BLUE [try_setexec "tput setaf 4"]
set MAGENTA [exec tput setaf 5] set MAGENTA [try_setexec "tput setaf 5"]
set CYAN [exec tput setaf 6] set CYAN [try_setexec "tput setaf 6"]
set WHITE [exec tput setaf 7] set WHITE [try_setexec "tput setaf 7"]
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Cleanup project directory # Description: Cleanup project directory
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Create Vivado project # Description: Create Vivado project
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
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− 64
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware' # Description: TCL script for re-creating Vivado project 'scalp_firmware'
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020/12/17 18:01:05
# #
################################################################################## ##################################################################################
...@@ -36,6 +36,7 @@ set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}] ...@@ -36,6 +36,7 @@ set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project # Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src" set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../ips/hw" set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
set comp_dir "${ip_dir}/$prj_name" set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src" set comp_src_dir "${comp_dir}/src"
set pkg_src_dir "${PKG_DIR}/hw" set pkg_src_dir "${PKG_DIR}/hw"
...@@ -49,55 +50,75 @@ set_property target_language VHDL [current_project] ...@@ -49,55 +50,75 @@ set_property target_language VHDL [current_project]
print_status "Create project" "OK" print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included # Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset] set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
update_ip_catalog update_ip_catalog
#---------------------------------------------------------------- #----------------------------------------------------------------
# Add project sources # Add project sources
#---------------------------------------------------------------- #----------------------------------------------------------------
# Get HDL source files directory
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources set hdl_src_dir "${src_dir}/hdl"
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd] set sim_src_dir "${src_dir}/sim"
set verilog_src_file_list [findFiles $src_dir/hdl *.v] } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list] # components sources are stored in an external directory
set hdl_src_dir "${comp_src_dir}/hdl"
set sim_src_dir "${comp_src_dir}/sim"
}
# add HDL source files
set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
set verilog_src_file_list [findFiles $hdl_src_dir *.v]
set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
if {$hdl_src_file_list != ""} {
add_files -norecurse $hdl_src_file_list
add_files -norecurse $hdl_src_file_list add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC) add_files -norecurse $hdl_src_file_list
add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc } else {
print_status "No sources to be added" "WARNING"
}
# Set VHDL version
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
# Add constraint files and IPs source files
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
set_property is_enabled true [get_files $src_dir/constrs/debug.xdc] set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc] set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc] set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc] set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
# add IPs source file # add IPs source files
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd] set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list { foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd] set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list { foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd] set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list { foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
...@@ -113,33 +134,14 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc ...@@ -113,33 +134,14 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory # add IPs source files
# add the project component
set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd] # add IP-XACT source file
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v] #add_files -norecurse $comp_dir/component.xml
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
} }
print_status "Add project sources" "OK" print_status "Add project sources" "OK"
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
#----------------------------------------------------------------
# Add constraints files
#----------------------------------------------------------------
# Set packages libraries if any # Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd] #set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1 #update_compile_order -fileset sources_1
...@@ -156,44 +158,45 @@ print_status "Add IPI design" "OK" ...@@ -156,44 +158,45 @@ print_status "Add IPI design" "OK"
set_property top $prj_name [current_fileset] set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1 update_compile_order -fileset sources_1
# Add testbench sources # Add simulation sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd] set verilog_sim_file_list [findFiles $sim_src_dir *.v]
set verilog_sim_file_list [findFiles $src_dir/sim *.v] set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v] if {$hdl_sim_file_list != ""} {
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add simulation sources" "OK"
} else {
print_status "No simulation sources to be added" "WARNING"
} }
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
foreach j $vhdl_sim_file_list { foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
} }
print_status "VHDL 2008 mode configured for testbench sources" "OK" print_status "VHDL 2008 mode configured for simulation sources" "OK"
# Add packages sources # Add packages sources
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd] set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list { foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd] set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list { foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd] set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list { foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
...@@ -204,7 +207,7 @@ print_status "VHDL 2008 mode configured for packages sources" "OK" ...@@ -204,7 +207,7 @@ print_status "VHDL 2008 mode configured for packages sources" "OK"
set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd] set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
add_files -norecurse $vhdl_soc_file_list add_files -norecurse $vhdl_soc_file_list
foreach j $vhdl_soc_file_list { foreach j $vhdl_soc_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Export the hardware design to SDK # Description: Export the hardware design to SDK
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
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− 1
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Export the hardware design to SDK # Description: Export the hardware design to SDK
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
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− 1
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Generate bitstream file # Description: Generate bitstream file
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
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− 1
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to generate bitstream file # Description: TCL script used to generate bitstream file
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Generate software application # Description: Generate software application
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
+ 1
− 1
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to generate software application # Description: TCL script used to generate software application
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Load bitstream file # Description: Load bitstream file
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
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− 1
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to load FPGA bitstream # Description: TCL script used to load FPGA bitstream
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Load software application # Description: Load software application
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
+ 1
− 1
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to load software application # Description: TCL script used to load software application
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Create Vivado project # Description: Create Vivado project
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
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designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
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View file @ c4925c31
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Project management utilities # Description: Project management utilities
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
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View file @ c4925c31
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts # Description: TCL script creating aliases for Vivado project management scripts
# #
# Last update: 2020-11-30 09:39:40 # Last update: 2020-12-17 17:50:45
# #
################################################################################## ##################################################################################
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