Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
S
scalp_firmware
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Deploy
Releases
Model registry
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
quentin.berthet
scalp_firmware
Repository graph
Repository graph
You can move around the graph by using the arrow keys.
ips_scalp_aurora_phy
Select Git revision
Branches
3
hl2
ips_scalp_aurora_phy
master
default
protected
Tags
2
v0.9.2
v0.9.1
5 results
Begin with the selected commit
Created with Raphaël 2.2.0
21
Dec
17
16
8
30
Nov
26
25
10
8
7
13
Oct
22
Sep
21
8
7
3
Update HL2 packaging file
hl2
hl2
Update project creation scripts
Enable HL2 ip in scalp_firmware creation project
Variable enaming, typos and packaging update of scalp_hl2 peripheral
Add files requires for packaging
Change project type from IPS to PERIPHERAL
Add headers and fix indentation
Fix copy-paste typo
Add scalp_hl2 comonent, imported from DMX ip, not modified yet
Modification of the file create_project.tcl with the description of the Scalp board.
master
master
Add SCALP node vivado board files
Added IP scalp_router to the scalp_firmware project, but not yet integrated in the design.
Creation of the IP scalp_router (HDL + SIM) to the scalp_firmware project.
Design scalp_firmware with 4 interfaces (north, east, south, west) and an example of the process of sending data in the form of packets and receiving data in the form of packets.
Updating the file create_project.tcl.
Firmware with four GTP interfaces (north, east, south, west) and congestion management and with Zynq SoC.
Firmware with four GTP interfaces (north, east, south, west) and congestion management and with Zynq SoC.
Updated the scalp_firmware reference design with some corrections on back pressure management. Back pressure management is external to the IP core scalp_aurora_pyh. The next update is to integrate it to the IP core.
v0.9.2
v0.9.2
Updated scalp_firmware firmware design.
Updated IP core scalp_packet_fifo with two clock sources.
Creation of a IP core scalp_packet_fifo.
Zynq SoC update with IP Core scalp_axilite.
Creation of the IP core scalp_axilite and IP packaging for integration in a Zynq SoC.
Back pressure process update
v0.9.1
v0.9.1
Updated firmware design "scalp_firmware" with back pressure management for each receiving fifo.
Creation of the IP core scalp_aurora_phy_rx_fifo
Creation of JSON file scalp_aurora_phy_rx_fifo.json
Addition of Zynq SoC.
ips_scalp_auror…
ips_scalp_aurora_phy
Addition of all packages.
Addition of all IPS.
Addition of the main design.
Added modifications to the vivado_prj_creator project.
Added and modified new JSON configuration files.
New version of scripts for the scalp_aurora_phy IPS.
New commit on tools/vivado_prj_creator.
Creation and initial tracking of scripts for the scalp_aurora_phy IPS.
New commit on tools/vivado_prj_creator.
Added a JSON file for the IP Core Aurora.
tools/vivado_prj_creator
Minimum project with support of a Zynq core.
Loading