Creation of TCL scripts for the creation and management of the Vivado project.

designs/vivado/scalp_router_firmware/2020.2/lin64/.gitignore

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_router_firmware

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+  set code [catch { set var [exec {*}$cmd] } ]
+  if { $code != 0 } { set var "" }
+
+  return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/clean_prj_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_router_firmware/ 2> /dev/null
+
+echo "> Done"
+

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/create_prj_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_router_firmware.tcl -notrace
+echo "> Done"
+

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/create_prj_scalp_router_firmware.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_router_firmware'
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_router_firmware"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "DESIGN_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+# Get HDL source files directory
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+    set hdl_src_dir "${src_dir}/hdl"
+    set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+    # components sources are stored in an external directory
+    set hdl_src_dir "${comp_src_dir}/hdl"
+    set sim_src_dir "${comp_src_dir}/sim"
+}    
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+  add_files -norecurse $hdl_src_file_list
+} else {
+  print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {  
+  # add the constraints file (XDC)
+  add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
+	set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
+	
+  # add IPs source files
+  set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_rx_link_layer/src/hdl *.vhd]
+	add_files -norecurse $vhdl_ips_file_list
+	foreach j $vhdl_ips_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_axis_fifo_wrapper/src/hdl *.vhd]
+	add_files -norecurse $vhdl_ips_file_list
+	foreach j $vhdl_ips_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
+	add_files -norecurse $vhdl_ips_file_list
+	foreach j $vhdl_ips_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
+	add_files -norecurse $vhdl_ips_file_list
+	foreach j $vhdl_ips_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
+	add_files -norecurse $vhdl_ips_file_list
+	foreach j $vhdl_ips_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci
+	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
+	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
+	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
+	read_ip ${ip_dir}/scalp_axis_fifo_wrapper/src/ip_core/scalp_axis_fifo/scalp_axis_fifo.xci
+	read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
+	read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
+	read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
+	read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
+	read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
+	read_ip ${ip_dir}/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
+
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+  # add IPs source files
+  
+  # add IP-XACT source file
+  #add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+  add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+  update_compile_order -fileset sim_1
+  print_status "Add simulation sources" "OK"
+} else {
+  print_status "No simulation sources to be added" "WARNING"
+}
+
+foreach j $vhdl_sim_file_list {
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
+
+# Add packages sources
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+		set_property library xil_defaultlib [get_files $j]
+	}
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+		set_property library xil_defaultlib [get_files $j]
+	}
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+		set_property library xil_defaultlib [get_files $j]
+	}
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
+
+# Add SoC wrapper sources files
+	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
+	add_files -norecurse $vhdl_soc_file_list
+	foreach j $vhdl_soc_file_list {
+		set_property file_type {VHDL 2008} [get_files $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+print_status "Add SoC wrapper sources" "OK"
+print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/export_hw_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to SDK
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+echo "> Export the hardware design to Vitis SDK"
+
+vivado -nojournal -nolog -mode tcl -source ./export_hw_scalp_router_firmware.tcl -notrace
+
+echo "> Done"
+

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/export_hw_scalp_router_firmware.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to Vitis SDK
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+source utils.tcl
+
+# Project paths
+set PRJ_DIR ".."
+set SRC_DIR "${PRJ_DIR}/../src"
+set EXPORT_DIR "${SRC_DIR}/sw/hw_export"
+
+# Initialize workspace directories name
+set prj_name "scalp_router_firmware"
+# Create the export directory if not present
+file mkdir ${EXPORT_DIR}
+print_status "Initialize workspace directories" "OK"
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/${prj_name}/${prj_name}.xpr
+print_status "Open project $prj_name" "OK"
+
+# Export the hardware including the bitstream
+write_hw_platform -fixed -force -include_bit -file ${EXPORT_DIR}/${prj_name}.xsa
+print_status "Export hardware to Vitis SDK" "OK"
+
+exit

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate bitstream file
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+PRJ_DIR=..
+
+echo "> Generate bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./gen_bitstream_scalp_router_firmware.tcl -notrace
+
+echo "> Copy bitstream file in current directory..."
+mkdir -p ${PRJ_DIR}/bitstream/
+cp ${PRJ_DIR}/scalp_router_firmware/scalp_router_firmware.runs/impl_1/scalp_router_firmware.bit ${PRJ_DIR}/bitstream/scalp_router_firmware.bit
+
+echo "> Done"
+

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_router_firmware.tcl

+#!/usr/bin/tcl
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to generate bitstream file
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_router_firmware"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
+update_compile_order -fileset sources_1
+print_status "Open project $prj_name" "OK"
+
+# Run synthesis
+print_status "Run synthesis" "IN_PROGRESS"
+launch_runs synth_1
+wait_on_run synth_1
+print_status "Run synthesis" "OK"
+
+# Run implementation
+print_status "Run implementation" "IN_PROGRESS"
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+wait_on_run impl_1
+print_status "Run implementation" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time on the screen
+puts $start_time
+puts $end_time
+
+exit

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Load bitstream file
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+echo "> Load bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./load_bitstream_scalp_router_firmware.tcl -notrace
+echo "> Done"
+

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_router_firmware.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to load FPGA bitstream
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_router_firmware"
+
+# Open the hardware manager and connect to the hardware server
+open_hw
+print_status "Open hardware manager" "OK"
+connect_hw_server -url localhost:3121
+print_status "Connect to hardware server" "OK"
+
+# Get the hardware target and open it
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
+open_hw_target
+print_status "Open hardware target" "OK"
+
+# Display targets list
+set index -1
+set targets [lindex [get_hw_devices]]
+puts "Found target(s):"
+foreach target $targets {
+  incr index
+  puts "$index : $target"
+}
+puts "Which target do you want to program?"
+set sel_target [read stdin 1]
+
+# Set the program file
+set_property PROGRAM.FILE ${PRJ_DIR}/bitstream/$prj_name.bit [lindex [get_hw_devices] $sel_target]
+current_hw_device [lindex [get_hw_devices] $sel_target]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] $sel_target]
+print_status "Set program file" "OK"
+
+# Program the device
+print_status "Program device" "IN_PROGRESS"
+program_hw_device [lindex [get_hw_devices] $sel_target]
+print_status "Program device" "OK"
+
+exit

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/open_prj_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Open Vivado project GUI
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_router_firmware/scalp_router_firmware.xpr

designs/vivado/scalp_router_firmware/2020.2/lin64/.scripts/utils.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+    # Fix the directory name, this ensures the directory name is in the
+    # native format for the platform and contains a final directory seperator
+    set basedir [string trimright [file join [file normalize $basedir] { }]]
+    set fileList {}
+
+    # Look in the current directory for matching files, -type {f r}
+    # means ony readable normal files are looked at, -nocomplain stops
+    # an error being thrown if the returned list is empty
+    foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+        lappend fileList $fileName
+    }
+
+    # Now look for any sub direcories in the current directory
+    foreach dirName [glob -nocomplain -type {d  r} -path $basedir *] {
+        # Recusively call the routine on the sub directory and append any
+        # new files to the results
+        set subDirList [findFiles $dirName $pattern]
+        if { [llength $subDirList] > 0 } {
+            foreach subDirFile $subDirList {
+                lappend fileList $subDirFile
+            }
+        }
+    }
+    return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+    set MAX_STR_LENGTH 70
+    source .prompt_colors.tcl
+    puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+

designs/vivado/scalp_router_firmware/2020.2/lin64/setup.sh

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_router_firmware.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_router_firmware.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_router_firmware.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_router_firmware.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_router_firmware.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_router_firmware.sh && cd ..'

designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: scalp_router_firmware - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: scalp_router_firmware
+--
+-- Last update: 2021-06-08 14:56:43
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity scalp_router_firmware is
+end scalp_router_firmware;
+
+
+architecture arch of scalp_router_firmware is
+
+begin
+
+end arch;

designs/vivado/scalp_router_firmware/2020.2/src/ipi_tcl/scalp_router_firmware_ipi.tcl

+source "../../../../../../soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl"
\ No newline at end of file

designs/vivado/scalp_router_firmware/2020.2/src/sim/tb_scalp_router_firmware.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: tb_scalp_router_firmware - arch
+-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+-- Tool version: 2020.2
+-- Description: Testbench for scalp_router_firmware
+--
+-- Last update: 2021-06-08 14:56:43
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_scalp_router_firmware is
+end tb_scalp_router_firmware;
+
+
+architecture behavioral of tb_scalp_router_firmware is
+
+begin
+
+end behavioral;

designs/vivado/scalp_router_firmware/2020.2/src/sw/.scripts/.prompt_colors.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+  set code [catch { set var [exec {*}$cmd] } ]
+  if { $code != 0 } { set var "" }
+
+  return ${var}
+}
+
+# Text attributes
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
+
+# Text colors
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]

designs/vivado/scalp_router_firmware/2020.2/src/sw/.scripts/clean_sdk_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup Vitis SDK workspace directory
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+echo "> Cleanup SDK workspace directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ./xrc.log/ 2> /dev/null
+rm -rf ./.Xil/ 2> /dev/null
+
+# Remove generated workspace directory
+rm -rf ${PRJ_DIR}/vitis_workspace/ 2> /dev/null
+
+echo "> Done"

designs/vivado/scalp_router_firmware/2020.2/src/sw/.scripts/gen_sw_apps_scalp_router_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_router_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate Vitis workspace for software applications
+#
+# Last update: 2021-06-08 14:56:43
+#
+##################################################################################
+
+echo "> Generate Vitis workspace software applications"
+xsct gen_sw_apps_scalp_router_firmware.tcl
+echo "> Done"