Creation of a Phy Aurora component.

ips/hw/phy_aurora/src/hdl/phy_aurora.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: phy_aurora - arch
+-- Target Device: SCALP xc7k325tffg900-2
+-- Tool version: 2019.2
+-- Description: phy_aurora
+--
+-- Last update: 2020-09-03 12:53:59
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity phy_aurora is
+end phy_aurora;
+
+
+architecture arch of phy_aurora is
+
+begin
+
+end arch;

ips/hw/phy_aurora/src/hdl/pkg/aurora_drp_pkg.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: aurora_drp_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: DRP interface control signals for the Aurora phy.
+--
+-- Last update: 2020-09-03
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package aurora_drp_pkg is
+
+    constant C_DRP_ADDR_SIZE : integer                                          := 11;
+    constant C_DRP_DATA_SIZE : integer                                          := 16;
+    constant C_DRP_SEL_SIZE  : integer                                          := 2;
+    constant C_DRP_SEL_NORTH : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "00";
+    constant C_DRP_SEL_EAST  : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "01";
+    constant C_DRP_SEL_SOUTH : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "10";
+    constant C_DRP_SEL_WEST  : std_ulogic_vector((C_DRP_SEL_SIZE - 1) downto 0) := "11";
+
+    -- DRP Ports
+    -- Master To Slave
+    type t_drpm2s is record
+        DrpClkxC  : std_logic;
+        DrpAddrxD : std_ulogic_vector((C_DRP_ADDR_SIZE - 1) downto 0);
+        DrpDIxD   : std_ulogic_vector((C_DRP_DATA_SIZE - 1) downto 0);
+        DrpEnxS   : std_ulogic;
+        DrpWExS   : std_ulogic;
+    end record t_drpm2s;
+
+    -- Slave To Master
+    type t_drps2m is record
+        DrpDOxD  : std_ulogic_vector((C_DRP_DATA_SIZE - 1) downto 0);
+        DrpRdyxS : std_ulogic;
+    end record t_drps2m;
+
+    type t_drp is record
+        M2S : t_drpm2s;
+        S2M : t_drps2m;
+    end record t_drp;
+
+    constant C_NO_DRP_M2S : t_drpm2s := (DrpClkxC  => '0',
+                                         DrpAddrxD => (others => '0'),
+                                         DrpDIxD   => (others => '0'),
+                                         DrpEnxS   => '0',
+                                         DrpWExS   => '0');
+
+    constant C_NO_DRP_S2M : t_drps2m := (DrpDOxD  => (others => '0'),
+                                         DrpRdyxS => '0');
+
+    constant C_NO_DRP : t_drp := (M2S => C_NO_DRP_M2S,
+                                  S2M => C_NO_DRP_S2M);
+
+end package aurora_drp_pkg;

ips/hw/phy_aurora/src/hdl/pkg/aurora_status_pkg.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: aurora_status_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: Control and status signals for the Aurora phy.
+--
+-- Last update: 2020-09-03
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+package aurora_status_pkg is
+
+    -- Constants
+
+    constant C_GTP_VECTOR_SIZE : integer := 1;
+    constant C_LANEUP_SIZE     : integer := 1;
+    constant C_LOOPBACK_SIZE   : integer := 3;
+    constant C_NB_GTP_CORE     : integer := 4;
+    constant C_NUM_PLL         : integer := 1;
+    constant C_GTP_NORTH_ID    : integer := 0;
+    constant C_GTP_EAST_ID     : integer := 1;
+    constant C_GTP_SOUTH_ID    : integer := 2;
+    constant C_GTP_WEST_ID     : integer := 3;
+
+    -- Types
+
+    type t_aurora_gtp_diff_io_rx is record
+        RXPxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+        RXNxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+    end record t_aurora_gtp_diff_io_rx;
+
+    type t_aurora_gtp_diff_io_tx is record
+        TXPxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+        TXNxD : std_ulogic_vector((C_GTP_VECTOR_SIZE - 1) downto 0);
+    end record t_aurora_gtp_diff_io_tx;
+
+    constant C_AURORA_NO_GTP_DIFF_IO_RX : t_aurora_gtp_diff_io_rx := (RXPxD => (others => '0'),
+                                                                  RXNxD => (others => '0'));
+
+    constant C_AURORA_NO_GTP_DIFF_IO_TX : t_aurora_gtp_diff_io_tx := (TXPxD => (others => '0'),
+                                                                  TXNxD => (others => '0'));
+
+    type t_gtp_diff_ref_clk is record
+        ClkPxC : std_ulogic;
+        ClkNxC : std_ulogic;
+    end record t_gtp_diff_ref_clk;
+
+    constant C_NO_GTP_DIFF_REF_CLK : t_gtp_diff_ref_clk := (ClkPxC => '0',
+                                                         ClkNxC => '0');
+
+    type t_aurora_control is record
+        LoopbackxD      : std_ulogic_vector((C_LOOPBACK_SIZE - 1) downto 0);
+        PowerDownxS     : std_ulogic;
+        GTPRefClkSrcxS  : std_ulogic;
+        InitClkLockedxS : std_ulogic;
+    end record t_aurora_control;
+
+    constant C_MGTREFCLK0_SRC : std_ulogic := '0';
+    constant C_MGTREFCLK1_SRC : std_ulogic := '1';
+
+    constant C_AURORA_NO_CONTROL : t_aurora_control := (LoopbackxD      => (others => '0'),
+                                                       PowerDownxS     => '1',
+                                                       GTPRefClkSrcxS  => C_MGTREFCLK0_SRC,
+                                                       InitClkLockedxS => '0');
+
+    type t_laneup_vector is array (0 to (C_NB_GTP_CORE - 1)) of std_ulogic_vector((C_LANEUP_SIZE - 1) downto 0);
+
+    type t_aurora_status is record
+        HardErrxD        : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+        SoftErrxD        : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+        FrameErrxD       : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+        LaneUpxD         : t_laneup_vector;
+        ChannelUpxD      : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+        RXResetDoneOutxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+        TXResetDoneOutxD : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+        TXLockxD         : std_ulogic_vector((C_NB_GTP_CORE - 1) downto 0);
+        PllNotLockedxS   : std_ulogic;
+    end record t_aurora_status;
+
+    constant C_AURORA_NO_STATUS : t_aurora_status := (HardErrxD        => (others => '0'),
+                                                     SoftErrxD        => (others => '0'),
+                                                     FrameErrxD       => (others => '0'),
+                                                     LaneUpxD         => (others => (others => '0')),
+                                                     ChannelUpxD      => (others => '0'),
+                                                     RXResetDoneOutxD => (others => '0'),
+                                                     TXResetDoneOutxD => (others => '0'),
+                                                     TXLockxD         => (others => '0'),
+                                                     PllNotLockedxS   => '1');
+
+    constant C_AURORA_STATUS_OK : t_aurora_status := (HardErrxD        => (others => '0'),
+                                                     SoftErrxD        => (others => '0'),
+                                                     FrameErrxD       => (others => '0'),
+                                                     LaneUpxD         => (others => (others => '1')),
+                                                     ChannelUpxD      => (others => '1'),
+                                                     RXResetDoneOutxD => (others => '1'),
+                                                     TXResetDoneOutxD => (others => '1'),
+                                                     TXLockxD         => (others => '1'),
+                                                     PllNotLockedxS   => '1');
+
+    type t_aurora_crc is record
+        CRCPassFailxSN : std_ulogic;
+        CRCValidxS     : std_ulogic;
+    end record t_aurora_crc;
+
+    constant C_AURORA_NO_CRC : t_aurora_crc := (CRCPassFailxSN => '0',
+                                               CRCValidxS     => '0');
+
+    constant C_AURORA_CRC_OK : t_aurora_crc := (CRCPassFailxSN => '1',
+                                               CRCValidxS     => '1');
+
+    constant C_AURORA_CRC_NO_OK : t_aurora_crc := (CRCPassFailxSN => '0',
+                                                  CRCValidxS     => '1');
+
+    type t_aurora_slave_clk is record
+        InitClkxC     : std_ulogic;
+        DrpClkxC      : std_ulogic;
+        GTClkxC       : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+        GTClkLockedxD : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+    end record t_aurora_slave_clk;
+
+    constant C_AURORA_NO_SLAVE_CLK : t_aurora_slave_clk := (InitClkxC     => '0',
+                                                          DrpClkxC      => '0',
+                                                          GTClkxC       => (others => '0'),
+                                                          GTClkLockedxD => (others => '0'));
+
+    type t_aurora_master_clk is record
+        InitClkxC      : std_ulogic;
+        UserClkxC      : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+        SyncClkxC      : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+        PllNotLockedxD : std_ulogic_vector((C_NUM_PLL - 1) downto 0);
+    end record t_aurora_master_clk;
+
+    constant C_AURORA_NO_MASTER_CLK : t_aurora_master_clk := (InitClkxC      => '0',
+                                                            UserClkxC      => (others => '0'),
+                                                            SyncClkxC      => (others => '0'),
+                                                            PllNotLockedxD => (others => '0'));
+
+    -- Functions
+
+    function std_bool (exp_in : in boolean) return std_ulogic;
+
+end package aurora_status_pkg;
+
+-- Functions definitions
+
+package body aurora_status_pkg is
+
+    function std_bool (exp_in : in boolean)
+        return std_ulogic is
+    begin  -- function std_bool
+
+        if exp_in = true then
+            return '1';
+        else
+            return '0';
+        end if;
+
+    end function std_bool;
+
+end package body aurora_status_pkg;

ips/hw/phy_aurora/src/hdl/pkg/axi4_pkg.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: axi4_pkg
+-- Target Device: SCALP xc7z015clg485-2
+-- Tool version: 2019.2
+-- Description: AXI4 format bus signals.
+--
+-- Last update: 2020-09-03
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package axi4_pkg is
+
+    constant C_AXI4_DATA_SIZE     : integer range 0 to 32 := 32;
+    constant C_AXI4_KEEP_SIZE     : integer range 0 to 32 := 4;
+    constant C_AXI4_UFC_DATA_SIZE : integer range 0 to 32 := 3;
+    constant C_AXI4_NFC_DATA_SIZE : integer range 0 to 32 := 4;
+    constant C_AXI4_DEST_SIZE     : integer range 0 to 32 := 4;
+    constant C_AXI4_STRB_SIZE     : integer range 0 to 32 := C_AXI4_KEEP_SIZE;  -- Same as Keep
+    constant C_AXI4_USER_SIZE     : integer range 0 to 32 := 32;
+
+    -- AXI4 Framing
+    -- Master to Slave
+    type t_axi4m2s is record
+        -- Big Endian
+        DataxD  : std_ulogic_vector(0 to (C_AXI4_DATA_SIZE - 1));
+        KeepxD  : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+        LastxS  : std_ulogic;
+        ValidxS : std_ulogic;
+        -- Not Necessary
+        IdxS    : std_ulogic;
+        DestxD  : std_ulogic_vector(0 to (C_AXI4_DEST_SIZE - 1));
+        StrbxD  : std_ulogic_vector(0 to (C_AXI4_STRB_SIZE - 1));
+        UserxD  : std_ulogic_vector(0 to (C_AXI4_USER_SIZE - 1));
+    end record t_axi4m2s;
+
+    -- Slave to Master
+    type t_axi4s2m is record
+        ReadyxS : std_ulogic;
+    end record t_axi4s2m;
+
+    constant C_NO_AXI4_M2S : t_axi4m2s := (DataxD  => (others => '0'),
+                                           KeepxD  => (others => '0'),
+                                           LastxS  => '0',
+                                           ValidxS => '0',
+                                           IdxS    => '0',
+                                           DestxD  => (others => '0'),
+                                           StrbxD  => (others => '0'),
+                                           UserxD  => (others => '0'));
+    constant C_NO_AXI4_S2M : t_axi4s2m := (ReadyxS => '0');
+
+    -- Non-Generic Vector of AXI4 Framing Bus
+    ---------------------------------------------------------------------------
+    -- constant C_SIM_VIVADO_VECTOR_SIZE : integer := 6;
+    -- type t_axi4m2s_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4m2s;
+    -- type t_axi4s2m_vector is array ((C_SIM_VIVADO_VECTOR_SIZE - 1) downto 0) of t_axi4s2m;
+
+    -- constant C_NO_SIM_AXISM2S_VECTOR : t_axi4m2s_vector := (others => C_NO_AXI4_M2S);
+    -- constant C_NO_SIM_AXISS2M_VECTOR : t_axi4s2m_vector := (others => C_NO_AXI4_S2M);
+    -- -- Generic Vector of AXI4 Framing Bus Vector
+    -- type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+    -- type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+    ---------------------------------------------------------------------------   
+    -- Generic Vector of AXI4 Framing Bus
+    type t_axi4m2s_vector is array (natural range <>) of t_axi4m2s;
+    type t_axi4s2m_vector is array (natural range <>) of t_axi4s2m;
+
+    -- Generic Vector of AXI4 Framing Bus Vector
+    type t_axi4m2s_vector_vector is array (natural range <>) of t_axi4m2s_vector;
+    type t_axi4s2m_vector_vector is array (natural range <>) of t_axi4s2m_vector;
+
+    -- AXI4 UFC
+    -- Master to Slave
+    type t_axi4ufcm2s is record
+        -- Big Endian
+        DataxD  : std_ulogic_vector(0 to (C_AXI4_UFC_DATA_SIZE - 1));
+        KeepxD  : std_ulogic_vector(0 to (C_AXI4_KEEP_SIZE - 1));
+        ValidxS : std_ulogic;
+    end record t_axi4ufcm2s;
+
+    -- Slave to Master
+    type t_axi4ufcs2m is record
+        ReadyxS : std_ulogic;
+    end record t_axi4ufcs2m;
+
+    constant C_NO_AXI4_UFC_M2S : t_axi4ufcm2s := (DataxD  => (others => '0'),
+                                                  KeepxD  => (others => '0'),
+                                                  ValidxS => '0');
+    constant C_NO_AXI4_UFC_S2M : t_axi4ufcs2m := (ReadyxS => '0');
+
+    -- AXI4 NFC
+    -- Master to Slave
+    type t_axi4nfcm2s is record
+        -- Big Endian
+        DataxD  : std_ulogic_vector(0 to (C_AXI4_NFC_DATA_SIZE - 1));
+        ValidxS : std_ulogic;
+    end record t_axi4nfcm2s;
+
+    -- Slave to Master
+    type t_axi4nfcs2m is record
+        ReadyxS : std_ulogic;
+    end record t_axi4nfcs2m;
+
+    constant C_NO_AXI4_NFC_M2S : t_axi4nfcm2s := (DataxD  => (others => '0'),
+                                                  ValidxS => '0');
+    constant C_NO_AXI4_NFC_S2M : t_axi4nfcs2m := (ReadyxS => '0');
+
+    -- AXI4 Functions
+    -- OR reduce from t_axi4s2m_vector
+    function or_reduce_t_axi4s2m_vector (
+        signal VectorxD : t_axi4s2m_vector)
+        return t_axi4s2m;
+
+end package axi4_pkg;
+
+package body axi4_pkg is
+
+    -- AXI4 Functions
+    -- OR reduce from t_axi4s2m_vector
+    function or_reduce_t_axi4s2m_vector (
+        signal VectorxD : t_axi4s2m_vector)
+        return t_axi4s2m is
+        variable ResultxS : t_axi4s2m := C_NO_AXI4_S2M;
+    begin  -- function or_reduce_t_axi4s2m_vector
+        for i in VectorxD'range loop
+            ResultxS.ReadyxS := ResultxS.ReadyxS or VectorxD(i).ReadyxS;
+        end loop;  -- i
+
+        return ResultxS;
+    end function or_reduce_t_axi4s2m_vector;
+
+end package body axi4_pkg;

ips/hw/phy_aurora/src/sim/tb_phy_aurora.vhd

+----------------------------------------------------------------------------------
+--                                 _             _
+--                                | |_  ___ _ __(_)__ _
+--                                | ' \/ -_) '_ \ / _` |
+--                                |_||_\___| .__/_\__,_|
+--                                         |_|
+--
+----------------------------------------------------------------------------------
+--
+-- Company: hepia
+-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+--
+-- Module Name: tb_phy_aurora - arch
+-- Target Device: SCALP xc7k325tffg900-2
+-- Tool version: 2019.2
+-- Description: Testbench for phy_aurora
+--
+-- Last update: 2020-09-03 12:53:59
+--
+---------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_phy_aurora is
+end tb_phy_aurora;
+
+
+architecture behavioral of tb_phy_aurora is
+
+begin
+
+end behavioral;

ips/vivado/phy_aurora/2019.2/lin64/.scripts/.prompt_colors.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: phy_aurora
+# Target Device: SCALP xc7k325tffg900-2
+# Tool version: 2019.2
+# Description: Console color print utility
+#
+# Last update: 2020-09-03 12:53:59
+#
+##################################################################################
+
+# Text attributes
+set RESET [exec tput sgr0]
+set BOLD [exec tput bold]
+set ITALIC [exec tput sitm]
+set BLINK [exec tput blink]
+set HIGHL [exec tput smso]
+
+# Text colors
+set RED [exec tput setaf 1]
+set GREEN [exec tput setaf 2]
+set YELLOW [exec tput setaf 3]
+set BLUE [exec tput setaf 4]
+set MAGENTA [exec tput setaf 5]
+set CYAN [exec tput setaf 6]
+set WHITE [exec tput setaf 7]
+

ips/vivado/phy_aurora/2019.2/lin64/.scripts/clean_prj_phy_aurora.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: phy_aurora
+# Target Device: SCALP xc7k325tffg900-2
+# Tool version: 2019.2
+# Description: Cleanup project directory
+#
+# Last update: 2020-09-03 12:53:59
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/phy_aurora/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+

ips/vivado/phy_aurora/2019.2/lin64/.scripts/create_prj_phy_aurora.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: phy_aurora
+# Target Device: SCALP xc7k325tffg900-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-03 12:53:59
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_phy_aurora.tcl -notrace
+echo "> Done"
+

ips/vivado/phy_aurora/2019.2/lin64/.scripts/create_prj_phy_aurora.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: phy_aurora
+# Target Device: SCALP xc7k325tffg900-2
+# Tool version: 2019.2
+# Description: TCL script for re-creating Vivado project 'phy_aurora'
+#
+# Last update: 2020-09-03 12:53:59
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "phy_aurora"
+
+# Set project type
+set PRJ_TYPE "COMP_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7k325tffg900-2
+set_property board_part SCALP [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	# add HDL sources
+	set hdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list
+	# add the constraints file (XDC)
+	add_files -fileset constrs_1 -norecurse  $src_dir/constrs/${prj_name}.xdc
+	# add IPs source file
+	#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	# components sources are stored in an external directory
+	# add the project component
+	set hdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list
+	# add IPs source file
+	#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
+	# add IP-XACT source file
+	#add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+# Set packages libraries if any
+#set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	set hdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	set hdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$hdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit

ips/vivado/phy_aurora/2019.2/lin64/.scripts/open_prj_phy_aurora.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: phy_aurora
+# Target Device: SCALP xc7k325tffg900-2
+# Tool version: 2019.2
+# Description: Create Vivado project
+#
+# Last update: 2020-09-03 12:53:59
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../phy_aurora/phy_aurora.xpr

ips/vivado/phy_aurora/2019.2/lin64/.scripts/utils.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: phy_aurora
+# Target Device: SCALP xc7k325tffg900-2
+# Tool version: 2019.2
+# Description: Project management utilities
+#
+# Last update: 2020-09-03 12:53:59
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+    # Fix the directory name, this ensures the directory name is in the
+    # native format for the platform and contains a final directory seperator
+    set basedir [string trimright [file join [file normalize $basedir] { }]]
+    set fileList {}
+
+    # Look in the current directory for matching files, -type {f r}
+    # means ony readable normal files are looked at, -nocomplain stops
+    # an error being thrown if the returned list is empty
+    foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+        lappend fileList $fileName
+    }
+
+    # Now look for any sub direcories in the current directory
+    foreach dirName [glob -nocomplain -type {d  r} -path $basedir *] {
+        # Recusively call the routine on the sub directory and append any
+        # new files to the results
+        set subDirList [findFiles $dirName $pattern]
+        if { [llength $subDirList] > 0 } {
+            foreach subDirFile $subDirList {
+                lappend fileList $subDirFile
+            }
+        }
+    }
+    return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+    set MAX_STR_LENGTH 70
+    source .prompt_colors.tcl
+    puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+

ips/vivado/phy_aurora/2019.2/lin64/setup.sh

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: phy_aurora
+# Target Device: SCALP xc7k325tffg900-2
+# Tool version: 2019.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2020-09-03 12:53:59
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_phy_aurora.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_phy_aurora.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_phy_aurora.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_phy_aurora.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_phy_aurora.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_phy_aurora.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_phy_aurora.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_phy_aurora.sh && cd ..'