Commit 06714c72 authored by joachim.schmidt's avatar joachim.schmidt
Browse files

Creation of a project for the Zynq processor in the SOC folder.

parent 5f953c84
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-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: scalp_zynqps - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: scalp_zynqps
--
-- Last update: 2020-09-07
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity scalp_zynqps is
port (
DDR_addr : inout std_logic_vector (14 downto 0);
DDR_ba : inout std_logic_vector (2 downto 0);
DDR_cas_n : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cke : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_dm : inout std_logic_vector (3 downto 0);
DDR_dq : inout std_logic_vector (31 downto 0);
DDR_dqs_n : inout std_logic_vector (3 downto 0);
DDR_dqs_p : inout std_logic_vector (3 downto 0);
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_we_n : inout std_logic;
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
FclkClk0xCO : out std_logic;
FclkReset0xRO : out std_logic;
Spi1MOSIxSO : out std_logic;
Spi1SSxSO : out std_logic;
Spi1SclkxCO : out std_logic;
Usb0VBusPwrFaultxSI : in std_logic);
end scalp_zynqps;
architecture arch of scalp_zynqps is
begin
ScalpZynqPSxI : entity work.scalp_zynqps
port map (
DDR_addr => DDR_addr,
DDR_ba => DDR_ba,
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm => DDR_dm,
DDR_dq => DDR_dq,
DDR_dqs_n => DDR_dqs_n,
DDR_dqs_p => DDR_dqs_p,
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio => FIXED_IO_mio,
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
FclkClk0xCO => FclkClk0xCO,
FclkReset0xRO(0) => FclkReset0xRO,
Spi1MOSIxSO => Spi1MOSIxSO,
Spi1SSxSO => Spi1SSxSO,
Spi1SclkxCO => Spi1SclkxCO,
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI);
end arch;
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: tb_scalp_zynqps - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: Testbench for scalp_zynqps
--
-- Last update: 2020-09-07 11:18:55
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_scalp_zynqps is
end tb_scalp_zynqps;
architecture behavioral of tb_scalp_zynqps is
begin
end behavioral;
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Console color print utility
#
# Last update: 2020-09-07 11:18:55
#
##################################################################################
# Text attributes
set RESET [exec tput sgr0]
set BOLD [exec tput bold]
set ITALIC [exec tput sitm]
set BLINK [exec tput blink]
set HIGHL [exec tput smso]
# Text colors
set RED [exec tput setaf 1]
set GREEN [exec tput setaf 2]
set YELLOW [exec tput setaf 3]
set BLUE [exec tput setaf 4]
set MAGENTA [exec tput setaf 5]
set CYAN [exec tput setaf 6]
set WHITE [exec tput setaf 7]
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Cleanup project directory
#
# Last update: 2020-09-07 11:18:55
#
##################################################################################
echo "> Cleanup project directory..."
PRJ_DIR=..
# Clean current directory
rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory
rm -rf ${PRJ_DIR}/scalp_zynqps/ 2> /dev/null
# Clean app directory
rm ${PRJ_DIR}/app/*.h 2> /dev/null
rm ${PRJ_DIR}/app/*.c 2> /dev/null
rm ${PRJ_DIR}/app/*.html 2> /dev/null
echo "> Done"
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-09-07 11:18:55
#
##################################################################################
echo "> Create Vivado project..."
vivado -nojournal -nolog -mode tcl -source create_prj_scalp_zynqps.tcl -notrace
echo "> Done"
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_zynqps'
#
# Last update: 2020-09-07 11:18:55
#
##################################################################################
# Include files
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_zynqps"
# Set project type
set PRJ_TYPE "COMP_PRJ_TYPE"
# Create a variable to store the start time
set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../soc/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
#set_property board_part SCALP [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset]
update_ip_catalog
#----------------------------------------------------------------
# Add project sources
#----------------------------------------------------------------
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources
set hdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file
#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
set hdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
set hdl_src_file_list [list {*}$hdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
# Create the IP Integrator portion of the design
#create_bd_design "axi_design"
#update_compile_order -fileset sources_1
# launch the TCL script to generate the IPI design
source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
print_status "Add IPI design" "OK"
# Set the top level design
set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1
# Add testbench sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_sim_file_list [findFiles $src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $src_dir/sim *.v]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set hdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
}
set hdl_sim_file_list [list {*}$hdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Display the start and end time to the screen
puts $start_time
puts $end_time
exit
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_zynqps
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-09-07 11:18:55
#
##################################################################################
echo "> Open Vivado GUI..."
vivado -nojournal -nolog -notrace ../scalp_zynqps/scalp_zynqps.xpr
--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
--Date : Mon Sep 7 11:52:31 2020
--Host : xps13-debian running 64-bit Debian GNU/Linux 10 (buster)
--Command : generate_target scalp_zynqps_wrapper.bd
--Design : scalp_zynqps_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity scalp_zynqps_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FclkClk0xCO : out STD_LOGIC;
FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
Spi1MOSIxSO : out STD_LOGIC;
Spi1SSxSO : out STD_LOGIC;
Spi1SclkxCO : out STD_LOGIC;
Usb0VBusPwrFaultxSI : in STD_LOGIC
);
end scalp_zynqps_wrapper;
architecture STRUCTURE of scalp_zynqps_wrapper is
component scalp_zynqps is
port (
FclkClk0xCO : out STD_LOGIC;
FclkReset0xRO : out STD_LOGIC_VECTOR ( 0 to 0 );
Spi1MOSIxSO : out STD_LOGIC;
Spi1SSxSO : out STD_LOGIC;
Spi1SclkxCO : out STD_LOGIC;
Usb0VBusPwrFaultxSI : in STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component scalp_zynqps;
begin
scalp_zynqps_i: component scalp_zynqps
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
FclkClk0xCO => FclkClk0xCO,
FclkReset0xRO(0) => FclkReset0xRO(0),
Spi1MOSIxSO => Spi1MOSIxSO,
Spi1SSxSO => Spi1SSxSO,
Spi1SclkxCO => Spi1SclkxCO,
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI
);
end STRUCTURE;
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