Some changes in MIPI project :

- Fix pins IOSTANDARD
- Clean block design

designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc

@@ -153,6 +153,7 @@ set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
 #set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom7NxSIO]
 
 ##### Camera MIPI connector (Bank 34) #####
+set_property INTERNAL_VREF 0.6 [get_iobanks 34]
 # Camera GPIO_BTA
 set_property PACKAGE_PIN P6 [get_ports LVDS2V5Bottom6PxSIO]
 set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom6PxSIO]
@@ -169,16 +170,16 @@ set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom5NxSIO]
 set_property PULLTYPE PULLUP [get_ports LVDS2V5Bottom5NxSIO]
 # Camera LP_CLK_P
 set_property PACKAGE_PIN R3 [get_ports LVDS2V5Bottom4PxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom4PxSIO]
+set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom4PxSIO]
 # Camera LP_CLK_N
 set_property PACKAGE_PIN R2 [get_ports LVDS2V5Bottom4NxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom4NxSIO]
+set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom4NxSIO]
 # Camera LP_LANE1_P
 set_property PACKAGE_PIN P3 [get_ports LVDS2V5Bottom3PxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom3PxSIO]
+set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom3PxSIO]
 # Camera LP_LANE1_N
 set_property PACKAGE_PIN P2 [get_ports LVDS2V5Bottom3NxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom3NxSIO]
+set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom3NxSIO]
 # Camera HS_LANE1_P
 set_property PACKAGE_PIN N1 [get_ports LVDS2V5Bottom2PxSIO]
 set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom2PxSIO]
@@ -187,10 +188,10 @@ set_property PACKAGE_PIN P1 [get_ports LVDS2V5Bottom2NxSIO]
 set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom2NxSIO]
 # Camera LP_LANE0_P
 set_property PACKAGE_PIN N4 [get_ports LVDS2V5Bottom1PxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom1PxSIO]
+set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom1PxSIO]
 # Camera LP_LANE0_N
 set_property PACKAGE_PIN N3 [get_ports LVDS2V5Bottom1NxSIO]
-set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom1NxSIO]
+set_property IOSTANDARD HSUL_12 [get_ports LVDS2V5Bottom1NxSIO]
 # Camera HS_LANE0_P
 set_property PACKAGE_PIN M2 [get_ports LVDS2V5Bottom0PxSIO]
 set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom0PxSIO]

soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl

@@ -123,7 +123,6 @@ set bCheckIPs 1
 if { $bCheckIPs == 1 } {
    set list_check_ips "\ 
 xilinx.com:ip:axi_data_fifo:2.1\
-xilinx.com:ip:axi_intc:4.1\
 xilinx.com:ip:axis_subset_converter:1.1\
 xilinx.com:ip:clk_wiz:6.0\
 xilinx.com:ip:xlconstant:1.1\
@@ -240,12 +239,6 @@ proc create_root_design { parentCell } {
    CONFIG.READ_FIFO_DEPTH {512} \
  ] $axi_data_fifo_0
 
-  # Create instance: axi_intc_0, and set properties
-  set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
-  set_property -dict [ list \
-   CONFIG.C_IRQ_CONNECTION {1} \
- ] $axi_intc_0
-
   # Create instance: axi_mem_intercon, and set properties
   set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ]
   set_property -dict [ list \
@@ -780,8 +773,8 @@ proc create_root_design { parentCell } {
   # Create instance: ps7_0_axi_periph, and set properties
   set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
   set_property -dict [ list \
-   CONFIG.NUM_MI {5} \
-   CONFIG.NUM_SI {2} \
+   CONFIG.NUM_MI {4} \
+   CONFIG.NUM_SI {1} \
  ] $ps7_0_axi_periph
 
   # Create instance: rst_ps7_0_125M, and set properties
@@ -869,7 +862,6 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins mipi_csi2_rx_subsyst_0/csirxss_s_axi] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins v_frmbuf_wr_0/s_axi_CTRL]
-  connect_bd_intf_net -intf_net ps7_0_axi_periph_M04_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins ps7_0_axi_periph/M04_AXI]
   connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_data_fifo_0/S_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
 
   # Create port connections
@@ -878,17 +870,16 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
   connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
   connect_bd_net -net RdDataxDI_0_1 [get_bd_ports RdDataxDI] [get_bd_pins scalp_axi4lite_0/RdDataxDI]
   connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
-  connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins processing_system7_0/IRQ_F2P]
   connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mipi_csi2_rx_subsyst_0/dphy_clk_200M]
   connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
-  connect_bd_net -net irq_xlconcat_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins irq_xlconcat/dout]
+  connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
   connect_bd_net -net mipi_csi2_rx_subsyst_0_csirxss_csi_irq [get_bd_pins irq_xlconcat/In1] [get_bd_pins mipi_csi2_rx_subsyst_0/csirxss_csi_irq]
-  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/M04_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins ps7_0_axi_periph/S01_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins vio_0/clk]
+  connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_data_fifo_0/aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axis_subset_converter_0/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aclk] [get_bd_pins mipi_csi2_rx_subsyst_0/video_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/M03_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_axi4lite_0/SAxiClkxCI] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk] [get_bd_pins v_frmbuf_wr_0/ap_clk] [get_bd_pins vio_0/clk]
   connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
   connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
   connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
   connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
-  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/M04_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins ps7_0_axi_periph/S01_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
+  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins mipi_csi2_rx_subsyst_0/lite_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/M03_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_axi4lite_0/SAxiResetxRANI] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn] [get_bd_pins v_frmbuf_wr_0/ap_rst_n]
   connect_bd_net -net scalp_axi4lite_0_InterruptxSO [get_bd_pins irq_xlconcat/In0] [get_bd_pins scalp_axi4lite_0/InterruptxSO]
   connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
   connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
@@ -902,10 +893,9 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_IIC_1] [get
   connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
 
   # Create address segments
-  assign_bd_address -offset 0x41800000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
   assign_bd_address -offset 0x43C20000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg] -force
   assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_axi4lite_0/SAXILitexDIO/SAXILiteAddr] -force
-  assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
+  assign_bd_address -offset 0x43C10000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
   assign_bd_address -offset 0x43C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs v_frmbuf_wr_0/s_axi_CTRL/Reg] -force
   assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces v_frmbuf_wr_0/Data_m_axi_mm_video] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force