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Commit 0d402bd1 authored by joachim.schmidt's avatar joachim.schmidt
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Update scalp_axis_fifo_wrapper with tlast internal management

parent 99042ffd
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2020.2 -- Tool version: 2020.2
-- Description: scalp_axis_fifo_wrapper -- Description: scalp_axis_fifo_wrapper
-- --
-- Last update: 2021-05-31 -- Last update: 2021-09-07
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
...@@ -30,6 +30,9 @@ use unisim.vcomponents.all; ...@@ -30,6 +30,9 @@ use unisim.vcomponents.all;
entity scalp_axis_fifo_wrapper is entity scalp_axis_fifo_wrapper is
generic (
C_CTRL_TLAST : boolean := true);
port ( port (
ClkxCI : in t_axi4_dual_clk; ClkxCI : in t_axi4_dual_clk;
ResetxRI : in t_axi4_rst; ResetxRI : in t_axi4_rst;
...@@ -50,29 +53,46 @@ architecture arch of scalp_axis_fifo_wrapper is ...@@ -50,29 +53,46 @@ architecture arch of scalp_axis_fifo_wrapper is
s_axis_tvalid : in std_logic; s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic; s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); s_axis_tdata : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
s_axis_tstrb : in std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0); -- s_axis_tstrb : in std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0);
s_axis_tkeep : in std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0); -- s_axis_tkeep : in std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
s_axis_tlast : in std_logic; s_axis_tlast : in std_logic;
s_axis_tid : in std_logic_vector(0 downto 0); -- s_axis_tid : in std_logic_vector(0 downto 0);
s_axis_tdest : in std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0); -- s_axis_tdest : in std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0);
s_axis_tuser : in std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0); -- s_axis_tuser : in std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0);
m_axis_aclk : in std_logic; m_axis_aclk : in std_logic;
m_axis_tvalid : out std_logic; m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic; m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); m_axis_tdata : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
m_axis_tstrb : out std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0); -- m_axis_tstrb : out std_logic_vector((C_AXI4_STRB_SIZE - 1) downto 0);
m_axis_tkeep : out std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0); -- m_axis_tkeep : out std_logic_vector((C_AXI4_KEEP_SIZE - 1) downto 0);
m_axis_tlast : out std_logic; m_axis_tlast : out std_logic;
m_axis_tid : out std_logic_vector(0 downto 0); -- m_axis_tid : out std_logic_vector(0 downto 0);
m_axis_tdest : out std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0); -- m_axis_tdest : out std_logic_vector((C_AXI4_DEST_SIZE - 1) downto 0);
m_axis_tuser : out std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0); -- m_axis_tuser : out std_logic_vector((C_AXI4_USER_SIZE - 1) downto 0);
axis_wr_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); axis_wr_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
axis_rd_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0); axis_rd_data_count : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
prog_full : out std_logic); prog_full : out std_logic);
end component; end component;
signal TXM2SLastxS : std_ulogic := '0';
-- Attributes
attribute mark_debug : string;
attribute keep : string;
--
begin -- architecture arch begin -- architecture arch
CtrlTLastxG : if C_CTRL_TLAST = true generate
TXM2SLastxAS : TXM2SxDO.LastxS <= '1' when (TXM2SLastxS = '1') and (TXM2SxDO.ValidxS = '1') else '0';
elsif C_CTRL_TLAST = false generate
TXM2SLastxAS : TXM2SxDO.LastxS <= TXM2SLastxS;
end generate CtrlTLastxG;
ScalpAxisFifoCorexI : entity work.scalp_axis_fifo ScalpAxisFifoCorexI : entity work.scalp_axis_fifo
port map ( port map (
s_axis_aresetn => ResetxRI.RstxRAN, s_axis_aresetn => ResetxRI.RstxRAN,
...@@ -80,22 +100,22 @@ begin -- architecture arch ...@@ -80,22 +100,22 @@ begin -- architecture arch
s_axis_tvalid => RXM2SxDI.ValidxS, s_axis_tvalid => RXM2SxDI.ValidxS,
s_axis_tready => RXS2MxSO.ReadyxS, s_axis_tready => RXS2MxSO.ReadyxS,
s_axis_tdata => RXM2SxDI.DataxD, s_axis_tdata => RXM2SxDI.DataxD,
s_axis_tstrb => RXM2SxDI.StrbxD, -- s_axis_tstrb => RXM2SxDI.StrbxD,
s_axis_tkeep => RXM2SxDI.KeepxD, -- s_axis_tkeep => RXM2SxDI.KeepxD,
s_axis_tlast => RXM2SxDI.LastxS, s_axis_tlast => RXM2SxDI.LastxS,
s_axis_tid(0) => RXM2SxDI.IdxS, -- s_axis_tid(0) => RXM2SxDI.IdxS,
s_axis_tdest => RXM2SxDI.DestxD, -- s_axis_tdest => RXM2SxDI.DestxD,
s_axis_tuser => RXM2SxDI.UserxD, -- s_axis_tuser => RXM2SxDI.UserxD,
m_axis_aclk => ClkxCI.TXClkxC, m_axis_aclk => ClkxCI.TXClkxC,
m_axis_tvalid => TXM2SxDO.ValidxS, m_axis_tvalid => TXM2SxDO.ValidxS,
m_axis_tready => TXS2MxSI.ReadyxS, m_axis_tready => TXS2MxSI.ReadyxS,
m_axis_tdata => TXM2SxDO.DataxD, m_axis_tdata => TXM2SxDO.DataxD,
m_axis_tstrb => TXM2SxDO.StrbxD, -- m_axis_tstrb => TXM2SxDO.StrbxD,
m_axis_tkeep => TXM2SxDO.KeepxD, -- m_axis_tkeep => TXM2SxDO.KeepxD,
m_axis_tlast => TXM2SxDO.LastxS, m_axis_tlast => TXM2SLastxS,
m_axis_tid(0) => TXM2SxDO.IdxS, -- m_axis_tid(0) => TXM2SxDO.IdxS,
m_axis_tdest => TXM2SxDO.DestxD, -- m_axis_tdest => TXM2SxDO.DestxD,
m_axis_tuser => TXM2SxDO.UserxD, -- m_axis_tuser => TXM2SxDO.UserxD,
axis_wr_data_count => FifoStatusxDO.WrDataCntxD, axis_wr_data_count => FifoStatusxDO.WrDataCntxD,
axis_rd_data_count => FifoStatusxDO.RdDataCntxD, axis_rd_data_count => FifoStatusxDO.RdDataCntxD,
prog_full => FifoStatusxDO.ProgFullxS); prog_full => FifoStatusxDO.ProgFullxS);
......
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