Update scalp_zynqp

soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl

@@ -127,7 +127,7 @@ xilinx.com:ip:xlconstant:1.1\
 xilinx.com:ip:xlconcat:2.1\
 xilinx.com:ip:processing_system7:5.5\
 xilinx.com:ip:proc_sys_reset:5.0\
-hepia.hesge.ch:user:scalp_router_regbank:0.8\
+hepia.hesge.ch:user:scalp_router_regbank:1.0\
 hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\
 xilinx.com:ip:util_vector_logic:2.0\
 xilinx.com:ip:vio:3.0\
@@ -691,7 +691,7 @@ proc create_root_design { parentCell } {
   set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
 
   # Create instance: scalp_router_regbank_0, and set properties
-  set scalp_router_regbank_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:0.8 scalp_router_regbank_0 ]
+  set scalp_router_regbank_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:1.0 scalp_router_regbank_0 ]
 
   # Create instance: scalp_safe_firmware_0, and set properties
   set scalp_safe_firmware_0 [ create_bd_cell -type ip -vlnv hepia.ch:user:scalp_safe_firmware_reg_bank:1.3 scalp_safe_firmware_0 ]