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Commit 27737797 authored by joachim.schmidt's avatar joachim.schmidt
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Update with DMA block design

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designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
+ 37
− 305
View file @ 27737797
......@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_router_firmware
--
-- Last update: 2021-09-17
-- Last update: 2021-09-20
--
---------------------------------------------------------------------------------
......@@ -565,61 +565,6 @@ architecture arch of scalp_router_firmware is
attribute keep of AuroraClkSlavexC : signal is "true";
attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
attribute mark_debug of NorthRXM2SxD : signal is "true";
attribute keep of NorthRXM2SxD : signal is "true";
attribute mark_debug of NorthRXS2MxD : signal is "true";
attribute keep of NorthRXS2MxD : signal is "true";
attribute mark_debug of NorthTXM2SxD : signal is "true";
attribute keep of NorthTXM2SxD : signal is "true";
attribute mark_debug of NorthTXS2MxD : signal is "true";
attribute keep of NorthTXS2MxD : signal is "true";
attribute mark_debug of EastRXM2SxD : signal is "true";
attribute keep of EastRXM2SxD : signal is "true";
attribute mark_debug of EastRXS2MxD : signal is "true";
attribute keep of EastRXS2MxD : signal is "true";
attribute mark_debug of EastTXM2SxD : signal is "true";
attribute keep of EastTXM2SxD : signal is "true";
attribute mark_debug of EastTXS2MxD : signal is "true";
attribute keep of EastTXS2MxD : signal is "true";
attribute mark_debug of SouthRXM2SxD : signal is "true";
attribute keep of SouthRXM2SxD : signal is "true";
attribute mark_debug of SouthRXS2MxD : signal is "true";
attribute keep of SouthRXS2MxD : signal is "true";
attribute mark_debug of SouthTXM2SxD : signal is "true";
attribute keep of SouthTXM2SxD : signal is "true";
attribute mark_debug of SouthTXS2MxD : signal is "true";
attribute keep of SouthTXS2MxD : signal is "true";
attribute mark_debug of WestRXM2SxD : signal is "true";
attribute keep of WestRXM2SxD : signal is "true";
attribute mark_debug of WestRXS2MxD : signal is "true";
attribute keep of WestRXS2MxD : signal is "true";
attribute mark_debug of WestTXM2SxD : signal is "true";
attribute keep of WestTXM2SxD : signal is "true";
attribute mark_debug of WestTXS2MxD : signal is "true";
attribute keep of WestTXS2MxD : signal is "true";
attribute mark_debug of LocNetAddrxD : signal is "true";
attribute keep of LocNetAddrxD : signal is "true";
--
attribute mark_debug of TXAxism2sVectorxD : signal is "true";
attribute keep of TXAxism2sVectorxD : signal is "true";
attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
attribute keep of TXAxiss2mVectorxD : signal is "true";
attribute mark_debug of RXFifoTXM2SxD : signal is "true";
attribute keep of RXFifoTXM2SxD : signal is "true";
attribute mark_debug of RXFifoTXS2MxS : signal is "true";
attribute keep of RXFifoTXS2MxS : signal is "true";
attribute mark_debug of RXFifoStatusxD : signal is "true";
attribute keep of RXFifoStatusxD : signal is "true";
attribute mark_debug of TXFifoRXM2SxD : signal is "true";
attribute keep of TXFifoRXM2SxD : signal is "true";
attribute mark_debug of TXFifoRXS2MxS : signal is "true";
attribute keep of TXFifoRXS2MxS : signal is "true";
attribute mark_debug of RXAxism2sVectorxD : signal is "true";
attribute keep of RXAxism2sVectorxD : signal is "true";
attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
attribute keep of RXAxiss2mVectorxD : signal is "true";
attribute mark_debug of TXFifoStatusxD : signal is "true";
attribute keep of TXFifoStatusxD : signal is "true";
begin
......@@ -662,19 +607,7 @@ begin
-- MIO
FIXED_IO_mio => MIOxDIO,
UserClkxCI => AuroraClkMasterxC.UserClkxC,
UserResetxRANI => ScalpRouterResetxRNA,
-- Scalp Axi Lite interface and IRQ
Irq0xDI => (others => '0'),
ScalpPacketWriteDataxDO => ScalpPacketWriteDataxD,
ScalpPacketReadDataxDI => ScalpPacketReadDataxD,
ScalpPacketCtrlxDO => ScalpPacketCtrlxD,
ScalpPacketStatusxDI => ScalpPacketStatusxD,
RXRdDataCntxDI => RXRdDataCntxD,
RXWrDataCntxDI => RXWrDataCntxD,
TXRdDataCntxDI => TXRdDataCntxD,
TXWrDataCntxDI => TXWrDataCntxD,
LocNetAddrxDO => LocNetAddrVectxD,
RgbLedsCtrlPortxDO => open);
UserResetxRANI => ScalpRouterResetxRNA);
end block ProcessingSystemxB;
......@@ -1100,207 +1033,6 @@ begin
SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
WrSpValidxI : entity work.vio_axi_cnt_ctrl
port map (
clk => AuroraClkMasterxC.UserClkxC,
probe_out0(0) => VioWrSpValidxS);
TXFifoStatusWrDataCntxAS : TXWrDataCntxD <= TXFifoStatusxD.WrDataCntxD;
TXFifoStatusRdDataCntxAS : TXRdDataCntxD <= TXFifoStatusxD.RdDataCntxD;
TXFifoStatusProgFullxAS : ScalpPacketStatusxD(C_TX_PROG_FULL) <= TXFifoStatusxD.ProgFullxS;
TXFifoWrDataxP : process (AuroraClkMasterxC.UserClkxC,
ScalpRouterResetxRNA) is
begin -- process TXFifoWrDataxP
if ScalpRouterResetxRNA = '0' then
TXFifoRXM2SxD <= C_NO_AXI4_M2S;
TXFifoWrDataStatexD <= E_WR_IDLE;
TXFifoWrDataStateNextxD <= E_WR_IDLE;
elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
-- Default Values
TXFifoRXM2SxD <= TXFifoRXM2SxD;
TXFifoWrDataStatexD <= TXFifoWrDataStatexD;
TXFifoWrDataStateNextxD <= TXFifoWrDataStateNextxD;
case TXFifoWrDataStatexD is
when E_WR_IDLE =>
TXFifoRXM2SxD.DataxD <= (others => '0');
TXFifoRXM2SxD.ValidxS <= '0';
TXFifoRXM2SxD.LastxS <= '0';
if ScalpPacketCtrlxD(C_WR_NEW_PACKET) = '1' then
TXFifoWrDataStatexD <= E_WR_H0;
end if;
when E_WR_H0 =>
TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD(31 downto 24) & ScalpPacketWriteDataxD(23 downto 16) &
ScalpPacketWriteDataxD(15 downto 8) & ScalpPacketWriteDataxD(7 downto 0));
TXFifoRXM2SxD.ValidxS <= '0';
TXFifoRXM2SxD.LastxS <= '0';
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
TXFifoWrDataStateNextxD <= E_WR_H1;
end if;
when E_WR_H1 =>
TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD(31 downto 24) & ScalpPacketWriteDataxD(23 downto 16) &
ScalpPacketWriteDataxD(15 downto 8) & "00000000");
TXFifoRXM2SxD.ValidxS <= '0';
TXFifoRXM2SxD.LastxS <= '0';
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
TXFifoWrDataStateNextxD <= E_WR_H2;
end if;
when E_WR_H2 =>
TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD(31 downto 16) & "0000000000000000");
TXFifoRXM2SxD.ValidxS <= '0';
TXFifoRXM2SxD.LastxS <= '0';
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
TXFifoWrDataStateNextxD <= E_WR_PLD;
end if;
when E_WR_PLD =>
TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD);
TXFifoRXM2SxD.ValidxS <= '0';
TXFifoRXM2SxD.LastxS <= '0';
if ScalpPacketCtrlxD(C_WR_VALID) = '1' and ScalpPacketCtrlxD(C_WR_NEXT) = '0' then
TXFifoRXM2SxD.ValidxS <= '1';
TXFifoWrDataStatexD <= E_WR_NEXT;
if ScalpPacketCtrlxD(C_WR_LAST) = '1' then
TXFifoRXM2SxD.LastxS <= '1';
TXFifoWrDataStateNextxD <= E_WR_IDLE;
else
TXFifoWrDataStateNextxD <= E_WR_PLD;
end if;
end if;
when E_WR_NEXT =>
TXFifoRXM2SxD.DataxD <= change_endian_ul(ScalpPacketWriteDataxD);
TXFifoRXM2SxD.ValidxS <= '0';
TXFifoRXM2SxD.LastxS <= '0';
if ScalpPacketCtrlxD(C_WR_NEXT) = '1' and ScalpPacketCtrlxD(C_WR_VALID) = '0' then
TXFifoWrDataStatexD <= TXFifoWrDataStateNextxD;
end if;
when others => null;
end case;
end if;
end process TXFifoWrDataxP;
-- TX Fifo
ScalpAxisFifoWrapperTXxI : entity work.scalp_axis_fifo_wrapper
generic map (
C_CTRL_TLAST => true)
port map (
ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC,
ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC,
ResetxRI.RstxRAN => ScalpRouterResetxRNA,
RXM2SxDI => TXFifoRXM2SxD,
RXS2MxSO => TXFifoRXS2MxS,
TXM2SxDO => RXAxism2sVectorxD(C_LOCAL_IF_ID),
TXS2MxSI => RXAxiss2mVectorxD(C_LOCAL_IF_ID),
FifoStatusxDO => TXFifoStatusxD);
RXFifoStatusWrDataCntxAS : RXWrDataCntxD <= RXFifoStatusxD.WrDataCntxD;
RXFifoStatusRdDataCntxAS : RXRdDataCntxD <= RXFifoStatusxD.RdDataCntxD;
RXFifoStatusProgFullxAS : ScalpPacketStatusxD(C_RX_PROG_FULL) <= RXFifoStatusxD.ProgFullxS;
RXFifoRdDataxP : process (AuroraClkMasterxC.UserClkxC,
ScalpRouterResetxRNA) is
variable HeaderCountxD : integer := 0;
begin -- process RXFifoRdDataxP
if ScalpRouterResetxRNA = '0' then
RXFifoRdDataStatexD <= E_RD_IDLE;
RXFifoRdDataStateNextxD <= E_RD_IDLE;
ScalpPacketReadDataxD <= (others => '0');
ScalpPacketStatusxD(C_RD_VALID) <= '0';
ScalpPacketStatusxD(C_RD_LAST) <= '0';
-- HeaderCountxD := 0;
elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
-- Default Values
RXFifoTXS2MxS.ReadyxS <= '0';
ScalpPacketReadDataxD <= (others => '0');
ScalpPacketStatusxD(C_RD_VALID) <= '0';
ScalpPacketStatusxD(C_RD_LAST) <= ScalpPacketStatusxD(C_RD_LAST);
ScalpPacketStatusxD(C_RD_WAIT_NEXT) <= '0';
RXFifoRdDataStatexD <= RXFifoRdDataStatexD;
RXFifoRdDataStateNextxD <= RXFifoRdDataStateNextxD;
-- HeaderCountxD := HeaderCountxD;
case RXFifoRdDataStatexD is
when E_RD_IDLE =>
if ScalpPacketCtrlxD(C_RD_NEW_PACKET) = '1' then
ScalpPacketStatusxD(C_RD_LAST) <= '0';
RXFifoRdDataStatexD <= E_RD_WORD;
-- HeaderCountxD := 0;
end if;
when E_RD_WORD =>
if RXFifoTXM2SxD.ValidxS = '1' and ScalpPacketCtrlxD(C_RD_NEXT) = '0' then
-- if HeaderCountxD = 0 then
-- ScalpPacketReadDataxD <= change_endian_ul(RXFifoTXM2SxD.DataxD);
-- elsif HeaderCountxD = 1 then
-- ScalpPacketReadDataxD <= change_endian_ul(RXFifoTXM2SxD.DataxD);
-- elsif HeaderCountxD = 2 then
-- ScalpPacketReadDataxD <= change_endian_ul("0000000000000000" & RXFifoTXM2SxD.DataxD(15 downto 0));
-- else
-- ScalpPacketReadDataxD <= change_endian_ul(RXFifoTXM2SxD.DataxD);
-- end if;
ScalpPacketReadDataxD <= change_endian_ul(RXFifoTXM2SxD.DataxD);
ScalpPacketStatusxD(C_RD_VALID) <= '1';
RXFifoRdDataStatexD <= E_RD_NEXT;
RXFifoRdDataStateNextxD <= E_RD_WORD;
if RXFifoTXM2SxD.LastxS = '1' then
ScalpPacketStatusxD(C_RD_LAST) <= '1';
RXFifoRdDataStateNextxD <= E_RD_IDLE;
end if;
end if;
when E_RD_NEXT =>
ScalpPacketReadDataxD <= change_endian_ul(RXFifoTXM2SxD.DataxD);
ScalpPacketStatusxD(C_RD_VALID) <= '1';
ScalpPacketStatusxD(C_RD_WAIT_NEXT) <= '1';
if ScalpPacketCtrlxD(C_RD_NEXT) = '1' then
RXFifoTXS2MxS.ReadyxS <= '1';
RXFifoRdDataStatexD <= RXFifoRdDataStateNextxD;
-- HeaderCountxD := HeaderCountxD + 1;
end if;
when others => null;
end case;
end if;
end process RXFifoRdDataxP;
-- RX Fifo
ScalpAxisFifoWrapperRXxI : entity work.scalp_axis_fifo_wrapper
generic map (
C_CTRL_TLAST => true)
port map (
ClkxCI.RXClkxC => AuroraClkMasterxC.UserClkxC,
ClkxCI.TXClkxC => AuroraClkMasterxC.UserClkxC,
ResetxRI.RstxRAN => ScalpRouterResetxRNA,
RXM2SxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
RXS2MxSO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
TXM2SxDO => RXFifoTXM2SxD,
TXS2MxSI => RXFifoTXS2MxS,
FifoStatusxDO => RXFifoStatusxD);
ScalpRouterxI : entity work.scalp_router
generic map (
C_SCALP_NUMBER_OF_INTERFACE => C_SCALP_NUMBER_OF_INTERFACE,
......
soc/hw/scalp_zynqps/src/hdl/scalp_zynqps_wrapper.vhd
+ 59
− 82
View file @ 27737797
......@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
-- Last update: 2021-06-22
-- Last update: 2021-09-20
--
---------------------------------------------------------------------------------
......@@ -60,19 +60,7 @@ entity scalp_zynqps_wrapper is
-- MIO
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
UserClkxCI : in std_logic;
UserResetxRANI : in std_logic;
-- Scalp Axi Lite interface and IRQ
Irq0xDI : in std_logic_vector(0 to 0);
ScalpPacketWriteDataxDO : out std_logic_vector(31 downto 0);
ScalpPacketReadDataxDI : in std_logic_vector(31 downto 0);
ScalpPacketCtrlxDO : out std_logic_vector(31 downto 0);
ScalpPacketStatusxDI : in std_logic_vector(31 downto 0);
RgbLedsCtrlPortxDO : out std_logic_vector(31 downto 0);
RXRdDataCntxDI : in std_logic_vector(31 downto 0);
RXWrDataCntxDI : in std_logic_vector(31 downto 0);
TXRdDataCntxDI : in std_logic_vector(31 downto 0);
TXWrDataCntxDI : in std_logic_vector(31 downto 0);
LocNetAddrxDO : out std_logic_vector(31 downto 0));
UserResetxRANI : in std_logic);
end scalp_zynqps_wrapper;
......@@ -110,17 +98,6 @@ begin
Spi1SclkxCO => Spi1SclkxCO,
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI,
UserClkxCI => UserClkxCI,
UserResetxRANI => UserResetxRANI,
Irq0xDI => Irq0xDI,
ScalpPacketWriteDataxDO => ScalpPacketWriteDataxDO,
ScalpPacketReadDataxDI => ScalpPacketReadDataxDI,
ScalpPacketCtrlxDO => ScalpPacketCtrlxDO,
ScalpPacketStatusxDI => ScalpPacketStatusxDI,
RXRdDataCntxDI => RXRdDataCntxDI,
RXWrDataCntxDI => RXWrDataCntxDI,
TXRdDataCntxDI => TXRdDataCntxDI,
TXWrDataCntxDI => TXWrDataCntxDI,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO,
LocNetAddrxDO => LocNetAddrxDO);
UserResetxRANI => UserResetxRANI);
end arch;
soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl
+ 56
− 47
View file @ 27737797
......@@ -123,14 +123,14 @@ set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:axis_data_fifo:2.0\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
hepia.hesge.ch:user:scalp_router_regbank:1.0\
hepia.ch:user:scalp_safe_firmware_reg_bank:1.3\
xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
xilinx.com:ip:xlconcat:2.1\
"
set list_ips_missing ""
......@@ -205,20 +205,9 @@ proc create_root_design { parentCell } {
CONFIG.FREQ_HZ {125000000} \
] $FclkClk0xCO
set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
set Irq0xDI [ create_bd_port -dir I -from 0 -to 0 Irq0xDI ]
set LocNetAddrxDO [ create_bd_port -dir O -from 31 -to 0 -type data LocNetAddrxDO ]
set RXRdDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data RXRdDataCntxDI ]
set RXWrDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data RXWrDataCntxDI ]
set RgbLedsCtrlPortxDO [ create_bd_port -dir O -from 31 -to 0 RgbLedsCtrlPortxDO ]
set ScalpPacketCtrlxDO [ create_bd_port -dir O -from 31 -to 0 -type data ScalpPacketCtrlxDO ]
set ScalpPacketReadDataxDI [ create_bd_port -dir I -from 31 -to 0 -type data ScalpPacketReadDataxDI ]
set ScalpPacketStatusxDI [ create_bd_port -dir I -from 31 -to 0 -type data ScalpPacketStatusxDI ]
set ScalpPacketWriteDataxDO [ create_bd_port -dir O -from 31 -to 0 -type data ScalpPacketWriteDataxDO ]
set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
set TXRdDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data TXRdDataCntxDI ]
set TXWrDataCntxDI [ create_bd_port -dir I -from 31 -to 0 -type data TXWrDataCntxDI ]
set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
set UserClkxCI [ create_bd_port -dir I -type clk -freq_hz 125000000 UserClkxCI ]
set UserResetxRANI [ create_bd_port -dir I -type rst UserResetxRANI ]
......@@ -226,18 +215,42 @@ proc create_root_design { parentCell } {
# Create instance: axi_clock_converter_0, and set properties
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: axi_clock_converter_1, and set properties
set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
# Create instance: axi_clock_converter_2, and set properties
set axi_clock_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_2 ]
# Create instance: axi_dma_0, and set properties
set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
set_property -dict [ list \
CONFIG.c_include_sg {0} \
CONFIG.c_sg_include_stscntrl_strm {0} \
] $axi_dma_0
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {2} \
] $axi_interconnect_0
# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
set_property -dict [ list \
CONFIG.ENABLE_ECC {0} \
CONFIG.FIFO_DEPTH {4096} \
CONFIG.FIFO_MEMORY_TYPE {block} \
CONFIG.HAS_RD_DATA_COUNT {1} \
CONFIG.HAS_WR_DATA_COUNT {1} \
] $axis_data_fifo_0
# Create instance: gnd_constant, and set properties
set gnd_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant ]
set_property -dict [ list \
CONFIG.CONST_VAL {0} \
] $gnd_constant
# Create instance: irq_xlconcat, and set properties
set irq_xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 irq_xlconcat ]
set_property -dict [ list \
CONFIG.NUM_PORTS {1} \
] $irq_xlconcat
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
......@@ -679,23 +692,18 @@ proc create_root_design { parentCell } {
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_S_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \
] $processing_system7_0
# Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {2} \
CONFIG.NUM_MI {1} \
] $ps7_0_axi_periph
# Create instance: rst_ps7_0_125M, and set properties
set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
# Create instance: scalp_router_regbank_0, and set properties
set scalp_router_regbank_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_router_regbank:1.0 scalp_router_regbank_0 ]
# Create instance: scalp_safe_firmware_0, and set properties
set scalp_safe_firmware_0 [ create_bd_cell -type ip -vlnv hepia.ch:user:scalp_safe_firmware_reg_bank:1.3 scalp_safe_firmware_0 ]
# Create instance: util_vector_logic_0, and set properties
set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
set_property -dict [ list \
......@@ -719,44 +727,45 @@ proc create_root_design { parentCell } {
CONFIG.C_NUM_PROBE_IN {0} \
] $vio_0
# Create instance: xlconcat_0, and set properties
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
# Create interface connections
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins scalp_router_regbank_0/SAxiLitexDIO]
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_dma_0/S_AXI_LITE]
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_2_M_AXI [get_bd_intf_pins axi_clock_converter_2/M_AXI] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_data_fifo_0/S_AXIS]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_MM2S]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_clock_converter_2/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_S2MM]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
# Create port connections
connect_bd_net -net In0_0_1 [get_bd_ports Irq0xDI] [get_bd_pins irq_xlconcat/In0]
connect_bd_net -net RXRdDataCntxDI_1 [get_bd_ports RXRdDataCntxDI] [get_bd_pins scalp_router_regbank_0/RXRdDataCntxDI]
connect_bd_net -net RXWrDataCntxDI_1 [get_bd_ports RXWrDataCntxDI] [get_bd_pins scalp_router_regbank_0/RXWrDataCntxDI]
connect_bd_net -net ScalpPacketReadDataxDI_1 [get_bd_ports ScalpPacketReadDataxDI] [get_bd_pins scalp_router_regbank_0/ScalpPacketReadDataxDI]
connect_bd_net -net ScalpPacketStatusxDI_1 [get_bd_ports ScalpPacketStatusxDI] [get_bd_pins scalp_router_regbank_0/ScalpPacketStatusxDI]
connect_bd_net -net TXRdDataCntxDI_1 [get_bd_ports TXRdDataCntxDI] [get_bd_pins scalp_router_regbank_0/TXRdDataCntxDI]
connect_bd_net -net TXWrDataCntxDI_1 [get_bd_ports TXWrDataCntxDI] [get_bd_pins scalp_router_regbank_0/TXWrDataCntxDI]
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins scalp_router_regbank_0/SAxiClkxCI]
connect_bd_net -net UserResetxRNA_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins scalp_router_regbank_0/SAxiRstxRANI]
connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins axi_clock_converter_2/s_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk]
connect_bd_net -net UserResetxRANI_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins axi_clock_converter_2/s_axi_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn]
connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0]
connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1]
connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net irq_xlconcat_dout [get_bd_pins irq_xlconcat/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_safe_firmware_0/SAxiClkxCI] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_clock_converter_2/m_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins vio_0/clk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_safe_firmware_0/SAxiRstxRANI]
connect_bd_net -net scalp_router_regbank_0_LocNetAddrxDO [get_bd_ports LocNetAddrxDO] [get_bd_pins scalp_router_regbank_0/LocNetAddrxDO]
connect_bd_net -net scalp_router_regbank_0_ScalpPacketCtrlxDO [get_bd_ports ScalpPacketCtrlxDO] [get_bd_pins scalp_router_regbank_0/ScalpPacketCtrlxDO]
connect_bd_net -net scalp_router_regbank_0_ScalpPacketWriteDataxDO [get_bd_ports ScalpPacketWriteDataxDO] [get_bd_pins scalp_router_regbank_0/ScalpPacketWriteDataxDO]
connect_bd_net -net scalp_safe_firmware_0_RgbLedsCtrlPortxDO [get_bd_ports RgbLedsCtrlPortxDO] [get_bd_pins scalp_safe_firmware_0/RgbLedsCtrlPortxDO]
connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_clock_converter_2/m_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn]
connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout]
# Create address segments
assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_router_regbank_0/SAxiLitexDIO/Reg] -force
assign_bd_address -offset 0x43C10000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_safe_firmware_0/SAXILitexDIO/SAXILiteAddr] -force
assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
assign_bd_address -offset 0x00000000 -range 0x10000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
assign_bd_address -offset 0x40400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
# Restore current instance
......
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