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Commit 32fdc010 authored by joachim.schmidt's avatar joachim.schmidt
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Updated scalp_fifo_double_register.vhd

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ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
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......@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Small fifo built with two registers.
--
-- Last update: 2021-05-17
-- Last update: 2021-05-18
--
---------------------------------------------------------------------------------
library ieee;
......@@ -56,13 +56,11 @@ architecture behavioral of scalp_fifo_double_register is
signal Axism2s1xDN : t_axi4m2s := C_NO_AXI4_M2S;
signal Axism2s2xDP : t_axi4m2s := C_NO_AXI4_M2S;
signal Axism2s2xDN : t_axi4m2s := C_NO_AXI4_M2S;
-- signal Axism2s3xD : t_axi4m2s := C_NO_AXI4_M2S;
signal Axism2s3xDN : t_axi4m2s := C_NO_AXI4_M2S;
signal Axism2s3xDP : t_axi4m2s := C_NO_AXI4_M2S;
signal Axism2s3xD : t_axi4m2s := C_NO_AXI4_M2S;
-- Axis Ready
signal Axiss2m0xD : t_axi4s2m := C_NO_AXI4_S2M;
signal Axiss2m1xDP : t_axi4s2m := C_NO_AXI4_S2M;
signal Axiss2m1xDN : t_axi4s2m := C_NO_AXI4_S2M;
signal Axiss2m1xDP : t_axi4s2m := C_NO_AXI4_S2M;
signal MUX3SelectxD : std_ulogic := '0';
-- Attributes
attribute mark_debug : string;
......@@ -78,83 +76,116 @@ architecture behavioral of scalp_fifo_double_register is
attribute keep of Axism2s2xDP : signal is "true";
attribute mark_debug of Axism2s2xDN : signal is "true";
attribute keep of Axism2s2xDN : signal is "true";
-- attribute mark_debug of Axism2s3xD : signal is "true";
-- attribute keep of Axism2s3xD : signal is "true";
attribute mark_debug of Axism2s3xDN : signal is "true";
attribute keep of Axism2s3xDN : signal is "true";
attribute mark_debug of Axism2s3xDP : signal is "true";
attribute keep of Axism2s3xDP : signal is "true";
attribute mark_debug of Axiss2m0xD : signal is "true";
attribute keep of Axiss2m0xD : signal is "true";
attribute mark_debug of Axiss2m1xDP : signal is "true";
attribute keep of Axiss2m1xDP : signal is "true";
attribute mark_debug of Axism2s3xD : signal is "true";
attribute keep of Axism2s3xD : signal is "true";
attribute mark_debug of Axiss2m1xDN : signal is "true";
attribute keep of Axiss2m1xDN : signal is "true";
attribute mark_debug of Axiss2m1xDP : signal is "true";
attribute keep of Axiss2m1xDP : signal is "true";
attribute mark_debug of MUX3SelectxD : signal is "true";
attribute keep of MUX3SelectxD : signal is "true";
begin -- architecture behavioral
EntityIOxB : block is
begin -- block EntityIOxB
-- Axis m2s
Axism2s0FromxAS : Axism2s0xD <= Axism2sLinkxDI;
Axism2s3ToxAS : Axism2sLinkxDO <= Axism2s3xDP;
-- Axis s2m
Axiss2m0FromxAS : Axiss2m0xD <= Axiss2mLinkxDI;
Axiss2m1FromxAS : Axiss2m1xDN <= Axiss2m0xD;
Axiss2m1ToxAS : Axiss2mLinkxDO <= Axiss2m1xDP;
end block EntityIOxB;
AsyncStatementsxB : block is
begin -- block AsyncStatementsxB
Axism2s3FromxAS : Axism2s3xDN <= Axism2s1xDP when
(Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1') or
(Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '1') else
Axism2s2xDP;
end block AsyncStatementsxB;
-- M2S
Axism2sLinkInxAS : Axism2s0xD <= Axism2sLinkxDI;
Axism2sLinkOutxAS : Axism2sLinkxDO <= Axism2s3xD;
-- S2M
Axiss2mLinkInxAS : Axiss2m1xDN <= Axiss2mLinkxDI;
Axiss2mLinkOutxAS : Axiss2mLinkxDO <= Axiss2m1xDP;
MUX3SelectxAS : MUX3SelectxD <= not Axiss2mLinkxDI.ReadyxS;
UpdateRegxP : process (SysClkxCI, SysRstxRNAI) is
begin -- process UpdateRegxP
end block EntityIOxB;
RegistersxP : process (SysClkxCI, SysRstxRNAI) is
begin -- process RegistersxP
if SysRstxRNAI = '0' then
-- Axis m2s
-- M2S
Axism2s1xDP <= C_NO_AXI4_M2S;
Axism2s2xDP <= C_NO_AXI4_M2S;
Axism2s3xDP <= C_NO_AXI4_M2S;
-- Axis s2m
-- S2M
Axiss2m1xDP <= C_NO_AXI4_S2M;
-- Enable Port
-- ScalpFifoEnablexSP <= '0';
elsif rising_edge(SysClkxCI) then
-- Axis m2s
-- M2S
Axism2s1xDP <= Axism2s1xDN;
Axism2s2xDP <= Axism2s2xDN;
Axism2s3xDP <= Axism2s3xDN;
-- Axis s2m
-- S2M
Axiss2m1xDP <= Axiss2m1xDN;
-- Enable Port
-- ScalpFifoEnablexSP <= ScalpFifoEnablexSN;
end if;
end process UpdateRegxP;
TransistionOnReadyxP : process (Axism2s0xD, Axism2s1xDP, Axism2s2xDP,
Axiss2m0xD.ReadyxS, Axiss2m1xDP.ReadyxS) is
begin -- process TransistionOnReadyxP
-- Defaults values
Axism2s1xDN <= Axism2s1xDP;
Axism2s2xDN <= Axism2s2xDP;
if Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '0' then
Axism2s1xDN <= Axism2s1xDP;
Axism2s2xDN <= Axism2s2xDP;
elsif Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1' then
Axism2s1xDN <= Axism2s0xD;
Axism2s2xDN <= Axism2s2xDP;
elsif Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '0' then
Axism2s1xDN <= Axism2s1xDP;
Axism2s2xDN <= Axism2s0xD;
else
Axism2s1xDN <= Axism2s0xD;
Axism2s2xDN <= Axism2s0xD;
end if;
end process TransistionOnReadyxP;
end process RegistersxP;
MUXxB : block is
begin -- block MUXxB
MUX1xAS : Axism2s1xDN <= Axism2s0xD when Axiss2m1xDP.ReadyxS = '1' else Axism2s1xDP;
MUX2xAS : Axism2s2xDN <= Axism2s0xD when Axiss2m1xDN.ReadyxS = '1' else Axism2s2xDP;
MUX3xAS : Axism2s3xD <= Axism2s1xDP when MUX3SelectxD = '1'else Axism2s2xDP;
end block MUXxB;
-- EntityIOxB : block is
-- begin -- block EntityIOxB
-- -- Axis m2s
-- Axism2s0FromxAS : Axism2s0xD <= Axism2sLinkxDI;
-- Axism2s3ToxAS : Axism2sLinkxDO <= Axism2s3xD;
-- -- Axis s2m
-- Axiss2m0FromxAS : Axiss2m0xD <= Axiss2mLinkxDI;
-- Axiss2m1FromxAS : Axiss2m1xDN <= Axiss2m0xD;
-- Axiss2m1ToxAS : Axiss2mLinkxDO <= Axiss2m1xDP;
-- end block EntityIOxB;
-- AsyncStatementsxB : block is
-- begin -- block AsyncStatementsxB
-- Axism2s3FromxAS : Axism2s3xD <= Axism2s1xDP when
-- (Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1') or
-- (Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '1') else
-- Axism2s2xDP;
-- end block AsyncStatementsxB;
-- UpdateRegxP : process (SysClkxCI, SysRstxRNAI) is
-- begin -- process UpdateRegxP
-- if SysRstxRNAI = '0' then
-- -- Axis m2s
-- Axism2s1xDP <= C_NO_AXI4_M2S;
-- Axism2s2xDP <= C_NO_AXI4_M2S;
-- -- Axis s2m
-- Axiss2m1xDP <= C_NO_AXI4_S2M;
-- -- Enable Port
-- -- ScalpFifoEnablexSP <= '0';
-- elsif rising_edge(SysClkxCI) then
-- -- Axis m2s
-- Axism2s1xDP <= Axism2s1xDN;
-- Axism2s2xDP <= Axism2s2xDN;
-- -- Axis s2m
-- Axiss2m1xDP <= Axiss2m1xDN;
-- -- Enable Port
-- -- ScalpFifoEnablexSP <= ScalpFifoEnablexSN;
-- end if;
-- end process UpdateRegxP;
-- TransistionOnReadyxP : process (Axism2s0xD, Axism2s1xDP, Axism2s2xDP,
-- Axiss2m0xD.ReadyxS, Axiss2m1xDP.ReadyxS) is
-- begin -- process TransistionOnReadyxP
-- -- Defaults values
-- Axism2s1xDN <= Axism2s1xDP;
-- Axism2s2xDN <= Axism2s2xDP;
-- if Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '0' then
-- Axism2s1xDN <= Axism2s1xDP;
-- Axism2s2xDN <= Axism2s2xDP;
-- elsif Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1' then
-- Axism2s1xDN <= Axism2s0xD;
-- Axism2s2xDN <= Axism2s2xDP;
-- elsif Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '0' then
-- Axism2s1xDN <= Axism2s1xDP;
-- Axism2s2xDN <= Axism2s0xD;
-- else
-- Axism2s1xDN <= Axism2s0xD;
-- Axism2s2xDN <= Axism2s0xD;
-- end if;
-- end process TransistionOnReadyxP;
end architecture behavioral;
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