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Commit 6ffefb67 authored by joachim.schmidt's avatar joachim.schmidt
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Added IP scalp_router to the scalp_firmware project, but not yet integrated in the design.

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with 33 additions and 21 deletions
......@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Console color print utility
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Cleanup project directory
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware'
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......@@ -73,14 +73,14 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
# add IPs source file
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
......@@ -94,17 +94,24 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
read_ip ${ip_dir}/scalp_packet_fifo_wrapper/src/ip_core/scalp_packet_fifo/scalp_packet_fifo.xci
read_ip ${ip_dir}/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
read_ip ${ip_dir}/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Export the hardware design to SDK
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Generate bitstream file
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: TCL script used to generate bitstream file
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Generate software application
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: TCL script used to generate software application
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Load bitstream file
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script used to load FPGA bitstream
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Load software application
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script used to load software application
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: Project management utilities
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2020-11-25 14:35:23
# Last update: 2020-11-30 09:39:40
#
##################################################################################
......
......@@ -31,6 +31,11 @@
"scalp_zynqps" : "enable"
},
"ips" : {
"scalp_router" : {
"hdl" : "enable",
"xci" : {
}
},
"scalp_aurora_phy" : {
"hdl" : "enable",
"xci" : {
......
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