Commit 77f1ab17 authored by joachim.schmidt's avatar joachim.schmidt
Browse files

Added and modified new JSON configuration files.

parent 2db04ea5
......@@ -20,6 +20,18 @@
"aurora_drp_pkg" : "enable",
"aurora_status_pkg" : "enable",
"axi4_pkg" : "enable"
}
},
"ips" : {
"scalp_aurora_phy" :
{
"hdl" : "enable",
"xci" : {
"east_channel" : "enable",
"north_channel" : "enable",
"south_channel" : "enable",
"west_channel" : "enable"
}
}
}
}
}
{
"author" : {
"name" : "Joachim Schmidt",
"email" : "<joachim.schmidt@hesge.ch"
},
"project" : {
"name" : "scalp_design_aurora_clk",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
"vivado_version" : "2019.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
"board_name" : "SCALP"
},
"components" : {
"ips" : {
"scalp_design_aurora_clk" :
{
"hdl" : "enable",
"xci" : {
"scalp_aurora_clk" : "enable"
}
}
}
}
}
{
"author" : {
"name" : "Joachim Schmidt",
"email" : "<joachim.schmidt@hesge.ch"
},
"project" : {
"name" : "scalp_design_debug",
"type" : "COMP_PRJ_TYPE",
"category" : "IPS",
"vivado_version" : "2019.2",
"target_language" : "VHDL",
"vhdl_version" : "VHDL 2008"
},
"hardware" : {
"part_name" : "xc7z015clg485-2",
"board_name" : "SCALP"
},
"components" : {
"ips" : {
"scalp_design_debug" :
{
"hdl" : "enable",
"xci" : {
"data_counter" : "enable",
"vio_axi_cnt_ctrl" : "enable",
"vio_status" : "enable"
}
}
}
}
}
......@@ -29,6 +29,31 @@
},
"soc" : {
"scalp_zynqps" : "enable"
},
"ips" : {
"scalp_aurora_phy" : {
"hdl" : "enable",
"xci" : {
"east_channel" : "enable",
"north_channel" : "enable",
"south_channel" : "enable",
"west_channel" : "enable"
}
},
"scalp_design_aurora_clk" : {
"hdl" : "disable",
"xci" : {
"scalp_aurora_clk" : "enable"
}
},
"scalp_design_debug" : {
"hdl" : "disable",
"xci" : {
"data_counter" : "enable",
"vio_axi_cnt_ctrl" : "enable",
"vio_status" : "enable"
}
}
}
}
}
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