Add ILA on GPIO output. Tested and working.

soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl

@@ -198,6 +198,10 @@ proc create_root_design { parentCell } {
 
   set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
 
+  set GPIO_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_0 ]
+
+  set I2C1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 I2C1 ]
+
 
   # Create ports
   set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
@@ -295,7 +299,9 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_EN_EMIO_CAN1 {0} \
    CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
    CONFIG.PCW_EN_EMIO_ENET0 {0} \
+   CONFIG.PCW_EN_EMIO_GPIO {1} \
    CONFIG.PCW_EN_EMIO_I2C0 {0} \
+   CONFIG.PCW_EN_EMIO_I2C1 {1} \
    CONFIG.PCW_EN_EMIO_SDIO1 {0} \
    CONFIG.PCW_EN_EMIO_SPI0 {0} \
    CONFIG.PCW_EN_EMIO_SPI1 {1} \
@@ -304,6 +310,7 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_EN_ENET0 {1} \
    CONFIG.PCW_EN_GPIO {1} \
    CONFIG.PCW_EN_I2C0 {1} \
+   CONFIG.PCW_EN_I2C1 {1} \
    CONFIG.PCW_EN_QSPI {1} \
    CONFIG.PCW_EN_SDIO1 {1} \
    CONFIG.PCW_EN_SPI0 {1} \
@@ -324,12 +331,19 @@ proc create_root_design { parentCell } {
    CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
    CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
    CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_IO {32} \
+   CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {32} \
    CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
    CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
    CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
    CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} \
    CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_I2C0_RESET_ENABLE {0} \
+   CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \
+   CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \
+   CONFIG.PCW_I2C1_I2C1_IO {EMIO} \
+   CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
    CONFIG.PCW_I2C1_RESET_ENABLE {0} \
    CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {125.000000} \
    CONFIG.PCW_I2C_RESET_ENABLE {1} \
@@ -691,9 +705,10 @@ proc create_root_design { parentCell } {
   # Create instance: system_ila_0, and set properties
   set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
   set_property -dict [ list \
-   CONFIG.C_MON_TYPE {NATIVE} \
-   CONFIG.C_NUM_OF_PROBES {1} \
-   CONFIG.C_PROBE0_TYPE {0} \
+   CONFIG.C_MON_TYPE {INTERFACE} \
+   CONFIG.C_NUM_MONITOR_SLOTS {1} \
+   CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:gpio_rtl:1.0} \
+   CONFIG.C_SLOT_0_TYPE {0} \
  ] $system_ila_0
 
   # Create instance: util_vector_logic_0, and set properties
@@ -722,6 +737,10 @@ proc create_root_design { parentCell } {
   # Create interface connections
   connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
   connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
+  connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_0] [get_bd_intf_pins processing_system7_0/GPIO_0]
+connect_bd_intf_net -intf_net [get_bd_intf_nets processing_system7_0_GPIO_0] [get_bd_intf_ports GPIO_0] [get_bd_intf_pins system_ila_0/SLOT_0_GPIO]
+  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets processing_system7_0_GPIO_0]
+  connect_bd_intf_net -intf_net processing_system7_0_IIC_1 [get_bd_intf_ports I2C1] [get_bd_intf_pins processing_system7_0/IIC_1]
   connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_axi4lite_0/SAXILitexDIO]
   connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins scalp_safe_firmware_0/SAXILitexDIO]
@@ -742,8 +761,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net scalp_axi4lite_0_RdAddrxDO [get_bd_ports RdAddrxDO] [get_bd_pins scalp_axi4lite_0/RdAddrxDO]
   connect_bd_net -net scalp_axi4lite_0_RdValidxSO [get_bd_ports RdValidxSO] [get_bd_pins scalp_axi4lite_0/RdValidxSO]
   connect_bd_net -net scalp_axi4lite_0_WrAddrxDO [get_bd_ports WrAddrxDO] [get_bd_pins scalp_axi4lite_0/WrAddrxDO]
-  connect_bd_net -net scalp_axi4lite_0_WrDataxDO [get_bd_ports WrDataxDO] [get_bd_pins scalp_axi4lite_0/WrDataxDO] [get_bd_pins system_ila_0/probe0]
-  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_axi4lite_0_WrDataxDO]
+  connect_bd_net -net scalp_axi4lite_0_WrDataxDO [get_bd_ports WrDataxDO] [get_bd_pins scalp_axi4lite_0/WrDataxDO]
   connect_bd_net -net scalp_axi4lite_0_WrValidxSO [get_bd_ports WrValidxSO] [get_bd_pins scalp_axi4lite_0/WrValidxSO]
   connect_bd_net -net scalp_safe_firmware_0_RgbLedsCtrlPortxDO [get_bd_ports RgbLedsCtrlPortxDO] [get_bd_pins scalp_safe_firmware_0/RgbLedsCtrlPortxDO]
   connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res]