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Commit 7d034984 authored by orphee.antoniad's avatar orphee.antoniad
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Update mipi project. 

- Add GPIO on EMIO
- Connect I2C1 to MIPI I2C pins
parent 694e9552
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designs/vivado/scalp_mipi/2020.2/lin64/.scripts/.Xil/Vivado-5340-scalpws/hw_ila_data_1/zip_work/hw_ila_data_1.wcfg 0 → 100755
+ 31
− 0
View file @ 7d034984
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/scalpuser/Desktop/scalp/scalp_firmware/designs/vivado/scalp_mipi/2020.2/lin64/scalp_mipi/scalp_mipi.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
<top_modules>
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="1fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="276"></NameColumnWidth>
<ValueColumnWidth column_width="120"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="1" />
<wvobject type="array" fp_name="ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/system_ila_0/U0/probe0_1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/system_ila_0/U0/probe0_1[31:0]</obj_property>
<obj_property name="ObjectShortName">probe0_1[31:0]</obj_property>
<obj_property name="label">scalp_axi4lite_0_WrDataxDO</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
</wave_config>
designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc
+ 66
− 24
View file @ 7d034984
......@@ -143,23 +143,58 @@ set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
#set_property PACKAGE_PIN "K5" [get_ports "LVDS2V5Top1NxSIO"]
#set_property PACKAGE_PIN "J2" [get_ports "LVDS2V5Top0PxSIO"]
#set_property PACKAGE_PIN "J1" [get_ports "LVDS2V5Top0NxSIO"]
# Bottom (bank 34)
##### GPIO0 (Bank 34) #####
# GPIO0_1
#set_property PACKAGE_PIN "N6" [get_ports "LVDS2V5Bottom7PxSIO"]
#set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom7PxSIO]
# GPIO0_0
#set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
#set_property PACKAGE_PIN "P6" [get_ports "LVDS2V5Bottom6PxSIO"]
#set_property PACKAGE_PIN "P5" [get_ports "LVDS2V5Bottom6NxSIO"]
#set_property PACKAGE_PIN "R5" [get_ports "LVDS2V5Bottom5PxSIO"]
#set_property PACKAGE_PIN "R4" [get_ports "LVDS2V5Bottom5NxSIO"]
#set_property PACKAGE_PIN "R3" [get_ports "LVDS2V5Bottom4PxSIO"]
#set_property PACKAGE_PIN "R2" [get_ports "LVDS2V5Bottom4NxSIO"]
#set_property PACKAGE_PIN "P3" [get_ports "LVDS2V5Bottom3PxSIO"]
#set_property PACKAGE_PIN "P2" [get_ports "LVDS2V5Bottom3NxSIO"]
#set_property PACKAGE_PIN "N1" [get_ports "LVDS2V5Bottom2PxSIO"]
#set_property PACKAGE_PIN "P1" [get_ports "LVDS2V5Bottom2NxSIO"]
#set_property PACKAGE_PIN "N4" [get_ports "LVDS2V5Bottom1PxSIO"]
#set_property PACKAGE_PIN "N3" [get_ports "LVDS2V5Bottom1NxSIO"]
#set_property PACKAGE_PIN "M2" [get_ports "LVDS2V5Bottom0PxSIO"]
#set_property PACKAGE_PIN "M1" [get_ports "LVDS2V5Bottom0NxSIO"]
#set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom7NxSIO]
##### Camera MIPI connector (Bank 34) #####
# Camera GPIO_BTA
set_property PACKAGE_PIN P6 [get_ports LVDS2V5Bottom6PxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom6PxSIO]
# Camera PWUP
set_property PACKAGE_PIN P5 [get_ports LVDS2V5Bottom6NxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom6NxSIO]
# Camera SDA
set_property PACKAGE_PIN R5 [get_ports LVDS2V5Bottom5PxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom5PxSIO]
# Camera SCL
set_property PACKAGE_PIN R4 [get_ports LVDS2V5Bottom5NxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom5NxSIO]
# Camera LP_CLK_P
set_property PACKAGE_PIN R3 [get_ports LVDS2V5Bottom4PxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom4PxSIO]
# Camera LP_CLK_N
set_property PACKAGE_PIN R2 [get_ports LVDS2V5Bottom4NxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom4NxSIO]
# Camera LP_LANE1_P
set_property PACKAGE_PIN P3 [get_ports LVDS2V5Bottom3PxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom3PxSIO]
# Camera LP_LANE1_N
set_property PACKAGE_PIN P2 [get_ports LVDS2V5Bottom3NxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom3NxSIO]
# Camera HS_LANE1_P
set_property PACKAGE_PIN N1 [get_ports LVDS2V5Bottom2PxSIO]
set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom2PxSIO]
# Camera HS_LANE1_N
set_property PACKAGE_PIN P1 [get_ports LVDS2V5Bottom2NxSIO]
set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom2NxSIO]
# Camera LP_LANE0_P
set_property PACKAGE_PIN N4 [get_ports LVDS2V5Bottom1PxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom1PxSIO]
# Camera LP_LANE0_N
set_property PACKAGE_PIN N3 [get_ports LVDS2V5Bottom1NxSIO]
set_property IOSTANDARD LVCMOS25 [get_ports LVDS2V5Bottom1NxSIO]
# Camera HS_LANE0_P
set_property PACKAGE_PIN M2 [get_ports LVDS2V5Bottom0PxSIO]
set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom0PxSIO]
# Camera HS_LANE0_N
set_property PACKAGE_PIN M1 [get_ports LVDS2V5Bottom0NxSIO]
set_property IOSTANDARD LVDS_25 [get_ports LVDS2V5Bottom0NxSIO]
##### RGB LEDs (banks 34 and 13) #####
# LED1_2V5_R_o (bank 34)
......@@ -209,8 +244,15 @@ set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
# Bank 34
#set_property PACKAGE_PIN "K4" [get_ports "Clk2V5TopPxCI"]
#set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
#set_property PACKAGE_PIN "U2" [get_ports "Clk2V5BottomPxCI"]
#set_property PACKAGE_PIN "U1" [get_ports "Clk2V5BottomNxCI"]
##### Camera MIPI connector (Bank 34) #####
# Camera HS_CLK_P
set_property PACKAGE_PIN U2 [get_ports Clk2V5BottomPxCI]
set_property IOSTANDARD LVDS_25 [get_ports Clk2V5BottomPxCI]
# Camera HS_CLK_N
set_property PACKAGE_PIN U1 [get_ports Clk2V5BottomNxCI]
set_property IOSTANDARD LVDS_25 [get_ports Clk2V5BottomNxCI]
# Bank 13
#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
#set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
......@@ -226,8 +268,15 @@ set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
# Bank 34
#set_property PACKAGE_PIN "P7" [get_ports "Clk2V5TopPxCO"]
#set_property PACKAGE_PIN "R7" [get_ports "Clk2V5TopNxCO"]
##### GPIO0 (Bank 34) #####
# GPIO0_3
#set_property PACKAGE_PIN "M4" [get_ports "Clk2V5BottomPxCO"]
#set_property IOSTANDARD LVCMOS25 [get_ports Clk2V5BottomPxCO]
# GPIO0_2
#set_property PACKAGE_PIN "M3" [get_ports "Clk2V5BottomNxCO"]
#set_property IOSTANDARD LVCMOS25 [get_ports Clk2V5BottomNxCO]
# Bank 13
#set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
#set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
......@@ -244,10 +293,3 @@ set_operating_conditions -grade extended -process maximum
# 4'' by 4'' PCB, no heatsink, no air flow
set_operating_conditions -airflow 0 -heatsink none -board small
designs/vivado/scalp_mipi/2020.2/src/hdl/scalp_mipi.vhd
+ 109
− 20
View file @ 7d034984
......@@ -190,20 +190,20 @@ entity scalp_mipi is
-- LVDS2V5Top7PxSIO : inout std_logic;
-- LVDS2V5Top7NxSIO : inout std_logic;
-- Bottom
-- LVDS2V5Bottom0PxSIO : inout std_logic;
-- LVDS2V5Bottom0NxSIO : inout std_logic;
-- LVDS2V5Bottom1PxSIO : inout std_logic;
-- LVDS2V5Bottom1NxSIO : inout std_logic;
-- LVDS2V5Bottom2PxSIO : inout std_logic;
-- LVDS2V5Bottom2NxSIO : inout std_logic;
-- LVDS2V5Bottom3PxSIO : inout std_logic;
-- LVDS2V5Bottom3NxSIO : inout std_logic;
-- LVDS2V5Bottom4PxSIO : inout std_logic;
-- LVDS2V5Bottom4NxSIO : inout std_logic;
-- LVDS2V5Bottom5PxSIO : inout std_logic;
-- LVDS2V5Bottom5NxSIO : inout std_logic;
-- LVDS2V5Bottom6PxSIO : inout std_logic;
-- LVDS2V5Bottom6NxSIO : inout std_logic;
-- LVDS2V5Bottom0PxSIO : in std_logic; -- Camera HS_LANE0_P
-- LVDS2V5Bottom0NxSIO : in std_logic; -- Camera HS_LANE0_N
-- LVDS2V5Bottom1PxSIO : in std_logic; -- Camera LP_LANE0_P
-- LVDS2V5Bottom1NxSIO : in std_logic; -- Camera LP_LANE0_N
-- LVDS2V5Bottom2PxSIO : in std_logic; -- Camera HS_LANE1_P
-- LVDS2V5Bottom2NxSIO : in std_logic; -- Camera HS_LANE1_N
-- LVDS2V5Bottom3PxSIO : in std_logic; -- Camera LP_LANE1_P
-- LVDS2V5Bottom3NxSIO : in std_logic; -- Camera LP_LANE1_N
-- LVDS2V5Bottom4PxSIO : in std_logic; -- Camera LP_CLK_P
-- LVDS2V5Bottom4NxSIO : in std_logic; -- Camera LP_CLK_N
LVDS2V5Bottom5PxSIO : inout std_logic; -- Camera I2C SDA
LVDS2V5Bottom5NxSIO : inout std_logic; -- Camera I2C SCL
LVDS2V5Bottom6PxSIO : inout std_logic; -- Camera GPIO_BTA
LVDS2V5Bottom6NxSIO : inout std_logic; -- Camera PWUP
-- LVDS2V5Bottom7PxSIO : inout std_logic;
-- LVDS2V5Bottom7NxSIO : inout std_logic;
-- RGB LEDs
......@@ -256,8 +256,8 @@ entity scalp_mipi is
-- Clk2V5TopPxCO : out std_logic;
-- Clk2V5TopNxCO : out std_logic;
-- -- Bottom
-- Clk2V5BottomPxCI : in std_logic;
-- Clk2V5BottomNxCI : in std_logic;
-- Clk2V5BottomPxCI : in std_logic; -- Camera HS_CLK_P
-- Clk2V5BottomNxCI : in std_logic -- Camera HS_CLK_N
-- Clk2V5BottomPxCO : out std_logic;
-- Clk2V5BottomNxCO : out std_logic;
-- -- Recovery
......@@ -292,13 +292,55 @@ architecture arch of scalp_mipi is
signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- RGB Leds
signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- I2C1 signals
signal I2c1SdaIxS : std_logic := '0';
signal I2c1SdaOxS : std_logic := '0';
signal I2c1SdaTxS : std_logic := '0';
signal I2c1SclIxS : std_logic := '0';
signal I2c1SclOxS : std_logic := '0';
signal I2c1SclTxS : std_logic := '0';
-- GPIO0 signals
signal GPIO0IxD : std_logic_vector(31 downto 0) := (others => '0');
signal GPIO0OxD : std_logic_vector(31 downto 0) := (others => '0');
signal GPIO0TxD : std_logic_vector(31 downto 0) := (others => '0');
-- Camera MIPI signals
-- signal MipiPhyClockHsNxC : std_logic := '0';
-- signal MipiPhyClockHsPxC : std_logic := '0';
-- signal MipiPhyClockLpNxC : std_logic := '0';
-- signal MipiPhyClockLpPxC : std_logic := '0';
-- signal MipiPhyDataHsNxD : std_logic_vector(1 downto 0) := (others => '0');
-- signal MipiPhyDataHsPxD : std_logic_vector(1 downto 0) := (others => '0');
-- signal MipiPhyDataLpNxD : std_logic_vector(1 downto 0) := (others => '0');
-- signal MipiPhyDataLpPxD : std_logic_vector(1 downto 0) := (others => '0');
-- Attributes
attribute mark_debug : string;
attribute keep : string;
-- attribute mark_debug : string;
-- attribute keep : string;
-- Clocks
attribute keep of PSSysClkxC : signal is "true";
-- attribute keep of PSSysClkxC : signal is "true";
-- GPIO debug probes
--attribute mark_debug of GPIO0IxD : signal is "true";
--attribute keep of GPIO0IxD : signal is "true";
--attribute mark_debug of GPIO0OxD : signal is "true";
-- attribute keep of GPIO0OxD : signal is "true";
-- attribute mark_debug of GPIO0TxD : signal is "true";
-- attribute keep of GPIO0TxD : signal is "true";
-- I2C1 debug probes
-- attribute mark_debug of I2c1SdaIxS : signal is "true";
-- attribute keep of I2c1SdaIxS : signal is "true";
-- attribute mark_debug of I2c1SdaOxS : signal is "true";
-- attribute keep of I2c1SdaOxS : signal is "true";
-- attribute mark_debug of I2c1SdaTxS : signal is "true";
-- attribute keep of I2c1SdaTxS : signal is "true";
-- attribute mark_debug of I2c1SclIxS : signal is "true";
-- attribute keep of I2c1SclIxS : signal is "true";
-- attribute mark_debug of I2c1SclOxS : signal is "true";
-- attribute keep of I2c1SclOxS : signal is "true";
-- attribute mark_debug of I2c1SclTxS : signal is "true";
-- attribute keep of I2c1SclTxS : signal is "true";
begin
......@@ -348,7 +390,28 @@ begin
WrAddrxDO => WrAddrxD,
WrDataxDO => WrDataxD,
WrValidxSO => WrValidxS,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD);
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD,
-- Zynq I2C1 interface
I2c1SdaxSI => I2c1SdaIxS,
I2c1SdaxSO => I2c1SdaOxS,
I2c1SdaxST => I2c1SdaTxS,
I2c1SclxSI => I2c1SclIxS,
I2c1SclxSO => I2c1SclOxS,
I2c1SclxST => I2c1SclTxS,
-- Zynq GPIO0 interface
GPIO0xDI => GPIO0IxD,
GPIO0xDO => GPIO0OxD,
GPIO0xDT => GPIO0TxD
-- MIPI interface
-- MipiPhyClockHsN => MipiPhyClockHsNxC,
-- MipiPhyClockHsP => MipiPhyClockHsPxC,
-- MipiPhyClockLpN => MipiPhyClockLpNxC,
-- MipiPhyClockLpP => MipiPhyClockLpPxC,
-- MipiPhyDataHsN => MipiPhyDataHsNxD,
-- MipiPhyDataHsP => MipiPhyDataHsPxD,
-- MipiPhyDataLpN => MipiPhyDataLpNxD,
-- MipiPhyDataLpP => MipiPhyDataLpPxD
);
end block ProcessingSystemxB;
......@@ -365,6 +428,32 @@ begin
Led22V5GxAS : Led22V5GxSO <= RgbLedsCtrlPortxD(4);
Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
-- Camera I2C SDA tri-state buffer
LVDS2V5Bottom5PxSIO <= I2c1SdaOxS when I2c1SdaTxS='1' else 'Z';
I2c1SdaIxS <= LVDS2V5Bottom5PxSIO;
-- Camera I2C SCL tri-state buffer
LVDS2V5Bottom5NxSIO <= I2c1SclOxS when I2c1SclTxS='1' else 'Z';
I2c1SclIxS <= LVDS2V5Bottom5NxSIO;
-- Camera PWUP tri-state buffer (GPIO0_4)
LVDS2V5Bottom6NxSIO <= GPIO0OxD(4) when GPIO0TxD(4)='1' else 'Z';
GPIO0IxD(4) <= LVDS2V5Bottom6NxSIO;
-- Camera GPIO tri-state buffer (GPIO0_5)
LVDS2V5Bottom6PxSIO <= GPIO0OxD(5) when GPIO0TxD(5)='1' else 'Z';
GPIO0IxD(5) <= LVDS2V5Bottom6PxSIO;
-- MIPI signal assignement
-- MipiPhyClockHsNxAS : MipiPhyClockHsNxC <= Clk2V5BottomNxCI;
-- MipiPhyClockHsPxAS : MipiPhyClockHsPxC <= Clk2V5BottomPxCI;
-- MipiPhyClockLpNxAS : MipiPhyClockLpNxC <= LVDS2V5Bottom4NxSIO;
-- MipiPhyClockLpPxAS : MipiPhyClockLpPxC <= LVDS2V5Bottom4PxSIO;
-- MipiPhyDataHsN0xAS : MipiPhyDataHsNxD(0) <= LVDS2V5Bottom0NxSIO;
-- MipiPhyDataHsP0xAS : MipiPhyDataHsPxD(0) <= LVDS2V5Bottom0PxSIO;
-- MipiPhyDataLpN0xAS : MipiPhyDataLpNxD(0) <= LVDS2V5Bottom1NxSIO;
-- MipiPhyDataLpP0xAS : MipiPhyDataLpPxD(0) <= LVDS2V5Bottom1PxSIO;
-- MipiPhyDataHsN1xAS : MipiPhyDataHsNxD(1) <= LVDS2V5Bottom2NxSIO;
-- MipiPhyDataHsP1xAS : MipiPhyDataHsPxD(1) <= LVDS2V5Bottom2PxSIO;
-- MipiPhyDataLpN1xAS : MipiPhyDataLpNxD(1) <= LVDS2V5Bottom3NxSIO;
-- MipiPhyDataLpP1xAS : MipiPhyDataLpPxD(1) <= LVDS2V5Bottom3PxSIO;
end block EntityIOxB;
......
soc/hw/scalp_mipi_zynqps/src/hdl/scalp_mipi_zynqps_wrapper.vhd
+ 41
− 2
View file @ 7d034984
......@@ -67,7 +67,28 @@ entity scalp_mipi_zynqps_wrapper is
WrAddrxDO : out std_logic_vector (11 downto 0);
WrDataxDO : out std_logic_vector (31 downto 0);
WrValidxSO : out std_logic;
RgbLedsCtrlPortxDO : out std_logic_vector (31 downto 0));
RgbLedsCtrlPortxDO : out std_logic_vector (31 downto 0);
-- I2C1 interface
I2c1SdaxSI : in std_logic;
I2c1SdaxSO : out std_logic;
I2c1SdaxST : out std_logic;
I2c1SclxSI : in std_logic;
I2c1SclxSO : out std_logic;
I2c1SclxST : out std_logic;
-- GPIO0 interface
GPIO0xDI : in std_logic_vector (31 downto 0);
GPIO0xDO : out std_logic_vector (31 downto 0);
GPIO0xDT : out std_logic_vector (31 downto 0)
-- MIPI interface
-- MipiPhyClockHsN : in std_logic;
-- MipiPhyClockHsP : in std_logic;
-- MipiPhyClockLpN : in std_logic;
-- MipiPhyClockLpP : in std_logic;
-- MipiPhyDataHsN : in std_logic_vector (1 downto 0);
-- MipiPhyDataHsP : in std_logic_vector (1 downto 0);
-- MipiPhyDataLpN : in std_logic_vector (1 downto 0);
-- MipiPhyDataLpP : in std_logic_vector (1 downto 0)
);
end scalp_mipi_zynqps_wrapper;
......@@ -111,6 +132,24 @@ begin
WrAddrxDO => WrAddrxDO,
WrDataxDO => WrDataxDO,
WrValidxSO => WrValidxSO,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO);
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO,
I2C1_SDA_I => I2c1SdaxSI,
I2C1_SDA_O => I2c1SdaxSO,
I2C1_SDA_T => I2c1SdaxST,
I2C1_SCL_I => I2c1SclxSI,
I2C1_SCL_O => I2c1SclxSO,
I2C1_SCL_T => I2c1SclxST,
GPIO_0_TRI_I => GPIO0xDI,
GPIO_0_TRI_O => GPIO0xDO,
GPIO_0_TRI_T => GPIO0xDT
-- MipiPhyClockHsN => MipiPhyClockHsN,
-- MipiPhyClockHsP => MipiPhyClockHsP,
-- MipiPhyClockLpN => MipiPhyClockLpN,
-- MipiPhyClockLpP => MipiPhyClockLpP,
-- MipiPhyDataHsN => MipiPhyDataHsN,
-- MipiPhyDataHsP => MipiPhyDataHsP,
-- MipiPhyDataLpN => MipiPhyDataLpN,
-- MipiPhyDataLpP => MipiPhyDataLpP
);
end arch;
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