Commit 83e5e8d6 authored by joachim.schmidt's avatar joachim.schmidt
Browse files

Creation of the HDL file scalp_zynqps_wrapper.vhd.

parent 8a80e65e
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--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: scalp_zynqps_wrapper - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: scalp_zynqps_wrapper
--
-- Last update: 2020-09-07
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity scalp_zynqps_wrapper is
port (
-- Processor interface
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
FclkClk0xCO : out std_logic;
FclkReset0xRO : out std_logic;
-- DDR interface
DDR_addr : inout std_logic_vector (14 downto 0);
DDR_ba : inout std_logic_vector (2 downto 0);
DDR_cas_n : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cke : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_dm : inout std_logic_vector (3 downto 0);
DDR_dq : inout std_logic_vector (31 downto 0);
DDR_dqs_n : inout std_logic_vector (3 downto 0);
DDR_dqs_p : inout std_logic_vector (3 downto 0);
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_we_n : inout std_logic;
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
-- USB interface
Usb0VBusPwrFaultxSI : in std_logic;
-- SPI1 used as uWire master. Clk, Data and LE signals are outputs
-- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
Spi1MOSIxSO : out std_logic;
Spi1SSxSO : out std_logic;
Spi1SclkxCO : out std_logic;
-- MIO
FIXED_IO_mio : inout std_logic_vector (53 downto 0));
end scalp_zynqps_wrapper;
architecture arch of scalp_zynqps_wrapper is
begin
ScalpZynqPSxI : entity work.scalp_zynqps
port map (
DDR_addr => DDR_addr,
DDR_ba => DDR_ba,
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm => DDR_dm,
DDR_dq => DDR_dq,
DDR_dqs_n => DDR_dqs_n,
DDR_dqs_p => DDR_dqs_p,
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio => FIXED_IO_mio,
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
FclkClk0xCO => FclkClk0xCO,
FclkReset0xRO(0) => FclkReset0xRO,
Spi1MOSIxSO => Spi1MOSIxSO,
Spi1SSxSO => Spi1SSxSO,
Spi1SclkxCO => Spi1SclkxCO,
Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI);
end arch;
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