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Commit 96446a0a authored by orphee.antoniad's avatar orphee.antoniad
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Update on scalp MIPI block design. Still not getting data from camera.

parent 02ace657
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designs/vivado/scalp_mipi/2020.2/src/constrs/scalp_mipi.xdc
View file @ 96446a0a
......@@ -192,7 +192,7 @@ set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
##### Camera MIPI connector (Bank 34) #####
set_property INTERNAL_VREF 0.6 [get_iobanks 34]
#set_property INTERNAL_VREF 0.6 [get_iobanks 34]
# Camera GPIO_BTA -> LVDS2V5Bottom6PxSIO
set_property PACKAGE_PIN P6 [get_ports CamGpioBta]
set_property IOSTANDARD LVCMOS25 [get_ports CamGpioBta]
......@@ -209,34 +209,38 @@ set_property IOSTANDARD LVCMOS25 [get_ports CamI2cScl]
set_property PULLTYPE PULLUP [get_ports CamI2cScl]
# Camera LP_CLK_P -> LVDS2V5Bottom4PxSIO
set_property PACKAGE_PIN R3 [get_ports CamLpClkP]
set_property IOSTANDARD HSUL_12 [get_ports CamLpClkP]
set_property IOSTANDARD LVCMOS25 [get_ports CamLpClkP]
# Camera LP_CLK_N -> LVDS2V5Bottom4NxSIO
set_property PACKAGE_PIN R2 [get_ports CamLpClkN]
set_property IOSTANDARD HSUL_12 [get_ports CamLpClkN]
set_property IOSTANDARD LVCMOS25 [get_ports CamLpClkN]
# Camera LP_LANE1_P -> LVDS2V5Bottom3PxSIO
set_property PACKAGE_PIN P3 [get_ports {CamLpDataP[1]}]
set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataP[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {CamLpDataP[1]}]
# Camera LP_LANE1_N -> LVDS2V5Bottom3NxSIO
set_property PACKAGE_PIN P2 [get_ports {CamLpDataN[1]}]
set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataN[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {CamLpDataN[1]}]
# Camera HS_LANE1_P -> LVDS2V5Bottom2PxSIO
set_property PACKAGE_PIN N1 [get_ports {CamHsDataP[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataP[1]}]
set_property DIFF_TERM true [get_ports {CamHsDataP[1]}]
# Camera HS_LANE1_N -> LVDS2V5Bottom2NxSIO
set_property PACKAGE_PIN P1 [get_ports {CamHsDataN[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataN[1]}]
set_property DIFF_TERM true [get_ports {CamHsDataN[1]}]
# Camera LP_LANE0_P -> LVDS2V5Bottom1PxSIO
set_property PACKAGE_PIN N4 [get_ports {CamLpDataP[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataP[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {CamLpDataP[0]}]
# Camera LP_LANE0_N -> LVDS2V5Bottom1NxSIO
set_property PACKAGE_PIN N3 [get_ports {CamLpDataN[0]}]
set_property IOSTANDARD HSUL_12 [get_ports {CamLpDataN[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {CamLpDataN[0]}]
# Camera HS_LANE0_P -> LVDS2V5Bottom0PxSIO
set_property PACKAGE_PIN M2 [get_ports {CamHsDataP[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataP[0]}]
set_property DIFF_TERM true [get_ports {CamHsDataP[0]}]
# Camera HS_LANE0_N -> LVDS2V5Bottom0NxSIO
set_property PACKAGE_PIN M1 [get_ports {CamHsDataN[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {CamHsDataN[0]}]
set_property DIFF_TERM true [get_ports {CamHsDataN[0]}]
##### RGB LEDs (banks 34 and 13) #####
# LED1_2V5_R_o (bank 34)
......@@ -291,9 +295,11 @@ set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
# Camera HS_CLK_P -> Clk2V5BottomPxCI
set_property PACKAGE_PIN U2 [get_ports CamHsClkP]
set_property IOSTANDARD LVDS_25 [get_ports CamHsClkP]
set_property DIFF_TERM true [get_ports CamHsClkP]
# Camera HS_CLK_N -> Clk2V5BottomNxCI
set_property PACKAGE_PIN U1 [get_ports CamHsClkN]
set_property IOSTANDARD LVDS_25 [get_ports CamHsClkN]
set_property DIFF_TERM true [get_ports CamHsClkN]
# Bank 13
#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
......
soc/vivado/scalp_mipi_zynqps/2020.2/src/ipi_tcl/scalp_mipi_zynqps_ipi.tcl
View file @ 96446a0a
......@@ -247,10 +247,10 @@ proc create_root_design { parentCell } {
CONFIG.M_TID_WIDTH {1} \
CONFIG.M_TUSER_WIDTH {1} \
CONFIG.S_HAS_TLAST {1} \
CONFIG.S_TDATA_NUM_BYTES {2} \
CONFIG.S_TDATA_NUM_BYTES {4} \
CONFIG.S_TDEST_WIDTH {10} \
CONFIG.S_TUSER_WIDTH {1} \
CONFIG.TDATA_REMAP {32'b00000000000000000000000000000000,tdata[15:0]} \
CONFIG.TDATA_REMAP {16'b0000000000000000,tdata[31:0]} \
CONFIG.TDEST_REMAP {tdest[0:0]} \
CONFIG.TKEEP_REMAP {6'b111111} \
CONFIG.TLAST_REMAP {tlast[0]} \
......@@ -315,10 +315,12 @@ proc create_root_design { parentCell } {
set mipi_csi2_rx_subsyst_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mipi_csi2_rx_subsystem:5.1 mipi_csi2_rx_subsyst_0 ]
set_property -dict [ list \
CONFIG.CMN_NUM_LANES {2} \
CONFIG.CMN_NUM_PIXELS {2} \
CONFIG.CMN_PXL_FORMAT {YUV422_8bit} \
CONFIG.CSI_BUF_DEPTH {4096} \
CONFIG.C_CAL_MODE {FIXED} \
CONFIG.C_DPHY_LANES {2} \
CONFIG.C_EN_TIMEOUT_REGS {false} \
CONFIG.C_HS_LINE_RATE {336} \
CONFIG.C_HS_SETTLE_NS {164} \
CONFIG.C_IDLY_TAP {2} \
......@@ -762,10 +764,10 @@ proc create_root_design { parentCell } {
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {2048 MBits} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
......@@ -810,12 +812,56 @@ proc create_root_design { parentCell } {
# Create instance: system_ila_0, and set properties
set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
set_property -dict [ list \
CONFIG.C_BRAM_CNT {51} \
CONFIG.C_DATA_DEPTH {4096} \
CONFIG.C_MON_TYPE {INTERFACE} \
CONFIG.C_NUM_MONITOR_SLOTS {1} \
CONFIG.C_NUM_MONITOR_SLOTS {2} \
CONFIG.C_SLOT_0_APC_EN {0} \
CONFIG.C_SLOT_0_AXI_DATA_SEL {1} \
CONFIG.C_SLOT_0_AXI_TRIG_SEL {1} \
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_1_APC_EN {0} \
CONFIG.C_SLOT_1_AXI_AR_SEL_DATA {1} \
CONFIG.C_SLOT_1_AXI_AR_SEL_TRIG {1} \
CONFIG.C_SLOT_1_AXI_AW_SEL_DATA {1} \
CONFIG.C_SLOT_1_AXI_AW_SEL_TRIG {1} \
CONFIG.C_SLOT_1_AXI_B_SEL_DATA {1} \
CONFIG.C_SLOT_1_AXI_B_SEL_TRIG {1} \
CONFIG.C_SLOT_1_AXI_DATA_SEL {1} \
CONFIG.C_SLOT_1_AXI_R_SEL_DATA {1} \
CONFIG.C_SLOT_1_AXI_R_SEL_TRIG {1} \
CONFIG.C_SLOT_1_AXI_TRIG_SEL {1} \
CONFIG.C_SLOT_1_AXI_W_SEL_DATA {1} \
CONFIG.C_SLOT_1_AXI_W_SEL_TRIG {1} \
CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
CONFIG.C_SLOT_1_TYPE {0} \
CONFIG.C_SLOT_2_APC_EN {0} \
CONFIG.C_SLOT_2_AXI_AR_SEL_DATA {1} \
CONFIG.C_SLOT_2_AXI_AR_SEL_TRIG {1} \
CONFIG.C_SLOT_2_AXI_AW_SEL_DATA {1} \
CONFIG.C_SLOT_2_AXI_AW_SEL_TRIG {1} \
CONFIG.C_SLOT_2_AXI_B_SEL_DATA {1} \
CONFIG.C_SLOT_2_AXI_B_SEL_TRIG {1} \
CONFIG.C_SLOT_2_AXI_R_SEL_DATA {1} \
CONFIG.C_SLOT_2_AXI_R_SEL_TRIG {1} \
CONFIG.C_SLOT_2_AXI_W_SEL_DATA {1} \
CONFIG.C_SLOT_2_AXI_W_SEL_TRIG {1} \
CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
CONFIG.C_SLOT_2_TYPE {0} \
CONFIG.C_SLOT_3_APC_EN {0} \
CONFIG.C_SLOT_3_AXI_AR_SEL_DATA {1} \
CONFIG.C_SLOT_3_AXI_AR_SEL_TRIG {1} \
CONFIG.C_SLOT_3_AXI_AW_SEL_DATA {1} \
CONFIG.C_SLOT_3_AXI_AW_SEL_TRIG {1} \
CONFIG.C_SLOT_3_AXI_B_SEL_DATA {1} \
CONFIG.C_SLOT_3_AXI_B_SEL_TRIG {1} \
CONFIG.C_SLOT_3_AXI_DATA_SEL {1} \
CONFIG.C_SLOT_3_AXI_R_SEL_DATA {1} \
CONFIG.C_SLOT_3_AXI_R_SEL_TRIG {1} \
CONFIG.C_SLOT_3_AXI_TRIG_SEL {1} \
CONFIG.C_SLOT_3_AXI_W_SEL_DATA {1} \
CONFIG.C_SLOT_3_AXI_W_SEL_TRIG {1} \
CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
] $system_ila_0
# Create instance: util_vector_logic_0, and set properties
......@@ -845,6 +891,7 @@ proc create_root_design { parentCell } {
CONFIG.HAS_YUYV8 {1} \
CONFIG.HAS_Y_UV8 {1} \
CONFIG.MAX_COLS {3840} \
CONFIG.MAX_DATA_WIDTH {8} \
CONFIG.MAX_NR_PLANES {2} \
CONFIG.MAX_ROWS {2160} \
CONFIG.SAMPLES_PER_CLOCK {2} \
......@@ -873,6 +920,8 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets mipi_csi2_rx_subsyst_0_video_out
connect_bd_intf_net -intf_net ps7_0_axi_periph_M02_AXI [get_bd_intf_pins mipi_csi2_rx_subsyst_0/csirxss_s_axi] [get_bd_intf_pins ps7_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M03_AXI [get_bd_intf_pins ps7_0_axi_periph/M03_AXI] [get_bd_intf_pins v_frmbuf_wr_0/s_axi_CTRL]
connect_bd_intf_net -intf_net v_frmbuf_wr_0_m_axi_mm_video [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins v_frmbuf_wr_0/m_axi_mm_video]
connect_bd_intf_net -intf_net [get_bd_intf_nets v_frmbuf_wr_0_m_axi_mm_video] [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins system_ila_0/SLOT_1_AXI]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets v_frmbuf_wr_0_m_axi_mm_video]
# Create port connections
connect_bd_net -net InterruptxSI_0_1 [get_bd_ports InterruptxSI] [get_bd_pins scalp_axi4lite_0/InterruptxSI]
......
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